Commit | Line | Data |
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af19b491 | 1 | /* |
40839129 | 2 | * QLogic qlcnic NIC Driver |
577ae39d | 3 | * Copyright (c) 2009-2013 QLogic Corporation |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #ifndef _QLCNIC_H_ | |
9 | #define _QLCNIC_H_ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ip.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/tcp.h> | |
21 | #include <linux/skbuff.h> | |
22 | #include <linux/firmware.h> | |
23 | ||
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mii.h> | |
26 | #include <linux/timer.h> | |
27 | ||
28 | #include <linux/vmalloc.h> | |
29 | ||
30 | #include <linux/io.h> | |
31 | #include <asm/byteorder.h> | |
b9796a14 AC |
32 | #include <linux/bitops.h> |
33 | #include <linux/if_vlan.h> | |
af19b491 AKS |
34 | |
35 | #include "qlcnic_hdr.h" | |
7f966452 SC |
36 | #include "qlcnic_hw.h" |
37 | #include "qlcnic_83xx_hw.h" | |
af19b491 AKS |
38 | |
39 | #define _QLCNIC_LINUX_MAJOR 5 | |
7a8feb42 | 40 | #define _QLCNIC_LINUX_MINOR 1 |
0fe1e04e SS |
41 | #define _QLCNIC_LINUX_SUBVERSION 38 |
42 | #define QLCNIC_LINUX_VERSIONID "5.1.38" | |
96f8118c | 43 | #define QLCNIC_DRV_IDC_VER 0x01 |
d4066833 SC |
44 | #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ |
45 | (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) | |
af19b491 AKS |
46 | |
47 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
48 | #define _major(v) (((v) >> 24) & 0xff) | |
49 | #define _minor(v) (((v) >> 16) & 0xff) | |
50 | #define _build(v) ((v) & 0xffff) | |
51 | ||
52 | /* version in image has weird encoding: | |
53 | * 7:0 - major | |
54 | * 15:8 - minor | |
55 | * 31:16 - build (little endian) | |
56 | */ | |
57 | #define QLCNIC_DECODE_VERSION(v) \ | |
58 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
59 | ||
8f891387 | 60 | #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
af19b491 AKS |
61 | #define QLCNIC_NUM_FLASH_SECTORS (64) |
62 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
63 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
64 | * QLCNIC_FLASH_SECTOR_SIZE) | |
65 | ||
66 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
67 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
68 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
69 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
70 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
71 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
72 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
73 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
74 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
75 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
76 | ||
77 | #define QLCNIC_P3P_A0 0x50 | |
a2050c7e | 78 | #define QLCNIC_P3P_C0 0x58 |
af19b491 AKS |
79 | |
80 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
81 | ||
82 | #define FIRST_PAGE_GROUP_START 0 | |
83 | #define FIRST_PAGE_GROUP_END 0x100000 | |
84 | ||
ff1b1bf8 SV |
85 | #define P3P_MAX_MTU (9600) |
86 | #define P3P_MIN_MTU (68) | |
af19b491 AKS |
87 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ |
88 | ||
ff1b1bf8 SV |
89 | #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) |
90 | #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) | |
af19b491 AKS |
91 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 |
92 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
93 | ||
af19b491 | 94 | /* Tx defines */ |
91a403ca | 95 | #define QLCNIC_MAX_FRAGS_PER_TX 14 |
ef71ff83 RB |
96 | #define MAX_TSO_HEADER_DESC 2 |
97 | #define MGMT_CMD_DESC_RESV 4 | |
98 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ | |
99 | + MGMT_CMD_DESC_RESV) | |
af19b491 | 100 | #define QLCNIC_MAX_TX_TIMEOUTS 2 |
af19b491 AKS |
101 | /* |
102 | * Following are the states of the Phantom. Phantom will set them and | |
103 | * Host will read to check if the fields are correct. | |
104 | */ | |
105 | #define PHAN_INITIALIZE_FAILED 0xffff | |
106 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
107 | ||
108 | /* Host writes the following to notify that it has done the init-handshake */ | |
109 | #define PHAN_INITIALIZE_ACK 0xf00f | |
110 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
111 | ||
112 | #define NUM_RCV_DESC_RINGS 3 | |
af19b491 AKS |
113 | |
114 | #define RCV_RING_NORMAL 0 | |
115 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
116 | |
117 | #define MIN_CMD_DESCRIPTORS 64 | |
118 | #define MIN_RCV_DESCRIPTORS 64 | |
119 | #define MIN_JUMBO_DESCRIPTORS 32 | |
120 | ||
121 | #define MAX_CMD_DESCRIPTORS 1024 | |
122 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
123 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
90d19005 | 124 | #define MAX_RCV_DESCRIPTORS_VF 2048 |
af19b491 AKS |
125 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 |
126 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
127 | |
128 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
129 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
90d19005 | 130 | #define DEFAULT_RCV_DESCRIPTORS_VF 1024 |
251b036a | 131 | #define MAX_RDS_RINGS 2 |
af19b491 AKS |
132 | |
133 | #define get_next_index(index, length) \ | |
134 | (((index) + 1) & ((length) - 1)) | |
135 | ||
af19b491 AKS |
136 | /* |
137 | * Following data structures describe the descriptors that will be used. | |
138 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
139 | * we are doing LSO (above the 1500 size packet) only. | |
140 | */ | |
af19b491 AKS |
141 | struct cmd_desc_type0 { |
142 | u8 tcp_hdr_offset; /* For LSO only */ | |
143 | u8 ip_hdr_offset; /* For LSO only */ | |
144 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
145 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
146 | ||
147 | __le64 addr_buffer2; | |
148 | ||
149 | __le16 reference_handle; | |
150 | __le16 mss; | |
151 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
152 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
153 | __le16 conn_id; /* IPSec offoad only */ | |
154 | ||
155 | __le64 addr_buffer3; | |
156 | __le64 addr_buffer1; | |
157 | ||
158 | __le16 buffer_length[4]; | |
159 | ||
160 | __le64 addr_buffer4; | |
161 | ||
2e9d722d | 162 | u8 eth_addr[ETH_ALEN]; |
af19b491 AKS |
163 | __le16 vlan_TCI; |
164 | ||
165 | } __attribute__ ((aligned(64))); | |
166 | ||
167 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
168 | struct rcv_desc { | |
169 | __le16 reference_handle; | |
170 | __le16 reserved; | |
171 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
172 | __le64 addr_buffer; | |
b1fc6d3c | 173 | } __packed; |
af19b491 | 174 | |
af19b491 AKS |
175 | struct status_desc { |
176 | __le64 status_desc_data[2]; | |
177 | } __attribute__ ((aligned(16))); | |
178 | ||
179 | /* UNIFIED ROMIMAGE */ | |
180 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
181 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
182 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
183 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
184 | ||
185 | /*Offsets */ | |
186 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
187 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
188 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
189 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
190 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
191 | ||
192 | struct uni_table_desc{ | |
63507592 SS |
193 | __le32 findex; |
194 | __le32 num_entries; | |
195 | __le32 entry_size; | |
196 | __le32 reserved[5]; | |
af19b491 AKS |
197 | }; |
198 | ||
199 | struct uni_data_desc{ | |
63507592 SS |
200 | __le32 findex; |
201 | __le32 size; | |
202 | __le32 reserved[5]; | |
af19b491 AKS |
203 | }; |
204 | ||
0e5f20b6 | 205 | /* Flash Defines and Structures */ |
206 | #define QLCNIC_FLT_LOCATION 0x3F1000 | |
d865ebb4 | 207 | #define QLCNIC_FDT_LOCATION 0x3F0000 |
a2050c7e SV |
208 | #define QLCNIC_B0_FW_IMAGE_REGION 0x74 |
209 | #define QLCNIC_C0_FW_IMAGE_REGION 0x97 | |
f8d54811 | 210 | #define QLCNIC_BOOTLD_REGION 0X72 |
0e5f20b6 | 211 | struct qlcnic_flt_header { |
212 | u16 version; | |
213 | u16 len; | |
214 | u16 checksum; | |
215 | u16 reserved; | |
216 | }; | |
217 | ||
218 | struct qlcnic_flt_entry { | |
219 | u8 region; | |
220 | u8 reserved0; | |
221 | u8 attrib; | |
222 | u8 reserved1; | |
223 | u32 size; | |
224 | u32 start_addr; | |
f8d54811 | 225 | u32 end_addr; |
0e5f20b6 | 226 | }; |
227 | ||
d865ebb4 SC |
228 | /* Flash Descriptor Table */ |
229 | struct qlcnic_fdt { | |
230 | u32 valid; | |
231 | u16 ver; | |
232 | u16 len; | |
233 | u16 cksum; | |
234 | u16 unused; | |
235 | u8 model[16]; | |
236 | u16 mfg_id; | |
237 | u16 id; | |
238 | u8 flag; | |
239 | u8 erase_cmd; | |
240 | u8 alt_erase_cmd; | |
241 | u8 write_enable_cmd; | |
242 | u8 write_enable_bits; | |
243 | u8 write_statusreg_cmd; | |
244 | u8 unprotected_sec_cmd; | |
245 | u8 read_manuf_cmd; | |
246 | u32 block_size; | |
247 | u32 alt_block_size; | |
248 | u32 flash_size; | |
249 | u32 write_enable_data; | |
250 | u8 readid_addr_len; | |
251 | u8 write_disable_bits; | |
252 | u8 read_dev_id_len; | |
253 | u8 chip_erase_cmd; | |
254 | u16 read_timeo; | |
255 | u8 protected_sec_cmd; | |
256 | u8 resvd[65]; | |
257 | }; | |
af19b491 AKS |
258 | /* Magic number to let user know flash is programmed */ |
259 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
260 | ||
ff1b1bf8 SV |
261 | #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 |
262 | #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 | |
263 | #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 | |
264 | #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 | |
265 | #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 | |
266 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 | |
267 | #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 | |
268 | #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 | |
269 | #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 | |
270 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a | |
271 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b | |
272 | #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 | |
273 | #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 | |
274 | #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 | |
af19b491 | 275 | |
2e9d722d AC |
276 | #define QLCNIC_MSIX_TABLE_OFFSET 0x44 |
277 | ||
af19b491 AKS |
278 | /* Flash memory map */ |
279 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
280 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
281 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
282 | #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ | |
283 | ||
284 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
285 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
286 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
287 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
288 | ||
289 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
290 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
291 | ||
292 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
293 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
294 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
295 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
296 | ||
297 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
298 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
299 | ||
300 | extern char qlcnic_driver_name[]; | |
301 | ||
629263ac SC |
302 | extern int qlcnic_use_msi; |
303 | extern int qlcnic_use_msi_x; | |
304 | extern int qlcnic_auto_fw_reset; | |
305 | extern int qlcnic_load_fw_file; | |
306 | extern int qlcnic_config_npars; | |
307 | ||
af19b491 AKS |
308 | /* Number of status descriptors to handle per interrupt */ |
309 | #define MAX_STATUS_HANDLE (64) | |
310 | ||
311 | /* | |
312 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
313 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
314 | */ | |
315 | struct qlcnic_skb_frag { | |
316 | u64 dma; | |
317 | u64 length; | |
318 | }; | |
319 | ||
af19b491 AKS |
320 | /* Following defines are for the state of the buffers */ |
321 | #define QLCNIC_BUFFER_FREE 0 | |
322 | #define QLCNIC_BUFFER_BUSY 1 | |
323 | ||
324 | /* | |
325 | * There will be one qlcnic_buffer per skb packet. These will be | |
326 | * used to save the dma info for pci_unmap_page() | |
327 | */ | |
328 | struct qlcnic_cmd_buffer { | |
329 | struct sk_buff *skb; | |
ef71ff83 | 330 | struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; |
af19b491 AKS |
331 | u32 frag_count; |
332 | }; | |
333 | ||
334 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
335 | struct qlcnic_rx_buffer { | |
b1fc6d3c | 336 | u16 ref_handle; |
af19b491 | 337 | struct sk_buff *skb; |
b1fc6d3c | 338 | struct list_head list; |
af19b491 | 339 | u64 dma; |
af19b491 AKS |
340 | }; |
341 | ||
342 | /* Board types */ | |
343 | #define QLCNIC_GBE 0x01 | |
344 | #define QLCNIC_XGBE 0x02 | |
345 | ||
8816d009 AC |
346 | /* |
347 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
348 | * adjusted based on configured MTU. | |
349 | */ | |
350 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 | |
351 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 | |
352 | ||
353 | #define QLCNIC_INTR_DEFAULT 0x04 | |
354 | #define QLCNIC_CONFIG_INTR_COALESCE 3 | |
7e38d04b | 355 | #define QLCNIC_DEV_INFO_SIZE 1 |
8816d009 AC |
356 | |
357 | struct qlcnic_nic_intr_coalesce { | |
358 | u8 type; | |
359 | u8 sts_ring_mask; | |
360 | u16 rx_packets; | |
361 | u16 rx_time_us; | |
362 | u16 flag; | |
363 | u32 timer_out; | |
364 | }; | |
365 | ||
18f2f616 | 366 | struct qlcnic_dump_template_hdr { |
63507592 SS |
367 | u32 type; |
368 | u32 offset; | |
369 | u32 size; | |
370 | u32 cap_mask; | |
371 | u32 num_entries; | |
372 | u32 version; | |
373 | u32 timestamp; | |
374 | u32 checksum; | |
375 | u32 drv_cap_mask; | |
376 | u32 sys_info[3]; | |
377 | u32 saved_state[16]; | |
378 | u32 cap_sizes[8]; | |
4e60ac46 | 379 | u32 ocm_wnd_reg[16]; |
63507592 | 380 | u32 rsvd[0]; |
18f2f616 AC |
381 | }; |
382 | ||
383 | struct qlcnic_fw_dump { | |
384 | u8 clr; /* flag to indicate if dump is cleared */ | |
9d6a6440 | 385 | u8 enable; /* enable/disable dump */ |
18f2f616 AC |
386 | u32 size; /* total size of the dump */ |
387 | void *data; /* dump data area */ | |
388 | struct qlcnic_dump_template_hdr *tmpl_hdr; | |
389 | }; | |
390 | ||
af19b491 AKS |
391 | /* |
392 | * One hardware_context{} per adapter | |
393 | * contains interrupt info as well shared hardware info. | |
394 | */ | |
395 | struct qlcnic_hardware_context { | |
396 | void __iomem *pci_base0; | |
397 | void __iomem *ocm_win_crb; | |
398 | ||
399 | unsigned long pci_len0; | |
400 | ||
af19b491 AKS |
401 | rwlock_t crb_lock; |
402 | struct mutex mem_lock; | |
403 | ||
af19b491 AKS |
404 | u8 revision_id; |
405 | u8 pci_func; | |
406 | u8 linkup; | |
22c8c934 | 407 | u8 loopback_state; |
79788450 SC |
408 | u8 beacon_state; |
409 | u8 has_link_events; | |
410 | u8 fw_type; | |
411 | u8 physical_port; | |
412 | u8 reset_context; | |
413 | u8 msix_supported; | |
414 | u8 max_mac_filters; | |
415 | u8 mc_enabled; | |
416 | u8 max_mc_count; | |
417 | u8 diag_test; | |
418 | u8 num_msix; | |
419 | u8 nic_mode; | |
420 | char diag_cnt; | |
421 | ||
af19b491 AKS |
422 | u16 port_type; |
423 | u16 board_type; | |
8816d009 | 424 | |
79788450 SC |
425 | u16 link_speed; |
426 | u16 link_duplex; | |
427 | u16 link_autoneg; | |
428 | u16 module_type; | |
429 | ||
430 | u16 op_mode; | |
431 | u16 switch_mode; | |
432 | u16 max_tx_ques; | |
433 | u16 max_rx_ques; | |
434 | u16 max_mtu; | |
435 | u32 msg_enable; | |
436 | u16 act_pci_func; | |
728a98b8 | 437 | |
79788450 | 438 | u32 capabilities; |
776e7bde | 439 | u32 capabilities2; |
79788450 SC |
440 | u32 temp; |
441 | u32 int_vec_bit; | |
442 | u32 fw_hal_version; | |
7f966452 | 443 | u32 port_config; |
79788450 | 444 | struct qlcnic_hardware_ops *hw_ops; |
8816d009 | 445 | struct qlcnic_nic_intr_coalesce coal; |
18f2f616 | 446 | struct qlcnic_fw_dump fw_dump; |
d865ebb4 | 447 | struct qlcnic_fdt fdt; |
81d0aeb0 | 448 | struct qlc_83xx_reset reset; |
629263ac SC |
449 | struct qlc_83xx_idc idc; |
450 | struct qlc_83xx_fw_info fw_info; | |
7f966452 | 451 | struct qlcnic_intrpt_config *intr_tbl; |
02feda17 | 452 | struct qlcnic_sriov *sriov; |
7e2cf4fe | 453 | u32 *reg_tbl; |
7f966452 SC |
454 | u32 *ext_reg_tbl; |
455 | u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; | |
456 | u32 mbox_reg[4]; | |
457 | spinlock_t mbx_lock; | |
af19b491 AKS |
458 | }; |
459 | ||
460 | struct qlcnic_adapter_stats { | |
461 | u64 xmitcalled; | |
462 | u64 xmitfinished; | |
463 | u64 rxdropped; | |
464 | u64 txdropped; | |
465 | u64 csummed; | |
466 | u64 rx_pkts; | |
467 | u64 lro_pkts; | |
468 | u64 rxbytes; | |
469 | u64 txbytes; | |
8bfe8b91 SC |
470 | u64 lrobytes; |
471 | u64 lso_frames; | |
472 | u64 xmit_on; | |
473 | u64 xmit_off; | |
474 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
475 | u64 null_rxbuf; |
476 | u64 rx_dma_map_error; | |
477 | u64 tx_dma_map_error; | |
7f966452 | 478 | u64 spurious_intr; |
4be41e92 | 479 | u64 mac_filter_limit_overrun; |
af19b491 AKS |
480 | }; |
481 | ||
482 | /* | |
483 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
484 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
485 | */ | |
486 | struct qlcnic_host_rds_ring { | |
036d61f0 AC |
487 | void __iomem *crb_rcv_producer; |
488 | struct rcv_desc *desc_head; | |
489 | struct qlcnic_rx_buffer *rx_buf_arr; | |
af19b491 | 490 | u32 num_desc; |
036d61f0 | 491 | u32 producer; |
af19b491 AKS |
492 | u32 dma_size; |
493 | u32 skb_size; | |
494 | u32 flags; | |
af19b491 AKS |
495 | struct list_head free_list; |
496 | spinlock_t lock; | |
497 | dma_addr_t phys_addr; | |
036d61f0 | 498 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
499 | |
500 | struct qlcnic_host_sds_ring { | |
501 | u32 consumer; | |
502 | u32 num_desc; | |
503 | void __iomem *crb_sts_consumer; | |
af19b491 AKS |
504 | |
505 | struct status_desc *desc_head; | |
506 | struct qlcnic_adapter *adapter; | |
507 | struct napi_struct napi; | |
508 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
509 | ||
036d61f0 | 510 | void __iomem *crb_intr_mask; |
af19b491 AKS |
511 | int irq; |
512 | ||
513 | dma_addr_t phys_addr; | |
514 | char name[IFNAMSIZ+4]; | |
036d61f0 | 515 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
516 | |
517 | struct qlcnic_host_tx_ring { | |
4be41e92 | 518 | int irq; |
7f966452 SC |
519 | void __iomem *crb_intr_mask; |
520 | char name[IFNAMSIZ+4]; | |
79788450 | 521 | u16 ctx_id; |
af19b491 | 522 | u32 producer; |
af19b491 | 523 | u32 sw_consumer; |
af19b491 | 524 | u32 num_desc; |
036d61f0 | 525 | void __iomem *crb_cmd_producer; |
af19b491 | 526 | struct cmd_desc_type0 *desc_head; |
4be41e92 SC |
527 | struct qlcnic_adapter *adapter; |
528 | struct napi_struct napi; | |
036d61f0 AC |
529 | struct qlcnic_cmd_buffer *cmd_buf_arr; |
530 | __le32 *hw_consumer; | |
531 | ||
af19b491 AKS |
532 | dma_addr_t phys_addr; |
533 | dma_addr_t hw_cons_phys_addr; | |
036d61f0 AC |
534 | struct netdev_queue *txq; |
535 | } ____cacheline_internodealigned_in_smp; | |
af19b491 AKS |
536 | |
537 | /* | |
538 | * Receive context. There is one such structure per instance of the | |
539 | * receive processing. Any state information that is relevant to | |
540 | * the receive, and is must be in this structure. The global data may be | |
541 | * present elsewhere. | |
542 | */ | |
543 | struct qlcnic_recv_context { | |
b1fc6d3c AC |
544 | struct qlcnic_host_rds_ring *rds_rings; |
545 | struct qlcnic_host_sds_ring *sds_rings; | |
af19b491 AKS |
546 | u32 state; |
547 | u16 context_id; | |
548 | u16 virt_port; | |
549 | ||
af19b491 AKS |
550 | }; |
551 | ||
552 | /* HW context creation */ | |
553 | ||
554 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
af19b491 AKS |
555 | |
556 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
557 | ||
558 | /* | |
559 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
560 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
561 | */ | |
562 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
563 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
564 | ||
565 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
566 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
567 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
568 | ||
569 | /* | |
570 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
571 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
572 | */ | |
573 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
af19b491 AKS |
574 | |
575 | #define QLCNIC_RCODE_SUCCESS 0 | |
e42ede22 | 576 | #define QLCNIC_RCODE_INVALID_ARGS 6 |
7e610caa | 577 | #define QLCNIC_RCODE_NOT_SUPPORTED 9 |
e42ede22 JK |
578 | #define QLCNIC_RCODE_NOT_PERMITTED 10 |
579 | #define QLCNIC_RCODE_NOT_IMPL 15 | |
580 | #define QLCNIC_RCODE_INVALID 16 | |
af19b491 AKS |
581 | #define QLCNIC_RCODE_TIMEOUT 17 |
582 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
583 | ||
584 | /* | |
585 | * Capabilities Announced | |
586 | */ | |
587 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
588 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
589 | #define QLCNIC_CAP0_LSO (1 << 6) | |
590 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
591 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
8f891387 | 592 | #define QLCNIC_CAP0_VALIDOFF (1 << 11) |
cae82d49 | 593 | #define QLCNIC_CAP0_LRO_MSS (1 << 21) |
af19b491 AKS |
594 | |
595 | /* | |
596 | * Context state | |
597 | */ | |
d626ad4d | 598 | #define QLCNIC_HOST_CTX_STATE_FREED 0 |
af19b491 AKS |
599 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
600 | ||
601 | /* | |
602 | * Rx context | |
603 | */ | |
604 | ||
605 | struct qlcnic_hostrq_sds_ring { | |
606 | __le64 host_phys_addr; /* Ring base addr */ | |
607 | __le32 ring_size; /* Ring entries */ | |
608 | __le16 msi_index; | |
609 | __le16 rsvd; /* Padding */ | |
b1fc6d3c | 610 | } __packed; |
af19b491 AKS |
611 | |
612 | struct qlcnic_hostrq_rds_ring { | |
613 | __le64 host_phys_addr; /* Ring base addr */ | |
614 | __le64 buff_size; /* Packet buffer size */ | |
615 | __le32 ring_size; /* Ring entries */ | |
616 | __le32 ring_kind; /* Class of ring */ | |
b1fc6d3c | 617 | } __packed; |
af19b491 AKS |
618 | |
619 | struct qlcnic_hostrq_rx_ctx { | |
620 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
621 | __le32 capabilities[4]; /* Flag bit vector */ | |
622 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
623 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
624 | /* These ring offsets are relative to data[0] below */ | |
625 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
626 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
627 | __le16 num_rds_rings; /* Count of RDS rings */ | |
628 | __le16 num_sds_rings; /* Count of SDS rings */ | |
8f891387 | 629 | __le16 valid_field_offset; |
630 | u8 txrx_sds_binding; | |
631 | u8 msix_handler; | |
632 | u8 reserved[128]; /* reserve space for future expansion*/ | |
af19b491 AKS |
633 | /* MUST BE 64-bit aligned. |
634 | The following is packed: | |
635 | - N hostrq_rds_rings | |
636 | - N hostrq_sds_rings */ | |
637 | char data[0]; | |
b1fc6d3c | 638 | } __packed; |
af19b491 AKS |
639 | |
640 | struct qlcnic_cardrsp_rds_ring{ | |
641 | __le32 host_producer_crb; /* Crb to use */ | |
642 | __le32 rsvd1; /* Padding */ | |
b1fc6d3c | 643 | } __packed; |
af19b491 AKS |
644 | |
645 | struct qlcnic_cardrsp_sds_ring { | |
646 | __le32 host_consumer_crb; /* Crb to use */ | |
647 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 648 | } __packed; |
af19b491 AKS |
649 | |
650 | struct qlcnic_cardrsp_rx_ctx { | |
651 | /* These ring offsets are relative to data[0] below */ | |
652 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
653 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
654 | __le32 host_ctx_state; /* Starting State */ | |
655 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
656 | __le16 num_rds_rings; /* Count of RDS rings */ | |
657 | __le16 num_sds_rings; /* Count of SDS rings */ | |
658 | __le16 context_id; /* Handle for context */ | |
659 | u8 phys_port; /* Physical id of port */ | |
660 | u8 virt_port; /* Virtual/Logical id of port */ | |
661 | u8 reserved[128]; /* save space for future expansion */ | |
662 | /* MUST BE 64-bit aligned. | |
663 | The following is packed: | |
664 | - N cardrsp_rds_rings | |
665 | - N cardrs_sds_rings */ | |
666 | char data[0]; | |
b1fc6d3c | 667 | } __packed; |
af19b491 AKS |
668 | |
669 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
670 | (sizeof(HOSTRQ_RX) + \ | |
671 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
672 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
673 | ||
674 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
675 | (sizeof(CARDRSP_RX) + \ | |
676 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
677 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
678 | ||
679 | /* | |
680 | * Tx context | |
681 | */ | |
682 | ||
683 | struct qlcnic_hostrq_cds_ring { | |
684 | __le64 host_phys_addr; /* Ring base addr */ | |
685 | __le32 ring_size; /* Ring entries */ | |
686 | __le32 rsvd; /* Padding */ | |
b1fc6d3c | 687 | } __packed; |
af19b491 AKS |
688 | |
689 | struct qlcnic_hostrq_tx_ctx { | |
690 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
691 | __le64 cmd_cons_dma_addr; /* */ | |
692 | __le64 dummy_dma_addr; /* */ | |
693 | __le32 capabilities[4]; /* Flag bit vector */ | |
694 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
695 | __le32 rsvd1; /* Padding */ | |
696 | __le16 rsvd2; /* Padding */ | |
697 | __le16 interrupt_ctl; | |
698 | __le16 msi_index; | |
699 | __le16 rsvd3; /* Padding */ | |
700 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
701 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 702 | } __packed; |
af19b491 AKS |
703 | |
704 | struct qlcnic_cardrsp_cds_ring { | |
705 | __le32 host_producer_crb; /* Crb to use */ | |
706 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 707 | } __packed; |
af19b491 AKS |
708 | |
709 | struct qlcnic_cardrsp_tx_ctx { | |
710 | __le32 host_ctx_state; /* Starting state */ | |
711 | __le16 context_id; /* Handle for context */ | |
712 | u8 phys_port; /* Physical id of port */ | |
713 | u8 virt_port; /* Virtual/Logical id of port */ | |
714 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
715 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 716 | } __packed; |
af19b491 AKS |
717 | |
718 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
719 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
720 | ||
721 | /* CRB */ | |
722 | ||
723 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
724 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
725 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
726 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
727 | ||
728 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
729 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
730 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
731 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
732 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
733 | ||
734 | ||
735 | /* MAC */ | |
736 | ||
ff1b1bf8 | 737 | #define MC_COUNT_P3P 38 |
af19b491 AKS |
738 | |
739 | #define QLCNIC_MAC_NOOP 0 | |
740 | #define QLCNIC_MAC_ADD 1 | |
741 | #define QLCNIC_MAC_DEL 2 | |
03c5d770 AKS |
742 | #define QLCNIC_MAC_VLAN_ADD 3 |
743 | #define QLCNIC_MAC_VLAN_DEL 4 | |
af19b491 AKS |
744 | |
745 | struct qlcnic_mac_list_s { | |
746 | struct list_head list; | |
747 | uint8_t mac_addr[ETH_ALEN+2]; | |
748 | }; | |
749 | ||
fe1adc6b JK |
750 | /* MAC Learn */ |
751 | #define NO_MAC_LEARN 0 | |
752 | #define DRV_MAC_LEARN 1 | |
753 | #define FDB_MAC_LEARN 2 | |
754 | ||
af19b491 AKS |
755 | #define QLCNIC_HOST_REQUEST 0x13 |
756 | #define QLCNIC_REQUEST 0x14 | |
757 | ||
758 | #define QLCNIC_MAC_EVENT 0x1 | |
759 | ||
760 | #define QLCNIC_IP_UP 2 | |
761 | #define QLCNIC_IP_DOWN 3 | |
762 | ||
22c8c934 | 763 | #define QLCNIC_ILB_MODE 0x1 |
e1428d26 | 764 | #define QLCNIC_ELB_MODE 0x2 |
22c8c934 SC |
765 | |
766 | #define QLCNIC_LINKEVENT 0x1 | |
767 | #define QLCNIC_LB_RESPONSE 0x2 | |
768 | #define QLCNIC_IS_LB_CONFIGURED(VAL) \ | |
769 | (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) | |
770 | ||
af19b491 AKS |
771 | /* |
772 | * Driver --> Firmware | |
773 | */ | |
b1fc6d3c AC |
774 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 |
775 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 | |
776 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 | |
777 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 | |
778 | #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc | |
779 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 | |
22c8c934 | 780 | |
b1fc6d3c AC |
781 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 |
782 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 | |
783 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 | |
22c8c934 SC |
784 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 |
785 | ||
af19b491 AKS |
786 | /* |
787 | * Firmware --> Driver | |
788 | */ | |
789 | ||
22c8c934 | 790 | #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f |
7f966452 | 791 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D |
af19b491 AKS |
792 | |
793 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
794 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
795 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
796 | ||
797 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
798 | ||
799 | /* Capabilites received */ | |
ac8d0c4f AC |
800 | #define QLCNIC_FW_CAPABILITY_TSO BIT_1 |
801 | #define QLCNIC_FW_CAPABILITY_BDG BIT_8 | |
802 | #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 | |
803 | #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 | |
fef0c060 | 804 | #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 |
cae82d49 RB |
805 | #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 |
806 | ||
807 | #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 | |
776e7bde | 808 | #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3 |
c84e340a | 809 | #define QLCNIC_FW_CAPABILITY_2_OCBB BIT_5 |
af19b491 AKS |
810 | |
811 | /* module types */ | |
812 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
813 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
814 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
815 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
816 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
817 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
818 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
819 | #define LINKEVENT_MODULE_TWINAX 8 | |
820 | ||
821 | #define LINKSPEED_10GBPS 10000 | |
822 | #define LINKSPEED_1GBPS 1000 | |
823 | #define LINKSPEED_100MBPS 100 | |
824 | #define LINKSPEED_10MBPS 10 | |
825 | ||
826 | #define LINKSPEED_ENCODED_10MBPS 0 | |
827 | #define LINKSPEED_ENCODED_100MBPS 1 | |
828 | #define LINKSPEED_ENCODED_1GBPS 2 | |
829 | ||
830 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
831 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
832 | ||
833 | #define LINKEVENT_HALF_DUPLEX 0 | |
834 | #define LINKEVENT_FULL_DUPLEX 1 | |
835 | ||
836 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
837 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
838 | ||
af19b491 AKS |
839 | /* firmware response header: |
840 | * 63:58 - message type | |
841 | * 57:56 - owner | |
842 | * 55:53 - desc count | |
843 | * 52:48 - reserved | |
844 | * 47:40 - completion id | |
845 | * 39:32 - opcode | |
846 | * 31:16 - error code | |
847 | * 15:00 - reserved | |
848 | */ | |
849 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
850 | ((msg_hdr >> 32) & 0xFF) | |
851 | ||
852 | struct qlcnic_fw_msg { | |
853 | union { | |
854 | struct { | |
855 | u64 hdr; | |
856 | u64 body[7]; | |
857 | }; | |
858 | u64 words[8]; | |
859 | }; | |
860 | }; | |
861 | ||
862 | struct qlcnic_nic_req { | |
863 | __le64 qhdr; | |
864 | __le64 req_hdr; | |
865 | __le64 words[6]; | |
b1fc6d3c | 866 | } __packed; |
af19b491 AKS |
867 | |
868 | struct qlcnic_mac_req { | |
869 | u8 op; | |
870 | u8 tag; | |
871 | u8 mac_addr[6]; | |
872 | }; | |
873 | ||
7e56cac4 SC |
874 | struct qlcnic_vlan_req { |
875 | __le16 vlan_id; | |
876 | __le16 rsvd[3]; | |
b1fc6d3c | 877 | } __packed; |
7e56cac4 | 878 | |
b501595c SC |
879 | struct qlcnic_ipaddr { |
880 | __be32 ipv4; | |
881 | __be32 ipv6[4]; | |
882 | }; | |
883 | ||
af19b491 AKS |
884 | #define QLCNIC_MSI_ENABLED 0x02 |
885 | #define QLCNIC_MSIX_ENABLED 0x04 | |
7f966452 | 886 | #define QLCNIC_LRO_ENABLED 0x01 |
24763d80 | 887 | #define QLCNIC_LRO_DISABLED 0x00 |
af19b491 AKS |
888 | #define QLCNIC_BRIDGE_ENABLED 0X10 |
889 | #define QLCNIC_DIAG_ENABLED 0x20 | |
0e33c664 | 890 | #define QLCNIC_ESWITCH_ENABLED 0x40 |
0866d96d | 891 | #define QLCNIC_ADAPTER_INITIALIZED 0x80 |
8cf61f89 | 892 | #define QLCNIC_TAGGING_ENABLED 0x100 |
fe4d434d | 893 | #define QLCNIC_MACSPOOF 0x200 |
7373373d | 894 | #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 |
ee07c1a7 | 895 | #define QLCNIC_PROMISC_DISABLED 0x800 |
b0044bcf | 896 | #define QLCNIC_NEED_FLR 0x1000 |
602ca6f0 | 897 | #define QLCNIC_FW_RESET_OWNER 0x2000 |
032a13c7 | 898 | #define QLCNIC_FW_HANG 0x4000 |
cae82d49 | 899 | #define QLCNIC_FW_LRO_MSS_CAP 0x8000 |
af19b491 AKS |
900 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ |
901 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
902 | ||
f94bc1e7 | 903 | #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4 |
af19b491 AKS |
904 | #define QLCNIC_MSIX_TBL_SPACE 8192 |
905 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
2e9d722d | 906 | #define QLCNIC_MSIX_TBL_PGSIZE 4096 |
af19b491 AKS |
907 | |
908 | #define QLCNIC_NETDEV_WEIGHT 128 | |
909 | #define QLCNIC_ADAPTER_UP_MAGIC 777 | |
910 | ||
911 | #define __QLCNIC_FW_ATTACHED 0 | |
912 | #define __QLCNIC_DEV_UP 1 | |
913 | #define __QLCNIC_RESETTING 2 | |
914 | #define __QLCNIC_START_FW 4 | |
451724c8 | 915 | #define __QLCNIC_AER 5 |
89b4208e | 916 | #define __QLCNIC_DIAG_RES_ALLOC 6 |
728a98b8 | 917 | #define __QLCNIC_LED_ENABLE 7 |
02feda17 RB |
918 | #define __QLCNIC_ELB_INPROGRESS 8 |
919 | #define __QLCNIC_SRIOV_ENABLE 10 | |
920 | #define __QLCNIC_SRIOV_CAPABLE 11 | |
af19b491 | 921 | |
7eb9855d | 922 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 923 | #define QLCNIC_LOOPBACK_TEST 2 |
c75822a3 | 924 | #define QLCNIC_LED_TEST 3 |
7eb9855d | 925 | |
b5e5492c | 926 | #define QLCNIC_FILTER_AGE 80 |
e5edb7b1 | 927 | #define QLCNIC_READD_AGE 20 |
b5e5492c | 928 | #define QLCNIC_LB_MAX_FILTERS 64 |
7f966452 | 929 | #define QLCNIC_LB_BUCKET_SIZE 32 |
b5e5492c | 930 | |
fef0c060 AKS |
931 | /* QLCNIC Driver Error Code */ |
932 | #define QLCNIC_FW_NOT_RESPOND 51 | |
933 | #define QLCNIC_TEST_IN_PROGRESS 52 | |
934 | #define QLCNIC_UNDEFINED_ERROR 53 | |
935 | #define QLCNIC_LB_CABLE_NOT_CONN 54 | |
629263ac | 936 | #define QLCNIC_ILB_MAX_RCV_LOOP 10 |
fef0c060 | 937 | |
b5e5492c AKS |
938 | struct qlcnic_filter { |
939 | struct hlist_node fnode; | |
940 | u8 faddr[ETH_ALEN]; | |
7e56cac4 | 941 | __le16 vlan_id; |
b5e5492c AKS |
942 | unsigned long ftime; |
943 | }; | |
944 | ||
945 | struct qlcnic_filter_hash { | |
946 | struct hlist_head *fhead; | |
947 | u8 fnum; | |
7f966452 SC |
948 | u16 fmax; |
949 | u16 fbucket_size; | |
b5e5492c AKS |
950 | }; |
951 | ||
af19b491 | 952 | struct qlcnic_adapter { |
b1fc6d3c AC |
953 | struct qlcnic_hardware_context *ahw; |
954 | struct qlcnic_recv_context *recv_ctx; | |
955 | struct qlcnic_host_tx_ring *tx_ring; | |
af19b491 AKS |
956 | struct net_device *netdev; |
957 | struct pci_dev *pdev; | |
af19b491 | 958 | |
b1fc6d3c AC |
959 | unsigned long state; |
960 | u32 flags; | |
af19b491 | 961 | |
79788450 | 962 | int max_drv_tx_rings; |
af19b491 AKS |
963 | u16 num_txd; |
964 | u16 num_rxd; | |
965 | u16 num_jumbo_rxd; | |
90d19005 SC |
966 | u16 max_rxd; |
967 | u16 max_jumbo_rxd; | |
af19b491 AKS |
968 | |
969 | u8 max_rds_rings; | |
970 | u8 max_sds_rings; | |
7f966452 | 971 | u8 rx_csum; |
af19b491 | 972 | u8 portnum; |
af19b491 | 973 | |
af19b491 AKS |
974 | u8 fw_wait_cnt; |
975 | u8 fw_fail_cnt; | |
976 | u8 tx_timeo_cnt; | |
977 | u8 need_fw_reset; | |
978 | ||
af19b491 | 979 | u16 is_up; |
8cf61f89 | 980 | u16 pvid; |
2e9d722d | 981 | |
af19b491 | 982 | u32 irq; |
4e70812b | 983 | u32 heartbeat; |
af19b491 AKS |
984 | |
985 | u8 dev_state; | |
aa5e18c0 SC |
986 | u8 reset_ack_timeo; |
987 | u8 dev_init_timeo; | |
af19b491 AKS |
988 | |
989 | u8 mac_addr[ETH_ALEN]; | |
990 | ||
6df900e9 | 991 | u64 dev_rst_time; |
fe1adc6b JK |
992 | bool drv_mac_learn; |
993 | bool fdb_mac_learn; | |
b9796a14 | 994 | unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
d865ebb4 | 995 | u8 flash_mfg_id; |
346fe763 | 996 | struct qlcnic_npar_info *npars; |
2e9d722d AC |
997 | struct qlcnic_eswitch *eswitch; |
998 | struct qlcnic_nic_template *nic_ops; | |
999 | ||
af19b491 | 1000 | struct qlcnic_adapter_stats stats; |
b1fc6d3c | 1001 | struct list_head mac_list; |
af19b491 AKS |
1002 | |
1003 | void __iomem *tgt_mask_reg; | |
1004 | void __iomem *tgt_status_reg; | |
1005 | void __iomem *crb_int_state_reg; | |
1006 | void __iomem *isr_int_vec; | |
1007 | ||
f94bc1e7 | 1008 | struct msix_entry *msix_entries; |
7f966452 | 1009 | struct workqueue_struct *qlcnic_wq; |
af19b491 | 1010 | struct delayed_work fw_work; |
7f966452 | 1011 | struct delayed_work idc_aen_work; |
af19b491 | 1012 | |
b5e5492c | 1013 | struct qlcnic_filter_hash fhash; |
53643a75 | 1014 | struct qlcnic_filter_hash rx_fhash; |
b5e5492c | 1015 | |
b1fc6d3c AC |
1016 | spinlock_t tx_clean_lock; |
1017 | spinlock_t mac_learn_lock; | |
53643a75 SS |
1018 | /* spinlock for catching rcv filters for eswitch traffic */ |
1019 | spinlock_t rx_mac_learn_lock; | |
63507592 | 1020 | u32 file_prd_off; /*File fw product offset*/ |
af19b491 AKS |
1021 | u32 fw_version; |
1022 | const struct firmware *fw; | |
1023 | }; | |
1024 | ||
63507592 | 1025 | struct qlcnic_info_le { |
2e9d722d | 1026 | __le16 pci_func; |
63507592 | 1027 | __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ |
2e9d722d | 1028 | __le16 phys_port; |
63507592 | 1029 | __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ |
2e9d722d AC |
1030 | |
1031 | __le32 capabilities; | |
1032 | u8 max_mac_filters; | |
1033 | u8 reserved1; | |
1034 | __le16 max_mtu; | |
1035 | ||
1036 | __le16 max_tx_ques; | |
1037 | __le16 max_rx_ques; | |
1038 | __le16 min_tx_bw; | |
1039 | __le16 max_tx_bw; | |
7f966452 SC |
1040 | __le32 op_type; |
1041 | __le16 max_bw_reg_offset; | |
1042 | __le16 max_linkspeed_reg_offset; | |
1043 | __le32 capability1; | |
1044 | __le32 capability2; | |
1045 | __le32 capability3; | |
1046 | __le16 max_tx_mac_filters; | |
1047 | __le16 max_rx_mcast_mac_filters; | |
1048 | __le16 max_rx_ucast_mac_filters; | |
1049 | __le16 max_rx_ip_addr; | |
1050 | __le16 max_rx_lro_flow; | |
1051 | __le16 max_rx_status_rings; | |
1052 | __le16 max_rx_buf_rings; | |
1053 | __le16 max_tx_vlan_keys; | |
1054 | u8 total_pf; | |
1055 | u8 total_rss_engines; | |
1056 | __le16 max_vports; | |
02feda17 RB |
1057 | __le16 linkstate_reg_offset; |
1058 | __le16 bit_offsets; | |
1059 | __le16 max_local_ipv6_addrs; | |
1060 | __le16 max_remote_ipv6_addrs; | |
1061 | u8 reserved2[56]; | |
b1fc6d3c | 1062 | } __packed; |
2e9d722d | 1063 | |
63507592 SS |
1064 | struct qlcnic_info { |
1065 | u16 pci_func; | |
1066 | u16 op_mode; | |
1067 | u16 phys_port; | |
1068 | u16 switch_mode; | |
1069 | u32 capabilities; | |
1070 | u8 max_mac_filters; | |
63507592 SS |
1071 | u16 max_mtu; |
1072 | u16 max_tx_ques; | |
1073 | u16 max_rx_ques; | |
1074 | u16 min_tx_bw; | |
1075 | u16 max_tx_bw; | |
7f966452 SC |
1076 | u32 op_type; |
1077 | u16 max_bw_reg_offset; | |
1078 | u16 max_linkspeed_reg_offset; | |
1079 | u32 capability1; | |
1080 | u32 capability2; | |
1081 | u32 capability3; | |
1082 | u16 max_tx_mac_filters; | |
1083 | u16 max_rx_mcast_mac_filters; | |
1084 | u16 max_rx_ucast_mac_filters; | |
1085 | u16 max_rx_ip_addr; | |
1086 | u16 max_rx_lro_flow; | |
1087 | u16 max_rx_status_rings; | |
1088 | u16 max_rx_buf_rings; | |
1089 | u16 max_tx_vlan_keys; | |
1090 | u8 total_pf; | |
1091 | u8 total_rss_engines; | |
1092 | u16 max_vports; | |
02feda17 RB |
1093 | u16 linkstate_reg_offset; |
1094 | u16 bit_offsets; | |
1095 | u16 max_local_ipv6_addrs; | |
1096 | u16 max_remote_ipv6_addrs; | |
63507592 | 1097 | }; |
2e9d722d | 1098 | |
63507592 SS |
1099 | struct qlcnic_pci_info_le { |
1100 | __le16 id; /* pci function id */ | |
1101 | __le16 active; /* 1 = Enabled */ | |
1102 | __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ | |
1103 | __le16 default_port; /* default port number */ | |
1104 | ||
1105 | __le16 tx_min_bw; /* Multiple of 100mbpc */ | |
2e9d722d AC |
1106 | __le16 tx_max_bw; |
1107 | __le16 reserved1[2]; | |
1108 | ||
1109 | u8 mac[ETH_ALEN]; | |
7f966452 SC |
1110 | __le16 func_count; |
1111 | u8 reserved2[104]; | |
1112 | ||
b1fc6d3c | 1113 | } __packed; |
2e9d722d | 1114 | |
63507592 SS |
1115 | struct qlcnic_pci_info { |
1116 | u16 id; | |
1117 | u16 active; | |
1118 | u16 type; | |
1119 | u16 default_port; | |
1120 | u16 tx_min_bw; | |
1121 | u16 tx_max_bw; | |
1122 | u8 mac[ETH_ALEN]; | |
7f966452 | 1123 | u16 func_count; |
63507592 SS |
1124 | }; |
1125 | ||
346fe763 | 1126 | struct qlcnic_npar_info { |
4e8acb01 | 1127 | u16 pvid; |
cea8975e AC |
1128 | u16 min_bw; |
1129 | u16 max_bw; | |
346fe763 RB |
1130 | u8 phy_port; |
1131 | u8 type; | |
1132 | u8 active; | |
1133 | u8 enable_pm; | |
1134 | u8 dest_npar; | |
346fe763 | 1135 | u8 discard_tagged; |
7373373d | 1136 | u8 mac_override; |
4e8acb01 RB |
1137 | u8 mac_anti_spoof; |
1138 | u8 promisc_mode; | |
1139 | u8 offload_flags; | |
bff57d8e | 1140 | u8 pci_func; |
346fe763 | 1141 | }; |
4e8acb01 | 1142 | |
2e9d722d AC |
1143 | struct qlcnic_eswitch { |
1144 | u8 port; | |
1145 | u8 active_vports; | |
1146 | u8 active_vlans; | |
1147 | u8 active_ucast_filters; | |
1148 | u8 max_ucast_filters; | |
1149 | u8 max_active_vlans; | |
1150 | ||
1151 | u32 flags; | |
1152 | #define QLCNIC_SWITCH_ENABLE BIT_1 | |
1153 | #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 | |
1154 | #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 | |
1155 | #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 | |
1156 | }; | |
1157 | ||
346fe763 RB |
1158 | |
1159 | /* Return codes for Error handling */ | |
1160 | #define QL_STATUS_INVALID_PARAM -1 | |
1161 | ||
2abea2f0 | 1162 | #define MAX_BW 100 /* % of link speed */ |
346fe763 RB |
1163 | #define MAX_VLAN_ID 4095 |
1164 | #define MIN_VLAN_ID 2 | |
346fe763 RB |
1165 | #define DEFAULT_MAC_LEARN 1 |
1166 | ||
0184bbba | 1167 | #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) |
2abea2f0 | 1168 | #define IS_VALID_BW(bw) (bw <= MAX_BW) |
346fe763 RB |
1169 | |
1170 | struct qlcnic_pci_func_cfg { | |
1171 | u16 func_type; | |
1172 | u16 min_bw; | |
1173 | u16 max_bw; | |
1174 | u16 port_num; | |
1175 | u8 pci_func; | |
1176 | u8 func_state; | |
1177 | u8 def_mac_addr[6]; | |
1178 | }; | |
1179 | ||
1180 | struct qlcnic_npar_func_cfg { | |
1181 | u32 fw_capab; | |
1182 | u16 port_num; | |
1183 | u16 min_bw; | |
1184 | u16 max_bw; | |
1185 | u16 max_tx_queues; | |
1186 | u16 max_rx_queues; | |
1187 | u8 pci_func; | |
1188 | u8 op_mode; | |
1189 | }; | |
1190 | ||
1191 | struct qlcnic_pm_func_cfg { | |
1192 | u8 pci_func; | |
1193 | u8 action; | |
1194 | u8 dest_npar; | |
1195 | u8 reserved[5]; | |
1196 | }; | |
1197 | ||
1198 | struct qlcnic_esw_func_cfg { | |
1199 | u16 vlan_id; | |
4e8acb01 RB |
1200 | u8 op_mode; |
1201 | u8 op_type; | |
346fe763 RB |
1202 | u8 pci_func; |
1203 | u8 host_vlan_tag; | |
1204 | u8 promisc_mode; | |
1205 | u8 discard_tagged; | |
7373373d | 1206 | u8 mac_override; |
4e8acb01 RB |
1207 | u8 mac_anti_spoof; |
1208 | u8 offload_flags; | |
1209 | u8 reserved[5]; | |
346fe763 RB |
1210 | }; |
1211 | ||
b6021212 AKS |
1212 | #define QLCNIC_STATS_VERSION 1 |
1213 | #define QLCNIC_STATS_PORT 1 | |
1214 | #define QLCNIC_STATS_ESWITCH 2 | |
1215 | #define QLCNIC_QUERY_RX_COUNTER 0 | |
1216 | #define QLCNIC_QUERY_TX_COUNTER 1 | |
54a8997c JK |
1217 | #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL |
1218 | #define QLCNIC_FILL_STATS(VAL1) \ | |
1219 | (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) | |
1220 | #define QLCNIC_MAC_STATS 1 | |
1221 | #define QLCNIC_ESW_STATS 2 | |
ef182805 AKS |
1222 | |
1223 | #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ | |
1224 | do { \ | |
54a8997c JK |
1225 | if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ |
1226 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 | 1227 | (VAL1) = (VAL2); \ |
54a8997c JK |
1228 | else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ |
1229 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 AKS |
1230 | (VAL1) += (VAL2); \ |
1231 | } while (0) | |
1232 | ||
63507592 | 1233 | struct qlcnic_mac_statistics_le { |
54a8997c JK |
1234 | __le64 mac_tx_frames; |
1235 | __le64 mac_tx_bytes; | |
1236 | __le64 mac_tx_mcast_pkts; | |
1237 | __le64 mac_tx_bcast_pkts; | |
1238 | __le64 mac_tx_pause_cnt; | |
1239 | __le64 mac_tx_ctrl_pkt; | |
1240 | __le64 mac_tx_lt_64b_pkts; | |
1241 | __le64 mac_tx_lt_127b_pkts; | |
1242 | __le64 mac_tx_lt_255b_pkts; | |
1243 | __le64 mac_tx_lt_511b_pkts; | |
1244 | __le64 mac_tx_lt_1023b_pkts; | |
1245 | __le64 mac_tx_lt_1518b_pkts; | |
1246 | __le64 mac_tx_gt_1518b_pkts; | |
1247 | __le64 rsvd1[3]; | |
1248 | ||
1249 | __le64 mac_rx_frames; | |
1250 | __le64 mac_rx_bytes; | |
1251 | __le64 mac_rx_mcast_pkts; | |
1252 | __le64 mac_rx_bcast_pkts; | |
1253 | __le64 mac_rx_pause_cnt; | |
1254 | __le64 mac_rx_ctrl_pkt; | |
1255 | __le64 mac_rx_lt_64b_pkts; | |
1256 | __le64 mac_rx_lt_127b_pkts; | |
1257 | __le64 mac_rx_lt_255b_pkts; | |
1258 | __le64 mac_rx_lt_511b_pkts; | |
1259 | __le64 mac_rx_lt_1023b_pkts; | |
1260 | __le64 mac_rx_lt_1518b_pkts; | |
1261 | __le64 mac_rx_gt_1518b_pkts; | |
1262 | __le64 rsvd2[3]; | |
1263 | ||
1264 | __le64 mac_rx_length_error; | |
1265 | __le64 mac_rx_length_small; | |
1266 | __le64 mac_rx_length_large; | |
1267 | __le64 mac_rx_jabber; | |
1268 | __le64 mac_rx_dropped; | |
1269 | __le64 mac_rx_crc_error; | |
1270 | __le64 mac_align_error; | |
1271 | } __packed; | |
1272 | ||
63507592 SS |
1273 | struct qlcnic_mac_statistics { |
1274 | u64 mac_tx_frames; | |
1275 | u64 mac_tx_bytes; | |
1276 | u64 mac_tx_mcast_pkts; | |
1277 | u64 mac_tx_bcast_pkts; | |
1278 | u64 mac_tx_pause_cnt; | |
1279 | u64 mac_tx_ctrl_pkt; | |
1280 | u64 mac_tx_lt_64b_pkts; | |
1281 | u64 mac_tx_lt_127b_pkts; | |
1282 | u64 mac_tx_lt_255b_pkts; | |
1283 | u64 mac_tx_lt_511b_pkts; | |
1284 | u64 mac_tx_lt_1023b_pkts; | |
1285 | u64 mac_tx_lt_1518b_pkts; | |
1286 | u64 mac_tx_gt_1518b_pkts; | |
1287 | u64 rsvd1[3]; | |
1288 | u64 mac_rx_frames; | |
1289 | u64 mac_rx_bytes; | |
1290 | u64 mac_rx_mcast_pkts; | |
1291 | u64 mac_rx_bcast_pkts; | |
1292 | u64 mac_rx_pause_cnt; | |
1293 | u64 mac_rx_ctrl_pkt; | |
1294 | u64 mac_rx_lt_64b_pkts; | |
1295 | u64 mac_rx_lt_127b_pkts; | |
1296 | u64 mac_rx_lt_255b_pkts; | |
1297 | u64 mac_rx_lt_511b_pkts; | |
1298 | u64 mac_rx_lt_1023b_pkts; | |
1299 | u64 mac_rx_lt_1518b_pkts; | |
1300 | u64 mac_rx_gt_1518b_pkts; | |
1301 | u64 rsvd2[3]; | |
1302 | u64 mac_rx_length_error; | |
1303 | u64 mac_rx_length_small; | |
1304 | u64 mac_rx_length_large; | |
1305 | u64 mac_rx_jabber; | |
1306 | u64 mac_rx_dropped; | |
1307 | u64 mac_rx_crc_error; | |
1308 | u64 mac_align_error; | |
1309 | }; | |
1310 | ||
1311 | struct qlcnic_esw_stats_le { | |
b6021212 AKS |
1312 | __le16 context_id; |
1313 | __le16 version; | |
1314 | __le16 size; | |
1315 | __le16 unused; | |
1316 | __le64 unicast_frames; | |
1317 | __le64 multicast_frames; | |
1318 | __le64 broadcast_frames; | |
1319 | __le64 dropped_frames; | |
1320 | __le64 errors; | |
1321 | __le64 local_frames; | |
1322 | __le64 numbytes; | |
1323 | __le64 rsvd[3]; | |
b1fc6d3c | 1324 | } __packed; |
b6021212 | 1325 | |
63507592 SS |
1326 | struct __qlcnic_esw_statistics { |
1327 | u16 context_id; | |
1328 | u16 version; | |
1329 | u16 size; | |
1330 | u16 unused; | |
1331 | u64 unicast_frames; | |
1332 | u64 multicast_frames; | |
1333 | u64 broadcast_frames; | |
1334 | u64 dropped_frames; | |
1335 | u64 errors; | |
1336 | u64 local_frames; | |
1337 | u64 numbytes; | |
1338 | u64 rsvd[3]; | |
1339 | }; | |
1340 | ||
b6021212 AKS |
1341 | struct qlcnic_esw_statistics { |
1342 | struct __qlcnic_esw_statistics rx; | |
1343 | struct __qlcnic_esw_statistics tx; | |
1344 | }; | |
1345 | ||
40522998 | 1346 | #define QLCNIC_DUMP_MASK_DEF 0x1f |
18f2f616 | 1347 | #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed |
9d6a6440 AC |
1348 | #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed |
1349 | #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed | |
3d46512c | 1350 | #define QLCNIC_FORCE_FW_RESET 0xdeaddead |
b43e5ee7 SC |
1351 | #define QLCNIC_SET_QUIESCENT 0xadd00010 |
1352 | #define QLCNIC_RESET_QUIESCENT 0xadd00020 | |
18f2f616 | 1353 | |
7777de9a | 1354 | struct _cdrp_cmd { |
7e2cf4fe SC |
1355 | u32 num; |
1356 | u32 *arg; | |
7777de9a AC |
1357 | }; |
1358 | ||
1359 | struct qlcnic_cmd_args { | |
1360 | struct _cdrp_cmd req; | |
1361 | struct _cdrp_cmd rsp; | |
1362 | }; | |
1363 | ||
18f2f616 | 1364 | int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); |
7e610caa | 1365 | int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); |
af19b491 AKS |
1366 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); |
1367 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
1368 | void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); |
1369 | void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); | |
1370 | ||
1371 | #define ADDR_IN_RANGE(addr, low, high) \ | |
1372 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 AKS |
1373 | |
1374 | #define QLCRD32(adapter, off) \ | |
7e2cf4fe SC |
1375 | (adapter->ahw->hw_ops->read_reg)(adapter, off) |
1376 | ||
af19b491 | 1377 | #define QLCWR32(adapter, off, val) \ |
7e2cf4fe | 1378 | adapter->ahw->hw_ops->write_reg(adapter, off, val) |
af19b491 AKS |
1379 | |
1380 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1381 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1382 | ||
1383 | #define qlcnic_rom_lock(a) \ | |
1384 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1385 | #define qlcnic_rom_unlock(a) \ | |
1386 | qlcnic_pcie_sem_unlock((a), 2) | |
1387 | #define qlcnic_phy_lock(a) \ | |
1388 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1389 | #define qlcnic_phy_unlock(a) \ | |
1390 | qlcnic_pcie_sem_unlock((a), 3) | |
af19b491 AKS |
1391 | #define qlcnic_sw_lock(a) \ |
1392 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1393 | #define qlcnic_sw_unlock(a) \ | |
1394 | qlcnic_pcie_sem_unlock((a), 6) | |
1395 | #define crb_win_lock(a) \ | |
1396 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1397 | #define crb_win_unlock(a) \ | |
1398 | qlcnic_pcie_sem_unlock((a), 7) | |
1399 | ||
728a98b8 SC |
1400 | #define __QLCNIC_MAX_LED_RATE 0xf |
1401 | #define __QLCNIC_MAX_LED_STATE 0x2 | |
1402 | ||
58634e74 SC |
1403 | #define MAX_CTL_CHECK 1000 |
1404 | ||
af19b491 | 1405 | int qlcnic_wol_supported(struct qlcnic_adapter *adapter); |
b5e5492c AKS |
1406 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); |
1407 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); | |
18f2f616 | 1408 | int qlcnic_dump_fw(struct qlcnic_adapter *); |
af19b491 AKS |
1409 | |
1410 | /* Functions from qlcnic_init.c */ | |
13159183 | 1411 | void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); |
af19b491 AKS |
1412 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
1413 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1414 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1415 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1416 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1417 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
8f891387 | 1418 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
af19b491 | 1419 | |
18f2f616 | 1420 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); |
af19b491 AKS |
1421 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, |
1422 | u8 *bytes, size_t size); | |
1423 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1424 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1425 | ||
15087c2b | 1426 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); |
af19b491 AKS |
1427 | |
1428 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1429 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1430 | ||
8a15ad1f AKS |
1431 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); |
1432 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); | |
1433 | ||
1434 | void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); | |
af19b491 AKS |
1435 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); |
1436 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter); | |
1437 | ||
d4066833 | 1438 | int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); |
af19b491 | 1439 | void qlcnic_watchdog_task(struct work_struct *work); |
b1fc6d3c | 1440 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, |
4be41e92 | 1441 | struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); |
af19b491 AKS |
1442 | int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); |
1443 | void qlcnic_set_multi(struct net_device *netdev); | |
fe1adc6b JK |
1444 | int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *); |
1445 | int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *); | |
af19b491 | 1446 | void qlcnic_free_mac_list(struct qlcnic_adapter *adapter); |
af19b491 AKS |
1447 | |
1448 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
c84e340a | 1449 | int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *); |
af19b491 | 1450 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); |
c8f44aff MM |
1451 | netdev_features_t qlcnic_fix_features(struct net_device *netdev, |
1452 | netdev_features_t features); | |
1453 | int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); | |
2e9d722d | 1454 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); |
af19b491 | 1455 | int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); |
5ad6ff9d | 1456 | void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); |
22c8c934 SC |
1457 | |
1458 | /* Functions from qlcnic_ethtool.c */ | |
ba4468db JK |
1459 | int qlcnic_check_loopback_buff(unsigned char *, u8 []); |
1460 | int qlcnic_do_lb_test(struct qlcnic_adapter *, u8); | |
1461 | int qlcnic_loopback_test(struct net_device *, u8); | |
af19b491 AKS |
1462 | |
1463 | /* Functions from qlcnic_main.c */ | |
1464 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
7eb9855d AKS |
1465 | void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); |
1466 | int qlcnic_diag_alloc_res(struct net_device *netdev, int test); | |
cdaff185 | 1467 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); |
319ecf12 SC |
1468 | int qlcnic_set_max_rss(struct qlcnic_adapter *, u8, size_t); |
1469 | int qlcnic_validate_max_rss(u8, u8); | |
e5dcf6dc | 1470 | void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); |
7f966452 | 1471 | int qlcnic_enable_msix(struct qlcnic_adapter *, u32); |
af19b491 | 1472 | |
2e9d722d | 1473 | /* eSwitch management functions */ |
4e8acb01 RB |
1474 | int qlcnic_config_switch_port(struct qlcnic_adapter *, |
1475 | struct qlcnic_esw_func_cfg *); | |
629263ac | 1476 | |
4e8acb01 RB |
1477 | int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, |
1478 | struct qlcnic_esw_func_cfg *); | |
2e9d722d | 1479 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); |
b6021212 AKS |
1480 | int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, |
1481 | struct __qlcnic_esw_statistics *); | |
1482 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, | |
1483 | struct __qlcnic_esw_statistics *); | |
1484 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); | |
54a8997c | 1485 | int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); |
2e9d722d | 1486 | |
7e2cf4fe | 1487 | void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); |
7e2cf4fe | 1488 | |
c70001a9 SC |
1489 | int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); |
1490 | void qlcnic_free_sds_rings(struct qlcnic_recv_context *); | |
7f966452 | 1491 | void qlcnic_advert_link_change(struct qlcnic_adapter *, int); |
c70001a9 SC |
1492 | void qlcnic_free_tx_rings(struct qlcnic_adapter *); |
1493 | int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); | |
1494 | ||
ec079a07 SC |
1495 | void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); |
1496 | void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); | |
1497 | void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter); | |
1498 | void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter); | |
7e2cf4fe SC |
1499 | void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); |
1500 | void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); | |
1501 | ||
ec079a07 SC |
1502 | int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); |
1503 | int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); | |
1504 | void qlcnic_set_vlan_config(struct qlcnic_adapter *, | |
1505 | struct qlcnic_esw_func_cfg *); | |
1506 | void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, | |
1507 | struct qlcnic_esw_func_cfg *); | |
629263ac SC |
1508 | |
1509 | void qlcnic_down(struct qlcnic_adapter *, struct net_device *); | |
1510 | int qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
319ecf12 SC |
1511 | void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); |
1512 | void qlcnic_detach(struct qlcnic_adapter *); | |
1513 | void qlcnic_teardown_intr(struct qlcnic_adapter *); | |
1514 | int qlcnic_attach(struct qlcnic_adapter *); | |
1515 | int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
1516 | void qlcnic_restore_indev_addr(struct net_device *, unsigned long); | |
1517 | ||
629263ac | 1518 | int qlcnic_check_temp(struct qlcnic_adapter *); |
d71170fb SC |
1519 | int qlcnic_init_pci_info(struct qlcnic_adapter *); |
1520 | int qlcnic_set_default_offload_settings(struct qlcnic_adapter *); | |
1521 | int qlcnic_reset_npar_config(struct qlcnic_adapter *); | |
1522 | int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *); | |
53643a75 SS |
1523 | void qlcnic_add_lb_filter(struct qlcnic_adapter *, struct sk_buff *, int, |
1524 | __le16); | |
02feda17 | 1525 | int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); |
f8468331 RB |
1526 | int qlcnic_read_mac_addr(struct qlcnic_adapter *); |
1527 | int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int); | |
1528 | ||
af19b491 AKS |
1529 | /* |
1530 | * QLOGIC Board information | |
1531 | */ | |
1532 | ||
02420be6 | 1533 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
22999798 | 1534 | struct qlcnic_board_info { |
af19b491 AKS |
1535 | unsigned short vendor; |
1536 | unsigned short device; | |
1537 | unsigned short sub_vendor; | |
1538 | unsigned short sub_device; | |
1539 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1540 | }; | |
1541 | ||
af19b491 AKS |
1542 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) |
1543 | { | |
036d61f0 | 1544 | if (likely(tx_ring->producer < tx_ring->sw_consumer)) |
af19b491 AKS |
1545 | return tx_ring->sw_consumer - tx_ring->producer; |
1546 | else | |
1547 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1548 | tx_ring->producer; | |
1549 | } | |
1550 | ||
7e2cf4fe SC |
1551 | struct qlcnic_nic_template { |
1552 | int (*config_bridged_mode) (struct qlcnic_adapter *, u32); | |
1553 | int (*config_led) (struct qlcnic_adapter *, u32, u32); | |
1554 | int (*start_firmware) (struct qlcnic_adapter *); | |
1555 | int (*init_driver) (struct qlcnic_adapter *); | |
1556 | void (*request_reset) (struct qlcnic_adapter *, u32); | |
1557 | void (*cancel_idc_work) (struct qlcnic_adapter *); | |
1558 | int (*napi_add)(struct qlcnic_adapter *, struct net_device *); | |
4be41e92 | 1559 | void (*napi_del)(struct qlcnic_adapter *); |
7e2cf4fe SC |
1560 | void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); |
1561 | irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); | |
1562 | }; | |
1563 | ||
1564 | /* Adapter hardware abstraction */ | |
1565 | struct qlcnic_hardware_ops { | |
1566 | void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
1567 | void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
1568 | int (*read_reg) (struct qlcnic_adapter *, ulong); | |
1569 | int (*write_reg) (struct qlcnic_adapter *, ulong, u32); | |
1570 | void (*get_ocm_win) (struct qlcnic_hardware_context *); | |
1571 | int (*get_mac_address) (struct qlcnic_adapter *, u8 *); | |
1572 | int (*setup_intr) (struct qlcnic_adapter *, u8); | |
1573 | int (*alloc_mbx_args)(struct qlcnic_cmd_args *, | |
1574 | struct qlcnic_adapter *, u32); | |
1575 | int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1576 | void (*get_func_no) (struct qlcnic_adapter *); | |
1577 | int (*api_lock) (struct qlcnic_adapter *); | |
1578 | void (*api_unlock) (struct qlcnic_adapter *); | |
1579 | void (*add_sysfs) (struct qlcnic_adapter *); | |
1580 | void (*remove_sysfs) (struct qlcnic_adapter *); | |
1581 | void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); | |
1582 | int (*create_rx_ctx) (struct qlcnic_adapter *); | |
1583 | int (*create_tx_ctx) (struct qlcnic_adapter *, | |
1584 | struct qlcnic_host_tx_ring *, int); | |
1585 | int (*setup_link_event) (struct qlcnic_adapter *, int); | |
1586 | int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); | |
1587 | int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); | |
1588 | int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); | |
1589 | int (*change_macvlan) (struct qlcnic_adapter *, u8*, __le16, u8); | |
1590 | void (*napi_enable) (struct qlcnic_adapter *); | |
1591 | void (*napi_disable) (struct qlcnic_adapter *); | |
1592 | void (*config_intr_coal) (struct qlcnic_adapter *); | |
1593 | int (*config_rss) (struct qlcnic_adapter *, int); | |
1594 | int (*config_hw_lro) (struct qlcnic_adapter *, int); | |
1595 | int (*config_loopback) (struct qlcnic_adapter *, u8); | |
1596 | int (*clear_loopback) (struct qlcnic_adapter *, u8); | |
1597 | int (*config_promisc_mode) (struct qlcnic_adapter *, u32); | |
1598 | void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, __le16); | |
1599 | int (*get_board_info) (struct qlcnic_adapter *); | |
1600 | }; | |
1601 | ||
1602 | extern struct qlcnic_nic_template qlcnic_vf_ops; | |
1603 | ||
1604 | static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) | |
1605 | { | |
1606 | return adapter->nic_ops->start_firmware(adapter); | |
1607 | } | |
1608 | ||
1609 | static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, | |
1610 | loff_t offset, size_t size) | |
1611 | { | |
1612 | adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); | |
1613 | } | |
1614 | ||
1615 | static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, | |
1616 | loff_t offset, size_t size) | |
1617 | { | |
1618 | adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); | |
1619 | } | |
1620 | ||
7f966452 | 1621 | static inline int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, |
7e2cf4fe SC |
1622 | ulong off) |
1623 | { | |
1624 | return adapter->ahw->hw_ops->read_reg(adapter, off); | |
1625 | } | |
1626 | ||
1627 | static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, | |
1628 | ulong off, u32 data) | |
1629 | { | |
1630 | return adapter->ahw->hw_ops->write_reg(adapter, off, data); | |
1631 | } | |
1632 | ||
1633 | static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, | |
1634 | u8 *mac) | |
1635 | { | |
1636 | return adapter->ahw->hw_ops->get_mac_address(adapter, mac); | |
1637 | } | |
1638 | ||
1639 | static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr) | |
1640 | { | |
1641 | return adapter->ahw->hw_ops->setup_intr(adapter, num_intr); | |
1642 | } | |
1643 | ||
1644 | static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, | |
1645 | struct qlcnic_adapter *adapter, u32 arg) | |
1646 | { | |
1647 | return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); | |
1648 | } | |
1649 | ||
1650 | static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, | |
1651 | struct qlcnic_cmd_args *cmd) | |
1652 | { | |
f8468331 RB |
1653 | if (adapter->ahw->hw_ops->mbx_cmd) |
1654 | return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); | |
1655 | ||
1656 | return -EIO; | |
7e2cf4fe SC |
1657 | } |
1658 | ||
1659 | static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) | |
1660 | { | |
1661 | adapter->ahw->hw_ops->get_func_no(adapter); | |
1662 | } | |
1663 | ||
1664 | static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) | |
1665 | { | |
1666 | return adapter->ahw->hw_ops->api_lock(adapter); | |
1667 | } | |
1668 | ||
1669 | static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) | |
1670 | { | |
1671 | adapter->ahw->hw_ops->api_unlock(adapter); | |
1672 | } | |
1673 | ||
1674 | static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) | |
1675 | { | |
f8468331 RB |
1676 | if (adapter->ahw->hw_ops->add_sysfs) |
1677 | adapter->ahw->hw_ops->add_sysfs(adapter); | |
7e2cf4fe SC |
1678 | } |
1679 | ||
1680 | static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) | |
1681 | { | |
f8468331 RB |
1682 | if (adapter->ahw->hw_ops->remove_sysfs) |
1683 | adapter->ahw->hw_ops->remove_sysfs(adapter); | |
7e2cf4fe SC |
1684 | } |
1685 | ||
1686 | static inline void | |
1687 | qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) | |
1688 | { | |
1689 | sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); | |
1690 | } | |
1691 | ||
1692 | static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) | |
1693 | { | |
1694 | return adapter->ahw->hw_ops->create_rx_ctx(adapter); | |
1695 | } | |
1696 | ||
1697 | static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, | |
1698 | struct qlcnic_host_tx_ring *ptr, | |
1699 | int ring) | |
1700 | { | |
1701 | return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); | |
1702 | } | |
1703 | ||
1704 | static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, | |
1705 | int enable) | |
1706 | { | |
1707 | return adapter->ahw->hw_ops->setup_link_event(adapter, enable); | |
1708 | } | |
1709 | ||
1710 | static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, | |
1711 | struct qlcnic_info *info, u8 id) | |
1712 | { | |
1713 | return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); | |
1714 | } | |
1715 | ||
1716 | static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, | |
1717 | struct qlcnic_pci_info *info) | |
1718 | { | |
1719 | return adapter->ahw->hw_ops->get_pci_info(adapter, info); | |
1720 | } | |
1721 | ||
1722 | static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, | |
1723 | struct qlcnic_info *info) | |
1724 | { | |
1725 | return adapter->ahw->hw_ops->set_nic_info(adapter, info); | |
1726 | } | |
1727 | ||
1728 | static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, | |
1729 | u8 *addr, __le16 id, u8 cmd) | |
1730 | { | |
1731 | return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); | |
1732 | } | |
1733 | ||
1734 | static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, | |
1735 | struct net_device *netdev) | |
1736 | { | |
1737 | return adapter->nic_ops->napi_add(adapter, netdev); | |
1738 | } | |
1739 | ||
4be41e92 SC |
1740 | static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) |
1741 | { | |
1742 | adapter->nic_ops->napi_del(adapter); | |
1743 | } | |
1744 | ||
7e2cf4fe SC |
1745 | static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) |
1746 | { | |
1747 | adapter->ahw->hw_ops->napi_enable(adapter); | |
1748 | } | |
1749 | ||
1750 | static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) | |
1751 | { | |
1752 | adapter->ahw->hw_ops->napi_disable(adapter); | |
1753 | } | |
1754 | ||
1755 | static inline void qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter) | |
1756 | { | |
1757 | adapter->ahw->hw_ops->config_intr_coal(adapter); | |
1758 | } | |
1759 | ||
1760 | static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) | |
1761 | { | |
1762 | return adapter->ahw->hw_ops->config_rss(adapter, enable); | |
1763 | } | |
1764 | ||
1765 | static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, | |
1766 | int enable) | |
1767 | { | |
1768 | return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); | |
1769 | } | |
1770 | ||
1771 | static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1772 | { | |
1773 | return adapter->ahw->hw_ops->config_loopback(adapter, mode); | |
1774 | } | |
1775 | ||
1776 | static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1777 | { | |
d09529e6 | 1778 | return adapter->ahw->hw_ops->clear_loopback(adapter, mode); |
7e2cf4fe SC |
1779 | } |
1780 | ||
1781 | static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, | |
1782 | u32 mode) | |
1783 | { | |
1784 | return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); | |
1785 | } | |
1786 | ||
1787 | static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, | |
1788 | u64 *addr, __le16 id) | |
1789 | { | |
1790 | adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); | |
1791 | } | |
1792 | ||
1793 | static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) | |
1794 | { | |
1795 | return adapter->ahw->hw_ops->get_board_info(adapter); | |
1796 | } | |
1797 | ||
1798 | static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, | |
1799 | u32 key) | |
1800 | { | |
f8468331 RB |
1801 | if (adapter->nic_ops->request_reset) |
1802 | adapter->nic_ops->request_reset(adapter, key); | |
7e2cf4fe SC |
1803 | } |
1804 | ||
1805 | static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) | |
1806 | { | |
f8468331 RB |
1807 | if (adapter->nic_ops->cancel_idc_work) |
1808 | adapter->nic_ops->cancel_idc_work(adapter); | |
7e2cf4fe SC |
1809 | } |
1810 | ||
1811 | static inline irqreturn_t | |
1812 | qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) | |
1813 | { | |
1814 | return adapter->nic_ops->clear_legacy_intr(adapter); | |
1815 | } | |
1816 | ||
1817 | static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, | |
1818 | u32 rate) | |
1819 | { | |
1820 | return adapter->nic_ops->config_led(adapter, state, rate); | |
1821 | } | |
1822 | ||
1823 | static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, | |
1824 | __be32 ip, int cmd) | |
1825 | { | |
1826 | adapter->nic_ops->config_ipaddr(adapter, ip, cmd); | |
1827 | } | |
1828 | ||
c70001a9 SC |
1829 | static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring) |
1830 | { | |
1831 | writel(0, sds_ring->crb_intr_mask); | |
1832 | } | |
1833 | ||
1834 | static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring) | |
1835 | { | |
1836 | struct qlcnic_adapter *adapter = sds_ring->adapter; | |
1837 | ||
1838 | writel(0x1, sds_ring->crb_intr_mask); | |
1839 | ||
1840 | if (!QLCNIC_IS_MSI_FAMILY(adapter)) | |
1841 | writel(0xfbff, adapter->tgt_mask_reg); | |
1842 | } | |
1843 | ||
af19b491 | 1844 | extern const struct ethtool_ops qlcnic_ethtool_ops; |
b43e5ee7 | 1845 | extern const struct ethtool_ops qlcnic_ethtool_failed_ops; |
af19b491 | 1846 | |
65b5b420 | 1847 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
79788450 | 1848 | if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ |
65b5b420 AKS |
1849 | printk(KERN_INFO "%s: %s: " _fmt, \ |
1850 | dev_name(&adapter->pdev->dev), \ | |
1851 | __func__, ##_args); \ | |
1852 | } while (0) | |
1853 | ||
7f966452 | 1854 | #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 |
f8468331 | 1855 | #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430 |
97ee45eb | 1856 | #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 |
f8468331 | 1857 | |
97ee45eb SC |
1858 | static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) |
1859 | { | |
1860 | unsigned short device = adapter->pdev->device; | |
1861 | return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; | |
1862 | } | |
1863 | ||
7f966452 SC |
1864 | static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) |
1865 | { | |
1866 | unsigned short device = adapter->pdev->device; | |
f8468331 RB |
1867 | bool status; |
1868 | ||
1869 | status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) || | |
1870 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false; | |
1871 | ||
1872 | return status; | |
7f966452 SC |
1873 | } |
1874 | ||
02feda17 RB |
1875 | static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter) |
1876 | { | |
1877 | return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false; | |
1878 | } | |
7f966452 | 1879 | |
f8468331 RB |
1880 | static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter) |
1881 | { | |
1882 | unsigned short device = adapter->pdev->device; | |
1883 | ||
1884 | return (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ? true : false; | |
1885 | } | |
af19b491 | 1886 | #endif /* __QLCNIC_H_ */ |