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qlcnic: Free up memory in error path.
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_ctx.c
CommitLineData
af19b491 1/*
40839129 2 * QLogic qlcnic NIC Driver
577ae39d 3 * Copyright (c) 2009-2013 QLogic Corporation
af19b491 4 *
40839129 5 * See LICENSE.qlcnic for copyright and licensing details.
af19b491
AKS		 6 */
7
8#include "qlcnic.h"
9
7e2cf4fe
SC		 10static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
11 {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
12 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
13 {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
14 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
15 {QLCNIC_CMD_INTRPT_TEST, 4, 1},
16 {QLCNIC_CMD_SET_MTU, 4, 1},
17 {QLCNIC_CMD_READ_PHY, 4, 2},
18 {QLCNIC_CMD_WRITE_PHY, 5, 1},
19 {QLCNIC_CMD_READ_HW_REG, 4, 1},
20 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
21 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
22 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
23 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
24 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
25 {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
26 {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
27 {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
28 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
29 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
30 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
31 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
32 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
33 {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
34 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
35 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
36 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
37 {QLCNIC_CMD_TEMP_SIZE, 4, 4},
38 {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
8af3f33d 39 {QLCNIC_CMD_82XX_SET_DRV_VER, 4, 1},
487042af 40 {QLCNIC_CMD_GET_LED_STATUS, 4, 2},
7e2cf4fe
SC		 41};
42
43static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
44{
45 return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
46 (0xcafe << 16);
47}
48
49/* Allocate mailbox registers */
50int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
51 struct qlcnic_adapter *adapter, u32 type)
52{
53 int i, size;
54 const struct qlcnic_mailbox_metadata *mbx_tbl;
55
56 mbx_tbl = qlcnic_mbx_tbl;
57 size = ARRAY_SIZE(qlcnic_mbx_tbl);
58 for (i = 0; i < size; i++) {
59 if (type == mbx_tbl[i].cmd) {
60 mbx->req.num = mbx_tbl[i].in_args;
61 mbx->rsp.num = mbx_tbl[i].out_args;
62 mbx->req.arg = kcalloc(mbx->req.num,
63 sizeof(u32), GFP_ATOMIC);
64 if (!mbx->req.arg)
65 return -ENOMEM;
66 mbx->rsp.arg = kcalloc(mbx->rsp.num,
67 sizeof(u32), GFP_ATOMIC);
68 if (!mbx->rsp.arg) {
69 kfree(mbx->req.arg);
70 mbx->req.arg = NULL;
71 return -ENOMEM;
72 }
73 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
74 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
75 mbx->req.arg[0] = type;
76 break;
77 }
78 }
79 return 0;
80}
81
82/* Free up mailbox registers */
83void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
84{
85 kfree(cmd->req.arg);
86 cmd->req.arg = NULL;
87 kfree(cmd->rsp.arg);
88 cmd->rsp.arg = NULL;
89}
90
bff57d8e
SC		 91static int qlcnic_is_valid_nic_func(struct qlcnic_adapter *adapter, u8 pci_func)
92{
93 int i;
94
95 for (i = 0; i < adapter->ahw->act_pci_func; i++) {
96 if (adapter->npars[i].pci_func == pci_func)
97 return i;
98 }
99
100 return -1;
101}
102
af19b491
AKS		 103static u32
104qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
105{
106 u32 rsp;
107 int timeout = 0;
108
109 do {
110 /* give atleast 1ms for firmware to respond */
68b3f28c 111 mdelay(1);
af19b491
AKS		 112
113 if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
114 return QLCNIC_CDRP_RSP_TIMEOUT;
115
116 rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET);
117 } while (!QLCNIC_CDRP_IS_RSP(rsp));
118
119 return rsp;
120}
121
7e2cf4fe
SC		 122int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
123 struct qlcnic_cmd_args *cmd)
af19b491 124{
7e2cf4fe 125 int i;
af19b491
AKS		 126 u32 rsp;
127 u32 signature;
af19b491 128 struct pci_dev *pdev = adapter->pdev;
7777de9a 129 struct qlcnic_hardware_context *ahw = adapter->ahw;
114ef38a 130 const char *fmt;
af19b491 131
7e2cf4fe 132 signature = qlcnic_get_cmd_signature(ahw);
af19b491
AKS		 133
134 /* Acquire semaphore before accessing CRB */
7777de9a 135 if (qlcnic_api_lock(adapter)) {
7e2cf4fe
SC		 136 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
137 return cmd->rsp.arg[0];
7777de9a 138 }
af19b491
AKS		 139
140 QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
7e2cf4fe
SC		 141 for (i = 1; i < QLCNIC_CDRP_MAX_ARGS; i++)
142 QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
7777de9a 143 QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
7e2cf4fe 144 QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
af19b491
AKS		 145 rsp = qlcnic_poll_rsp(adapter);
146
147 if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
7e2cf4fe
SC		 148 dev_err(&pdev->dev, "card response timeout.\n");
149 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
af19b491 150 } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
7e2cf4fe 151 cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1));
114ef38a
JK		 152 switch (cmd->rsp.arg[0]) {
153 case QLCNIC_RCODE_INVALID_ARGS:
154 fmt = "CDRP invalid args: [%d]\n";
155 break;
156 case QLCNIC_RCODE_NOT_SUPPORTED:
157 case QLCNIC_RCODE_NOT_IMPL:
158 fmt = "CDRP command not supported: [%d]\n";
159 break;
160 case QLCNIC_RCODE_NOT_PERMITTED:
161 fmt = "CDRP requested action not permitted: [%d]\n";
162 break;
163 case QLCNIC_RCODE_INVALID:
164 fmt = "CDRP invalid or unknown cmd received: [%d]\n";
165 break;
166 case QLCNIC_RCODE_TIMEOUT:
167 fmt = "CDRP command timeout: [%d]\n";
168 break;
169 default:
170 fmt = "CDRP command failed: [%d]\n";
171 break;
172 }
173 dev_err(&pdev->dev, fmt, cmd->rsp.arg[0]);
7e2cf4fe
SC		 174 } else if (rsp == QLCNIC_CDRP_RSP_OK)
175 cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
176
177 for (i = 1; i < cmd->rsp.num; i++)
178 cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i));
af19b491
AKS		 179
180 /* Release semaphore */
181 qlcnic_api_unlock(adapter);
7e2cf4fe 182 return cmd->rsp.arg[0];
18f2f616
AC		 183}
184
8af3f33d 185int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *adapter, u32 fw_cmd)
c84e340a
SV		 186{
187 struct qlcnic_cmd_args cmd;
188 u32 arg1, arg2, arg3;
189 char drv_string[12];
190 int err = 0;
191
192 memset(drv_string, 0, sizeof(drv_string));
193 snprintf(drv_string, sizeof(drv_string), "%d"".""%d"".""%d",
194 _QLCNIC_LINUX_MAJOR, _QLCNIC_LINUX_MINOR,
195 _QLCNIC_LINUX_SUBVERSION);
196
8af3f33d 197 err = qlcnic_alloc_mbx_args(&cmd, adapter, fw_cmd);
b6b4316c
SS		 198 if (err)
199 return err;
200
c84e340a
SV		 201 memcpy(&arg1, drv_string, sizeof(u32));
202 memcpy(&arg2, drv_string + 4, sizeof(u32));
203 memcpy(&arg3, drv_string + 8, sizeof(u32));
204
205 cmd.req.arg[1] = arg1;
206 cmd.req.arg[2] = arg2;
207 cmd.req.arg[3] = arg3;
208
209 err = qlcnic_issue_cmd(adapter, &cmd);
210 if (err) {
211 dev_info(&adapter->pdev->dev,
212 "Failed to set driver version in firmware\n");
f91bbcb0 213 err = -EIO;
c84e340a 214 }
f91bbcb0
HM		 215 qlcnic_free_mbx_args(&cmd);
216 return err;
c84e340a
SV		 217}
218
af19b491
AKS		 219int
220qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
221{
7e2cf4fe 222 int err = 0;
7777de9a 223 struct qlcnic_cmd_args cmd;
b1fc6d3c 224 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
af19b491 225
7e2cf4fe
SC		 226 if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
227 return err;
b6b4316c
SS		 228 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
229 if (err)
230 return err;
231
7e2cf4fe
SC		 232 cmd.req.arg[1] = recv_ctx->context_id;
233 cmd.req.arg[2] = mtu;
af19b491 234
7e2cf4fe
SC		 235 err = qlcnic_issue_cmd(adapter, &cmd);
236 if (err) {
237 dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
238 err = -EIO;
239 }
240 qlcnic_free_mbx_args(&cmd);
241 return err;
af19b491
AKS		 242}
243
7e2cf4fe 244int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
af19b491
AKS		 245{
246 void *addr;
247 struct qlcnic_hostrq_rx_ctx *prq;
248 struct qlcnic_cardrsp_rx_ctx *prsp;
249 struct qlcnic_hostrq_rds_ring *prq_rds;
250 struct qlcnic_hostrq_sds_ring *prq_sds;
251 struct qlcnic_cardrsp_rds_ring *prsp_rds;
252 struct qlcnic_cardrsp_sds_ring *prsp_sds;
253 struct qlcnic_host_rds_ring *rds_ring;
254 struct qlcnic_host_sds_ring *sds_ring;
7777de9a 255 struct qlcnic_cmd_args cmd;
af19b491
AKS		 256
257 dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
258 u64 phys_addr;
259
b1fc6d3c 260 u8 i, nrds_rings, nsds_rings;
7e2cf4fe 261 u16 temp_u16;
af19b491 262 size_t rq_size, rsp_size;
2e9d722d 263 u32 cap, reg, val, reg2;
af19b491
AKS		 264 int err;
265
b1fc6d3c 266 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
af19b491
AKS		 267
268 nrds_rings = adapter->max_rds_rings;
269 nsds_rings = adapter->max_sds_rings;
270
271 rq_size =
272 SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
273 nsds_rings);
274 rsp_size =
275 SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
276 nsds_rings);
277
b1fc6d3c
AC		 278 addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
279 &hostrq_phys_addr, GFP_KERNEL);
af19b491
AKS		 280 if (addr == NULL)
281 return -ENOMEM;
43d620c8 282 prq = addr;
af19b491 283
b1fc6d3c
AC		 284 addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
285 &cardrsp_phys_addr, GFP_KERNEL);
af19b491
AKS		 286 if (addr == NULL) {
287 err = -ENOMEM;
288 goto out_free_rq;
289 }
43d620c8 290 prsp = addr;
af19b491
AKS		 291
292 prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
293
8f891387 294 cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
295 | QLCNIC_CAP0_VALIDOFF);
af19b491
AKS		 296 cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
297
7e2cf4fe
SC		 298 temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
299 prq->valid_field_offset = cpu_to_le16(temp_u16);
8f891387 300 prq->txrx_sds_binding = nsds_rings - 1;
301
af19b491
AKS		 302 prq->capabilities[0] = cpu_to_le32(cap);
303 prq->host_int_crb_mode =
304 cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
305 prq->host_rds_crb_mode =
306 cpu_to_le32(QLCNIC_HOST_RDS_CRB_MODE_UNIQUE);
307
308 prq->num_rds_rings = cpu_to_le16(nrds_rings);
309 prq->num_sds_rings = cpu_to_le16(nsds_rings);
b1fc6d3c 310 prq->rds_ring_offset = 0;
af19b491
AKS		 311
312 val = le32_to_cpu(prq->rds_ring_offset) +
313 (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
314 prq->sds_ring_offset = cpu_to_le32(val);
315
316 prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
317 le32_to_cpu(prq->rds_ring_offset));
318
319 for (i = 0; i < nrds_rings; i++) {
320
321 rds_ring = &recv_ctx->rds_rings[i];
8a15ad1f 322 rds_ring->producer = 0;
af19b491
AKS		 323
324 prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
325 prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
326 prq_rds[i].ring_kind = cpu_to_le32(i);
327 prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
328 }
329
330 prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
331 le32_to_cpu(prq->sds_ring_offset));
332
333 for (i = 0; i < nsds_rings; i++) {
334
335 sds_ring = &recv_ctx->sds_rings[i];
8a15ad1f
AKS		 336 sds_ring->consumer = 0;
337 memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
af19b491
AKS		 338
339 prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
340 prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
341 prq_sds[i].msi_index = cpu_to_le16(i);
342 }
343
344 phys_addr = hostrq_phys_addr;
b6b4316c
SS		 345 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
346 if (err)
347 goto out_free_rsp;
348
7e2cf4fe
SC		 349 cmd.req.arg[1] = MSD(phys_addr);
350 cmd.req.arg[2] = LSD(phys_addr);
351 cmd.req.arg[3] = rq_size;
352 err = qlcnic_issue_cmd(adapter, &cmd);
af19b491
AKS		 353 if (err) {
354 dev_err(&adapter->pdev->dev,
355 "Failed to create rx ctx in firmware%d\n", err);
356 goto out_free_rsp;
357 }
358
af19b491
AKS		 359 prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
360 &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
361
362 for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
363 rds_ring = &recv_ctx->rds_rings[i];
364
365 reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
b1fc6d3c 366 rds_ring->crb_rcv_producer = adapter->ahw->pci_base0 + reg;
af19b491
AKS		 367 }
368
369 prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
370 &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
371
372 for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
373 sds_ring = &recv_ctx->sds_rings[i];
374
375 reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
2e9d722d 376 reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
af19b491 377
b1fc6d3c
AC		 378 sds_ring->crb_sts_consumer = adapter->ahw->pci_base0 + reg;
379 sds_ring->crb_intr_mask = adapter->ahw->pci_base0 + reg2;
af19b491
AKS		 380 }
381
382 recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
383 recv_ctx->context_id = le16_to_cpu(prsp->context_id);
384 recv_ctx->virt_port = prsp->virt_port;
385
b6b4316c 386 qlcnic_free_mbx_args(&cmd);
af19b491 387out_free_rsp:
b1fc6d3c 388 dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
b6b4316c 389 cardrsp_phys_addr);
af19b491 390out_free_rq:
b1fc6d3c 391 dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
af19b491
AKS		 392 return err;
393}
394
7cb03b23 395void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
af19b491 396{
7e2cf4fe 397 int err;
7777de9a 398 struct qlcnic_cmd_args cmd;
b1fc6d3c 399 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
af19b491 400
b6b4316c
SS		 401 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
402 if (err)
403 return;
404
7e2cf4fe
SC		 405 cmd.req.arg[1] = recv_ctx->context_id;
406 err = qlcnic_issue_cmd(adapter, &cmd);
407 if (err)
af19b491
AKS		 408 dev_err(&adapter->pdev->dev,
409 "Failed to destroy rx ctx in firmware\n");
d626ad4d
AKS		 410
411 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
7e2cf4fe 412 qlcnic_free_mbx_args(&cmd);
af19b491
AKS		 413}
414
7e2cf4fe
SC		 415int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
416 struct qlcnic_host_tx_ring *tx_ring,
417 int ring)
af19b491
AKS		 418{
419 struct qlcnic_hostrq_tx_ctx *prq;
420 struct qlcnic_hostrq_cds_ring *prq_cds;
421 struct qlcnic_cardrsp_tx_ctx *prsp;
422 void *rq_addr, *rsp_addr;
423 size_t rq_size, rsp_size;
424 u32 temp;
7777de9a 425 struct qlcnic_cmd_args cmd;
af19b491
AKS		 426 int err;
427 u64 phys_addr;
428 dma_addr_t rq_phys_addr, rsp_phys_addr;
af19b491 429
8a15ad1f
AKS		 430 /* reset host resources */
431 tx_ring->producer = 0;
432 tx_ring->sw_consumer = 0;
433 *(tx_ring->hw_consumer) = 0;
434
af19b491 435 rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
b1fc6d3c 436 rq_addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
1f9061d2 437 &rq_phys_addr, GFP_KERNEL | __GFP_ZERO);
af19b491
AKS		 438 if (!rq_addr)
439 return -ENOMEM;
440
441 rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
b1fc6d3c 442 rsp_addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
1f9061d2 443 &rsp_phys_addr, GFP_KERNEL | __GFP_ZERO);
af19b491
AKS		 444 if (!rsp_addr) {
445 err = -ENOMEM;
446 goto out_free_rq;
447 }
448
43d620c8 449 prq = rq_addr;
af19b491 450
43d620c8 451 prsp = rsp_addr;
af19b491
AKS		 452
453 prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
454
455 temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
456 QLCNIC_CAP0_LSO);
457 prq->capabilities[0] = cpu_to_le32(temp);
458
459 prq->host_int_crb_mode =
460 cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
7e2cf4fe 461 prq->msi_index = 0;
af19b491
AKS		 462
463 prq->interrupt_ctl = 0;
af19b491
AKS		 464 prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
465
466 prq_cds = &prq->cds_ring;
467
468 prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
469 prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
470
471 phys_addr = rq_phys_addr;
7e2cf4fe 472
b6b4316c
SS		 473 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
474 if (err)
475 goto out_free_rsp;
476
7e2cf4fe
SC		 477 cmd.req.arg[1] = MSD(phys_addr);
478 cmd.req.arg[2] = LSD(phys_addr);
479 cmd.req.arg[3] = rq_size;
480 err = qlcnic_issue_cmd(adapter, &cmd);
af19b491
AKS		 481
482 if (err == QLCNIC_RCODE_SUCCESS) {
483 temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
b1fc6d3c 484 tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
7e2cf4fe 485 tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
af19b491
AKS		 486 } else {
487 dev_err(&adapter->pdev->dev,
488 "Failed to create tx ctx in firmware%d\n", err);
489 err = -EIO;
490 }
491
b6b4316c
SS		 492 qlcnic_free_mbx_args(&cmd);
493
494out_free_rsp:
b1fc6d3c 495 dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
7e2cf4fe 496 rsp_phys_addr);
af19b491 497out_free_rq:
b1fc6d3c 498 dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
af19b491
AKS		 499
500 return err;
501}
502
7cb03b23
RB		 503void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
504 struct qlcnic_host_tx_ring *tx_ring)
af19b491 505{
7777de9a 506 struct qlcnic_cmd_args cmd;
b6b4316c 507 int ret;
7777de9a 508
b6b4316c
SS		 509 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
510 if (ret)
511 return;
7cb03b23 512
7e2cf4fe
SC		 513 cmd.req.arg[1] = tx_ring->ctx_id;
514 if (qlcnic_issue_cmd(adapter, &cmd))
af19b491
AKS		 515 dev_err(&adapter->pdev->dev,
516 "Failed to destroy tx ctx in firmware\n");
7e2cf4fe 517 qlcnic_free_mbx_args(&cmd);
af19b491
AKS		 518}
519
520int
7e610caa 521qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
af19b491 522{
7e2cf4fe 523 int err;
7777de9a
AC		 524 struct qlcnic_cmd_args cmd;
525
b6b4316c
SS		 526 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
527 if (err)
528 return err;
529
7e2cf4fe
SC		 530 cmd.req.arg[1] = config;
531 err = qlcnic_issue_cmd(adapter, &cmd);
532 qlcnic_free_mbx_args(&cmd);
533 return err;
af19b491
AKS		 534}
535
536int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
537{
538 void *addr;
4be41e92 539 int err, ring;
af19b491
AKS		 540 struct qlcnic_recv_context *recv_ctx;
541 struct qlcnic_host_rds_ring *rds_ring;
542 struct qlcnic_host_sds_ring *sds_ring;
543 struct qlcnic_host_tx_ring *tx_ring;
4be41e92 544 __le32 *ptr;
af19b491
AKS		 545
546 struct pci_dev *pdev = adapter->pdev;
547
b1fc6d3c 548 recv_ctx = adapter->recv_ctx;
af19b491 549
4be41e92
SC		 550 for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
551 tx_ring = &adapter->tx_ring[ring];
552 ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
553 &tx_ring->hw_cons_phys_addr,
554 GFP_KERNEL);
d0320f75 555 if (ptr == NULL)
4be41e92 556 return -ENOMEM;
d0320f75 557
4be41e92
SC		 558 tx_ring->hw_consumer = ptr;
559 /* cmd desc ring */
560 addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
561 &tx_ring->phys_addr,
562 GFP_KERNEL);
4be41e92 563 if (addr == NULL) {
4be41e92
SC		 564 err = -ENOMEM;
565 goto err_out_free;
566 }
af19b491 567
4be41e92
SC		 568 tx_ring->desc_head = addr;
569 }
af19b491
AKS		 570
571 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
572 rds_ring = &recv_ctx->rds_rings[ring];
b1fc6d3c 573 addr = dma_alloc_coherent(&adapter->pdev->dev,
d0320f75
JP		 574 RCV_DESC_RINGSIZE(rds_ring),
575 &rds_ring->phys_addr, GFP_KERNEL);
af19b491 576 if (addr == NULL) {
af19b491
AKS		 577 err = -ENOMEM;
578 goto err_out_free;
579 }
43d620c8 580 rds_ring->desc_head = addr;
af19b491
AKS		 581
582 }
583
584 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
585 sds_ring = &recv_ctx->sds_rings[ring];
586
b1fc6d3c 587 addr = dma_alloc_coherent(&adapter->pdev->dev,
d0320f75
JP		 588 STATUS_DESC_RINGSIZE(sds_ring),
589 &sds_ring->phys_addr, GFP_KERNEL);
af19b491 590 if (addr == NULL) {
af19b491
AKS		 591 err = -ENOMEM;
592 goto err_out_free;
593 }
43d620c8 594 sds_ring->desc_head = addr;
af19b491
AKS		 595 }
596
af19b491
AKS		 597 return 0;
598
599err_out_free:
600 qlcnic_free_hw_resources(adapter);
601 return err;
602}
603
7e2cf4fe 604int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
af19b491 605{
7e2cf4fe 606 int i, err, ring;
8a15ad1f 607
7e2cf4fe
SC		 608 if (dev->flags & QLCNIC_NEED_FLR) {
609 pci_reset_function(dev->pdev);
610 dev->flags &= ~QLCNIC_NEED_FLR;
b0044bcf 611 }
c21fd48c 612
7dd90cf1
SC		 613 if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
614 if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST) {
615 err = qlcnic_83xx_config_intrpt(dev, 1);
616 if (err)
617 return err;
618 }
619 }
620
7e2cf4fe 621 err = qlcnic_fw_cmd_create_rx_ctx(dev);
8a15ad1f 622 if (err)
7dd90cf1 623 goto err_out;
8a15ad1f 624
7e2cf4fe
SC		 625 for (ring = 0; ring < dev->max_drv_tx_rings; ring++) {
626 err = qlcnic_fw_cmd_create_tx_ctx(dev,
627 &dev->tx_ring[ring],
628 ring);
629 if (err) {
7cb03b23 630 qlcnic_fw_cmd_del_rx_ctx(dev);
7e2cf4fe 631 if (ring == 0)
7dd90cf1 632 goto err_out;
7e2cf4fe
SC		 633
634 for (i = 0; i < ring; i++)
7cb03b23 635 qlcnic_fw_cmd_del_tx_ctx(dev, &dev->tx_ring[i]);
7e2cf4fe 636
7dd90cf1 637 goto err_out;
7e2cf4fe 638 }
8a15ad1f 639 }
af19b491 640
7e2cf4fe 641 set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
8a15ad1f 642 return 0;
7dd90cf1
SC		 643
644err_out:
645 if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
646 if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
647 qlcnic_83xx_config_intrpt(dev, 0);
648 }
649 return err;
8a15ad1f 650}
af19b491 651
8a15ad1f
AKS		 652void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
653{
7e2cf4fe
SC		 654 int ring;
655
af19b491 656 if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
7cb03b23 657 qlcnic_fw_cmd_del_rx_ctx(adapter);
7e2cf4fe 658 for (ring = 0; ring < adapter->max_drv_tx_rings; ring++)
7cb03b23
RB		 659 qlcnic_fw_cmd_del_tx_ctx(adapter,
660 &adapter->tx_ring[ring]);
7dd90cf1
SC		 661
662 if (qlcnic_83xx_check(adapter) &&
663 (adapter->flags & QLCNIC_MSIX_ENABLED)) {
664 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
665 qlcnic_83xx_config_intrpt(adapter, 0);
666 }
af19b491 667 /* Allow dma queues to drain after context reset */
f57da7a6 668 mdelay(20);
af19b491 669 }
8a15ad1f
AKS		 670}
671
672void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
673{
674 struct qlcnic_recv_context *recv_ctx;
675 struct qlcnic_host_rds_ring *rds_ring;
676 struct qlcnic_host_sds_ring *sds_ring;
677 struct qlcnic_host_tx_ring *tx_ring;
678 int ring;
af19b491 679
b1fc6d3c 680 recv_ctx = adapter->recv_ctx;
af19b491 681
4be41e92
SC		 682 for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
683 tx_ring = &adapter->tx_ring[ring];
684 if (tx_ring->hw_consumer != NULL) {
685 dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
686 tx_ring->hw_consumer,
687 tx_ring->hw_cons_phys_addr);
af19b491 688
4be41e92
SC		 689 tx_ring->hw_consumer = NULL;
690 }
691
692 if (tx_ring->desc_head != NULL) {
693 dma_free_coherent(&adapter->pdev->dev,
694 TX_DESC_RINGSIZE(tx_ring),
695 tx_ring->desc_head,
696 tx_ring->phys_addr);
697 tx_ring->desc_head = NULL;
698 }
af19b491
AKS		 699 }
700
701 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
702 rds_ring = &recv_ctx->rds_rings[ring];
703
704 if (rds_ring->desc_head != NULL) {
b1fc6d3c 705 dma_free_coherent(&adapter->pdev->dev,
af19b491
AKS		 706 RCV_DESC_RINGSIZE(rds_ring),
707 rds_ring->desc_head,
708 rds_ring->phys_addr);
709 rds_ring->desc_head = NULL;
710 }
711 }
712
713 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
714 sds_ring = &recv_ctx->sds_rings[ring];
715
716 if (sds_ring->desc_head != NULL) {
b1fc6d3c 717 dma_free_coherent(&adapter->pdev->dev,
af19b491
AKS		 718 STATUS_DESC_RINGSIZE(sds_ring),
719 sds_ring->desc_head,
720 sds_ring->phys_addr);
721 sds_ring->desc_head = NULL;
722 }
723 }
724}
725
2e9d722d 726
7e2cf4fe 727int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
2e9d722d 728{
7e2cf4fe 729 int err, i;
7777de9a 730 struct qlcnic_cmd_args cmd;
7e2cf4fe 731 u32 mac_low, mac_high;
7777de9a 732
b6b4316c
SS		 733 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
734 if (err)
735 return err;
736
7e2cf4fe
SC		 737 cmd.req.arg[1] = adapter->ahw->pci_func | BIT_8;
738 err = qlcnic_issue_cmd(adapter, &cmd);
2e9d722d 739
7e2cf4fe
SC		 740 if (err == QLCNIC_RCODE_SUCCESS) {
741 mac_low = cmd.rsp.arg[1];
742 mac_high = cmd.rsp.arg[2];
743
744 for (i = 0; i < 2; i++)
745 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
746 for (i = 2; i < 6; i++)
747 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
748 } else {
2e9d722d
AC		 749 dev_err(&adapter->pdev->dev,
750 "Failed to get mac address%d\n", err);
751 err = -EIO;
752 }
7e2cf4fe 753 qlcnic_free_mbx_args(&cmd);
2e9d722d
AC		 754 return err;
755}
756
757/* Get info of a NIC partition */
7e2cf4fe
SC		 758int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
759 struct qlcnic_info *npar_info, u8 func_id)
2e9d722d
AC		 760{
761 int err;
762 dma_addr_t nic_dma_t;
7e2cf4fe 763 const struct qlcnic_info_le *nic_info;
2e9d722d 764 void *nic_info_addr;
7777de9a 765 struct qlcnic_cmd_args cmd;
7e2cf4fe 766 size_t nic_size = sizeof(struct qlcnic_info_le);
2e9d722d 767
b1fc6d3c 768 nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
1f9061d2 769 &nic_dma_t, GFP_KERNEL | __GFP_ZERO);
2e9d722d
AC		 770 if (!nic_info_addr)
771 return -ENOMEM;
2e9d722d 772
43d620c8 773 nic_info = nic_info_addr;
2e9d722d 774
b6b4316c
SS		 775 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
776 if (err)
777 goto out_free_dma;
778
7e2cf4fe
SC		 779 cmd.req.arg[1] = MSD(nic_dma_t);
780 cmd.req.arg[2] = LSD(nic_dma_t);
781 cmd.req.arg[3] = (func_id << 16 | nic_size);
782 err = qlcnic_issue_cmd(adapter, &cmd);
783 if (err != QLCNIC_RCODE_SUCCESS) {
784 dev_err(&adapter->pdev->dev,
785 "Failed to get nic info%d\n", err);
786 err = -EIO;
787 } else {
cea8975e
AC		 788 npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
789 npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
7e2cf4fe
SC		 790 npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
791 npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
346fe763
RB		 792 npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
793 npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
794 npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
795 npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
346fe763
RB		 796 npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
797 npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
2e9d722d
AC		 798 }
799
b6b4316c
SS		 800 qlcnic_free_mbx_args(&cmd);
801out_free_dma:
b1fc6d3c 802 dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
7e2cf4fe 803 nic_dma_t);
7e2cf4fe 804
2e9d722d
AC		 805 return err;
806}
807
808/* Configure a NIC partition */
7e2cf4fe
SC		 809int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
810 struct qlcnic_info *nic)
2e9d722d
AC		 811{
812 int err = -EIO;
2e9d722d
AC		 813 dma_addr_t nic_dma_t;
814 void *nic_info_addr;
7777de9a 815 struct qlcnic_cmd_args cmd;
63507592
SS		 816 struct qlcnic_info_le *nic_info;
817 size_t nic_size = sizeof(struct qlcnic_info_le);
2e9d722d 818
79788450 819 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
2e9d722d
AC		 820 return err;
821
b1fc6d3c 822 nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
1f9061d2 823 &nic_dma_t, GFP_KERNEL | __GFP_ZERO);
2e9d722d
AC		 824 if (!nic_info_addr)
825 return -ENOMEM;
826
43d620c8 827 nic_info = nic_info_addr;
2e9d722d
AC		 828
829 nic_info->pci_func = cpu_to_le16(nic->pci_func);
830 nic_info->op_mode = cpu_to_le16(nic->op_mode);
831 nic_info->phys_port = cpu_to_le16(nic->phys_port);
832 nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
833 nic_info->capabilities = cpu_to_le32(nic->capabilities);
834 nic_info->max_mac_filters = nic->max_mac_filters;
835 nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
836 nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
837 nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
838 nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
839
b6b4316c
SS		 840 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
841 if (err)
842 goto out_free_dma;
843
7e2cf4fe
SC		 844 cmd.req.arg[1] = MSD(nic_dma_t);
845 cmd.req.arg[2] = LSD(nic_dma_t);
846 cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
847 err = qlcnic_issue_cmd(adapter, &cmd);
2e9d722d
AC		 848
849 if (err != QLCNIC_RCODE_SUCCESS) {
850 dev_err(&adapter->pdev->dev,
851 "Failed to set nic info%d\n", err);
852 err = -EIO;
853 }
854
7e2cf4fe 855 qlcnic_free_mbx_args(&cmd);
b6b4316c
SS		 856out_free_dma:
857 dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
858 nic_dma_t);
7e2cf4fe 859
2e9d722d
AC		 860 return err;
861}
862
863/* Get PCI Info of a partition */
7e2cf4fe
SC		 864int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
865 struct qlcnic_pci_info *pci_info)
2e9d722d
AC		 866{
867 int err = 0, i;
7777de9a 868 struct qlcnic_cmd_args cmd;
2e9d722d 869 dma_addr_t pci_info_dma_t;
63507592 870 struct qlcnic_pci_info_le *npar;
2e9d722d 871 void *pci_info_addr;
63507592 872 size_t npar_size = sizeof(struct qlcnic_pci_info_le);
2e9d722d
AC		 873 size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC;
874
b1fc6d3c 875 pci_info_addr = dma_alloc_coherent(&adapter->pdev->dev, pci_size,
1f9061d2
JP		 876 &pci_info_dma_t,
877 GFP_KERNEL | __GFP_ZERO);
2e9d722d
AC		 878 if (!pci_info_addr)
879 return -ENOMEM;
2e9d722d 880
43d620c8 881 npar = pci_info_addr;
b6b4316c
SS		 882 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
883 if (err)
884 goto out_free_dma;
885
7e2cf4fe
SC		 886 cmd.req.arg[1] = MSD(pci_info_dma_t);
887 cmd.req.arg[2] = LSD(pci_info_dma_t);
888 cmd.req.arg[3] = pci_size;
889 err = qlcnic_issue_cmd(adapter, &cmd);
2e9d722d 890
bff57d8e 891 adapter->ahw->act_pci_func = 0;
2e9d722d 892 if (err == QLCNIC_RCODE_SUCCESS) {
346fe763 893 for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++, pci_info++) {
a1c0c459
SC		 894 pci_info->id = le16_to_cpu(npar->id);
895 pci_info->active = le16_to_cpu(npar->active);
896 pci_info->type = le16_to_cpu(npar->type);
bff57d8e
SC		 897 if (pci_info->type == QLCNIC_TYPE_NIC)
898 adapter->ahw->act_pci_func++;
346fe763 899 pci_info->default_port =
a1c0c459 900 le16_to_cpu(npar->default_port);
346fe763 901 pci_info->tx_min_bw =
a1c0c459 902 le16_to_cpu(npar->tx_min_bw);
346fe763 903 pci_info->tx_max_bw =
a1c0c459 904 le16_to_cpu(npar->tx_max_bw);
346fe763 905 memcpy(pci_info->mac, npar->mac, ETH_ALEN);
2e9d722d
AC		 906 }
907 } else {
908 dev_err(&adapter->pdev->dev,
909 "Failed to get PCI Info%d\n", err);
2e9d722d
AC		 910 err = -EIO;
911 }
2e9d722d 912
b6b4316c
SS		 913 qlcnic_free_mbx_args(&cmd);
914out_free_dma:
b1fc6d3c 915 dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
2e9d722d 916 pci_info_dma_t);
7e2cf4fe 917
2e9d722d
AC		 918 return err;
919}
920
2e9d722d
AC		 921/* Configure eSwitch for port mirroring */
922int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
ee9e8b6c 923 u8 enable_mirroring, u8 pci_func)
2e9d722d 924{
ee9e8b6c
MC		 925 struct device *dev = &adapter->pdev->dev;
926 struct qlcnic_cmd_args cmd;
2e9d722d
AC		 927 int err = -EIO;
928 u32 arg1;
929
79788450
SC		 930 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
931 !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE))
2e9d722d
AC		 932 return err;
933
934 arg1 = id | (enable_mirroring ? BIT_4 : 0);
935 arg1 |= pci_func << 8;
936
b6b4316c
SS		 937 err = qlcnic_alloc_mbx_args(&cmd, adapter,
938 QLCNIC_CMD_SET_PORTMIRRORING);
939 if (err)
940 return err;
941
7e2cf4fe
SC		 942 cmd.req.arg[1] = arg1;
943 err = qlcnic_issue_cmd(adapter, &cmd);
2e9d722d 944
7e2cf4fe 945 if (err != QLCNIC_RCODE_SUCCESS)
ee9e8b6c 946 dev_err(dev, "Failed to configure port mirroring for vNIC function %d on eSwitch %d\n",
2e9d722d 947 pci_func, id);
7e2cf4fe 948 else
ee9e8b6c
MC		 949 dev_info(dev, "Configured port mirroring for vNIC function %d on eSwitch %d\n",
950 pci_func, id);
7e2cf4fe 951 qlcnic_free_mbx_args(&cmd);
2e9d722d
AC		 952
953 return err;
954}
955
b6021212
AKS		 956int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
957 const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
958
63507592
SS		 959 size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
960 struct qlcnic_esw_stats_le *stats;
b6021212
AKS		 961 dma_addr_t stats_dma_t;
962 void *stats_addr;
963 u32 arg1;
7777de9a 964 struct qlcnic_cmd_args cmd;
b6021212
AKS		 965 int err;
966
967 if (esw_stats == NULL)
968 return -ENOMEM;
969
79788450
SC		 970 if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
971 (func != adapter->ahw->pci_func)) {
b6021212
AKS		 972 dev_err(&adapter->pdev->dev,
973 "Not privilege to query stats for func=%d", func);
974 return -EIO;
975 }
976
b1fc6d3c 977 stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
1f9061d2 978 &stats_dma_t, GFP_KERNEL | __GFP_ZERO);
d0320f75 979 if (!stats_addr)
b6021212 980 return -ENOMEM;
d0320f75 981
b6021212
AKS		 982 arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
983 arg1 |= rx_tx << 15 | stats_size << 16;
984
b6b4316c
SS		 985 err = qlcnic_alloc_mbx_args(&cmd, adapter,
986 QLCNIC_CMD_GET_ESWITCH_STATS);
987 if (err)
988 goto out_free_dma;
989
7e2cf4fe
SC		 990 cmd.req.arg[1] = arg1;
991 cmd.req.arg[2] = MSD(stats_dma_t);
992 cmd.req.arg[3] = LSD(stats_dma_t);
993 err = qlcnic_issue_cmd(adapter, &cmd);
b6021212 994
63e74e9c 995 if (!err) {
43d620c8 996 stats = stats_addr;
63e74e9c
AKS		 997 esw_stats->context_id = le16_to_cpu(stats->context_id);
998 esw_stats->version = le16_to_cpu(stats->version);
999 esw_stats->size = le16_to_cpu(stats->size);
1000 esw_stats->multicast_frames =
1001 le64_to_cpu(stats->multicast_frames);
1002 esw_stats->broadcast_frames =
1003 le64_to_cpu(stats->broadcast_frames);
1004 esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
1005 esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
1006 esw_stats->local_frames = le64_to_cpu(stats->local_frames);
1007 esw_stats->errors = le64_to_cpu(stats->errors);
1008 esw_stats->numbytes = le64_to_cpu(stats->numbytes);
1009 }
b6021212 1010
7e2cf4fe 1011 qlcnic_free_mbx_args(&cmd);
b6b4316c
SS		 1012out_free_dma:
1013 dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
1014 stats_dma_t);
7e2cf4fe 1015
b6021212
AKS		 1016 return err;
1017}
1018
54a8997c
JK		 1019/* This routine will retrieve the MAC statistics from firmware */
1020int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
1021 struct qlcnic_mac_statistics *mac_stats)
1022{
63507592 1023 struct qlcnic_mac_statistics_le *stats;
54a8997c 1024 struct qlcnic_cmd_args cmd;
63507592 1025 size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
54a8997c
JK		 1026 dma_addr_t stats_dma_t;
1027 void *stats_addr;
1028 int err;
1029
7e2cf4fe
SC		 1030 if (mac_stats == NULL)
1031 return -ENOMEM;
1032
54a8997c 1033 stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
1f9061d2 1034 &stats_dma_t, GFP_KERNEL | __GFP_ZERO);
d0320f75 1035 if (!stats_addr)
54a8997c 1036 return -ENOMEM;
d0320f75 1037
b6b4316c
SS		 1038 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
1039 if (err)
1040 goto out_free_dma;
1041
7e2cf4fe
SC		 1042 cmd.req.arg[1] = stats_size << 16;
1043 cmd.req.arg[2] = MSD(stats_dma_t);
1044 cmd.req.arg[3] = LSD(stats_dma_t);
1045 err = qlcnic_issue_cmd(adapter, &cmd);
54a8997c
JK		 1046 if (!err) {
1047 stats = stats_addr;
1048 mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
1049 mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
1050 mac_stats->mac_tx_mcast_pkts =
1051 le64_to_cpu(stats->mac_tx_mcast_pkts);
1052 mac_stats->mac_tx_bcast_pkts =
1053 le64_to_cpu(stats->mac_tx_bcast_pkts);
1054 mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
1055 mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
1056 mac_stats->mac_rx_mcast_pkts =
1057 le64_to_cpu(stats->mac_rx_mcast_pkts);
1058 mac_stats->mac_rx_length_error =
1059 le64_to_cpu(stats->mac_rx_length_error);
1060 mac_stats->mac_rx_length_small =
1061 le64_to_cpu(stats->mac_rx_length_small);
1062 mac_stats->mac_rx_length_large =
1063 le64_to_cpu(stats->mac_rx_length_large);
1064 mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
1065 mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
1066 mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
7e2cf4fe
SC		 1067 } else {
1068 dev_err(&adapter->pdev->dev,
1069 "%s: Get mac stats failed, err=%d.\n", __func__, err);
54a8997c
JK		 1070 }
1071
7e2cf4fe
SC		 1072 qlcnic_free_mbx_args(&cmd);
1073
b6b4316c
SS		 1074out_free_dma:
1075 dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
1076 stats_dma_t);
1077
54a8997c
JK		 1078 return err;
1079}
1080
b6021212
AKS		 1081int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
1082 const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
1083
1084 struct __qlcnic_esw_statistics port_stats;
1085 u8 i;
1086 int ret = -EIO;
1087
1088 if (esw_stats == NULL)
1089 return -ENOMEM;
79788450 1090 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
b6021212
AKS		 1091 return -EIO;
1092 if (adapter->npars == NULL)
1093 return -EIO;
1094
ef182805 1095 memset(esw_stats, 0, sizeof(u64));
54a8997c
JK		 1096 esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
1097 esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
1098 esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
1099 esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
1100 esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
1101 esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
1102 esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
b6021212
AKS		 1103 esw_stats->context_id = eswitch;
1104
bff57d8e 1105 for (i = 0; i < adapter->ahw->act_pci_func; i++) {
b6021212
AKS		 1106 if (adapter->npars[i].phy_port != eswitch)
1107 continue;
1108
1109 memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
bff57d8e
SC		 1110 if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
1111 rx_tx, &port_stats))
b6021212
AKS		 1112 continue;
1113
1114 esw_stats->size = port_stats.size;
1115 esw_stats->version = port_stats.version;
ef182805
AKS		 1116 QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
1117 port_stats.unicast_frames);
1118 QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
1119 port_stats.multicast_frames);
1120 QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
1121 port_stats.broadcast_frames);
1122 QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
1123 port_stats.dropped_frames);
1124 QLCNIC_ADD_ESW_STATS(esw_stats->errors,
1125 port_stats.errors);
1126 QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
1127 port_stats.local_frames);
1128 QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
1129 port_stats.numbytes);
b6021212
AKS		 1130 ret = 0;
1131 }
1132 return ret;
1133}
1134
1135int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
1136 const u8 port, const u8 rx_tx)
1137{
7e2cf4fe 1138 int err;
b6021212 1139 u32 arg1;
7777de9a 1140 struct qlcnic_cmd_args cmd;
b6021212 1141
79788450 1142 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
b6021212
AKS		 1143 return -EIO;
1144
1145 if (func_esw == QLCNIC_STATS_PORT) {
1146 if (port >= QLCNIC_MAX_PCI_FUNC)
1147 goto err_ret;
1148 } else if (func_esw == QLCNIC_STATS_ESWITCH) {
1149 if (port >= QLCNIC_NIU_MAX_XG_PORTS)
1150 goto err_ret;
1151 } else {
1152 goto err_ret;
1153 }
1154
1155 if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
1156 goto err_ret;
1157
1158 arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
1159 arg1 |= BIT_14 | rx_tx << 15;
1160
b6b4316c
SS		 1161 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1162 QLCNIC_CMD_GET_ESWITCH_STATS);
1163 if (err)
1164 return err;
1165
7e2cf4fe
SC		 1166 cmd.req.arg[1] = arg1;
1167 err = qlcnic_issue_cmd(adapter, &cmd);
1168 qlcnic_free_mbx_args(&cmd);
1169 return err;
b6021212
AKS		 1170
1171err_ret:
7e2cf4fe
SC		 1172 dev_err(&adapter->pdev->dev,
1173 "Invalid args func_esw %d port %d rx_ctx %d\n",
1174 func_esw, port, rx_tx);
b6021212
AKS		 1175 return -EIO;
1176}
4e8acb01 1177
ee9e8b6c
MC		 1178static int __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
1179 u32 *arg1, u32 *arg2)
4e8acb01 1180{
ee9e8b6c 1181 struct device *dev = &adapter->pdev->dev;
7777de9a 1182 struct qlcnic_cmd_args cmd;
ee9e8b6c 1183 u8 pci_func = *arg1 >> 8;
b6b4316c
SS		 1184 int err;
1185
1186 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1187 QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
1188 if (err)
1189 return err;
7777de9a 1190
7e2cf4fe
SC		 1191 cmd.req.arg[1] = *arg1;
1192 err = qlcnic_issue_cmd(adapter, &cmd);
1193 *arg1 = cmd.rsp.arg[1];
1194 *arg2 = cmd.rsp.arg[2];
1195 qlcnic_free_mbx_args(&cmd);
4e8acb01 1196
7e2cf4fe 1197 if (err == QLCNIC_RCODE_SUCCESS)
ee9e8b6c
MC		 1198 dev_info(dev, "Get eSwitch port config for vNIC function %d\n",
1199 pci_func);
7e2cf4fe 1200 else
ee9e8b6c
MC		 1201 dev_err(dev, "Failed to get eswitch port config for vNIC function %d\n",
1202 pci_func);
4e8acb01
RB		 1203 return err;
1204}
1205/* Configure eSwitch port
1206op_mode = 0 for setting default port behavior
1207op_mode = 1 for setting vlan id
1208op_mode = 2 for deleting vlan id
1209op_type = 0 for vlan_id
1210op_type = 1 for port vlan_id
1211*/
1212int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
1213 struct qlcnic_esw_func_cfg *esw_cfg)
1214{
ee9e8b6c
MC		 1215 struct device *dev = &adapter->pdev->dev;
1216 struct qlcnic_cmd_args cmd;
bff57d8e 1217 int err = -EIO, index;
4e8acb01
RB		 1218 u32 arg1, arg2 = 0;
1219 u8 pci_func;
1220
79788450 1221 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
4e8acb01
RB		 1222 return err;
1223 pci_func = esw_cfg->pci_func;
bff57d8e
SC		 1224 index = qlcnic_is_valid_nic_func(adapter, pci_func);
1225 if (index < 0)
1226 return err;
1227 arg1 = (adapter->npars[index].phy_port & BIT_0);
4e8acb01
RB		 1228 arg1 |= (pci_func << 8);
1229
1230 if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
1231 return err;
1232 arg1 &= ~(0x0ff << 8);
1233 arg1 |= (pci_func << 8);
1234 arg1 &= ~(BIT_2 | BIT_3);
1235 switch (esw_cfg->op_mode) {
1236 case QLCNIC_PORT_DEFAULTS:
1237 arg1 |= (BIT_4 | BIT_6 | BIT_7);
1238 arg2 |= (BIT_0 | BIT_1);
79788450 1239 if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
4e8acb01
RB		 1240 arg2 |= (BIT_2 | BIT_3);
1241 if (!(esw_cfg->discard_tagged))
1242 arg1 &= ~BIT_4;
1243 if (!(esw_cfg->promisc_mode))
1244 arg1 &= ~BIT_6;
7373373d 1245 if (!(esw_cfg->mac_override))
4e8acb01
RB		 1246 arg1 &= ~BIT_7;
1247 if (!(esw_cfg->mac_anti_spoof))
1248 arg2 &= ~BIT_0;
1249 if (!(esw_cfg->offload_flags & BIT_0))
1250 arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
1251 if (!(esw_cfg->offload_flags & BIT_1))
1252 arg2 &= ~BIT_2;
1253 if (!(esw_cfg->offload_flags & BIT_2))
1254 arg2 &= ~BIT_3;
1255 break;
1256 case QLCNIC_ADD_VLAN:
1257 arg1 |= (BIT_2 | BIT_5);
1258 arg1 |= (esw_cfg->vlan_id << 16);
1259 break;
1260 case QLCNIC_DEL_VLAN:
1261 arg1 |= (BIT_3 | BIT_5);
1262 arg1 &= ~(0x0ffff << 16);
e9a47700 1263 break;
4e8acb01
RB		 1264 default:
1265 return err;
1266 }
1267
b6b4316c
SS		 1268 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1269 QLCNIC_CMD_CONFIGURE_ESWITCH);
1270 if (err)
1271 return err;
1272
7e2cf4fe
SC		 1273 cmd.req.arg[1] = arg1;
1274 cmd.req.arg[2] = arg2;
1275 err = qlcnic_issue_cmd(adapter, &cmd);
1276 qlcnic_free_mbx_args(&cmd);
4e8acb01 1277
7e2cf4fe 1278 if (err != QLCNIC_RCODE_SUCCESS)
ee9e8b6c
MC		 1279 dev_err(dev, "Failed to configure eswitch for vNIC function %d\n",
1280 pci_func);
7e2cf4fe 1281 else
ee9e8b6c
MC		 1282 dev_info(dev, "Configured eSwitch for vNIC function %d\n",
1283 pci_func);
4e8acb01
RB		 1284
1285 return err;
1286}
1287
1288int
1289qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
1290 struct qlcnic_esw_func_cfg *esw_cfg)
1291{
1292 u32 arg1, arg2;
bff57d8e 1293 int index;
4e8acb01 1294 u8 phy_port;
bff57d8e
SC		 1295
1296 if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
1297 index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
1298 if (index < 0)
1299 return -EIO;
1300 phy_port = adapter->npars[index].phy_port;
1301 } else {
79788450 1302 phy_port = adapter->ahw->physical_port;
bff57d8e 1303 }
4e8acb01
RB		 1304 arg1 = phy_port;
1305 arg1 |= (esw_cfg->pci_func << 8);
1306 if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
1307 return -EIO;
1308
1309 esw_cfg->discard_tagged = !!(arg1 & BIT_4);
1310 esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
1311 esw_cfg->promisc_mode = !!(arg1 & BIT_6);
7373373d 1312 esw_cfg->mac_override = !!(arg1 & BIT_7);
4e8acb01
RB		 1313 esw_cfg->vlan_id = LSW(arg1 >> 16);
1314 esw_cfg->mac_anti_spoof = (arg2 & 0x1);
1315 esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
1316
1317 return 0;
1318}
Linux kernel - Deliverables
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