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qlcnic: Add support for PEX DMA method to read memory section of adapter dump
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_hw.c
CommitLineData
af19b491 1/*
40839129 2 * QLogic qlcnic NIC Driver
577ae39d 3 * Copyright (c) 2009-2013 QLogic Corporation
af19b491 4 *
40839129 5 * See LICENSE.qlcnic for copyright and licensing details.
af19b491
AKS		 6 */
7
8#include "qlcnic.h"
15087c2b 9#include "qlcnic_hdr.h"
af19b491 10
5a0e3ad6 11#include <linux/slab.h>
af19b491 12#include <net/ip.h>
18f2f616 13#include <linux/bitops.h>
af19b491
AKS		 14
15#define MASK(n) ((1ULL<<(n))-1)
16#define OCM_WIN_P3P(addr) (addr & 0xffc0000)
17
18#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
19
20#define CRB_BLK(off) ((off >> 20) & 0x3f)
21#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
22#define CRB_WINDOW_2M (0x130060)
23#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
24#define CRB_INDIRECT_2M (0x1e0000UL)
25
15087c2b
SC		 26struct qlcnic_ms_reg_ctrl {
27 u32 ocm_window;
28 u32 control;
29 u32 hi;
30 u32 low;
31 u32 rd[4];
32 u32 wd[4];
33 u64 off;
34};
af19b491
AKS		 35
36#ifndef readq
37static inline u64 readq(void __iomem *addr)
38{
39 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
40}
41#endif
42
43#ifndef writeq
44static inline void writeq(u64 val, void __iomem *addr)
45{
46 writel(((u32) (val)), (addr));
47 writel(((u32) (val >> 32)), (addr + 4));
48}
49#endif
50
c477ebd8 51static struct crb_128M_2M_block_map
af19b491
AKS		 52crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
53 {{{0, 0, 0, 0} } }, /* 0: PCI */
54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
55 {1, 0x0110000, 0x0120000, 0x130000},
56 {1, 0x0120000, 0x0122000, 0x124000},
57 {1, 0x0130000, 0x0132000, 0x126000},
58 {1, 0x0140000, 0x0142000, 0x128000},
59 {1, 0x0150000, 0x0152000, 0x12a000},
60 {1, 0x0160000, 0x0170000, 0x110000},
61 {1, 0x0170000, 0x0172000, 0x12e000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {1, 0x01e0000, 0x01e0800, 0x122000},
69 {0, 0x0000000, 0x0000000, 0x000000} } },
70 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
71 {{{0, 0, 0, 0} } }, /* 3: */
72 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
73 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
76 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {1, 0x08f0000, 0x08f2000, 0x172000} } },
92 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x09f0000, 0x09f2000, 0x176000} } },
108 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
124 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
145 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
146 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
147 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
148 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
149 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
150 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
151 {{{0, 0, 0, 0} } }, /* 23: */
152 {{{0, 0, 0, 0} } }, /* 24: */
153 {{{0, 0, 0, 0} } }, /* 25: */
154 {{{0, 0, 0, 0} } }, /* 26: */
155 {{{0, 0, 0, 0} } }, /* 27: */
156 {{{0, 0, 0, 0} } }, /* 28: */
157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
160 {{{0} } }, /* 32: PCI */
161 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
162 {1, 0x2110000, 0x2120000, 0x130000},
163 {1, 0x2120000, 0x2122000, 0x124000},
164 {1, 0x2130000, 0x2132000, 0x126000},
165 {1, 0x2140000, 0x2142000, 0x128000},
166 {1, 0x2150000, 0x2152000, 0x12a000},
167 {1, 0x2160000, 0x2170000, 0x110000},
168 {1, 0x2170000, 0x2172000, 0x12e000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000} } },
177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
178 {{{0} } }, /* 35: */
179 {{{0} } }, /* 36: */
180 {{{0} } }, /* 37: */
181 {{{0} } }, /* 38: */
182 {{{0} } }, /* 39: */
183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
195 {{{0} } }, /* 52: */
196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
202 {{{0} } }, /* 59: I2C0 */
203 {{{0} } }, /* 60: I2C1 */
204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
207};
208
209/*
210 * top 12 bits of crb internal address (hub, agent)
211 */
212static const unsigned crb_hub_agt[64] = {
213 0,
214 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
215 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
216 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
217 0,
218 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
219 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
223 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
240 0,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
243 0,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
245 0,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
248 0,
249 0,
250 0,
251 0,
252 0,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
254 0,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
260 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
265 0,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
270 0,
271 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
274 0,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
276 0,
277};
278
15087c2b
SC		 279static const u32 msi_tgt_status[8] = {
280 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
281 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
282 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
283 ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
284};
285
af19b491
AKS		 286/* PCI Windowing for DDR regions. */
287
288#define QLCNIC_PCIE_SEM_TIMEOUT 10000
289
15087c2b
SC		 290static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
291{
292 u32 dest;
293 void __iomem *val;
294
295 dest = addr & 0xFFFF0000;
296 val = bar0 + QLCNIC_FW_DUMP_REG1;
297 writel(dest, val);
298 readl(val);
299 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
300 *data = readl(val);
301}
302
303static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
304{
305 u32 dest;
306 void __iomem *val;
307
308 dest = addr & 0xFFFF0000;
309 val = bar0 + QLCNIC_FW_DUMP_REG1;
310 writel(dest, val);
311 readl(val);
312 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
313 writel(data, val);
314 readl(val);
315}
316
af19b491
AKS		 317int
318qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
319{
320 int done = 0, timeout = 0;
321
322 while (!done) {
323 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
324 if (done == 1)
325 break;
65b5b420
AKS		 326 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
327 dev_err(&adapter->pdev->dev,
091754a1
SC		 328 "Failed to acquire sem=%d lock; holdby=%d\n",
329 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
af19b491 330 return -EIO;
65b5b420 331 }
af19b491
AKS		 332 msleep(1);
333 }
334
335 if (id_reg)
336 QLCWR32(adapter, id_reg, adapter->portnum);
337
338 return 0;
339}
340
341void
342qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
343{
344 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
345}
346
7f966452 347int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
15087c2b
SC		 348{
349 u32 data;
350
351 if (qlcnic_82xx_check(adapter))
352 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
7f966452
SC		 353 else {
354 data = qlcnic_83xx_rd_reg_indirect(adapter, addr);
355 if (data == -EIO)
356 return -EIO;
357 }
15087c2b
SC		 358 return data;
359}
360
7f966452 361void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
15087c2b
SC		 362{
363 if (qlcnic_82xx_check(adapter))
364 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
7f966452
SC		 365 else
366 qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
15087c2b
SC		 367}
368
af19b491
AKS		 369static int
370qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
371 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
372{
5d17f36b 373 u32 i, producer;
af19b491
AKS		 374 struct qlcnic_cmd_buffer *pbuf;
375 struct cmd_desc_type0 *cmd_desc;
376 struct qlcnic_host_tx_ring *tx_ring;
377
378 i = 0;
379
8a15ad1f 380 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
af19b491
AKS		 381 return -EIO;
382
383 tx_ring = adapter->tx_ring;
384 __netif_tx_lock_bh(tx_ring->txq);
385
386 producer = tx_ring->producer;
af19b491
AKS		 387
388 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
389 netif_tx_stop_queue(tx_ring->txq);
ef71ff83
RB		 390 smp_mb();
391 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
392 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
393 netif_tx_wake_queue(tx_ring->txq);
394 } else {
395 adapter->stats.xmit_off++;
396 __netif_tx_unlock_bh(tx_ring->txq);
397 return -EBUSY;
398 }
af19b491
AKS		 399 }
400
401 do {
402 cmd_desc = &cmd_desc_arr[i];
403
404 pbuf = &tx_ring->cmd_buf_arr[producer];
405 pbuf->skb = NULL;
406 pbuf->frag_count = 0;
407
408 memcpy(&tx_ring->desc_head[producer],
5d17f36b 409 cmd_desc, sizeof(struct cmd_desc_type0));
af19b491
AKS		 410
411 producer = get_next_index(producer, tx_ring->num_desc);
412 i++;
413
414 } while (i != nr_desc);
415
416 tx_ring->producer = producer;
417
5ad6ff9d 418 qlcnic_update_cmd_producer(tx_ring);
af19b491
AKS		 419
420 __netif_tx_unlock_bh(tx_ring->txq);
421
422 return 0;
423}
424
7e2cf4fe 425int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
f80bc8fe 426 u16 vlan_id, u8 op)
af19b491
AKS		 427{
428 struct qlcnic_nic_req req;
429 struct qlcnic_mac_req *mac_req;
7e56cac4 430 struct qlcnic_vlan_req *vlan_req;
af19b491
AKS		 431 u64 word;
432
433 memset(&req, 0, sizeof(struct qlcnic_nic_req));
434 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
435
436 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
437 req.req_hdr = cpu_to_le64(word);
438
439 mac_req = (struct qlcnic_mac_req *)&req.words[0];
440 mac_req->op = op;
441 memcpy(mac_req->mac_addr, addr, 6);
442
7e56cac4 443 vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
f80bc8fe 444 vlan_req->vlan_id = cpu_to_le16(vlan_id);
03c5d770 445
af19b491
AKS		 446 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
447}
448
fe1adc6b
JK		 449int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
450{
451 struct list_head *head;
452 struct qlcnic_mac_list_s *cur;
453 int err = -EINVAL;
454
455 /* Delete MAC from the existing list */
456 list_for_each(head, &adapter->mac_list) {
457 cur = list_entry(head, struct qlcnic_mac_list_s, list);
458 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
459 err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
460 0, QLCNIC_MAC_DEL);
461 if (err)
462 return err;
463 list_del(&cur->list);
464 kfree(cur);
465 return err;
466 }
467 }
468 return err;
469}
470
91b7282b 471int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan)
af19b491
AKS		 472{
473 struct list_head *head;
474 struct qlcnic_mac_list_s *cur;
475
476 /* look up if already exists */
9ab17b39 477 list_for_each(head, &adapter->mac_list) {
af19b491 478 cur = list_entry(head, struct qlcnic_mac_list_s, list);
9ab17b39 479 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
af19b491 480 return 0;
af19b491
AKS		 481 }
482
483 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
b2adaca9 484 if (cur == NULL)
af19b491 485 return -ENOMEM;
b2adaca9 486
af19b491 487 memcpy(cur->mac_addr, addr, ETH_ALEN);
af19b491 488
42f65cba 489 if (qlcnic_sre_macaddr_change(adapter,
91b7282b 490 cur->mac_addr, vlan, QLCNIC_MAC_ADD)) {
42f65cba
AKS		 491 kfree(cur);
492 return -EIO;
493 }
494
495 list_add_tail(&cur->list, &adapter->mac_list);
496 return 0;
af19b491
AKS		 497}
498
91b7282b 499void __qlcnic_set_multi(struct net_device *netdev, u16 vlan)
af19b491
AKS		 500{
501 struct qlcnic_adapter *adapter = netdev_priv(netdev);
52e493d0 502 struct qlcnic_hardware_context *ahw = adapter->ahw;
22bedad3 503 struct netdev_hw_addr *ha;
215faf9c
JP		 504 static const u8 bcast_addr[ETH_ALEN] = {
505 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
506 };
af19b491 507 u32 mode = VPORT_MISS_MODE_DROP;
af19b491 508
8a15ad1f 509 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
a55cb185
AKS		 510 return;
511
e8b508ef 512 if (!qlcnic_sriov_vf_check(adapter))
91b7282b
RB		 513 qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan);
514 qlcnic_nic_add_mac(adapter, bcast_addr, vlan);
af19b491
AKS		 515
516 if (netdev->flags & IFF_PROMISC) {
ee07c1a7
RB		 517 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
518 mode = VPORT_MISS_MODE_ACCEPT_ALL;
52e493d0
JK		 519 } else if (netdev->flags & IFF_ALLMULTI) {
520 if (netdev_mc_count(netdev) > ahw->max_mc_count) {
521 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
522 } else if (!netdev_mc_empty(netdev) &&
523 !qlcnic_sriov_vf_check(adapter)) {
524 netdev_for_each_mc_addr(ha, netdev)
525 qlcnic_nic_add_mac(adapter, ha->addr,
526 vlan);
527 }
528 if (mode != VPORT_MISS_MODE_ACCEPT_MULTI &&
529 qlcnic_sriov_vf_check(adapter))
530 qlcnic_vf_add_mc_list(netdev, vlan);
af19b491
AKS		 531 }
532
52e493d0
JK		 533 /* configure unicast MAC address, if there is not sufficient space
534 * to store all the unicast addresses then enable promiscuous mode
535 */
536 if (netdev_uc_count(netdev) > ahw->max_uc_count) {
537 mode = VPORT_MISS_MODE_ACCEPT_ALL;
538 } else if (!netdev_uc_empty(netdev)) {
539 netdev_for_each_uc_addr(ha, netdev)
91b7282b 540 qlcnic_nic_add_mac(adapter, ha->addr, vlan);
af19b491
AKS		 541 }
542
e8b508ef
RB		 543 if (!qlcnic_sriov_vf_check(adapter)) {
544 if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
545 !adapter->fdb_mac_learn) {
546 qlcnic_alloc_lb_filters_mem(adapter);
547 adapter->drv_mac_learn = true;
548 } else {
549 adapter->drv_mac_learn = false;
550 }
e5dcf6dc
SC		 551 }
552
af19b491 553 qlcnic_nic_set_promisc(adapter, mode);
af19b491
AKS		 554}
555
e8b508ef
RB		 556void qlcnic_set_multi(struct net_device *netdev)
557{
558 struct qlcnic_adapter *adapter = netdev_priv(netdev);
559 struct netdev_hw_addr *ha;
560 struct qlcnic_mac_list_s *cur;
561
562 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
563 return;
564 if (qlcnic_sriov_vf_check(adapter)) {
565 if (!netdev_mc_empty(netdev)) {
566 netdev_for_each_mc_addr(ha, netdev) {
567 cur = kzalloc(sizeof(struct qlcnic_mac_list_s),
568 GFP_ATOMIC);
d8fe3436
RB		 569 if (cur == NULL)
570 break;
e8b508ef
RB		 571 memcpy(cur->mac_addr,
572 ha->addr, ETH_ALEN);
573 list_add_tail(&cur->list, &adapter->vf_mc_list);
574 }
575 }
576 qlcnic_sriov_vf_schedule_multi(adapter->netdev);
577 return;
578 }
91b7282b 579 __qlcnic_set_multi(netdev, 0);
e8b508ef
RB		 580}
581
7e2cf4fe 582int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
af19b491
AKS		 583{
584 struct qlcnic_nic_req req;
585 u64 word;
586
587 memset(&req, 0, sizeof(struct qlcnic_nic_req));
588
589 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
590
b1fc6d3c 591 word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
af19b491
AKS		 592 ((u64)adapter->portnum << 16);
593 req.req_hdr = cpu_to_le64(word);
594
595 req.words[0] = cpu_to_le64(mode);
596
597 return qlcnic_send_cmd_descs(adapter,
598 (struct cmd_desc_type0 *)&req, 1);
599}
600
91b7282b 601void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter)
af19b491
AKS		 602{
603 struct qlcnic_mac_list_s *cur;
604 struct list_head *head = &adapter->mac_list;
605
606 while (!list_empty(head)) {
607 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
608 qlcnic_sre_macaddr_change(adapter,
03c5d770 609 cur->mac_addr, 0, QLCNIC_MAC_DEL);
af19b491
AKS		 610 list_del(&cur->list);
611 kfree(cur);
612 }
613}
614
b5e5492c
AKS		 615void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
616{
617 struct qlcnic_filter *tmp_fil;
b67bfe0d 618 struct hlist_node *n;
b5e5492c 619 struct hlist_head *head;
53643a75
SS		 620 int i;
621 unsigned long time;
7f966452 622 u8 cmd;
b5e5492c 623
7f966452 624 for (i = 0; i < adapter->fhash.fbucket_size; i++) {
b5e5492c 625 head = &(adapter->fhash.fhead[i]);
b67bfe0d 626 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
7f966452
SC		 627 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
628 QLCNIC_MAC_DEL;
629 time = tmp_fil->ftime;
630 if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
b5e5492c 631 qlcnic_sre_macaddr_change(adapter,
7f966452
SC		 632 tmp_fil->faddr,
633 tmp_fil->vlan_id,
634 cmd);
b5e5492c
AKS		 635 spin_lock_bh(&adapter->mac_learn_lock);
636 adapter->fhash.fnum--;
637 hlist_del(&tmp_fil->fnode);
638 spin_unlock_bh(&adapter->mac_learn_lock);
639 kfree(tmp_fil);
640 }
641 }
642 }
53643a75
SS		 643 for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) {
644 head = &(adapter->rx_fhash.fhead[i]);
645
b67bfe0d 646 hlist_for_each_entry_safe(tmp_fil, n, head, fnode)
53643a75
SS		 647 {
648 time = tmp_fil->ftime;
649 if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
650 spin_lock_bh(&adapter->rx_mac_learn_lock);
651 adapter->rx_fhash.fnum--;
652 hlist_del(&tmp_fil->fnode);
653 spin_unlock_bh(&adapter->rx_mac_learn_lock);
654 kfree(tmp_fil);
655 }
656 }
657 }
b5e5492c
AKS		 658}
659
660void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
661{
662 struct qlcnic_filter *tmp_fil;
b67bfe0d 663 struct hlist_node *n;
b5e5492c
AKS		 664 struct hlist_head *head;
665 int i;
7f966452 666 u8 cmd;
b5e5492c 667
7f966452 668 for (i = 0; i < adapter->fhash.fbucket_size; i++) {
b5e5492c 669 head = &(adapter->fhash.fhead[i]);
b67bfe0d 670 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
7f966452
SC		 671 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
672 QLCNIC_MAC_DEL;
673 qlcnic_sre_macaddr_change(adapter,
674 tmp_fil->faddr,
675 tmp_fil->vlan_id,
676 cmd);
b5e5492c
AKS		 677 spin_lock_bh(&adapter->mac_learn_lock);
678 adapter->fhash.fnum--;
679 hlist_del(&tmp_fil->fnode);
680 spin_unlock_bh(&adapter->mac_learn_lock);
681 kfree(tmp_fil);
682 }
683 }
684}
685
6d973cb1 686static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
22c8c934
SC		 687{
688 struct qlcnic_nic_req req;
689 int rv;
690
691 memset(&req, 0, sizeof(struct qlcnic_nic_req));
692
693 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
694 req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
695 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
696
697 req.words[0] = cpu_to_le64(flag);
698
699 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
700 if (rv != 0)
701 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
702 flag ? "Set" : "Reset");
703 return rv;
704}
705
7e2cf4fe 706int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
22c8c934
SC		 707{
708 if (qlcnic_set_fw_loopback(adapter, mode))
709 return -EIO;
710
7e2cf4fe
SC		 711 if (qlcnic_nic_set_promisc(adapter,
712 VPORT_MISS_MODE_ACCEPT_ALL)) {
ad567b8f 713 qlcnic_set_fw_loopback(adapter, 0);
22c8c934
SC		 714 return -EIO;
715 }
716
717 msleep(1000);
718 return 0;
719}
720
7e2cf4fe 721int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
22c8c934 722{
22c8c934
SC		 723 struct net_device *netdev = adapter->netdev;
724
7e2cf4fe 725 mode = VPORT_MISS_MODE_DROP;
22c8c934
SC		 726 qlcnic_set_fw_loopback(adapter, 0);
727
728 if (netdev->flags & IFF_PROMISC)
729 mode = VPORT_MISS_MODE_ACCEPT_ALL;
730 else if (netdev->flags & IFF_ALLMULTI)
731 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
732
733 qlcnic_nic_set_promisc(adapter, mode);
734 msleep(1000);
7e2cf4fe 735 return 0;
22c8c934
SC		 736}
737
af19b491
AKS		 738/*
739 * Send the interrupt coalescing parameter set by ethtool to the card.
740 */
7e2cf4fe 741void qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter)
af19b491
AKS		 742{
743 struct qlcnic_nic_req req;
8816d009 744 int rv;
af19b491
AKS		 745
746 memset(&req, 0, sizeof(struct qlcnic_nic_req));
747
748 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
749
8816d009
AC		 750 req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
751 ((u64) adapter->portnum << 16));
af19b491 752
8816d009
AC		 753 req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
754 req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
755 ((u64) adapter->ahw->coal.rx_time_us) << 16);
756 req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
757 ((u64) adapter->ahw->coal.type) << 32 |
758 ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
af19b491
AKS		 759 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
760 if (rv != 0)
761 dev_err(&adapter->netdev->dev,
762 "Could not send interrupt coalescing parameters\n");
af19b491
AKS		 763}
764
776e7bde
SS		 765#define QLCNIC_ENABLE_IPV4_LRO 1
766#define QLCNIC_ENABLE_IPV6_LRO 2
767#define QLCNIC_NO_DEST_IPV4_CHECK (1 << 8)
768#define QLCNIC_NO_DEST_IPV6_CHECK (2 << 8)
769
7e2cf4fe 770int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
af19b491
AKS		 771{
772 struct qlcnic_nic_req req;
773 u64 word;
774 int rv;
775
b56421d0
RB		 776 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
777 return 0;
778
af19b491
AKS		 779 memset(&req, 0, sizeof(struct qlcnic_nic_req));
780
781 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
782
783 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
784 req.req_hdr = cpu_to_le64(word);
785
776e7bde
SS		 786 word = 0;
787 if (enable) {
788 word = QLCNIC_ENABLE_IPV4_LRO | QLCNIC_NO_DEST_IPV4_CHECK;
789 if (adapter->ahw->capabilities2 & QLCNIC_FW_CAP2_HW_LRO_IPV6)
790 word |= QLCNIC_ENABLE_IPV6_LRO |
791 QLCNIC_NO_DEST_IPV6_CHECK;
792 }
793
794 req.words[0] = cpu_to_le64(word);
af19b491
AKS		 795
796 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
797 if (rv != 0)
798 dev_err(&adapter->netdev->dev,
799 "Could not send configure hw lro request\n");
800
af19b491
AKS		 801 return rv;
802}
803
2e9d722d 804int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
af19b491
AKS		 805{
806 struct qlcnic_nic_req req;
807 u64 word;
808 int rv;
809
810 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
811 return 0;
812
813 memset(&req, 0, sizeof(struct qlcnic_nic_req));
814
815 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
816
817 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
818 ((u64)adapter->portnum << 16);
819 req.req_hdr = cpu_to_le64(word);
820
821 req.words[0] = cpu_to_le64(enable);
822
823 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
824 if (rv != 0)
825 dev_err(&adapter->netdev->dev,
826 "Could not send configure bridge mode request\n");
827
828 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
829
830 return rv;
831}
832
833
efbcb1b2
SS		 834#define QLCNIC_RSS_HASHTYPE_IP_TCP 0x3
835#define QLCNIC_ENABLE_TYPE_C_RSS BIT_10
836#define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
837#define QLCNIC_RSS_IND_TABLE_MASK 0x7ULL
af19b491 838
7e2cf4fe 839int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
af19b491
AKS		 840{
841 struct qlcnic_nic_req req;
842 u64 word;
843 int i, rv;
844
215faf9c
JP		 845 static const u64 key[] = {
846 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
847 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
848 0x255b0ec26d5a56daULL
849 };
af19b491
AKS		 850
851 memset(&req, 0, sizeof(struct qlcnic_nic_req));
852 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
853
854 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
855 req.req_hdr = cpu_to_le64(word);
856
857 /*
858 * RSS request:
859 * bits 3-0: hash_method
860 * 5-4: hash_type_ipv4
861 * 7-6: hash_type_ipv6
862 * 8: enable
863 * 9: use indirection table
efbcb1b2
SS		 864 * 10: type-c rss
865 * 11: udp rss
866 * 47-12: reserved
867 * 62-48: indirection table mask
868 * 63: feature flag
af19b491 869 */
efbcb1b2
SS		 870 word = ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
871 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
af19b491 872 ((u64)(enable & 0x1) << 8) |
efbcb1b2
SS		 873 ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
874 (u64)QLCNIC_ENABLE_TYPE_C_RSS |
875 (u64)QLCNIC_RSS_FEATURE_FLAG;
876
af19b491
AKS		 877 req.words[0] = cpu_to_le64(word);
878 for (i = 0; i < 5; i++)
879 req.words[i+1] = cpu_to_le64(key[i]);
880
881 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
882 if (rv != 0)
883 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
884
885 return rv;
886}
887
7e2cf4fe
SC		 888void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
889 __be32 ip, int cmd)
af19b491
AKS		 890{
891 struct qlcnic_nic_req req;
b501595c 892 struct qlcnic_ipaddr *ipa;
af19b491
AKS		 893 u64 word;
894 int rv;
895
896 memset(&req, 0, sizeof(struct qlcnic_nic_req));
897 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
898
899 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
900 req.req_hdr = cpu_to_le64(word);
901
902 req.words[0] = cpu_to_le64(cmd);
b501595c
SC		 903 ipa = (struct qlcnic_ipaddr *)&req.words[1];
904 ipa->ipv4 = ip;
af19b491
AKS		 905
906 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
907 if (rv != 0)
908 dev_err(&adapter->netdev->dev,
909 "could not notify %s IP 0x%x reuqest\n",
910 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
af19b491
AKS		 911}
912
7e2cf4fe 913int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
af19b491
AKS		 914{
915 struct qlcnic_nic_req req;
916 u64 word;
917 int rv;
af19b491
AKS		 918 memset(&req, 0, sizeof(struct qlcnic_nic_req));
919 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
920
921 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
922 req.req_hdr = cpu_to_le64(word);
923 req.words[0] = cpu_to_le64(enable | (enable << 8));
af19b491
AKS		 924 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
925 if (rv != 0)
926 dev_err(&adapter->netdev->dev,
927 "could not configure link notification\n");
928
929 return rv;
930}
931
932int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
933{
934 struct qlcnic_nic_req req;
935 u64 word;
936 int rv;
937
b56421d0
RB		 938 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
939 return 0;
940
af19b491
AKS		 941 memset(&req, 0, sizeof(struct qlcnic_nic_req));
942 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
943
944 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
945 ((u64)adapter->portnum << 16) |
946 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
947
948 req.req_hdr = cpu_to_le64(word);
949
950 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
951 if (rv != 0)
952 dev_err(&adapter->netdev->dev,
953 "could not cleanup lro flows\n");
954
955 return rv;
956}
957
958/*
959 * qlcnic_change_mtu - Change the Maximum Transfer Unit
960 * @returns 0 on success, negative on failure
961 */
962
963int qlcnic_change_mtu(struct net_device *netdev, int mtu)
964{
965 struct qlcnic_adapter *adapter = netdev_priv(netdev);
966 int rc = 0;
967
ff1b1bf8 968 if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
0bd9e6a9 969 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
ff1b1bf8 970 " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
af19b491
AKS		 971 return -EINVAL;
972 }
973
974 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
975
976 if (!rc)
977 netdev->mtu = mtu;
978
979 return rc;
980}
981
147a9088
SS		 982static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter,
983 netdev_features_t features)
984{
985 u32 offload_flags = adapter->offload_flags;
986
987 if (offload_flags & BIT_0) {
988 features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
989 NETIF_F_IPV6_CSUM;
990 adapter->rx_csum = 1;
991 if (QLCNIC_IS_TSO_CAPABLE(adapter)) {
992 if (!(offload_flags & BIT_1))
993 features &= ~NETIF_F_TSO;
994 else
995 features |= NETIF_F_TSO;
996
997 if (!(offload_flags & BIT_2))
998 features &= ~NETIF_F_TSO6;
999 else
1000 features |= NETIF_F_TSO6;
1001 }
1002 } else {
1003 features &= ~(NETIF_F_RXCSUM |
1004 NETIF_F_IP_CSUM |
1005 NETIF_F_IPV6_CSUM);
1006
1007 if (QLCNIC_IS_TSO_CAPABLE(adapter))
1008 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1009 adapter->rx_csum = 0;
1010 }
1011
1012 return features;
1013}
135d84a9 1014
c8f44aff
MM		 1015netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1016 netdev_features_t features)
135d84a9
MM		 1017{
1018 struct qlcnic_adapter *adapter = netdev_priv(netdev);
147a9088 1019 netdev_features_t changed;
135d84a9 1020
147a9088
SS		 1021 if (qlcnic_82xx_check(adapter) &&
1022 (adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
1023 if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) {
1024 features = qlcnic_process_flags(adapter, features);
1025 } else {
1026 changed = features ^ netdev->features;
1027 features ^= changed & (NETIF_F_RXCSUM |
1028 NETIF_F_IP_CSUM |
1029 NETIF_F_IPV6_CSUM |
1030 NETIF_F_TSO |
1031 NETIF_F_TSO6);
1032 }
135d84a9
MM		 1033 }
1034
1035 if (!(features & NETIF_F_RXCSUM))
1036 features &= ~NETIF_F_LRO;
1037
1038 return features;
1039}
1040
1041
c8f44aff 1042int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
135d84a9
MM		 1043{
1044 struct qlcnic_adapter *adapter = netdev_priv(netdev);
c8f44aff 1045 netdev_features_t changed = netdev->features ^ features;
135d84a9
MM		 1046 int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
1047
1048 if (!(changed & NETIF_F_LRO))
1049 return 0;
1050
7e38d04b 1051 netdev->features ^= NETIF_F_LRO;
135d84a9
MM		 1052
1053 if (qlcnic_config_hw_lro(adapter, hw_lro))
1054 return -EIO;
1055
283c1c68
M		 1056 if (!hw_lro && qlcnic_82xx_check(adapter)) {
1057 if (qlcnic_send_lro_cleanup(adapter))
1058 return -EIO;
1059 }
135d84a9
MM		 1060
1061 return 0;
1062}
1063
af19b491
AKS		 1064/*
1065 * Changes the CRB window to the specified window.
1066 */
1067 /* Returns < 0 if off is not valid,
1068 * 1 if window access is needed. 'off' is set to offset from
1069 * CRB space in 128M pci map
1070 * 0 if no window access is needed. 'off' is set to 2M addr
1071 * In: 'off' is offset from base in 128M pci map
1072 */
15087c2b
SC		 1073static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
1074 ulong off, void __iomem **addr)
af19b491
AKS		 1075{
1076 const struct crb_128M_2M_sub_block_map *m;
1077
1078 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
1079 return -EINVAL;
1080
1081 off -= QLCNIC_PCI_CRBSPACE;
1082
1083 /*
1084 * Try direct map
1085 */
1086 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1087
1088 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
15087c2b 1089 *addr = ahw->pci_base0 + m->start_2M +
af19b491
AKS		 1090 (off - m->start_128M);
1091 return 0;
1092 }
1093
1094 /*
1095 * Not in direct map, use crb window
1096 */
15087c2b 1097 *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
af19b491
AKS		 1098 return 1;
1099}
1100
1101/*
1102 * In: 'off' is offset from CRB space in 128M pci map
1103 * Out: 'off' is 2M pci map addr
1104 * side effect: lock crb window
1105 */
4de57826 1106static int
af19b491
AKS		 1107qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1108{
1109 u32 window;
b1fc6d3c 1110 void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
af19b491
AKS		 1111
1112 off -= QLCNIC_PCI_CRBSPACE;
1113
1114 window = CRB_HI(off);
4de57826
AKS		 1115 if (window == 0) {
1116 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1117 return -EIO;
1118 }
af19b491 1119
af19b491
AKS		 1120 writel(window, addr);
1121 if (readl(addr) != window) {
1122 if (printk_ratelimit())
1123 dev_warn(&adapter->pdev->dev,
1124 "failed to set CRB window to %d off 0x%lx\n",
1125 window, off);
4de57826 1126 return -EIO;
af19b491 1127 }
4de57826 1128 return 0;
af19b491
AKS		 1129}
1130
7e2cf4fe
SC		 1131int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1132 u32 data)
af19b491
AKS		 1133{
1134 unsigned long flags;
1135 int rv;
1136 void __iomem *addr = NULL;
1137
15087c2b 1138 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
af19b491
AKS		 1139
1140 if (rv == 0) {
1141 writel(data, addr);
1142 return 0;
1143 }
1144
1145 if (rv > 0) {
1146 /* indirect access */
b1fc6d3c 1147 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
af19b491 1148 crb_win_lock(adapter);
4de57826
AKS		 1149 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1150 if (!rv)
1151 writel(data, addr);
af19b491 1152 crb_win_unlock(adapter);
b1fc6d3c 1153 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
4de57826 1154 return rv;
af19b491
AKS		 1155 }
1156
1157 dev_err(&adapter->pdev->dev,
1158 "%s: invalid offset: 0x%016lx\n", __func__, off);
1159 dump_stack();
1160 return -EIO;
1161}
1162
7e2cf4fe 1163int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
af19b491
AKS		 1164{
1165 unsigned long flags;
1166 int rv;
4de57826 1167 u32 data = -1;
af19b491
AKS		 1168 void __iomem *addr = NULL;
1169
15087c2b 1170 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
af19b491
AKS		 1171
1172 if (rv == 0)
1173 return readl(addr);
1174
1175 if (rv > 0) {
1176 /* indirect access */
b1fc6d3c 1177 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
af19b491 1178 crb_win_lock(adapter);
4de57826
AKS		 1179 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1180 data = readl(addr);
af19b491 1181 crb_win_unlock(adapter);
b1fc6d3c 1182 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
af19b491
AKS		 1183 return data;
1184 }
1185
1186 dev_err(&adapter->pdev->dev,
1187 "%s: invalid offset: 0x%016lx\n", __func__, off);
1188 dump_stack();
1189 return -1;
1190}
1191
15087c2b
SC		 1192void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1193 u32 offset)
af19b491
AKS		 1194{
1195 void __iomem *addr = NULL;
1196
15087c2b 1197 WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
af19b491
AKS		 1198
1199 return addr;
1200}
1201
15087c2b
SC		 1202static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1203 u32 window, u64 off, u64 *data, int op)
af19b491 1204{
0c39aa48 1205 void __iomem *addr;
af19b491
AKS		 1206 u32 start;
1207
b1fc6d3c 1208 mutex_lock(&adapter->ahw->mem_lock);
af19b491 1209
15087c2b
SC		 1210 writel(window, adapter->ahw->ocm_win_crb);
1211 /* read back to flush */
1212 readl(adapter->ahw->ocm_win_crb);
1213 start = QLCNIC_PCI_OCM0_2M + off;
af19b491 1214
b1fc6d3c 1215 addr = adapter->ahw->pci_base0 + start;
af19b491 1216
af19b491
AKS		 1217 if (op == 0) /* read */
1218 *data = readq(addr);
1219 else /* write */
1220 writeq(*data, addr);
1221
15087c2b
SC		 1222 /* Set window to 0 */
1223 writel(0, adapter->ahw->ocm_win_crb);
1224 readl(adapter->ahw->ocm_win_crb);
af19b491 1225
15087c2b
SC		 1226 mutex_unlock(&adapter->ahw->mem_lock);
1227 return 0;
af19b491
AKS		 1228}
1229
897e8c7c
DP		 1230void
1231qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1232{
b1fc6d3c 1233 void __iomem *addr = adapter->ahw->pci_base0 +
897e8c7c
DP		 1234 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1235
b1fc6d3c 1236 mutex_lock(&adapter->ahw->mem_lock);
897e8c7c 1237 *data = readq(addr);
b1fc6d3c 1238 mutex_unlock(&adapter->ahw->mem_lock);
897e8c7c
DP		 1239}
1240
1241void
1242qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1243{
b1fc6d3c 1244 void __iomem *addr = adapter->ahw->pci_base0 +
897e8c7c
DP		 1245 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1246
b1fc6d3c 1247 mutex_lock(&adapter->ahw->mem_lock);
897e8c7c 1248 writeq(data, addr);
b1fc6d3c 1249 mutex_unlock(&adapter->ahw->mem_lock);
897e8c7c
DP		 1250}
1251
15087c2b
SC		 1252
1253
1254/* Set MS memory control data for different adapters */
1255static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1256 struct qlcnic_ms_reg_ctrl *ms)
1257{
1258 ms->control = QLCNIC_MS_CTRL;
1259 ms->low = QLCNIC_MS_ADDR_LO;
1260 ms->hi = QLCNIC_MS_ADDR_HI;
1261 if (off & 0xf) {
1262 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1263 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1264 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1265 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1266 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1267 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1268 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1269 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1270 } else {
1271 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1272 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1273 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1274 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1275 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1276 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1277 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1278 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1279 }
1280
1281 ms->ocm_window = OCM_WIN_P3P(off);
1282 ms->off = GET_MEM_OFFS_2M(off);
1283}
1284
1285int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
af19b491 1286{
15087c2b 1287 int j, ret = 0;
af19b491 1288 u32 temp, off8;
15087c2b 1289 struct qlcnic_ms_reg_ctrl ms;
af19b491
AKS		 1290
1291 /* Only 64-bit aligned access */
1292 if (off & 7)
1293 return -EIO;
1294
15087c2b
SC		 1295 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1296 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1297 QLCNIC_ADDR_QDR_NET_MAX) ||
1298 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1299 QLCNIC_ADDR_DDR_NET_MAX)))
1300 return -EIO;
af19b491 1301
15087c2b 1302 qlcnic_set_ms_controls(adapter, off, &ms);
af19b491
AKS		 1303
1304 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
15087c2b
SC		 1305 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1306 ms.off, &data, 1);
af19b491 1307
b47acacd 1308 off8 = off & ~0xf;
af19b491 1309
b1fc6d3c 1310 mutex_lock(&adapter->ahw->mem_lock);
af19b491 1311
15087c2b
SC		 1312 qlcnic_ind_wr(adapter, ms.low, off8);
1313 qlcnic_ind_wr(adapter, ms.hi, 0);
af19b491 1314
15087c2b
SC		 1315 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1316 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
af19b491 1317
b47acacd 1318 for (j = 0; j < MAX_CTL_CHECK; j++) {
15087c2b 1319 temp = qlcnic_ind_rd(adapter, ms.control);
b47acacd
DP		 1320 if ((temp & TA_CTL_BUSY) == 0)
1321 break;
1322 }
af19b491 1323
b47acacd
DP		 1324 if (j >= MAX_CTL_CHECK) {
1325 ret = -EIO;
1326 goto done;
af19b491
AKS		 1327 }
1328
15087c2b
SC		 1329 /* This is the modify part of read-modify-write */
1330 qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1331 qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1332 /* This is the write part of read-modify-write */
1333 qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1334 qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
af19b491 1335
15087c2b
SC		 1336 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1337 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
af19b491
AKS		 1338
1339 for (j = 0; j < MAX_CTL_CHECK; j++) {
15087c2b 1340 temp = qlcnic_ind_rd(adapter, ms.control);
af19b491
AKS		 1341 if ((temp & TA_CTL_BUSY) == 0)
1342 break;
1343 }
1344
1345 if (j >= MAX_CTL_CHECK) {
1346 if (printk_ratelimit())
1347 dev_err(&adapter->pdev->dev,
1348 "failed to write through agent\n");
1349 ret = -EIO;
1350 } else
1351 ret = 0;
1352
1353done:
b1fc6d3c 1354 mutex_unlock(&adapter->ahw->mem_lock);
af19b491
AKS		 1355
1356 return ret;
1357}
1358
15087c2b 1359int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
af19b491
AKS		 1360{
1361 int j, ret;
1362 u32 temp, off8;
b47acacd 1363 u64 val;
15087c2b 1364 struct qlcnic_ms_reg_ctrl ms;
af19b491
AKS		 1365
1366 /* Only 64-bit aligned access */
1367 if (off & 7)
1368 return -EIO;
15087c2b
SC		 1369 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1370 QLCNIC_ADDR_QDR_NET_MAX) ||
1371 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1372 QLCNIC_ADDR_DDR_NET_MAX)))
1373 return -EIO;
af19b491 1374
15087c2b
SC		 1375 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1376 qlcnic_set_ms_controls(adapter, off, &ms);
af19b491 1377
15087c2b
SC		 1378 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1379 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1380 ms.off, data, 0);
af19b491 1381
15087c2b 1382 mutex_lock(&adapter->ahw->mem_lock);
af19b491 1383
b47acacd 1384 off8 = off & ~0xf;
af19b491 1385
15087c2b
SC		 1386 qlcnic_ind_wr(adapter, ms.low, off8);
1387 qlcnic_ind_wr(adapter, ms.hi, 0);
af19b491 1388
15087c2b
SC		 1389 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1390 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
af19b491
AKS		 1391
1392 for (j = 0; j < MAX_CTL_CHECK; j++) {
15087c2b 1393 temp = qlcnic_ind_rd(adapter, ms.control);
af19b491
AKS		 1394 if ((temp & TA_CTL_BUSY) == 0)
1395 break;
1396 }
1397
1398 if (j >= MAX_CTL_CHECK) {
1399 if (printk_ratelimit())
1400 dev_err(&adapter->pdev->dev,
1401 "failed to read through agent\n");
1402 ret = -EIO;
1403 } else {
af19b491 1404
15087c2b 1405 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
af19b491 1406 val = (u64)temp << 32;
15087c2b 1407 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
af19b491
AKS		 1408 *data = val;
1409 ret = 0;
1410 }
1411
b1fc6d3c 1412 mutex_unlock(&adapter->ahw->mem_lock);
af19b491
AKS		 1413
1414 return ret;
1415}
1416
7e2cf4fe 1417int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
af19b491
AKS		 1418{
1419 int offset, board_type, magic;
1420 struct pci_dev *pdev = adapter->pdev;
1421
1422 offset = QLCNIC_FW_MAGIC_OFFSET;
1423 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1424 return -EIO;
1425
1426 if (magic != QLCNIC_BDINFO_MAGIC) {
1427 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1428 magic);
1429 return -EIO;
1430 }
1431
1432 offset = QLCNIC_BRDTYPE_OFFSET;
1433 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1434 return -EIO;
1435
b1fc6d3c 1436 adapter->ahw->board_type = board_type;
af19b491 1437
ff1b1bf8 1438 if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
af19b491
AKS		 1439 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1440 if ((gpio & 0x8000) == 0)
ff1b1bf8 1441 board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
af19b491
AKS		 1442 }
1443
1444 switch (board_type) {
ff1b1bf8
SV		 1445 case QLCNIC_BRDTYPE_P3P_HMEZ:
1446 case QLCNIC_BRDTYPE_P3P_XG_LOM:
1447 case QLCNIC_BRDTYPE_P3P_10G_CX4:
1448 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1449 case QLCNIC_BRDTYPE_P3P_IMEZ:
1450 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1451 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1452 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1453 case QLCNIC_BRDTYPE_P3P_10G_XFP:
1454 case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
b1fc6d3c 1455 adapter->ahw->port_type = QLCNIC_XGBE;
af19b491 1456 break;
ff1b1bf8
SV		 1457 case QLCNIC_BRDTYPE_P3P_REF_QG:
1458 case QLCNIC_BRDTYPE_P3P_4_GB:
1459 case QLCNIC_BRDTYPE_P3P_4_GB_MM:
b1fc6d3c 1460 adapter->ahw->port_type = QLCNIC_GBE;
af19b491 1461 break;
ff1b1bf8 1462 case QLCNIC_BRDTYPE_P3P_10G_TP:
b1fc6d3c 1463 adapter->ahw->port_type = (adapter->portnum < 2) ?
af19b491
AKS		 1464 QLCNIC_XGBE : QLCNIC_GBE;
1465 break;
1466 default:
1467 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
b1fc6d3c 1468 adapter->ahw->port_type = QLCNIC_XGBE;
af19b491
AKS		 1469 break;
1470 }
1471
1472 return 0;
1473}
1474
1475int
1476qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1477{
1478 u32 wol_cfg;
1479
1480 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1481 if (wol_cfg & (1UL << adapter->portnum)) {
1482 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1483 if (wol_cfg & (1 << adapter->portnum))
1484 return 1;
1485 }
1486
1487 return 0;
1488}
897d3596 1489
7e2cf4fe 1490int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
897d3596
SC		 1491{
1492 struct qlcnic_nic_req req;
1493 int rv;
1494 u64 word;
1495
1496 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1497 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1498
1499 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1500 req.req_hdr = cpu_to_le64(word);
1501
dbab22c1 1502 req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
897d3596
SC		 1503 req.words[1] = cpu_to_le64(state);
1504
1505 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1506 if (rv)
1507 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1508
1509 return rv;
1510}
7e2cf4fe 1511
487042af
HM		 1512int qlcnic_get_beacon_state(struct qlcnic_adapter *adapter, u8 *h_state)
1513{
1514 struct qlcnic_cmd_args cmd;
1515 int err;
1516
1517 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_STATUS);
1518 if (!err) {
1519 err = qlcnic_issue_cmd(adapter, &cmd);
1520 if (!err)
1521 *h_state = cmd.rsp.arg[1];
1522 }
1523 qlcnic_free_mbx_args(&cmd);
1524 return err;
1525}
1526
7e2cf4fe
SC		 1527void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1528{
1529 void __iomem *msix_base_addr;
1530 u32 func;
1531 u32 msix_base;
1532
1533 pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1534 msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1535 msix_base = readl(msix_base_addr);
1536 func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1537 adapter->ahw->pci_func = func;
1538}
1539
1540void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1541 loff_t offset, size_t size)
1542{
1543 u32 data;
1544 u64 qmdata;
1545
1546 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1547 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1548 memcpy(buf, &qmdata, size);
1549 } else {
1550 data = QLCRD32(adapter, offset);
1551 memcpy(buf, &data, size);
1552 }
1553}
1554
1555void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1556 loff_t offset, size_t size)
1557{
1558 u32 data;
1559 u64 qmdata;
1560
1561 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1562 memcpy(&qmdata, buf, size);
1563 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1564 } else {
1565 memcpy(&data, buf, size);
1566 QLCWR32(adapter, offset, data);
1567 }
1568}
1569
1570int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1571{
1572 return qlcnic_pcie_sem_lock(adapter, 5, 0);
1573}
1574
1575void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1576{
1577 qlcnic_pcie_sem_unlock(adapter, 5);
1578}
Linux kernel - Deliverables
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