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r6040: remove unused variables and definitions
[deliverable/linux.git] / drivers / net / ethernet / rdc / r6040.c
CommitLineData
7a47dd7a
SW		 1/*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
5ac5d616 6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7a47dd7a
SW		 7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23*/
24
25#include <linux/kernel.h>
26#include <linux/module.h>
7a47dd7a
SW		 27#include <linux/moduleparam.h>
28#include <linux/string.h>
29#include <linux/timer.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
7a47dd7a
SW		 32#include <linux/interrupt.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/mii.h>
40#include <linux/ethtool.h>
41#include <linux/crc32.h>
42#include <linux/spinlock.h>
092427be
JG		 43#include <linux/bitops.h>
44#include <linux/io.h>
45#include <linux/irq.h>
46#include <linux/uaccess.h>
3831861b 47#include <linux/phy.h>
7a47dd7a
SW		 48
49#include <asm/processor.h>
7a47dd7a
SW		 50
51#define DRV_NAME "r6040"
5bdc4f5d
FF		 52#define DRV_VERSION "0.28"
53#define DRV_RELDATE "07Oct2011"
7a47dd7a 54
7a47dd7a 55/* Time in jiffies before concluding the transmitter is hung. */
5ac5d616 56#define TX_TIMEOUT (6000 * HZ / 1000)
7a47dd7a
SW		 57
58/* RDC MAC I/O Size */
59#define R6040_IO_SIZE 256
60
61/* MAX RDC MAC */
62#define MAX_MAC 2
63
64/* MAC registers */
65#define MCR0 0x00 /* Control register 0 */
c60c9c71
SL		 66#define MCR0_PROMISC 0x0020 /* Promiscuous mode */
67#define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
7a47dd7a
SW		 68#define MCR1 0x04 /* Control register 1 */
69#define MAC_RST 0x0001 /* Reset the MAC */
70#define MBCR 0x08 /* Bus control */
71#define MT_ICR 0x0C /* TX interrupt control */
72#define MR_ICR 0x10 /* RX interrupt control */
73#define MTPR 0x14 /* TX poll command register */
74#define MR_BSR 0x18 /* RX buffer size */
75#define MR_DCR 0x1A /* RX descriptor control */
76#define MLSR 0x1C /* Last status */
77#define MMDIO 0x20 /* MDIO control register */
78#define MDIO_WRITE 0x4000 /* MDIO write */
79#define MDIO_READ 0x2000 /* MDIO read */
80#define MMRD 0x24 /* MDIO read data register */
81#define MMWD 0x28 /* MDIO write data register */
82#define MTD_SA0 0x2C /* TX descriptor start address 0 */
83#define MTD_SA1 0x30 /* TX descriptor start address 1 */
84#define MRD_SA0 0x34 /* RX descriptor start address 0 */
85#define MRD_SA1 0x38 /* RX descriptor start address 1 */
86#define MISR 0x3C /* Status register */
87#define MIER 0x40 /* INT enable register */
88#define MSK_INT 0x0000 /* Mask off interrupts */
3d254348
FF		 89#define RX_FINISH 0x0001 /* RX finished */
90#define RX_NO_DESC 0x0002 /* No RX descriptor available */
91#define RX_FIFO_FULL 0x0004 /* RX FIFO full */
92#define RX_EARLY 0x0008 /* RX early */
93#define TX_FINISH 0x0010 /* TX finished */
94#define TX_EARLY 0x0080 /* TX early */
95#define EVENT_OVRFL 0x0100 /* Event counter overflow */
96#define LINK_CHANGED 0x0200 /* PHY link changed */
7a47dd7a
SW		 97#define ME_CISR 0x44 /* Event counter INT status */
98#define ME_CIER 0x48 /* Event counter INT enable */
99#define MR_CNT 0x50 /* Successfully received packet counter */
100#define ME_CNT0 0x52 /* Event counter 0 */
101#define ME_CNT1 0x54 /* Event counter 1 */
102#define ME_CNT2 0x56 /* Event counter 2 */
103#define ME_CNT3 0x58 /* Event counter 3 */
104#define MT_CNT 0x5A /* Successfully transmit packet counter */
105#define ME_CNT4 0x5C /* Event counter 4 */
106#define MP_CNT 0x5E /* Pause frame counter register */
107#define MAR0 0x60 /* Hash table 0 */
108#define MAR1 0x62 /* Hash table 1 */
109#define MAR2 0x64 /* Hash table 2 */
110#define MAR3 0x66 /* Hash table 3 */
111#define MID_0L 0x68 /* Multicast address MID0 Low */
112#define MID_0M 0x6A /* Multicast address MID0 Medium */
113#define MID_0H 0x6C /* Multicast address MID0 High */
114#define MID_1L 0x70 /* MID1 Low */
115#define MID_1M 0x72 /* MID1 Medium */
116#define MID_1H 0x74 /* MID1 High */
117#define MID_2L 0x78 /* MID2 Low */
118#define MID_2M 0x7A /* MID2 Medium */
119#define MID_2H 0x7C /* MID2 High */
120#define MID_3L 0x80 /* MID3 Low */
121#define MID_3M 0x82 /* MID3 Medium */
122#define MID_3H 0x84 /* MID3 High */
123#define PHY_CC 0x88 /* PHY status change configuration register */
124#define PHY_ST 0x8A /* PHY status register */
125#define MAC_SM 0xAC /* MAC status machine */
126#define MAC_ID 0xBE /* Identifier register */
127
128#define TX_DCNT 0x80 /* TX descriptor count */
129#define RX_DCNT 0x80 /* RX descriptor count */
130#define MAX_BUF_SIZE 0x600
6c323103
FR		 131#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
132#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
7a47dd7a 133#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
3bcf8229 134#define MCAST_MAX 3 /* Max number multicast addresses to filter */
7a47dd7a 135
32f565df
FF		 136/* Descriptor status */
137#define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
138#define DSC_RX_OK 0x4000 /* RX was successful */
139#define DSC_RX_ERR 0x0800 /* RX PHY error */
140#define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
141#define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
142#define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
143#define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
144#define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
145#define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
146#define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
147#define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
148#define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
149#define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
150
7a47dd7a
SW		 151MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
152 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
153 "Florian Fainelli <florian@openwrt.org>");
154MODULE_LICENSE("GPL");
155MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
bc4de260 156MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
7a47dd7a 157
3d254348 158/* RX and TX interrupts that we handle */
e24ddf3a
FF		 159#define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
160#define TX_INTS (TX_FINISH)
161#define INT_MASK (RX_INTS | TX_INTS)
7a47dd7a
SW		 162
163struct r6040_descriptor {
164 u16 status, len; /* 0-3 */
165 __le32 buf; /* 4-7 */
166 __le32 ndesc; /* 8-B */
167 u32 rev1; /* C-F */
168 char *vbufp; /* 10-13 */
169 struct r6040_descriptor *vndescp; /* 14-17 */
170 struct sk_buff *skb_ptr; /* 18-1B */
171 u32 rev2; /* 1C-1F */
172} __attribute__((aligned(32)));
173
174struct r6040_private {
175 spinlock_t lock; /* driver lock */
7a47dd7a
SW		 176 struct pci_dev *pdev;
177 struct r6040_descriptor *rx_insert_ptr;
178 struct r6040_descriptor *rx_remove_ptr;
179 struct r6040_descriptor *tx_insert_ptr;
180 struct r6040_descriptor *tx_remove_ptr;
6c323103
FR		 181 struct r6040_descriptor *rx_ring;
182 struct r6040_descriptor *tx_ring;
183 dma_addr_t rx_ring_dma;
184 dma_addr_t tx_ring_dma;
49f26720 185 u16 tx_free_desc;
7a47dd7a 186 u16 mcr0, mcr1;
7a47dd7a 187 struct net_device *dev;
3831861b 188 struct mii_bus *mii_bus;
7a47dd7a 189 struct napi_struct napi;
7a47dd7a 190 void __iomem *base;
3831861b
FF		 191 struct phy_device *phydev;
192 int old_link;
193 int old_duplex;
7a47dd7a
SW		 194};
195
2154c704 196static char version[] __devinitdata = DRV_NAME
7a47dd7a 197 ": RDC R6040 NAPI net driver,"
9a48ce84 198 "version "DRV_VERSION " (" DRV_RELDATE ")";
7a47dd7a 199
7a47dd7a 200/* Read a word data from PHY Chip */
c6e69bb9 201static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
7a47dd7a
SW		 202{
203 int limit = 2048;
204 u16 cmd;
205
206 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
207 /* Wait for the read bit to be cleared */
208 while (limit--) {
209 cmd = ioread16(ioaddr + MMDIO);
11e5e8f5 210 if (!(cmd & MDIO_READ))
7a47dd7a
SW		 211 break;
212 }
213
214 return ioread16(ioaddr + MMRD);
215}
216
217/* Write a word data from PHY Chip */
2154c704
FF		 218static void r6040_phy_write(void __iomem *ioaddr,
219 int phy_addr, int reg, u16 val)
7a47dd7a
SW		 220{
221 int limit = 2048;
222 u16 cmd;
223
224 iowrite16(val, ioaddr + MMWD);
225 /* Write the command to the MDIO bus */
226 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
227 /* Wait for the write bit to be cleared */
228 while (limit--) {
229 cmd = ioread16(ioaddr + MMDIO);
11e5e8f5 230 if (!(cmd & MDIO_WRITE))
7a47dd7a
SW		 231 break;
232 }
233}
234
3831861b 235static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
7a47dd7a 236{
3831861b 237 struct net_device *dev = bus->priv;
7a47dd7a
SW		 238 struct r6040_private *lp = netdev_priv(dev);
239 void __iomem *ioaddr = lp->base;
240
3831861b 241 return r6040_phy_read(ioaddr, phy_addr, reg);
7a47dd7a
SW		 242}
243
3831861b
FF		 244static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
245 int reg, u16 value)
7a47dd7a 246{
3831861b 247 struct net_device *dev = bus->priv;
7a47dd7a
SW		 248 struct r6040_private *lp = netdev_priv(dev);
249 void __iomem *ioaddr = lp->base;
250
3831861b
FF		 251 r6040_phy_write(ioaddr, phy_addr, reg, value);
252
253 return 0;
254}
255
256static int r6040_mdiobus_reset(struct mii_bus *bus)
257{
258 return 0;
7a47dd7a
SW		 259}
260
b4f1255d
FF		 261static void r6040_free_txbufs(struct net_device *dev)
262{
263 struct r6040_private *lp = netdev_priv(dev);
264 int i;
265
266 for (i = 0; i < TX_DCNT; i++) {
267 if (lp->tx_insert_ptr->skb_ptr) {
ed773b4a
AV		 268 pci_unmap_single(lp->pdev,
269 le32_to_cpu(lp->tx_insert_ptr->buf),
b4f1255d
FF		 270 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
271 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
3b060be0 272 lp->tx_insert_ptr->skb_ptr = NULL;
b4f1255d
FF		 273 }
274 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
275 }
276}
277
278static void r6040_free_rxbufs(struct net_device *dev)
279{
280 struct r6040_private *lp = netdev_priv(dev);
281 int i;
282
283 for (i = 0; i < RX_DCNT; i++) {
284 if (lp->rx_insert_ptr->skb_ptr) {
ed773b4a
AV		 285 pci_unmap_single(lp->pdev,
286 le32_to_cpu(lp->rx_insert_ptr->buf),
b4f1255d
FF		 287 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
288 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
289 lp->rx_insert_ptr->skb_ptr = NULL;
290 }
291 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
292 }
293}
294
b4f1255d
FF		 295static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
296 dma_addr_t desc_dma, int size)
297{
298 struct r6040_descriptor *desc = desc_ring;
299 dma_addr_t mapping = desc_dma;
300
301 while (size-- > 0) {
3f6602ad 302 mapping += sizeof(*desc);
b4f1255d
FF		 303 desc->ndesc = cpu_to_le32(mapping);
304 desc->vndescp = desc + 1;
305 desc++;
306 }
307 desc--;
308 desc->ndesc = cpu_to_le32(desc_dma);
309 desc->vndescp = desc_ring;
310}
311
3d463419 312static void r6040_init_txbufs(struct net_device *dev)
b4f1255d
FF		 313{
314 struct r6040_private *lp = netdev_priv(dev);
b4f1255d
FF		 315
316 lp->tx_free_desc = TX_DCNT;
317
318 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
319 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
b4f1255d
FF		 320}
321
3d463419 322static int r6040_alloc_rxbufs(struct net_device *dev)
b4f1255d
FF		 323{
324 struct r6040_private *lp = netdev_priv(dev);
3d463419
FF		 325 struct r6040_descriptor *desc;
326 struct sk_buff *skb;
327 int rc;
b4f1255d
FF		 328
329 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
330 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
331
3d463419
FF		 332 /* Allocate skbs for the rx descriptors */
333 desc = lp->rx_ring;
334 do {
335 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
336 if (!skb) {
7d53b809 337 netdev_err(dev, "failed to alloc skb for rx\n");
3d463419
FF		 338 rc = -ENOMEM;
339 goto err_exit;
340 }
341 desc->skb_ptr = skb;
342 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
2154c704
FF		 343 desc->skb_ptr->data,
344 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
32f565df 345 desc->status = DSC_OWNER_MAC;
3d463419
FF		 346 desc = desc->vndescp;
347 } while (desc != lp->rx_ring);
348
349 return 0;
350
351err_exit:
352 /* Deallocate all previously allocated skbs */
353 r6040_free_rxbufs(dev);
354 return rc;
fec3a23b
FF		 355}
356
357static void r6040_init_mac_regs(struct net_device *dev)
358{
359 struct r6040_private *lp = netdev_priv(dev);
360 void __iomem *ioaddr = lp->base;
361 int limit = 2048;
362 u16 cmd;
363
364 /* Mask Off Interrupt */
365 iowrite16(MSK_INT, ioaddr + MIER);
366
367 /* Reset RDC MAC */
368 iowrite16(MAC_RST, ioaddr + MCR1);
369 while (limit--) {
370 cmd = ioread16(ioaddr + MCR1);
371 if (cmd & 0x1)
372 break;
373 }
374 /* Reset internal state machine */
375 iowrite16(2, ioaddr + MAC_SM);
376 iowrite16(0, ioaddr + MAC_SM);
c1d69937 377 mdelay(5);
fec3a23b
FF		 378
379 /* MAC Bus Control Register */
380 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
381
382 /* Buffer Size Register */
383 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
384
385 /* Write TX ring start address */
386 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
387 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
b4f1255d 388
fec3a23b 389 /* Write RX ring start address */
b4f1255d
FF		 390 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
391 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
fec3a23b
FF		 392
393 /* Set interrupt waiting time and packet numbers */
31718ded
FF		 394 iowrite16(0, ioaddr + MT_ICR);
395 iowrite16(0, ioaddr + MR_ICR);
fec3a23b
FF		 396
397 /* Enable interrupts */
398 iowrite16(INT_MASK, ioaddr + MIER);
399
400 /* Enable TX and RX */
401 iowrite16(lp->mcr0 | 0x0002, ioaddr);
402
403 /* Let TX poll the descriptors
404 * we may got called by r6040_tx_timeout which has left
405 * some unsent tx buffers */
406 iowrite16(0x01, ioaddr + MTPR);
b4f1255d 407}
7a47dd7a 408
106adf3c
FF		 409static void r6040_tx_timeout(struct net_device *dev)
410{
411 struct r6040_private *priv = netdev_priv(dev);
412 void __iomem *ioaddr = priv->base;
413
7d53b809 414 netdev_warn(dev, "transmit timed out, int enable %4.4x "
3831861b 415 "status %4.4x\n",
7d53b809 416 ioread16(ioaddr + MIER),
3831861b 417 ioread16(ioaddr + MISR));
106adf3c 418
106adf3c 419 dev->stats.tx_errors++;
fec3a23b
FF		 420
421 /* Reset MAC and re-init all registers */
422 r6040_init_mac_regs(dev);
106adf3c
FF		 423}
424
7a47dd7a
SW		 425static struct net_device_stats *r6040_get_stats(struct net_device *dev)
426{
427 struct r6040_private *priv = netdev_priv(dev);
428 void __iomem *ioaddr = priv->base;
429 unsigned long flags;
430
431 spin_lock_irqsave(&priv->lock, flags);
d248fd77
FF		 432 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
433 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
7a47dd7a
SW		 434 spin_unlock_irqrestore(&priv->lock, flags);
435
d248fd77 436 return &dev->stats;
7a47dd7a
SW		 437}
438
439/* Stop RDC MAC and Free the allocated resource */
440static void r6040_down(struct net_device *dev)
441{
442 struct r6040_private *lp = netdev_priv(dev);
443 void __iomem *ioaddr = lp->base;
7a47dd7a
SW		 444 int limit = 2048;
445 u16 *adrp;
446 u16 cmd;
447
448 /* Stop MAC */
449 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
450 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
451 while (limit--) {
452 cmd = ioread16(ioaddr + MCR1);
453 if (cmd & 0x1)
454 break;
455 }
456
457 /* Restore MAC Address to MIDx */
458 adrp = (u16 *) dev->dev_addr;
459 iowrite16(adrp[0], ioaddr + MID_0L);
460 iowrite16(adrp[1], ioaddr + MID_0M);
461 iowrite16(adrp[2], ioaddr + MID_0H);
06e92c33
FF		 462
463 phy_stop(lp->phydev);
7a47dd7a
SW		 464}
465
5ac5d616 466static int r6040_close(struct net_device *dev)
7a47dd7a
SW		 467{
468 struct r6040_private *lp = netdev_priv(dev);
58854c6b 469 struct pci_dev *pdev = lp->pdev;
7a47dd7a 470
7a47dd7a 471 spin_lock_irq(&lp->lock);
129cf9a7 472 napi_disable(&lp->napi);
7a47dd7a
SW		 473 netif_stop_queue(dev);
474 r6040_down(dev);
58854c6b
FF		 475
476 free_irq(dev->irq, dev);
477
478 /* Free RX buffer */
479 r6040_free_rxbufs(dev);
480
481 /* Free TX buffer */
482 r6040_free_txbufs(dev);
483
7a47dd7a
SW		 484 spin_unlock_irq(&lp->lock);
485
58854c6b
FF		 486 /* Free Descriptor memory */
487 if (lp->rx_ring) {
2154c704
FF		 488 pci_free_consistent(pdev,
489 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
5b5103ec 490 lp->rx_ring = NULL;
58854c6b
FF		 491 }
492
493 if (lp->tx_ring) {
2154c704
FF		 494 pci_free_consistent(pdev,
495 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
5b5103ec 496 lp->tx_ring = NULL;
58854c6b
FF		 497 }
498
7a47dd7a
SW		 499 return 0;
500}
501
7a47dd7a
SW		 502static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
503{
504 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a 505
3831861b 506 if (!lp->phydev)
7a47dd7a 507 return -EINVAL;
3831861b 508
4cfa580e 509 return phy_mii_ioctl(lp->phydev, rq, cmd);
7a47dd7a
SW		 510}
511
512static int r6040_rx(struct net_device *dev, int limit)
513{
514 struct r6040_private *priv = netdev_priv(dev);
9ca28dc4
FF		 515 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
516 struct sk_buff *skb_ptr, *new_skb;
517 int count = 0;
7a47dd7a
SW		 518 u16 err;
519
9ca28dc4 520 /* Limit not reached and the descriptor belongs to the CPU */
32f565df 521 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
9ca28dc4
FF		 522 /* Read the descriptor status */
523 err = descptr->status;
524 /* Global error status set */
32f565df 525 if (err & DSC_RX_ERR) {
9ca28dc4 526 /* RX dribble */
32f565df 527 if (err & DSC_RX_ERR_DRI)
9ca28dc4 528 dev->stats.rx_frame_errors++;
25985edc 529 /* Buffer length exceeded */
32f565df 530 if (err & DSC_RX_ERR_BUF)
9ca28dc4
FF		 531 dev->stats.rx_length_errors++;
532 /* Packet too long */
32f565df 533 if (err & DSC_RX_ERR_LONG)
9ca28dc4
FF		 534 dev->stats.rx_length_errors++;
535 /* Packet < 64 bytes */
32f565df 536 if (err & DSC_RX_ERR_RUNT)
9ca28dc4
FF		 537 dev->stats.rx_length_errors++;
538 /* CRC error */
32f565df 539 if (err & DSC_RX_ERR_CRC) {
9ca28dc4
FF		 540 spin_lock(&priv->lock);
541 dev->stats.rx_crc_errors++;
542 spin_unlock(&priv->lock);
7a47dd7a 543 }
9ca28dc4
FF		 544 goto next_descr;
545 }
2154c704 546
9ca28dc4
FF		 547 /* Packet successfully received */
548 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
549 if (!new_skb) {
550 dev->stats.rx_dropped++;
551 goto next_descr;
7a47dd7a 552 }
9ca28dc4
FF		 553 skb_ptr = descptr->skb_ptr;
554 skb_ptr->dev = priv->dev;
2154c704 555
9ca28dc4
FF		 556 /* Do not count the CRC */
557 skb_put(skb_ptr, descptr->len - 4);
558 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
559 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
560 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
2154c704 561
9ca28dc4
FF		 562 /* Send to upper layer */
563 netif_receive_skb(skb_ptr);
9ca28dc4
FF		 564 dev->stats.rx_packets++;
565 dev->stats.rx_bytes += descptr->len - 4;
566
567 /* put new skb into descriptor */
568 descptr->skb_ptr = new_skb;
569 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
570 descptr->skb_ptr->data,
571 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
572
573next_descr:
574 /* put the descriptor back to the MAC */
32f565df 575 descptr->status = DSC_OWNER_MAC;
9ca28dc4
FF		 576 descptr = descptr->vndescp;
577 count++;
7a47dd7a 578 }
9ca28dc4 579 priv->rx_remove_ptr = descptr;
7a47dd7a
SW		 580
581 return count;
582}
583
584static void r6040_tx(struct net_device *dev)
585{
586 struct r6040_private *priv = netdev_priv(dev);
587 struct r6040_descriptor *descptr;
588 void __iomem *ioaddr = priv->base;
589 struct sk_buff *skb_ptr;
590 u16 err;
591
592 spin_lock(&priv->lock);
593 descptr = priv->tx_remove_ptr;
594 while (priv->tx_free_desc < TX_DCNT) {
595 /* Check for errors */
596 err = ioread16(ioaddr + MLSR);
597
d248fd77
FF		 598 if (err & 0x0200)
599 dev->stats.rx_fifo_errors++;
600 if (err & (0x2000 | 0x4000))
601 dev->stats.tx_carrier_errors++;
7a47dd7a 602
32f565df 603 if (descptr->status & DSC_OWNER_MAC)
ec6d2d45 604 break; /* Not complete */
7a47dd7a 605 skb_ptr = descptr->skb_ptr;
ed773b4a 606 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
7a47dd7a
SW		 607 skb_ptr->len, PCI_DMA_TODEVICE);
608 /* Free buffer */
609 dev_kfree_skb_irq(skb_ptr);
610 descptr->skb_ptr = NULL;
611 /* To next descriptor */
612 descptr = descptr->vndescp;
613 priv->tx_free_desc++;
614 }
615 priv->tx_remove_ptr = descptr;
616
617 if (priv->tx_free_desc)
618 netif_wake_queue(dev);
619 spin_unlock(&priv->lock);
620}
621
622static int r6040_poll(struct napi_struct *napi, int budget)
623{
624 struct r6040_private *priv =
625 container_of(napi, struct r6040_private, napi);
626 struct net_device *dev = priv->dev;
627 void __iomem *ioaddr = priv->base;
628 int work_done;
629
630 work_done = r6040_rx(dev, budget);
631
632 if (work_done < budget) {
288379f0 633 napi_complete(napi);
7a47dd7a 634 /* Enable RX interrupt */
e24ddf3a 635 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
7a47dd7a
SW		 636 }
637 return work_done;
638}
639
640/* The RDC interrupt handler. */
641static irqreturn_t r6040_interrupt(int irq, void *dev_id)
642{
643 struct net_device *dev = dev_id;
644 struct r6040_private *lp = netdev_priv(dev);
645 void __iomem *ioaddr = lp->base;
3e7c469f 646 u16 misr, status;
7a47dd7a 647
3e7c469f
JC		 648 /* Save MIER */
649 misr = ioread16(ioaddr + MIER);
7a47dd7a
SW		 650 /* Mask off RDC MAC interrupt */
651 iowrite16(MSK_INT, ioaddr + MIER);
652 /* Read MISR status and clear */
653 status = ioread16(ioaddr + MISR);
654
35976d4d
FF		 655 if (status == 0x0000 || status == 0xffff) {
656 /* Restore RDC MAC interrupt */
657 iowrite16(misr, ioaddr + MIER);
7a47dd7a 658 return IRQ_NONE;
35976d4d 659 }
7a47dd7a
SW		 660
661 /* RX interrupt request */
e24ddf3a
FF		 662 if (status & RX_INTS) {
663 if (status & RX_NO_DESC) {
664 /* RX descriptor unavailable */
665 dev->stats.rx_dropped++;
666 dev->stats.rx_missed_errors++;
667 }
668 if (status & RX_FIFO_FULL)
669 dev->stats.rx_fifo_errors++;
670
0d9b6e73
MT		 671 if (likely(napi_schedule_prep(&lp->napi))) {
672 /* Mask off RX interrupt */
673 misr &= ~RX_INTS;
674 __napi_schedule(&lp->napi);
675 }
7a47dd7a
SW		 676 }
677
678 /* TX interrupt request */
e24ddf3a 679 if (status & TX_INTS)
7a47dd7a
SW		 680 r6040_tx(dev);
681
3e7c469f
JC		 682 /* Restore RDC MAC interrupt */
683 iowrite16(misr, ioaddr + MIER);
684
ec6d2d45 685 return IRQ_HANDLED;
7a47dd7a
SW		 686}
687
688#ifdef CONFIG_NET_POLL_CONTROLLER
689static void r6040_poll_controller(struct net_device *dev)
690{
691 disable_irq(dev->irq);
5ac5d616 692 r6040_interrupt(dev->irq, dev);
7a47dd7a
SW		 693 enable_irq(dev->irq);
694}
695#endif
696
7a47dd7a 697/* Init RDC MAC */
3d463419 698static int r6040_up(struct net_device *dev)
7a47dd7a
SW		 699{
700 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a 701 void __iomem *ioaddr = lp->base;
3d463419 702 int ret;
7a47dd7a 703
b4f1255d 704 /* Initialise and alloc RX/TX buffers */
3d463419
FF		 705 r6040_init_txbufs(dev);
706 ret = r6040_alloc_rxbufs(dev);
707 if (ret)
708 return ret;
7a47dd7a 709
7a47dd7a 710 /* improve performance (by RDC guys) */
2154c704
FF		 711 r6040_phy_write(ioaddr, 30, 17,
712 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
713 r6040_phy_write(ioaddr, 30, 17,
714 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
c6e69bb9
FF		 715 r6040_phy_write(ioaddr, 0, 19, 0x0000);
716 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
7a47dd7a 717
fec3a23b
FF		 718 /* Initialize all MAC registers */
719 r6040_init_mac_regs(dev);
3d463419 720
06e92c33
FF		 721 phy_start(lp->phydev);
722
3d463419 723 return 0;
7a47dd7a
SW		 724}
725
7a47dd7a
SW		 726
727/* Read/set MAC address routines */
728static void r6040_mac_address(struct net_device *dev)
729{
730 struct r6040_private *lp = netdev_priv(dev);
731 void __iomem *ioaddr = lp->base;
732 u16 *adrp;
733
734 /* MAC operation register */
735 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
736 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
737 iowrite16(0, ioaddr + MAC_SM);
c1d69937 738 mdelay(5);
7a47dd7a
SW		 739
740 /* Restore MAC Address */
741 adrp = (u16 *) dev->dev_addr;
742 iowrite16(adrp[0], ioaddr + MID_0L);
743 iowrite16(adrp[1], ioaddr + MID_0M);
744 iowrite16(adrp[2], ioaddr + MID_0H);
42099d7a
OS		 745
746 /* Store MAC Address in perm_addr */
747 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
7a47dd7a
SW		 748}
749
5ac5d616 750static int r6040_open(struct net_device *dev)
7a47dd7a 751{
5ac5d616 752 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 753 int ret;
754
755 /* Request IRQ and Register interrupt handler */
91dcbf36 756 ret = request_irq(dev->irq, r6040_interrupt,
7a47dd7a
SW		 757 IRQF_SHARED, dev->name, dev);
758 if (ret)
ced1de4c 759 goto out;
7a47dd7a
SW		 760
761 /* Set MAC address */
762 r6040_mac_address(dev);
763
764 /* Allocate Descriptor memory */
6c323103
FR		 765 lp->rx_ring =
766 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
ced1de4c
DK		 767 if (!lp->rx_ring) {
768 ret = -ENOMEM;
769 goto err_free_irq;
770 }
7a47dd7a 771
6c323103
FR		 772 lp->tx_ring =
773 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
774 if (!lp->tx_ring) {
ced1de4c
DK		 775 ret = -ENOMEM;
776 goto err_free_rx_ring;
6c323103
FR		 777 }
778
3d463419 779 ret = r6040_up(dev);
ced1de4c
DK		 780 if (ret)
781 goto err_free_tx_ring;
7a47dd7a
SW		 782
783 napi_enable(&lp->napi);
784 netif_start_queue(dev);
785
7a47dd7a 786 return 0;
ced1de4c
DK		 787
788err_free_tx_ring:
789 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
790 lp->tx_ring_dma);
791err_free_rx_ring:
792 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
793 lp->rx_ring_dma);
794err_free_irq:
795 free_irq(dev->irq, dev);
796out:
797 return ret;
7a47dd7a
SW		 798}
799
61357325
SH		 800static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
801 struct net_device *dev)
7a47dd7a
SW		 802{
803 struct r6040_private *lp = netdev_priv(dev);
804 struct r6040_descriptor *descptr;
805 void __iomem *ioaddr = lp->base;
806 unsigned long flags;
7a47dd7a
SW		 807
808 /* Critical Section */
809 spin_lock_irqsave(&lp->lock, flags);
810
811 /* TX resource check */
812 if (!lp->tx_free_desc) {
813 spin_unlock_irqrestore(&lp->lock, flags);
092427be 814 netif_stop_queue(dev);
7d53b809 815 netdev_err(dev, ": no tx descriptor\n");
61357325 816 return NETDEV_TX_BUSY;
7a47dd7a
SW		 817 }
818
819 /* Statistic Counter */
820 dev->stats.tx_packets++;
821 dev->stats.tx_bytes += skb->len;
822 /* Set TX descriptor & Transmit it */
823 lp->tx_free_desc--;
824 descptr = lp->tx_insert_ptr;
825 if (skb->len < MISR)
826 descptr->len = MISR;
827 else
828 descptr->len = skb->len;
829
830 descptr->skb_ptr = skb;
831 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
832 skb->data, skb->len, PCI_DMA_TODEVICE));
32f565df 833 descptr->status = DSC_OWNER_MAC;
2aa8f4c9
RC		 834
835 skb_tx_timestamp(skb);
836
7a47dd7a
SW		 837 /* Trigger the MAC to check the TX descriptor */
838 iowrite16(0x01, ioaddr + MTPR);
839 lp->tx_insert_ptr = descptr->vndescp;
840
841 /* If no tx resource, stop */
842 if (!lp->tx_free_desc)
843 netif_stop_queue(dev);
844
7a47dd7a 845 spin_unlock_irqrestore(&lp->lock, flags);
61357325
SH		 846
847 return NETDEV_TX_OK;
7a47dd7a
SW		 848}
849
5ac5d616 850static void r6040_multicast_list(struct net_device *dev)
7a47dd7a
SW		 851{
852 struct r6040_private *lp = netdev_priv(dev);
853 void __iomem *ioaddr = lp->base;
7a47dd7a 854 unsigned long flags;
22bedad3 855 struct netdev_hw_addr *ha;
7a47dd7a 856 int i;
c60c9c71
SL		 857 u16 *adrp;
858 u16 hash_table[4] = { 0 };
859
860 spin_lock_irqsave(&lp->lock, flags);
7a47dd7a 861
c60c9c71 862 /* Keep our MAC Address */
7a47dd7a
SW		 863 adrp = (u16 *)dev->dev_addr;
864 iowrite16(adrp[0], ioaddr + MID_0L);
865 iowrite16(adrp[1], ioaddr + MID_0M);
866 iowrite16(adrp[2], ioaddr + MID_0H);
867
7a47dd7a 868 /* Clear AMCP & PROM bits */
c60c9c71 869 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
7a47dd7a 870
c60c9c71
SL		 871 /* Promiscuous mode */
872 if (dev->flags & IFF_PROMISC)
873 lp->mcr0 |= MCR0_PROMISC;
7a47dd7a 874
c60c9c71
SL		 875 /* Enable multicast hash table function to
876 * receive all multicast packets. */
877 else if (dev->flags & IFF_ALLMULTI) {
878 lp->mcr0 |= MCR0_HASH_EN;
7a47dd7a 879
c60c9c71
SL		 880 for (i = 0; i < MCAST_MAX ; i++) {
881 iowrite16(0, ioaddr + MID_1L + 8 * i);
882 iowrite16(0, ioaddr + MID_1M + 8 * i);
883 iowrite16(0, ioaddr + MID_1H + 8 * i);
884 }
7a47dd7a 885
c60c9c71
SL		 886 for (i = 0; i < 4; i++)
887 hash_table[i] = 0xffff;
888 }
889 /* Use internal multicast address registers if the number of
890 * multicast addresses is not greater than MCAST_MAX. */
891 else if (netdev_mc_count(dev) <= MCAST_MAX) {
892 i = 0;
22bedad3 893 netdev_for_each_mc_addr(ha, dev) {
c60c9c71
SL		 894 u16 *adrp = (u16 *) ha->addr;
895 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
896 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
897 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
898 i++;
899 }
900 while (i < MCAST_MAX) {
901 iowrite16(0, ioaddr + MID_1L + 8 * i);
902 iowrite16(0, ioaddr + MID_1M + 8 * i);
903 iowrite16(0, ioaddr + MID_1H + 8 * i);
904 i++;
905 }
906 }
907 /* Otherwise, Enable multicast hash table function. */
908 else {
909 u32 crc;
7a47dd7a 910
c60c9c71
SL		 911 lp->mcr0 |= MCR0_HASH_EN;
912
913 for (i = 0; i < MCAST_MAX ; i++) {
914 iowrite16(0, ioaddr + MID_1L + 8 * i);
915 iowrite16(0, ioaddr + MID_1M + 8 * i);
916 iowrite16(0, ioaddr + MID_1H + 8 * i);
917 }
7a47dd7a 918
c60c9c71
SL		 919 /* Build multicast hash table */
920 netdev_for_each_mc_addr(ha, dev) {
921 u8 *addrs = ha->addr;
922
923 crc = ether_crc(ETH_ALEN, addrs);
7a47dd7a 924 crc >>= 26;
c60c9c71 925 hash_table[crc >> 4] |= 1 << (crc & 0xf);
7a47dd7a 926 }
c60c9c71
SL		 927 }
928
929 iowrite16(lp->mcr0, ioaddr + MCR0);
930
931 /* Fill the MAC hash tables with their values */
bbc13ab9 932 if (lp->mcr0 & MCR0_HASH_EN) {
7a47dd7a
SW		 933 iowrite16(hash_table[0], ioaddr + MAR0);
934 iowrite16(hash_table[1], ioaddr + MAR1);
935 iowrite16(hash_table[2], ioaddr + MAR2);
936 iowrite16(hash_table[3], ioaddr + MAR3);
937 }
c60c9c71
SL		 938
939 spin_unlock_irqrestore(&lp->lock, flags);
7a47dd7a
SW		 940}
941
942static void netdev_get_drvinfo(struct net_device *dev,
943 struct ethtool_drvinfo *info)
944{
945 struct r6040_private *rp = netdev_priv(dev);
946
947 strcpy(info->driver, DRV_NAME);
948 strcpy(info->version, DRV_VERSION);
949 strcpy(info->bus_info, pci_name(rp->pdev));
950}
951
952static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
953{
954 struct r6040_private *rp = netdev_priv(dev);
7a47dd7a 955
3831861b 956 return phy_ethtool_gset(rp->phydev, cmd);
7a47dd7a
SW		 957}
958
959static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7a47dd7a
SW		 960{
961 struct r6040_private *rp = netdev_priv(dev);
962
3831861b 963 return phy_ethtool_sset(rp->phydev, cmd);
7a47dd7a
SW		 964}
965
a7bd89cb 966static const struct ethtool_ops netdev_ethtool_ops = {
7a47dd7a
SW		 967 .get_drvinfo = netdev_get_drvinfo,
968 .get_settings = netdev_get_settings,
969 .set_settings = netdev_set_settings,
3831861b 970 .get_link = ethtool_op_get_link,
7a47dd7a
SW		 971};
972
a7bd89cb
SH		 973static const struct net_device_ops r6040_netdev_ops = {
974 .ndo_open = r6040_open,
975 .ndo_stop = r6040_close,
976 .ndo_start_xmit = r6040_start_xmit,
977 .ndo_get_stats = r6040_get_stats,
afc4b13d 978 .ndo_set_rx_mode = r6040_multicast_list,
a7bd89cb
SH		 979 .ndo_change_mtu = eth_change_mtu,
980 .ndo_validate_addr = eth_validate_addr,
2154c704 981 .ndo_set_mac_address = eth_mac_addr,
a7bd89cb
SH		 982 .ndo_do_ioctl = r6040_ioctl,
983 .ndo_tx_timeout = r6040_tx_timeout,
984#ifdef CONFIG_NET_POLL_CONTROLLER
985 .ndo_poll_controller = r6040_poll_controller,
986#endif
987};
988
3831861b
FF		 989static void r6040_adjust_link(struct net_device *dev)
990{
991 struct r6040_private *lp = netdev_priv(dev);
992 struct phy_device *phydev = lp->phydev;
993 int status_changed = 0;
994 void __iomem *ioaddr = lp->base;
995
996 BUG_ON(!phydev);
997
998 if (lp->old_link != phydev->link) {
999 status_changed = 1;
1000 lp->old_link = phydev->link;
1001 }
1002
1003 /* reflect duplex change */
1004 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
1005 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? 0x8000 : 0);
1006 iowrite16(lp->mcr0, ioaddr);
1007
1008 status_changed = 1;
1009 lp->old_duplex = phydev->duplex;
1010 }
1011
1012 if (status_changed) {
1013 pr_info("%s: link %s", dev->name, phydev->link ?
1014 "UP" : "DOWN");
1015 if (phydev->link)
1016 pr_cont(" - %d/%s", phydev->speed,
1017 DUPLEX_FULL == phydev->duplex ? "full" : "half");
1018 pr_cont("\n");
1019 }
1020}
1021
1022static int r6040_mii_probe(struct net_device *dev)
1023{
1024 struct r6040_private *lp = netdev_priv(dev);
1025 struct phy_device *phydev = NULL;
1026
1027 phydev = phy_find_first(lp->mii_bus);
1028 if (!phydev) {
1029 dev_err(&lp->pdev->dev, "no PHY found\n");
1030 return -ENODEV;
1031 }
1032
1033 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1034 0, PHY_INTERFACE_MODE_MII);
1035
1036 if (IS_ERR(phydev)) {
1037 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1038 return PTR_ERR(phydev);
1039 }
1040
1041 /* mask with MAC supported features */
1042 phydev->supported &= (SUPPORTED_10baseT_Half
1043 | SUPPORTED_10baseT_Full
1044 | SUPPORTED_100baseT_Half
1045 | SUPPORTED_100baseT_Full
1046 | SUPPORTED_Autoneg
1047 | SUPPORTED_MII
1048 | SUPPORTED_TP);
1049
1050 phydev->advertising = phydev->supported;
1051 lp->phydev = phydev;
1052 lp->old_link = 0;
1053 lp->old_duplex = -1;
1054
1055 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1056 "(mii_bus:phy_addr=%s)\n",
1057 phydev->drv->name, dev_name(&phydev->dev));
1058
1059 return 0;
1060}
1061
7a47dd7a
SW		 1062static int __devinit r6040_init_one(struct pci_dev *pdev,
1063 const struct pci_device_id *ent)
1064{
1065 struct net_device *dev;
1066 struct r6040_private *lp;
1067 void __iomem *ioaddr;
1068 int err, io_size = R6040_IO_SIZE;
1069 static int card_idx = -1;
1070 int bar = 0;
7a47dd7a 1071 u16 *adrp;
3831861b 1072 int i;
7a47dd7a 1073
2154c704 1074 pr_info("%s\n", version);
7a47dd7a
SW		 1075
1076 err = pci_enable_device(pdev);
1077 if (err)
b0e45390 1078 goto err_out;
7a47dd7a
SW		 1079
1080 /* this should always be supported */
284901a9 1081 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b0e45390 1082 if (err) {
7d53b809 1083 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
7a47dd7a 1084 "not supported by the card\n");
b0e45390 1085 goto err_out;
7a47dd7a 1086 }
284901a9 1087 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b0e45390 1088 if (err) {
7d53b809 1089 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
092427be 1090 "not supported by the card\n");
b0e45390 1091 goto err_out;
092427be 1092 }
7a47dd7a
SW		 1093
1094 /* IO Size check */
6f5bec19 1095 if (pci_resource_len(pdev, bar) < io_size) {
7d53b809 1096 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
b0e45390
FF		 1097 err = -EIO;
1098 goto err_out;
7a47dd7a
SW		 1099 }
1100
7a47dd7a
SW		 1101 pci_set_master(pdev);
1102
1103 dev = alloc_etherdev(sizeof(struct r6040_private));
1104 if (!dev) {
7d53b809 1105 dev_err(&pdev->dev, "Failed to allocate etherdev\n");
b0e45390
FF		 1106 err = -ENOMEM;
1107 goto err_out;
7a47dd7a
SW		 1108 }
1109 SET_NETDEV_DEV(dev, &pdev->dev);
1110 lp = netdev_priv(dev);
7a47dd7a 1111
b0e45390
FF		 1112 err = pci_request_regions(pdev, DRV_NAME);
1113
1114 if (err) {
7d53b809 1115 dev_err(&pdev->dev, "Failed to request PCI regions\n");
b0e45390 1116 goto err_out_free_dev;
7a47dd7a
SW		 1117 }
1118
1119 ioaddr = pci_iomap(pdev, bar, io_size);
1120 if (!ioaddr) {
7d53b809 1121 dev_err(&pdev->dev, "ioremap failed for device\n");
b0e45390
FF		 1122 err = -EIO;
1123 goto err_out_free_res;
7a47dd7a 1124 }
84314bf9
FF		 1125 /* If PHY status change register is still set to zero it means the
1126 * bootloader didn't initialize it */
1127 if (ioread16(ioaddr + PHY_CC) == 0)
1128 iowrite16(0x9f07, ioaddr + PHY_CC);
7a47dd7a
SW		 1129
1130 /* Init system & device */
7a47dd7a
SW		 1131 lp->base = ioaddr;
1132 dev->irq = pdev->irq;
1133
1134 spin_lock_init(&lp->lock);
1135 pci_set_drvdata(pdev, dev);
1136
1137 /* Set MAC address */
1138 card_idx++;
1139
1140 adrp = (u16 *)dev->dev_addr;
1141 adrp[0] = ioread16(ioaddr + MID_0L);
1142 adrp[1] = ioread16(ioaddr + MID_0M);
1143 adrp[2] = ioread16(ioaddr + MID_0H);
1144
1d2b1a76
FF		 1145 /* Some bootloader/BIOSes do not initialize
1146 * MAC address, warn about that */
9f113618 1147 if (!(adrp[0] || adrp[1] || adrp[2])) {
2154c704
FF		 1148 netdev_warn(dev, "MAC address not initialized, "
1149 "generating random\n");
9f113618
FF		 1150 random_ether_addr(dev->dev_addr);
1151 }
1d2b1a76 1152
7a47dd7a
SW		 1153 /* Link new device into r6040_root_dev */
1154 lp->pdev = pdev;
129cf9a7 1155 lp->dev = dev;
7a47dd7a
SW		 1156
1157 /* Init RDC private data */
1158 lp->mcr0 = 0x1002;
7a47dd7a
SW		 1159
1160 /* The RDC-specific entries in the device structure. */
a7bd89cb 1161 dev->netdev_ops = &r6040_netdev_ops;
7a47dd7a 1162 dev->ethtool_ops = &netdev_ethtool_ops;
7a47dd7a 1163 dev->watchdog_timeo = TX_TIMEOUT;
a7bd89cb 1164
7a47dd7a 1165 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
3831861b
FF		 1166
1167 lp->mii_bus = mdiobus_alloc();
1168 if (!lp->mii_bus) {
1169 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
9c86c0f4 1170 err = -ENOMEM;
e03f614a
MK		 1171 goto err_out_unmap;
1172 }
1173
3831861b
FF		 1174 lp->mii_bus->priv = dev;
1175 lp->mii_bus->read = r6040_mdiobus_read;
1176 lp->mii_bus->write = r6040_mdiobus_write;
1177 lp->mii_bus->reset = r6040_mdiobus_reset;
1178 lp->mii_bus->name = "r6040_eth_mii";
817380e1
FF		 1179 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1180 dev_name(&pdev->dev), card_idx);
3831861b
FF		 1181 lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1182 if (!lp->mii_bus->irq) {
1183 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
9c86c0f4 1184 err = -ENOMEM;
3831861b
FF		 1185 goto err_out_mdio;
1186 }
1187
1188 for (i = 0; i < PHY_MAX_ADDR; i++)
1189 lp->mii_bus->irq[i] = PHY_POLL;
1190
1191 err = mdiobus_register(lp->mii_bus);
1192 if (err) {
1193 dev_err(&pdev->dev, "failed to register MII bus\n");
1194 goto err_out_mdio_irq;
1195 }
1196
1197 err = r6040_mii_probe(dev);
1198 if (err) {
1199 dev_err(&pdev->dev, "failed to probe MII bus\n");
1200 goto err_out_mdio_unregister;
1201 }
1202
7a47dd7a
SW		 1203 /* Register net device. After this dev->name assign */
1204 err = register_netdev(dev);
1205 if (err) {
7d53b809 1206 dev_err(&pdev->dev, "Failed to register net device\n");
3831861b 1207 goto err_out_mdio_unregister;
7a47dd7a
SW		 1208 }
1209 return 0;
1210
3831861b
FF		 1211err_out_mdio_unregister:
1212 mdiobus_unregister(lp->mii_bus);
1213err_out_mdio_irq:
1214 kfree(lp->mii_bus->irq);
1215err_out_mdio:
1216 mdiobus_free(lp->mii_bus);
b0e45390
FF		 1217err_out_unmap:
1218 pci_iounmap(pdev, ioaddr);
1219err_out_free_res:
7a47dd7a 1220 pci_release_regions(pdev);
b0e45390 1221err_out_free_dev:
7a47dd7a 1222 free_netdev(dev);
b0e45390 1223err_out:
7a47dd7a
SW		 1224 return err;
1225}
1226
1227static void __devexit r6040_remove_one(struct pci_dev *pdev)
1228{
1229 struct net_device *dev = pci_get_drvdata(pdev);
3831861b 1230 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 1231
1232 unregister_netdev(dev);
3831861b
FF		 1233 mdiobus_unregister(lp->mii_bus);
1234 kfree(lp->mii_bus->irq);
1235 mdiobus_free(lp->mii_bus);
7a47dd7a
SW		 1236 pci_release_regions(pdev);
1237 free_netdev(dev);
1238 pci_disable_device(pdev);
1239 pci_set_drvdata(pdev, NULL);
1240}
1241
1242
a3aa1884 1243static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
5ac5d616
FR		 1244 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1245 { 0 }
7a47dd7a
SW		 1246};
1247MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1248
1249static struct pci_driver r6040_driver = {
5ac5d616 1250 .name = DRV_NAME,
7a47dd7a
SW		 1251 .id_table = r6040_pci_tbl,
1252 .probe = r6040_init_one,
1253 .remove = __devexit_p(r6040_remove_one),
1254};
1255
1256
1257static int __init r6040_init(void)
1258{
1259 return pci_register_driver(&r6040_driver);
1260}
1261
1262
1263static void __exit r6040_cleanup(void)
1264{
1265 pci_unregister_driver(&r6040_driver);
1266}
1267
1268module_init(r6040_init);
1269module_exit(r6040_cleanup);
Linux kernel - Deliverables
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