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Merge tag 'dax-misc-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm...
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
9c14ceaf 87#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 107#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 108
109enum mac_version {
85bffe6c
FR		 110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
70090424 143 RTL_GIGA_MAC_VER_34,
c2218925
HW		 144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
7e18dca1 146 RTL_GIGA_MAC_VER_37,
b3d7b2f2 147 RTL_GIGA_MAC_VER_38,
5598bfe5 148 RTL_GIGA_MAC_VER_39,
c558386b
HW		 149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
57538c4a 151 RTL_GIGA_MAC_VER_42,
58152cd4 152 RTL_GIGA_MAC_VER_43,
45dd95c4 153 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
85bffe6c 161 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 162};
163
2b7b4318
FR		 164enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167};
168
d58d46b5
FR		 169#define JUMBO_1K ETH_DATA_LEN
170#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175#define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181}
1da177e4 182
3c6bee1d 183static const struct {
1da177e4 184 const char *name;
2b7b4318 185 enum rtl_tx_desc_version txd_version;
953a12cc 186 const char *fw_name;
d58d46b5
FR		 187 u16 jumbo_max;
188 bool jumbo_tx_csum;
85bffe6c
FR		 189} rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
d58d46b5 192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 193 [RTL_GIGA_MAC_VER_02] =
d58d46b5 194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 195 [RTL_GIGA_MAC_VER_03] =
d58d46b5 196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 197 [RTL_GIGA_MAC_VER_04] =
d58d46b5 198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 199 [RTL_GIGA_MAC_VER_05] =
d58d46b5 200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 201 [RTL_GIGA_MAC_VER_06] =
d58d46b5 202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
d58d46b5 205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_08] =
d58d46b5 207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_09] =
d58d46b5 209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_10] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_11] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_12] =
d58d46b5 215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_13] =
d58d46b5 217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 218 [RTL_GIGA_MAC_VER_14] =
d58d46b5 219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 220 [RTL_GIGA_MAC_VER_15] =
d58d46b5 221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 222 [RTL_GIGA_MAC_VER_16] =
d58d46b5 223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 224 [RTL_GIGA_MAC_VER_17] =
f75761b6 225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_18] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_19] =
d58d46b5 229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_20] =
d58d46b5 231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_21] =
d58d46b5 233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_22] =
d58d46b5 235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_23] =
d58d46b5 237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_24] =
d58d46b5 239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_27] =
d58d46b5 247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 248 [RTL_GIGA_MAC_VER_28] =
d58d46b5 249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 250 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
85bffe6c 253 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
85bffe6c 256 [RTL_GIGA_MAC_VER_31] =
d58d46b5 257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 258 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
85bffe6c 261 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
70090424 264 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
c2218925 267 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
c2218925 270 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
7e18dca1
HW		 273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
b3d7b2f2
HW		 276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
5598bfe5
HW		 279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
c558386b 282 [RTL_GIGA_MAC_VER_40] =
beb330a4 283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
58152cd4 290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
45dd95c4 293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
6e1d0b89
CHL		 296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
935e2218
CHL		 308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
953a12cc 317};
85bffe6c 318#undef _R
953a12cc 319
bcf0bf90
FR		 320enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324};
325
9baa3c34 326static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 340 { 0x0001, 0x8168,
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 342 {0,},
343};
344
345MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
346
6f0333b8 347static int rx_buf_sz = 16383;
27896c83 348static int use_dac = -1;
b57b7e5a
SH		 349static struct {
350 u32 msg_enable;
351} debug = { -1 };
1da177e4 352
07d3f51f
FR		 353enum rtl_registers {
354 MAC0 = 0, /* Ethernet hardware address. */
773d2021 355 MAC4 = 4,
07d3f51f
FR		 356 MAR0 = 8, /* Multicast filter. */
357 CounterAddrLow = 0x10,
358 CounterAddrHigh = 0x14,
359 TxDescStartAddrLow = 0x20,
360 TxDescStartAddrHigh = 0x24,
361 TxHDescStartAddrLow = 0x28,
362 TxHDescStartAddrHigh = 0x2c,
363 FLASH = 0x30,
364 ERSR = 0x36,
365 ChipCmd = 0x37,
366 TxPoll = 0x38,
367 IntrMask = 0x3c,
368 IntrStatus = 0x3e,
4f6b00e5 369
07d3f51f 370 TxConfig = 0x40,
4f6b00e5
HW		 371#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 373
4f6b00e5
HW		 374 RxConfig = 0x44,
375#define RX128_INT_EN (1 << 15) /* 8111c and later */
376#define RX_MULTI_EN (1 << 14) /* 8111c only */
377#define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 380#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 381#define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 384
07d3f51f
FR		 385 RxMissed = 0x4c,
386 Cfg9346 = 0x50,
387 Config0 = 0x51,
388 Config1 = 0x52,
389 Config2 = 0x53,
d387b427
FR		 390#define PME_SIGNAL (1 << 5) /* 8168c and later */
391
07d3f51f
FR		 392 Config3 = 0x54,
393 Config4 = 0x55,
394 Config5 = 0x56,
395 MultiIntr = 0x5c,
396 PHYAR = 0x60,
07d3f51f
FR		 397 PHYstatus = 0x6c,
398 RxMaxSize = 0xda,
399 CPlusCmd = 0xe0,
400 IntrMitigate = 0xe2,
401 RxDescAddrLow = 0xe4,
402 RxDescAddrHigh = 0xe8,
f0298f81 403 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
404
405#define NoEarlyTx 0x3f /* Max value : no early transmit. */
406
407 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
408
409#define TxPacketMax (8064 >> 7)
3090bd9a 410#define EarlySize 0x27
f0298f81 411
07d3f51f
FR		 412 FuncEvent = 0xf0,
413 FuncEventMask = 0xf4,
414 FuncPresetState = 0xf8,
935e2218
CHL		 415 IBCR0 = 0xf8,
416 IBCR2 = 0xf9,
417 IBIMR0 = 0xfa,
418 IBISR0 = 0xfb,
07d3f51f 419 FuncForceEvent = 0xfc,
1da177e4
LT		 420};
421
f162a5d1
FR		 422enum rtl8110_registers {
423 TBICSR = 0x64,
424 TBI_ANAR = 0x68,
425 TBI_LPAR = 0x6a,
426};
427
428enum rtl8168_8101_registers {
429 CSIDR = 0x64,
430 CSIAR = 0x68,
431#define CSIAR_FLAG 0x80000000
432#define CSIAR_WRITE_CMD 0x80000000
433#define CSIAR_BYTE_ENABLE 0x0f
434#define CSIAR_BYTE_ENABLE_SHIFT 12
435#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 436#define CSIAR_FUNC_CARD 0x00000000
437#define CSIAR_FUNC_SDIO 0x00010000
438#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 439#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 440 PMCH = 0x6f,
f162a5d1
FR		 441 EPHYAR = 0x80,
442#define EPHYAR_FLAG 0x80000000
443#define EPHYAR_WRITE_CMD 0x80000000
444#define EPHYAR_REG_MASK 0x1f
445#define EPHYAR_REG_SHIFT 16
446#define EPHYAR_DATA_MASK 0xffff
5a5e4443 447 DLLPR = 0xd0,
4f6b00e5 448#define PFM_EN (1 << 6)
6e1d0b89 449#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 450 DBG_REG = 0xd1,
451#define FIX_NAK_1 (1 << 4)
452#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 453 TWSI = 0xd2,
454 MCU = 0xd3,
4f6b00e5 455#define NOW_IS_OOB (1 << 7)
c558386b
HW		 456#define TX_EMPTY (1 << 5)
457#define RX_EMPTY (1 << 4)
458#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 459#define EN_NDP (1 << 3)
460#define EN_OOB_RESET (1 << 2)
c558386b 461#define LINK_LIST_RDY (1 << 1)
daf9df6d 462 EFUSEAR = 0xdc,
463#define EFUSEAR_FLAG 0x80000000
464#define EFUSEAR_WRITE_CMD 0x80000000
465#define EFUSEAR_READ_CMD 0x00000000
466#define EFUSEAR_REG_MASK 0x03ff
467#define EFUSEAR_REG_SHIFT 8
468#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 469 MISC_1 = 0xf2,
470#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 471};
472
c0e45c1c 473enum rtl8168_registers {
4f6b00e5
HW		 474 LED_FREQ = 0x1a,
475 EEE_LED = 0x1b,
b646d900 476 ERIDR = 0x70,
477 ERIAR = 0x74,
478#define ERIAR_FLAG 0x80000000
479#define ERIAR_WRITE_CMD 0x80000000
480#define ERIAR_READ_CMD 0x00000000
481#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 482#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 483#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 486#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 487#define ERIAR_MASK_SHIFT 12
488#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 490#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 491#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 492#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 493 EPHY_RXER_NUM = 0x7c,
494 OCPDR = 0xb0, /* OCP GPHY access */
495#define OCPDR_WRITE_CMD 0x80000000
496#define OCPDR_READ_CMD 0x00000000
497#define OCPDR_REG_MASK 0x7f
498#define OCPDR_GPHY_REG_SHIFT 16
499#define OCPDR_DATA_MASK 0xffff
500 OCPAR = 0xb4,
501#define OCPAR_FLAG 0x80000000
502#define OCPAR_GPHY_WRITE_CMD 0x8000f060
503#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 504 GPHY_OCP = 0xb8,
01dc7fec 505 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC = 0xf0, /* 8168e only. */
cecb5fd7 507#define TXPLA_RST (1 << 29)
5598bfe5 508#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 509#define PWM_EN (1 << 22)
c558386b 510#define RXDV_GATED_EN (1 << 19)
5598bfe5 511#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 512};
513
07d3f51f 514enum rtl_register_content {
1da177e4 515 /* InterruptStatusBits */
07d3f51f
FR		 516 SYSErr = 0x8000,
517 PCSTimeout = 0x4000,
518 SWInt = 0x0100,
519 TxDescUnavail = 0x0080,
520 RxFIFOOver = 0x0040,
521 LinkChg = 0x0020,
522 RxOverflow = 0x0010,
523 TxErr = 0x0008,
524 TxOK = 0x0004,
525 RxErr = 0x0002,
526 RxOK = 0x0001,
1da177e4
LT		 527
528 /* RxStatusDesc */
e03f33af 529 RxBOVF = (1 << 24),
9dccf611
FR		 530 RxFOVF = (1 << 23),
531 RxRWT = (1 << 22),
532 RxRES = (1 << 21),
533 RxRUNT = (1 << 20),
534 RxCRC = (1 << 19),
1da177e4
LT		 535
536 /* ChipCmdBits */
4f6b00e5 537 StopReq = 0x80,
07d3f51f
FR		 538 CmdReset = 0x10,
539 CmdRxEnb = 0x08,
540 CmdTxEnb = 0x04,
541 RxBufEmpty = 0x01,
1da177e4 542
275391a4
FR		 543 /* TXPoll register p.5 */
544 HPQ = 0x80, /* Poll cmd on the high prio queue */
545 NPQ = 0x40, /* Poll cmd on the low prio queue */
546 FSWInt = 0x01, /* Forced software interrupt */
547
1da177e4 548 /* Cfg9346Bits */
07d3f51f
FR		 549 Cfg9346_Lock = 0x00,
550 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 551
552 /* rx_mode_bits */
07d3f51f
FR		 553 AcceptErr = 0x20,
554 AcceptRunt = 0x10,
555 AcceptBroadcast = 0x08,
556 AcceptMulticast = 0x04,
557 AcceptMyPhys = 0x02,
558 AcceptAllPhys = 0x01,
1687b566 559#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 560
1da177e4
LT		 561 /* TxConfigBits */
562 TxInterFrameGapShift = 24,
563 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
564
5d06a99f 565 /* Config1 register p.24 */
f162a5d1
FR		 566 LEDS1 = (1 << 7),
567 LEDS0 = (1 << 6),
f162a5d1
FR		 568 Speed_down = (1 << 4),
569 MEMMAP = (1 << 3),
570 IOMAP = (1 << 2),
571 VPD = (1 << 1),
5d06a99f
FR		 572 PMEnable = (1 << 0), /* Power Management Enable */
573
6dccd16b 574 /* Config2 register p. 25 */
57538c4a 575 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 576 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 577 PCI_Clock_66MHz = 0x01,
578 PCI_Clock_33MHz = 0x00,
579
61a4dcc2
FR		 580 /* Config3 register p.25 */
581 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 583 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 584 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 585 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 586
d58d46b5
FR		 587 /* Config4 register */
588 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
589
5d06a99f 590 /* Config5 register p.27 */
61a4dcc2
FR		 591 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF = (1 << 5), /* Accept Multicast wakeup frame */
593 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 594 Spi_en = (1 << 3),
61a4dcc2 595 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 596 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 597 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 598
1da177e4
LT		 599 /* TBICSR p.28 */
600 TBIReset = 0x80000000,
601 TBILoopback = 0x40000000,
602 TBINwEnable = 0x20000000,
603 TBINwRestart = 0x10000000,
604 TBILinkOk = 0x02000000,
605 TBINwComplete = 0x01000000,
606
607 /* CPlusCmd p.31 */
f162a5d1
FR		 608 EnableBist = (1 << 15), // 8168 8101
609 Mac_dbgo_oe = (1 << 14), // 8168 8101
610 Normal_mode = (1 << 13), // unused
611 Force_half_dup = (1 << 12), // 8168 8101
612 Force_rxflow_en = (1 << 11), // 8168 8101
613 Force_txflow_en = (1 << 10), // 8168 8101
614 Cxpl_dbg_sel = (1 << 9), // 8168 8101
615 ASF = (1 << 8), // 8168 8101
616 PktCntrDisable = (1 << 7), // 8168 8101
617 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 618 RxVlan = (1 << 6),
619 RxChkSum = (1 << 5),
620 PCIDAC = (1 << 4),
621 PCIMulRW = (1 << 3),
0e485150
FR		 622 INTT_0 = 0x0000, // 8168
623 INTT_1 = 0x0001, // 8168
624 INTT_2 = 0x0002, // 8168
625 INTT_3 = 0x0003, // 8168
1da177e4
LT		 626
627 /* rtl8169_PHYstatus */
07d3f51f
FR		 628 TBI_Enable = 0x80,
629 TxFlowCtrl = 0x40,
630 RxFlowCtrl = 0x20,
631 _1000bpsF = 0x10,
632 _100bps = 0x08,
633 _10bps = 0x04,
634 LinkStatus = 0x02,
635 FullDup = 0x01,
1da177e4 636
1da177e4 637 /* _TBICSRBit */
07d3f51f 638 TBILinkOK = 0x02000000,
d4a3a0fc 639
6e85d5ad
CV		 640 /* ResetCounterCommand */
641 CounterReset = 0x1,
642
d4a3a0fc 643 /* DumpCounterCommand */
07d3f51f 644 CounterDump = 0x8,
6e1d0b89
CHL		 645
646 /* magic enable v2 */
647 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 648};
649
2b7b4318
FR		 650enum rtl_desc_bit {
651 /* First doubleword. */
1da177e4
LT		 652 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
653 RingEnd = (1 << 30), /* End of descriptor ring */
654 FirstFrag = (1 << 29), /* First segment of a packet */
655 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 656};
657
658/* Generic case. */
659enum rtl_tx_desc_bit {
660 /* First doubleword. */
661 TD_LSO = (1 << 27), /* Large Send Offload */
662#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 663
2b7b4318
FR		 664 /* Second doubleword. */
665 TxVlanTag = (1 << 17), /* Add VLAN tag */
666};
667
668/* 8169, 8168b and 810x except 8102e. */
669enum rtl_tx_desc_bit_0 {
670 /* First doubleword. */
671#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
672 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
673 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
674 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
675};
676
677/* 8102e, 8168c and beyond. */
678enum rtl_tx_desc_bit_1 {
bdfa4ed6 679 /* First doubleword. */
680 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 681 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 682#define GTTCPHO_SHIFT 18
e974604b 683#define GTTCPHO_MAX 0x7fU
bdfa4ed6 684
2b7b4318 685 /* Second doubleword. */
e974604b 686#define TCPHO_SHIFT 18
687#define TCPHO_MAX 0x3ffU
2b7b4318 688#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 689 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
690 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 691 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
692 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
693};
1da177e4 694
2b7b4318 695enum rtl_rx_desc_bit {
1da177e4
LT		 696 /* Rx private */
697 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
698 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
699
700#define RxProtoUDP (PID1)
701#define RxProtoTCP (PID0)
702#define RxProtoIP (PID1 | PID0)
703#define RxProtoMask RxProtoIP
704
705 IPFail = (1 << 16), /* IP checksum failed */
706 UDPFail = (1 << 15), /* UDP/IP checksum failed */
707 TCPFail = (1 << 14), /* TCP/IP checksum failed */
708 RxVlanTag = (1 << 16), /* VLAN tag available */
709};
710
711#define RsvdMask 0x3fffc000
712
713struct TxDesc {
6cccd6e7
REB		 714 __le32 opts1;
715 __le32 opts2;
716 __le64 addr;
1da177e4
LT		 717};
718
719struct RxDesc {
6cccd6e7
REB		 720 __le32 opts1;
721 __le32 opts2;
722 __le64 addr;
1da177e4
LT		 723};
724
725struct ring_info {
726 struct sk_buff *skb;
727 u32 len;
728 u8 __pad[sizeof(void *) - sizeof(u32)];
729};
730
f23e7fda 731enum features {
ccdffb9a
FR		 732 RTL_FEATURE_WOL = (1 << 0),
733 RTL_FEATURE_MSI = (1 << 1),
734 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 735};
736
355423d0
IV		 737struct rtl8169_counters {
738 __le64 tx_packets;
739 __le64 rx_packets;
740 __le64 tx_errors;
741 __le32 rx_errors;
742 __le16 rx_missed;
743 __le16 align_errors;
744 __le32 tx_one_collision;
745 __le32 tx_multi_collision;
746 __le64 rx_unicast;
747 __le64 rx_broadcast;
748 __le32 rx_multicast;
749 __le16 tx_aborted;
750 __le16 tx_underun;
751};
752
6e85d5ad
CV		 753struct rtl8169_tc_offsets {
754 bool inited;
755 __le64 tx_errors;
756 __le32 tx_multi_collision;
6e85d5ad
CV		 757 __le16 tx_aborted;
758};
759
da78dbff 760enum rtl_flag {
6c4a70c5 761 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 762 RTL_FLAG_TASK_SLOW_PENDING,
763 RTL_FLAG_TASK_RESET_PENDING,
764 RTL_FLAG_TASK_PHY_PENDING,
765 RTL_FLAG_MAX
766};
767
8027aa24
JW		 768struct rtl8169_stats {
769 u64 packets;
770 u64 bytes;
771 struct u64_stats_sync syncp;
772};
773
1da177e4
LT		 774struct rtl8169_private {
775 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 776 struct pci_dev *pci_dev;
c4028958 777 struct net_device *dev;
bea3348e 778 struct napi_struct napi;
b57b7e5a 779 u32 msg_enable;
2b7b4318
FR		 780 u16 txd_version;
781 u16 mac_version;
1da177e4
LT		 782 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
783 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 784 u32 dirty_tx;
8027aa24
JW		 785 struct rtl8169_stats rx_stats;
786 struct rtl8169_stats tx_stats;
1da177e4
LT		 787 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
788 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
789 dma_addr_t TxPhyAddr;
790 dma_addr_t RxPhyAddr;
6f0333b8 791 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 792 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 793 struct timer_list timer;
794 u16 cp_cmd;
da78dbff
FR		 795
796 u16 event_slow;
c0e45c1c 797
798 struct mdio_ops {
24192210
FR		 799 void (*write)(struct rtl8169_private *, int, int);
800 int (*read)(struct rtl8169_private *, int);
c0e45c1c 801 } mdio_ops;
802
065c27c1 803 struct pll_power_ops {
804 void (*down)(struct rtl8169_private *);
805 void (*up)(struct rtl8169_private *);
806 } pll_power_ops;
807
d58d46b5
FR		 808 struct jumbo_ops {
809 void (*enable)(struct rtl8169_private *);
810 void (*disable)(struct rtl8169_private *);
811 } jumbo_ops;
812
beb1fe18 813 struct csi_ops {
52989f0e
FR		 814 void (*write)(struct rtl8169_private *, int, int);
815 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 816 } csi_ops;
817
54405cde 818 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 819 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 820 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 821 void (*hw_start)(struct net_device *);
4da19633 822 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 823 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 824 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 825 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 826
827 struct {
da78dbff
FR		 828 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
829 struct mutex mutex;
4422bcd4
FR		 830 struct work_struct work;
831 } wk;
832
f23e7fda 833 unsigned features;
ccdffb9a
FR		 834
835 struct mii_if_info mii;
42020320
CV		 836 dma_addr_t counters_phys_addr;
837 struct rtl8169_counters *counters;
6e85d5ad 838 struct rtl8169_tc_offsets tc_offset;
e1759441 839 u32 saved_wolopts;
e03f33af 840 u32 opts1_mask;
f1e02ed1 841
b6ffd97f
FR		 842 struct rtl_fw {
843 const struct firmware *fw;
1c361efb
FR		 844
845#define RTL_VER_SIZE 32
846
847 char version[RTL_VER_SIZE];
848
849 struct rtl_fw_phy_action {
850 __le32 *code;
851 size_t size;
852 } phy_action;
b6ffd97f 853 } *rtl_fw;
497888cf 854#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 855
856 u32 ocp_base;
1da177e4
LT		 857};
858
979b6c13 859MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 860MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 861module_param(use_dac, int, 0);
4300e8c7 862MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 863module_param_named(debug, debug.msg_enable, int, 0);
864MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 865MODULE_LICENSE("GPL");
866MODULE_VERSION(RTL8169_VERSION);
bca03d5f 867MODULE_FIRMWARE(FIRMWARE_8168D_1);
868MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 869MODULE_FIRMWARE(FIRMWARE_8168E_1);
870MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 871MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 872MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 873MODULE_FIRMWARE(FIRMWARE_8168F_1);
874MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 875MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 876MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 877MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 878MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 879MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 880MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 881MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 882MODULE_FIRMWARE(FIRMWARE_8168H_1);
883MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 884MODULE_FIRMWARE(FIRMWARE_8107E_1);
885MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 886
da78dbff
FR		 887static void rtl_lock_work(struct rtl8169_private *tp)
888{
889 mutex_lock(&tp->wk.mutex);
890}
891
892static void rtl_unlock_work(struct rtl8169_private *tp)
893{
894 mutex_unlock(&tp->wk.mutex);
895}
896
d58d46b5
FR		 897static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
898{
7d7903b2
JL		 899 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
900 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 901}
902
ffc46952
FR		 903struct rtl_cond {
904 bool (*check)(struct rtl8169_private *);
905 const char *msg;
906};
907
908static void rtl_udelay(unsigned int d)
909{
910 udelay(d);
911}
912
913static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
914 void (*delay)(unsigned int), unsigned int d, int n,
915 bool high)
916{
917 int i;
918
919 for (i = 0; i < n; i++) {
920 delay(d);
921 if (c->check(tp) == high)
922 return true;
923 }
82e316ef
FR		 924 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
925 c->msg, !high, n, d);
ffc46952
FR		 926 return false;
927}
928
929static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
930 const struct rtl_cond *c,
931 unsigned int d, int n)
932{
933 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
934}
935
936static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
937 const struct rtl_cond *c,
938 unsigned int d, int n)
939{
940 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
941}
942
943static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
944 const struct rtl_cond *c,
945 unsigned int d, int n)
946{
947 return rtl_loop_wait(tp, c, msleep, d, n, true);
948}
949
950static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
951 const struct rtl_cond *c,
952 unsigned int d, int n)
953{
954 return rtl_loop_wait(tp, c, msleep, d, n, false);
955}
956
957#define DECLARE_RTL_COND(name) \
958static bool name ## _check(struct rtl8169_private *); \
959 \
960static const struct rtl_cond name = { \
961 .check = name ## _check, \
962 .msg = #name \
963}; \
964 \
965static bool name ## _check(struct rtl8169_private *tp)
966
c558386b
HW		 967static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
968{
969 if (reg & 0xffff0001) {
970 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
971 return true;
972 }
973 return false;
974}
975
976DECLARE_RTL_COND(rtl_ocp_gphy_cond)
977{
978 void __iomem *ioaddr = tp->mmio_addr;
979
980 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
981}
982
983static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
984{
985 void __iomem *ioaddr = tp->mmio_addr;
986
987 if (rtl_ocp_reg_failure(tp, reg))
988 return;
989
990 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
991
992 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
993}
994
995static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
996{
997 void __iomem *ioaddr = tp->mmio_addr;
998
999 if (rtl_ocp_reg_failure(tp, reg))
1000 return 0;
1001
1002 RTL_W32(GPHY_OCP, reg << 15);
1003
1004 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1005 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1006}
1007
c558386b
HW		 1008static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1009{
1010 void __iomem *ioaddr = tp->mmio_addr;
1011
1012 if (rtl_ocp_reg_failure(tp, reg))
1013 return;
1014
1015 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1016}
1017
1018static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1019{
1020 void __iomem *ioaddr = tp->mmio_addr;
1021
1022 if (rtl_ocp_reg_failure(tp, reg))
1023 return 0;
1024
1025 RTL_W32(OCPDR, reg << 15);
1026
3a83ad12 1027 return RTL_R32(OCPDR);
c558386b
HW		 1028}
1029
1030#define OCP_STD_PHY_BASE 0xa400
1031
1032static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1033{
1034 if (reg == 0x1f) {
1035 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1036 return;
1037 }
1038
1039 if (tp->ocp_base != OCP_STD_PHY_BASE)
1040 reg -= 0x10;
1041
1042 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1043}
1044
1045static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1046{
1047 if (tp->ocp_base != OCP_STD_PHY_BASE)
1048 reg -= 0x10;
1049
1050 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1051}
1052
eee3786f 1053static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1054{
1055 if (reg == 0x1f) {
1056 tp->ocp_base = value << 4;
1057 return;
1058 }
1059
1060 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1061}
1062
1063static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1064{
1065 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1066}
1067
ffc46952
FR		 1068DECLARE_RTL_COND(rtl_phyar_cond)
1069{
1070 void __iomem *ioaddr = tp->mmio_addr;
1071
1072 return RTL_R32(PHYAR) & 0x80000000;
1073}
1074
24192210 1075static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1076{
24192210 1077 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1078
24192210 1079 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1080
ffc46952 1081 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1082 /*
81a95f04
TT		 1083 * According to hardware specs a 20us delay is required after write
1084 * complete indication, but before sending next command.
024a07ba 1085 */
81a95f04 1086 udelay(20);
1da177e4
LT		 1087}
1088
24192210 1089static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1090{
24192210 1091 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1092 int value;
1da177e4 1093
24192210 1094 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1095
ffc46952
FR		 1096 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1097 RTL_R32(PHYAR) & 0xffff : ~0;
1098
81a95f04
TT		 1099 /*
1100 * According to hardware specs a 20us delay is required after read
1101 * complete indication, but before sending next command.
1102 */
1103 udelay(20);
1104
1da177e4
LT		 1105 return value;
1106}
1107
935e2218
CHL		 1108DECLARE_RTL_COND(rtl_ocpar_cond)
1109{
1110 void __iomem *ioaddr = tp->mmio_addr;
1111
1112 return RTL_R32(OCPAR) & OCPAR_FLAG;
1113}
1114
24192210 1115static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1116{
24192210 1117 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1118
24192210 1119 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1120 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1121 RTL_W32(EPHY_RXER_NUM, 0);
1122
ffc46952 1123 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1124}
1125
24192210 1126static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1127{
24192210
FR		 1128 r8168dp_1_mdio_access(tp, reg,
1129 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1130}
1131
24192210 1132static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1133{
24192210 1134 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1135
24192210 1136 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1137
1138 mdelay(1);
1139 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1140 RTL_W32(EPHY_RXER_NUM, 0);
1141
ffc46952
FR		 1142 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1143 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1144}
1145
e6de30d6 1146#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1147
1148static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1149{
1150 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1151}
1152
1153static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1154{
1155 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1156}
1157
24192210 1158static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1159{
24192210
FR		 1160 void __iomem *ioaddr = tp->mmio_addr;
1161
e6de30d6 1162 r8168dp_2_mdio_start(ioaddr);
1163
24192210 1164 r8169_mdio_write(tp, reg, value);
e6de30d6 1165
1166 r8168dp_2_mdio_stop(ioaddr);
1167}
1168
24192210 1169static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1170{
24192210 1171 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1172 int value;
1173
1174 r8168dp_2_mdio_start(ioaddr);
1175
24192210 1176 value = r8169_mdio_read(tp, reg);
e6de30d6 1177
1178 r8168dp_2_mdio_stop(ioaddr);
1179
1180 return value;
1181}
1182
4da19633 1183static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1184{
24192210 1185 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1186}
1187
4da19633 1188static int rtl_readphy(struct rtl8169_private *tp, int location)
1189{
24192210 1190 return tp->mdio_ops.read(tp, location);
4da19633 1191}
1192
1193static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1194{
1195 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1196}
1197
76564428 1198static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1199{
1200 int val;
1201
4da19633 1202 val = rtl_readphy(tp, reg_addr);
76564428 1203 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1204}
1205
ccdffb9a
FR		 1206static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1207 int val)
1208{
1209 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1210
4da19633 1211 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1212}
1213
1214static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1215{
1216 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1217
4da19633 1218 return rtl_readphy(tp, location);
ccdffb9a
FR		 1219}
1220
ffc46952
FR		 1221DECLARE_RTL_COND(rtl_ephyar_cond)
1222{
1223 void __iomem *ioaddr = tp->mmio_addr;
1224
1225 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1226}
1227
fdf6fc06 1228static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1229{
fdf6fc06 1230 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1231
1232 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1233 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1234
ffc46952
FR		 1235 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1236
1237 udelay(10);
dacf8154
FR		 1238}
1239
fdf6fc06 1240static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1241{
fdf6fc06 1242 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1243
1244 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1245
ffc46952
FR		 1246 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1247 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1248}
1249
935e2218
CHL		 1250DECLARE_RTL_COND(rtl_eriar_cond)
1251{
1252 void __iomem *ioaddr = tp->mmio_addr;
1253
1254 return RTL_R32(ERIAR) & ERIAR_FLAG;
1255}
1256
fdf6fc06
FR		 1257static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1258 u32 val, int type)
133ac40a 1259{
fdf6fc06 1260 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1261
1262 BUG_ON((addr & 3) || (mask == 0));
1263 RTL_W32(ERIDR, val);
1264 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1265
ffc46952 1266 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1267}
1268
fdf6fc06 1269static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1270{
fdf6fc06 1271 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1272
1273 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1274
ffc46952
FR		 1275 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1276 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1277}
1278
706123d0 1279static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1280 u32 m, int type)
133ac40a
HW		 1281{
1282 u32 val;
1283
fdf6fc06
FR		 1284 val = rtl_eri_read(tp, addr, type);
1285 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1286}
1287
935e2218
CHL		 1288static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1289{
1290 void __iomem *ioaddr = tp->mmio_addr;
1291
1292 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1293 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1294 RTL_R32(OCPDR) : ~0;
1295}
1296
1297static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1298{
1299 return rtl_eri_read(tp, reg, ERIAR_OOB);
1300}
1301
1302static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1303{
1304 switch (tp->mac_version) {
1305 case RTL_GIGA_MAC_VER_27:
1306 case RTL_GIGA_MAC_VER_28:
1307 case RTL_GIGA_MAC_VER_31:
1308 return r8168dp_ocp_read(tp, mask, reg);
1309 case RTL_GIGA_MAC_VER_49:
1310 case RTL_GIGA_MAC_VER_50:
1311 case RTL_GIGA_MAC_VER_51:
1312 return r8168ep_ocp_read(tp, mask, reg);
1313 default:
1314 BUG();
1315 return ~0;
1316 }
1317}
1318
1319static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1320 u32 data)
1321{
1322 void __iomem *ioaddr = tp->mmio_addr;
1323
1324 RTL_W32(OCPDR, data);
1325 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1326 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1327}
1328
1329static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1330 u32 data)
1331{
1332 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1333 data, ERIAR_OOB);
1334}
1335
1336static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1337{
1338 switch (tp->mac_version) {
1339 case RTL_GIGA_MAC_VER_27:
1340 case RTL_GIGA_MAC_VER_28:
1341 case RTL_GIGA_MAC_VER_31:
1342 r8168dp_ocp_write(tp, mask, reg, data);
1343 break;
1344 case RTL_GIGA_MAC_VER_49:
1345 case RTL_GIGA_MAC_VER_50:
1346 case RTL_GIGA_MAC_VER_51:
1347 r8168ep_ocp_write(tp, mask, reg, data);
1348 break;
1349 default:
1350 BUG();
1351 break;
1352 }
1353}
1354
2a9b4d96
CHL		 1355static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1356{
1357 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1358
1359 ocp_write(tp, 0x1, 0x30, 0x00000001);
1360}
1361
1362#define OOB_CMD_RESET 0x00
1363#define OOB_CMD_DRIVER_START 0x05
1364#define OOB_CMD_DRIVER_STOP 0x06
1365
1366static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1367{
1368 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1369}
1370
1371DECLARE_RTL_COND(rtl_ocp_read_cond)
1372{
1373 u16 reg;
1374
1375 reg = rtl8168_get_ocp_reg(tp);
1376
1377 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1378}
1379
935e2218 1380DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1381{
935e2218
CHL		 1382 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1383}
1384
1385DECLARE_RTL_COND(rtl_ocp_tx_cond)
1386{
1387 void __iomem *ioaddr = tp->mmio_addr;
1388
1389 return RTL_R8(IBISR0) & 0x02;
1390}
2a9b4d96 1391
003609da
CHL		 1392static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1393{
1394 void __iomem *ioaddr = tp->mmio_addr;
1395
1396 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1397 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1398 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1399 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1400}
1401
935e2218
CHL		 1402static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1403{
1404 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1405 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1406}
1407
935e2218 1408static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1409{
935e2218
CHL		 1410 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1411 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1412 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1413}
1414
1415static void rtl8168_driver_start(struct rtl8169_private *tp)
1416{
1417 switch (tp->mac_version) {
1418 case RTL_GIGA_MAC_VER_27:
1419 case RTL_GIGA_MAC_VER_28:
1420 case RTL_GIGA_MAC_VER_31:
1421 rtl8168dp_driver_start(tp);
1422 break;
1423 case RTL_GIGA_MAC_VER_49:
1424 case RTL_GIGA_MAC_VER_50:
1425 case RTL_GIGA_MAC_VER_51:
1426 rtl8168ep_driver_start(tp);
1427 break;
1428 default:
1429 BUG();
1430 break;
1431 }
1432}
2a9b4d96 1433
935e2218
CHL		 1434static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1435{
1436 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1437 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1438}
1439
935e2218
CHL		 1440static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1441{
003609da 1442 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1443 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1444 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1445 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1446}
1447
1448static void rtl8168_driver_stop(struct rtl8169_private *tp)
1449{
1450 switch (tp->mac_version) {
1451 case RTL_GIGA_MAC_VER_27:
1452 case RTL_GIGA_MAC_VER_28:
1453 case RTL_GIGA_MAC_VER_31:
1454 rtl8168dp_driver_stop(tp);
1455 break;
1456 case RTL_GIGA_MAC_VER_49:
1457 case RTL_GIGA_MAC_VER_50:
1458 case RTL_GIGA_MAC_VER_51:
1459 rtl8168ep_driver_stop(tp);
1460 break;
1461 default:
1462 BUG();
1463 break;
1464 }
1465}
1466
1467static int r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1468{
1469 u16 reg = rtl8168_get_ocp_reg(tp);
1470
1471 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1472}
1473
935e2218
CHL		 1474static int r8168ep_check_dash(struct rtl8169_private *tp)
1475{
1476 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1477}
1478
1479static int r8168_check_dash(struct rtl8169_private *tp)
1480{
1481 switch (tp->mac_version) {
1482 case RTL_GIGA_MAC_VER_27:
1483 case RTL_GIGA_MAC_VER_28:
1484 case RTL_GIGA_MAC_VER_31:
1485 return r8168dp_check_dash(tp);
1486 case RTL_GIGA_MAC_VER_49:
1487 case RTL_GIGA_MAC_VER_50:
1488 case RTL_GIGA_MAC_VER_51:
1489 return r8168ep_check_dash(tp);
1490 default:
1491 return 0;
1492 }
1493}
1494
c28aa385 1495struct exgmac_reg {
1496 u16 addr;
1497 u16 mask;
1498 u32 val;
1499};
1500
fdf6fc06 1501static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1502 const struct exgmac_reg *r, int len)
1503{
1504 while (len-- > 0) {
fdf6fc06 1505 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1506 r++;
1507 }
1508}
1509
ffc46952
FR		 1510DECLARE_RTL_COND(rtl_efusear_cond)
1511{
1512 void __iomem *ioaddr = tp->mmio_addr;
1513
1514 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1515}
1516
fdf6fc06 1517static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1518{
fdf6fc06 1519 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1520
1521 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1522
ffc46952
FR		 1523 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1524 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1525}
1526
9085cdfa
FR		 1527static u16 rtl_get_events(struct rtl8169_private *tp)
1528{
1529 void __iomem *ioaddr = tp->mmio_addr;
1530
1531 return RTL_R16(IntrStatus);
1532}
1533
1534static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1535{
1536 void __iomem *ioaddr = tp->mmio_addr;
1537
1538 RTL_W16(IntrStatus, bits);
1539 mmiowb();
1540}
1541
1542static void rtl_irq_disable(struct rtl8169_private *tp)
1543{
1544 void __iomem *ioaddr = tp->mmio_addr;
1545
1546 RTL_W16(IntrMask, 0);
1547 mmiowb();
1548}
1549
3e990ff5
FR		 1550static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1551{
1552 void __iomem *ioaddr = tp->mmio_addr;
1553
1554 RTL_W16(IntrMask, bits);
1555}
1556
da78dbff
FR		 1557#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1558#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1559#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1560
1561static void rtl_irq_enable_all(struct rtl8169_private *tp)
1562{
1563 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1564}
1565
811fd301 1566static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1567{
811fd301 1568 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1569
9085cdfa 1570 rtl_irq_disable(tp);
da78dbff 1571 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1572 RTL_R8(ChipCmd);
1da177e4
LT		 1573}
1574
4da19633 1575static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1576{
4da19633 1577 void __iomem *ioaddr = tp->mmio_addr;
1578
1da177e4
LT		 1579 return RTL_R32(TBICSR) & TBIReset;
1580}
1581
4da19633 1582static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1583{
4da19633 1584 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1585}
1586
1587static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1588{
1589 return RTL_R32(TBICSR) & TBILinkOk;
1590}
1591
1592static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1593{
1594 return RTL_R8(PHYstatus) & LinkStatus;
1595}
1596
4da19633 1597static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1598{
4da19633 1599 void __iomem *ioaddr = tp->mmio_addr;
1600
1da177e4
LT		 1601 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1602}
1603
4da19633 1604static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1605{
1606 unsigned int val;
1607
4da19633 1608 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1609 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1610}
1611
70090424
HW		 1612static void rtl_link_chg_patch(struct rtl8169_private *tp)
1613{
1614 void __iomem *ioaddr = tp->mmio_addr;
1615 struct net_device *dev = tp->dev;
1616
1617 if (!netif_running(dev))
1618 return;
1619
b3d7b2f2
HW		 1620 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1621 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1622 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1623 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1624 ERIAR_EXGMAC);
1625 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1626 ERIAR_EXGMAC);
70090424 1627 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1628 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1629 ERIAR_EXGMAC);
1630 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1631 ERIAR_EXGMAC);
70090424 1632 } else {
fdf6fc06
FR		 1633 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1634 ERIAR_EXGMAC);
1635 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1636 ERIAR_EXGMAC);
70090424
HW		 1637 }
1638 /* Reset packet filter */
706123d0 1639 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1640 ERIAR_EXGMAC);
706123d0 1641 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1642 ERIAR_EXGMAC);
c2218925
HW		 1643 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1644 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1645 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1646 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1647 ERIAR_EXGMAC);
1648 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1649 ERIAR_EXGMAC);
c2218925 1650 } else {
fdf6fc06
FR		 1651 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1652 ERIAR_EXGMAC);
1653 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1654 ERIAR_EXGMAC);
c2218925 1655 }
7e18dca1
HW		 1656 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1657 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1658 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1659 ERIAR_EXGMAC);
1660 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1661 ERIAR_EXGMAC);
7e18dca1 1662 } else {
fdf6fc06
FR		 1663 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1664 ERIAR_EXGMAC);
7e18dca1 1665 }
70090424
HW		 1666 }
1667}
1668
e4fbce74 1669static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1670 struct rtl8169_private *tp,
1671 void __iomem *ioaddr, bool pm)
1da177e4 1672{
1da177e4 1673 if (tp->link_ok(ioaddr)) {
70090424 1674 rtl_link_chg_patch(tp);
e1759441 1675 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1676 if (pm)
1677 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1678 netif_carrier_on(dev);
1519e57f
FR		 1679 if (net_ratelimit())
1680 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1681 } else {
1da177e4 1682 netif_carrier_off(dev);
bf82c189 1683 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1684 if (pm)
10953db8 1685 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1686 }
1da177e4
LT		 1687}
1688
e4fbce74
RW		 1689static void rtl8169_check_link_status(struct net_device *dev,
1690 struct rtl8169_private *tp,
1691 void __iomem *ioaddr)
1692{
1693 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1694}
1695
e1759441
RW		 1696#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1697
1698static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1699{
61a4dcc2
FR		 1700 void __iomem *ioaddr = tp->mmio_addr;
1701 u8 options;
e1759441 1702 u32 wolopts = 0;
61a4dcc2
FR		 1703
1704 options = RTL_R8(Config1);
1705 if (!(options & PMEnable))
e1759441 1706 return 0;
61a4dcc2
FR		 1707
1708 options = RTL_R8(Config3);
1709 if (options & LinkUp)
e1759441 1710 wolopts |= WAKE_PHY;
6e1d0b89 1711 switch (tp->mac_version) {
ac85bcdb
CHL		 1712 case RTL_GIGA_MAC_VER_34:
1713 case RTL_GIGA_MAC_VER_35:
1714 case RTL_GIGA_MAC_VER_36:
1715 case RTL_GIGA_MAC_VER_37:
1716 case RTL_GIGA_MAC_VER_38:
1717 case RTL_GIGA_MAC_VER_40:
1718 case RTL_GIGA_MAC_VER_41:
1719 case RTL_GIGA_MAC_VER_42:
1720 case RTL_GIGA_MAC_VER_43:
1721 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1722 case RTL_GIGA_MAC_VER_45:
1723 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1724 case RTL_GIGA_MAC_VER_47:
1725 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1726 case RTL_GIGA_MAC_VER_49:
1727 case RTL_GIGA_MAC_VER_50:
1728 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1729 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1730 wolopts |= WAKE_MAGIC;
1731 break;
1732 default:
1733 if (options & MagicPacket)
1734 wolopts |= WAKE_MAGIC;
1735 break;
1736 }
61a4dcc2
FR		 1737
1738 options = RTL_R8(Config5);
1739 if (options & UWF)
e1759441 1740 wolopts |= WAKE_UCAST;
61a4dcc2 1741 if (options & BWF)
e1759441 1742 wolopts |= WAKE_BCAST;
61a4dcc2 1743 if (options & MWF)
e1759441 1744 wolopts |= WAKE_MCAST;
61a4dcc2 1745
e1759441 1746 return wolopts;
61a4dcc2
FR		 1747}
1748
e1759441 1749static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1750{
1751 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1752
da78dbff 1753 rtl_lock_work(tp);
e1759441
RW		 1754
1755 wol->supported = WAKE_ANY;
1756 wol->wolopts = __rtl8169_get_wol(tp);
1757
da78dbff 1758 rtl_unlock_work(tp);
e1759441
RW		 1759}
1760
1761static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1762{
61a4dcc2 1763 void __iomem *ioaddr = tp->mmio_addr;
6e1d0b89 1764 unsigned int i, tmp;
350f7596 1765 static const struct {
61a4dcc2
FR		 1766 u32 opt;
1767 u16 reg;
1768 u8 mask;
1769 } cfg[] = {
61a4dcc2 1770 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1771 { WAKE_UCAST, Config5, UWF },
1772 { WAKE_BCAST, Config5, BWF },
1773 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1774 { WAKE_ANY, Config5, LanWake },
1775 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1776 };
851e6022 1777 u8 options;
61a4dcc2 1778
61a4dcc2
FR		 1779 RTL_W8(Cfg9346, Cfg9346_Unlock);
1780
6e1d0b89 1781 switch (tp->mac_version) {
ac85bcdb
CHL		 1782 case RTL_GIGA_MAC_VER_34:
1783 case RTL_GIGA_MAC_VER_35:
1784 case RTL_GIGA_MAC_VER_36:
1785 case RTL_GIGA_MAC_VER_37:
1786 case RTL_GIGA_MAC_VER_38:
1787 case RTL_GIGA_MAC_VER_40:
1788 case RTL_GIGA_MAC_VER_41:
1789 case RTL_GIGA_MAC_VER_42:
1790 case RTL_GIGA_MAC_VER_43:
1791 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1792 case RTL_GIGA_MAC_VER_45:
1793 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1794 case RTL_GIGA_MAC_VER_47:
1795 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1796 case RTL_GIGA_MAC_VER_49:
1797 case RTL_GIGA_MAC_VER_50:
1798 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1799 tmp = ARRAY_SIZE(cfg) - 1;
1800 if (wolopts & WAKE_MAGIC)
706123d0 1801 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1802 0x0dc,
1803 ERIAR_MASK_0100,
1804 MagicPacket_v2,
1805 0x0000,
1806 ERIAR_EXGMAC);
1807 else
706123d0 1808 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1809 0x0dc,
1810 ERIAR_MASK_0100,
1811 0x0000,
1812 MagicPacket_v2,
1813 ERIAR_EXGMAC);
1814 break;
1815 default:
1816 tmp = ARRAY_SIZE(cfg);
1817 break;
1818 }
1819
1820 for (i = 0; i < tmp; i++) {
851e6022 1821 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1822 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1823 options |= cfg[i].mask;
1824 RTL_W8(cfg[i].reg, options);
1825 }
1826
851e6022
FR		 1827 switch (tp->mac_version) {
1828 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1829 options = RTL_R8(Config1) & ~PMEnable;
1830 if (wolopts)
1831 options |= PMEnable;
1832 RTL_W8(Config1, options);
1833 break;
1834 default:
d387b427
FR		 1835 options = RTL_R8(Config2) & ~PME_SIGNAL;
1836 if (wolopts)
1837 options |= PME_SIGNAL;
1838 RTL_W8(Config2, options);
851e6022
FR		 1839 break;
1840 }
1841
61a4dcc2 1842 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1843}
1844
1845static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1846{
1847 struct rtl8169_private *tp = netdev_priv(dev);
1848
da78dbff 1849 rtl_lock_work(tp);
61a4dcc2 1850
f23e7fda
FR		 1851 if (wol->wolopts)
1852 tp->features |= RTL_FEATURE_WOL;
1853 else
1854 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1855 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1856
1857 rtl_unlock_work(tp);
61a4dcc2 1858
ea80907f 1859 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1860
61a4dcc2
FR		 1861 return 0;
1862}
1863
31bd204f
FR		 1864static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1865{
85bffe6c 1866 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1867}
1868
1da177e4
LT		 1869static void rtl8169_get_drvinfo(struct net_device *dev,
1870 struct ethtool_drvinfo *info)
1871{
1872 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1873 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1874
68aad78c
RJ		 1875 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1876 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1877 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1878 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1879 if (!IS_ERR_OR_NULL(rtl_fw))
1880 strlcpy(info->fw_version, rtl_fw->version,
1881 sizeof(info->fw_version));
1da177e4
LT		 1882}
1883
1884static int rtl8169_get_regs_len(struct net_device *dev)
1885{
1886 return R8169_REGS_SIZE;
1887}
1888
1889static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1890 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1891{
1892 struct rtl8169_private *tp = netdev_priv(dev);
1893 void __iomem *ioaddr = tp->mmio_addr;
1894 int ret = 0;
1895 u32 reg;
1896
1897 reg = RTL_R32(TBICSR);
1898 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1899 (duplex == DUPLEX_FULL)) {
1900 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1901 } else if (autoneg == AUTONEG_ENABLE)
1902 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1903 else {
bf82c189
JP		 1904 netif_warn(tp, link, dev,
1905 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1906 ret = -EOPNOTSUPP;
1907 }
1908
1909 return ret;
1910}
1911
1912static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1913 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1914{
1915 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1916 int giga_ctrl, bmcr;
54405cde 1917 int rc = -EINVAL;
1da177e4 1918
716b50a3 1919 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1920
1921 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1922 int auto_nego;
1923
4da19633 1924 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1925 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1926 ADVERTISE_100HALF | ADVERTISE_100FULL);
1927
1928 if (adv & ADVERTISED_10baseT_Half)
1929 auto_nego |= ADVERTISE_10HALF;
1930 if (adv & ADVERTISED_10baseT_Full)
1931 auto_nego |= ADVERTISE_10FULL;
1932 if (adv & ADVERTISED_100baseT_Half)
1933 auto_nego |= ADVERTISE_100HALF;
1934 if (adv & ADVERTISED_100baseT_Full)
1935 auto_nego |= ADVERTISE_100FULL;
1936
3577aa1b 1937 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1938
4da19633 1939 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1940 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1941
3577aa1b 1942 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1943 if (tp->mii.supports_gmii) {
54405cde
ON		 1944 if (adv & ADVERTISED_1000baseT_Half)
1945 giga_ctrl |= ADVERTISE_1000HALF;
1946 if (adv & ADVERTISED_1000baseT_Full)
1947 giga_ctrl |= ADVERTISE_1000FULL;
1948 } else if (adv & (ADVERTISED_1000baseT_Half |
1949 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1950 netif_info(tp, link, dev,
1951 "PHY does not support 1000Mbps\n");
54405cde 1952 goto out;
bcf0bf90 1953 }
1da177e4 1954
3577aa1b 1955 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1956
4da19633 1957 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1958 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1959 } else {
1960 giga_ctrl = 0;
1961
1962 if (speed == SPEED_10)
1963 bmcr = 0;
1964 else if (speed == SPEED_100)
1965 bmcr = BMCR_SPEED100;
1966 else
54405cde 1967 goto out;
3577aa1b 1968
1969 if (duplex == DUPLEX_FULL)
1970 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1971 }
1972
4da19633 1973 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1974
cecb5fd7
FR		 1975 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1976 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1977 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1978 rtl_writephy(tp, 0x17, 0x2138);
1979 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1980 } else {
4da19633 1981 rtl_writephy(tp, 0x17, 0x2108);
1982 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1983 }
1984 }
1985
54405cde
ON		 1986 rc = 0;
1987out:
1988 return rc;
1da177e4
LT		 1989}
1990
1991static int rtl8169_set_speed(struct net_device *dev,
54405cde 1992 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1993{
1994 struct rtl8169_private *tp = netdev_priv(dev);
1995 int ret;
1996
54405cde 1997 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1998 if (ret < 0)
1999 goto out;
1da177e4 2000
4876cc1e 2001 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
c4556975
CHL		 2002 (advertising & ADVERTISED_1000baseT_Full) &&
2003 !pci_is_pcie(tp->pci_dev)) {
1da177e4 2004 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 2005 }
2006out:
1da177e4
LT		 2007 return ret;
2008}
2009
2010static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2011{
2012 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 2013 int ret;
2014
4876cc1e
FR		 2015 del_timer_sync(&tp->timer);
2016
da78dbff 2017 rtl_lock_work(tp);
cecb5fd7 2018 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 2019 cmd->duplex, cmd->advertising);
da78dbff 2020 rtl_unlock_work(tp);
5b0384f4 2021
1da177e4
LT		 2022 return ret;
2023}
2024
c8f44aff
MM		 2025static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2026 netdev_features_t features)
1da177e4 2027{
d58d46b5
FR		 2028 struct rtl8169_private *tp = netdev_priv(dev);
2029
2b7b4318 2030 if (dev->mtu > TD_MSS_MAX)
350fb32a 2031 features &= ~NETIF_F_ALL_TSO;
1da177e4 2032
d58d46b5
FR		 2033 if (dev->mtu > JUMBO_1K &&
2034 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2035 features &= ~NETIF_F_IP_CSUM;
2036
350fb32a 2037 return features;
1da177e4
LT		 2038}
2039
da78dbff
FR		 2040static void __rtl8169_set_features(struct net_device *dev,
2041 netdev_features_t features)
1da177e4
LT		 2042{
2043 struct rtl8169_private *tp = netdev_priv(dev);
da78dbff 2044 void __iomem *ioaddr = tp->mmio_addr;
929a031d 2045 u32 rx_config;
1da177e4 2046
929a031d 2047 rx_config = RTL_R32(RxConfig);
2048 if (features & NETIF_F_RXALL)
2049 rx_config |= (AcceptErr | AcceptRunt);
2050 else
2051 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 2052
929a031d 2053 RTL_W32(RxConfig, rx_config);
350fb32a 2054
929a031d 2055 if (features & NETIF_F_RXCSUM)
2056 tp->cp_cmd |= RxChkSum;
2057 else
2058 tp->cp_cmd &= ~RxChkSum;
6bbe021d 2059
929a031d 2060 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2061 tp->cp_cmd |= RxVlan;
2062 else
2063 tp->cp_cmd &= ~RxVlan;
2064
2065 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2066
2067 RTL_W16(CPlusCmd, tp->cp_cmd);
2068 RTL_R16(CPlusCmd);
da78dbff 2069}
1da177e4 2070
da78dbff
FR		 2071static int rtl8169_set_features(struct net_device *dev,
2072 netdev_features_t features)
2073{
2074 struct rtl8169_private *tp = netdev_priv(dev);
2075
929a031d 2076 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2077
da78dbff 2078 rtl_lock_work(tp);
85911d71 2079 if (features ^ dev->features)
929a031d 2080 __rtl8169_set_features(dev, features);
da78dbff 2081 rtl_unlock_work(tp);
1da177e4
LT		 2082
2083 return 0;
2084}
2085
da78dbff 2086
810f4893 2087static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 2088{
df8a39de
JP		 2089 return (skb_vlan_tag_present(skb)) ?
2090 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 2091}
2092
7a8fc77b 2093static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 2094{
2095 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 2096
7a8fc77b 2097 if (opts2 & RxVlanTag)
86a9bad3 2098 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 2099}
2100
ccdffb9a 2101static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 2102{
2103 struct rtl8169_private *tp = netdev_priv(dev);
2104 void __iomem *ioaddr = tp->mmio_addr;
2105 u32 status;
2106
2107 cmd->supported =
2108 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2109 cmd->port = PORT_FIBRE;
2110 cmd->transceiver = XCVR_INTERNAL;
2111
2112 status = RTL_R32(TBICSR);
2113 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2114 cmd->autoneg = !!(status & TBINwEnable);
2115
70739497 2116 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 2117 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 2118
2119 return 0;
1da177e4
LT		 2120}
2121
ccdffb9a 2122static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 2123{
2124 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 2125
2126 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 2127}
2128
2129static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2130{
2131 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2132 int rc;
1da177e4 2133
da78dbff 2134 rtl_lock_work(tp);
ccdffb9a 2135 rc = tp->get_settings(dev, cmd);
da78dbff 2136 rtl_unlock_work(tp);
1da177e4 2137
ccdffb9a 2138 return rc;
1da177e4
LT		 2139}
2140
2141static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2142 void *p)
2143{
5b0384f4 2144 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 2145 u32 __iomem *data = tp->mmio_addr;
2146 u32 *dw = p;
2147 int i;
1da177e4 2148
da78dbff 2149 rtl_lock_work(tp);
15edae91
PW		 2150 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2151 memcpy_fromio(dw++, data++, 4);
da78dbff 2152 rtl_unlock_work(tp);
1da177e4
LT		 2153}
2154
b57b7e5a
SH		 2155static u32 rtl8169_get_msglevel(struct net_device *dev)
2156{
2157 struct rtl8169_private *tp = netdev_priv(dev);
2158
2159 return tp->msg_enable;
2160}
2161
2162static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2163{
2164 struct rtl8169_private *tp = netdev_priv(dev);
2165
2166 tp->msg_enable = value;
2167}
2168
d4a3a0fc
SH		 2169static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2170 "tx_packets",
2171 "rx_packets",
2172 "tx_errors",
2173 "rx_errors",
2174 "rx_missed",
2175 "align_errors",
2176 "tx_single_collisions",
2177 "tx_multi_collisions",
2178 "unicast",
2179 "broadcast",
2180 "multicast",
2181 "tx_aborted",
2182 "tx_underrun",
2183};
2184
b9f2c044 2185static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2186{
b9f2c044
JG		 2187 switch (sset) {
2188 case ETH_SS_STATS:
2189 return ARRAY_SIZE(rtl8169_gstrings);
2190 default:
2191 return -EOPNOTSUPP;
2192 }
d4a3a0fc
SH		 2193}
2194
42020320 2195DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 2196{
6e85d5ad 2197 void __iomem *ioaddr = tp->mmio_addr;
6e85d5ad 2198
42020320 2199 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 2200}
2201
42020320 2202static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
6e85d5ad
CV		 2203{
2204 struct rtl8169_private *tp = netdev_priv(dev);
2205 void __iomem *ioaddr = tp->mmio_addr;
42020320
CV		 2206 dma_addr_t paddr = tp->counters_phys_addr;
2207 u32 cmd;
2208 bool ret;
6e85d5ad 2209
42020320
CV		 2210 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2211 cmd = (u64)paddr & DMA_BIT_MASK(32);
2212 RTL_W32(CounterAddrLow, cmd);
2213 RTL_W32(CounterAddrLow, cmd | counter_cmd);
6e85d5ad 2214
42020320 2215 ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad 2216
42020320
CV		 2217 RTL_W32(CounterAddrLow, 0);
2218 RTL_W32(CounterAddrHigh, 0);
6e85d5ad 2219
42020320 2220 return ret;
6e85d5ad
CV		 2221}
2222
2223static bool rtl8169_reset_counters(struct net_device *dev)
2224{
2225 struct rtl8169_private *tp = netdev_priv(dev);
6e85d5ad
CV		 2226
2227 /*
2228 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2229 * tally counters.
2230 */
2231 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2232 return true;
2233
42020320 2234 return rtl8169_do_counters(dev, CounterReset);
ffc46952
FR		 2235}
2236
6e85d5ad 2237static bool rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2238{
2239 struct rtl8169_private *tp = netdev_priv(dev);
2240 void __iomem *ioaddr = tp->mmio_addr;
d4a3a0fc 2241
355423d0
IV		 2242 /*
2243 * Some chips are unable to dump tally counters when the receiver
2244 * is disabled.
2245 */
2246 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 2247 return true;
d4a3a0fc 2248
42020320 2249 return rtl8169_do_counters(dev, CounterDump);
6e85d5ad
CV		 2250}
2251
2252static bool rtl8169_init_counter_offsets(struct net_device *dev)
2253{
2254 struct rtl8169_private *tp = netdev_priv(dev);
42020320 2255 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 2256 bool ret = false;
2257
2258 /*
2259 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2260 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2261 * reset by a power cycle, while the counter values collected by the
2262 * driver are reset at every driver unload/load cycle.
2263 *
2264 * To make sure the HW values returned by @get_stats64 match the SW
2265 * values, we collect the initial values at first open(*) and use them
2266 * as offsets to normalize the values returned by @get_stats64.
2267 *
2268 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2269 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2270 * set at open time by rtl_hw_start.
2271 */
2272
2273 if (tp->tc_offset.inited)
2274 return true;
2275
2276 /* If both, reset and update fail, propagate to caller. */
2277 if (rtl8169_reset_counters(dev))
2278 ret = true;
2279
2280 if (rtl8169_update_counters(dev))
2281 ret = true;
2282
42020320
CV		 2283 tp->tc_offset.tx_errors = counters->tx_errors;
2284 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2285 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 2286 tp->tc_offset.inited = true;
2287
2288 return ret;
d4a3a0fc
SH		 2289}
2290
355423d0
IV		 2291static void rtl8169_get_ethtool_stats(struct net_device *dev,
2292 struct ethtool_stats *stats, u64 *data)
2293{
2294 struct rtl8169_private *tp = netdev_priv(dev);
42020320 2295 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 2296
2297 ASSERT_RTNL();
2298
2299 rtl8169_update_counters(dev);
2300
42020320
CV		 2301 data[0] = le64_to_cpu(counters->tx_packets);
2302 data[1] = le64_to_cpu(counters->rx_packets);
2303 data[2] = le64_to_cpu(counters->tx_errors);
2304 data[3] = le32_to_cpu(counters->rx_errors);
2305 data[4] = le16_to_cpu(counters->rx_missed);
2306 data[5] = le16_to_cpu(counters->align_errors);
2307 data[6] = le32_to_cpu(counters->tx_one_collision);
2308 data[7] = le32_to_cpu(counters->tx_multi_collision);
2309 data[8] = le64_to_cpu(counters->rx_unicast);
2310 data[9] = le64_to_cpu(counters->rx_broadcast);
2311 data[10] = le32_to_cpu(counters->rx_multicast);
2312 data[11] = le16_to_cpu(counters->tx_aborted);
2313 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 2314}
2315
d4a3a0fc
SH		 2316static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2317{
2318 switch(stringset) {
2319 case ETH_SS_STATS:
2320 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2321 break;
2322 }
2323}
2324
7282d491 2325static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2326 .get_drvinfo = rtl8169_get_drvinfo,
2327 .get_regs_len = rtl8169_get_regs_len,
2328 .get_link = ethtool_op_get_link,
2329 .get_settings = rtl8169_get_settings,
2330 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2331 .get_msglevel = rtl8169_get_msglevel,
2332 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2333 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2334 .get_wol = rtl8169_get_wol,
2335 .set_wol = rtl8169_set_wol,
d4a3a0fc 2336 .get_strings = rtl8169_get_strings,
b9f2c044 2337 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2338 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2339 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2340};
2341
07d3f51f 2342static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2343 struct net_device *dev, u8 default_version)
1da177e4 2344{
5d320a20 2345 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2346 /*
2347 * The driver currently handles the 8168Bf and the 8168Be identically
2348 * but they can be identified more specifically through the test below
2349 * if needed:
2350 *
2351 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2352 *
2353 * Same thing for the 8101Eb and the 8101Ec:
2354 *
2355 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2356 */
3744100e 2357 static const struct rtl_mac_info {
1da177e4 2358 u32 mask;
e3cf0cc0 2359 u32 val;
1da177e4
LT		 2360 int mac_version;
2361 } mac_info[] = {
935e2218
CHL		 2362 /* 8168EP family. */
2363 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2364 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2365 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2366
6e1d0b89
CHL		 2367 /* 8168H family. */
2368 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2369 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2370
c558386b 2371 /* 8168G family. */
45dd95c4 2372 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2373 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2374 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2375 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2376
c2218925 2377 /* 8168F family. */
b3d7b2f2 2378 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2379 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2380 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2381
01dc7fec 2382 /* 8168E family. */
70090424 2383 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2384 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2385 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2386 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2387
5b538df9 2388 /* 8168D family. */
daf9df6d 2389 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2390 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2391 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2392
e6de30d6 2393 /* 8168DP family. */
2394 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2395 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2396 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2397
ef808d50 2398 /* 8168C family. */
17c99297 2399 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2400 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2401 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2402 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2403 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2404 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2405 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2406 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2407 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2408
2409 /* 8168B family. */
2410 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2411 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2412 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2413 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2414
2415 /* 8101 family. */
5598bfe5
HW		 2416 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2417 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2418 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2419 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2420 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2421 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2422 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2423 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2424 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2425 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2426 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2427 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2428 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2429 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2430 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2431 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2432 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2433 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2434 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2435 /* FIXME: where did these entries come from ? -- FR */
2436 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2437 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2438
2439 /* 8110 family. */
2440 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2441 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2442 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2443 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2444 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2445 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2446
f21b75e9
JD		 2447 /* Catch-all */
2448 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2449 };
2450 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2451 u32 reg;
2452
e3cf0cc0
FR		 2453 reg = RTL_R32(TxConfig);
2454 while ((reg & p->mask) != p->val)
1da177e4
LT		 2455 p++;
2456 tp->mac_version = p->mac_version;
5d320a20
FR		 2457
2458 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2459 netif_notice(tp, probe, dev,
2460 "unknown MAC, using family default\n");
2461 tp->mac_version = default_version;
58152cd4 2462 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2463 tp->mac_version = tp->mii.supports_gmii ?
2464 RTL_GIGA_MAC_VER_42 :
2465 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2466 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2467 tp->mac_version = tp->mii.supports_gmii ?
2468 RTL_GIGA_MAC_VER_45 :
2469 RTL_GIGA_MAC_VER_47;
2470 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2471 tp->mac_version = tp->mii.supports_gmii ?
2472 RTL_GIGA_MAC_VER_46 :
2473 RTL_GIGA_MAC_VER_48;
5d320a20 2474 }
1da177e4
LT		 2475}
2476
2477static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2478{
bcf0bf90 2479 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2480}
2481
867763c1
FR		 2482struct phy_reg {
2483 u16 reg;
2484 u16 val;
2485};
2486
4da19633 2487static void rtl_writephy_batch(struct rtl8169_private *tp,
2488 const struct phy_reg *regs, int len)
867763c1
FR		 2489{
2490 while (len-- > 0) {
4da19633 2491 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2492 regs++;
2493 }
2494}
2495
bca03d5f 2496#define PHY_READ 0x00000000
2497#define PHY_DATA_OR 0x10000000
2498#define PHY_DATA_AND 0x20000000
2499#define PHY_BJMPN 0x30000000
eee3786f 2500#define PHY_MDIO_CHG 0x40000000
bca03d5f 2501#define PHY_CLEAR_READCOUNT 0x70000000
2502#define PHY_WRITE 0x80000000
2503#define PHY_READCOUNT_EQ_SKIP 0x90000000
2504#define PHY_COMP_EQ_SKIPN 0xa0000000
2505#define PHY_COMP_NEQ_SKIPN 0xb0000000
2506#define PHY_WRITE_PREVIOUS 0xc0000000
2507#define PHY_SKIPN 0xd0000000
2508#define PHY_DELAY_MS 0xe0000000
bca03d5f 2509
960aee6c
HW		 2510struct fw_info {
2511 u32 magic;
2512 char version[RTL_VER_SIZE];
2513 __le32 fw_start;
2514 __le32 fw_len;
2515 u8 chksum;
2516} __packed;
2517
1c361efb
FR		 2518#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2519
2520static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2521{
b6ffd97f 2522 const struct firmware *fw = rtl_fw->fw;
960aee6c 2523 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2524 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2525 char *version = rtl_fw->version;
2526 bool rc = false;
2527
2528 if (fw->size < FW_OPCODE_SIZE)
2529 goto out;
960aee6c
HW		 2530
2531 if (!fw_info->magic) {
2532 size_t i, size, start;
2533 u8 checksum = 0;
2534
2535 if (fw->size < sizeof(*fw_info))
2536 goto out;
2537
2538 for (i = 0; i < fw->size; i++)
2539 checksum += fw->data[i];
2540 if (checksum != 0)
2541 goto out;
2542
2543 start = le32_to_cpu(fw_info->fw_start);
2544 if (start > fw->size)
2545 goto out;
2546
2547 size = le32_to_cpu(fw_info->fw_len);
2548 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2549 goto out;
2550
2551 memcpy(version, fw_info->version, RTL_VER_SIZE);
2552
2553 pa->code = (__le32 *)(fw->data + start);
2554 pa->size = size;
2555 } else {
1c361efb
FR		 2556 if (fw->size % FW_OPCODE_SIZE)
2557 goto out;
2558
2559 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2560
2561 pa->code = (__le32 *)fw->data;
2562 pa->size = fw->size / FW_OPCODE_SIZE;
2563 }
2564 version[RTL_VER_SIZE - 1] = 0;
2565
2566 rc = true;
2567out:
2568 return rc;
2569}
2570
fd112f2e
FR		 2571static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2572 struct rtl_fw_phy_action *pa)
1c361efb 2573{
fd112f2e 2574 bool rc = false;
1c361efb 2575 size_t index;
bca03d5f 2576
1c361efb
FR		 2577 for (index = 0; index < pa->size; index++) {
2578 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2579 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2580
42b82dc1 2581 switch(action & 0xf0000000) {
2582 case PHY_READ:
2583 case PHY_DATA_OR:
2584 case PHY_DATA_AND:
eee3786f 2585 case PHY_MDIO_CHG:
42b82dc1 2586 case PHY_CLEAR_READCOUNT:
2587 case PHY_WRITE:
2588 case PHY_WRITE_PREVIOUS:
2589 case PHY_DELAY_MS:
2590 break;
2591
2592 case PHY_BJMPN:
2593 if (regno > index) {
fd112f2e 2594 netif_err(tp, ifup, tp->dev,
cecb5fd7 2595 "Out of range of firmware\n");
fd112f2e 2596 goto out;
42b82dc1 2597 }
2598 break;
2599 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2600 if (index + 2 >= pa->size) {
fd112f2e 2601 netif_err(tp, ifup, tp->dev,
cecb5fd7 2602 "Out of range of firmware\n");
fd112f2e 2603 goto out;
42b82dc1 2604 }
2605 break;
2606 case PHY_COMP_EQ_SKIPN:
2607 case PHY_COMP_NEQ_SKIPN:
2608 case PHY_SKIPN:
1c361efb 2609 if (index + 1 + regno >= pa->size) {
fd112f2e 2610 netif_err(tp, ifup, tp->dev,
cecb5fd7 2611 "Out of range of firmware\n");
fd112f2e 2612 goto out;
42b82dc1 2613 }
bca03d5f 2614 break;
2615
42b82dc1 2616 default:
fd112f2e 2617 netif_err(tp, ifup, tp->dev,
42b82dc1 2618 "Invalid action 0x%08x\n", action);
fd112f2e 2619 goto out;
bca03d5f 2620 }
2621 }
fd112f2e
FR		 2622 rc = true;
2623out:
2624 return rc;
2625}
bca03d5f 2626
fd112f2e
FR		 2627static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2628{
2629 struct net_device *dev = tp->dev;
2630 int rc = -EINVAL;
2631
2632 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2633 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2634 goto out;
2635 }
2636
2637 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2638 rc = 0;
2639out:
2640 return rc;
2641}
2642
2643static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2644{
2645 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2646 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2647 u32 predata, count;
2648 size_t index;
2649
2650 predata = count = 0;
eee3786f 2651 org.write = ops->write;
2652 org.read = ops->read;
42b82dc1 2653
1c361efb
FR		 2654 for (index = 0; index < pa->size; ) {
2655 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2656 u32 data = action & 0x0000ffff;
42b82dc1 2657 u32 regno = (action & 0x0fff0000) >> 16;
2658
2659 if (!action)
2660 break;
bca03d5f 2661
2662 switch(action & 0xf0000000) {
42b82dc1 2663 case PHY_READ:
2664 predata = rtl_readphy(tp, regno);
2665 count++;
2666 index++;
2667 break;
2668 case PHY_DATA_OR:
2669 predata |= data;
2670 index++;
2671 break;
2672 case PHY_DATA_AND:
2673 predata &= data;
2674 index++;
2675 break;
2676 case PHY_BJMPN:
2677 index -= regno;
2678 break;
eee3786f 2679 case PHY_MDIO_CHG:
2680 if (data == 0) {
2681 ops->write = org.write;
2682 ops->read = org.read;
2683 } else if (data == 1) {
2684 ops->write = mac_mcu_write;
2685 ops->read = mac_mcu_read;
2686 }
2687
42b82dc1 2688 index++;
2689 break;
2690 case PHY_CLEAR_READCOUNT:
2691 count = 0;
2692 index++;
2693 break;
bca03d5f 2694 case PHY_WRITE:
42b82dc1 2695 rtl_writephy(tp, regno, data);
2696 index++;
2697 break;
2698 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2699 index += (count == data) ? 2 : 1;
bca03d5f 2700 break;
42b82dc1 2701 case PHY_COMP_EQ_SKIPN:
2702 if (predata == data)
2703 index += regno;
2704 index++;
2705 break;
2706 case PHY_COMP_NEQ_SKIPN:
2707 if (predata != data)
2708 index += regno;
2709 index++;
2710 break;
2711 case PHY_WRITE_PREVIOUS:
2712 rtl_writephy(tp, regno, predata);
2713 index++;
2714 break;
2715 case PHY_SKIPN:
2716 index += regno + 1;
2717 break;
2718 case PHY_DELAY_MS:
2719 mdelay(data);
2720 index++;
2721 break;
2722
bca03d5f 2723 default:
2724 BUG();
2725 }
2726 }
eee3786f 2727
2728 ops->write = org.write;
2729 ops->read = org.read;
bca03d5f 2730}
2731
f1e02ed1 2732static void rtl_release_firmware(struct rtl8169_private *tp)
2733{
b6ffd97f
FR		 2734 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2735 release_firmware(tp->rtl_fw->fw);
2736 kfree(tp->rtl_fw);
2737 }
2738 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2739}
2740
953a12cc 2741static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2742{
b6ffd97f 2743 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2744
2745 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2746 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2747 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2748}
2749
2750static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2751{
2752 if (rtl_readphy(tp, reg) != val)
2753 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2754 else
2755 rtl_apply_firmware(tp);
f1e02ed1 2756}
2757
4da19633 2758static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2759{
350f7596 2760 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2761 { 0x1f, 0x0001 },
2762 { 0x06, 0x006e },
2763 { 0x08, 0x0708 },
2764 { 0x15, 0x4000 },
2765 { 0x18, 0x65c7 },
1da177e4 2766
0b9b571d 2767 { 0x1f, 0x0001 },
2768 { 0x03, 0x00a1 },
2769 { 0x02, 0x0008 },
2770 { 0x01, 0x0120 },
2771 { 0x00, 0x1000 },
2772 { 0x04, 0x0800 },
2773 { 0x04, 0x0000 },
1da177e4 2774
0b9b571d 2775 { 0x03, 0xff41 },
2776 { 0x02, 0xdf60 },
2777 { 0x01, 0x0140 },
2778 { 0x00, 0x0077 },
2779 { 0x04, 0x7800 },
2780 { 0x04, 0x7000 },
2781
2782 { 0x03, 0x802f },
2783 { 0x02, 0x4f02 },
2784 { 0x01, 0x0409 },
2785 { 0x00, 0xf0f9 },
2786 { 0x04, 0x9800 },
2787 { 0x04, 0x9000 },
2788
2789 { 0x03, 0xdf01 },
2790 { 0x02, 0xdf20 },
2791 { 0x01, 0xff95 },
2792 { 0x00, 0xba00 },
2793 { 0x04, 0xa800 },
2794 { 0x04, 0xa000 },
2795
2796 { 0x03, 0xff41 },
2797 { 0x02, 0xdf20 },
2798 { 0x01, 0x0140 },
2799 { 0x00, 0x00bb },
2800 { 0x04, 0xb800 },
2801 { 0x04, 0xb000 },
2802
2803 { 0x03, 0xdf41 },
2804 { 0x02, 0xdc60 },
2805 { 0x01, 0x6340 },
2806 { 0x00, 0x007d },
2807 { 0x04, 0xd800 },
2808 { 0x04, 0xd000 },
2809
2810 { 0x03, 0xdf01 },
2811 { 0x02, 0xdf20 },
2812 { 0x01, 0x100a },
2813 { 0x00, 0xa0ff },
2814 { 0x04, 0xf800 },
2815 { 0x04, 0xf000 },
2816
2817 { 0x1f, 0x0000 },
2818 { 0x0b, 0x0000 },
2819 { 0x00, 0x9200 }
2820 };
1da177e4 2821
4da19633 2822 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2823}
2824
4da19633 2825static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2826{
350f7596 2827 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2828 { 0x1f, 0x0002 },
2829 { 0x01, 0x90d0 },
2830 { 0x1f, 0x0000 }
2831 };
2832
4da19633 2833 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2834}
2835
4da19633 2836static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2837{
2838 struct pci_dev *pdev = tp->pci_dev;
2e955856 2839
ccbae55e
SS		 2840 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2841 (pdev->subsystem_device != 0xe000))
2e955856 2842 return;
2843
4da19633 2844 rtl_writephy(tp, 0x1f, 0x0001);
2845 rtl_writephy(tp, 0x10, 0xf01b);
2846 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2847}
2848
4da19633 2849static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2850{
350f7596 2851 static const struct phy_reg phy_reg_init[] = {
2e955856 2852 { 0x1f, 0x0001 },
2853 { 0x04, 0x0000 },
2854 { 0x03, 0x00a1 },
2855 { 0x02, 0x0008 },
2856 { 0x01, 0x0120 },
2857 { 0x00, 0x1000 },
2858 { 0x04, 0x0800 },
2859 { 0x04, 0x9000 },
2860 { 0x03, 0x802f },
2861 { 0x02, 0x4f02 },
2862 { 0x01, 0x0409 },
2863 { 0x00, 0xf099 },
2864 { 0x04, 0x9800 },
2865 { 0x04, 0xa000 },
2866 { 0x03, 0xdf01 },
2867 { 0x02, 0xdf20 },
2868 { 0x01, 0xff95 },
2869 { 0x00, 0xba00 },
2870 { 0x04, 0xa800 },
2871 { 0x04, 0xf000 },
2872 { 0x03, 0xdf01 },
2873 { 0x02, 0xdf20 },
2874 { 0x01, 0x101a },
2875 { 0x00, 0xa0ff },
2876 { 0x04, 0xf800 },
2877 { 0x04, 0x0000 },
2878 { 0x1f, 0x0000 },
2879
2880 { 0x1f, 0x0001 },
2881 { 0x10, 0xf41b },
2882 { 0x14, 0xfb54 },
2883 { 0x18, 0xf5c7 },
2884 { 0x1f, 0x0000 },
2885
2886 { 0x1f, 0x0001 },
2887 { 0x17, 0x0cc0 },
2888 { 0x1f, 0x0000 }
2889 };
2890
4da19633 2891 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2892
4da19633 2893 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2894}
2895
4da19633 2896static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2897{
350f7596 2898 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2899 { 0x1f, 0x0001 },
2900 { 0x04, 0x0000 },
2901 { 0x03, 0x00a1 },
2902 { 0x02, 0x0008 },
2903 { 0x01, 0x0120 },
2904 { 0x00, 0x1000 },
2905 { 0x04, 0x0800 },
2906 { 0x04, 0x9000 },
2907 { 0x03, 0x802f },
2908 { 0x02, 0x4f02 },
2909 { 0x01, 0x0409 },
2910 { 0x00, 0xf099 },
2911 { 0x04, 0x9800 },
2912 { 0x04, 0xa000 },
2913 { 0x03, 0xdf01 },
2914 { 0x02, 0xdf20 },
2915 { 0x01, 0xff95 },
2916 { 0x00, 0xba00 },
2917 { 0x04, 0xa800 },
2918 { 0x04, 0xf000 },
2919 { 0x03, 0xdf01 },
2920 { 0x02, 0xdf20 },
2921 { 0x01, 0x101a },
2922 { 0x00, 0xa0ff },
2923 { 0x04, 0xf800 },
2924 { 0x04, 0x0000 },
2925 { 0x1f, 0x0000 },
2926
2927 { 0x1f, 0x0001 },
2928 { 0x0b, 0x8480 },
2929 { 0x1f, 0x0000 },
2930
2931 { 0x1f, 0x0001 },
2932 { 0x18, 0x67c7 },
2933 { 0x04, 0x2000 },
2934 { 0x03, 0x002f },
2935 { 0x02, 0x4360 },
2936 { 0x01, 0x0109 },
2937 { 0x00, 0x3022 },
2938 { 0x04, 0x2800 },
2939 { 0x1f, 0x0000 },
2940
2941 { 0x1f, 0x0001 },
2942 { 0x17, 0x0cc0 },
2943 { 0x1f, 0x0000 }
2944 };
2945
4da19633 2946 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2947}
2948
4da19633 2949static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2950{
350f7596 2951 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2952 { 0x10, 0xf41b },
2953 { 0x1f, 0x0000 }
2954 };
2955
4da19633 2956 rtl_writephy(tp, 0x1f, 0x0001);
2957 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2958
4da19633 2959 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2960}
2961
4da19633 2962static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2963{
350f7596 2964 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2965 { 0x1f, 0x0001 },
2966 { 0x10, 0xf41b },
2967 { 0x1f, 0x0000 }
2968 };
2969
4da19633 2970 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2971}
2972
4da19633 2973static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2974{
350f7596 2975 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2976 { 0x1f, 0x0000 },
2977 { 0x1d, 0x0f00 },
2978 { 0x1f, 0x0002 },
2979 { 0x0c, 0x1ec8 },
2980 { 0x1f, 0x0000 }
2981 };
2982
4da19633 2983 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2984}
2985
4da19633 2986static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2987{
350f7596 2988 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2989 { 0x1f, 0x0001 },
2990 { 0x1d, 0x3d98 },
2991 { 0x1f, 0x0000 }
2992 };
2993
4da19633 2994 rtl_writephy(tp, 0x1f, 0x0000);
2995 rtl_patchphy(tp, 0x14, 1 << 5);
2996 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2997
4da19633 2998 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2999}
3000
4da19633 3001static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3002{
350f7596 3003 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 3004 { 0x1f, 0x0001 },
3005 { 0x12, 0x2300 },
867763c1
FR		 3006 { 0x1f, 0x0002 },
3007 { 0x00, 0x88d4 },
3008 { 0x01, 0x82b1 },
3009 { 0x03, 0x7002 },
3010 { 0x08, 0x9e30 },
3011 { 0x09, 0x01f0 },
3012 { 0x0a, 0x5500 },
3013 { 0x0c, 0x00c8 },
3014 { 0x1f, 0x0003 },
3015 { 0x12, 0xc096 },
3016 { 0x16, 0x000a },
f50d4275
FR		 3017 { 0x1f, 0x0000 },
3018 { 0x1f, 0x0000 },
3019 { 0x09, 0x2000 },
3020 { 0x09, 0x0000 }
867763c1
FR		 3021 };
3022
4da19633 3023 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3024
4da19633 3025 rtl_patchphy(tp, 0x14, 1 << 5);
3026 rtl_patchphy(tp, 0x0d, 1 << 5);
3027 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 3028}
3029
4da19633 3030static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 3031{
350f7596 3032 static const struct phy_reg phy_reg_init[] = {
f50d4275 3033 { 0x1f, 0x0001 },
7da97ec9 3034 { 0x12, 0x2300 },
f50d4275
FR		 3035 { 0x03, 0x802f },
3036 { 0x02, 0x4f02 },
3037 { 0x01, 0x0409 },
3038 { 0x00, 0xf099 },
3039 { 0x04, 0x9800 },
3040 { 0x04, 0x9000 },
3041 { 0x1d, 0x3d98 },
7da97ec9
FR		 3042 { 0x1f, 0x0002 },
3043 { 0x0c, 0x7eb8 },
f50d4275
FR		 3044 { 0x06, 0x0761 },
3045 { 0x1f, 0x0003 },
3046 { 0x16, 0x0f0a },
7da97ec9
FR		 3047 { 0x1f, 0x0000 }
3048 };
3049
4da19633 3050 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3051
4da19633 3052 rtl_patchphy(tp, 0x16, 1 << 0);
3053 rtl_patchphy(tp, 0x14, 1 << 5);
3054 rtl_patchphy(tp, 0x0d, 1 << 5);
3055 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 3056}
3057
4da19633 3058static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 3059{
350f7596 3060 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 3061 { 0x1f, 0x0001 },
3062 { 0x12, 0x2300 },
3063 { 0x1d, 0x3d98 },
3064 { 0x1f, 0x0002 },
3065 { 0x0c, 0x7eb8 },
3066 { 0x06, 0x5461 },
3067 { 0x1f, 0x0003 },
3068 { 0x16, 0x0f0a },
3069 { 0x1f, 0x0000 }
3070 };
3071
4da19633 3072 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 3073
4da19633 3074 rtl_patchphy(tp, 0x16, 1 << 0);
3075 rtl_patchphy(tp, 0x14, 1 << 5);
3076 rtl_patchphy(tp, 0x0d, 1 << 5);
3077 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 3078}
3079
4da19633 3080static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 3081{
4da19633 3082 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3083}
3084
bca03d5f 3085static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3086{
350f7596 3087 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3088 /* Channel Estimation */
5b538df9 3089 { 0x1f, 0x0001 },
daf9df6d 3090 { 0x06, 0x4064 },
3091 { 0x07, 0x2863 },
3092 { 0x08, 0x059c },
3093 { 0x09, 0x26b4 },
3094 { 0x0a, 0x6a19 },
3095 { 0x0b, 0xdcc8 },
3096 { 0x10, 0xf06d },
3097 { 0x14, 0x7f68 },
3098 { 0x18, 0x7fd9 },
3099 { 0x1c, 0xf0ff },
3100 { 0x1d, 0x3d9c },
5b538df9 3101 { 0x1f, 0x0003 },
daf9df6d 3102 { 0x12, 0xf49f },
3103 { 0x13, 0x070b },
3104 { 0x1a, 0x05ad },
bca03d5f 3105 { 0x14, 0x94c0 },
3106
3107 /*
3108 * Tx Error Issue
cecb5fd7 3109 * Enhance line driver power
bca03d5f 3110 */
5b538df9 3111 { 0x1f, 0x0002 },
daf9df6d 3112 { 0x06, 0x5561 },
3113 { 0x1f, 0x0005 },
3114 { 0x05, 0x8332 },
bca03d5f 3115 { 0x06, 0x5561 },
3116
3117 /*
3118 * Can not link to 1Gbps with bad cable
3119 * Decrease SNR threshold form 21.07dB to 19.04dB
3120 */
3121 { 0x1f, 0x0001 },
3122 { 0x17, 0x0cc0 },
daf9df6d 3123
5b538df9 3124 { 0x1f, 0x0000 },
bca03d5f 3125 { 0x0d, 0xf880 }
daf9df6d 3126 };
3127
4da19633 3128 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3129
bca03d5f 3130 /*
3131 * Rx Error Issue
3132 * Fine Tune Switching regulator parameter
3133 */
4da19633 3134 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3135 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3136 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3137
fdf6fc06 3138 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3139 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3140 { 0x1f, 0x0002 },
3141 { 0x05, 0x669a },
3142 { 0x1f, 0x0005 },
3143 { 0x05, 0x8330 },
3144 { 0x06, 0x669a },
3145 { 0x1f, 0x0002 }
3146 };
3147 int val;
3148
4da19633 3149 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3150
4da19633 3151 val = rtl_readphy(tp, 0x0d);
daf9df6d 3152
3153 if ((val & 0x00ff) != 0x006c) {
350f7596 3154 static const u32 set[] = {
daf9df6d 3155 0x0065, 0x0066, 0x0067, 0x0068,
3156 0x0069, 0x006a, 0x006b, 0x006c
3157 };
3158 int i;
3159
4da19633 3160 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3161
3162 val &= 0xff00;
3163 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3164 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3165 }
3166 } else {
350f7596 3167 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3168 { 0x1f, 0x0002 },
3169 { 0x05, 0x6662 },
3170 { 0x1f, 0x0005 },
3171 { 0x05, 0x8330 },
3172 { 0x06, 0x6662 }
3173 };
3174
4da19633 3175 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3176 }
3177
bca03d5f 3178 /* RSET couple improve */
4da19633 3179 rtl_writephy(tp, 0x1f, 0x0002);
3180 rtl_patchphy(tp, 0x0d, 0x0300);
3181 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3182
bca03d5f 3183 /* Fine tune PLL performance */
4da19633 3184 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3185 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3186 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3187
4da19633 3188 rtl_writephy(tp, 0x1f, 0x0005);
3189 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3190
3191 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3192
4da19633 3193 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3194}
3195
bca03d5f 3196static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3197{
350f7596 3198 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3199 /* Channel Estimation */
daf9df6d 3200 { 0x1f, 0x0001 },
3201 { 0x06, 0x4064 },
3202 { 0x07, 0x2863 },
3203 { 0x08, 0x059c },
3204 { 0x09, 0x26b4 },
3205 { 0x0a, 0x6a19 },
3206 { 0x0b, 0xdcc8 },
3207 { 0x10, 0xf06d },
3208 { 0x14, 0x7f68 },
3209 { 0x18, 0x7fd9 },
3210 { 0x1c, 0xf0ff },
3211 { 0x1d, 0x3d9c },
3212 { 0x1f, 0x0003 },
3213 { 0x12, 0xf49f },
3214 { 0x13, 0x070b },
3215 { 0x1a, 0x05ad },
3216 { 0x14, 0x94c0 },
3217
bca03d5f 3218 /*
3219 * Tx Error Issue
cecb5fd7 3220 * Enhance line driver power
bca03d5f 3221 */
daf9df6d 3222 { 0x1f, 0x0002 },
3223 { 0x06, 0x5561 },
3224 { 0x1f, 0x0005 },
3225 { 0x05, 0x8332 },
bca03d5f 3226 { 0x06, 0x5561 },
3227
3228 /*
3229 * Can not link to 1Gbps with bad cable
3230 * Decrease SNR threshold form 21.07dB to 19.04dB
3231 */
3232 { 0x1f, 0x0001 },
3233 { 0x17, 0x0cc0 },
daf9df6d 3234
3235 { 0x1f, 0x0000 },
bca03d5f 3236 { 0x0d, 0xf880 }
5b538df9
FR		 3237 };
3238
4da19633 3239 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3240
fdf6fc06 3241 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3242 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3243 { 0x1f, 0x0002 },
3244 { 0x05, 0x669a },
5b538df9 3245 { 0x1f, 0x0005 },
daf9df6d 3246 { 0x05, 0x8330 },
3247 { 0x06, 0x669a },
3248
3249 { 0x1f, 0x0002 }
3250 };
3251 int val;
3252
4da19633 3253 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3254
4da19633 3255 val = rtl_readphy(tp, 0x0d);
daf9df6d 3256 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3257 static const u32 set[] = {
daf9df6d 3258 0x0065, 0x0066, 0x0067, 0x0068,
3259 0x0069, 0x006a, 0x006b, 0x006c
3260 };
3261 int i;
3262
4da19633 3263 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3264
3265 val &= 0xff00;
3266 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3267 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3268 }
3269 } else {
350f7596 3270 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3271 { 0x1f, 0x0002 },
3272 { 0x05, 0x2642 },
5b538df9 3273 { 0x1f, 0x0005 },
daf9df6d 3274 { 0x05, 0x8330 },
3275 { 0x06, 0x2642 }
5b538df9
FR		 3276 };
3277
4da19633 3278 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3279 }
3280
bca03d5f 3281 /* Fine tune PLL performance */
4da19633 3282 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3283 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3284 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3285
bca03d5f 3286 /* Switching regulator Slew rate */
4da19633 3287 rtl_writephy(tp, 0x1f, 0x0002);
3288 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3289
4da19633 3290 rtl_writephy(tp, 0x1f, 0x0005);
3291 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3292
3293 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3294
4da19633 3295 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3296}
3297
4da19633 3298static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3299{
350f7596 3300 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3301 { 0x1f, 0x0002 },
3302 { 0x10, 0x0008 },
3303 { 0x0d, 0x006c },
3304
3305 { 0x1f, 0x0000 },
3306 { 0x0d, 0xf880 },
3307
3308 { 0x1f, 0x0001 },
3309 { 0x17, 0x0cc0 },
3310
3311 { 0x1f, 0x0001 },
3312 { 0x0b, 0xa4d8 },
3313 { 0x09, 0x281c },
3314 { 0x07, 0x2883 },
3315 { 0x0a, 0x6b35 },
3316 { 0x1d, 0x3da4 },
3317 { 0x1c, 0xeffd },
3318 { 0x14, 0x7f52 },
3319 { 0x18, 0x7fc6 },
3320 { 0x08, 0x0601 },
3321 { 0x06, 0x4063 },
3322 { 0x10, 0xf074 },
3323 { 0x1f, 0x0003 },
3324 { 0x13, 0x0789 },
3325 { 0x12, 0xf4bd },
3326 { 0x1a, 0x04fd },
3327 { 0x14, 0x84b0 },
3328 { 0x1f, 0x0000 },
3329 { 0x00, 0x9200 },
3330
3331 { 0x1f, 0x0005 },
3332 { 0x01, 0x0340 },
3333 { 0x1f, 0x0001 },
3334 { 0x04, 0x4000 },
3335 { 0x03, 0x1d21 },
3336 { 0x02, 0x0c32 },
3337 { 0x01, 0x0200 },
3338 { 0x00, 0x5554 },
3339 { 0x04, 0x4800 },
3340 { 0x04, 0x4000 },
3341 { 0x04, 0xf000 },
3342 { 0x03, 0xdf01 },
3343 { 0x02, 0xdf20 },
3344 { 0x01, 0x101a },
3345 { 0x00, 0xa0ff },
3346 { 0x04, 0xf800 },
3347 { 0x04, 0xf000 },
3348 { 0x1f, 0x0000 },
3349
3350 { 0x1f, 0x0007 },
3351 { 0x1e, 0x0023 },
3352 { 0x16, 0x0000 },
3353 { 0x1f, 0x0000 }
3354 };
3355
4da19633 3356 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3357}
3358
e6de30d6 3359static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3360{
3361 static const struct phy_reg phy_reg_init[] = {
3362 { 0x1f, 0x0001 },
3363 { 0x17, 0x0cc0 },
3364
3365 { 0x1f, 0x0007 },
3366 { 0x1e, 0x002d },
3367 { 0x18, 0x0040 },
3368 { 0x1f, 0x0000 }
3369 };
3370
3371 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3372 rtl_patchphy(tp, 0x0d, 1 << 5);
3373}
3374
70090424 3375static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3376{
3377 static const struct phy_reg phy_reg_init[] = {
3378 /* Enable Delay cap */
3379 { 0x1f, 0x0005 },
3380 { 0x05, 0x8b80 },
3381 { 0x06, 0xc896 },
3382 { 0x1f, 0x0000 },
3383
3384 /* Channel estimation fine tune */
3385 { 0x1f, 0x0001 },
3386 { 0x0b, 0x6c20 },
3387 { 0x07, 0x2872 },
3388 { 0x1c, 0xefff },
3389 { 0x1f, 0x0003 },
3390 { 0x14, 0x6420 },
3391 { 0x1f, 0x0000 },
3392
3393 /* Update PFM & 10M TX idle timer */
3394 { 0x1f, 0x0007 },
3395 { 0x1e, 0x002f },
3396 { 0x15, 0x1919 },
3397 { 0x1f, 0x0000 },
3398
3399 { 0x1f, 0x0007 },
3400 { 0x1e, 0x00ac },
3401 { 0x18, 0x0006 },
3402 { 0x1f, 0x0000 }
3403 };
3404
15ecd039
FR		 3405 rtl_apply_firmware(tp);
3406
01dc7fec 3407 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3408
3409 /* DCO enable for 10M IDLE Power */
3410 rtl_writephy(tp, 0x1f, 0x0007);
3411 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3412 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3413 rtl_writephy(tp, 0x1f, 0x0000);
3414
3415 /* For impedance matching */
3416 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3417 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3418 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3419
3420 /* PHY auto speed down */
3421 rtl_writephy(tp, 0x1f, 0x0007);
3422 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3423 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3424 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3425 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3426
3427 rtl_writephy(tp, 0x1f, 0x0005);
3428 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3429 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3430 rtl_writephy(tp, 0x1f, 0x0000);
3431
3432 rtl_writephy(tp, 0x1f, 0x0005);
3433 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3434 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3435 rtl_writephy(tp, 0x1f, 0x0007);
3436 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3437 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3438 rtl_writephy(tp, 0x1f, 0x0006);
3439 rtl_writephy(tp, 0x00, 0x5a00);
3440 rtl_writephy(tp, 0x1f, 0x0000);
3441 rtl_writephy(tp, 0x0d, 0x0007);
3442 rtl_writephy(tp, 0x0e, 0x003c);
3443 rtl_writephy(tp, 0x0d, 0x4007);
3444 rtl_writephy(tp, 0x0e, 0x0000);
3445 rtl_writephy(tp, 0x0d, 0x0000);
3446}
3447
9ecb9aab 3448static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3449{
3450 const u16 w[] = {
3451 addr[0] | (addr[1] << 8),
3452 addr[2] | (addr[3] << 8),
3453 addr[4] | (addr[5] << 8)
3454 };
3455 const struct exgmac_reg e[] = {
3456 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3457 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3458 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3459 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3460 };
3461
3462 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3463}
3464
70090424
HW		 3465static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3466{
3467 static const struct phy_reg phy_reg_init[] = {
3468 /* Enable Delay cap */
3469 { 0x1f, 0x0004 },
3470 { 0x1f, 0x0007 },
3471 { 0x1e, 0x00ac },
3472 { 0x18, 0x0006 },
3473 { 0x1f, 0x0002 },
3474 { 0x1f, 0x0000 },
3475 { 0x1f, 0x0000 },
3476
3477 /* Channel estimation fine tune */
3478 { 0x1f, 0x0003 },
3479 { 0x09, 0xa20f },
3480 { 0x1f, 0x0000 },
3481 { 0x1f, 0x0000 },
3482
3483 /* Green Setting */
3484 { 0x1f, 0x0005 },
3485 { 0x05, 0x8b5b },
3486 { 0x06, 0x9222 },
3487 { 0x05, 0x8b6d },
3488 { 0x06, 0x8000 },
3489 { 0x05, 0x8b76 },
3490 { 0x06, 0x8000 },
3491 { 0x1f, 0x0000 }
3492 };
3493
3494 rtl_apply_firmware(tp);
3495
3496 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3497
3498 /* For 4-corner performance improve */
3499 rtl_writephy(tp, 0x1f, 0x0005);
3500 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3501 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3502 rtl_writephy(tp, 0x1f, 0x0000);
3503
3504 /* PHY auto speed down */
3505 rtl_writephy(tp, 0x1f, 0x0004);
3506 rtl_writephy(tp, 0x1f, 0x0007);
3507 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3508 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3509 rtl_writephy(tp, 0x1f, 0x0002);
3510 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3511 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3512
3513 /* improve 10M EEE waveform */
3514 rtl_writephy(tp, 0x1f, 0x0005);
3515 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3516 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3517 rtl_writephy(tp, 0x1f, 0x0000);
3518
3519 /* Improve 2-pair detection performance */
3520 rtl_writephy(tp, 0x1f, 0x0005);
3521 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3522 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3523 rtl_writephy(tp, 0x1f, 0x0000);
3524
3525 /* EEE setting */
706123d0 3526 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3527 rtl_writephy(tp, 0x1f, 0x0005);
3528 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3529 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
70090424
HW		 3530 rtl_writephy(tp, 0x1f, 0x0004);
3531 rtl_writephy(tp, 0x1f, 0x0007);
3532 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3533 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3534 rtl_writephy(tp, 0x1f, 0x0002);
3535 rtl_writephy(tp, 0x1f, 0x0000);
3536 rtl_writephy(tp, 0x0d, 0x0007);
3537 rtl_writephy(tp, 0x0e, 0x003c);
3538 rtl_writephy(tp, 0x0d, 0x4007);
3539 rtl_writephy(tp, 0x0e, 0x0000);
3540 rtl_writephy(tp, 0x0d, 0x0000);
3541
3542 /* Green feature */
3543 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3544 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3545 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
70090424 3546 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3547
9ecb9aab 3548 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3549 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3550}
3551
5f886e08
HW		 3552static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3553{
3554 /* For 4-corner performance improve */
3555 rtl_writephy(tp, 0x1f, 0x0005);
3556 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3557 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3558 rtl_writephy(tp, 0x1f, 0x0000);
3559
3560 /* PHY auto speed down */
3561 rtl_writephy(tp, 0x1f, 0x0007);
3562 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3563 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3564 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3565 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3566
3567 /* Improve 10M EEE waveform */
3568 rtl_writephy(tp, 0x1f, 0x0005);
3569 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3570 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3571 rtl_writephy(tp, 0x1f, 0x0000);
3572}
3573
c2218925
HW		 3574static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3575{
3576 static const struct phy_reg phy_reg_init[] = {
3577 /* Channel estimation fine tune */
3578 { 0x1f, 0x0003 },
3579 { 0x09, 0xa20f },
3580 { 0x1f, 0x0000 },
3581
3582 /* Modify green table for giga & fnet */
3583 { 0x1f, 0x0005 },
3584 { 0x05, 0x8b55 },
3585 { 0x06, 0x0000 },
3586 { 0x05, 0x8b5e },
3587 { 0x06, 0x0000 },
3588 { 0x05, 0x8b67 },
3589 { 0x06, 0x0000 },
3590 { 0x05, 0x8b70 },
3591 { 0x06, 0x0000 },
3592 { 0x1f, 0x0000 },
3593 { 0x1f, 0x0007 },
3594 { 0x1e, 0x0078 },
3595 { 0x17, 0x0000 },
3596 { 0x19, 0x00fb },
3597 { 0x1f, 0x0000 },
3598
3599 /* Modify green table for 10M */
3600 { 0x1f, 0x0005 },
3601 { 0x05, 0x8b79 },
3602 { 0x06, 0xaa00 },
3603 { 0x1f, 0x0000 },
3604
3605 /* Disable hiimpedance detection (RTCT) */
3606 { 0x1f, 0x0003 },
3607 { 0x01, 0x328a },
3608 { 0x1f, 0x0000 }
3609 };
3610
3611 rtl_apply_firmware(tp);
3612
3613 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3614
5f886e08 3615 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3616
3617 /* Improve 2-pair detection performance */
3618 rtl_writephy(tp, 0x1f, 0x0005);
3619 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3620 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3621 rtl_writephy(tp, 0x1f, 0x0000);
3622}
3623
3624static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3625{
3626 rtl_apply_firmware(tp);
3627
5f886e08 3628 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3629}
3630
b3d7b2f2
HW		 3631static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3632{
b3d7b2f2
HW		 3633 static const struct phy_reg phy_reg_init[] = {
3634 /* Channel estimation fine tune */
3635 { 0x1f, 0x0003 },
3636 { 0x09, 0xa20f },
3637 { 0x1f, 0x0000 },
3638
3639 /* Modify green table for giga & fnet */
3640 { 0x1f, 0x0005 },
3641 { 0x05, 0x8b55 },
3642 { 0x06, 0x0000 },
3643 { 0x05, 0x8b5e },
3644 { 0x06, 0x0000 },
3645 { 0x05, 0x8b67 },
3646 { 0x06, 0x0000 },
3647 { 0x05, 0x8b70 },
3648 { 0x06, 0x0000 },
3649 { 0x1f, 0x0000 },
3650 { 0x1f, 0x0007 },
3651 { 0x1e, 0x0078 },
3652 { 0x17, 0x0000 },
3653 { 0x19, 0x00aa },
3654 { 0x1f, 0x0000 },
3655
3656 /* Modify green table for 10M */
3657 { 0x1f, 0x0005 },
3658 { 0x05, 0x8b79 },
3659 { 0x06, 0xaa00 },
3660 { 0x1f, 0x0000 },
3661
3662 /* Disable hiimpedance detection (RTCT) */
3663 { 0x1f, 0x0003 },
3664 { 0x01, 0x328a },
3665 { 0x1f, 0x0000 }
3666 };
3667
3668
3669 rtl_apply_firmware(tp);
3670
3671 rtl8168f_hw_phy_config(tp);
3672
3673 /* Improve 2-pair detection performance */
3674 rtl_writephy(tp, 0x1f, 0x0005);
3675 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3676 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3677 rtl_writephy(tp, 0x1f, 0x0000);
3678
3679 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3680
3681 /* Modify green table for giga */
3682 rtl_writephy(tp, 0x1f, 0x0005);
3683 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3684 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3685 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3686 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3687 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3688 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3689 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3690 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3691 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3692 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3693 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3694 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3695 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3696 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3697 rtl_writephy(tp, 0x1f, 0x0000);
3698
3699 /* uc same-seed solution */
3700 rtl_writephy(tp, 0x1f, 0x0005);
3701 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3702 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3703 rtl_writephy(tp, 0x1f, 0x0000);
3704
3705 /* eee setting */
706123d0 3706 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3707 rtl_writephy(tp, 0x1f, 0x0005);
3708 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3709 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3710 rtl_writephy(tp, 0x1f, 0x0004);
3711 rtl_writephy(tp, 0x1f, 0x0007);
3712 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3713 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3714 rtl_writephy(tp, 0x1f, 0x0000);
3715 rtl_writephy(tp, 0x0d, 0x0007);
3716 rtl_writephy(tp, 0x0e, 0x003c);
3717 rtl_writephy(tp, 0x0d, 0x4007);
3718 rtl_writephy(tp, 0x0e, 0x0000);
3719 rtl_writephy(tp, 0x0d, 0x0000);
3720
3721 /* Green feature */
3722 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3723 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3724 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3725 rtl_writephy(tp, 0x1f, 0x0000);
3726}
3727
c558386b
HW		 3728static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3729{
c558386b
HW		 3730 rtl_apply_firmware(tp);
3731
41f44d13 3732 rtl_writephy(tp, 0x1f, 0x0a46);
3733 if (rtl_readphy(tp, 0x10) & 0x0100) {
3734 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3735 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3736 } else {
3737 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3738 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3739 }
c558386b 3740
41f44d13 3741 rtl_writephy(tp, 0x1f, 0x0a46);
3742 if (rtl_readphy(tp, 0x13) & 0x0100) {
3743 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3744 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3745 } else {
fe7524c0 3746 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3747 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3748 }
c558386b 3749
41f44d13 3750 /* Enable PHY auto speed down */
3751 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3752 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3753
fe7524c0 3754 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3755 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3756 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3757 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3758 rtl_writephy(tp, 0x1f, 0x0a43);
3759 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3760 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3761 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3762
41f44d13 3763 /* EEE auto-fallback function */
3764 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3765 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3766
41f44d13 3767 /* Enable UC LPF tune function */
3768 rtl_writephy(tp, 0x1f, 0x0a43);
3769 rtl_writephy(tp, 0x13, 0x8012);
76564428 3770 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3771
3772 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3773 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3774
fe7524c0 3775 /* Improve SWR Efficiency */
3776 rtl_writephy(tp, 0x1f, 0x0bcd);
3777 rtl_writephy(tp, 0x14, 0x5065);
3778 rtl_writephy(tp, 0x14, 0xd065);
3779 rtl_writephy(tp, 0x1f, 0x0bc8);
3780 rtl_writephy(tp, 0x11, 0x5655);
3781 rtl_writephy(tp, 0x1f, 0x0bcd);
3782 rtl_writephy(tp, 0x14, 0x1065);
3783 rtl_writephy(tp, 0x14, 0x9065);
3784 rtl_writephy(tp, 0x14, 0x1065);
3785
1bac1072
DC		 3786 /* Check ALDPS bit, disable it if enabled */
3787 rtl_writephy(tp, 0x1f, 0x0a43);
3788 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3789 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3790
41f44d13 3791 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3792}
3793
57538c4a 3794static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3795{
3796 rtl_apply_firmware(tp);
3797}
3798
6e1d0b89
CHL		 3799static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3800{
3801 u16 dout_tapbin;
3802 u32 data;
3803
3804 rtl_apply_firmware(tp);
3805
3806 /* CHN EST parameters adjust - giga master */
3807 rtl_writephy(tp, 0x1f, 0x0a43);
3808 rtl_writephy(tp, 0x13, 0x809b);
76564428 3809 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3810 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3811 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3812 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3813 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3814 rtl_writephy(tp, 0x13, 0x809c);
76564428 3815 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3816 rtl_writephy(tp, 0x1f, 0x0000);
3817
3818 /* CHN EST parameters adjust - giga slave */
3819 rtl_writephy(tp, 0x1f, 0x0a43);
3820 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3821 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3822 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3823 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3824 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3825 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3826 rtl_writephy(tp, 0x1f, 0x0000);
3827
3828 /* CHN EST parameters adjust - fnet */
3829 rtl_writephy(tp, 0x1f, 0x0a43);
3830 rtl_writephy(tp, 0x13, 0x808e);
76564428 3831 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3832 rtl_writephy(tp, 0x13, 0x8090);
76564428 3833 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3834 rtl_writephy(tp, 0x13, 0x8092);
76564428 3835 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3836 rtl_writephy(tp, 0x1f, 0x0000);
3837
3838 /* enable R-tune & PGA-retune function */
3839 dout_tapbin = 0;
3840 rtl_writephy(tp, 0x1f, 0x0a46);
3841 data = rtl_readphy(tp, 0x13);
3842 data &= 3;
3843 data <<= 2;
3844 dout_tapbin |= data;
3845 data = rtl_readphy(tp, 0x12);
3846 data &= 0xc000;
3847 data >>= 14;
3848 dout_tapbin |= data;
3849 dout_tapbin = ~(dout_tapbin^0x08);
3850 dout_tapbin <<= 12;
3851 dout_tapbin &= 0xf000;
3852 rtl_writephy(tp, 0x1f, 0x0a43);
3853 rtl_writephy(tp, 0x13, 0x827a);
76564428 3854 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3855 rtl_writephy(tp, 0x13, 0x827b);
76564428 3856 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3857 rtl_writephy(tp, 0x13, 0x827c);
76564428 3858 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3859 rtl_writephy(tp, 0x13, 0x827d);
76564428 3860 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3861
3862 rtl_writephy(tp, 0x1f, 0x0a43);
3863 rtl_writephy(tp, 0x13, 0x0811);
76564428 3864 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3865 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3866 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3867 rtl_writephy(tp, 0x1f, 0x0000);
3868
3869 /* enable GPHY 10M */
3870 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3871 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3872 rtl_writephy(tp, 0x1f, 0x0000);
3873
3874 /* SAR ADC performance */
3875 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3876 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3877 rtl_writephy(tp, 0x1f, 0x0000);
3878
3879 rtl_writephy(tp, 0x1f, 0x0a43);
3880 rtl_writephy(tp, 0x13, 0x803f);
76564428 3881 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3882 rtl_writephy(tp, 0x13, 0x8047);
76564428 3883 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3884 rtl_writephy(tp, 0x13, 0x804f);
76564428 3885 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3886 rtl_writephy(tp, 0x13, 0x8057);
76564428 3887 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3888 rtl_writephy(tp, 0x13, 0x805f);
76564428 3889 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3890 rtl_writephy(tp, 0x13, 0x8067);
76564428 3891 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3892 rtl_writephy(tp, 0x13, 0x806f);
76564428 3893 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3894 rtl_writephy(tp, 0x1f, 0x0000);
3895
3896 /* disable phy pfm mode */
3897 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3898 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3899 rtl_writephy(tp, 0x1f, 0x0000);
3900
3901 /* Check ALDPS bit, disable it if enabled */
3902 rtl_writephy(tp, 0x1f, 0x0a43);
3903 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3904 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3905
3906 rtl_writephy(tp, 0x1f, 0x0000);
3907}
3908
3909static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3910{
3911 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3912 u16 rlen;
3913 u32 data;
3914
3915 rtl_apply_firmware(tp);
3916
3917 /* CHIN EST parameter update */
3918 rtl_writephy(tp, 0x1f, 0x0a43);
3919 rtl_writephy(tp, 0x13, 0x808a);
76564428 3920 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3921 rtl_writephy(tp, 0x1f, 0x0000);
3922
3923 /* enable R-tune & PGA-retune function */
3924 rtl_writephy(tp, 0x1f, 0x0a43);
3925 rtl_writephy(tp, 0x13, 0x0811);
76564428 3926 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3927 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3928 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3929 rtl_writephy(tp, 0x1f, 0x0000);
3930
3931 /* enable GPHY 10M */
3932 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3933 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3934 rtl_writephy(tp, 0x1f, 0x0000);
3935
3936 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3937 data = r8168_mac_ocp_read(tp, 0xdd02);
3938 ioffset_p3 = ((data & 0x80)>>7);
3939 ioffset_p3 <<= 3;
3940
3941 data = r8168_mac_ocp_read(tp, 0xdd00);
3942 ioffset_p3 |= ((data & (0xe000))>>13);
3943 ioffset_p2 = ((data & (0x1e00))>>9);
3944 ioffset_p1 = ((data & (0x01e0))>>5);
3945 ioffset_p0 = ((data & 0x0010)>>4);
3946 ioffset_p0 <<= 3;
3947 ioffset_p0 |= (data & (0x07));
3948 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3949
05b9687b 3950 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3951 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3952 rtl_writephy(tp, 0x1f, 0x0bcf);
3953 rtl_writephy(tp, 0x16, data);
3954 rtl_writephy(tp, 0x1f, 0x0000);
3955 }
3956
3957 /* Modify rlen (TX LPF corner frequency) level */
3958 rtl_writephy(tp, 0x1f, 0x0bcd);
3959 data = rtl_readphy(tp, 0x16);
3960 data &= 0x000f;
3961 rlen = 0;
3962 if (data > 3)
3963 rlen = data - 3;
3964 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3965 rtl_writephy(tp, 0x17, data);
3966 rtl_writephy(tp, 0x1f, 0x0bcd);
3967 rtl_writephy(tp, 0x1f, 0x0000);
3968
3969 /* disable phy pfm mode */
3970 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3971 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3972 rtl_writephy(tp, 0x1f, 0x0000);
3973
3974 /* Check ALDPS bit, disable it if enabled */
3975 rtl_writephy(tp, 0x1f, 0x0a43);
3976 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3977 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3978
3979 rtl_writephy(tp, 0x1f, 0x0000);
3980}
3981
935e2218
CHL		 3982static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3983{
3984 /* Enable PHY auto speed down */
3985 rtl_writephy(tp, 0x1f, 0x0a44);
3986 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3987 rtl_writephy(tp, 0x1f, 0x0000);
3988
3989 /* patch 10M & ALDPS */
3990 rtl_writephy(tp, 0x1f, 0x0bcc);
3991 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3992 rtl_writephy(tp, 0x1f, 0x0a44);
3993 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3994 rtl_writephy(tp, 0x1f, 0x0a43);
3995 rtl_writephy(tp, 0x13, 0x8084);
3996 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3997 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3998 rtl_writephy(tp, 0x1f, 0x0000);
3999
4000 /* Enable EEE auto-fallback function */
4001 rtl_writephy(tp, 0x1f, 0x0a4b);
4002 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4003 rtl_writephy(tp, 0x1f, 0x0000);
4004
4005 /* Enable UC LPF tune function */
4006 rtl_writephy(tp, 0x1f, 0x0a43);
4007 rtl_writephy(tp, 0x13, 0x8012);
4008 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4009 rtl_writephy(tp, 0x1f, 0x0000);
4010
4011 /* set rg_sel_sdm_rate */
4012 rtl_writephy(tp, 0x1f, 0x0c42);
4013 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4014 rtl_writephy(tp, 0x1f, 0x0000);
4015
4016 /* Check ALDPS bit, disable it if enabled */
4017 rtl_writephy(tp, 0x1f, 0x0a43);
4018 if (rtl_readphy(tp, 0x10) & 0x0004)
4019 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4020
4021 rtl_writephy(tp, 0x1f, 0x0000);
4022}
4023
4024static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4025{
4026 /* patch 10M & ALDPS */
4027 rtl_writephy(tp, 0x1f, 0x0bcc);
4028 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4029 rtl_writephy(tp, 0x1f, 0x0a44);
4030 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4031 rtl_writephy(tp, 0x1f, 0x0a43);
4032 rtl_writephy(tp, 0x13, 0x8084);
4033 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4034 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4035 rtl_writephy(tp, 0x1f, 0x0000);
4036
4037 /* Enable UC LPF tune function */
4038 rtl_writephy(tp, 0x1f, 0x0a43);
4039 rtl_writephy(tp, 0x13, 0x8012);
4040 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4041 rtl_writephy(tp, 0x1f, 0x0000);
4042
4043 /* Set rg_sel_sdm_rate */
4044 rtl_writephy(tp, 0x1f, 0x0c42);
4045 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4046 rtl_writephy(tp, 0x1f, 0x0000);
4047
4048 /* Channel estimation parameters */
4049 rtl_writephy(tp, 0x1f, 0x0a43);
4050 rtl_writephy(tp, 0x13, 0x80f3);
4051 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4052 rtl_writephy(tp, 0x13, 0x80f0);
4053 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4054 rtl_writephy(tp, 0x13, 0x80ef);
4055 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4056 rtl_writephy(tp, 0x13, 0x80f6);
4057 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4058 rtl_writephy(tp, 0x13, 0x80ec);
4059 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4060 rtl_writephy(tp, 0x13, 0x80ed);
4061 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4062 rtl_writephy(tp, 0x13, 0x80f2);
4063 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4064 rtl_writephy(tp, 0x13, 0x80f4);
4065 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4066 rtl_writephy(tp, 0x1f, 0x0a43);
4067 rtl_writephy(tp, 0x13, 0x8110);
4068 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4069 rtl_writephy(tp, 0x13, 0x810f);
4070 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4071 rtl_writephy(tp, 0x13, 0x8111);
4072 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4073 rtl_writephy(tp, 0x13, 0x8113);
4074 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4075 rtl_writephy(tp, 0x13, 0x8115);
4076 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4077 rtl_writephy(tp, 0x13, 0x810e);
4078 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4079 rtl_writephy(tp, 0x13, 0x810c);
4080 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4081 rtl_writephy(tp, 0x13, 0x810b);
4082 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4083 rtl_writephy(tp, 0x1f, 0x0a43);
4084 rtl_writephy(tp, 0x13, 0x80d1);
4085 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4086 rtl_writephy(tp, 0x13, 0x80cd);
4087 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4088 rtl_writephy(tp, 0x13, 0x80d3);
4089 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4090 rtl_writephy(tp, 0x13, 0x80d5);
4091 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4092 rtl_writephy(tp, 0x13, 0x80d7);
4093 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4094
4095 /* Force PWM-mode */
4096 rtl_writephy(tp, 0x1f, 0x0bcd);
4097 rtl_writephy(tp, 0x14, 0x5065);
4098 rtl_writephy(tp, 0x14, 0xd065);
4099 rtl_writephy(tp, 0x1f, 0x0bc8);
4100 rtl_writephy(tp, 0x12, 0x00ed);
4101 rtl_writephy(tp, 0x1f, 0x0bcd);
4102 rtl_writephy(tp, 0x14, 0x1065);
4103 rtl_writephy(tp, 0x14, 0x9065);
4104 rtl_writephy(tp, 0x14, 0x1065);
4105 rtl_writephy(tp, 0x1f, 0x0000);
4106
4107 /* Check ALDPS bit, disable it if enabled */
4108 rtl_writephy(tp, 0x1f, 0x0a43);
4109 if (rtl_readphy(tp, 0x10) & 0x0004)
4110 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4111
4112 rtl_writephy(tp, 0x1f, 0x0000);
4113}
4114
4da19633 4115static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4116{
350f7596 4117 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4118 { 0x1f, 0x0003 },
4119 { 0x08, 0x441d },
4120 { 0x01, 0x9100 },
4121 { 0x1f, 0x0000 }
4122 };
4123
4da19633 4124 rtl_writephy(tp, 0x1f, 0x0000);
4125 rtl_patchphy(tp, 0x11, 1 << 12);
4126 rtl_patchphy(tp, 0x19, 1 << 13);
4127 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4128
4da19633 4129 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4130}
4131
5a5e4443
HW		 4132static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4133{
4134 static const struct phy_reg phy_reg_init[] = {
4135 { 0x1f, 0x0005 },
4136 { 0x1a, 0x0000 },
4137 { 0x1f, 0x0000 },
4138
4139 { 0x1f, 0x0004 },
4140 { 0x1c, 0x0000 },
4141 { 0x1f, 0x0000 },
4142
4143 { 0x1f, 0x0001 },
4144 { 0x15, 0x7701 },
4145 { 0x1f, 0x0000 }
4146 };
4147
4148 /* Disable ALDPS before ram code */
eef63cc1
FR		 4149 rtl_writephy(tp, 0x1f, 0x0000);
4150 rtl_writephy(tp, 0x18, 0x0310);
4151 msleep(100);
5a5e4443 4152
953a12cc 4153 rtl_apply_firmware(tp);
5a5e4443
HW		 4154
4155 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4156}
4157
7e18dca1
HW		 4158static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4159{
7e18dca1 4160 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4161 rtl_writephy(tp, 0x1f, 0x0000);
4162 rtl_writephy(tp, 0x18, 0x0310);
4163 msleep(20);
7e18dca1
HW		 4164
4165 rtl_apply_firmware(tp);
4166
4167 /* EEE setting */
fdf6fc06 4168 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4169 rtl_writephy(tp, 0x1f, 0x0004);
4170 rtl_writephy(tp, 0x10, 0x401f);
4171 rtl_writephy(tp, 0x19, 0x7030);
4172 rtl_writephy(tp, 0x1f, 0x0000);
4173}
4174
5598bfe5
HW		 4175static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4176{
5598bfe5
HW		 4177 static const struct phy_reg phy_reg_init[] = {
4178 { 0x1f, 0x0004 },
4179 { 0x10, 0xc07f },
4180 { 0x19, 0x7030 },
4181 { 0x1f, 0x0000 }
4182 };
4183
4184 /* Disable ALDPS before ram code */
eef63cc1
FR		 4185 rtl_writephy(tp, 0x1f, 0x0000);
4186 rtl_writephy(tp, 0x18, 0x0310);
4187 msleep(100);
5598bfe5
HW		 4188
4189 rtl_apply_firmware(tp);
4190
fdf6fc06 4191 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4192 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4193
fdf6fc06 4194 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4195}
4196
5615d9f1
FR		 4197static void rtl_hw_phy_config(struct net_device *dev)
4198{
4199 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4200
4201 rtl8169_print_mac_version(tp);
4202
4203 switch (tp->mac_version) {
4204 case RTL_GIGA_MAC_VER_01:
4205 break;
4206 case RTL_GIGA_MAC_VER_02:
4207 case RTL_GIGA_MAC_VER_03:
4da19633 4208 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4209 break;
4210 case RTL_GIGA_MAC_VER_04:
4da19633 4211 rtl8169sb_hw_phy_config(tp);
5615d9f1 4212 break;
2e955856 4213 case RTL_GIGA_MAC_VER_05:
4da19633 4214 rtl8169scd_hw_phy_config(tp);
2e955856 4215 break;
8c7006aa 4216 case RTL_GIGA_MAC_VER_06:
4da19633 4217 rtl8169sce_hw_phy_config(tp);
8c7006aa 4218 break;
2857ffb7
FR		 4219 case RTL_GIGA_MAC_VER_07:
4220 case RTL_GIGA_MAC_VER_08:
4221 case RTL_GIGA_MAC_VER_09:
4da19633 4222 rtl8102e_hw_phy_config(tp);
2857ffb7 4223 break;
236b8082 4224 case RTL_GIGA_MAC_VER_11:
4da19633 4225 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4226 break;
4227 case RTL_GIGA_MAC_VER_12:
4da19633 4228 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4229 break;
4230 case RTL_GIGA_MAC_VER_17:
4da19633 4231 rtl8168bef_hw_phy_config(tp);
236b8082 4232 break;
867763c1 4233 case RTL_GIGA_MAC_VER_18:
4da19633 4234 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4235 break;
4236 case RTL_GIGA_MAC_VER_19:
4da19633 4237 rtl8168c_1_hw_phy_config(tp);
867763c1 4238 break;
7da97ec9 4239 case RTL_GIGA_MAC_VER_20:
4da19633 4240 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4241 break;
197ff761 4242 case RTL_GIGA_MAC_VER_21:
4da19633 4243 rtl8168c_3_hw_phy_config(tp);
197ff761 4244 break;
6fb07058 4245 case RTL_GIGA_MAC_VER_22:
4da19633 4246 rtl8168c_4_hw_phy_config(tp);
6fb07058 4247 break;
ef3386f0 4248 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4249 case RTL_GIGA_MAC_VER_24:
4da19633 4250 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4251 break;
5b538df9 4252 case RTL_GIGA_MAC_VER_25:
bca03d5f 4253 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4254 break;
4255 case RTL_GIGA_MAC_VER_26:
bca03d5f 4256 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4257 break;
4258 case RTL_GIGA_MAC_VER_27:
4da19633 4259 rtl8168d_3_hw_phy_config(tp);
5b538df9 4260 break;
e6de30d6 4261 case RTL_GIGA_MAC_VER_28:
4262 rtl8168d_4_hw_phy_config(tp);
4263 break;
5a5e4443
HW		 4264 case RTL_GIGA_MAC_VER_29:
4265 case RTL_GIGA_MAC_VER_30:
4266 rtl8105e_hw_phy_config(tp);
4267 break;
cecb5fd7
FR		 4268 case RTL_GIGA_MAC_VER_31:
4269 /* None. */
4270 break;
01dc7fec 4271 case RTL_GIGA_MAC_VER_32:
01dc7fec 4272 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4273 rtl8168e_1_hw_phy_config(tp);
4274 break;
4275 case RTL_GIGA_MAC_VER_34:
4276 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4277 break;
c2218925
HW		 4278 case RTL_GIGA_MAC_VER_35:
4279 rtl8168f_1_hw_phy_config(tp);
4280 break;
4281 case RTL_GIGA_MAC_VER_36:
4282 rtl8168f_2_hw_phy_config(tp);
4283 break;
ef3386f0 4284
7e18dca1
HW		 4285 case RTL_GIGA_MAC_VER_37:
4286 rtl8402_hw_phy_config(tp);
4287 break;
4288
b3d7b2f2
HW		 4289 case RTL_GIGA_MAC_VER_38:
4290 rtl8411_hw_phy_config(tp);
4291 break;
4292
5598bfe5
HW		 4293 case RTL_GIGA_MAC_VER_39:
4294 rtl8106e_hw_phy_config(tp);
4295 break;
4296
c558386b
HW		 4297 case RTL_GIGA_MAC_VER_40:
4298 rtl8168g_1_hw_phy_config(tp);
4299 break;
57538c4a 4300 case RTL_GIGA_MAC_VER_42:
58152cd4 4301 case RTL_GIGA_MAC_VER_43:
45dd95c4 4302 case RTL_GIGA_MAC_VER_44:
57538c4a 4303 rtl8168g_2_hw_phy_config(tp);
4304 break;
6e1d0b89
CHL		 4305 case RTL_GIGA_MAC_VER_45:
4306 case RTL_GIGA_MAC_VER_47:
4307 rtl8168h_1_hw_phy_config(tp);
4308 break;
4309 case RTL_GIGA_MAC_VER_46:
4310 case RTL_GIGA_MAC_VER_48:
4311 rtl8168h_2_hw_phy_config(tp);
4312 break;
c558386b 4313
935e2218
CHL		 4314 case RTL_GIGA_MAC_VER_49:
4315 rtl8168ep_1_hw_phy_config(tp);
4316 break;
4317 case RTL_GIGA_MAC_VER_50:
4318 case RTL_GIGA_MAC_VER_51:
4319 rtl8168ep_2_hw_phy_config(tp);
4320 break;
4321
c558386b 4322 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4323 default:
4324 break;
4325 }
4326}
4327
da78dbff 4328static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 4329{
1da177e4
LT		 4330 struct timer_list *timer = &tp->timer;
4331 void __iomem *ioaddr = tp->mmio_addr;
4332 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4333
bcf0bf90 4334 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 4335
4da19633 4336 if (tp->phy_reset_pending(tp)) {
5b0384f4 4337 /*
1da177e4
LT		 4338 * A busy loop could burn quite a few cycles on nowadays CPU.
4339 * Let's delay the execution of the timer for a few ticks.
4340 */
4341 timeout = HZ/10;
4342 goto out_mod_timer;
4343 }
4344
4345 if (tp->link_ok(ioaddr))
da78dbff 4346 return;
1da177e4 4347
9bb8eeb5 4348 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 4349
4da19633 4350 tp->phy_reset_enable(tp);
1da177e4
LT		 4351
4352out_mod_timer:
4353 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 4354}
4355
4356static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4357{
da78dbff
FR		 4358 if (!test_and_set_bit(flag, tp->wk.flags))
4359 schedule_work(&tp->wk.work);
da78dbff
FR		 4360}
4361
4362static void rtl8169_phy_timer(unsigned long __opaque)
4363{
4364 struct net_device *dev = (struct net_device *)__opaque;
4365 struct rtl8169_private *tp = netdev_priv(dev);
4366
98ddf986 4367 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 4368}
4369
1da177e4
LT		 4370static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4371 void __iomem *ioaddr)
4372{
4373 iounmap(ioaddr);
4374 pci_release_regions(pdev);
87aeec76 4375 pci_clear_mwi(pdev);
1da177e4
LT		 4376 pci_disable_device(pdev);
4377 free_netdev(dev);
4378}
4379
ffc46952
FR		 4380DECLARE_RTL_COND(rtl_phy_reset_cond)
4381{
4382 return tp->phy_reset_pending(tp);
4383}
4384
bf793295
FR		 4385static void rtl8169_phy_reset(struct net_device *dev,
4386 struct rtl8169_private *tp)
4387{
4da19633 4388 tp->phy_reset_enable(tp);
ffc46952 4389 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4390}
4391
2544bfc0
FR		 4392static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4393{
4394 void __iomem *ioaddr = tp->mmio_addr;
4395
4396 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4397 (RTL_R8(PHYstatus) & TBI_Enable);
4398}
4399
4ff96fa6
FR		 4400static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4401{
4402 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 4403
5615d9f1 4404 rtl_hw_phy_config(dev);
4ff96fa6 4405
77332894
MS		 4406 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4407 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4408 RTL_W8(0x82, 0x01);
4409 }
4ff96fa6 4410
6dccd16b
FR		 4411 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4412
4413 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4414 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4415
bcf0bf90 4416 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 4417 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4418 RTL_W8(0x82, 0x01);
4419 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4420 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4421 }
4422
bf793295
FR		 4423 rtl8169_phy_reset(dev, tp);
4424
54405cde 4425 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4426 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4427 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4428 (tp->mii.supports_gmii ?
4429 ADVERTISED_1000baseT_Half |
4430 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4431
2544bfc0 4432 if (rtl_tbi_enabled(tp))
bf82c189 4433 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4434}
4435
773d2021
FR		 4436static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4437{
4438 void __iomem *ioaddr = tp->mmio_addr;
773d2021 4439
da78dbff 4440 rtl_lock_work(tp);
773d2021
FR		 4441
4442 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 4443
9ecb9aab 4444 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 4445 RTL_R32(MAC4);
4446
9ecb9aab 4447 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 4448 RTL_R32(MAC0);
4449
9ecb9aab 4450 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4451 rtl_rar_exgmac_set(tp, addr);
c28aa385 4452
773d2021
FR		 4453 RTL_W8(Cfg9346, Cfg9346_Lock);
4454
da78dbff 4455 rtl_unlock_work(tp);
773d2021
FR		 4456}
4457
4458static int rtl_set_mac_address(struct net_device *dev, void *p)
4459{
4460 struct rtl8169_private *tp = netdev_priv(dev);
4461 struct sockaddr *addr = p;
4462
4463 if (!is_valid_ether_addr(addr->sa_data))
4464 return -EADDRNOTAVAIL;
4465
4466 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4467
4468 rtl_rar_set(tp, dev->dev_addr);
4469
4470 return 0;
4471}
4472
5f787a1a
FR		 4473static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4474{
4475 struct rtl8169_private *tp = netdev_priv(dev);
4476 struct mii_ioctl_data *data = if_mii(ifr);
4477
8b4ab28d
FR		 4478 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4479}
5f787a1a 4480
cecb5fd7
FR		 4481static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4482 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4483{
5f787a1a
FR		 4484 switch (cmd) {
4485 case SIOCGMIIPHY:
4486 data->phy_id = 32; /* Internal PHY */
4487 return 0;
4488
4489 case SIOCGMIIREG:
4da19633 4490 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4491 return 0;
4492
4493 case SIOCSMIIREG:
4da19633 4494 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4495 return 0;
4496 }
4497 return -EOPNOTSUPP;
4498}
4499
8b4ab28d
FR		 4500static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4501{
4502 return -EOPNOTSUPP;
4503}
4504
fbac58fc
FR		 4505static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4506{
4507 if (tp->features & RTL_FEATURE_MSI) {
4508 pci_disable_msi(pdev);
4509 tp->features &= ~RTL_FEATURE_MSI;
4510 }
4511}
4512
baf63293 4513static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4514{
4515 struct mdio_ops *ops = &tp->mdio_ops;
4516
4517 switch (tp->mac_version) {
4518 case RTL_GIGA_MAC_VER_27:
4519 ops->write = r8168dp_1_mdio_write;
4520 ops->read = r8168dp_1_mdio_read;
4521 break;
e6de30d6 4522 case RTL_GIGA_MAC_VER_28:
4804b3b3 4523 case RTL_GIGA_MAC_VER_31:
e6de30d6 4524 ops->write = r8168dp_2_mdio_write;
4525 ops->read = r8168dp_2_mdio_read;
4526 break;
c558386b
HW		 4527 case RTL_GIGA_MAC_VER_40:
4528 case RTL_GIGA_MAC_VER_41:
57538c4a 4529 case RTL_GIGA_MAC_VER_42:
58152cd4 4530 case RTL_GIGA_MAC_VER_43:
45dd95c4 4531 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4532 case RTL_GIGA_MAC_VER_45:
4533 case RTL_GIGA_MAC_VER_46:
4534 case RTL_GIGA_MAC_VER_47:
4535 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4536 case RTL_GIGA_MAC_VER_49:
4537 case RTL_GIGA_MAC_VER_50:
4538 case RTL_GIGA_MAC_VER_51:
c558386b
HW		 4539 ops->write = r8168g_mdio_write;
4540 ops->read = r8168g_mdio_read;
4541 break;
c0e45c1c 4542 default:
4543 ops->write = r8169_mdio_write;
4544 ops->read = r8169_mdio_read;
4545 break;
4546 }
4547}
4548
e2409d83 4549static void rtl_speed_down(struct rtl8169_private *tp)
4550{
4551 u32 adv;
4552 int lpa;
4553
4554 rtl_writephy(tp, 0x1f, 0x0000);
4555 lpa = rtl_readphy(tp, MII_LPA);
4556
4557 if (lpa & (LPA_10HALF | LPA_10FULL))
4558 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4559 else if (lpa & (LPA_100HALF | LPA_100FULL))
4560 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4561 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4562 else
4563 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4564 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4565 (tp->mii.supports_gmii ?
4566 ADVERTISED_1000baseT_Half |
4567 ADVERTISED_1000baseT_Full : 0);
4568
4569 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4570 adv);
4571}
4572
649b3b8c 4573static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4574{
4575 void __iomem *ioaddr = tp->mmio_addr;
4576
4577 switch (tp->mac_version) {
b00e69de
CB		 4578 case RTL_GIGA_MAC_VER_25:
4579 case RTL_GIGA_MAC_VER_26:
649b3b8c 4580 case RTL_GIGA_MAC_VER_29:
4581 case RTL_GIGA_MAC_VER_30:
4582 case RTL_GIGA_MAC_VER_32:
4583 case RTL_GIGA_MAC_VER_33:
4584 case RTL_GIGA_MAC_VER_34:
7e18dca1 4585 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4586 case RTL_GIGA_MAC_VER_38:
5598bfe5 4587 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4588 case RTL_GIGA_MAC_VER_40:
4589 case RTL_GIGA_MAC_VER_41:
57538c4a 4590 case RTL_GIGA_MAC_VER_42:
58152cd4 4591 case RTL_GIGA_MAC_VER_43:
45dd95c4 4592 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4593 case RTL_GIGA_MAC_VER_45:
4594 case RTL_GIGA_MAC_VER_46:
4595 case RTL_GIGA_MAC_VER_47:
4596 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4597 case RTL_GIGA_MAC_VER_49:
4598 case RTL_GIGA_MAC_VER_50:
4599 case RTL_GIGA_MAC_VER_51:
649b3b8c 4600 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4601 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4602 break;
4603 default:
4604 break;
4605 }
4606}
4607
4608static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4609{
4610 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4611 return false;
4612
e2409d83 4613 rtl_speed_down(tp);
649b3b8c 4614 rtl_wol_suspend_quirk(tp);
4615
4616 return true;
4617}
4618
065c27c1 4619static void r810x_phy_power_down(struct rtl8169_private *tp)
4620{
4621 rtl_writephy(tp, 0x1f, 0x0000);
4622 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4623}
4624
4625static void r810x_phy_power_up(struct rtl8169_private *tp)
4626{
4627 rtl_writephy(tp, 0x1f, 0x0000);
4628 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4629}
4630
4631static void r810x_pll_power_down(struct rtl8169_private *tp)
4632{
0004299a
HW		 4633 void __iomem *ioaddr = tp->mmio_addr;
4634
649b3b8c 4635 if (rtl_wol_pll_power_down(tp))
065c27c1 4636 return;
065c27c1 4637
4638 r810x_phy_power_down(tp);
0004299a
HW		 4639
4640 switch (tp->mac_version) {
4641 case RTL_GIGA_MAC_VER_07:
4642 case RTL_GIGA_MAC_VER_08:
4643 case RTL_GIGA_MAC_VER_09:
4644 case RTL_GIGA_MAC_VER_10:
4645 case RTL_GIGA_MAC_VER_13:
4646 case RTL_GIGA_MAC_VER_16:
4647 break;
4648 default:
4649 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4650 break;
4651 }
065c27c1 4652}
4653
4654static void r810x_pll_power_up(struct rtl8169_private *tp)
4655{
0004299a
HW		 4656 void __iomem *ioaddr = tp->mmio_addr;
4657
065c27c1 4658 r810x_phy_power_up(tp);
0004299a
HW		 4659
4660 switch (tp->mac_version) {
4661 case RTL_GIGA_MAC_VER_07:
4662 case RTL_GIGA_MAC_VER_08:
4663 case RTL_GIGA_MAC_VER_09:
4664 case RTL_GIGA_MAC_VER_10:
4665 case RTL_GIGA_MAC_VER_13:
4666 case RTL_GIGA_MAC_VER_16:
4667 break;
6e1d0b89
CHL		 4668 case RTL_GIGA_MAC_VER_47:
4669 case RTL_GIGA_MAC_VER_48:
05b9687b 4670 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4671 break;
0004299a
HW		 4672 default:
4673 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4674 break;
4675 }
065c27c1 4676}
4677
4678static void r8168_phy_power_up(struct rtl8169_private *tp)
4679{
4680 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4681 switch (tp->mac_version) {
4682 case RTL_GIGA_MAC_VER_11:
4683 case RTL_GIGA_MAC_VER_12:
4684 case RTL_GIGA_MAC_VER_17:
4685 case RTL_GIGA_MAC_VER_18:
4686 case RTL_GIGA_MAC_VER_19:
4687 case RTL_GIGA_MAC_VER_20:
4688 case RTL_GIGA_MAC_VER_21:
4689 case RTL_GIGA_MAC_VER_22:
4690 case RTL_GIGA_MAC_VER_23:
4691 case RTL_GIGA_MAC_VER_24:
4692 case RTL_GIGA_MAC_VER_25:
4693 case RTL_GIGA_MAC_VER_26:
4694 case RTL_GIGA_MAC_VER_27:
4695 case RTL_GIGA_MAC_VER_28:
4696 case RTL_GIGA_MAC_VER_31:
4697 rtl_writephy(tp, 0x0e, 0x0000);
4698 break;
4699 default:
4700 break;
4701 }
065c27c1 4702 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4703}
4704
4705static void r8168_phy_power_down(struct rtl8169_private *tp)
4706{
4707 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4708 switch (tp->mac_version) {
4709 case RTL_GIGA_MAC_VER_32:
4710 case RTL_GIGA_MAC_VER_33:
beb330a4 4711 case RTL_GIGA_MAC_VER_40:
4712 case RTL_GIGA_MAC_VER_41:
01dc7fec 4713 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4714 break;
4715
4716 case RTL_GIGA_MAC_VER_11:
4717 case RTL_GIGA_MAC_VER_12:
4718 case RTL_GIGA_MAC_VER_17:
4719 case RTL_GIGA_MAC_VER_18:
4720 case RTL_GIGA_MAC_VER_19:
4721 case RTL_GIGA_MAC_VER_20:
4722 case RTL_GIGA_MAC_VER_21:
4723 case RTL_GIGA_MAC_VER_22:
4724 case RTL_GIGA_MAC_VER_23:
4725 case RTL_GIGA_MAC_VER_24:
4726 case RTL_GIGA_MAC_VER_25:
4727 case RTL_GIGA_MAC_VER_26:
4728 case RTL_GIGA_MAC_VER_27:
4729 case RTL_GIGA_MAC_VER_28:
4730 case RTL_GIGA_MAC_VER_31:
4731 rtl_writephy(tp, 0x0e, 0x0200);
4732 default:
4733 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4734 break;
4735 }
065c27c1 4736}
4737
4738static void r8168_pll_power_down(struct rtl8169_private *tp)
4739{
4740 void __iomem *ioaddr = tp->mmio_addr;
4741
cecb5fd7
FR		 4742 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4743 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 4744 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4745 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4746 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4747 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
2f8c040c 4748 r8168_check_dash(tp)) {
065c27c1 4749 return;
5d2e1957 4750 }
065c27c1 4751
cecb5fd7
FR		 4752 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4753 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4754 (RTL_R16(CPlusCmd) & ASF)) {
4755 return;
4756 }
4757
01dc7fec 4758 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4759 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4760 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4761
649b3b8c 4762 if (rtl_wol_pll_power_down(tp))
065c27c1 4763 return;
065c27c1 4764
4765 r8168_phy_power_down(tp);
4766
4767 switch (tp->mac_version) {
4768 case RTL_GIGA_MAC_VER_25:
4769 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4770 case RTL_GIGA_MAC_VER_27:
4771 case RTL_GIGA_MAC_VER_28:
4804b3b3 4772 case RTL_GIGA_MAC_VER_31:
01dc7fec 4773 case RTL_GIGA_MAC_VER_32:
4774 case RTL_GIGA_MAC_VER_33:
42fde737 4775 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4776 case RTL_GIGA_MAC_VER_45:
4777 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4778 case RTL_GIGA_MAC_VER_50:
4779 case RTL_GIGA_MAC_VER_51:
065c27c1 4780 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4781 break;
beb330a4 4782 case RTL_GIGA_MAC_VER_40:
4783 case RTL_GIGA_MAC_VER_41:
935e2218 4784 case RTL_GIGA_MAC_VER_49:
706123d0 4785 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4786 0xfc000000, ERIAR_EXGMAC);
b8e5e6ad 4787 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
beb330a4 4788 break;
065c27c1 4789 }
4790}
4791
4792static void r8168_pll_power_up(struct rtl8169_private *tp)
4793{
4794 void __iomem *ioaddr = tp->mmio_addr;
4795
065c27c1 4796 switch (tp->mac_version) {
4797 case RTL_GIGA_MAC_VER_25:
4798 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4799 case RTL_GIGA_MAC_VER_27:
4800 case RTL_GIGA_MAC_VER_28:
4804b3b3 4801 case RTL_GIGA_MAC_VER_31:
01dc7fec 4802 case RTL_GIGA_MAC_VER_32:
4803 case RTL_GIGA_MAC_VER_33:
065c27c1 4804 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4805 break;
42fde737 4806 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4807 case RTL_GIGA_MAC_VER_45:
4808 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4809 case RTL_GIGA_MAC_VER_50:
4810 case RTL_GIGA_MAC_VER_51:
05b9687b 4811 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4812 break;
beb330a4 4813 case RTL_GIGA_MAC_VER_40:
4814 case RTL_GIGA_MAC_VER_41:
935e2218 4815 case RTL_GIGA_MAC_VER_49:
b8e5e6ad 4816 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
706123d0 4817 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4818 0x00000000, ERIAR_EXGMAC);
4819 break;
065c27c1 4820 }
4821
4822 r8168_phy_power_up(tp);
4823}
4824
d58d46b5
FR		 4825static void rtl_generic_op(struct rtl8169_private *tp,
4826 void (*op)(struct rtl8169_private *))
065c27c1 4827{
4828 if (op)
4829 op(tp);
4830}
4831
4832static void rtl_pll_power_down(struct rtl8169_private *tp)
4833{
d58d46b5 4834 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4835}
4836
4837static void rtl_pll_power_up(struct rtl8169_private *tp)
4838{
d58d46b5 4839 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4840}
4841
baf63293 4842static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4843{
4844 struct pll_power_ops *ops = &tp->pll_power_ops;
4845
4846 switch (tp->mac_version) {
4847 case RTL_GIGA_MAC_VER_07:
4848 case RTL_GIGA_MAC_VER_08:
4849 case RTL_GIGA_MAC_VER_09:
4850 case RTL_GIGA_MAC_VER_10:
4851 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4852 case RTL_GIGA_MAC_VER_29:
4853 case RTL_GIGA_MAC_VER_30:
7e18dca1 4854 case RTL_GIGA_MAC_VER_37:
5598bfe5 4855 case RTL_GIGA_MAC_VER_39:
58152cd4 4856 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 4857 case RTL_GIGA_MAC_VER_47:
4858 case RTL_GIGA_MAC_VER_48:
065c27c1 4859 ops->down = r810x_pll_power_down;
4860 ops->up = r810x_pll_power_up;
4861 break;
4862
4863 case RTL_GIGA_MAC_VER_11:
4864 case RTL_GIGA_MAC_VER_12:
4865 case RTL_GIGA_MAC_VER_17:
4866 case RTL_GIGA_MAC_VER_18:
4867 case RTL_GIGA_MAC_VER_19:
4868 case RTL_GIGA_MAC_VER_20:
4869 case RTL_GIGA_MAC_VER_21:
4870 case RTL_GIGA_MAC_VER_22:
4871 case RTL_GIGA_MAC_VER_23:
4872 case RTL_GIGA_MAC_VER_24:
4873 case RTL_GIGA_MAC_VER_25:
4874 case RTL_GIGA_MAC_VER_26:
4875 case RTL_GIGA_MAC_VER_27:
e6de30d6 4876 case RTL_GIGA_MAC_VER_28:
4804b3b3 4877 case RTL_GIGA_MAC_VER_31:
01dc7fec 4878 case RTL_GIGA_MAC_VER_32:
4879 case RTL_GIGA_MAC_VER_33:
70090424 4880 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4881 case RTL_GIGA_MAC_VER_35:
4882 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4883 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4884 case RTL_GIGA_MAC_VER_40:
4885 case RTL_GIGA_MAC_VER_41:
57538c4a 4886 case RTL_GIGA_MAC_VER_42:
45dd95c4 4887 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4888 case RTL_GIGA_MAC_VER_45:
4889 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4890 case RTL_GIGA_MAC_VER_49:
4891 case RTL_GIGA_MAC_VER_50:
4892 case RTL_GIGA_MAC_VER_51:
065c27c1 4893 ops->down = r8168_pll_power_down;
4894 ops->up = r8168_pll_power_up;
4895 break;
4896
4897 default:
4898 ops->down = NULL;
4899 ops->up = NULL;
4900 break;
4901 }
4902}
4903
e542a226
HW		 4904static void rtl_init_rxcfg(struct rtl8169_private *tp)
4905{
4906 void __iomem *ioaddr = tp->mmio_addr;
4907
4908 switch (tp->mac_version) {
4909 case RTL_GIGA_MAC_VER_01:
4910 case RTL_GIGA_MAC_VER_02:
4911 case RTL_GIGA_MAC_VER_03:
4912 case RTL_GIGA_MAC_VER_04:
4913 case RTL_GIGA_MAC_VER_05:
4914 case RTL_GIGA_MAC_VER_06:
4915 case RTL_GIGA_MAC_VER_10:
4916 case RTL_GIGA_MAC_VER_11:
4917 case RTL_GIGA_MAC_VER_12:
4918 case RTL_GIGA_MAC_VER_13:
4919 case RTL_GIGA_MAC_VER_14:
4920 case RTL_GIGA_MAC_VER_15:
4921 case RTL_GIGA_MAC_VER_16:
4922 case RTL_GIGA_MAC_VER_17:
4923 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4924 break;
4925 case RTL_GIGA_MAC_VER_18:
4926 case RTL_GIGA_MAC_VER_19:
4927 case RTL_GIGA_MAC_VER_20:
4928 case RTL_GIGA_MAC_VER_21:
4929 case RTL_GIGA_MAC_VER_22:
4930 case RTL_GIGA_MAC_VER_23:
4931 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4932 case RTL_GIGA_MAC_VER_34:
3ced8c95 4933 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 4934 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4935 break;
beb330a4 4936 case RTL_GIGA_MAC_VER_40:
4937 case RTL_GIGA_MAC_VER_41:
57538c4a 4938 case RTL_GIGA_MAC_VER_42:
58152cd4 4939 case RTL_GIGA_MAC_VER_43:
45dd95c4 4940 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4941 case RTL_GIGA_MAC_VER_45:
4942 case RTL_GIGA_MAC_VER_46:
4943 case RTL_GIGA_MAC_VER_47:
4944 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4945 case RTL_GIGA_MAC_VER_49:
4946 case RTL_GIGA_MAC_VER_50:
4947 case RTL_GIGA_MAC_VER_51:
7ebc4822 4948 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4949 break;
e542a226
HW		 4950 default:
4951 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4952 break;
4953 }
4954}
4955
92fc43b4
HW		 4956static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4957{
9fba0812 4958 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4959}
4960
d58d46b5
FR		 4961static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4962{
9c5028e9 4963 void __iomem *ioaddr = tp->mmio_addr;
4964
4965 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4966 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4967 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4968}
4969
4970static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4971{
9c5028e9 4972 void __iomem *ioaddr = tp->mmio_addr;
4973
4974 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4975 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4976 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4977}
4978
4979static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4980{
4981 void __iomem *ioaddr = tp->mmio_addr;
4982
4983 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4984 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
f65d539c 4985 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4986}
4987
4988static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4989{
4990 void __iomem *ioaddr = tp->mmio_addr;
4991
4992 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4993 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4994 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4995}
4996
4997static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4998{
4999 void __iomem *ioaddr = tp->mmio_addr;
5000
5001 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5002}
5003
5004static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5005{
5006 void __iomem *ioaddr = tp->mmio_addr;
5007
5008 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5009}
5010
5011static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5012{
5013 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5014
5015 RTL_W8(MaxTxPacketSize, 0x3f);
5016 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5017 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
f65d539c 5018 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5019}
5020
5021static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5022{
5023 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5024
5025 RTL_W8(MaxTxPacketSize, 0x0c);
5026 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5027 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 5028 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 5029}
5030
5031static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5032{
5033 rtl_tx_performance_tweak(tp->pci_dev,
f65d539c 5034 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 5035}
5036
5037static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5038{
5039 rtl_tx_performance_tweak(tp->pci_dev,
5040 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5041}
5042
5043static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5044{
5045 void __iomem *ioaddr = tp->mmio_addr;
5046
5047 r8168b_0_hw_jumbo_enable(tp);
5048
5049 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5050}
5051
5052static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5053{
5054 void __iomem *ioaddr = tp->mmio_addr;
5055
5056 r8168b_0_hw_jumbo_disable(tp);
5057
5058 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5059}
5060
baf63293 5061static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 5062{
5063 struct jumbo_ops *ops = &tp->jumbo_ops;
5064
5065 switch (tp->mac_version) {
5066 case RTL_GIGA_MAC_VER_11:
5067 ops->disable = r8168b_0_hw_jumbo_disable;
5068 ops->enable = r8168b_0_hw_jumbo_enable;
5069 break;
5070 case RTL_GIGA_MAC_VER_12:
5071 case RTL_GIGA_MAC_VER_17:
5072 ops->disable = r8168b_1_hw_jumbo_disable;
5073 ops->enable = r8168b_1_hw_jumbo_enable;
5074 break;
5075 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5076 case RTL_GIGA_MAC_VER_19:
5077 case RTL_GIGA_MAC_VER_20:
5078 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5079 case RTL_GIGA_MAC_VER_22:
5080 case RTL_GIGA_MAC_VER_23:
5081 case RTL_GIGA_MAC_VER_24:
5082 case RTL_GIGA_MAC_VER_25:
5083 case RTL_GIGA_MAC_VER_26:
5084 ops->disable = r8168c_hw_jumbo_disable;
5085 ops->enable = r8168c_hw_jumbo_enable;
5086 break;
5087 case RTL_GIGA_MAC_VER_27:
5088 case RTL_GIGA_MAC_VER_28:
5089 ops->disable = r8168dp_hw_jumbo_disable;
5090 ops->enable = r8168dp_hw_jumbo_enable;
5091 break;
5092 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5093 case RTL_GIGA_MAC_VER_32:
5094 case RTL_GIGA_MAC_VER_33:
5095 case RTL_GIGA_MAC_VER_34:
5096 ops->disable = r8168e_hw_jumbo_disable;
5097 ops->enable = r8168e_hw_jumbo_enable;
5098 break;
5099
5100 /*
5101 * No action needed for jumbo frames with 8169.
5102 * No jumbo for 810x at all.
5103 */
c558386b
HW		 5104 case RTL_GIGA_MAC_VER_40:
5105 case RTL_GIGA_MAC_VER_41:
57538c4a 5106 case RTL_GIGA_MAC_VER_42:
58152cd4 5107 case RTL_GIGA_MAC_VER_43:
45dd95c4 5108 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5109 case RTL_GIGA_MAC_VER_45:
5110 case RTL_GIGA_MAC_VER_46:
5111 case RTL_GIGA_MAC_VER_47:
5112 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5113 case RTL_GIGA_MAC_VER_49:
5114 case RTL_GIGA_MAC_VER_50:
5115 case RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 5116 default:
5117 ops->disable = NULL;
5118 ops->enable = NULL;
5119 break;
5120 }
5121}
5122
ffc46952
FR		 5123DECLARE_RTL_COND(rtl_chipcmd_cond)
5124{
5125 void __iomem *ioaddr = tp->mmio_addr;
5126
5127 return RTL_R8(ChipCmd) & CmdReset;
5128}
5129
6f43adc8
FR		 5130static void rtl_hw_reset(struct rtl8169_private *tp)
5131{
5132 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 5133
6f43adc8
FR		 5134 RTL_W8(ChipCmd, CmdReset);
5135
ffc46952 5136 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 5137}
5138
b6ffd97f 5139static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 5140{
b6ffd97f
FR		 5141 struct rtl_fw *rtl_fw;
5142 const char *name;
5143 int rc = -ENOMEM;
953a12cc 5144
b6ffd97f
FR		 5145 name = rtl_lookup_firmware_name(tp);
5146 if (!name)
5147 goto out_no_firmware;
953a12cc 5148
b6ffd97f
FR		 5149 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5150 if (!rtl_fw)
5151 goto err_warn;
31bd204f 5152
b6ffd97f
FR		 5153 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5154 if (rc < 0)
5155 goto err_free;
5156
fd112f2e
FR		 5157 rc = rtl_check_firmware(tp, rtl_fw);
5158 if (rc < 0)
5159 goto err_release_firmware;
5160
b6ffd97f
FR		 5161 tp->rtl_fw = rtl_fw;
5162out:
5163 return;
5164
fd112f2e
FR		 5165err_release_firmware:
5166 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 5167err_free:
5168 kfree(rtl_fw);
5169err_warn:
5170 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5171 name, rc);
5172out_no_firmware:
5173 tp->rtl_fw = NULL;
5174 goto out;
5175}
5176
5177static void rtl_request_firmware(struct rtl8169_private *tp)
5178{
5179 if (IS_ERR(tp->rtl_fw))
5180 rtl_request_uncached_firmware(tp);
953a12cc
FR		 5181}
5182
92fc43b4
HW		 5183static void rtl_rx_close(struct rtl8169_private *tp)
5184{
5185 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 5186
1687b566 5187 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 5188}
5189
ffc46952
FR		 5190DECLARE_RTL_COND(rtl_npq_cond)
5191{
5192 void __iomem *ioaddr = tp->mmio_addr;
5193
5194 return RTL_R8(TxPoll) & NPQ;
5195}
5196
5197DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5198{
5199 void __iomem *ioaddr = tp->mmio_addr;
5200
5201 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5202}
5203
e6de30d6 5204static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 5205{
e6de30d6 5206 void __iomem *ioaddr = tp->mmio_addr;
5207
1da177e4 5208 /* Disable interrupts */
811fd301 5209 rtl8169_irq_mask_and_ack(tp);
1da177e4 5210
92fc43b4
HW		 5211 rtl_rx_close(tp);
5212
5d2e1957 5213 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 5214 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5215 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 5216 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 5217 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 5218 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5219 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5220 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5221 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5222 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5223 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5224 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5225 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5226 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5227 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5228 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5229 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 5230 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5231 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5232 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5233 tp->mac_version == RTL_GIGA_MAC_VER_51) {
c2b0c1e7 5234 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 5235 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 5236 } else {
5237 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5238 udelay(100);
e6de30d6 5239 }
5240
92fc43b4 5241 rtl_hw_reset(tp);
1da177e4
LT		 5242}
5243
7f796d83 5244static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 5245{
5246 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 5247
5248 /* Set DMA burst size and Interframe Gap Time */
5249 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5250 (InterFrameGap << TxInterFrameGapShift));
5251}
5252
07ce4064 5253static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 5254{
5255 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5256
07ce4064
FR		 5257 tp->hw_start(dev);
5258
da78dbff 5259 rtl_irq_enable_all(tp);
07ce4064
FR		 5260}
5261
7f796d83
FR		 5262static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5263 void __iomem *ioaddr)
5264{
5265 /*
5266 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5267 * register to be written before TxDescAddrLow to work.
5268 * Switching from MMIO to I/O access fixes the issue as well.
5269 */
5270 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 5271 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 5272 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 5273 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 5274}
5275
5276static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5277{
5278 u16 cmd;
5279
5280 cmd = RTL_R16(CPlusCmd);
5281 RTL_W16(CPlusCmd, cmd);
5282 return cmd;
5283}
5284
fdd7b4c3 5285static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 5286{
5287 /* Low hurts. Let's disable the filtering. */
207d6e87 5288 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 5289}
5290
6dccd16b
FR		 5291static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5292{
3744100e 5293 static const struct rtl_cfg2_info {
6dccd16b
FR		 5294 u32 mac_version;
5295 u32 clk;
5296 u32 val;
5297 } cfg2_info [] = {
5298 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5299 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5300 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5301 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 5302 };
5303 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 5304 unsigned int i;
5305 u32 clk;
5306
5307 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 5308 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 5309 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5310 RTL_W32(0x7c, p->val);
5311 break;
5312 }
5313 }
5314}
5315
e6b763ea
FR		 5316static void rtl_set_rx_mode(struct net_device *dev)
5317{
5318 struct rtl8169_private *tp = netdev_priv(dev);
5319 void __iomem *ioaddr = tp->mmio_addr;
5320 u32 mc_filter[2]; /* Multicast hash filter */
5321 int rx_mode;
5322 u32 tmp = 0;
5323
5324 if (dev->flags & IFF_PROMISC) {
5325 /* Unconditionally log net taps. */
5326 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5327 rx_mode =
5328 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5329 AcceptAllPhys;
5330 mc_filter[1] = mc_filter[0] = 0xffffffff;
5331 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5332 (dev->flags & IFF_ALLMULTI)) {
5333 /* Too many to filter perfectly -- accept all multicasts. */
5334 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5335 mc_filter[1] = mc_filter[0] = 0xffffffff;
5336 } else {
5337 struct netdev_hw_addr *ha;
5338
5339 rx_mode = AcceptBroadcast | AcceptMyPhys;
5340 mc_filter[1] = mc_filter[0] = 0;
5341 netdev_for_each_mc_addr(ha, dev) {
5342 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5343 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5344 rx_mode |= AcceptMulticast;
5345 }
5346 }
5347
5348 if (dev->features & NETIF_F_RXALL)
5349 rx_mode |= (AcceptErr | AcceptRunt);
5350
5351 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5352
5353 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5354 u32 data = mc_filter[0];
5355
5356 mc_filter[0] = swab32(mc_filter[1]);
5357 mc_filter[1] = swab32(data);
5358 }
5359
0481776b
NW		 5360 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5361 mc_filter[1] = mc_filter[0] = 0xffffffff;
5362
e6b763ea
FR		 5363 RTL_W32(MAR0 + 4, mc_filter[1]);
5364 RTL_W32(MAR0 + 0, mc_filter[0]);
5365
5366 RTL_W32(RxConfig, tmp);
5367}
5368
07ce4064
FR		 5369static void rtl_hw_start_8169(struct net_device *dev)
5370{
5371 struct rtl8169_private *tp = netdev_priv(dev);
5372 void __iomem *ioaddr = tp->mmio_addr;
5373 struct pci_dev *pdev = tp->pci_dev;
07ce4064 5374
9cb427b6
FR		 5375 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5376 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5377 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5378 }
5379
1da177e4 5380 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 5381 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5382 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5383 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5384 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 5385 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5386
e542a226
HW		 5387 rtl_init_rxcfg(tp);
5388
f0298f81 5389 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 5390
6f0333b8 5391 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 5392
cecb5fd7
FR		 5393 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5394 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5395 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5396 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 5397 rtl_set_rx_tx_config_registers(tp);
1da177e4 5398
7f796d83 5399 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 5400
cecb5fd7
FR		 5401 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5402 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5403 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5404 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5405 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5406 }
5407
bcf0bf90
FR		 5408 RTL_W16(CPlusCmd, tp->cp_cmd);
5409
6dccd16b
FR		 5410 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5411
1da177e4
LT		 5412 /*
5413 * Undocumented corner. Supposedly:
5414 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5415 */
5416 RTL_W16(IntrMitigate, 0x0000);
5417
7f796d83 5418 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 5419
cecb5fd7
FR		 5420 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5421 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5422 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5423 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 5424 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5425 rtl_set_rx_tx_config_registers(tp);
5426 }
5427
1da177e4 5428 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5429
5430 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5431 RTL_R8(IntrMask);
1da177e4
LT		 5432
5433 RTL_W32(RxMissed, 0);
5434
07ce4064 5435 rtl_set_rx_mode(dev);
1da177e4
LT		 5436
5437 /* no early-rx interrupts */
05b9687b 5438 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5439}
1da177e4 5440
beb1fe18
HW		 5441static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5442{
5443 if (tp->csi_ops.write)
52989f0e 5444 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5445}
5446
5447static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5448{
52989f0e 5449 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5450}
5451
5452static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5453{
5454 u32 csi;
5455
beb1fe18
HW		 5456 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5457 rtl_csi_write(tp, 0x070c, csi | bits);
5458}
5459
5460static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5461{
5462 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5463}
5464
beb1fe18 5465static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5466{
beb1fe18 5467 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5468}
5469
ffc46952
FR		 5470DECLARE_RTL_COND(rtl_csiar_cond)
5471{
5472 void __iomem *ioaddr = tp->mmio_addr;
5473
5474 return RTL_R32(CSIAR) & CSIAR_FLAG;
5475}
5476
52989f0e 5477static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5478{
52989f0e 5479 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5480
5481 RTL_W32(CSIDR, value);
5482 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5483 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5484
ffc46952 5485 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5486}
5487
52989f0e 5488static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5489{
52989f0e 5490 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5491
5492 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5493 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5494
ffc46952
FR		 5495 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5496 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 5497}
5498
52989f0e 5499static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5500{
52989f0e 5501 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5502
5503 RTL_W32(CSIDR, value);
5504 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5505 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5506 CSIAR_FUNC_NIC);
5507
ffc46952 5508 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5509}
5510
52989f0e 5511static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5512{
52989f0e 5513 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5514
5515 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5516 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5517
ffc46952
FR		 5518 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5519 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 5520}
5521
45dd95c4 5522static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5523{
5524 void __iomem *ioaddr = tp->mmio_addr;
5525
5526 RTL_W32(CSIDR, value);
5527 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5528 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5529 CSIAR_FUNC_NIC2);
5530
5531 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5532}
5533
5534static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5535{
5536 void __iomem *ioaddr = tp->mmio_addr;
5537
5538 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5539 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5540
5541 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5542 RTL_R32(CSIDR) : ~0;
5543}
5544
baf63293 5545static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5546{
5547 struct csi_ops *ops = &tp->csi_ops;
5548
5549 switch (tp->mac_version) {
5550 case RTL_GIGA_MAC_VER_01:
5551 case RTL_GIGA_MAC_VER_02:
5552 case RTL_GIGA_MAC_VER_03:
5553 case RTL_GIGA_MAC_VER_04:
5554 case RTL_GIGA_MAC_VER_05:
5555 case RTL_GIGA_MAC_VER_06:
5556 case RTL_GIGA_MAC_VER_10:
5557 case RTL_GIGA_MAC_VER_11:
5558 case RTL_GIGA_MAC_VER_12:
5559 case RTL_GIGA_MAC_VER_13:
5560 case RTL_GIGA_MAC_VER_14:
5561 case RTL_GIGA_MAC_VER_15:
5562 case RTL_GIGA_MAC_VER_16:
5563 case RTL_GIGA_MAC_VER_17:
5564 ops->write = NULL;
5565 ops->read = NULL;
5566 break;
5567
7e18dca1 5568 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5569 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5570 ops->write = r8402_csi_write;
5571 ops->read = r8402_csi_read;
5572 break;
5573
45dd95c4 5574 case RTL_GIGA_MAC_VER_44:
5575 ops->write = r8411_csi_write;
5576 ops->read = r8411_csi_read;
5577 break;
5578
beb1fe18
HW		 5579 default:
5580 ops->write = r8169_csi_write;
5581 ops->read = r8169_csi_read;
5582 break;
5583 }
dacf8154
FR		 5584}
5585
5586struct ephy_info {
5587 unsigned int offset;
5588 u16 mask;
5589 u16 bits;
5590};
5591
fdf6fc06
FR		 5592static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5593 int len)
dacf8154
FR		 5594{
5595 u16 w;
5596
5597 while (len-- > 0) {
fdf6fc06
FR		 5598 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5599 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5600 e++;
5601 }
5602}
5603
b726e493
FR		 5604static void rtl_disable_clock_request(struct pci_dev *pdev)
5605{
7d7903b2
JL		 5606 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5607 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5608}
5609
e6de30d6 5610static void rtl_enable_clock_request(struct pci_dev *pdev)
5611{
7d7903b2
JL		 5612 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5613 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5614}
5615
b51ecea8 5616static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5617{
5618 void __iomem *ioaddr = tp->mmio_addr;
5619 u8 data;
5620
5621 data = RTL_R8(Config3);
5622
5623 if (enable)
5624 data |= Rdy_to_L23;
5625 else
5626 data &= ~Rdy_to_L23;
5627
5628 RTL_W8(Config3, data);
5629}
5630
b726e493
FR		 5631#define R8168_CPCMD_QUIRK_MASK (\
5632 EnableBist | \
5633 Mac_dbgo_oe | \
5634 Force_half_dup | \
5635 Force_rxflow_en | \
5636 Force_txflow_en | \
5637 Cxpl_dbg_sel | \
5638 ASF | \
5639 PktCntrDisable | \
5640 Mac_dbgo_sel)
5641
beb1fe18 5642static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5643{
beb1fe18
HW		 5644 void __iomem *ioaddr = tp->mmio_addr;
5645 struct pci_dev *pdev = tp->pci_dev;
5646
b726e493
FR		 5647 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5648
5649 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5650
faf1e785 5651 if (tp->dev->mtu <= ETH_DATA_LEN) {
5652 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5653 PCI_EXP_DEVCTL_NOSNOOP_EN);
5654 }
219a1e9d
FR		 5655}
5656
beb1fe18 5657static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5658{
beb1fe18
HW		 5659 void __iomem *ioaddr = tp->mmio_addr;
5660
5661 rtl_hw_start_8168bb(tp);
b726e493 5662
f0298f81 5663 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 5664
5665 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 5666}
5667
beb1fe18 5668static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5669{
beb1fe18
HW		 5670 void __iomem *ioaddr = tp->mmio_addr;
5671 struct pci_dev *pdev = tp->pci_dev;
5672
b726e493
FR		 5673 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5674
5675 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5676
faf1e785 5677 if (tp->dev->mtu <= ETH_DATA_LEN)
5678 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 5679
5680 rtl_disable_clock_request(pdev);
5681
5682 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5683}
5684
beb1fe18 5685static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5686{
350f7596 5687 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5688 { 0x01, 0, 0x0001 },
5689 { 0x02, 0x0800, 0x1000 },
5690 { 0x03, 0, 0x0042 },
5691 { 0x06, 0x0080, 0x0000 },
5692 { 0x07, 0, 0x2000 }
5693 };
5694
beb1fe18 5695 rtl_csi_access_enable_2(tp);
b726e493 5696
fdf6fc06 5697 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5698
beb1fe18 5699 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5700}
5701
beb1fe18 5702static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5703{
beb1fe18
HW		 5704 void __iomem *ioaddr = tp->mmio_addr;
5705 struct pci_dev *pdev = tp->pci_dev;
5706
5707 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 5708
5709 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5710
faf1e785 5711 if (tp->dev->mtu <= ETH_DATA_LEN)
5712 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 5713
5714 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5715}
5716
beb1fe18 5717static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5718{
beb1fe18
HW		 5719 void __iomem *ioaddr = tp->mmio_addr;
5720 struct pci_dev *pdev = tp->pci_dev;
5721
5722 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 5723
5724 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5725
5726 /* Magic. */
5727 RTL_W8(DBG_REG, 0x20);
5728
f0298f81 5729 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5730
faf1e785 5731 if (tp->dev->mtu <= ETH_DATA_LEN)
5732 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5733
5734 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5735}
5736
beb1fe18 5737static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5738{
beb1fe18 5739 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5740 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5741 { 0x02, 0x0800, 0x1000 },
5742 { 0x03, 0, 0x0002 },
5743 { 0x06, 0x0080, 0x0000 }
5744 };
5745
beb1fe18 5746 rtl_csi_access_enable_2(tp);
b726e493
FR		 5747
5748 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5749
fdf6fc06 5750 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5751
beb1fe18 5752 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5753}
5754
beb1fe18 5755static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5756{
350f7596 5757 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5758 { 0x01, 0, 0x0001 },
5759 { 0x03, 0x0400, 0x0220 }
5760 };
5761
beb1fe18 5762 rtl_csi_access_enable_2(tp);
b726e493 5763
fdf6fc06 5764 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5765
beb1fe18 5766 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5767}
5768
beb1fe18 5769static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5770{
beb1fe18 5771 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5772}
5773
beb1fe18 5774static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5775{
beb1fe18 5776 rtl_csi_access_enable_2(tp);
6fb07058 5777
beb1fe18 5778 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5779}
5780
beb1fe18 5781static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5782{
beb1fe18
HW		 5783 void __iomem *ioaddr = tp->mmio_addr;
5784 struct pci_dev *pdev = tp->pci_dev;
5785
5786 rtl_csi_access_enable_2(tp);
5b538df9
FR		 5787
5788 rtl_disable_clock_request(pdev);
5789
f0298f81 5790 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 5791
faf1e785 5792 if (tp->dev->mtu <= ETH_DATA_LEN)
5793 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 5794
5795 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5796}
5797
beb1fe18 5798static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5799{
beb1fe18
HW		 5800 void __iomem *ioaddr = tp->mmio_addr;
5801 struct pci_dev *pdev = tp->pci_dev;
5802
5803 rtl_csi_access_enable_1(tp);
4804b3b3 5804
faf1e785 5805 if (tp->dev->mtu <= ETH_DATA_LEN)
5806 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 5807
5808 RTL_W8(MaxTxPacketSize, TxPacketMax);
5809
5810 rtl_disable_clock_request(pdev);
5811}
5812
beb1fe18 5813static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5814{
beb1fe18
HW		 5815 void __iomem *ioaddr = tp->mmio_addr;
5816 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 5817 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 5818 { 0x0b, 0x0000, 0x0048 },
5819 { 0x19, 0x0020, 0x0050 },
5820 { 0x0c, 0x0100, 0x0020 }
e6de30d6 5821 };
e6de30d6 5822
beb1fe18 5823 rtl_csi_access_enable_1(tp);
e6de30d6 5824
5825 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5826
5827 RTL_W8(MaxTxPacketSize, TxPacketMax);
5828
1016a4a1 5829 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 5830
5831 rtl_enable_clock_request(pdev);
5832}
5833
beb1fe18 5834static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5835{
beb1fe18
HW		 5836 void __iomem *ioaddr = tp->mmio_addr;
5837 struct pci_dev *pdev = tp->pci_dev;
70090424 5838 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5839 { 0x00, 0x0200, 0x0100 },
5840 { 0x00, 0x0000, 0x0004 },
5841 { 0x06, 0x0002, 0x0001 },
5842 { 0x06, 0x0000, 0x0030 },
5843 { 0x07, 0x0000, 0x2000 },
5844 { 0x00, 0x0000, 0x0020 },
5845 { 0x03, 0x5800, 0x2000 },
5846 { 0x03, 0x0000, 0x0001 },
5847 { 0x01, 0x0800, 0x1000 },
5848 { 0x07, 0x0000, 0x4000 },
5849 { 0x1e, 0x0000, 0x2000 },
5850 { 0x19, 0xffff, 0xfe6c },
5851 { 0x0a, 0x0000, 0x0040 }
5852 };
5853
beb1fe18 5854 rtl_csi_access_enable_2(tp);
01dc7fec 5855
fdf6fc06 5856 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5857
faf1e785 5858 if (tp->dev->mtu <= ETH_DATA_LEN)
5859 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5860
5861 RTL_W8(MaxTxPacketSize, TxPacketMax);
5862
5863 rtl_disable_clock_request(pdev);
5864
5865 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5866 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5867 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5868
cecb5fd7 5869 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5870}
5871
beb1fe18 5872static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5873{
beb1fe18
HW		 5874 void __iomem *ioaddr = tp->mmio_addr;
5875 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5876 static const struct ephy_info e_info_8168e_2[] = {
5877 { 0x09, 0x0000, 0x0080 },
5878 { 0x19, 0x0000, 0x0224 }
5879 };
5880
beb1fe18 5881 rtl_csi_access_enable_1(tp);
70090424 5882
fdf6fc06 5883 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5884
faf1e785 5885 if (tp->dev->mtu <= ETH_DATA_LEN)
5886 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5887
fdf6fc06
FR		 5888 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5889 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5890 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5891 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5892 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5893 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5894 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5895 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5896
3090bd9a 5897 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5898
4521e1a9
FR		 5899 rtl_disable_clock_request(pdev);
5900
70090424
HW		 5901 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5902 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5903
5904 /* Adjust EEE LED frequency */
5905 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5906
5907 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5908 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5909 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5910}
5911
5f886e08 5912static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5913{
beb1fe18
HW		 5914 void __iomem *ioaddr = tp->mmio_addr;
5915 struct pci_dev *pdev = tp->pci_dev;
c2218925 5916
5f886e08 5917 rtl_csi_access_enable_2(tp);
c2218925
HW		 5918
5919 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5920
fdf6fc06
FR		 5921 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5922 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5923 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5924 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5925 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5926 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5927 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5928 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5929 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5930 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5931
5932 RTL_W8(MaxTxPacketSize, EarlySize);
5933
4521e1a9
FR		 5934 rtl_disable_clock_request(pdev);
5935
c2218925
HW		 5936 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5937 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5938 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5939 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5940 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5941}
5942
5f886e08
HW		 5943static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5944{
5945 void __iomem *ioaddr = tp->mmio_addr;
5946 static const struct ephy_info e_info_8168f_1[] = {
5947 { 0x06, 0x00c0, 0x0020 },
5948 { 0x08, 0x0001, 0x0002 },
5949 { 0x09, 0x0000, 0x0080 },
5950 { 0x19, 0x0000, 0x0224 }
5951 };
5952
5953 rtl_hw_start_8168f(tp);
5954
fdf6fc06 5955 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5956
706123d0 5957 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5958
5959 /* Adjust EEE LED frequency */
5960 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5961}
5962
b3d7b2f2
HW		 5963static void rtl_hw_start_8411(struct rtl8169_private *tp)
5964{
b3d7b2f2
HW		 5965 static const struct ephy_info e_info_8168f_1[] = {
5966 { 0x06, 0x00c0, 0x0020 },
5967 { 0x0f, 0xffff, 0x5200 },
5968 { 0x1e, 0x0000, 0x4000 },
5969 { 0x19, 0x0000, 0x0224 }
5970 };
5971
5972 rtl_hw_start_8168f(tp);
b51ecea8 5973 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5974
fdf6fc06 5975 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5976
706123d0 5977 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5978}
5979
5fbea337 5980static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b
HW		 5981{
5982 void __iomem *ioaddr = tp->mmio_addr;
5983 struct pci_dev *pdev = tp->pci_dev;
5984
beb330a4 5985 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5986
c558386b
HW		 5987 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5988 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5989 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5990 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5991
5992 rtl_csi_access_enable_1(tp);
5993
5994 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5995
706123d0
CHL		 5996 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5997 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5998 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5999
4521e1a9 6000 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 6001 RTL_W8(MaxTxPacketSize, EarlySize);
6002
6003 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6004 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6005
6006 /* Adjust EEE LED frequency */
6007 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6008
706123d0
CHL		 6009 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6010 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 6011
6012 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 6013}
6014
5fbea337
CHL		 6015static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6016{
6017 void __iomem *ioaddr = tp->mmio_addr;
6018 static const struct ephy_info e_info_8168g_1[] = {
6019 { 0x00, 0x0000, 0x0008 },
6020 { 0x0c, 0x37d0, 0x0820 },
6021 { 0x1e, 0x0000, 0x0001 },
6022 { 0x19, 0x8000, 0x0000 }
6023 };
6024
6025 rtl_hw_start_8168g(tp);
6026
6027 /* disable aspm and clock request before access ephy */
6028 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6029 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6030 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6031}
6032
57538c4a 6033static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6034{
6035 void __iomem *ioaddr = tp->mmio_addr;
6036 static const struct ephy_info e_info_8168g_2[] = {
6037 { 0x00, 0x0000, 0x0008 },
6038 { 0x0c, 0x3df0, 0x0200 },
6039 { 0x19, 0xffff, 0xfc00 },
6040 { 0x1e, 0xffff, 0x20eb }
6041 };
6042
5fbea337 6043 rtl_hw_start_8168g(tp);
57538c4a 6044
6045 /* disable aspm and clock request before access ephy */
6046 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6047 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6048 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6049}
6050
45dd95c4 6051static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6052{
6053 void __iomem *ioaddr = tp->mmio_addr;
6054 static const struct ephy_info e_info_8411_2[] = {
6055 { 0x00, 0x0000, 0x0008 },
6056 { 0x0c, 0x3df0, 0x0200 },
6057 { 0x0f, 0xffff, 0x5200 },
6058 { 0x19, 0x0020, 0x0000 },
6059 { 0x1e, 0x0000, 0x2000 }
6060 };
6061
5fbea337 6062 rtl_hw_start_8168g(tp);
45dd95c4 6063
6064 /* disable aspm and clock request before access ephy */
6065 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6066 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6067 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6068}
6069
6e1d0b89
CHL		 6070static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6071{
6072 void __iomem *ioaddr = tp->mmio_addr;
6073 struct pci_dev *pdev = tp->pci_dev;
72521ea0 6074 int rg_saw_cnt;
6e1d0b89
CHL		 6075 u32 data;
6076 static const struct ephy_info e_info_8168h_1[] = {
6077 { 0x1e, 0x0800, 0x0001 },
6078 { 0x1d, 0x0000, 0x0800 },
6079 { 0x05, 0xffff, 0x2089 },
6080 { 0x06, 0xffff, 0x5881 },
6081 { 0x04, 0xffff, 0x154a },
6082 { 0x01, 0xffff, 0x068b }
6083 };
6084
6085 /* disable aspm and clock request before access ephy */
6086 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6087 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6088 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6089
6090 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6091
6092 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6093 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6094 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6095 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6096
6097 rtl_csi_access_enable_1(tp);
6098
6099 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6100
706123d0
CHL		 6101 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6102 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 6103
706123d0 6104 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 6105
706123d0 6106 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 6107
6108 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6109
6e1d0b89
CHL		 6110 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6111 RTL_W8(MaxTxPacketSize, EarlySize);
6112
6113 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6114 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6115
6116 /* Adjust EEE LED frequency */
6117 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6118
6119 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6120 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89
CHL		 6121
6122 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6123
706123d0 6124 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 6125
6126 rtl_pcie_state_l2l3_enable(tp, false);
6127
6128 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 6129 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 6130 rtl_writephy(tp, 0x1f, 0x0000);
6131 if (rg_saw_cnt > 0) {
6132 u16 sw_cnt_1ms_ini;
6133
6134 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6135 sw_cnt_1ms_ini &= 0x0fff;
6136 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 6137 data &= ~0x0fff;
6e1d0b89
CHL		 6138 data |= sw_cnt_1ms_ini;
6139 r8168_mac_ocp_write(tp, 0xd412, data);
6140 }
6141
6142 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 6143 data &= ~0xf0;
6144 data |= 0x70;
6e1d0b89
CHL		 6145 r8168_mac_ocp_write(tp, 0xe056, data);
6146
6147 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 6148 data &= ~0x6000;
6149 data |= 0x8008;
6e1d0b89
CHL		 6150 r8168_mac_ocp_write(tp, 0xe052, data);
6151
6152 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 6153 data &= ~0x01ff;
6e1d0b89
CHL		 6154 data |= 0x017f;
6155 r8168_mac_ocp_write(tp, 0xe0d6, data);
6156
6157 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 6158 data &= ~0x0fff;
6e1d0b89
CHL		 6159 data |= 0x047f;
6160 r8168_mac_ocp_write(tp, 0xd420, data);
6161
6162 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6163 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6164 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6165 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6166}
6167
935e2218
CHL		 6168static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6169{
6170 void __iomem *ioaddr = tp->mmio_addr;
6171 struct pci_dev *pdev = tp->pci_dev;
6172
003609da
CHL		 6173 rtl8168ep_stop_cmac(tp);
6174
935e2218
CHL		 6175 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6176
6177 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6178 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6179 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6180 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6181
6182 rtl_csi_access_enable_1(tp);
6183
6184 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6185
6186 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6187 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6188
6189 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6190
6191 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6192
935e2218
CHL		 6193 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6194 RTL_W8(MaxTxPacketSize, EarlySize);
6195
6196 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6197 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6198
6199 /* Adjust EEE LED frequency */
6200 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6201
6202 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6203
6204 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6205
6206 rtl_pcie_state_l2l3_enable(tp, false);
6207}
6208
6209static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6210{
6211 void __iomem *ioaddr = tp->mmio_addr;
6212 static const struct ephy_info e_info_8168ep_1[] = {
6213 { 0x00, 0xffff, 0x10ab },
6214 { 0x06, 0xffff, 0xf030 },
6215 { 0x08, 0xffff, 0x2006 },
6216 { 0x0d, 0xffff, 0x1666 },
6217 { 0x0c, 0x3ff0, 0x0000 }
6218 };
6219
6220 /* disable aspm and clock request before access ephy */
6221 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6222 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6223 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6224
6225 rtl_hw_start_8168ep(tp);
6226}
6227
6228static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6229{
6230 void __iomem *ioaddr = tp->mmio_addr;
6231 static const struct ephy_info e_info_8168ep_2[] = {
6232 { 0x00, 0xffff, 0x10a3 },
6233 { 0x19, 0xffff, 0xfc00 },
6234 { 0x1e, 0xffff, 0x20ea }
6235 };
6236
6237 /* disable aspm and clock request before access ephy */
6238 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6239 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6240 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6241
6242 rtl_hw_start_8168ep(tp);
6243
6244 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6245 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6246}
6247
6248static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6249{
6250 void __iomem *ioaddr = tp->mmio_addr;
6251 u32 data;
6252 static const struct ephy_info e_info_8168ep_3[] = {
6253 { 0x00, 0xffff, 0x10a3 },
6254 { 0x19, 0xffff, 0x7c00 },
6255 { 0x1e, 0xffff, 0x20eb },
6256 { 0x0d, 0xffff, 0x1666 }
6257 };
6258
6259 /* disable aspm and clock request before access ephy */
6260 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6261 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6262 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6263
6264 rtl_hw_start_8168ep(tp);
6265
6266 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6267 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6268
6269 data = r8168_mac_ocp_read(tp, 0xd3e2);
6270 data &= 0xf000;
6271 data |= 0x0271;
6272 r8168_mac_ocp_write(tp, 0xd3e2, data);
6273
6274 data = r8168_mac_ocp_read(tp, 0xd3e4);
6275 data &= 0xff00;
6276 r8168_mac_ocp_write(tp, 0xd3e4, data);
6277
6278 data = r8168_mac_ocp_read(tp, 0xe860);
6279 data |= 0x0080;
6280 r8168_mac_ocp_write(tp, 0xe860, data);
6281}
6282
07ce4064
FR		 6283static void rtl_hw_start_8168(struct net_device *dev)
6284{
2dd99530
FR		 6285 struct rtl8169_private *tp = netdev_priv(dev);
6286 void __iomem *ioaddr = tp->mmio_addr;
6287
6288 RTL_W8(Cfg9346, Cfg9346_Unlock);
6289
f0298f81 6290 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 6291
6f0333b8 6292 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 6293
0e485150 6294 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 6295
6296 RTL_W16(CPlusCmd, tp->cp_cmd);
6297
0e485150 6298 RTL_W16(IntrMitigate, 0x5151);
2dd99530 6299
0e485150 6300 /* Work around for RxFIFO overflow. */
811fd301 6301 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 6302 tp->event_slow |= RxFIFOOver | PCSTimeout;
6303 tp->event_slow &= ~RxOverflow;
0e485150
FR		 6304 }
6305
6306 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 6307
1a964649 6308 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 6309
6310 RTL_R8(IntrMask);
6311
219a1e9d
FR		 6312 switch (tp->mac_version) {
6313 case RTL_GIGA_MAC_VER_11:
beb1fe18 6314 rtl_hw_start_8168bb(tp);
4804b3b3 6315 break;
219a1e9d
FR		 6316
6317 case RTL_GIGA_MAC_VER_12:
6318 case RTL_GIGA_MAC_VER_17:
beb1fe18 6319 rtl_hw_start_8168bef(tp);
4804b3b3 6320 break;
219a1e9d
FR		 6321
6322 case RTL_GIGA_MAC_VER_18:
beb1fe18 6323 rtl_hw_start_8168cp_1(tp);
4804b3b3 6324 break;
219a1e9d
FR		 6325
6326 case RTL_GIGA_MAC_VER_19:
beb1fe18 6327 rtl_hw_start_8168c_1(tp);
4804b3b3 6328 break;
219a1e9d
FR		 6329
6330 case RTL_GIGA_MAC_VER_20:
beb1fe18 6331 rtl_hw_start_8168c_2(tp);
4804b3b3 6332 break;
219a1e9d 6333
197ff761 6334 case RTL_GIGA_MAC_VER_21:
beb1fe18 6335 rtl_hw_start_8168c_3(tp);
4804b3b3 6336 break;
197ff761 6337
6fb07058 6338 case RTL_GIGA_MAC_VER_22:
beb1fe18 6339 rtl_hw_start_8168c_4(tp);
4804b3b3 6340 break;
6fb07058 6341
ef3386f0 6342 case RTL_GIGA_MAC_VER_23:
beb1fe18 6343 rtl_hw_start_8168cp_2(tp);
4804b3b3 6344 break;
ef3386f0 6345
7f3e3d3a 6346 case RTL_GIGA_MAC_VER_24:
beb1fe18 6347 rtl_hw_start_8168cp_3(tp);
4804b3b3 6348 break;
7f3e3d3a 6349
5b538df9 6350 case RTL_GIGA_MAC_VER_25:
daf9df6d 6351 case RTL_GIGA_MAC_VER_26:
6352 case RTL_GIGA_MAC_VER_27:
beb1fe18 6353 rtl_hw_start_8168d(tp);
4804b3b3 6354 break;
5b538df9 6355
e6de30d6 6356 case RTL_GIGA_MAC_VER_28:
beb1fe18 6357 rtl_hw_start_8168d_4(tp);
4804b3b3 6358 break;
cecb5fd7 6359
4804b3b3 6360 case RTL_GIGA_MAC_VER_31:
beb1fe18 6361 rtl_hw_start_8168dp(tp);
4804b3b3 6362 break;
6363
01dc7fec 6364 case RTL_GIGA_MAC_VER_32:
6365 case RTL_GIGA_MAC_VER_33:
beb1fe18 6366 rtl_hw_start_8168e_1(tp);
70090424
HW		 6367 break;
6368 case RTL_GIGA_MAC_VER_34:
beb1fe18 6369 rtl_hw_start_8168e_2(tp);
01dc7fec 6370 break;
e6de30d6 6371
c2218925
HW		 6372 case RTL_GIGA_MAC_VER_35:
6373 case RTL_GIGA_MAC_VER_36:
beb1fe18 6374 rtl_hw_start_8168f_1(tp);
c2218925
HW		 6375 break;
6376
b3d7b2f2
HW		 6377 case RTL_GIGA_MAC_VER_38:
6378 rtl_hw_start_8411(tp);
6379 break;
6380
c558386b
HW		 6381 case RTL_GIGA_MAC_VER_40:
6382 case RTL_GIGA_MAC_VER_41:
6383 rtl_hw_start_8168g_1(tp);
6384 break;
57538c4a 6385 case RTL_GIGA_MAC_VER_42:
6386 rtl_hw_start_8168g_2(tp);
6387 break;
c558386b 6388
45dd95c4 6389 case RTL_GIGA_MAC_VER_44:
6390 rtl_hw_start_8411_2(tp);
6391 break;
6392
6e1d0b89
CHL		 6393 case RTL_GIGA_MAC_VER_45:
6394 case RTL_GIGA_MAC_VER_46:
6395 rtl_hw_start_8168h_1(tp);
6396 break;
6397
935e2218
CHL		 6398 case RTL_GIGA_MAC_VER_49:
6399 rtl_hw_start_8168ep_1(tp);
6400 break;
6401
6402 case RTL_GIGA_MAC_VER_50:
6403 rtl_hw_start_8168ep_2(tp);
6404 break;
6405
6406 case RTL_GIGA_MAC_VER_51:
6407 rtl_hw_start_8168ep_3(tp);
6408 break;
6409
219a1e9d
FR		 6410 default:
6411 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6412 dev->name, tp->mac_version);
4804b3b3 6413 break;
219a1e9d 6414 }
2dd99530 6415
1a964649 6416 RTL_W8(Cfg9346, Cfg9346_Lock);
6417
0e485150
FR		 6418 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6419
1a964649 6420 rtl_set_rx_mode(dev);
b8363901 6421
05b9687b 6422 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 6423}
1da177e4 6424
2857ffb7
FR		 6425#define R810X_CPCMD_QUIRK_MASK (\
6426 EnableBist | \
6427 Mac_dbgo_oe | \
6428 Force_half_dup | \
5edcc537 6429 Force_rxflow_en | \
2857ffb7
FR		 6430 Force_txflow_en | \
6431 Cxpl_dbg_sel | \
6432 ASF | \
6433 PktCntrDisable | \
d24e9aaf 6434 Mac_dbgo_sel)
2857ffb7 6435
beb1fe18 6436static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 6437{
beb1fe18
HW		 6438 void __iomem *ioaddr = tp->mmio_addr;
6439 struct pci_dev *pdev = tp->pci_dev;
350f7596 6440 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 6441 { 0x01, 0, 0x6e65 },
6442 { 0x02, 0, 0x091f },
6443 { 0x03, 0, 0xc2f9 },
6444 { 0x06, 0, 0xafb5 },
6445 { 0x07, 0, 0x0e00 },
6446 { 0x19, 0, 0xec80 },
6447 { 0x01, 0, 0x2e65 },
6448 { 0x01, 0, 0x6e65 }
6449 };
6450 u8 cfg1;
6451
beb1fe18 6452 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6453
6454 RTL_W8(DBG_REG, FIX_NAK_1);
6455
6456 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6457
6458 RTL_W8(Config1,
6459 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6460 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6461
6462 cfg1 = RTL_R8(Config1);
6463 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6464 RTL_W8(Config1, cfg1 & ~LEDS0);
6465
fdf6fc06 6466 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 6467}
6468
beb1fe18 6469static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 6470{
beb1fe18
HW		 6471 void __iomem *ioaddr = tp->mmio_addr;
6472 struct pci_dev *pdev = tp->pci_dev;
6473
6474 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6475
6476 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6477
6478 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6479 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 6480}
6481
beb1fe18 6482static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 6483{
beb1fe18 6484 rtl_hw_start_8102e_2(tp);
2857ffb7 6485
fdf6fc06 6486 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 6487}
6488
beb1fe18 6489static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 6490{
beb1fe18 6491 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 6492 static const struct ephy_info e_info_8105e_1[] = {
6493 { 0x07, 0, 0x4000 },
6494 { 0x19, 0, 0x0200 },
6495 { 0x19, 0, 0x0020 },
6496 { 0x1e, 0, 0x2000 },
6497 { 0x03, 0, 0x0001 },
6498 { 0x19, 0, 0x0100 },
6499 { 0x19, 0, 0x0004 },
6500 { 0x0a, 0, 0x0020 }
6501 };
6502
cecb5fd7 6503 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 6504 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6505
cecb5fd7 6506 /* Disable Early Tally Counter */
5a5e4443
HW		 6507 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6508
6509 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 6510 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 6511
fdf6fc06 6512 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 6513
6514 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 6515}
6516
beb1fe18 6517static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 6518{
beb1fe18 6519 rtl_hw_start_8105e_1(tp);
fdf6fc06 6520 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 6521}
6522
7e18dca1
HW		 6523static void rtl_hw_start_8402(struct rtl8169_private *tp)
6524{
6525 void __iomem *ioaddr = tp->mmio_addr;
6526 static const struct ephy_info e_info_8402[] = {
6527 { 0x19, 0xffff, 0xff64 },
6528 { 0x1e, 0, 0x4000 }
6529 };
6530
6531 rtl_csi_access_enable_2(tp);
6532
6533 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6534 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6535
6536 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6537 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6538
fdf6fc06 6539 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 6540
6541 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6542
fdf6fc06
FR		 6543 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6544 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6545 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6546 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6547 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6548 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6549 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6550
6551 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6552}
6553
5598bfe5
HW		 6554static void rtl_hw_start_8106(struct rtl8169_private *tp)
6555{
6556 void __iomem *ioaddr = tp->mmio_addr;
6557
6558 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6559 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6560
4521e1a9 6561 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 6562 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6563 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 6564
6565 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6566}
6567
07ce4064
FR		 6568static void rtl_hw_start_8101(struct net_device *dev)
6569{
cdf1a608
FR		 6570 struct rtl8169_private *tp = netdev_priv(dev);
6571 void __iomem *ioaddr = tp->mmio_addr;
6572 struct pci_dev *pdev = tp->pci_dev;
6573
da78dbff
FR		 6574 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6575 tp->event_slow &= ~RxFIFOOver;
811fd301 6576
cecb5fd7 6577 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6578 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6579 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6580 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6581
d24e9aaf
HW		 6582 RTL_W8(Cfg9346, Cfg9346_Unlock);
6583
1a964649 6584 RTL_W8(MaxTxPacketSize, TxPacketMax);
6585
6586 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6587
6588 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6589 RTL_W16(CPlusCmd, tp->cp_cmd);
6590
6591 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6592
6593 rtl_set_rx_tx_config_registers(tp);
6594
2857ffb7
FR		 6595 switch (tp->mac_version) {
6596 case RTL_GIGA_MAC_VER_07:
beb1fe18 6597 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6598 break;
6599
6600 case RTL_GIGA_MAC_VER_08:
beb1fe18 6601 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6602 break;
6603
6604 case RTL_GIGA_MAC_VER_09:
beb1fe18 6605 rtl_hw_start_8102e_2(tp);
2857ffb7 6606 break;
5a5e4443
HW		 6607
6608 case RTL_GIGA_MAC_VER_29:
beb1fe18 6609 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6610 break;
6611 case RTL_GIGA_MAC_VER_30:
beb1fe18 6612 rtl_hw_start_8105e_2(tp);
5a5e4443 6613 break;
7e18dca1
HW		 6614
6615 case RTL_GIGA_MAC_VER_37:
6616 rtl_hw_start_8402(tp);
6617 break;
5598bfe5
HW		 6618
6619 case RTL_GIGA_MAC_VER_39:
6620 rtl_hw_start_8106(tp);
6621 break;
58152cd4 6622 case RTL_GIGA_MAC_VER_43:
6623 rtl_hw_start_8168g_2(tp);
6624 break;
6e1d0b89
CHL		 6625 case RTL_GIGA_MAC_VER_47:
6626 case RTL_GIGA_MAC_VER_48:
6627 rtl_hw_start_8168h_1(tp);
6628 break;
cdf1a608
FR		 6629 }
6630
d24e9aaf 6631 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 6632
cdf1a608
FR		 6633 RTL_W16(IntrMitigate, 0x0000);
6634
cdf1a608 6635 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6636
cdf1a608
FR		 6637 rtl_set_rx_mode(dev);
6638
1a964649 6639 RTL_R8(IntrMask);
6640
cdf1a608 6641 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 6642}
6643
6644static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6645{
d58d46b5
FR		 6646 struct rtl8169_private *tp = netdev_priv(dev);
6647
6648 if (new_mtu < ETH_ZLEN ||
6649 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 6650 return -EINVAL;
6651
d58d46b5
FR		 6652 if (new_mtu > ETH_DATA_LEN)
6653 rtl_hw_jumbo_enable(tp);
6654 else
6655 rtl_hw_jumbo_disable(tp);
6656
1da177e4 6657 dev->mtu = new_mtu;
350fb32a
MM		 6658 netdev_update_features(dev);
6659
323bb685 6660 return 0;
1da177e4
LT		 6661}
6662
6663static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6664{
95e0918d 6665 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6666 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6667}
6668
6f0333b8
ED		 6669static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6670 void **data_buff, struct RxDesc *desc)
1da177e4 6671{
48addcc9 6672 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 6673 DMA_FROM_DEVICE);
48addcc9 6674
6f0333b8
ED		 6675 kfree(*data_buff);
6676 *data_buff = NULL;
1da177e4
LT		 6677 rtl8169_make_unusable_by_asic(desc);
6678}
6679
6680static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6681{
6682 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6683
a0750138
AD		 6684 /* Force memory writes to complete before releasing descriptor */
6685 dma_wmb();
6686
1da177e4
LT		 6687 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6688}
6689
6690static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6691 u32 rx_buf_sz)
6692{
6693 desc->addr = cpu_to_le64(mapping);
1da177e4
LT		 6694 rtl8169_mark_to_asic(desc, rx_buf_sz);
6695}
6696
6f0333b8
ED		 6697static inline void *rtl8169_align(void *data)
6698{
6699 return (void *)ALIGN((long)data, 16);
6700}
6701
0ecbe1ca
SG		 6702static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6703 struct RxDesc *desc)
1da177e4 6704{
6f0333b8 6705 void *data;
1da177e4 6706 dma_addr_t mapping;
48addcc9 6707 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 6708 struct net_device *dev = tp->dev;
6f0333b8 6709 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 6710
6f0333b8
ED		 6711 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6712 if (!data)
6713 return NULL;
e9f63f30 6714
6f0333b8
ED		 6715 if (rtl8169_align(data) != data) {
6716 kfree(data);
6717 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6718 if (!data)
6719 return NULL;
6720 }
3eafe507 6721
48addcc9 6722 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 6723 DMA_FROM_DEVICE);
d827d86b
SG		 6724 if (unlikely(dma_mapping_error(d, mapping))) {
6725 if (net_ratelimit())
6726 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6727 goto err_out;
d827d86b 6728 }
1da177e4
LT		 6729
6730 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 6731 return data;
3eafe507
SG		 6732
6733err_out:
6734 kfree(data);
6735 return NULL;
1da177e4
LT		 6736}
6737
6738static void rtl8169_rx_clear(struct rtl8169_private *tp)
6739{
07d3f51f 6740 unsigned int i;
1da177e4
LT		 6741
6742 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6743 if (tp->Rx_databuff[i]) {
6744 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6745 tp->RxDescArray + i);
6746 }
6747 }
6748}
6749
0ecbe1ca 6750static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6751{
0ecbe1ca
SG		 6752 desc->opts1 |= cpu_to_le32(RingEnd);
6753}
5b0384f4 6754
0ecbe1ca
SG		 6755static int rtl8169_rx_fill(struct rtl8169_private *tp)
6756{
6757 unsigned int i;
1da177e4 6758
0ecbe1ca
SG		 6759 for (i = 0; i < NUM_RX_DESC; i++) {
6760 void *data;
4ae47c2d 6761
6f0333b8 6762 if (tp->Rx_databuff[i])
1da177e4 6763 continue;
bcf0bf90 6764
0ecbe1ca 6765 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6766 if (!data) {
6767 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6768 goto err_out;
6f0333b8
ED		 6769 }
6770 tp->Rx_databuff[i] = data;
1da177e4 6771 }
1da177e4 6772
0ecbe1ca
SG		 6773 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6774 return 0;
6775
6776err_out:
6777 rtl8169_rx_clear(tp);
6778 return -ENOMEM;
1da177e4
LT		 6779}
6780
1da177e4
LT		 6781static int rtl8169_init_ring(struct net_device *dev)
6782{
6783 struct rtl8169_private *tp = netdev_priv(dev);
6784
6785 rtl8169_init_ring_indexes(tp);
6786
6787 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 6788 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 6789
0ecbe1ca 6790 return rtl8169_rx_fill(tp);
1da177e4
LT		 6791}
6792
48addcc9 6793static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6794 struct TxDesc *desc)
6795{
6796 unsigned int len = tx_skb->len;
6797
48addcc9
SG		 6798 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6799
1da177e4
LT		 6800 desc->opts1 = 0x00;
6801 desc->opts2 = 0x00;
6802 desc->addr = 0x00;
6803 tx_skb->len = 0;
6804}
6805
3eafe507
SG		 6806static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6807 unsigned int n)
1da177e4
LT		 6808{
6809 unsigned int i;
6810
3eafe507
SG		 6811 for (i = 0; i < n; i++) {
6812 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6813 struct ring_info *tx_skb = tp->tx_skb + entry;
6814 unsigned int len = tx_skb->len;
6815
6816 if (len) {
6817 struct sk_buff *skb = tx_skb->skb;
6818
48addcc9 6819 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 6820 tp->TxDescArray + entry);
6821 if (skb) {
cac4b22f 6822 tp->dev->stats.tx_dropped++;
989c9ba1 6823 dev_kfree_skb_any(skb);
1da177e4
LT		 6824 tx_skb->skb = NULL;
6825 }
1da177e4
LT		 6826 }
6827 }
3eafe507
SG		 6828}
6829
6830static void rtl8169_tx_clear(struct rtl8169_private *tp)
6831{
6832 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6833 tp->cur_tx = tp->dirty_tx = 0;
6834}
6835
4422bcd4 6836static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6837{
c4028958 6838 struct net_device *dev = tp->dev;
56de414c 6839 int i;
1da177e4 6840
da78dbff
FR		 6841 napi_disable(&tp->napi);
6842 netif_stop_queue(dev);
6843 synchronize_sched();
1da177e4 6844
c7c2c39b 6845 rtl8169_hw_reset(tp);
6846
56de414c
FR		 6847 for (i = 0; i < NUM_RX_DESC; i++)
6848 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6849
1da177e4 6850 rtl8169_tx_clear(tp);
c7c2c39b 6851 rtl8169_init_ring_indexes(tp);
1da177e4 6852
da78dbff 6853 napi_enable(&tp->napi);
56de414c
FR		 6854 rtl_hw_start(dev);
6855 netif_wake_queue(dev);
6856 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 6857}
6858
6859static void rtl8169_tx_timeout(struct net_device *dev)
6860{
da78dbff
FR		 6861 struct rtl8169_private *tp = netdev_priv(dev);
6862
6863 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6864}
6865
6866static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6867 u32 *opts)
1da177e4
LT		 6868{
6869 struct skb_shared_info *info = skb_shinfo(skb);
6870 unsigned int cur_frag, entry;
6e1d0b89 6871 struct TxDesc *uninitialized_var(txd);
48addcc9 6872 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6873
6874 entry = tp->cur_tx;
6875 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6876 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6877 dma_addr_t mapping;
6878 u32 status, len;
6879 void *addr;
6880
6881 entry = (entry + 1) % NUM_TX_DESC;
6882
6883 txd = tp->TxDescArray + entry;
9e903e08 6884 len = skb_frag_size(frag);
929f6189 6885 addr = skb_frag_address(frag);
48addcc9 6886 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6887 if (unlikely(dma_mapping_error(d, mapping))) {
6888 if (net_ratelimit())
6889 netif_err(tp, drv, tp->dev,
6890 "Failed to map TX fragments DMA!\n");
3eafe507 6891 goto err_out;
d827d86b 6892 }
1da177e4 6893
cecb5fd7 6894 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6895 status = opts[0] | len |
6896 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6897
6898 txd->opts1 = cpu_to_le32(status);
2b7b4318 6899 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6900 txd->addr = cpu_to_le64(mapping);
6901
6902 tp->tx_skb[entry].len = len;
6903 }
6904
6905 if (cur_frag) {
6906 tp->tx_skb[entry].skb = skb;
6907 txd->opts1 |= cpu_to_le32(LastFrag);
6908 }
6909
6910 return cur_frag;
3eafe507
SG		 6911
6912err_out:
6913 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6914 return -EIO;
1da177e4
LT		 6915}
6916
b423e9ae 6917static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6918{
6919 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6920}
6921
e974604b 6922static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6923 struct net_device *dev);
6924/* r8169_csum_workaround()
6925 * The hw limites the value the transport offset. When the offset is out of the
6926 * range, calculate the checksum by sw.
6927 */
6928static void r8169_csum_workaround(struct rtl8169_private *tp,
6929 struct sk_buff *skb)
6930{
6931 if (skb_shinfo(skb)->gso_size) {
6932 netdev_features_t features = tp->dev->features;
6933 struct sk_buff *segs, *nskb;
6934
6935 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6936 segs = skb_gso_segment(skb, features);
6937 if (IS_ERR(segs) || !segs)
6938 goto drop;
6939
6940 do {
6941 nskb = segs;
6942 segs = segs->next;
6943 nskb->next = NULL;
6944 rtl8169_start_xmit(nskb, tp->dev);
6945 } while (segs);
6946
eb781397 6947 dev_consume_skb_any(skb);
e974604b 6948 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6949 if (skb_checksum_help(skb) < 0)
6950 goto drop;
6951
6952 rtl8169_start_xmit(skb, tp->dev);
6953 } else {
6954 struct net_device_stats *stats;
6955
6956drop:
6957 stats = &tp->dev->stats;
6958 stats->tx_dropped++;
eb781397 6959 dev_kfree_skb_any(skb);
e974604b 6960 }
6961}
6962
6963/* msdn_giant_send_check()
6964 * According to the document of microsoft, the TCP Pseudo Header excludes the
6965 * packet length for IPv6 TCP large packets.
6966 */
6967static int msdn_giant_send_check(struct sk_buff *skb)
6968{
6969 const struct ipv6hdr *ipv6h;
6970 struct tcphdr *th;
6971 int ret;
6972
6973 ret = skb_cow_head(skb, 0);
6974 if (ret)
6975 return ret;
6976
6977 ipv6h = ipv6_hdr(skb);
6978 th = tcp_hdr(skb);
6979
6980 th->check = 0;
6981 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6982
6983 return ret;
6984}
6985
6986static inline __be16 get_protocol(struct sk_buff *skb)
6987{
6988 __be16 protocol;
6989
6990 if (skb->protocol == htons(ETH_P_8021Q))
6991 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6992 else
6993 protocol = skb->protocol;
6994
6995 return protocol;
6996}
6997
5888d3fc 6998static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6999 struct sk_buff *skb, u32 *opts)
1da177e4 7000{
350fb32a
MM		 7001 u32 mss = skb_shinfo(skb)->gso_size;
7002
2b7b4318
FR		 7003 if (mss) {
7004 opts[0] |= TD_LSO;
5888d3fc 7005 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7006 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7007 const struct iphdr *ip = ip_hdr(skb);
7008
7009 if (ip->protocol == IPPROTO_TCP)
7010 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7011 else if (ip->protocol == IPPROTO_UDP)
7012 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7013 else
7014 WARN_ON_ONCE(1);
7015 }
7016
7017 return true;
7018}
7019
7020static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7021 struct sk_buff *skb, u32 *opts)
7022{
bdfa4ed6 7023 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 7024 u32 mss = skb_shinfo(skb)->gso_size;
7025
7026 if (mss) {
e974604b 7027 if (transport_offset > GTTCPHO_MAX) {
7028 netif_warn(tp, tx_err, tp->dev,
7029 "Invalid transport offset 0x%x for TSO\n",
7030 transport_offset);
7031 return false;
7032 }
7033
7034 switch (get_protocol(skb)) {
7035 case htons(ETH_P_IP):
7036 opts[0] |= TD1_GTSENV4;
7037 break;
7038
7039 case htons(ETH_P_IPV6):
7040 if (msdn_giant_send_check(skb))
7041 return false;
7042
7043 opts[0] |= TD1_GTSENV6;
7044 break;
7045
7046 default:
7047 WARN_ON_ONCE(1);
7048 break;
7049 }
7050
bdfa4ed6 7051 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 7052 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 7053 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 7054 u8 ip_protocol;
1da177e4 7055
b423e9ae 7056 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7057 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 7058
e974604b 7059 if (transport_offset > TCPHO_MAX) {
7060 netif_warn(tp, tx_err, tp->dev,
7061 "Invalid transport offset 0x%x\n",
7062 transport_offset);
7063 return false;
7064 }
7065
7066 switch (get_protocol(skb)) {
7067 case htons(ETH_P_IP):
7068 opts[1] |= TD1_IPv4_CS;
7069 ip_protocol = ip_hdr(skb)->protocol;
7070 break;
7071
7072 case htons(ETH_P_IPV6):
7073 opts[1] |= TD1_IPv6_CS;
7074 ip_protocol = ipv6_hdr(skb)->nexthdr;
7075 break;
7076
7077 default:
7078 ip_protocol = IPPROTO_RAW;
7079 break;
7080 }
7081
7082 if (ip_protocol == IPPROTO_TCP)
7083 opts[1] |= TD1_TCP_CS;
7084 else if (ip_protocol == IPPROTO_UDP)
7085 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 7086 else
7087 WARN_ON_ONCE(1);
e974604b 7088
7089 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 7090 } else {
7091 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7092 return !eth_skb_pad(skb);
1da177e4 7093 }
5888d3fc 7094
b423e9ae 7095 return true;
1da177e4
LT		 7096}
7097
61357325
SH		 7098static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7099 struct net_device *dev)
1da177e4
LT		 7100{
7101 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 7102 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 7103 struct TxDesc *txd = tp->TxDescArray + entry;
7104 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 7105 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 7106 dma_addr_t mapping;
7107 u32 status, len;
2b7b4318 7108 u32 opts[2];
3eafe507 7109 int frags;
5b0384f4 7110
477206a0 7111 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 7112 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 7113 goto err_stop_0;
1da177e4
LT		 7114 }
7115
7116 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 7117 goto err_stop_0;
7118
b423e9ae 7119 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7120 opts[0] = DescOwn;
7121
e974604b 7122 if (!tp->tso_csum(tp, skb, opts)) {
7123 r8169_csum_workaround(tp, skb);
7124 return NETDEV_TX_OK;
7125 }
b423e9ae 7126
3eafe507 7127 len = skb_headlen(skb);
48addcc9 7128 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 7129 if (unlikely(dma_mapping_error(d, mapping))) {
7130 if (net_ratelimit())
7131 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 7132 goto err_dma_0;
d827d86b 7133 }
3eafe507
SG		 7134
7135 tp->tx_skb[entry].len = len;
7136 txd->addr = cpu_to_le64(mapping);
1da177e4 7137
2b7b4318 7138 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 7139 if (frags < 0)
7140 goto err_dma_1;
7141 else if (frags)
2b7b4318 7142 opts[0] |= FirstFrag;
3eafe507 7143 else {
2b7b4318 7144 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 7145 tp->tx_skb[entry].skb = skb;
7146 }
7147
2b7b4318
FR		 7148 txd->opts2 = cpu_to_le32(opts[1]);
7149
5047fb5d
RC		 7150 skb_tx_timestamp(skb);
7151
a0750138
AD		 7152 /* Force memory writes to complete before releasing descriptor */
7153 dma_wmb();
1da177e4 7154
cecb5fd7 7155 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 7156 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 7157 txd->opts1 = cpu_to_le32(status);
7158
a0750138 7159 /* Force all memory writes to complete before notifying device */
4c020a96 7160 wmb();
1da177e4 7161
a0750138
AD		 7162 tp->cur_tx += frags + 1;
7163
87cda7cb 7164 RTL_W8(TxPoll, NPQ);
1da177e4 7165
87cda7cb 7166 mmiowb();
da78dbff 7167
87cda7cb 7168 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 7169 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7170 * not miss a ring update when it notices a stopped queue.
7171 */
7172 smp_wmb();
1da177e4 7173 netif_stop_queue(dev);
ae1f23fb
FR		 7174 /* Sync with rtl_tx:
7175 * - publish queue status and cur_tx ring index (write barrier)
7176 * - refresh dirty_tx ring index (read barrier).
7177 * May the current thread have a pessimistic view of the ring
7178 * status and forget to wake up queue, a racing rtl_tx thread
7179 * can't.
7180 */
1e874e04 7181 smp_mb();
477206a0 7182 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 7183 netif_wake_queue(dev);
7184 }
7185
61357325 7186 return NETDEV_TX_OK;
1da177e4 7187
3eafe507 7188err_dma_1:
48addcc9 7189 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 7190err_dma_0:
989c9ba1 7191 dev_kfree_skb_any(skb);
3eafe507
SG		 7192 dev->stats.tx_dropped++;
7193 return NETDEV_TX_OK;
7194
7195err_stop_0:
1da177e4 7196 netif_stop_queue(dev);
cebf8cc7 7197 dev->stats.tx_dropped++;
61357325 7198 return NETDEV_TX_BUSY;
1da177e4
LT		 7199}
7200
7201static void rtl8169_pcierr_interrupt(struct net_device *dev)
7202{
7203 struct rtl8169_private *tp = netdev_priv(dev);
7204 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 7205 u16 pci_status, pci_cmd;
7206
7207 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7208 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7209
bf82c189
JP		 7210 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7211 pci_cmd, pci_status);
1da177e4
LT		 7212
7213 /*
7214 * The recovery sequence below admits a very elaborated explanation:
7215 * - it seems to work;
d03902b8
FR		 7216 * - I did not see what else could be done;
7217 * - it makes iop3xx happy.
1da177e4
LT		 7218 *
7219 * Feel free to adjust to your needs.
7220 */
a27993f3 7221 if (pdev->broken_parity_status)
d03902b8
FR		 7222 pci_cmd &= ~PCI_COMMAND_PARITY;
7223 else
7224 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7225
7226 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 7227
7228 pci_write_config_word(pdev, PCI_STATUS,
7229 pci_status & (PCI_STATUS_DETECTED_PARITY |
7230 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7231 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7232
7233 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 7234 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 7235 void __iomem *ioaddr = tp->mmio_addr;
7236
bf82c189 7237 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 7238 tp->cp_cmd &= ~PCIDAC;
7239 RTL_W16(CPlusCmd, tp->cp_cmd);
7240 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 7241 }
7242
e6de30d6 7243 rtl8169_hw_reset(tp);
d03902b8 7244
98ddf986 7245 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 7246}
7247
da78dbff 7248static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 7249{
7250 unsigned int dirty_tx, tx_left;
7251
1da177e4
LT		 7252 dirty_tx = tp->dirty_tx;
7253 smp_rmb();
7254 tx_left = tp->cur_tx - dirty_tx;
7255
7256 while (tx_left > 0) {
7257 unsigned int entry = dirty_tx % NUM_TX_DESC;
7258 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 7259 u32 status;
7260
1da177e4
LT		 7261 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7262 if (status & DescOwn)
7263 break;
7264
a0750138
AD		 7265 /* This barrier is needed to keep us from reading
7266 * any other fields out of the Tx descriptor until
7267 * we know the status of DescOwn
7268 */
7269 dma_rmb();
7270
48addcc9
SG		 7271 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7272 tp->TxDescArray + entry);
1da177e4 7273 if (status & LastFrag) {
87cda7cb
DM		 7274 u64_stats_update_begin(&tp->tx_stats.syncp);
7275 tp->tx_stats.packets++;
7276 tp->tx_stats.bytes += tx_skb->skb->len;
7277 u64_stats_update_end(&tp->tx_stats.syncp);
989c9ba1 7278 dev_kfree_skb_any(tx_skb->skb);
1da177e4
LT		 7279 tx_skb->skb = NULL;
7280 }
7281 dirty_tx++;
7282 tx_left--;
7283 }
7284
7285 if (tp->dirty_tx != dirty_tx) {
7286 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 7287 /* Sync with rtl8169_start_xmit:
7288 * - publish dirty_tx ring index (write barrier)
7289 * - refresh cur_tx ring index and queue status (read barrier)
7290 * May the current thread miss the stopped queue condition,
7291 * a racing xmit thread can only have a right view of the
7292 * ring status.
7293 */
1e874e04 7294 smp_mb();
1da177e4 7295 if (netif_queue_stopped(dev) &&
477206a0 7296 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 7297 netif_wake_queue(dev);
7298 }
d78ae2dc
FR		 7299 /*
7300 * 8168 hack: TxPoll requests are lost when the Tx packets are
7301 * too close. Let's kick an extra TxPoll request when a burst
7302 * of start_xmit activity is detected (if it is not detected,
7303 * it is slow enough). -- FR
7304 */
da78dbff
FR		 7305 if (tp->cur_tx != dirty_tx) {
7306 void __iomem *ioaddr = tp->mmio_addr;
7307
d78ae2dc 7308 RTL_W8(TxPoll, NPQ);
da78dbff 7309 }
1da177e4
LT		 7310 }
7311}
7312
126fa4b9
FR		 7313static inline int rtl8169_fragmented_frame(u32 status)
7314{
7315 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7316}
7317
adea1ac7 7318static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 7319{
1da177e4
LT		 7320 u32 status = opts1 & RxProtoMask;
7321
7322 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 7323 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 7324 skb->ip_summed = CHECKSUM_UNNECESSARY;
7325 else
bc8acf2c 7326 skb_checksum_none_assert(skb);
1da177e4
LT		 7327}
7328
6f0333b8
ED		 7329static struct sk_buff *rtl8169_try_rx_copy(void *data,
7330 struct rtl8169_private *tp,
7331 int pkt_size,
7332 dma_addr_t addr)
1da177e4 7333{
b449655f 7334 struct sk_buff *skb;
48addcc9 7335 struct device *d = &tp->pci_dev->dev;
b449655f 7336
6f0333b8 7337 data = rtl8169_align(data);
48addcc9 7338 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 7339 prefetch(data);
e2338f86 7340 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8
ED		 7341 if (skb)
7342 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 7343 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7344
6f0333b8 7345 return skb;
1da177e4
LT		 7346}
7347
da78dbff 7348static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 7349{
7350 unsigned int cur_rx, rx_left;
6f0333b8 7351 unsigned int count;
1da177e4 7352
1da177e4 7353 cur_rx = tp->cur_rx;
1da177e4 7354
9fba0812 7355 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 7356 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 7357 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 7358 u32 status;
7359
e03f33af 7360 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 7361 if (status & DescOwn)
7362 break;
a0750138
AD		 7363
7364 /* This barrier is needed to keep us from reading
7365 * any other fields out of the Rx descriptor until
7366 * we know the status of DescOwn
7367 */
7368 dma_rmb();
7369
4dcb7d33 7370 if (unlikely(status & RxRES)) {
bf82c189
JP		 7371 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7372 status);
cebf8cc7 7373 dev->stats.rx_errors++;
1da177e4 7374 if (status & (RxRWT | RxRUNT))
cebf8cc7 7375 dev->stats.rx_length_errors++;
1da177e4 7376 if (status & RxCRC)
cebf8cc7 7377 dev->stats.rx_crc_errors++;
9dccf611 7378 if (status & RxFOVF) {
da78dbff 7379 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 7380 dev->stats.rx_fifo_errors++;
9dccf611 7381 }
6bbe021d
BG		 7382 if ((status & (RxRUNT | RxCRC)) &&
7383 !(status & (RxRWT | RxFOVF)) &&
7384 (dev->features & NETIF_F_RXALL))
7385 goto process_pkt;
1da177e4 7386 } else {
6f0333b8 7387 struct sk_buff *skb;
6bbe021d
BG		 7388 dma_addr_t addr;
7389 int pkt_size;
7390
7391process_pkt:
7392 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 7393 if (likely(!(dev->features & NETIF_F_RXFCS)))
7394 pkt_size = (status & 0x00003fff) - 4;
7395 else
7396 pkt_size = status & 0x00003fff;
1da177e4 7397
126fa4b9
FR		 7398 /*
7399 * The driver does not support incoming fragmented
7400 * frames. They are seen as a symptom of over-mtu
7401 * sized frames.
7402 */
7403 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 7404 dev->stats.rx_dropped++;
7405 dev->stats.rx_length_errors++;
ce11ff5e 7406 goto release_descriptor;
126fa4b9
FR		 7407 }
7408
6f0333b8
ED		 7409 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7410 tp, pkt_size, addr);
6f0333b8
ED		 7411 if (!skb) {
7412 dev->stats.rx_dropped++;
ce11ff5e 7413 goto release_descriptor;
1da177e4
LT		 7414 }
7415
adea1ac7 7416 rtl8169_rx_csum(skb, status);
1da177e4
LT		 7417 skb_put(skb, pkt_size);
7418 skb->protocol = eth_type_trans(skb, dev);
7419
7a8fc77b
FR		 7420 rtl8169_rx_vlan_tag(desc, skb);
7421
39174291 7422 if (skb->pkt_type == PACKET_MULTICAST)
7423 dev->stats.multicast++;
7424
56de414c 7425 napi_gro_receive(&tp->napi, skb);
1da177e4 7426
8027aa24
JW		 7427 u64_stats_update_begin(&tp->rx_stats.syncp);
7428 tp->rx_stats.packets++;
7429 tp->rx_stats.bytes += pkt_size;
7430 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 7431 }
ce11ff5e 7432release_descriptor:
7433 desc->opts2 = 0;
ce11ff5e 7434 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 7435 }
7436
7437 count = cur_rx - tp->cur_rx;
7438 tp->cur_rx = cur_rx;
7439
1da177e4
LT		 7440 return count;
7441}
7442
07d3f51f 7443static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 7444{
07d3f51f 7445 struct net_device *dev = dev_instance;
1da177e4 7446 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7447 int handled = 0;
9085cdfa 7448 u16 status;
1da177e4 7449
9085cdfa 7450 status = rtl_get_events(tp);
da78dbff
FR		 7451 if (status && status != 0xffff) {
7452 status &= RTL_EVENT_NAPI | tp->event_slow;
7453 if (status) {
7454 handled = 1;
1da177e4 7455
da78dbff
FR		 7456 rtl_irq_disable(tp);
7457 napi_schedule(&tp->napi);
f11a377b 7458 }
da78dbff
FR		 7459 }
7460 return IRQ_RETVAL(handled);
7461}
1da177e4 7462
da78dbff
FR		 7463/*
7464 * Workqueue context.
7465 */
7466static void rtl_slow_event_work(struct rtl8169_private *tp)
7467{
7468 struct net_device *dev = tp->dev;
7469 u16 status;
7470
7471 status = rtl_get_events(tp) & tp->event_slow;
7472 rtl_ack_events(tp, status);
1da177e4 7473
da78dbff
FR		 7474 if (unlikely(status & RxFIFOOver)) {
7475 switch (tp->mac_version) {
7476 /* Work around for rx fifo overflow */
7477 case RTL_GIGA_MAC_VER_11:
7478 netif_stop_queue(dev);
934714d0
FR		 7479 /* XXX - Hack alert. See rtl_task(). */
7480 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 7481 default:
f11a377b
DD		 7482 break;
7483 }
da78dbff 7484 }
1da177e4 7485
da78dbff
FR		 7486 if (unlikely(status & SYSErr))
7487 rtl8169_pcierr_interrupt(dev);
0e485150 7488
da78dbff
FR		 7489 if (status & LinkChg)
7490 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 7491
7dbb4918 7492 rtl_irq_enable_all(tp);
1da177e4
LT		 7493}
7494
4422bcd4
FR		 7495static void rtl_task(struct work_struct *work)
7496{
da78dbff
FR		 7497 static const struct {
7498 int bitnr;
7499 void (*action)(struct rtl8169_private *);
7500 } rtl_work[] = {
934714d0 7501 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 7502 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7503 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7504 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7505 };
4422bcd4
FR		 7506 struct rtl8169_private *tp =
7507 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 7508 struct net_device *dev = tp->dev;
7509 int i;
7510
7511 rtl_lock_work(tp);
7512
6c4a70c5
FR		 7513 if (!netif_running(dev) ||
7514 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 7515 goto out_unlock;
7516
7517 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7518 bool pending;
7519
da78dbff 7520 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 7521 if (pending)
7522 rtl_work[i].action(tp);
7523 }
4422bcd4 7524
da78dbff
FR		 7525out_unlock:
7526 rtl_unlock_work(tp);
4422bcd4
FR		 7527}
7528
bea3348e 7529static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 7530{
bea3348e
SH		 7531 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7532 struct net_device *dev = tp->dev;
da78dbff
FR		 7533 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7534 int work_done= 0;
7535 u16 status;
7536
7537 status = rtl_get_events(tp);
7538 rtl_ack_events(tp, status & ~tp->event_slow);
7539
7540 if (status & RTL_EVENT_NAPI_RX)
7541 work_done = rtl_rx(dev, tp, (u32) budget);
7542
7543 if (status & RTL_EVENT_NAPI_TX)
7544 rtl_tx(dev, tp);
1da177e4 7545
da78dbff
FR		 7546 if (status & tp->event_slow) {
7547 enable_mask &= ~tp->event_slow;
7548
7549 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7550 }
1da177e4 7551
bea3348e 7552 if (work_done < budget) {
288379f0 7553 napi_complete(napi);
f11a377b 7554
da78dbff
FR		 7555 rtl_irq_enable(tp, enable_mask);
7556 mmiowb();
1da177e4
LT		 7557 }
7558
bea3348e 7559 return work_done;
1da177e4 7560}
1da177e4 7561
523a6094
FR		 7562static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7563{
7564 struct rtl8169_private *tp = netdev_priv(dev);
7565
7566 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7567 return;
7568
7569 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7570 RTL_W32(RxMissed, 0);
7571}
7572
1da177e4
LT		 7573static void rtl8169_down(struct net_device *dev)
7574{
7575 struct rtl8169_private *tp = netdev_priv(dev);
7576 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 7577
4876cc1e 7578 del_timer_sync(&tp->timer);
1da177e4 7579
93dd79e8 7580 napi_disable(&tp->napi);
da78dbff 7581 netif_stop_queue(dev);
1da177e4 7582
92fc43b4 7583 rtl8169_hw_reset(tp);
323bb685
SG		 7584 /*
7585 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7586 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7587 * and napi is disabled (rtl8169_poll).
323bb685 7588 */
523a6094 7589 rtl8169_rx_missed(dev, ioaddr);
1da177e4 7590
1da177e4 7591 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7592 synchronize_sched();
1da177e4 7593
1da177e4
LT		 7594 rtl8169_tx_clear(tp);
7595
7596 rtl8169_rx_clear(tp);
065c27c1 7597
7598 rtl_pll_power_down(tp);
1da177e4
LT		 7599}
7600
7601static int rtl8169_close(struct net_device *dev)
7602{
7603 struct rtl8169_private *tp = netdev_priv(dev);
7604 struct pci_dev *pdev = tp->pci_dev;
7605
e1759441
RW		 7606 pm_runtime_get_sync(&pdev->dev);
7607
cecb5fd7 7608 /* Update counters before going down */
355423d0
IV		 7609 rtl8169_update_counters(dev);
7610
da78dbff 7611 rtl_lock_work(tp);
6c4a70c5 7612 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7613
1da177e4 7614 rtl8169_down(dev);
da78dbff 7615 rtl_unlock_work(tp);
1da177e4 7616
4ea72445
L		 7617 cancel_work_sync(&tp->wk.work);
7618
92a7c4e7 7619 free_irq(pdev->irq, dev);
1da177e4 7620
82553bb6
SG		 7621 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7622 tp->RxPhyAddr);
7623 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7624 tp->TxPhyAddr);
1da177e4
LT		 7625 tp->TxDescArray = NULL;
7626 tp->RxDescArray = NULL;
7627
e1759441
RW		 7628 pm_runtime_put_sync(&pdev->dev);
7629
1da177e4
LT		 7630 return 0;
7631}
7632
dc1c00ce
FR		 7633#ifdef CONFIG_NET_POLL_CONTROLLER
7634static void rtl8169_netpoll(struct net_device *dev)
7635{
7636 struct rtl8169_private *tp = netdev_priv(dev);
7637
7638 rtl8169_interrupt(tp->pci_dev->irq, dev);
7639}
7640#endif
7641
df43ac78
FR		 7642static int rtl_open(struct net_device *dev)
7643{
7644 struct rtl8169_private *tp = netdev_priv(dev);
7645 void __iomem *ioaddr = tp->mmio_addr;
7646 struct pci_dev *pdev = tp->pci_dev;
7647 int retval = -ENOMEM;
7648
7649 pm_runtime_get_sync(&pdev->dev);
7650
7651 /*
e75d6606 7652 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7653 * dma_alloc_coherent provides more.
7654 */
7655 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7656 &tp->TxPhyAddr, GFP_KERNEL);
7657 if (!tp->TxDescArray)
7658 goto err_pm_runtime_put;
7659
7660 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7661 &tp->RxPhyAddr, GFP_KERNEL);
7662 if (!tp->RxDescArray)
7663 goto err_free_tx_0;
7664
7665 retval = rtl8169_init_ring(dev);
7666 if (retval < 0)
7667 goto err_free_rx_1;
7668
7669 INIT_WORK(&tp->wk.work, rtl_task);
7670
7671 smp_mb();
7672
7673 rtl_request_firmware(tp);
7674
92a7c4e7 7675 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 7676 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7677 dev->name, dev);
7678 if (retval < 0)
7679 goto err_release_fw_2;
7680
7681 rtl_lock_work(tp);
7682
7683 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7684
7685 napi_enable(&tp->napi);
7686
7687 rtl8169_init_phy(dev, tp);
7688
7689 __rtl8169_set_features(dev, dev->features);
7690
7691 rtl_pll_power_up(tp);
7692
7693 rtl_hw_start(dev);
7694
6e85d5ad
CV		 7695 if (!rtl8169_init_counter_offsets(dev))
7696 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7697
df43ac78
FR		 7698 netif_start_queue(dev);
7699
7700 rtl_unlock_work(tp);
7701
7702 tp->saved_wolopts = 0;
7703 pm_runtime_put_noidle(&pdev->dev);
7704
7705 rtl8169_check_link_status(dev, tp, ioaddr);
7706out:
7707 return retval;
7708
7709err_release_fw_2:
7710 rtl_release_firmware(tp);
7711 rtl8169_rx_clear(tp);
7712err_free_rx_1:
7713 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7714 tp->RxPhyAddr);
7715 tp->RxDescArray = NULL;
7716err_free_tx_0:
7717 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7718 tp->TxPhyAddr);
7719 tp->TxDescArray = NULL;
7720err_pm_runtime_put:
7721 pm_runtime_put_noidle(&pdev->dev);
7722 goto out;
7723}
7724
8027aa24
JW		 7725static struct rtnl_link_stats64 *
7726rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7727{
7728 struct rtl8169_private *tp = netdev_priv(dev);
7729 void __iomem *ioaddr = tp->mmio_addr;
f09cf4b7 7730 struct pci_dev *pdev = tp->pci_dev;
42020320 7731 struct rtl8169_counters *counters = tp->counters;
8027aa24 7732 unsigned int start;
1da177e4 7733
f09cf4b7
CHL		 7734 pm_runtime_get_noresume(&pdev->dev);
7735
7736 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
523a6094 7737 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 7738
8027aa24 7739 do {
57a7744e 7740 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7741 stats->rx_packets = tp->rx_stats.packets;
7742 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7743 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 7744
8027aa24 7745 do {
57a7744e 7746 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7747 stats->tx_packets = tp->tx_stats.packets;
7748 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7749 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7750
7751 stats->rx_dropped = dev->stats.rx_dropped;
7752 stats->tx_dropped = dev->stats.tx_dropped;
7753 stats->rx_length_errors = dev->stats.rx_length_errors;
7754 stats->rx_errors = dev->stats.rx_errors;
7755 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7756 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7757 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 7758 stats->multicast = dev->stats.multicast;
8027aa24 7759
6e85d5ad
CV		 7760 /*
7761 * Fetch additonal counter values missing in stats collected by driver
7762 * from tally counters.
7763 */
f09cf4b7
CHL		 7764 if (pm_runtime_active(&pdev->dev))
7765 rtl8169_update_counters(dev);
6e85d5ad
CV		 7766
7767 /*
7768 * Subtract values fetched during initalization.
7769 * See rtl8169_init_counter_offsets for a description why we do that.
7770 */
42020320 7771 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 7772 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 7773 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 7774 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 7775 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 7776 le16_to_cpu(tp->tc_offset.tx_aborted);
7777
f09cf4b7
CHL		 7778 pm_runtime_put_noidle(&pdev->dev);
7779
8027aa24 7780 return stats;
1da177e4
LT		 7781}
7782
861ab440 7783static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7784{
065c27c1 7785 struct rtl8169_private *tp = netdev_priv(dev);
7786
5d06a99f 7787 if (!netif_running(dev))
861ab440 7788 return;
5d06a99f
FR		 7789
7790 netif_device_detach(dev);
7791 netif_stop_queue(dev);
da78dbff
FR		 7792
7793 rtl_lock_work(tp);
7794 napi_disable(&tp->napi);
6c4a70c5 7795 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7796 rtl_unlock_work(tp);
7797
7798 rtl_pll_power_down(tp);
861ab440
RW		 7799}
7800
7801#ifdef CONFIG_PM
7802
7803static int rtl8169_suspend(struct device *device)
7804{
7805 struct pci_dev *pdev = to_pci_dev(device);
7806 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7807
861ab440 7808 rtl8169_net_suspend(dev);
1371fa6d 7809
5d06a99f
FR		 7810 return 0;
7811}
7812
e1759441
RW		 7813static void __rtl8169_resume(struct net_device *dev)
7814{
065c27c1 7815 struct rtl8169_private *tp = netdev_priv(dev);
7816
e1759441 7817 netif_device_attach(dev);
065c27c1 7818
7819 rtl_pll_power_up(tp);
7820
cff4c162
AS		 7821 rtl_lock_work(tp);
7822 napi_enable(&tp->napi);
6c4a70c5 7823 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7824 rtl_unlock_work(tp);
da78dbff 7825
98ddf986 7826 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7827}
7828
861ab440 7829static int rtl8169_resume(struct device *device)
5d06a99f 7830{
861ab440 7831 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 7832 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 7833 struct rtl8169_private *tp = netdev_priv(dev);
7834
7835 rtl8169_init_phy(dev, tp);
5d06a99f 7836
e1759441
RW		 7837 if (netif_running(dev))
7838 __rtl8169_resume(dev);
5d06a99f 7839
e1759441
RW		 7840 return 0;
7841}
7842
7843static int rtl8169_runtime_suspend(struct device *device)
7844{
7845 struct pci_dev *pdev = to_pci_dev(device);
7846 struct net_device *dev = pci_get_drvdata(pdev);
7847 struct rtl8169_private *tp = netdev_priv(dev);
7848
7849 if (!tp->TxDescArray)
7850 return 0;
7851
da78dbff 7852 rtl_lock_work(tp);
e1759441
RW		 7853 tp->saved_wolopts = __rtl8169_get_wol(tp);
7854 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7855 rtl_unlock_work(tp);
e1759441
RW		 7856
7857 rtl8169_net_suspend(dev);
7858
f09cf4b7
CHL		 7859 /* Update counters before going runtime suspend */
7860 rtl8169_rx_missed(dev, tp->mmio_addr);
7861 rtl8169_update_counters(dev);
7862
e1759441
RW		 7863 return 0;
7864}
7865
7866static int rtl8169_runtime_resume(struct device *device)
7867{
7868 struct pci_dev *pdev = to_pci_dev(device);
7869 struct net_device *dev = pci_get_drvdata(pdev);
7870 struct rtl8169_private *tp = netdev_priv(dev);
7871
7872 if (!tp->TxDescArray)
7873 return 0;
7874
da78dbff 7875 rtl_lock_work(tp);
e1759441
RW		 7876 __rtl8169_set_wol(tp, tp->saved_wolopts);
7877 tp->saved_wolopts = 0;
da78dbff 7878 rtl_unlock_work(tp);
e1759441 7879
fccec10b
SG		 7880 rtl8169_init_phy(dev, tp);
7881
e1759441 7882 __rtl8169_resume(dev);
5d06a99f 7883
5d06a99f
FR		 7884 return 0;
7885}
7886
e1759441
RW		 7887static int rtl8169_runtime_idle(struct device *device)
7888{
7889 struct pci_dev *pdev = to_pci_dev(device);
7890 struct net_device *dev = pci_get_drvdata(pdev);
7891 struct rtl8169_private *tp = netdev_priv(dev);
7892
e4fbce74 7893 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 7894}
7895
47145210 7896static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7897 .suspend = rtl8169_suspend,
7898 .resume = rtl8169_resume,
7899 .freeze = rtl8169_suspend,
7900 .thaw = rtl8169_resume,
7901 .poweroff = rtl8169_suspend,
7902 .restore = rtl8169_resume,
7903 .runtime_suspend = rtl8169_runtime_suspend,
7904 .runtime_resume = rtl8169_runtime_resume,
7905 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7906};
7907
7908#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7909
7910#else /* !CONFIG_PM */
7911
7912#define RTL8169_PM_OPS NULL
7913
7914#endif /* !CONFIG_PM */
7915
649b3b8c 7916static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7917{
7918 void __iomem *ioaddr = tp->mmio_addr;
7919
7920 /* WoL fails with 8168b when the receiver is disabled. */
7921 switch (tp->mac_version) {
7922 case RTL_GIGA_MAC_VER_11:
7923 case RTL_GIGA_MAC_VER_12:
7924 case RTL_GIGA_MAC_VER_17:
7925 pci_clear_master(tp->pci_dev);
7926
7927 RTL_W8(ChipCmd, CmdRxEnb);
7928 /* PCI commit */
7929 RTL_R8(ChipCmd);
7930 break;
7931 default:
7932 break;
7933 }
7934}
7935
1765f95d
FR		 7936static void rtl_shutdown(struct pci_dev *pdev)
7937{
861ab440 7938 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7939 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 7940 struct device *d = &pdev->dev;
7941
7942 pm_runtime_get_sync(d);
861ab440
RW		 7943
7944 rtl8169_net_suspend(dev);
1765f95d 7945
cecb5fd7 7946 /* Restore original MAC address */
cc098dc7
IV		 7947 rtl_rar_set(tp, dev->perm_addr);
7948
92fc43b4 7949 rtl8169_hw_reset(tp);
4bb3f522 7950
861ab440 7951 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 7952 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7953 rtl_wol_suspend_quirk(tp);
7954 rtl_wol_shutdown_quirk(tp);
ca52efd5 7955 }
7956
861ab440
RW		 7957 pci_wake_from_d3(pdev, true);
7958 pci_set_power_state(pdev, PCI_D3hot);
7959 }
2a15cd2f 7960
7961 pm_runtime_put_noidle(d);
861ab440 7962}
5d06a99f 7963
baf63293 7964static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7965{
7966 struct net_device *dev = pci_get_drvdata(pdev);
7967 struct rtl8169_private *tp = netdev_priv(dev);
7968
ee7a1beb
CHL		 7969 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7970 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 7971 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7972 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7973 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7974 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 7975 r8168_check_dash(tp)) {
e27566ed
FR		 7976 rtl8168_driver_stop(tp);
7977 }
7978
ad1be8d3
DN		 7979 netif_napi_del(&tp->napi);
7980
e27566ed
FR		 7981 unregister_netdev(dev);
7982
42020320
CV		 7983 dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
7984 tp->counters, tp->counters_phys_addr);
7985
e27566ed
FR		 7986 rtl_release_firmware(tp);
7987
7988 if (pci_dev_run_wake(pdev))
7989 pm_runtime_get_noresume(&pdev->dev);
7990
7991 /* restore original MAC address */
7992 rtl_rar_set(tp, dev->perm_addr);
7993
7994 rtl_disable_msi(pdev, tp);
7995 rtl8169_release_board(pdev, dev, tp->mmio_addr);
e27566ed
FR		 7996}
7997
fa9c385e 7998static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7999 .ndo_open = rtl_open,
fa9c385e
FR		 8000 .ndo_stop = rtl8169_close,
8001 .ndo_get_stats64 = rtl8169_get_stats64,
8002 .ndo_start_xmit = rtl8169_start_xmit,
8003 .ndo_tx_timeout = rtl8169_tx_timeout,
8004 .ndo_validate_addr = eth_validate_addr,
8005 .ndo_change_mtu = rtl8169_change_mtu,
8006 .ndo_fix_features = rtl8169_fix_features,
8007 .ndo_set_features = rtl8169_set_features,
8008 .ndo_set_mac_address = rtl_set_mac_address,
8009 .ndo_do_ioctl = rtl8169_ioctl,
8010 .ndo_set_rx_mode = rtl_set_rx_mode,
8011#ifdef CONFIG_NET_POLL_CONTROLLER
8012 .ndo_poll_controller = rtl8169_netpoll,
8013#endif
8014
8015};
8016
31fa8b18
FR		 8017static const struct rtl_cfg_info {
8018 void (*hw_start)(struct net_device *);
8019 unsigned int region;
8020 unsigned int align;
8021 u16 event_slow;
8022 unsigned features;
8023 u8 default_ver;
8024} rtl_cfg_infos [] = {
8025 [RTL_CFG_0] = {
8026 .hw_start = rtl_hw_start_8169,
8027 .region = 1,
8028 .align = 0,
8029 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8030 .features = RTL_FEATURE_GMII,
8031 .default_ver = RTL_GIGA_MAC_VER_01,
8032 },
8033 [RTL_CFG_1] = {
8034 .hw_start = rtl_hw_start_8168,
8035 .region = 2,
8036 .align = 8,
8037 .event_slow = SYSErr | LinkChg | RxOverflow,
8038 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8039 .default_ver = RTL_GIGA_MAC_VER_11,
8040 },
8041 [RTL_CFG_2] = {
8042 .hw_start = rtl_hw_start_8101,
8043 .region = 2,
8044 .align = 8,
8045 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8046 PCSTimeout,
8047 .features = RTL_FEATURE_MSI,
8048 .default_ver = RTL_GIGA_MAC_VER_13,
8049 }
8050};
8051
8052/* Cfg9346_Unlock assumed. */
8053static unsigned rtl_try_msi(struct rtl8169_private *tp,
8054 const struct rtl_cfg_info *cfg)
8055{
8056 void __iomem *ioaddr = tp->mmio_addr;
8057 unsigned msi = 0;
8058 u8 cfg2;
8059
8060 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8061 if (cfg->features & RTL_FEATURE_MSI) {
8062 if (pci_enable_msi(tp->pci_dev)) {
8063 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8064 } else {
8065 cfg2 |= MSIEnable;
8066 msi = RTL_FEATURE_MSI;
8067 }
8068 }
8069 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8070 RTL_W8(Config2, cfg2);
8071 return msi;
8072}
8073
c558386b
HW		 8074DECLARE_RTL_COND(rtl_link_list_ready_cond)
8075{
8076 void __iomem *ioaddr = tp->mmio_addr;
8077
8078 return RTL_R8(MCU) & LINK_LIST_RDY;
8079}
8080
8081DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8082{
8083 void __iomem *ioaddr = tp->mmio_addr;
8084
8085 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8086}
8087
baf63293 8088static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 8089{
8090 void __iomem *ioaddr = tp->mmio_addr;
8091 u32 data;
8092
8093 tp->ocp_base = OCP_STD_PHY_BASE;
8094
8095 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8096
8097 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8098 return;
8099
8100 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8101 return;
8102
8103 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8104 msleep(1);
8105 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8106
5f8bcce9 8107 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8108 data &= ~(1 << 14);
8109 r8168_mac_ocp_write(tp, 0xe8de, data);
8110
8111 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8112 return;
8113
5f8bcce9 8114 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8115 data |= (1 << 15);
8116 r8168_mac_ocp_write(tp, 0xe8de, data);
8117
8118 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8119 return;
8120}
8121
003609da
CHL		 8122static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8123{
8124 rtl8168ep_stop_cmac(tp);
8125 rtl_hw_init_8168g(tp);
8126}
8127
baf63293 8128static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 8129{
8130 switch (tp->mac_version) {
8131 case RTL_GIGA_MAC_VER_40:
8132 case RTL_GIGA_MAC_VER_41:
57538c4a 8133 case RTL_GIGA_MAC_VER_42:
58152cd4 8134 case RTL_GIGA_MAC_VER_43:
45dd95c4 8135 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8136 case RTL_GIGA_MAC_VER_45:
8137 case RTL_GIGA_MAC_VER_46:
8138 case RTL_GIGA_MAC_VER_47:
8139 case RTL_GIGA_MAC_VER_48:
003609da
CHL		 8140 rtl_hw_init_8168g(tp);
8141 break;
935e2218
CHL		 8142 case RTL_GIGA_MAC_VER_49:
8143 case RTL_GIGA_MAC_VER_50:
8144 case RTL_GIGA_MAC_VER_51:
003609da 8145 rtl_hw_init_8168ep(tp);
c558386b 8146 break;
c558386b
HW		 8147 default:
8148 break;
8149 }
8150}
8151
929a031d 8152static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 8153{
8154 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8155 const unsigned int region = cfg->region;
8156 struct rtl8169_private *tp;
8157 struct mii_if_info *mii;
8158 struct net_device *dev;
8159 void __iomem *ioaddr;
8160 int chipset, i;
8161 int rc;
8162
8163 if (netif_msg_drv(&debug)) {
8164 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8165 MODULENAME, RTL8169_VERSION);
8166 }
8167
8168 dev = alloc_etherdev(sizeof (*tp));
8169 if (!dev) {
8170 rc = -ENOMEM;
8171 goto out;
8172 }
8173
8174 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 8175 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 8176 tp = netdev_priv(dev);
8177 tp->dev = dev;
8178 tp->pci_dev = pdev;
8179 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8180
8181 mii = &tp->mii;
8182 mii->dev = dev;
8183 mii->mdio_read = rtl_mdio_read;
8184 mii->mdio_write = rtl_mdio_write;
8185 mii->phy_id_mask = 0x1f;
8186 mii->reg_num_mask = 0x1f;
8187 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8188
8189 /* disable ASPM completely as that cause random device stop working
8190 * problems as well as full system hangs for some PCIe devices users */
8191 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8192 PCIE_LINK_STATE_CLKPM);
8193
8194 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8195 rc = pci_enable_device(pdev);
8196 if (rc < 0) {
8197 netif_err(tp, probe, dev, "enable failure\n");
8198 goto err_out_free_dev_1;
8199 }
8200
8201 if (pci_set_mwi(pdev) < 0)
8202 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8203
8204 /* make sure PCI base addr 1 is MMIO */
8205 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8206 netif_err(tp, probe, dev,
8207 "region #%d not an MMIO resource, aborting\n",
8208 region);
8209 rc = -ENODEV;
8210 goto err_out_mwi_2;
8211 }
8212
8213 /* check for weird/broken PCI region reporting */
8214 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8215 netif_err(tp, probe, dev,
8216 "Invalid PCI region size(s), aborting\n");
8217 rc = -ENODEV;
8218 goto err_out_mwi_2;
8219 }
8220
8221 rc = pci_request_regions(pdev, MODULENAME);
8222 if (rc < 0) {
8223 netif_err(tp, probe, dev, "could not request regions\n");
8224 goto err_out_mwi_2;
8225 }
8226
3b6cf25d
FR		 8227 /* ioremap MMIO region */
8228 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8229 if (!ioaddr) {
8230 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8231 rc = -EIO;
8232 goto err_out_free_res_3;
8233 }
8234 tp->mmio_addr = ioaddr;
8235
8236 if (!pci_is_pcie(pdev))
8237 netif_info(tp, probe, dev, "not PCI Express\n");
8238
8239 /* Identify chip attached to board */
8240 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8241
27896c83
AB		 8242 tp->cp_cmd = 0;
8243
8244 if ((sizeof(dma_addr_t) > 4) &&
8245 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8246 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8247 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
8248
8249 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8250 if (!pci_is_pcie(pdev))
8251 tp->cp_cmd |= PCIDAC;
8252 dev->features |= NETIF_F_HIGHDMA;
8253 } else {
8254 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8255 if (rc < 0) {
8256 netif_err(tp, probe, dev, "DMA configuration failed\n");
8257 goto err_out_unmap_4;
8258 }
8259 }
8260
3b6cf25d
FR		 8261 rtl_init_rxcfg(tp);
8262
8263 rtl_irq_disable(tp);
8264
c558386b
HW		 8265 rtl_hw_initialize(tp);
8266
3b6cf25d
FR		 8267 rtl_hw_reset(tp);
8268
8269 rtl_ack_events(tp, 0xffff);
8270
8271 pci_set_master(pdev);
8272
3b6cf25d
FR		 8273 rtl_init_mdio_ops(tp);
8274 rtl_init_pll_power_ops(tp);
8275 rtl_init_jumbo_ops(tp);
beb1fe18 8276 rtl_init_csi_ops(tp);
3b6cf25d
FR		 8277
8278 rtl8169_print_mac_version(tp);
8279
8280 chipset = tp->mac_version;
8281 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8282
8283 RTL_W8(Cfg9346, Cfg9346_Unlock);
8284 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8f9d5138 8285 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
6e1d0b89 8286 switch (tp->mac_version) {
ac85bcdb
CHL		 8287 case RTL_GIGA_MAC_VER_34:
8288 case RTL_GIGA_MAC_VER_35:
8289 case RTL_GIGA_MAC_VER_36:
8290 case RTL_GIGA_MAC_VER_37:
8291 case RTL_GIGA_MAC_VER_38:
8292 case RTL_GIGA_MAC_VER_40:
8293 case RTL_GIGA_MAC_VER_41:
8294 case RTL_GIGA_MAC_VER_42:
8295 case RTL_GIGA_MAC_VER_43:
8296 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8297 case RTL_GIGA_MAC_VER_45:
8298 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 8299 case RTL_GIGA_MAC_VER_47:
8300 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 8301 case RTL_GIGA_MAC_VER_49:
8302 case RTL_GIGA_MAC_VER_50:
8303 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 8304 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8305 tp->features |= RTL_FEATURE_WOL;
8306 if ((RTL_R8(Config3) & LinkUp) != 0)
8307 tp->features |= RTL_FEATURE_WOL;
8308 break;
8309 default:
8310 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8311 tp->features |= RTL_FEATURE_WOL;
8312 break;
8313 }
3b6cf25d
FR		 8314 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8315 tp->features |= RTL_FEATURE_WOL;
8316 tp->features |= rtl_try_msi(tp, cfg);
8317 RTL_W8(Cfg9346, Cfg9346_Lock);
8318
8319 if (rtl_tbi_enabled(tp)) {
8320 tp->set_speed = rtl8169_set_speed_tbi;
8321 tp->get_settings = rtl8169_gset_tbi;
8322 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8323 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8324 tp->link_ok = rtl8169_tbi_link_ok;
8325 tp->do_ioctl = rtl_tbi_ioctl;
8326 } else {
8327 tp->set_speed = rtl8169_set_speed_xmii;
8328 tp->get_settings = rtl8169_gset_xmii;
8329 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8330 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8331 tp->link_ok = rtl8169_xmii_link_ok;
8332 tp->do_ioctl = rtl_xmii_ioctl;
8333 }
8334
8335 mutex_init(&tp->wk.mutex);
340fea3d
KM		 8336 u64_stats_init(&tp->rx_stats.syncp);
8337 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 8338
8339 /* Get MAC address */
89cceb27
CHL		 8340 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8341 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8342 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8343 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8344 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8345 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8346 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8347 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8348 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8349 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
6e1d0b89
CHL		 8350 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8351 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 8352 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8353 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8354 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8355 tp->mac_version == RTL_GIGA_MAC_VER_51) {
6e1d0b89
CHL		 8356 u16 mac_addr[3];
8357
05b9687b
CHL		 8358 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8359 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89
CHL		 8360
8361 if (is_valid_ether_addr((u8 *)mac_addr))
8362 rtl_rar_set(tp, (u8 *)mac_addr);
8363 }
3b6cf25d
FR		 8364 for (i = 0; i < ETH_ALEN; i++)
8365 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 8366
7ad24ea4 8367 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 8368 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 8369
8370 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8371
8372 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8373 * properly for all devices */
8374 dev->features |= NETIF_F_RXCSUM |
f646968f 8375 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8376
8377 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 8378 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8379 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8380 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8381 NETIF_F_HIGHDMA;
8382
929a031d 8383 tp->cp_cmd |= RxChkSum | RxVlan;
8384
8385 /*
8386 * Pretend we are using VLANs; This bypasses a nasty bug where
8387 * Interrupts stop flowing on high load on 8110SCd controllers.
8388 */
3b6cf25d 8389 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 8390 /* Disallow toggling */
f646968f 8391 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 8392
5888d3fc 8393 if (tp->txd_version == RTL_TD_0)
8394 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 8395 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 8396 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 8397 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8398 } else
5888d3fc 8399 WARN_ON_ONCE(1);
8400
3b6cf25d
FR		 8401 dev->hw_features |= NETIF_F_RXALL;
8402 dev->hw_features |= NETIF_F_RXFCS;
8403
8404 tp->hw_start = cfg->hw_start;
8405 tp->event_slow = cfg->event_slow;
8406
8407 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8408 ~(RxBOVF | RxFOVF) : ~0;
8409
8410 init_timer(&tp->timer);
8411 tp->timer.data = (unsigned long) dev;
8412 tp->timer.function = rtl8169_phy_timer;
8413
8414 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8415
42020320
CV		 8416 tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8417 &tp->counters_phys_addr, GFP_KERNEL);
8418 if (!tp->counters) {
8419 rc = -ENOMEM;
27896c83 8420 goto err_out_msi_5;
42020320
CV		 8421 }
8422
3b6cf25d
FR		 8423 rc = register_netdev(dev);
8424 if (rc < 0)
27896c83 8425 goto err_out_cnt_6;
3b6cf25d
FR		 8426
8427 pci_set_drvdata(pdev, dev);
8428
92a7c4e7
FR		 8429 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8430 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8431 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 8432 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8433 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8434 "tx checksumming: %s]\n",
8435 rtl_chip_infos[chipset].jumbo_max,
8436 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8437 }
8438
ee7a1beb
CHL		 8439 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8440 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 8441 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8442 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8443 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8444 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 8445 r8168_check_dash(tp)) {
3b6cf25d
FR		 8446 rtl8168_driver_start(tp);
8447 }
8448
8449 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8450
8451 if (pci_dev_run_wake(pdev))
8452 pm_runtime_put_noidle(&pdev->dev);
8453
8454 netif_carrier_off(dev);
8455
8456out:
8457 return rc;
8458
27896c83 8459err_out_cnt_6:
42020320
CV		 8460 dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8461 tp->counters_phys_addr);
27896c83 8462err_out_msi_5:
ad1be8d3 8463 netif_napi_del(&tp->napi);
3b6cf25d 8464 rtl_disable_msi(pdev, tp);
27896c83 8465err_out_unmap_4:
3b6cf25d
FR		 8466 iounmap(ioaddr);
8467err_out_free_res_3:
8468 pci_release_regions(pdev);
8469err_out_mwi_2:
8470 pci_clear_mwi(pdev);
8471 pci_disable_device(pdev);
8472err_out_free_dev_1:
8473 free_netdev(dev);
8474 goto out;
8475}
8476
1da177e4
LT		 8477static struct pci_driver rtl8169_pci_driver = {
8478 .name = MODULENAME,
8479 .id_table = rtl8169_pci_tbl,
3b6cf25d 8480 .probe = rtl_init_one,
baf63293 8481 .remove = rtl_remove_one,
1765f95d 8482 .shutdown = rtl_shutdown,
861ab440 8483 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 8484};
8485
3eeb7da9 8486module_pci_driver(rtl8169_pci_driver);
Linux kernel - Deliverables
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