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wimax: convert printk to pr_foo()
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
9c14ceaf 87#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 107#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 108
109enum mac_version {
85bffe6c
FR		 110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
70090424 143 RTL_GIGA_MAC_VER_34,
c2218925
HW		 144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
7e18dca1 146 RTL_GIGA_MAC_VER_37,
b3d7b2f2 147 RTL_GIGA_MAC_VER_38,
5598bfe5 148 RTL_GIGA_MAC_VER_39,
c558386b
HW		 149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
57538c4a 151 RTL_GIGA_MAC_VER_42,
58152cd4 152 RTL_GIGA_MAC_VER_43,
45dd95c4 153 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
85bffe6c 158 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 159};
160
2b7b4318
FR		 161enum rtl_tx_desc_version {
162 RTL_TD_0 = 0,
163 RTL_TD_1 = 1,
164};
165
d58d46b5
FR		 166#define JUMBO_1K ETH_DATA_LEN
167#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
168#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
169#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
170#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
171
172#define _R(NAME,TD,FW,SZ,B) { \
173 .name = NAME, \
174 .txd_version = TD, \
175 .fw_name = FW, \
176 .jumbo_max = SZ, \
177 .jumbo_tx_csum = B \
178}
1da177e4 179
3c6bee1d 180static const struct {
1da177e4 181 const char *name;
2b7b4318 182 enum rtl_tx_desc_version txd_version;
953a12cc 183 const char *fw_name;
d58d46b5
FR		 184 u16 jumbo_max;
185 bool jumbo_tx_csum;
85bffe6c
FR		 186} rtl_chip_infos[] = {
187 /* PCI devices. */
188 [RTL_GIGA_MAC_VER_01] =
d58d46b5 189 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_02] =
d58d46b5 191 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_03] =
d58d46b5 193 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_04] =
d58d46b5 195 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_05] =
d58d46b5 197 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_06] =
d58d46b5 199 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 200 /* PCI-E devices. */
201 [RTL_GIGA_MAC_VER_07] =
d58d46b5 202 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 203 [RTL_GIGA_MAC_VER_08] =
d58d46b5 204 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 205 [RTL_GIGA_MAC_VER_09] =
d58d46b5 206 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 207 [RTL_GIGA_MAC_VER_10] =
d58d46b5 208 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 209 [RTL_GIGA_MAC_VER_11] =
d58d46b5 210 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 211 [RTL_GIGA_MAC_VER_12] =
d58d46b5 212 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 213 [RTL_GIGA_MAC_VER_13] =
d58d46b5 214 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 215 [RTL_GIGA_MAC_VER_14] =
d58d46b5 216 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 217 [RTL_GIGA_MAC_VER_15] =
d58d46b5 218 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 219 [RTL_GIGA_MAC_VER_16] =
d58d46b5 220 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 221 [RTL_GIGA_MAC_VER_17] =
f75761b6 222 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 223 [RTL_GIGA_MAC_VER_18] =
d58d46b5 224 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_19] =
d58d46b5 226 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 227 [RTL_GIGA_MAC_VER_20] =
d58d46b5 228 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 229 [RTL_GIGA_MAC_VER_21] =
d58d46b5 230 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 231 [RTL_GIGA_MAC_VER_22] =
d58d46b5 232 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 233 [RTL_GIGA_MAC_VER_23] =
d58d46b5 234 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 235 [RTL_GIGA_MAC_VER_24] =
d58d46b5 236 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 237 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 238 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
239 JUMBO_9K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_27] =
d58d46b5 244 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 245 [RTL_GIGA_MAC_VER_28] =
d58d46b5 246 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 247 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 248 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
249 JUMBO_1K, true),
85bffe6c 250 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
85bffe6c 253 [RTL_GIGA_MAC_VER_31] =
d58d46b5 254 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 255 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 256 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
257 JUMBO_9K, false),
85bffe6c 258 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
260 JUMBO_9K, false),
70090424 261 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 262 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
263 JUMBO_9K, false),
c2218925 264 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 265 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
266 JUMBO_9K, false),
c2218925 267 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
269 JUMBO_9K, false),
7e18dca1
HW		 270 [RTL_GIGA_MAC_VER_37] =
271 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
272 JUMBO_1K, true),
b3d7b2f2
HW		 273 [RTL_GIGA_MAC_VER_38] =
274 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
275 JUMBO_9K, false),
5598bfe5
HW		 276 [RTL_GIGA_MAC_VER_39] =
277 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
278 JUMBO_1K, true),
c558386b 279 [RTL_GIGA_MAC_VER_40] =
beb330a4 280 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 281 JUMBO_9K, false),
282 [RTL_GIGA_MAC_VER_41] =
283 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 284 [RTL_GIGA_MAC_VER_42] =
285 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
286 JUMBO_9K, false),
58152cd4 287 [RTL_GIGA_MAC_VER_43] =
288 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
289 JUMBO_1K, true),
45dd95c4 290 [RTL_GIGA_MAC_VER_44] =
291 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
292 JUMBO_9K, false),
6e1d0b89
CHL		 293 [RTL_GIGA_MAC_VER_45] =
294 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
295 JUMBO_9K, false),
296 [RTL_GIGA_MAC_VER_46] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_47] =
300 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
301 JUMBO_1K, false),
302 [RTL_GIGA_MAC_VER_48] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
304 JUMBO_1K, false),
953a12cc 305};
85bffe6c 306#undef _R
953a12cc 307
bcf0bf90
FR		 308enum cfg_version {
309 RTL_CFG_0 = 0x00,
310 RTL_CFG_1,
311 RTL_CFG_2
312};
313
9baa3c34 314static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 315 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 316 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 317 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 318 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 319 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 320 { PCI_VENDOR_ID_DLINK, 0x4300,
321 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 322 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 323 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 324 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 325 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
326 { PCI_VENDOR_ID_LINKSYS, 0x1032,
327 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 328 { 0x0001, 0x8168,
329 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 330 {0,},
331};
332
333MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
334
6f0333b8 335static int rx_buf_sz = 16383;
4300e8c7 336static int use_dac;
b57b7e5a
SH		 337static struct {
338 u32 msg_enable;
339} debug = { -1 };
1da177e4 340
07d3f51f
FR		 341enum rtl_registers {
342 MAC0 = 0, /* Ethernet hardware address. */
773d2021 343 MAC4 = 4,
07d3f51f
FR		 344 MAR0 = 8, /* Multicast filter. */
345 CounterAddrLow = 0x10,
346 CounterAddrHigh = 0x14,
347 TxDescStartAddrLow = 0x20,
348 TxDescStartAddrHigh = 0x24,
349 TxHDescStartAddrLow = 0x28,
350 TxHDescStartAddrHigh = 0x2c,
351 FLASH = 0x30,
352 ERSR = 0x36,
353 ChipCmd = 0x37,
354 TxPoll = 0x38,
355 IntrMask = 0x3c,
356 IntrStatus = 0x3e,
4f6b00e5 357
07d3f51f 358 TxConfig = 0x40,
4f6b00e5
HW		 359#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
360#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 361
4f6b00e5
HW		 362 RxConfig = 0x44,
363#define RX128_INT_EN (1 << 15) /* 8111c and later */
364#define RX_MULTI_EN (1 << 14) /* 8111c only */
365#define RXCFG_FIFO_SHIFT 13
366 /* No threshold before first PCI xfer */
367#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 368#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 369#define RXCFG_DMA_SHIFT 8
370 /* Unlimited maximum PCI burst. */
371#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 372
07d3f51f
FR		 373 RxMissed = 0x4c,
374 Cfg9346 = 0x50,
375 Config0 = 0x51,
376 Config1 = 0x52,
377 Config2 = 0x53,
d387b427
FR		 378#define PME_SIGNAL (1 << 5) /* 8168c and later */
379
07d3f51f
FR		 380 Config3 = 0x54,
381 Config4 = 0x55,
382 Config5 = 0x56,
383 MultiIntr = 0x5c,
384 PHYAR = 0x60,
07d3f51f
FR		 385 PHYstatus = 0x6c,
386 RxMaxSize = 0xda,
387 CPlusCmd = 0xe0,
388 IntrMitigate = 0xe2,
389 RxDescAddrLow = 0xe4,
390 RxDescAddrHigh = 0xe8,
f0298f81 391 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
392
393#define NoEarlyTx 0x3f /* Max value : no early transmit. */
394
395 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
396
397#define TxPacketMax (8064 >> 7)
3090bd9a 398#define EarlySize 0x27
f0298f81 399
07d3f51f
FR		 400 FuncEvent = 0xf0,
401 FuncEventMask = 0xf4,
402 FuncPresetState = 0xf8,
403 FuncForceEvent = 0xfc,
1da177e4
LT		 404};
405
f162a5d1
FR		 406enum rtl8110_registers {
407 TBICSR = 0x64,
408 TBI_ANAR = 0x68,
409 TBI_LPAR = 0x6a,
410};
411
412enum rtl8168_8101_registers {
413 CSIDR = 0x64,
414 CSIAR = 0x68,
415#define CSIAR_FLAG 0x80000000
416#define CSIAR_WRITE_CMD 0x80000000
417#define CSIAR_BYTE_ENABLE 0x0f
418#define CSIAR_BYTE_ENABLE_SHIFT 12
419#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 420#define CSIAR_FUNC_CARD 0x00000000
421#define CSIAR_FUNC_SDIO 0x00010000
422#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 423#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 424 PMCH = 0x6f,
f162a5d1
FR		 425 EPHYAR = 0x80,
426#define EPHYAR_FLAG 0x80000000
427#define EPHYAR_WRITE_CMD 0x80000000
428#define EPHYAR_REG_MASK 0x1f
429#define EPHYAR_REG_SHIFT 16
430#define EPHYAR_DATA_MASK 0xffff
5a5e4443 431 DLLPR = 0xd0,
4f6b00e5 432#define PFM_EN (1 << 6)
6e1d0b89 433#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 434 DBG_REG = 0xd1,
435#define FIX_NAK_1 (1 << 4)
436#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 437 TWSI = 0xd2,
438 MCU = 0xd3,
4f6b00e5 439#define NOW_IS_OOB (1 << 7)
c558386b
HW		 440#define TX_EMPTY (1 << 5)
441#define RX_EMPTY (1 << 4)
442#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 443#define EN_NDP (1 << 3)
444#define EN_OOB_RESET (1 << 2)
c558386b 445#define LINK_LIST_RDY (1 << 1)
daf9df6d 446 EFUSEAR = 0xdc,
447#define EFUSEAR_FLAG 0x80000000
448#define EFUSEAR_WRITE_CMD 0x80000000
449#define EFUSEAR_READ_CMD 0x00000000
450#define EFUSEAR_REG_MASK 0x03ff
451#define EFUSEAR_REG_SHIFT 8
452#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 453 MISC_1 = 0xf2,
454#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 455};
456
c0e45c1c 457enum rtl8168_registers {
4f6b00e5
HW		 458 LED_FREQ = 0x1a,
459 EEE_LED = 0x1b,
b646d900 460 ERIDR = 0x70,
461 ERIAR = 0x74,
462#define ERIAR_FLAG 0x80000000
463#define ERIAR_WRITE_CMD 0x80000000
464#define ERIAR_READ_CMD 0x00000000
465#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 466#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 467#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
468#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
469#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
470#define ERIAR_MASK_SHIFT 12
471#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
472#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 473#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 474#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 475#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 476 EPHY_RXER_NUM = 0x7c,
477 OCPDR = 0xb0, /* OCP GPHY access */
478#define OCPDR_WRITE_CMD 0x80000000
479#define OCPDR_READ_CMD 0x00000000
480#define OCPDR_REG_MASK 0x7f
481#define OCPDR_GPHY_REG_SHIFT 16
482#define OCPDR_DATA_MASK 0xffff
483 OCPAR = 0xb4,
484#define OCPAR_FLAG 0x80000000
485#define OCPAR_GPHY_WRITE_CMD 0x8000f060
486#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 487 GPHY_OCP = 0xb8,
01dc7fec 488 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
489 MISC = 0xf0, /* 8168e only. */
cecb5fd7 490#define TXPLA_RST (1 << 29)
5598bfe5 491#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 492#define PWM_EN (1 << 22)
c558386b 493#define RXDV_GATED_EN (1 << 19)
5598bfe5 494#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 495};
496
07d3f51f 497enum rtl_register_content {
1da177e4 498 /* InterruptStatusBits */
07d3f51f
FR		 499 SYSErr = 0x8000,
500 PCSTimeout = 0x4000,
501 SWInt = 0x0100,
502 TxDescUnavail = 0x0080,
503 RxFIFOOver = 0x0040,
504 LinkChg = 0x0020,
505 RxOverflow = 0x0010,
506 TxErr = 0x0008,
507 TxOK = 0x0004,
508 RxErr = 0x0002,
509 RxOK = 0x0001,
1da177e4
LT		 510
511 /* RxStatusDesc */
e03f33af 512 RxBOVF = (1 << 24),
9dccf611
FR		 513 RxFOVF = (1 << 23),
514 RxRWT = (1 << 22),
515 RxRES = (1 << 21),
516 RxRUNT = (1 << 20),
517 RxCRC = (1 << 19),
1da177e4
LT		 518
519 /* ChipCmdBits */
4f6b00e5 520 StopReq = 0x80,
07d3f51f
FR		 521 CmdReset = 0x10,
522 CmdRxEnb = 0x08,
523 CmdTxEnb = 0x04,
524 RxBufEmpty = 0x01,
1da177e4 525
275391a4
FR		 526 /* TXPoll register p.5 */
527 HPQ = 0x80, /* Poll cmd on the high prio queue */
528 NPQ = 0x40, /* Poll cmd on the low prio queue */
529 FSWInt = 0x01, /* Forced software interrupt */
530
1da177e4 531 /* Cfg9346Bits */
07d3f51f
FR		 532 Cfg9346_Lock = 0x00,
533 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 534
535 /* rx_mode_bits */
07d3f51f
FR		 536 AcceptErr = 0x20,
537 AcceptRunt = 0x10,
538 AcceptBroadcast = 0x08,
539 AcceptMulticast = 0x04,
540 AcceptMyPhys = 0x02,
541 AcceptAllPhys = 0x01,
1687b566 542#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 543
1da177e4
LT		 544 /* TxConfigBits */
545 TxInterFrameGapShift = 24,
546 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
547
5d06a99f 548 /* Config1 register p.24 */
f162a5d1
FR		 549 LEDS1 = (1 << 7),
550 LEDS0 = (1 << 6),
f162a5d1
FR		 551 Speed_down = (1 << 4),
552 MEMMAP = (1 << 3),
553 IOMAP = (1 << 2),
554 VPD = (1 << 1),
5d06a99f
FR		 555 PMEnable = (1 << 0), /* Power Management Enable */
556
6dccd16b 557 /* Config2 register p. 25 */
57538c4a 558 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 559 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 560 PCI_Clock_66MHz = 0x01,
561 PCI_Clock_33MHz = 0x00,
562
61a4dcc2
FR		 563 /* Config3 register p.25 */
564 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
565 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 566 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 567 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 568 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 569
d58d46b5
FR		 570 /* Config4 register */
571 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
572
5d06a99f 573 /* Config5 register p.27 */
61a4dcc2
FR		 574 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
575 MWF = (1 << 5), /* Accept Multicast wakeup frame */
576 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 577 Spi_en = (1 << 3),
61a4dcc2 578 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 579 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 580 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 581
1da177e4
LT		 582 /* TBICSR p.28 */
583 TBIReset = 0x80000000,
584 TBILoopback = 0x40000000,
585 TBINwEnable = 0x20000000,
586 TBINwRestart = 0x10000000,
587 TBILinkOk = 0x02000000,
588 TBINwComplete = 0x01000000,
589
590 /* CPlusCmd p.31 */
f162a5d1
FR		 591 EnableBist = (1 << 15), // 8168 8101
592 Mac_dbgo_oe = (1 << 14), // 8168 8101
593 Normal_mode = (1 << 13), // unused
594 Force_half_dup = (1 << 12), // 8168 8101
595 Force_rxflow_en = (1 << 11), // 8168 8101
596 Force_txflow_en = (1 << 10), // 8168 8101
597 Cxpl_dbg_sel = (1 << 9), // 8168 8101
598 ASF = (1 << 8), // 8168 8101
599 PktCntrDisable = (1 << 7), // 8168 8101
600 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 601 RxVlan = (1 << 6),
602 RxChkSum = (1 << 5),
603 PCIDAC = (1 << 4),
604 PCIMulRW = (1 << 3),
0e485150
FR		 605 INTT_0 = 0x0000, // 8168
606 INTT_1 = 0x0001, // 8168
607 INTT_2 = 0x0002, // 8168
608 INTT_3 = 0x0003, // 8168
1da177e4
LT		 609
610 /* rtl8169_PHYstatus */
07d3f51f
FR		 611 TBI_Enable = 0x80,
612 TxFlowCtrl = 0x40,
613 RxFlowCtrl = 0x20,
614 _1000bpsF = 0x10,
615 _100bps = 0x08,
616 _10bps = 0x04,
617 LinkStatus = 0x02,
618 FullDup = 0x01,
1da177e4 619
1da177e4 620 /* _TBICSRBit */
07d3f51f 621 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 622
623 /* DumpCounterCommand */
07d3f51f 624 CounterDump = 0x8,
6e1d0b89
CHL		 625
626 /* magic enable v2 */
627 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 628};
629
2b7b4318
FR		 630enum rtl_desc_bit {
631 /* First doubleword. */
1da177e4
LT		 632 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
633 RingEnd = (1 << 30), /* End of descriptor ring */
634 FirstFrag = (1 << 29), /* First segment of a packet */
635 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 636};
637
638/* Generic case. */
639enum rtl_tx_desc_bit {
640 /* First doubleword. */
641 TD_LSO = (1 << 27), /* Large Send Offload */
642#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 643
2b7b4318
FR		 644 /* Second doubleword. */
645 TxVlanTag = (1 << 17), /* Add VLAN tag */
646};
647
648/* 8169, 8168b and 810x except 8102e. */
649enum rtl_tx_desc_bit_0 {
650 /* First doubleword. */
651#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
652 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
653 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
654 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
655};
656
657/* 8102e, 8168c and beyond. */
658enum rtl_tx_desc_bit_1 {
bdfa4ed6 659 /* First doubleword. */
660 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 661 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 662#define GTTCPHO_SHIFT 18
e974604b 663#define GTTCPHO_MAX 0x7fU
bdfa4ed6 664
2b7b4318 665 /* Second doubleword. */
e974604b 666#define TCPHO_SHIFT 18
667#define TCPHO_MAX 0x3ffU
2b7b4318 668#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 669 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
670 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 671 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
672 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
673};
1da177e4 674
2b7b4318 675enum rtl_rx_desc_bit {
1da177e4
LT		 676 /* Rx private */
677 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
678 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
679
680#define RxProtoUDP (PID1)
681#define RxProtoTCP (PID0)
682#define RxProtoIP (PID1 | PID0)
683#define RxProtoMask RxProtoIP
684
685 IPFail = (1 << 16), /* IP checksum failed */
686 UDPFail = (1 << 15), /* UDP/IP checksum failed */
687 TCPFail = (1 << 14), /* TCP/IP checksum failed */
688 RxVlanTag = (1 << 16), /* VLAN tag available */
689};
690
691#define RsvdMask 0x3fffc000
692
693struct TxDesc {
6cccd6e7
REB		 694 __le32 opts1;
695 __le32 opts2;
696 __le64 addr;
1da177e4
LT		 697};
698
699struct RxDesc {
6cccd6e7
REB		 700 __le32 opts1;
701 __le32 opts2;
702 __le64 addr;
1da177e4
LT		 703};
704
705struct ring_info {
706 struct sk_buff *skb;
707 u32 len;
708 u8 __pad[sizeof(void *) - sizeof(u32)];
709};
710
f23e7fda 711enum features {
ccdffb9a
FR		 712 RTL_FEATURE_WOL = (1 << 0),
713 RTL_FEATURE_MSI = (1 << 1),
714 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 715};
716
355423d0
IV		 717struct rtl8169_counters {
718 __le64 tx_packets;
719 __le64 rx_packets;
720 __le64 tx_errors;
721 __le32 rx_errors;
722 __le16 rx_missed;
723 __le16 align_errors;
724 __le32 tx_one_collision;
725 __le32 tx_multi_collision;
726 __le64 rx_unicast;
727 __le64 rx_broadcast;
728 __le32 rx_multicast;
729 __le16 tx_aborted;
730 __le16 tx_underun;
731};
732
da78dbff 733enum rtl_flag {
6c4a70c5 734 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 735 RTL_FLAG_TASK_SLOW_PENDING,
736 RTL_FLAG_TASK_RESET_PENDING,
737 RTL_FLAG_TASK_PHY_PENDING,
738 RTL_FLAG_MAX
739};
740
8027aa24
JW		 741struct rtl8169_stats {
742 u64 packets;
743 u64 bytes;
744 struct u64_stats_sync syncp;
745};
746
1da177e4
LT		 747struct rtl8169_private {
748 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 749 struct pci_dev *pci_dev;
c4028958 750 struct net_device *dev;
bea3348e 751 struct napi_struct napi;
b57b7e5a 752 u32 msg_enable;
2b7b4318
FR		 753 u16 txd_version;
754 u16 mac_version;
1da177e4
LT		 755 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
756 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 757 u32 dirty_tx;
8027aa24
JW		 758 struct rtl8169_stats rx_stats;
759 struct rtl8169_stats tx_stats;
1da177e4
LT		 760 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
761 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
762 dma_addr_t TxPhyAddr;
763 dma_addr_t RxPhyAddr;
6f0333b8 764 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 765 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 766 struct timer_list timer;
767 u16 cp_cmd;
da78dbff
FR		 768
769 u16 event_slow;
c0e45c1c 770
771 struct mdio_ops {
24192210
FR		 772 void (*write)(struct rtl8169_private *, int, int);
773 int (*read)(struct rtl8169_private *, int);
c0e45c1c 774 } mdio_ops;
775
065c27c1 776 struct pll_power_ops {
777 void (*down)(struct rtl8169_private *);
778 void (*up)(struct rtl8169_private *);
779 } pll_power_ops;
780
d58d46b5
FR		 781 struct jumbo_ops {
782 void (*enable)(struct rtl8169_private *);
783 void (*disable)(struct rtl8169_private *);
784 } jumbo_ops;
785
beb1fe18 786 struct csi_ops {
52989f0e
FR		 787 void (*write)(struct rtl8169_private *, int, int);
788 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 789 } csi_ops;
790
54405cde 791 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 792 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 793 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 794 void (*hw_start)(struct net_device *);
4da19633 795 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 796 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 797 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 798 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 799
800 struct {
da78dbff
FR		 801 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
802 struct mutex mutex;
4422bcd4
FR		 803 struct work_struct work;
804 } wk;
805
f23e7fda 806 unsigned features;
ccdffb9a
FR		 807
808 struct mii_if_info mii;
355423d0 809 struct rtl8169_counters counters;
e1759441 810 u32 saved_wolopts;
e03f33af 811 u32 opts1_mask;
f1e02ed1 812
b6ffd97f
FR		 813 struct rtl_fw {
814 const struct firmware *fw;
1c361efb
FR		 815
816#define RTL_VER_SIZE 32
817
818 char version[RTL_VER_SIZE];
819
820 struct rtl_fw_phy_action {
821 __le32 *code;
822 size_t size;
823 } phy_action;
b6ffd97f 824 } *rtl_fw;
497888cf 825#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 826
827 u32 ocp_base;
1da177e4
LT		 828};
829
979b6c13 830MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 831MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 832module_param(use_dac, int, 0);
4300e8c7 833MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 834module_param_named(debug, debug.msg_enable, int, 0);
835MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 836MODULE_LICENSE("GPL");
837MODULE_VERSION(RTL8169_VERSION);
bca03d5f 838MODULE_FIRMWARE(FIRMWARE_8168D_1);
839MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 840MODULE_FIRMWARE(FIRMWARE_8168E_1);
841MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 842MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 843MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 844MODULE_FIRMWARE(FIRMWARE_8168F_1);
845MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 846MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 847MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 848MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 849MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 850MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 851MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 852MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 853MODULE_FIRMWARE(FIRMWARE_8168H_1);
854MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 855MODULE_FIRMWARE(FIRMWARE_8107E_1);
856MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 857
da78dbff
FR		 858static void rtl_lock_work(struct rtl8169_private *tp)
859{
860 mutex_lock(&tp->wk.mutex);
861}
862
863static void rtl_unlock_work(struct rtl8169_private *tp)
864{
865 mutex_unlock(&tp->wk.mutex);
866}
867
d58d46b5
FR		 868static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
869{
7d7903b2
JL		 870 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
871 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 872}
873
ffc46952
FR		 874struct rtl_cond {
875 bool (*check)(struct rtl8169_private *);
876 const char *msg;
877};
878
879static void rtl_udelay(unsigned int d)
880{
881 udelay(d);
882}
883
884static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
885 void (*delay)(unsigned int), unsigned int d, int n,
886 bool high)
887{
888 int i;
889
890 for (i = 0; i < n; i++) {
891 delay(d);
892 if (c->check(tp) == high)
893 return true;
894 }
82e316ef
FR		 895 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
896 c->msg, !high, n, d);
ffc46952
FR		 897 return false;
898}
899
900static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
901 const struct rtl_cond *c,
902 unsigned int d, int n)
903{
904 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
905}
906
907static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
908 const struct rtl_cond *c,
909 unsigned int d, int n)
910{
911 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
912}
913
914static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
915 const struct rtl_cond *c,
916 unsigned int d, int n)
917{
918 return rtl_loop_wait(tp, c, msleep, d, n, true);
919}
920
921static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
922 const struct rtl_cond *c,
923 unsigned int d, int n)
924{
925 return rtl_loop_wait(tp, c, msleep, d, n, false);
926}
927
928#define DECLARE_RTL_COND(name) \
929static bool name ## _check(struct rtl8169_private *); \
930 \
931static const struct rtl_cond name = { \
932 .check = name ## _check, \
933 .msg = #name \
934}; \
935 \
936static bool name ## _check(struct rtl8169_private *tp)
937
938DECLARE_RTL_COND(rtl_ocpar_cond)
939{
940 void __iomem *ioaddr = tp->mmio_addr;
941
942 return RTL_R32(OCPAR) & OCPAR_FLAG;
943}
944
b646d900 945static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
946{
947 void __iomem *ioaddr = tp->mmio_addr;
b646d900 948
949 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 950
951 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
952 RTL_R32(OCPDR) : ~0;
b646d900 953}
954
955static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
956{
957 void __iomem *ioaddr = tp->mmio_addr;
b646d900 958
959 RTL_W32(OCPDR, data);
960 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 961
962 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
963}
964
965DECLARE_RTL_COND(rtl_eriar_cond)
966{
967 void __iomem *ioaddr = tp->mmio_addr;
968
969 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 970}
971
c558386b
HW		 972static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
973{
974 if (reg & 0xffff0001) {
975 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
976 return true;
977 }
978 return false;
979}
980
981DECLARE_RTL_COND(rtl_ocp_gphy_cond)
982{
983 void __iomem *ioaddr = tp->mmio_addr;
984
985 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
986}
987
988static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
989{
990 void __iomem *ioaddr = tp->mmio_addr;
991
992 if (rtl_ocp_reg_failure(tp, reg))
993 return;
994
995 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
996
997 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
998}
999
1000static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1001{
1002 void __iomem *ioaddr = tp->mmio_addr;
1003
1004 if (rtl_ocp_reg_failure(tp, reg))
1005 return 0;
1006
1007 RTL_W32(GPHY_OCP, reg << 15);
1008
1009 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1010 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1011}
1012
c558386b
HW		 1013static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1014{
1015 void __iomem *ioaddr = tp->mmio_addr;
1016
1017 if (rtl_ocp_reg_failure(tp, reg))
1018 return;
1019
1020 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1021}
1022
1023static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1024{
1025 void __iomem *ioaddr = tp->mmio_addr;
1026
1027 if (rtl_ocp_reg_failure(tp, reg))
1028 return 0;
1029
1030 RTL_W32(OCPDR, reg << 15);
1031
3a83ad12 1032 return RTL_R32(OCPDR);
c558386b
HW		 1033}
1034
1035#define OCP_STD_PHY_BASE 0xa400
1036
1037static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1038{
1039 if (reg == 0x1f) {
1040 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1041 return;
1042 }
1043
1044 if (tp->ocp_base != OCP_STD_PHY_BASE)
1045 reg -= 0x10;
1046
1047 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1048}
1049
1050static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1051{
1052 if (tp->ocp_base != OCP_STD_PHY_BASE)
1053 reg -= 0x10;
1054
1055 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1056}
1057
eee3786f 1058static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1059{
1060 if (reg == 0x1f) {
1061 tp->ocp_base = value << 4;
1062 return;
1063 }
1064
1065 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1066}
1067
1068static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1069{
1070 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1071}
1072
ffc46952
FR		 1073DECLARE_RTL_COND(rtl_phyar_cond)
1074{
1075 void __iomem *ioaddr = tp->mmio_addr;
1076
1077 return RTL_R32(PHYAR) & 0x80000000;
1078}
1079
24192210 1080static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1081{
24192210 1082 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1083
24192210 1084 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1085
ffc46952 1086 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1087 /*
81a95f04
TT		 1088 * According to hardware specs a 20us delay is required after write
1089 * complete indication, but before sending next command.
024a07ba 1090 */
81a95f04 1091 udelay(20);
1da177e4
LT		 1092}
1093
24192210 1094static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1095{
24192210 1096 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1097 int value;
1da177e4 1098
24192210 1099 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1100
ffc46952
FR		 1101 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1102 RTL_R32(PHYAR) & 0xffff : ~0;
1103
81a95f04
TT		 1104 /*
1105 * According to hardware specs a 20us delay is required after read
1106 * complete indication, but before sending next command.
1107 */
1108 udelay(20);
1109
1da177e4
LT		 1110 return value;
1111}
1112
24192210 1113static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1114{
24192210 1115 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1116
24192210 1117 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1118 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1119 RTL_W32(EPHY_RXER_NUM, 0);
1120
ffc46952 1121 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1122}
1123
24192210 1124static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1125{
24192210
FR		 1126 r8168dp_1_mdio_access(tp, reg,
1127 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1128}
1129
24192210 1130static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1131{
24192210 1132 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1133
24192210 1134 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1135
1136 mdelay(1);
1137 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1138 RTL_W32(EPHY_RXER_NUM, 0);
1139
ffc46952
FR		 1140 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1141 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1142}
1143
e6de30d6 1144#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1145
1146static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1147{
1148 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1149}
1150
1151static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1152{
1153 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1154}
1155
24192210 1156static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1157{
24192210
FR		 1158 void __iomem *ioaddr = tp->mmio_addr;
1159
e6de30d6 1160 r8168dp_2_mdio_start(ioaddr);
1161
24192210 1162 r8169_mdio_write(tp, reg, value);
e6de30d6 1163
1164 r8168dp_2_mdio_stop(ioaddr);
1165}
1166
24192210 1167static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1168{
24192210 1169 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1170 int value;
1171
1172 r8168dp_2_mdio_start(ioaddr);
1173
24192210 1174 value = r8169_mdio_read(tp, reg);
e6de30d6 1175
1176 r8168dp_2_mdio_stop(ioaddr);
1177
1178 return value;
1179}
1180
4da19633 1181static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1182{
24192210 1183 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1184}
1185
4da19633 1186static int rtl_readphy(struct rtl8169_private *tp, int location)
1187{
24192210 1188 return tp->mdio_ops.read(tp, location);
4da19633 1189}
1190
1191static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1192{
1193 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1194}
1195
76564428 1196static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1197{
1198 int val;
1199
4da19633 1200 val = rtl_readphy(tp, reg_addr);
76564428 1201 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1202}
1203
ccdffb9a
FR		 1204static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1205 int val)
1206{
1207 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1208
4da19633 1209 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1210}
1211
1212static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1213{
1214 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1215
4da19633 1216 return rtl_readphy(tp, location);
ccdffb9a
FR		 1217}
1218
ffc46952
FR		 1219DECLARE_RTL_COND(rtl_ephyar_cond)
1220{
1221 void __iomem *ioaddr = tp->mmio_addr;
1222
1223 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1224}
1225
fdf6fc06 1226static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1227{
fdf6fc06 1228 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1229
1230 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1231 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1232
ffc46952
FR		 1233 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1234
1235 udelay(10);
dacf8154
FR		 1236}
1237
fdf6fc06 1238static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1239{
fdf6fc06 1240 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1241
1242 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1243
ffc46952
FR		 1244 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1245 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1246}
1247
fdf6fc06
FR		 1248static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1249 u32 val, int type)
133ac40a 1250{
fdf6fc06 1251 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1252
1253 BUG_ON((addr & 3) || (mask == 0));
1254 RTL_W32(ERIDR, val);
1255 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1256
ffc46952 1257 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1258}
1259
fdf6fc06 1260static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1261{
fdf6fc06 1262 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1263
1264 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1265
ffc46952
FR		 1266 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1267 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1268}
1269
706123d0 1270static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1271 u32 m, int type)
133ac40a
HW		 1272{
1273 u32 val;
1274
fdf6fc06
FR		 1275 val = rtl_eri_read(tp, addr, type);
1276 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1277}
1278
2a9b4d96
CHL		 1279static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1280{
1281 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1282
1283 ocp_write(tp, 0x1, 0x30, 0x00000001);
1284}
1285
1286#define OOB_CMD_RESET 0x00
1287#define OOB_CMD_DRIVER_START 0x05
1288#define OOB_CMD_DRIVER_STOP 0x06
1289
1290static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1291{
1292 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1293}
1294
1295DECLARE_RTL_COND(rtl_ocp_read_cond)
1296{
1297 u16 reg;
1298
1299 reg = rtl8168_get_ocp_reg(tp);
1300
1301 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1302}
1303
1304static void rtl8168_driver_start(struct rtl8169_private *tp)
1305{
1306 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1307
1308 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1309}
1310
1311static void rtl8168_driver_stop(struct rtl8169_private *tp)
1312{
1313 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1314
1315 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1316}
1317
1318static int r8168_check_dash(struct rtl8169_private *tp)
1319{
1320 u16 reg = rtl8168_get_ocp_reg(tp);
1321
1322 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1323}
1324
c28aa385 1325struct exgmac_reg {
1326 u16 addr;
1327 u16 mask;
1328 u32 val;
1329};
1330
fdf6fc06 1331static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1332 const struct exgmac_reg *r, int len)
1333{
1334 while (len-- > 0) {
fdf6fc06 1335 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1336 r++;
1337 }
1338}
1339
ffc46952
FR		 1340DECLARE_RTL_COND(rtl_efusear_cond)
1341{
1342 void __iomem *ioaddr = tp->mmio_addr;
1343
1344 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1345}
1346
fdf6fc06 1347static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1348{
fdf6fc06 1349 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1350
1351 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1352
ffc46952
FR		 1353 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1354 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1355}
1356
9085cdfa
FR		 1357static u16 rtl_get_events(struct rtl8169_private *tp)
1358{
1359 void __iomem *ioaddr = tp->mmio_addr;
1360
1361 return RTL_R16(IntrStatus);
1362}
1363
1364static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1365{
1366 void __iomem *ioaddr = tp->mmio_addr;
1367
1368 RTL_W16(IntrStatus, bits);
1369 mmiowb();
1370}
1371
1372static void rtl_irq_disable(struct rtl8169_private *tp)
1373{
1374 void __iomem *ioaddr = tp->mmio_addr;
1375
1376 RTL_W16(IntrMask, 0);
1377 mmiowb();
1378}
1379
3e990ff5
FR		 1380static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1381{
1382 void __iomem *ioaddr = tp->mmio_addr;
1383
1384 RTL_W16(IntrMask, bits);
1385}
1386
da78dbff
FR		 1387#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1388#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1389#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1390
1391static void rtl_irq_enable_all(struct rtl8169_private *tp)
1392{
1393 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1394}
1395
811fd301 1396static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1397{
811fd301 1398 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1399
9085cdfa 1400 rtl_irq_disable(tp);
da78dbff 1401 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1402 RTL_R8(ChipCmd);
1da177e4
LT		 1403}
1404
4da19633 1405static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1406{
4da19633 1407 void __iomem *ioaddr = tp->mmio_addr;
1408
1da177e4
LT		 1409 return RTL_R32(TBICSR) & TBIReset;
1410}
1411
4da19633 1412static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1413{
4da19633 1414 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1415}
1416
1417static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1418{
1419 return RTL_R32(TBICSR) & TBILinkOk;
1420}
1421
1422static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1423{
1424 return RTL_R8(PHYstatus) & LinkStatus;
1425}
1426
4da19633 1427static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1428{
4da19633 1429 void __iomem *ioaddr = tp->mmio_addr;
1430
1da177e4
LT		 1431 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1432}
1433
4da19633 1434static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1435{
1436 unsigned int val;
1437
4da19633 1438 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1439 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1440}
1441
70090424
HW		 1442static void rtl_link_chg_patch(struct rtl8169_private *tp)
1443{
1444 void __iomem *ioaddr = tp->mmio_addr;
1445 struct net_device *dev = tp->dev;
1446
1447 if (!netif_running(dev))
1448 return;
1449
b3d7b2f2
HW		 1450 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1451 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1452 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1453 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1454 ERIAR_EXGMAC);
1455 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1456 ERIAR_EXGMAC);
70090424 1457 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1458 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1459 ERIAR_EXGMAC);
1460 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1461 ERIAR_EXGMAC);
70090424 1462 } else {
fdf6fc06
FR		 1463 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1464 ERIAR_EXGMAC);
1465 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1466 ERIAR_EXGMAC);
70090424
HW		 1467 }
1468 /* Reset packet filter */
706123d0 1469 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1470 ERIAR_EXGMAC);
706123d0 1471 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1472 ERIAR_EXGMAC);
c2218925
HW		 1473 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1474 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1475 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1476 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1477 ERIAR_EXGMAC);
1478 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1479 ERIAR_EXGMAC);
c2218925 1480 } else {
fdf6fc06
FR		 1481 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1482 ERIAR_EXGMAC);
1483 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1484 ERIAR_EXGMAC);
c2218925 1485 }
7e18dca1
HW		 1486 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1487 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1488 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1489 ERIAR_EXGMAC);
1490 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1491 ERIAR_EXGMAC);
7e18dca1 1492 } else {
fdf6fc06
FR		 1493 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1494 ERIAR_EXGMAC);
7e18dca1 1495 }
70090424
HW		 1496 }
1497}
1498
e4fbce74 1499static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1500 struct rtl8169_private *tp,
1501 void __iomem *ioaddr, bool pm)
1da177e4 1502{
1da177e4 1503 if (tp->link_ok(ioaddr)) {
70090424 1504 rtl_link_chg_patch(tp);
e1759441 1505 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1506 if (pm)
1507 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1508 netif_carrier_on(dev);
1519e57f
FR		 1509 if (net_ratelimit())
1510 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1511 } else {
1da177e4 1512 netif_carrier_off(dev);
bf82c189 1513 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1514 if (pm)
10953db8 1515 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1516 }
1da177e4
LT		 1517}
1518
e4fbce74
RW		 1519static void rtl8169_check_link_status(struct net_device *dev,
1520 struct rtl8169_private *tp,
1521 void __iomem *ioaddr)
1522{
1523 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1524}
1525
e1759441
RW		 1526#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1527
1528static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1529{
61a4dcc2
FR		 1530 void __iomem *ioaddr = tp->mmio_addr;
1531 u8 options;
e1759441 1532 u32 wolopts = 0;
61a4dcc2
FR		 1533
1534 options = RTL_R8(Config1);
1535 if (!(options & PMEnable))
e1759441 1536 return 0;
61a4dcc2
FR		 1537
1538 options = RTL_R8(Config3);
1539 if (options & LinkUp)
e1759441 1540 wolopts |= WAKE_PHY;
6e1d0b89 1541 switch (tp->mac_version) {
ac85bcdb
CHL		 1542 case RTL_GIGA_MAC_VER_34:
1543 case RTL_GIGA_MAC_VER_35:
1544 case RTL_GIGA_MAC_VER_36:
1545 case RTL_GIGA_MAC_VER_37:
1546 case RTL_GIGA_MAC_VER_38:
1547 case RTL_GIGA_MAC_VER_40:
1548 case RTL_GIGA_MAC_VER_41:
1549 case RTL_GIGA_MAC_VER_42:
1550 case RTL_GIGA_MAC_VER_43:
1551 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1552 case RTL_GIGA_MAC_VER_45:
1553 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1554 case RTL_GIGA_MAC_VER_47:
1555 case RTL_GIGA_MAC_VER_48:
6e1d0b89
CHL		 1556 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1557 wolopts |= WAKE_MAGIC;
1558 break;
1559 default:
1560 if (options & MagicPacket)
1561 wolopts |= WAKE_MAGIC;
1562 break;
1563 }
61a4dcc2
FR		 1564
1565 options = RTL_R8(Config5);
1566 if (options & UWF)
e1759441 1567 wolopts |= WAKE_UCAST;
61a4dcc2 1568 if (options & BWF)
e1759441 1569 wolopts |= WAKE_BCAST;
61a4dcc2 1570 if (options & MWF)
e1759441 1571 wolopts |= WAKE_MCAST;
61a4dcc2 1572
e1759441 1573 return wolopts;
61a4dcc2
FR		 1574}
1575
e1759441 1576static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1577{
1578 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1579
da78dbff 1580 rtl_lock_work(tp);
e1759441
RW		 1581
1582 wol->supported = WAKE_ANY;
1583 wol->wolopts = __rtl8169_get_wol(tp);
1584
da78dbff 1585 rtl_unlock_work(tp);
e1759441
RW		 1586}
1587
1588static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1589{
61a4dcc2 1590 void __iomem *ioaddr = tp->mmio_addr;
6e1d0b89 1591 unsigned int i, tmp;
350f7596 1592 static const struct {
61a4dcc2
FR		 1593 u32 opt;
1594 u16 reg;
1595 u8 mask;
1596 } cfg[] = {
61a4dcc2 1597 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1598 { WAKE_UCAST, Config5, UWF },
1599 { WAKE_BCAST, Config5, BWF },
1600 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1601 { WAKE_ANY, Config5, LanWake },
1602 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1603 };
851e6022 1604 u8 options;
61a4dcc2 1605
61a4dcc2
FR		 1606 RTL_W8(Cfg9346, Cfg9346_Unlock);
1607
6e1d0b89 1608 switch (tp->mac_version) {
ac85bcdb
CHL		 1609 case RTL_GIGA_MAC_VER_34:
1610 case RTL_GIGA_MAC_VER_35:
1611 case RTL_GIGA_MAC_VER_36:
1612 case RTL_GIGA_MAC_VER_37:
1613 case RTL_GIGA_MAC_VER_38:
1614 case RTL_GIGA_MAC_VER_40:
1615 case RTL_GIGA_MAC_VER_41:
1616 case RTL_GIGA_MAC_VER_42:
1617 case RTL_GIGA_MAC_VER_43:
1618 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1619 case RTL_GIGA_MAC_VER_45:
1620 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1621 case RTL_GIGA_MAC_VER_47:
1622 case RTL_GIGA_MAC_VER_48:
6e1d0b89
CHL		 1623 tmp = ARRAY_SIZE(cfg) - 1;
1624 if (wolopts & WAKE_MAGIC)
706123d0 1625 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1626 0x0dc,
1627 ERIAR_MASK_0100,
1628 MagicPacket_v2,
1629 0x0000,
1630 ERIAR_EXGMAC);
1631 else
706123d0 1632 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1633 0x0dc,
1634 ERIAR_MASK_0100,
1635 0x0000,
1636 MagicPacket_v2,
1637 ERIAR_EXGMAC);
1638 break;
1639 default:
1640 tmp = ARRAY_SIZE(cfg);
1641 break;
1642 }
1643
1644 for (i = 0; i < tmp; i++) {
851e6022 1645 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1646 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1647 options |= cfg[i].mask;
1648 RTL_W8(cfg[i].reg, options);
1649 }
1650
851e6022
FR		 1651 switch (tp->mac_version) {
1652 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1653 options = RTL_R8(Config1) & ~PMEnable;
1654 if (wolopts)
1655 options |= PMEnable;
1656 RTL_W8(Config1, options);
1657 break;
1658 default:
d387b427
FR		 1659 options = RTL_R8(Config2) & ~PME_SIGNAL;
1660 if (wolopts)
1661 options |= PME_SIGNAL;
1662 RTL_W8(Config2, options);
851e6022
FR		 1663 break;
1664 }
1665
61a4dcc2 1666 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1667}
1668
1669static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1670{
1671 struct rtl8169_private *tp = netdev_priv(dev);
1672
da78dbff 1673 rtl_lock_work(tp);
61a4dcc2 1674
f23e7fda
FR		 1675 if (wol->wolopts)
1676 tp->features |= RTL_FEATURE_WOL;
1677 else
1678 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1679 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1680
1681 rtl_unlock_work(tp);
61a4dcc2 1682
ea80907f 1683 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1684
61a4dcc2
FR		 1685 return 0;
1686}
1687
31bd204f
FR		 1688static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1689{
85bffe6c 1690 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1691}
1692
1da177e4
LT		 1693static void rtl8169_get_drvinfo(struct net_device *dev,
1694 struct ethtool_drvinfo *info)
1695{
1696 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1697 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1698
68aad78c
RJ		 1699 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1700 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1701 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1702 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1703 if (!IS_ERR_OR_NULL(rtl_fw))
1704 strlcpy(info->fw_version, rtl_fw->version,
1705 sizeof(info->fw_version));
1da177e4
LT		 1706}
1707
1708static int rtl8169_get_regs_len(struct net_device *dev)
1709{
1710 return R8169_REGS_SIZE;
1711}
1712
1713static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1714 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1715{
1716 struct rtl8169_private *tp = netdev_priv(dev);
1717 void __iomem *ioaddr = tp->mmio_addr;
1718 int ret = 0;
1719 u32 reg;
1720
1721 reg = RTL_R32(TBICSR);
1722 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1723 (duplex == DUPLEX_FULL)) {
1724 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1725 } else if (autoneg == AUTONEG_ENABLE)
1726 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1727 else {
bf82c189
JP		 1728 netif_warn(tp, link, dev,
1729 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1730 ret = -EOPNOTSUPP;
1731 }
1732
1733 return ret;
1734}
1735
1736static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1737 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1738{
1739 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1740 int giga_ctrl, bmcr;
54405cde 1741 int rc = -EINVAL;
1da177e4 1742
716b50a3 1743 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1744
1745 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1746 int auto_nego;
1747
4da19633 1748 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1749 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1750 ADVERTISE_100HALF | ADVERTISE_100FULL);
1751
1752 if (adv & ADVERTISED_10baseT_Half)
1753 auto_nego |= ADVERTISE_10HALF;
1754 if (adv & ADVERTISED_10baseT_Full)
1755 auto_nego |= ADVERTISE_10FULL;
1756 if (adv & ADVERTISED_100baseT_Half)
1757 auto_nego |= ADVERTISE_100HALF;
1758 if (adv & ADVERTISED_100baseT_Full)
1759 auto_nego |= ADVERTISE_100FULL;
1760
3577aa1b 1761 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1762
4da19633 1763 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1764 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1765
3577aa1b 1766 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1767 if (tp->mii.supports_gmii) {
54405cde
ON		 1768 if (adv & ADVERTISED_1000baseT_Half)
1769 giga_ctrl |= ADVERTISE_1000HALF;
1770 if (adv & ADVERTISED_1000baseT_Full)
1771 giga_ctrl |= ADVERTISE_1000FULL;
1772 } else if (adv & (ADVERTISED_1000baseT_Half |
1773 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1774 netif_info(tp, link, dev,
1775 "PHY does not support 1000Mbps\n");
54405cde 1776 goto out;
bcf0bf90 1777 }
1da177e4 1778
3577aa1b 1779 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1780
4da19633 1781 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1782 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1783 } else {
1784 giga_ctrl = 0;
1785
1786 if (speed == SPEED_10)
1787 bmcr = 0;
1788 else if (speed == SPEED_100)
1789 bmcr = BMCR_SPEED100;
1790 else
54405cde 1791 goto out;
3577aa1b 1792
1793 if (duplex == DUPLEX_FULL)
1794 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1795 }
1796
4da19633 1797 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1798
cecb5fd7
FR		 1799 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1800 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1801 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1802 rtl_writephy(tp, 0x17, 0x2138);
1803 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1804 } else {
4da19633 1805 rtl_writephy(tp, 0x17, 0x2108);
1806 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1807 }
1808 }
1809
54405cde
ON		 1810 rc = 0;
1811out:
1812 return rc;
1da177e4
LT		 1813}
1814
1815static int rtl8169_set_speed(struct net_device *dev,
54405cde 1816 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1817{
1818 struct rtl8169_private *tp = netdev_priv(dev);
1819 int ret;
1820
54405cde 1821 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1822 if (ret < 0)
1823 goto out;
1da177e4 1824
4876cc1e
FR		 1825 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1826 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1827 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1828 }
1829out:
1da177e4
LT		 1830 return ret;
1831}
1832
1833static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1834{
1835 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1836 int ret;
1837
4876cc1e
FR		 1838 del_timer_sync(&tp->timer);
1839
da78dbff 1840 rtl_lock_work(tp);
cecb5fd7 1841 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1842 cmd->duplex, cmd->advertising);
da78dbff 1843 rtl_unlock_work(tp);
5b0384f4 1844
1da177e4
LT		 1845 return ret;
1846}
1847
c8f44aff
MM		 1848static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1849 netdev_features_t features)
1da177e4 1850{
d58d46b5
FR		 1851 struct rtl8169_private *tp = netdev_priv(dev);
1852
2b7b4318 1853 if (dev->mtu > TD_MSS_MAX)
350fb32a 1854 features &= ~NETIF_F_ALL_TSO;
1da177e4 1855
d58d46b5
FR		 1856 if (dev->mtu > JUMBO_1K &&
1857 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1858 features &= ~NETIF_F_IP_CSUM;
1859
350fb32a 1860 return features;
1da177e4
LT		 1861}
1862
da78dbff
FR		 1863static void __rtl8169_set_features(struct net_device *dev,
1864 netdev_features_t features)
1da177e4
LT		 1865{
1866 struct rtl8169_private *tp = netdev_priv(dev);
da78dbff 1867 void __iomem *ioaddr = tp->mmio_addr;
929a031d 1868 u32 rx_config;
1da177e4 1869
929a031d 1870 rx_config = RTL_R32(RxConfig);
1871 if (features & NETIF_F_RXALL)
1872 rx_config |= (AcceptErr | AcceptRunt);
1873 else
1874 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1875
929a031d 1876 RTL_W32(RxConfig, rx_config);
350fb32a 1877
929a031d 1878 if (features & NETIF_F_RXCSUM)
1879 tp->cp_cmd |= RxChkSum;
1880 else
1881 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1882
929a031d 1883 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1884 tp->cp_cmd |= RxVlan;
1885 else
1886 tp->cp_cmd &= ~RxVlan;
1887
1888 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
1889
1890 RTL_W16(CPlusCmd, tp->cp_cmd);
1891 RTL_R16(CPlusCmd);
da78dbff 1892}
1da177e4 1893
da78dbff
FR		 1894static int rtl8169_set_features(struct net_device *dev,
1895 netdev_features_t features)
1896{
1897 struct rtl8169_private *tp = netdev_priv(dev);
1898
929a031d 1899 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
1900
da78dbff 1901 rtl_lock_work(tp);
85911d71 1902 if (features ^ dev->features)
929a031d 1903 __rtl8169_set_features(dev, features);
da78dbff 1904 rtl_unlock_work(tp);
1da177e4
LT		 1905
1906 return 0;
1907}
1908
da78dbff 1909
810f4893 1910static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1911{
eab6d18d 1912 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1913 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1914}
1915
7a8fc77b 1916static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1917{
1918 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1919
7a8fc77b 1920 if (opts2 & RxVlanTag)
86a9bad3 1921 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1922}
1923
ccdffb9a 1924static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1925{
1926 struct rtl8169_private *tp = netdev_priv(dev);
1927 void __iomem *ioaddr = tp->mmio_addr;
1928 u32 status;
1929
1930 cmd->supported =
1931 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1932 cmd->port = PORT_FIBRE;
1933 cmd->transceiver = XCVR_INTERNAL;
1934
1935 status = RTL_R32(TBICSR);
1936 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1937 cmd->autoneg = !!(status & TBINwEnable);
1938
70739497 1939 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1940 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1941
1942 return 0;
1da177e4
LT		 1943}
1944
ccdffb9a 1945static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1946{
1947 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1948
1949 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1950}
1951
1952static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1953{
1954 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1955 int rc;
1da177e4 1956
da78dbff 1957 rtl_lock_work(tp);
ccdffb9a 1958 rc = tp->get_settings(dev, cmd);
da78dbff 1959 rtl_unlock_work(tp);
1da177e4 1960
ccdffb9a 1961 return rc;
1da177e4
LT		 1962}
1963
1964static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1965 void *p)
1966{
5b0384f4 1967 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1968 u32 __iomem *data = tp->mmio_addr;
1969 u32 *dw = p;
1970 int i;
1da177e4 1971
da78dbff 1972 rtl_lock_work(tp);
15edae91
PW		 1973 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1974 memcpy_fromio(dw++, data++, 4);
da78dbff 1975 rtl_unlock_work(tp);
1da177e4
LT		 1976}
1977
b57b7e5a
SH		 1978static u32 rtl8169_get_msglevel(struct net_device *dev)
1979{
1980 struct rtl8169_private *tp = netdev_priv(dev);
1981
1982 return tp->msg_enable;
1983}
1984
1985static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1986{
1987 struct rtl8169_private *tp = netdev_priv(dev);
1988
1989 tp->msg_enable = value;
1990}
1991
d4a3a0fc
SH		 1992static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1993 "tx_packets",
1994 "rx_packets",
1995 "tx_errors",
1996 "rx_errors",
1997 "rx_missed",
1998 "align_errors",
1999 "tx_single_collisions",
2000 "tx_multi_collisions",
2001 "unicast",
2002 "broadcast",
2003 "multicast",
2004 "tx_aborted",
2005 "tx_underrun",
2006};
2007
b9f2c044 2008static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2009{
b9f2c044
JG		 2010 switch (sset) {
2011 case ETH_SS_STATS:
2012 return ARRAY_SIZE(rtl8169_gstrings);
2013 default:
2014 return -EOPNOTSUPP;
2015 }
d4a3a0fc
SH		 2016}
2017
ffc46952
FR		 2018DECLARE_RTL_COND(rtl_counters_cond)
2019{
2020 void __iomem *ioaddr = tp->mmio_addr;
2021
2022 return RTL_R32(CounterAddrLow) & CounterDump;
2023}
2024
355423d0 2025static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2026{
2027 struct rtl8169_private *tp = netdev_priv(dev);
2028 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 2029 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 2030 struct rtl8169_counters *counters;
2031 dma_addr_t paddr;
2032 u32 cmd;
2033
355423d0
IV		 2034 /*
2035 * Some chips are unable to dump tally counters when the receiver
2036 * is disabled.
2037 */
2038 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2039 return;
d4a3a0fc 2040
48addcc9 2041 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 2042 if (!counters)
2043 return;
2044
2045 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 2046 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 2047 RTL_W32(CounterAddrLow, cmd);
2048 RTL_W32(CounterAddrLow, cmd | CounterDump);
2049
ffc46952
FR		 2050 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2051 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 2052
2053 RTL_W32(CounterAddrLow, 0);
2054 RTL_W32(CounterAddrHigh, 0);
2055
48addcc9 2056 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 2057}
2058
355423d0
IV		 2059static void rtl8169_get_ethtool_stats(struct net_device *dev,
2060 struct ethtool_stats *stats, u64 *data)
2061{
2062 struct rtl8169_private *tp = netdev_priv(dev);
2063
2064 ASSERT_RTNL();
2065
2066 rtl8169_update_counters(dev);
2067
2068 data[0] = le64_to_cpu(tp->counters.tx_packets);
2069 data[1] = le64_to_cpu(tp->counters.rx_packets);
2070 data[2] = le64_to_cpu(tp->counters.tx_errors);
2071 data[3] = le32_to_cpu(tp->counters.rx_errors);
2072 data[4] = le16_to_cpu(tp->counters.rx_missed);
2073 data[5] = le16_to_cpu(tp->counters.align_errors);
2074 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2075 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2076 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2077 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2078 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2079 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2080 data[12] = le16_to_cpu(tp->counters.tx_underun);
2081}
2082
d4a3a0fc
SH		 2083static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2084{
2085 switch(stringset) {
2086 case ETH_SS_STATS:
2087 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2088 break;
2089 }
2090}
2091
7282d491 2092static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2093 .get_drvinfo = rtl8169_get_drvinfo,
2094 .get_regs_len = rtl8169_get_regs_len,
2095 .get_link = ethtool_op_get_link,
2096 .get_settings = rtl8169_get_settings,
2097 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2098 .get_msglevel = rtl8169_get_msglevel,
2099 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2100 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2101 .get_wol = rtl8169_get_wol,
2102 .set_wol = rtl8169_set_wol,
d4a3a0fc 2103 .get_strings = rtl8169_get_strings,
b9f2c044 2104 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2105 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2106 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2107};
2108
07d3f51f 2109static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2110 struct net_device *dev, u8 default_version)
1da177e4 2111{
5d320a20 2112 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2113 /*
2114 * The driver currently handles the 8168Bf and the 8168Be identically
2115 * but they can be identified more specifically through the test below
2116 * if needed:
2117 *
2118 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2119 *
2120 * Same thing for the 8101Eb and the 8101Ec:
2121 *
2122 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2123 */
3744100e 2124 static const struct rtl_mac_info {
1da177e4 2125 u32 mask;
e3cf0cc0 2126 u32 val;
1da177e4
LT		 2127 int mac_version;
2128 } mac_info[] = {
6e1d0b89
CHL		 2129 /* 8168H family. */
2130 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2131 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2132
c558386b 2133 /* 8168G family. */
45dd95c4 2134 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2135 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2136 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2137 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2138
c2218925 2139 /* 8168F family. */
b3d7b2f2 2140 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2141 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2142 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2143
01dc7fec 2144 /* 8168E family. */
70090424 2145 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2146 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2147 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2148 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2149
5b538df9 2150 /* 8168D family. */
daf9df6d 2151 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2152 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2153 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2154
e6de30d6 2155 /* 8168DP family. */
2156 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2157 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2158 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2159
ef808d50 2160 /* 8168C family. */
17c99297 2161 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2162 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2163 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2164 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2165 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2166 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2167 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2168 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2169 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2170
2171 /* 8168B family. */
2172 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2173 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2174 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2175 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2176
2177 /* 8101 family. */
5598bfe5
HW		 2178 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2179 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2180 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2181 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2182 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2183 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2184 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2185 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2186 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2187 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2188 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2189 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2190 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2191 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2192 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2193 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2194 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2195 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2196 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2197 /* FIXME: where did these entries come from ? -- FR */
2198 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2199 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2200
2201 /* 8110 family. */
2202 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2203 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2204 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2205 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2206 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2207 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2208
f21b75e9
JD		 2209 /* Catch-all */
2210 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2211 };
2212 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2213 u32 reg;
2214
e3cf0cc0
FR		 2215 reg = RTL_R32(TxConfig);
2216 while ((reg & p->mask) != p->val)
1da177e4
LT		 2217 p++;
2218 tp->mac_version = p->mac_version;
5d320a20
FR		 2219
2220 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2221 netif_notice(tp, probe, dev,
2222 "unknown MAC, using family default\n");
2223 tp->mac_version = default_version;
58152cd4 2224 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2225 tp->mac_version = tp->mii.supports_gmii ?
2226 RTL_GIGA_MAC_VER_42 :
2227 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2228 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2229 tp->mac_version = tp->mii.supports_gmii ?
2230 RTL_GIGA_MAC_VER_45 :
2231 RTL_GIGA_MAC_VER_47;
2232 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2233 tp->mac_version = tp->mii.supports_gmii ?
2234 RTL_GIGA_MAC_VER_46 :
2235 RTL_GIGA_MAC_VER_48;
5d320a20 2236 }
1da177e4
LT		 2237}
2238
2239static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2240{
bcf0bf90 2241 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2242}
2243
867763c1
FR		 2244struct phy_reg {
2245 u16 reg;
2246 u16 val;
2247};
2248
4da19633 2249static void rtl_writephy_batch(struct rtl8169_private *tp,
2250 const struct phy_reg *regs, int len)
867763c1
FR		 2251{
2252 while (len-- > 0) {
4da19633 2253 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2254 regs++;
2255 }
2256}
2257
bca03d5f 2258#define PHY_READ 0x00000000
2259#define PHY_DATA_OR 0x10000000
2260#define PHY_DATA_AND 0x20000000
2261#define PHY_BJMPN 0x30000000
eee3786f 2262#define PHY_MDIO_CHG 0x40000000
bca03d5f 2263#define PHY_CLEAR_READCOUNT 0x70000000
2264#define PHY_WRITE 0x80000000
2265#define PHY_READCOUNT_EQ_SKIP 0x90000000
2266#define PHY_COMP_EQ_SKIPN 0xa0000000
2267#define PHY_COMP_NEQ_SKIPN 0xb0000000
2268#define PHY_WRITE_PREVIOUS 0xc0000000
2269#define PHY_SKIPN 0xd0000000
2270#define PHY_DELAY_MS 0xe0000000
bca03d5f 2271
960aee6c
HW		 2272struct fw_info {
2273 u32 magic;
2274 char version[RTL_VER_SIZE];
2275 __le32 fw_start;
2276 __le32 fw_len;
2277 u8 chksum;
2278} __packed;
2279
1c361efb
FR		 2280#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2281
2282static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2283{
b6ffd97f 2284 const struct firmware *fw = rtl_fw->fw;
960aee6c 2285 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2286 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2287 char *version = rtl_fw->version;
2288 bool rc = false;
2289
2290 if (fw->size < FW_OPCODE_SIZE)
2291 goto out;
960aee6c
HW		 2292
2293 if (!fw_info->magic) {
2294 size_t i, size, start;
2295 u8 checksum = 0;
2296
2297 if (fw->size < sizeof(*fw_info))
2298 goto out;
2299
2300 for (i = 0; i < fw->size; i++)
2301 checksum += fw->data[i];
2302 if (checksum != 0)
2303 goto out;
2304
2305 start = le32_to_cpu(fw_info->fw_start);
2306 if (start > fw->size)
2307 goto out;
2308
2309 size = le32_to_cpu(fw_info->fw_len);
2310 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2311 goto out;
2312
2313 memcpy(version, fw_info->version, RTL_VER_SIZE);
2314
2315 pa->code = (__le32 *)(fw->data + start);
2316 pa->size = size;
2317 } else {
1c361efb
FR		 2318 if (fw->size % FW_OPCODE_SIZE)
2319 goto out;
2320
2321 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2322
2323 pa->code = (__le32 *)fw->data;
2324 pa->size = fw->size / FW_OPCODE_SIZE;
2325 }
2326 version[RTL_VER_SIZE - 1] = 0;
2327
2328 rc = true;
2329out:
2330 return rc;
2331}
2332
fd112f2e
FR		 2333static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2334 struct rtl_fw_phy_action *pa)
1c361efb 2335{
fd112f2e 2336 bool rc = false;
1c361efb 2337 size_t index;
bca03d5f 2338
1c361efb
FR		 2339 for (index = 0; index < pa->size; index++) {
2340 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2341 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2342
42b82dc1 2343 switch(action & 0xf0000000) {
2344 case PHY_READ:
2345 case PHY_DATA_OR:
2346 case PHY_DATA_AND:
eee3786f 2347 case PHY_MDIO_CHG:
42b82dc1 2348 case PHY_CLEAR_READCOUNT:
2349 case PHY_WRITE:
2350 case PHY_WRITE_PREVIOUS:
2351 case PHY_DELAY_MS:
2352 break;
2353
2354 case PHY_BJMPN:
2355 if (regno > index) {
fd112f2e 2356 netif_err(tp, ifup, tp->dev,
cecb5fd7 2357 "Out of range of firmware\n");
fd112f2e 2358 goto out;
42b82dc1 2359 }
2360 break;
2361 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2362 if (index + 2 >= pa->size) {
fd112f2e 2363 netif_err(tp, ifup, tp->dev,
cecb5fd7 2364 "Out of range of firmware\n");
fd112f2e 2365 goto out;
42b82dc1 2366 }
2367 break;
2368 case PHY_COMP_EQ_SKIPN:
2369 case PHY_COMP_NEQ_SKIPN:
2370 case PHY_SKIPN:
1c361efb 2371 if (index + 1 + regno >= pa->size) {
fd112f2e 2372 netif_err(tp, ifup, tp->dev,
cecb5fd7 2373 "Out of range of firmware\n");
fd112f2e 2374 goto out;
42b82dc1 2375 }
bca03d5f 2376 break;
2377
42b82dc1 2378 default:
fd112f2e 2379 netif_err(tp, ifup, tp->dev,
42b82dc1 2380 "Invalid action 0x%08x\n", action);
fd112f2e 2381 goto out;
bca03d5f 2382 }
2383 }
fd112f2e
FR		 2384 rc = true;
2385out:
2386 return rc;
2387}
bca03d5f 2388
fd112f2e
FR		 2389static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2390{
2391 struct net_device *dev = tp->dev;
2392 int rc = -EINVAL;
2393
2394 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2395 netif_err(tp, ifup, dev, "invalid firwmare\n");
2396 goto out;
2397 }
2398
2399 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2400 rc = 0;
2401out:
2402 return rc;
2403}
2404
2405static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2406{
2407 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2408 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2409 u32 predata, count;
2410 size_t index;
2411
2412 predata = count = 0;
eee3786f 2413 org.write = ops->write;
2414 org.read = ops->read;
42b82dc1 2415
1c361efb
FR		 2416 for (index = 0; index < pa->size; ) {
2417 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2418 u32 data = action & 0x0000ffff;
42b82dc1 2419 u32 regno = (action & 0x0fff0000) >> 16;
2420
2421 if (!action)
2422 break;
bca03d5f 2423
2424 switch(action & 0xf0000000) {
42b82dc1 2425 case PHY_READ:
2426 predata = rtl_readphy(tp, regno);
2427 count++;
2428 index++;
2429 break;
2430 case PHY_DATA_OR:
2431 predata |= data;
2432 index++;
2433 break;
2434 case PHY_DATA_AND:
2435 predata &= data;
2436 index++;
2437 break;
2438 case PHY_BJMPN:
2439 index -= regno;
2440 break;
eee3786f 2441 case PHY_MDIO_CHG:
2442 if (data == 0) {
2443 ops->write = org.write;
2444 ops->read = org.read;
2445 } else if (data == 1) {
2446 ops->write = mac_mcu_write;
2447 ops->read = mac_mcu_read;
2448 }
2449
42b82dc1 2450 index++;
2451 break;
2452 case PHY_CLEAR_READCOUNT:
2453 count = 0;
2454 index++;
2455 break;
bca03d5f 2456 case PHY_WRITE:
42b82dc1 2457 rtl_writephy(tp, regno, data);
2458 index++;
2459 break;
2460 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2461 index += (count == data) ? 2 : 1;
bca03d5f 2462 break;
42b82dc1 2463 case PHY_COMP_EQ_SKIPN:
2464 if (predata == data)
2465 index += regno;
2466 index++;
2467 break;
2468 case PHY_COMP_NEQ_SKIPN:
2469 if (predata != data)
2470 index += regno;
2471 index++;
2472 break;
2473 case PHY_WRITE_PREVIOUS:
2474 rtl_writephy(tp, regno, predata);
2475 index++;
2476 break;
2477 case PHY_SKIPN:
2478 index += regno + 1;
2479 break;
2480 case PHY_DELAY_MS:
2481 mdelay(data);
2482 index++;
2483 break;
2484
bca03d5f 2485 default:
2486 BUG();
2487 }
2488 }
eee3786f 2489
2490 ops->write = org.write;
2491 ops->read = org.read;
bca03d5f 2492}
2493
f1e02ed1 2494static void rtl_release_firmware(struct rtl8169_private *tp)
2495{
b6ffd97f
FR		 2496 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2497 release_firmware(tp->rtl_fw->fw);
2498 kfree(tp->rtl_fw);
2499 }
2500 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2501}
2502
953a12cc 2503static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2504{
b6ffd97f 2505 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2506
2507 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2508 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2509 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2510}
2511
2512static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2513{
2514 if (rtl_readphy(tp, reg) != val)
2515 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2516 else
2517 rtl_apply_firmware(tp);
f1e02ed1 2518}
2519
4da19633 2520static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2521{
350f7596 2522 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2523 { 0x1f, 0x0001 },
2524 { 0x06, 0x006e },
2525 { 0x08, 0x0708 },
2526 { 0x15, 0x4000 },
2527 { 0x18, 0x65c7 },
1da177e4 2528
0b9b571d 2529 { 0x1f, 0x0001 },
2530 { 0x03, 0x00a1 },
2531 { 0x02, 0x0008 },
2532 { 0x01, 0x0120 },
2533 { 0x00, 0x1000 },
2534 { 0x04, 0x0800 },
2535 { 0x04, 0x0000 },
1da177e4 2536
0b9b571d 2537 { 0x03, 0xff41 },
2538 { 0x02, 0xdf60 },
2539 { 0x01, 0x0140 },
2540 { 0x00, 0x0077 },
2541 { 0x04, 0x7800 },
2542 { 0x04, 0x7000 },
2543
2544 { 0x03, 0x802f },
2545 { 0x02, 0x4f02 },
2546 { 0x01, 0x0409 },
2547 { 0x00, 0xf0f9 },
2548 { 0x04, 0x9800 },
2549 { 0x04, 0x9000 },
2550
2551 { 0x03, 0xdf01 },
2552 { 0x02, 0xdf20 },
2553 { 0x01, 0xff95 },
2554 { 0x00, 0xba00 },
2555 { 0x04, 0xa800 },
2556 { 0x04, 0xa000 },
2557
2558 { 0x03, 0xff41 },
2559 { 0x02, 0xdf20 },
2560 { 0x01, 0x0140 },
2561 { 0x00, 0x00bb },
2562 { 0x04, 0xb800 },
2563 { 0x04, 0xb000 },
2564
2565 { 0x03, 0xdf41 },
2566 { 0x02, 0xdc60 },
2567 { 0x01, 0x6340 },
2568 { 0x00, 0x007d },
2569 { 0x04, 0xd800 },
2570 { 0x04, 0xd000 },
2571
2572 { 0x03, 0xdf01 },
2573 { 0x02, 0xdf20 },
2574 { 0x01, 0x100a },
2575 { 0x00, 0xa0ff },
2576 { 0x04, 0xf800 },
2577 { 0x04, 0xf000 },
2578
2579 { 0x1f, 0x0000 },
2580 { 0x0b, 0x0000 },
2581 { 0x00, 0x9200 }
2582 };
1da177e4 2583
4da19633 2584 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2585}
2586
4da19633 2587static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2588{
350f7596 2589 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2590 { 0x1f, 0x0002 },
2591 { 0x01, 0x90d0 },
2592 { 0x1f, 0x0000 }
2593 };
2594
4da19633 2595 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2596}
2597
4da19633 2598static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2599{
2600 struct pci_dev *pdev = tp->pci_dev;
2e955856 2601
ccbae55e
SS		 2602 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2603 (pdev->subsystem_device != 0xe000))
2e955856 2604 return;
2605
4da19633 2606 rtl_writephy(tp, 0x1f, 0x0001);
2607 rtl_writephy(tp, 0x10, 0xf01b);
2608 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2609}
2610
4da19633 2611static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2612{
350f7596 2613 static const struct phy_reg phy_reg_init[] = {
2e955856 2614 { 0x1f, 0x0001 },
2615 { 0x04, 0x0000 },
2616 { 0x03, 0x00a1 },
2617 { 0x02, 0x0008 },
2618 { 0x01, 0x0120 },
2619 { 0x00, 0x1000 },
2620 { 0x04, 0x0800 },
2621 { 0x04, 0x9000 },
2622 { 0x03, 0x802f },
2623 { 0x02, 0x4f02 },
2624 { 0x01, 0x0409 },
2625 { 0x00, 0xf099 },
2626 { 0x04, 0x9800 },
2627 { 0x04, 0xa000 },
2628 { 0x03, 0xdf01 },
2629 { 0x02, 0xdf20 },
2630 { 0x01, 0xff95 },
2631 { 0x00, 0xba00 },
2632 { 0x04, 0xa800 },
2633 { 0x04, 0xf000 },
2634 { 0x03, 0xdf01 },
2635 { 0x02, 0xdf20 },
2636 { 0x01, 0x101a },
2637 { 0x00, 0xa0ff },
2638 { 0x04, 0xf800 },
2639 { 0x04, 0x0000 },
2640 { 0x1f, 0x0000 },
2641
2642 { 0x1f, 0x0001 },
2643 { 0x10, 0xf41b },
2644 { 0x14, 0xfb54 },
2645 { 0x18, 0xf5c7 },
2646 { 0x1f, 0x0000 },
2647
2648 { 0x1f, 0x0001 },
2649 { 0x17, 0x0cc0 },
2650 { 0x1f, 0x0000 }
2651 };
2652
4da19633 2653 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2654
4da19633 2655 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2656}
2657
4da19633 2658static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2659{
350f7596 2660 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2661 { 0x1f, 0x0001 },
2662 { 0x04, 0x0000 },
2663 { 0x03, 0x00a1 },
2664 { 0x02, 0x0008 },
2665 { 0x01, 0x0120 },
2666 { 0x00, 0x1000 },
2667 { 0x04, 0x0800 },
2668 { 0x04, 0x9000 },
2669 { 0x03, 0x802f },
2670 { 0x02, 0x4f02 },
2671 { 0x01, 0x0409 },
2672 { 0x00, 0xf099 },
2673 { 0x04, 0x9800 },
2674 { 0x04, 0xa000 },
2675 { 0x03, 0xdf01 },
2676 { 0x02, 0xdf20 },
2677 { 0x01, 0xff95 },
2678 { 0x00, 0xba00 },
2679 { 0x04, 0xa800 },
2680 { 0x04, 0xf000 },
2681 { 0x03, 0xdf01 },
2682 { 0x02, 0xdf20 },
2683 { 0x01, 0x101a },
2684 { 0x00, 0xa0ff },
2685 { 0x04, 0xf800 },
2686 { 0x04, 0x0000 },
2687 { 0x1f, 0x0000 },
2688
2689 { 0x1f, 0x0001 },
2690 { 0x0b, 0x8480 },
2691 { 0x1f, 0x0000 },
2692
2693 { 0x1f, 0x0001 },
2694 { 0x18, 0x67c7 },
2695 { 0x04, 0x2000 },
2696 { 0x03, 0x002f },
2697 { 0x02, 0x4360 },
2698 { 0x01, 0x0109 },
2699 { 0x00, 0x3022 },
2700 { 0x04, 0x2800 },
2701 { 0x1f, 0x0000 },
2702
2703 { 0x1f, 0x0001 },
2704 { 0x17, 0x0cc0 },
2705 { 0x1f, 0x0000 }
2706 };
2707
4da19633 2708 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2709}
2710
4da19633 2711static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2712{
350f7596 2713 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2714 { 0x10, 0xf41b },
2715 { 0x1f, 0x0000 }
2716 };
2717
4da19633 2718 rtl_writephy(tp, 0x1f, 0x0001);
2719 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2720
4da19633 2721 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2722}
2723
4da19633 2724static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2725{
350f7596 2726 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2727 { 0x1f, 0x0001 },
2728 { 0x10, 0xf41b },
2729 { 0x1f, 0x0000 }
2730 };
2731
4da19633 2732 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2733}
2734
4da19633 2735static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2736{
350f7596 2737 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2738 { 0x1f, 0x0000 },
2739 { 0x1d, 0x0f00 },
2740 { 0x1f, 0x0002 },
2741 { 0x0c, 0x1ec8 },
2742 { 0x1f, 0x0000 }
2743 };
2744
4da19633 2745 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2746}
2747
4da19633 2748static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2749{
350f7596 2750 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2751 { 0x1f, 0x0001 },
2752 { 0x1d, 0x3d98 },
2753 { 0x1f, 0x0000 }
2754 };
2755
4da19633 2756 rtl_writephy(tp, 0x1f, 0x0000);
2757 rtl_patchphy(tp, 0x14, 1 << 5);
2758 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2759
4da19633 2760 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2761}
2762
4da19633 2763static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2764{
350f7596 2765 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2766 { 0x1f, 0x0001 },
2767 { 0x12, 0x2300 },
867763c1
FR		 2768 { 0x1f, 0x0002 },
2769 { 0x00, 0x88d4 },
2770 { 0x01, 0x82b1 },
2771 { 0x03, 0x7002 },
2772 { 0x08, 0x9e30 },
2773 { 0x09, 0x01f0 },
2774 { 0x0a, 0x5500 },
2775 { 0x0c, 0x00c8 },
2776 { 0x1f, 0x0003 },
2777 { 0x12, 0xc096 },
2778 { 0x16, 0x000a },
f50d4275
FR		 2779 { 0x1f, 0x0000 },
2780 { 0x1f, 0x0000 },
2781 { 0x09, 0x2000 },
2782 { 0x09, 0x0000 }
867763c1
FR		 2783 };
2784
4da19633 2785 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2786
4da19633 2787 rtl_patchphy(tp, 0x14, 1 << 5);
2788 rtl_patchphy(tp, 0x0d, 1 << 5);
2789 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2790}
2791
4da19633 2792static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2793{
350f7596 2794 static const struct phy_reg phy_reg_init[] = {
f50d4275 2795 { 0x1f, 0x0001 },
7da97ec9 2796 { 0x12, 0x2300 },
f50d4275
FR		 2797 { 0x03, 0x802f },
2798 { 0x02, 0x4f02 },
2799 { 0x01, 0x0409 },
2800 { 0x00, 0xf099 },
2801 { 0x04, 0x9800 },
2802 { 0x04, 0x9000 },
2803 { 0x1d, 0x3d98 },
7da97ec9
FR		 2804 { 0x1f, 0x0002 },
2805 { 0x0c, 0x7eb8 },
f50d4275
FR		 2806 { 0x06, 0x0761 },
2807 { 0x1f, 0x0003 },
2808 { 0x16, 0x0f0a },
7da97ec9
FR		 2809 { 0x1f, 0x0000 }
2810 };
2811
4da19633 2812 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2813
4da19633 2814 rtl_patchphy(tp, 0x16, 1 << 0);
2815 rtl_patchphy(tp, 0x14, 1 << 5);
2816 rtl_patchphy(tp, 0x0d, 1 << 5);
2817 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2818}
2819
4da19633 2820static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2821{
350f7596 2822 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2823 { 0x1f, 0x0001 },
2824 { 0x12, 0x2300 },
2825 { 0x1d, 0x3d98 },
2826 { 0x1f, 0x0002 },
2827 { 0x0c, 0x7eb8 },
2828 { 0x06, 0x5461 },
2829 { 0x1f, 0x0003 },
2830 { 0x16, 0x0f0a },
2831 { 0x1f, 0x0000 }
2832 };
2833
4da19633 2834 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2835
4da19633 2836 rtl_patchphy(tp, 0x16, 1 << 0);
2837 rtl_patchphy(tp, 0x14, 1 << 5);
2838 rtl_patchphy(tp, 0x0d, 1 << 5);
2839 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2840}
2841
4da19633 2842static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2843{
4da19633 2844 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2845}
2846
bca03d5f 2847static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2848{
350f7596 2849 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2850 /* Channel Estimation */
5b538df9 2851 { 0x1f, 0x0001 },
daf9df6d 2852 { 0x06, 0x4064 },
2853 { 0x07, 0x2863 },
2854 { 0x08, 0x059c },
2855 { 0x09, 0x26b4 },
2856 { 0x0a, 0x6a19 },
2857 { 0x0b, 0xdcc8 },
2858 { 0x10, 0xf06d },
2859 { 0x14, 0x7f68 },
2860 { 0x18, 0x7fd9 },
2861 { 0x1c, 0xf0ff },
2862 { 0x1d, 0x3d9c },
5b538df9 2863 { 0x1f, 0x0003 },
daf9df6d 2864 { 0x12, 0xf49f },
2865 { 0x13, 0x070b },
2866 { 0x1a, 0x05ad },
bca03d5f 2867 { 0x14, 0x94c0 },
2868
2869 /*
2870 * Tx Error Issue
cecb5fd7 2871 * Enhance line driver power
bca03d5f 2872 */
5b538df9 2873 { 0x1f, 0x0002 },
daf9df6d 2874 { 0x06, 0x5561 },
2875 { 0x1f, 0x0005 },
2876 { 0x05, 0x8332 },
bca03d5f 2877 { 0x06, 0x5561 },
2878
2879 /*
2880 * Can not link to 1Gbps with bad cable
2881 * Decrease SNR threshold form 21.07dB to 19.04dB
2882 */
2883 { 0x1f, 0x0001 },
2884 { 0x17, 0x0cc0 },
daf9df6d 2885
5b538df9 2886 { 0x1f, 0x0000 },
bca03d5f 2887 { 0x0d, 0xf880 }
daf9df6d 2888 };
2889
4da19633 2890 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2891
bca03d5f 2892 /*
2893 * Rx Error Issue
2894 * Fine Tune Switching regulator parameter
2895 */
4da19633 2896 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2897 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2898 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2899
fdf6fc06 2900 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2901 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2902 { 0x1f, 0x0002 },
2903 { 0x05, 0x669a },
2904 { 0x1f, 0x0005 },
2905 { 0x05, 0x8330 },
2906 { 0x06, 0x669a },
2907 { 0x1f, 0x0002 }
2908 };
2909 int val;
2910
4da19633 2911 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2912
4da19633 2913 val = rtl_readphy(tp, 0x0d);
daf9df6d 2914
2915 if ((val & 0x00ff) != 0x006c) {
350f7596 2916 static const u32 set[] = {
daf9df6d 2917 0x0065, 0x0066, 0x0067, 0x0068,
2918 0x0069, 0x006a, 0x006b, 0x006c
2919 };
2920 int i;
2921
4da19633 2922 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2923
2924 val &= 0xff00;
2925 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2926 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2927 }
2928 } else {
350f7596 2929 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2930 { 0x1f, 0x0002 },
2931 { 0x05, 0x6662 },
2932 { 0x1f, 0x0005 },
2933 { 0x05, 0x8330 },
2934 { 0x06, 0x6662 }
2935 };
2936
4da19633 2937 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2938 }
2939
bca03d5f 2940 /* RSET couple improve */
4da19633 2941 rtl_writephy(tp, 0x1f, 0x0002);
2942 rtl_patchphy(tp, 0x0d, 0x0300);
2943 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2944
bca03d5f 2945 /* Fine tune PLL performance */
4da19633 2946 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2947 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2948 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2949
4da19633 2950 rtl_writephy(tp, 0x1f, 0x0005);
2951 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2952
2953 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2954
4da19633 2955 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2956}
2957
bca03d5f 2958static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2959{
350f7596 2960 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2961 /* Channel Estimation */
daf9df6d 2962 { 0x1f, 0x0001 },
2963 { 0x06, 0x4064 },
2964 { 0x07, 0x2863 },
2965 { 0x08, 0x059c },
2966 { 0x09, 0x26b4 },
2967 { 0x0a, 0x6a19 },
2968 { 0x0b, 0xdcc8 },
2969 { 0x10, 0xf06d },
2970 { 0x14, 0x7f68 },
2971 { 0x18, 0x7fd9 },
2972 { 0x1c, 0xf0ff },
2973 { 0x1d, 0x3d9c },
2974 { 0x1f, 0x0003 },
2975 { 0x12, 0xf49f },
2976 { 0x13, 0x070b },
2977 { 0x1a, 0x05ad },
2978 { 0x14, 0x94c0 },
2979
bca03d5f 2980 /*
2981 * Tx Error Issue
cecb5fd7 2982 * Enhance line driver power
bca03d5f 2983 */
daf9df6d 2984 { 0x1f, 0x0002 },
2985 { 0x06, 0x5561 },
2986 { 0x1f, 0x0005 },
2987 { 0x05, 0x8332 },
bca03d5f 2988 { 0x06, 0x5561 },
2989
2990 /*
2991 * Can not link to 1Gbps with bad cable
2992 * Decrease SNR threshold form 21.07dB to 19.04dB
2993 */
2994 { 0x1f, 0x0001 },
2995 { 0x17, 0x0cc0 },
daf9df6d 2996
2997 { 0x1f, 0x0000 },
bca03d5f 2998 { 0x0d, 0xf880 }
5b538df9
FR		 2999 };
3000
4da19633 3001 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3002
fdf6fc06 3003 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3004 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3005 { 0x1f, 0x0002 },
3006 { 0x05, 0x669a },
5b538df9 3007 { 0x1f, 0x0005 },
daf9df6d 3008 { 0x05, 0x8330 },
3009 { 0x06, 0x669a },
3010
3011 { 0x1f, 0x0002 }
3012 };
3013 int val;
3014
4da19633 3015 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3016
4da19633 3017 val = rtl_readphy(tp, 0x0d);
daf9df6d 3018 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3019 static const u32 set[] = {
daf9df6d 3020 0x0065, 0x0066, 0x0067, 0x0068,
3021 0x0069, 0x006a, 0x006b, 0x006c
3022 };
3023 int i;
3024
4da19633 3025 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3026
3027 val &= 0xff00;
3028 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3029 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3030 }
3031 } else {
350f7596 3032 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3033 { 0x1f, 0x0002 },
3034 { 0x05, 0x2642 },
5b538df9 3035 { 0x1f, 0x0005 },
daf9df6d 3036 { 0x05, 0x8330 },
3037 { 0x06, 0x2642 }
5b538df9
FR		 3038 };
3039
4da19633 3040 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3041 }
3042
bca03d5f 3043 /* Fine tune PLL performance */
4da19633 3044 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3045 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3046 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3047
bca03d5f 3048 /* Switching regulator Slew rate */
4da19633 3049 rtl_writephy(tp, 0x1f, 0x0002);
3050 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3051
4da19633 3052 rtl_writephy(tp, 0x1f, 0x0005);
3053 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3054
3055 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3056
4da19633 3057 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3058}
3059
4da19633 3060static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3061{
350f7596 3062 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3063 { 0x1f, 0x0002 },
3064 { 0x10, 0x0008 },
3065 { 0x0d, 0x006c },
3066
3067 { 0x1f, 0x0000 },
3068 { 0x0d, 0xf880 },
3069
3070 { 0x1f, 0x0001 },
3071 { 0x17, 0x0cc0 },
3072
3073 { 0x1f, 0x0001 },
3074 { 0x0b, 0xa4d8 },
3075 { 0x09, 0x281c },
3076 { 0x07, 0x2883 },
3077 { 0x0a, 0x6b35 },
3078 { 0x1d, 0x3da4 },
3079 { 0x1c, 0xeffd },
3080 { 0x14, 0x7f52 },
3081 { 0x18, 0x7fc6 },
3082 { 0x08, 0x0601 },
3083 { 0x06, 0x4063 },
3084 { 0x10, 0xf074 },
3085 { 0x1f, 0x0003 },
3086 { 0x13, 0x0789 },
3087 { 0x12, 0xf4bd },
3088 { 0x1a, 0x04fd },
3089 { 0x14, 0x84b0 },
3090 { 0x1f, 0x0000 },
3091 { 0x00, 0x9200 },
3092
3093 { 0x1f, 0x0005 },
3094 { 0x01, 0x0340 },
3095 { 0x1f, 0x0001 },
3096 { 0x04, 0x4000 },
3097 { 0x03, 0x1d21 },
3098 { 0x02, 0x0c32 },
3099 { 0x01, 0x0200 },
3100 { 0x00, 0x5554 },
3101 { 0x04, 0x4800 },
3102 { 0x04, 0x4000 },
3103 { 0x04, 0xf000 },
3104 { 0x03, 0xdf01 },
3105 { 0x02, 0xdf20 },
3106 { 0x01, 0x101a },
3107 { 0x00, 0xa0ff },
3108 { 0x04, 0xf800 },
3109 { 0x04, 0xf000 },
3110 { 0x1f, 0x0000 },
3111
3112 { 0x1f, 0x0007 },
3113 { 0x1e, 0x0023 },
3114 { 0x16, 0x0000 },
3115 { 0x1f, 0x0000 }
3116 };
3117
4da19633 3118 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3119}
3120
e6de30d6 3121static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3122{
3123 static const struct phy_reg phy_reg_init[] = {
3124 { 0x1f, 0x0001 },
3125 { 0x17, 0x0cc0 },
3126
3127 { 0x1f, 0x0007 },
3128 { 0x1e, 0x002d },
3129 { 0x18, 0x0040 },
3130 { 0x1f, 0x0000 }
3131 };
3132
3133 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3134 rtl_patchphy(tp, 0x0d, 1 << 5);
3135}
3136
70090424 3137static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3138{
3139 static const struct phy_reg phy_reg_init[] = {
3140 /* Enable Delay cap */
3141 { 0x1f, 0x0005 },
3142 { 0x05, 0x8b80 },
3143 { 0x06, 0xc896 },
3144 { 0x1f, 0x0000 },
3145
3146 /* Channel estimation fine tune */
3147 { 0x1f, 0x0001 },
3148 { 0x0b, 0x6c20 },
3149 { 0x07, 0x2872 },
3150 { 0x1c, 0xefff },
3151 { 0x1f, 0x0003 },
3152 { 0x14, 0x6420 },
3153 { 0x1f, 0x0000 },
3154
3155 /* Update PFM & 10M TX idle timer */
3156 { 0x1f, 0x0007 },
3157 { 0x1e, 0x002f },
3158 { 0x15, 0x1919 },
3159 { 0x1f, 0x0000 },
3160
3161 { 0x1f, 0x0007 },
3162 { 0x1e, 0x00ac },
3163 { 0x18, 0x0006 },
3164 { 0x1f, 0x0000 }
3165 };
3166
15ecd039
FR		 3167 rtl_apply_firmware(tp);
3168
01dc7fec 3169 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3170
3171 /* DCO enable for 10M IDLE Power */
3172 rtl_writephy(tp, 0x1f, 0x0007);
3173 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3174 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3175 rtl_writephy(tp, 0x1f, 0x0000);
3176
3177 /* For impedance matching */
3178 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3179 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3180 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3181
3182 /* PHY auto speed down */
3183 rtl_writephy(tp, 0x1f, 0x0007);
3184 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3185 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3186 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3187 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3188
3189 rtl_writephy(tp, 0x1f, 0x0005);
3190 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3191 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3192 rtl_writephy(tp, 0x1f, 0x0000);
3193
3194 rtl_writephy(tp, 0x1f, 0x0005);
3195 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3196 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3197 rtl_writephy(tp, 0x1f, 0x0007);
3198 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3199 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3200 rtl_writephy(tp, 0x1f, 0x0006);
3201 rtl_writephy(tp, 0x00, 0x5a00);
3202 rtl_writephy(tp, 0x1f, 0x0000);
3203 rtl_writephy(tp, 0x0d, 0x0007);
3204 rtl_writephy(tp, 0x0e, 0x003c);
3205 rtl_writephy(tp, 0x0d, 0x4007);
3206 rtl_writephy(tp, 0x0e, 0x0000);
3207 rtl_writephy(tp, 0x0d, 0x0000);
3208}
3209
9ecb9aab 3210static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3211{
3212 const u16 w[] = {
3213 addr[0] | (addr[1] << 8),
3214 addr[2] | (addr[3] << 8),
3215 addr[4] | (addr[5] << 8)
3216 };
3217 const struct exgmac_reg e[] = {
3218 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3219 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3220 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3221 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3222 };
3223
3224 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3225}
3226
70090424
HW		 3227static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3228{
3229 static const struct phy_reg phy_reg_init[] = {
3230 /* Enable Delay cap */
3231 { 0x1f, 0x0004 },
3232 { 0x1f, 0x0007 },
3233 { 0x1e, 0x00ac },
3234 { 0x18, 0x0006 },
3235 { 0x1f, 0x0002 },
3236 { 0x1f, 0x0000 },
3237 { 0x1f, 0x0000 },
3238
3239 /* Channel estimation fine tune */
3240 { 0x1f, 0x0003 },
3241 { 0x09, 0xa20f },
3242 { 0x1f, 0x0000 },
3243 { 0x1f, 0x0000 },
3244
3245 /* Green Setting */
3246 { 0x1f, 0x0005 },
3247 { 0x05, 0x8b5b },
3248 { 0x06, 0x9222 },
3249 { 0x05, 0x8b6d },
3250 { 0x06, 0x8000 },
3251 { 0x05, 0x8b76 },
3252 { 0x06, 0x8000 },
3253 { 0x1f, 0x0000 }
3254 };
3255
3256 rtl_apply_firmware(tp);
3257
3258 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3259
3260 /* For 4-corner performance improve */
3261 rtl_writephy(tp, 0x1f, 0x0005);
3262 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3263 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3264 rtl_writephy(tp, 0x1f, 0x0000);
3265
3266 /* PHY auto speed down */
3267 rtl_writephy(tp, 0x1f, 0x0004);
3268 rtl_writephy(tp, 0x1f, 0x0007);
3269 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3270 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3271 rtl_writephy(tp, 0x1f, 0x0002);
3272 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3273 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3274
3275 /* improve 10M EEE waveform */
3276 rtl_writephy(tp, 0x1f, 0x0005);
3277 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3278 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3279 rtl_writephy(tp, 0x1f, 0x0000);
3280
3281 /* Improve 2-pair detection performance */
3282 rtl_writephy(tp, 0x1f, 0x0005);
3283 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3284 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3285 rtl_writephy(tp, 0x1f, 0x0000);
3286
3287 /* EEE setting */
706123d0 3288 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3289 rtl_writephy(tp, 0x1f, 0x0005);
3290 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3291 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
70090424
HW		 3292 rtl_writephy(tp, 0x1f, 0x0004);
3293 rtl_writephy(tp, 0x1f, 0x0007);
3294 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3295 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3296 rtl_writephy(tp, 0x1f, 0x0002);
3297 rtl_writephy(tp, 0x1f, 0x0000);
3298 rtl_writephy(tp, 0x0d, 0x0007);
3299 rtl_writephy(tp, 0x0e, 0x003c);
3300 rtl_writephy(tp, 0x0d, 0x4007);
3301 rtl_writephy(tp, 0x0e, 0x0000);
3302 rtl_writephy(tp, 0x0d, 0x0000);
3303
3304 /* Green feature */
3305 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3306 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3307 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
70090424 3308 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3309
9ecb9aab 3310 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3311 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3312}
3313
5f886e08
HW		 3314static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3315{
3316 /* For 4-corner performance improve */
3317 rtl_writephy(tp, 0x1f, 0x0005);
3318 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3319 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3320 rtl_writephy(tp, 0x1f, 0x0000);
3321
3322 /* PHY auto speed down */
3323 rtl_writephy(tp, 0x1f, 0x0007);
3324 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3325 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3326 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3327 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3328
3329 /* Improve 10M EEE waveform */
3330 rtl_writephy(tp, 0x1f, 0x0005);
3331 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3332 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3333 rtl_writephy(tp, 0x1f, 0x0000);
3334}
3335
c2218925
HW		 3336static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3337{
3338 static const struct phy_reg phy_reg_init[] = {
3339 /* Channel estimation fine tune */
3340 { 0x1f, 0x0003 },
3341 { 0x09, 0xa20f },
3342 { 0x1f, 0x0000 },
3343
3344 /* Modify green table for giga & fnet */
3345 { 0x1f, 0x0005 },
3346 { 0x05, 0x8b55 },
3347 { 0x06, 0x0000 },
3348 { 0x05, 0x8b5e },
3349 { 0x06, 0x0000 },
3350 { 0x05, 0x8b67 },
3351 { 0x06, 0x0000 },
3352 { 0x05, 0x8b70 },
3353 { 0x06, 0x0000 },
3354 { 0x1f, 0x0000 },
3355 { 0x1f, 0x0007 },
3356 { 0x1e, 0x0078 },
3357 { 0x17, 0x0000 },
3358 { 0x19, 0x00fb },
3359 { 0x1f, 0x0000 },
3360
3361 /* Modify green table for 10M */
3362 { 0x1f, 0x0005 },
3363 { 0x05, 0x8b79 },
3364 { 0x06, 0xaa00 },
3365 { 0x1f, 0x0000 },
3366
3367 /* Disable hiimpedance detection (RTCT) */
3368 { 0x1f, 0x0003 },
3369 { 0x01, 0x328a },
3370 { 0x1f, 0x0000 }
3371 };
3372
3373 rtl_apply_firmware(tp);
3374
3375 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3376
5f886e08 3377 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3378
3379 /* Improve 2-pair detection performance */
3380 rtl_writephy(tp, 0x1f, 0x0005);
3381 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3382 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3383 rtl_writephy(tp, 0x1f, 0x0000);
3384}
3385
3386static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3387{
3388 rtl_apply_firmware(tp);
3389
5f886e08 3390 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3391}
3392
b3d7b2f2
HW		 3393static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3394{
b3d7b2f2
HW		 3395 static const struct phy_reg phy_reg_init[] = {
3396 /* Channel estimation fine tune */
3397 { 0x1f, 0x0003 },
3398 { 0x09, 0xa20f },
3399 { 0x1f, 0x0000 },
3400
3401 /* Modify green table for giga & fnet */
3402 { 0x1f, 0x0005 },
3403 { 0x05, 0x8b55 },
3404 { 0x06, 0x0000 },
3405 { 0x05, 0x8b5e },
3406 { 0x06, 0x0000 },
3407 { 0x05, 0x8b67 },
3408 { 0x06, 0x0000 },
3409 { 0x05, 0x8b70 },
3410 { 0x06, 0x0000 },
3411 { 0x1f, 0x0000 },
3412 { 0x1f, 0x0007 },
3413 { 0x1e, 0x0078 },
3414 { 0x17, 0x0000 },
3415 { 0x19, 0x00aa },
3416 { 0x1f, 0x0000 },
3417
3418 /* Modify green table for 10M */
3419 { 0x1f, 0x0005 },
3420 { 0x05, 0x8b79 },
3421 { 0x06, 0xaa00 },
3422 { 0x1f, 0x0000 },
3423
3424 /* Disable hiimpedance detection (RTCT) */
3425 { 0x1f, 0x0003 },
3426 { 0x01, 0x328a },
3427 { 0x1f, 0x0000 }
3428 };
3429
3430
3431 rtl_apply_firmware(tp);
3432
3433 rtl8168f_hw_phy_config(tp);
3434
3435 /* Improve 2-pair detection performance */
3436 rtl_writephy(tp, 0x1f, 0x0005);
3437 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3438 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3439 rtl_writephy(tp, 0x1f, 0x0000);
3440
3441 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3442
3443 /* Modify green table for giga */
3444 rtl_writephy(tp, 0x1f, 0x0005);
3445 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3446 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3447 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3448 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3449 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3450 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3451 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3452 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3453 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3454 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3455 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3456 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3457 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3458 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3459 rtl_writephy(tp, 0x1f, 0x0000);
3460
3461 /* uc same-seed solution */
3462 rtl_writephy(tp, 0x1f, 0x0005);
3463 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3464 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3465 rtl_writephy(tp, 0x1f, 0x0000);
3466
3467 /* eee setting */
706123d0 3468 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3469 rtl_writephy(tp, 0x1f, 0x0005);
3470 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3471 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3472 rtl_writephy(tp, 0x1f, 0x0004);
3473 rtl_writephy(tp, 0x1f, 0x0007);
3474 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3475 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3476 rtl_writephy(tp, 0x1f, 0x0000);
3477 rtl_writephy(tp, 0x0d, 0x0007);
3478 rtl_writephy(tp, 0x0e, 0x003c);
3479 rtl_writephy(tp, 0x0d, 0x4007);
3480 rtl_writephy(tp, 0x0e, 0x0000);
3481 rtl_writephy(tp, 0x0d, 0x0000);
3482
3483 /* Green feature */
3484 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3485 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3486 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3487 rtl_writephy(tp, 0x1f, 0x0000);
3488}
3489
c558386b
HW		 3490static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3491{
c558386b
HW		 3492 rtl_apply_firmware(tp);
3493
41f44d13 3494 rtl_writephy(tp, 0x1f, 0x0a46);
3495 if (rtl_readphy(tp, 0x10) & 0x0100) {
3496 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3497 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3498 } else {
3499 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3500 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3501 }
c558386b 3502
41f44d13 3503 rtl_writephy(tp, 0x1f, 0x0a46);
3504 if (rtl_readphy(tp, 0x13) & 0x0100) {
3505 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3506 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3507 } else {
fe7524c0 3508 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3509 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3510 }
c558386b 3511
41f44d13 3512 /* Enable PHY auto speed down */
3513 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3514 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3515
fe7524c0 3516 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3517 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3518 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3519 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3520 rtl_writephy(tp, 0x1f, 0x0a43);
3521 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3522 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3523 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3524
41f44d13 3525 /* EEE auto-fallback function */
3526 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3527 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3528
41f44d13 3529 /* Enable UC LPF tune function */
3530 rtl_writephy(tp, 0x1f, 0x0a43);
3531 rtl_writephy(tp, 0x13, 0x8012);
76564428 3532 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3533
3534 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3535 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3536
fe7524c0 3537 /* Improve SWR Efficiency */
3538 rtl_writephy(tp, 0x1f, 0x0bcd);
3539 rtl_writephy(tp, 0x14, 0x5065);
3540 rtl_writephy(tp, 0x14, 0xd065);
3541 rtl_writephy(tp, 0x1f, 0x0bc8);
3542 rtl_writephy(tp, 0x11, 0x5655);
3543 rtl_writephy(tp, 0x1f, 0x0bcd);
3544 rtl_writephy(tp, 0x14, 0x1065);
3545 rtl_writephy(tp, 0x14, 0x9065);
3546 rtl_writephy(tp, 0x14, 0x1065);
3547
1bac1072
DC		 3548 /* Check ALDPS bit, disable it if enabled */
3549 rtl_writephy(tp, 0x1f, 0x0a43);
3550 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3551 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3552
41f44d13 3553 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3554}
3555
57538c4a 3556static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3557{
3558 rtl_apply_firmware(tp);
3559}
3560
6e1d0b89
CHL		 3561static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3562{
3563 u16 dout_tapbin;
3564 u32 data;
3565
3566 rtl_apply_firmware(tp);
3567
3568 /* CHN EST parameters adjust - giga master */
3569 rtl_writephy(tp, 0x1f, 0x0a43);
3570 rtl_writephy(tp, 0x13, 0x809b);
76564428 3571 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3572 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3573 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3574 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3575 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3576 rtl_writephy(tp, 0x13, 0x809c);
76564428 3577 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3578 rtl_writephy(tp, 0x1f, 0x0000);
3579
3580 /* CHN EST parameters adjust - giga slave */
3581 rtl_writephy(tp, 0x1f, 0x0a43);
3582 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3583 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3584 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3585 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3586 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3587 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3588 rtl_writephy(tp, 0x1f, 0x0000);
3589
3590 /* CHN EST parameters adjust - fnet */
3591 rtl_writephy(tp, 0x1f, 0x0a43);
3592 rtl_writephy(tp, 0x13, 0x808e);
76564428 3593 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3594 rtl_writephy(tp, 0x13, 0x8090);
76564428 3595 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3596 rtl_writephy(tp, 0x13, 0x8092);
76564428 3597 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3598 rtl_writephy(tp, 0x1f, 0x0000);
3599
3600 /* enable R-tune & PGA-retune function */
3601 dout_tapbin = 0;
3602 rtl_writephy(tp, 0x1f, 0x0a46);
3603 data = rtl_readphy(tp, 0x13);
3604 data &= 3;
3605 data <<= 2;
3606 dout_tapbin |= data;
3607 data = rtl_readphy(tp, 0x12);
3608 data &= 0xc000;
3609 data >>= 14;
3610 dout_tapbin |= data;
3611 dout_tapbin = ~(dout_tapbin^0x08);
3612 dout_tapbin <<= 12;
3613 dout_tapbin &= 0xf000;
3614 rtl_writephy(tp, 0x1f, 0x0a43);
3615 rtl_writephy(tp, 0x13, 0x827a);
76564428 3616 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3617 rtl_writephy(tp, 0x13, 0x827b);
76564428 3618 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3619 rtl_writephy(tp, 0x13, 0x827c);
76564428 3620 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3621 rtl_writephy(tp, 0x13, 0x827d);
76564428 3622 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3623
3624 rtl_writephy(tp, 0x1f, 0x0a43);
3625 rtl_writephy(tp, 0x13, 0x0811);
76564428 3626 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3627 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3628 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3629 rtl_writephy(tp, 0x1f, 0x0000);
3630
3631 /* enable GPHY 10M */
3632 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3633 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3634 rtl_writephy(tp, 0x1f, 0x0000);
3635
3636 /* SAR ADC performance */
3637 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3638 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3639 rtl_writephy(tp, 0x1f, 0x0000);
3640
3641 rtl_writephy(tp, 0x1f, 0x0a43);
3642 rtl_writephy(tp, 0x13, 0x803f);
76564428 3643 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3644 rtl_writephy(tp, 0x13, 0x8047);
76564428 3645 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3646 rtl_writephy(tp, 0x13, 0x804f);
76564428 3647 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3648 rtl_writephy(tp, 0x13, 0x8057);
76564428 3649 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3650 rtl_writephy(tp, 0x13, 0x805f);
76564428 3651 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3652 rtl_writephy(tp, 0x13, 0x8067);
76564428 3653 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3654 rtl_writephy(tp, 0x13, 0x806f);
76564428 3655 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3656 rtl_writephy(tp, 0x1f, 0x0000);
3657
3658 /* disable phy pfm mode */
3659 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3660 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
6e1d0b89
CHL		 3661 rtl_writephy(tp, 0x1f, 0x0000);
3662
3663 /* Check ALDPS bit, disable it if enabled */
3664 rtl_writephy(tp, 0x1f, 0x0a43);
3665 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3666 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3667
3668 rtl_writephy(tp, 0x1f, 0x0000);
3669}
3670
3671static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3672{
3673 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3674 u16 rlen;
3675 u32 data;
3676
3677 rtl_apply_firmware(tp);
3678
3679 /* CHIN EST parameter update */
3680 rtl_writephy(tp, 0x1f, 0x0a43);
3681 rtl_writephy(tp, 0x13, 0x808a);
76564428 3682 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3683 rtl_writephy(tp, 0x1f, 0x0000);
3684
3685 /* enable R-tune & PGA-retune function */
3686 rtl_writephy(tp, 0x1f, 0x0a43);
3687 rtl_writephy(tp, 0x13, 0x0811);
76564428 3688 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3689 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3690 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3691 rtl_writephy(tp, 0x1f, 0x0000);
3692
3693 /* enable GPHY 10M */
3694 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3695 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3696 rtl_writephy(tp, 0x1f, 0x0000);
3697
3698 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3699 data = r8168_mac_ocp_read(tp, 0xdd02);
3700 ioffset_p3 = ((data & 0x80)>>7);
3701 ioffset_p3 <<= 3;
3702
3703 data = r8168_mac_ocp_read(tp, 0xdd00);
3704 ioffset_p3 |= ((data & (0xe000))>>13);
3705 ioffset_p2 = ((data & (0x1e00))>>9);
3706 ioffset_p1 = ((data & (0x01e0))>>5);
3707 ioffset_p0 = ((data & 0x0010)>>4);
3708 ioffset_p0 <<= 3;
3709 ioffset_p0 |= (data & (0x07));
3710 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3711
05b9687b
CHL		 3712 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3713 (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
6e1d0b89
CHL		 3714 rtl_writephy(tp, 0x1f, 0x0bcf);
3715 rtl_writephy(tp, 0x16, data);
3716 rtl_writephy(tp, 0x1f, 0x0000);
3717 }
3718
3719 /* Modify rlen (TX LPF corner frequency) level */
3720 rtl_writephy(tp, 0x1f, 0x0bcd);
3721 data = rtl_readphy(tp, 0x16);
3722 data &= 0x000f;
3723 rlen = 0;
3724 if (data > 3)
3725 rlen = data - 3;
3726 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3727 rtl_writephy(tp, 0x17, data);
3728 rtl_writephy(tp, 0x1f, 0x0bcd);
3729 rtl_writephy(tp, 0x1f, 0x0000);
3730
3731 /* disable phy pfm mode */
3732 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3733 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
6e1d0b89
CHL		 3734 rtl_writephy(tp, 0x1f, 0x0000);
3735
3736 /* Check ALDPS bit, disable it if enabled */
3737 rtl_writephy(tp, 0x1f, 0x0a43);
3738 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3739 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3740
3741 rtl_writephy(tp, 0x1f, 0x0000);
3742}
3743
4da19633 3744static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3745{
350f7596 3746 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3747 { 0x1f, 0x0003 },
3748 { 0x08, 0x441d },
3749 { 0x01, 0x9100 },
3750 { 0x1f, 0x0000 }
3751 };
3752
4da19633 3753 rtl_writephy(tp, 0x1f, 0x0000);
3754 rtl_patchphy(tp, 0x11, 1 << 12);
3755 rtl_patchphy(tp, 0x19, 1 << 13);
3756 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3757
4da19633 3758 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3759}
3760
5a5e4443
HW		 3761static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3762{
3763 static const struct phy_reg phy_reg_init[] = {
3764 { 0x1f, 0x0005 },
3765 { 0x1a, 0x0000 },
3766 { 0x1f, 0x0000 },
3767
3768 { 0x1f, 0x0004 },
3769 { 0x1c, 0x0000 },
3770 { 0x1f, 0x0000 },
3771
3772 { 0x1f, 0x0001 },
3773 { 0x15, 0x7701 },
3774 { 0x1f, 0x0000 }
3775 };
3776
3777 /* Disable ALDPS before ram code */
eef63cc1
FR		 3778 rtl_writephy(tp, 0x1f, 0x0000);
3779 rtl_writephy(tp, 0x18, 0x0310);
3780 msleep(100);
5a5e4443 3781
953a12cc 3782 rtl_apply_firmware(tp);
5a5e4443
HW		 3783
3784 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3785}
3786
7e18dca1
HW		 3787static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3788{
7e18dca1 3789 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3790 rtl_writephy(tp, 0x1f, 0x0000);
3791 rtl_writephy(tp, 0x18, 0x0310);
3792 msleep(20);
7e18dca1
HW		 3793
3794 rtl_apply_firmware(tp);
3795
3796 /* EEE setting */
fdf6fc06 3797 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3798 rtl_writephy(tp, 0x1f, 0x0004);
3799 rtl_writephy(tp, 0x10, 0x401f);
3800 rtl_writephy(tp, 0x19, 0x7030);
3801 rtl_writephy(tp, 0x1f, 0x0000);
3802}
3803
5598bfe5
HW		 3804static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3805{
5598bfe5
HW		 3806 static const struct phy_reg phy_reg_init[] = {
3807 { 0x1f, 0x0004 },
3808 { 0x10, 0xc07f },
3809 { 0x19, 0x7030 },
3810 { 0x1f, 0x0000 }
3811 };
3812
3813 /* Disable ALDPS before ram code */
eef63cc1
FR		 3814 rtl_writephy(tp, 0x1f, 0x0000);
3815 rtl_writephy(tp, 0x18, 0x0310);
3816 msleep(100);
5598bfe5
HW		 3817
3818 rtl_apply_firmware(tp);
3819
fdf6fc06 3820 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3821 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3822
fdf6fc06 3823 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3824}
3825
5615d9f1
FR		 3826static void rtl_hw_phy_config(struct net_device *dev)
3827{
3828 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3829
3830 rtl8169_print_mac_version(tp);
3831
3832 switch (tp->mac_version) {
3833 case RTL_GIGA_MAC_VER_01:
3834 break;
3835 case RTL_GIGA_MAC_VER_02:
3836 case RTL_GIGA_MAC_VER_03:
4da19633 3837 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3838 break;
3839 case RTL_GIGA_MAC_VER_04:
4da19633 3840 rtl8169sb_hw_phy_config(tp);
5615d9f1 3841 break;
2e955856 3842 case RTL_GIGA_MAC_VER_05:
4da19633 3843 rtl8169scd_hw_phy_config(tp);
2e955856 3844 break;
8c7006aa 3845 case RTL_GIGA_MAC_VER_06:
4da19633 3846 rtl8169sce_hw_phy_config(tp);
8c7006aa 3847 break;
2857ffb7
FR		 3848 case RTL_GIGA_MAC_VER_07:
3849 case RTL_GIGA_MAC_VER_08:
3850 case RTL_GIGA_MAC_VER_09:
4da19633 3851 rtl8102e_hw_phy_config(tp);
2857ffb7 3852 break;
236b8082 3853 case RTL_GIGA_MAC_VER_11:
4da19633 3854 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3855 break;
3856 case RTL_GIGA_MAC_VER_12:
4da19633 3857 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3858 break;
3859 case RTL_GIGA_MAC_VER_17:
4da19633 3860 rtl8168bef_hw_phy_config(tp);
236b8082 3861 break;
867763c1 3862 case RTL_GIGA_MAC_VER_18:
4da19633 3863 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3864 break;
3865 case RTL_GIGA_MAC_VER_19:
4da19633 3866 rtl8168c_1_hw_phy_config(tp);
867763c1 3867 break;
7da97ec9 3868 case RTL_GIGA_MAC_VER_20:
4da19633 3869 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3870 break;
197ff761 3871 case RTL_GIGA_MAC_VER_21:
4da19633 3872 rtl8168c_3_hw_phy_config(tp);
197ff761 3873 break;
6fb07058 3874 case RTL_GIGA_MAC_VER_22:
4da19633 3875 rtl8168c_4_hw_phy_config(tp);
6fb07058 3876 break;
ef3386f0 3877 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3878 case RTL_GIGA_MAC_VER_24:
4da19633 3879 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3880 break;
5b538df9 3881 case RTL_GIGA_MAC_VER_25:
bca03d5f 3882 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3883 break;
3884 case RTL_GIGA_MAC_VER_26:
bca03d5f 3885 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3886 break;
3887 case RTL_GIGA_MAC_VER_27:
4da19633 3888 rtl8168d_3_hw_phy_config(tp);
5b538df9 3889 break;
e6de30d6 3890 case RTL_GIGA_MAC_VER_28:
3891 rtl8168d_4_hw_phy_config(tp);
3892 break;
5a5e4443
HW		 3893 case RTL_GIGA_MAC_VER_29:
3894 case RTL_GIGA_MAC_VER_30:
3895 rtl8105e_hw_phy_config(tp);
3896 break;
cecb5fd7
FR		 3897 case RTL_GIGA_MAC_VER_31:
3898 /* None. */
3899 break;
01dc7fec 3900 case RTL_GIGA_MAC_VER_32:
01dc7fec 3901 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3902 rtl8168e_1_hw_phy_config(tp);
3903 break;
3904 case RTL_GIGA_MAC_VER_34:
3905 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3906 break;
c2218925
HW		 3907 case RTL_GIGA_MAC_VER_35:
3908 rtl8168f_1_hw_phy_config(tp);
3909 break;
3910 case RTL_GIGA_MAC_VER_36:
3911 rtl8168f_2_hw_phy_config(tp);
3912 break;
ef3386f0 3913
7e18dca1
HW		 3914 case RTL_GIGA_MAC_VER_37:
3915 rtl8402_hw_phy_config(tp);
3916 break;
3917
b3d7b2f2
HW		 3918 case RTL_GIGA_MAC_VER_38:
3919 rtl8411_hw_phy_config(tp);
3920 break;
3921
5598bfe5
HW		 3922 case RTL_GIGA_MAC_VER_39:
3923 rtl8106e_hw_phy_config(tp);
3924 break;
3925
c558386b
HW		 3926 case RTL_GIGA_MAC_VER_40:
3927 rtl8168g_1_hw_phy_config(tp);
3928 break;
57538c4a 3929 case RTL_GIGA_MAC_VER_42:
58152cd4 3930 case RTL_GIGA_MAC_VER_43:
45dd95c4 3931 case RTL_GIGA_MAC_VER_44:
57538c4a 3932 rtl8168g_2_hw_phy_config(tp);
3933 break;
6e1d0b89
CHL		 3934 case RTL_GIGA_MAC_VER_45:
3935 case RTL_GIGA_MAC_VER_47:
3936 rtl8168h_1_hw_phy_config(tp);
3937 break;
3938 case RTL_GIGA_MAC_VER_46:
3939 case RTL_GIGA_MAC_VER_48:
3940 rtl8168h_2_hw_phy_config(tp);
3941 break;
c558386b
HW		 3942
3943 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3944 default:
3945 break;
3946 }
3947}
3948
da78dbff 3949static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3950{
1da177e4
LT		 3951 struct timer_list *timer = &tp->timer;
3952 void __iomem *ioaddr = tp->mmio_addr;
3953 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3954
bcf0bf90 3955 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3956
4da19633 3957 if (tp->phy_reset_pending(tp)) {
5b0384f4 3958 /*
1da177e4
LT		 3959 * A busy loop could burn quite a few cycles on nowadays CPU.
3960 * Let's delay the execution of the timer for a few ticks.
3961 */
3962 timeout = HZ/10;
3963 goto out_mod_timer;
3964 }
3965
3966 if (tp->link_ok(ioaddr))
da78dbff 3967 return;
1da177e4 3968
9bb8eeb5 3969 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3970
4da19633 3971 tp->phy_reset_enable(tp);
1da177e4
LT		 3972
3973out_mod_timer:
3974 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3975}
3976
3977static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3978{
da78dbff
FR		 3979 if (!test_and_set_bit(flag, tp->wk.flags))
3980 schedule_work(&tp->wk.work);
da78dbff
FR		 3981}
3982
3983static void rtl8169_phy_timer(unsigned long __opaque)
3984{
3985 struct net_device *dev = (struct net_device *)__opaque;
3986 struct rtl8169_private *tp = netdev_priv(dev);
3987
98ddf986 3988 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3989}
3990
1da177e4
LT		 3991static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3992 void __iomem *ioaddr)
3993{
3994 iounmap(ioaddr);
3995 pci_release_regions(pdev);
87aeec76 3996 pci_clear_mwi(pdev);
1da177e4
LT		 3997 pci_disable_device(pdev);
3998 free_netdev(dev);
3999}
4000
ffc46952
FR		 4001DECLARE_RTL_COND(rtl_phy_reset_cond)
4002{
4003 return tp->phy_reset_pending(tp);
4004}
4005
bf793295
FR		 4006static void rtl8169_phy_reset(struct net_device *dev,
4007 struct rtl8169_private *tp)
4008{
4da19633 4009 tp->phy_reset_enable(tp);
ffc46952 4010 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4011}
4012
2544bfc0
FR		 4013static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4014{
4015 void __iomem *ioaddr = tp->mmio_addr;
4016
4017 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4018 (RTL_R8(PHYstatus) & TBI_Enable);
4019}
4020
4ff96fa6
FR		 4021static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4022{
4023 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 4024
5615d9f1 4025 rtl_hw_phy_config(dev);
4ff96fa6 4026
77332894
MS		 4027 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4028 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4029 RTL_W8(0x82, 0x01);
4030 }
4ff96fa6 4031
6dccd16b
FR		 4032 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4033
4034 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4035 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4036
bcf0bf90 4037 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 4038 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4039 RTL_W8(0x82, 0x01);
4040 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4041 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4042 }
4043
bf793295
FR		 4044 rtl8169_phy_reset(dev, tp);
4045
54405cde 4046 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4047 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4048 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4049 (tp->mii.supports_gmii ?
4050 ADVERTISED_1000baseT_Half |
4051 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4052
2544bfc0 4053 if (rtl_tbi_enabled(tp))
bf82c189 4054 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4055}
4056
773d2021
FR		 4057static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4058{
4059 void __iomem *ioaddr = tp->mmio_addr;
773d2021 4060
da78dbff 4061 rtl_lock_work(tp);
773d2021
FR		 4062
4063 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 4064
9ecb9aab 4065 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 4066 RTL_R32(MAC4);
4067
9ecb9aab 4068 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 4069 RTL_R32(MAC0);
4070
9ecb9aab 4071 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4072 rtl_rar_exgmac_set(tp, addr);
c28aa385 4073
773d2021
FR		 4074 RTL_W8(Cfg9346, Cfg9346_Lock);
4075
da78dbff 4076 rtl_unlock_work(tp);
773d2021
FR		 4077}
4078
4079static int rtl_set_mac_address(struct net_device *dev, void *p)
4080{
4081 struct rtl8169_private *tp = netdev_priv(dev);
4082 struct sockaddr *addr = p;
4083
4084 if (!is_valid_ether_addr(addr->sa_data))
4085 return -EADDRNOTAVAIL;
4086
4087 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4088
4089 rtl_rar_set(tp, dev->dev_addr);
4090
4091 return 0;
4092}
4093
5f787a1a
FR		 4094static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4095{
4096 struct rtl8169_private *tp = netdev_priv(dev);
4097 struct mii_ioctl_data *data = if_mii(ifr);
4098
8b4ab28d
FR		 4099 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4100}
5f787a1a 4101
cecb5fd7
FR		 4102static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4103 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4104{
5f787a1a
FR		 4105 switch (cmd) {
4106 case SIOCGMIIPHY:
4107 data->phy_id = 32; /* Internal PHY */
4108 return 0;
4109
4110 case SIOCGMIIREG:
4da19633 4111 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4112 return 0;
4113
4114 case SIOCSMIIREG:
4da19633 4115 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4116 return 0;
4117 }
4118 return -EOPNOTSUPP;
4119}
4120
8b4ab28d
FR		 4121static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4122{
4123 return -EOPNOTSUPP;
4124}
4125
fbac58fc
FR		 4126static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4127{
4128 if (tp->features & RTL_FEATURE_MSI) {
4129 pci_disable_msi(pdev);
4130 tp->features &= ~RTL_FEATURE_MSI;
4131 }
4132}
4133
baf63293 4134static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4135{
4136 struct mdio_ops *ops = &tp->mdio_ops;
4137
4138 switch (tp->mac_version) {
4139 case RTL_GIGA_MAC_VER_27:
4140 ops->write = r8168dp_1_mdio_write;
4141 ops->read = r8168dp_1_mdio_read;
4142 break;
e6de30d6 4143 case RTL_GIGA_MAC_VER_28:
4804b3b3 4144 case RTL_GIGA_MAC_VER_31:
e6de30d6 4145 ops->write = r8168dp_2_mdio_write;
4146 ops->read = r8168dp_2_mdio_read;
4147 break;
c558386b
HW		 4148 case RTL_GIGA_MAC_VER_40:
4149 case RTL_GIGA_MAC_VER_41:
57538c4a 4150 case RTL_GIGA_MAC_VER_42:
58152cd4 4151 case RTL_GIGA_MAC_VER_43:
45dd95c4 4152 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4153 case RTL_GIGA_MAC_VER_45:
4154 case RTL_GIGA_MAC_VER_46:
4155 case RTL_GIGA_MAC_VER_47:
4156 case RTL_GIGA_MAC_VER_48:
c558386b
HW		 4157 ops->write = r8168g_mdio_write;
4158 ops->read = r8168g_mdio_read;
4159 break;
c0e45c1c 4160 default:
4161 ops->write = r8169_mdio_write;
4162 ops->read = r8169_mdio_read;
4163 break;
4164 }
4165}
4166
e2409d83 4167static void rtl_speed_down(struct rtl8169_private *tp)
4168{
4169 u32 adv;
4170 int lpa;
4171
4172 rtl_writephy(tp, 0x1f, 0x0000);
4173 lpa = rtl_readphy(tp, MII_LPA);
4174
4175 if (lpa & (LPA_10HALF | LPA_10FULL))
4176 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4177 else if (lpa & (LPA_100HALF | LPA_100FULL))
4178 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4179 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4180 else
4181 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4182 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4183 (tp->mii.supports_gmii ?
4184 ADVERTISED_1000baseT_Half |
4185 ADVERTISED_1000baseT_Full : 0);
4186
4187 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4188 adv);
4189}
4190
649b3b8c 4191static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4192{
4193 void __iomem *ioaddr = tp->mmio_addr;
4194
4195 switch (tp->mac_version) {
b00e69de
CB		 4196 case RTL_GIGA_MAC_VER_25:
4197 case RTL_GIGA_MAC_VER_26:
649b3b8c 4198 case RTL_GIGA_MAC_VER_29:
4199 case RTL_GIGA_MAC_VER_30:
4200 case RTL_GIGA_MAC_VER_32:
4201 case RTL_GIGA_MAC_VER_33:
4202 case RTL_GIGA_MAC_VER_34:
7e18dca1 4203 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4204 case RTL_GIGA_MAC_VER_38:
5598bfe5 4205 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4206 case RTL_GIGA_MAC_VER_40:
4207 case RTL_GIGA_MAC_VER_41:
57538c4a 4208 case RTL_GIGA_MAC_VER_42:
58152cd4 4209 case RTL_GIGA_MAC_VER_43:
45dd95c4 4210 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4211 case RTL_GIGA_MAC_VER_45:
4212 case RTL_GIGA_MAC_VER_46:
4213 case RTL_GIGA_MAC_VER_47:
4214 case RTL_GIGA_MAC_VER_48:
649b3b8c 4215 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4216 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4217 break;
4218 default:
4219 break;
4220 }
4221}
4222
4223static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4224{
4225 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4226 return false;
4227
e2409d83 4228 rtl_speed_down(tp);
649b3b8c 4229 rtl_wol_suspend_quirk(tp);
4230
4231 return true;
4232}
4233
065c27c1 4234static void r810x_phy_power_down(struct rtl8169_private *tp)
4235{
4236 rtl_writephy(tp, 0x1f, 0x0000);
4237 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4238}
4239
4240static void r810x_phy_power_up(struct rtl8169_private *tp)
4241{
4242 rtl_writephy(tp, 0x1f, 0x0000);
4243 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4244}
4245
4246static void r810x_pll_power_down(struct rtl8169_private *tp)
4247{
0004299a
HW		 4248 void __iomem *ioaddr = tp->mmio_addr;
4249
649b3b8c 4250 if (rtl_wol_pll_power_down(tp))
065c27c1 4251 return;
065c27c1 4252
4253 r810x_phy_power_down(tp);
0004299a
HW		 4254
4255 switch (tp->mac_version) {
4256 case RTL_GIGA_MAC_VER_07:
4257 case RTL_GIGA_MAC_VER_08:
4258 case RTL_GIGA_MAC_VER_09:
4259 case RTL_GIGA_MAC_VER_10:
4260 case RTL_GIGA_MAC_VER_13:
4261 case RTL_GIGA_MAC_VER_16:
4262 break;
4263 default:
4264 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4265 break;
4266 }
065c27c1 4267}
4268
4269static void r810x_pll_power_up(struct rtl8169_private *tp)
4270{
0004299a
HW		 4271 void __iomem *ioaddr = tp->mmio_addr;
4272
065c27c1 4273 r810x_phy_power_up(tp);
0004299a
HW		 4274
4275 switch (tp->mac_version) {
4276 case RTL_GIGA_MAC_VER_07:
4277 case RTL_GIGA_MAC_VER_08:
4278 case RTL_GIGA_MAC_VER_09:
4279 case RTL_GIGA_MAC_VER_10:
4280 case RTL_GIGA_MAC_VER_13:
4281 case RTL_GIGA_MAC_VER_16:
4282 break;
6e1d0b89
CHL		 4283 case RTL_GIGA_MAC_VER_47:
4284 case RTL_GIGA_MAC_VER_48:
05b9687b 4285 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4286 break;
0004299a
HW		 4287 default:
4288 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4289 break;
4290 }
065c27c1 4291}
4292
4293static void r8168_phy_power_up(struct rtl8169_private *tp)
4294{
4295 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4296 switch (tp->mac_version) {
4297 case RTL_GIGA_MAC_VER_11:
4298 case RTL_GIGA_MAC_VER_12:
4299 case RTL_GIGA_MAC_VER_17:
4300 case RTL_GIGA_MAC_VER_18:
4301 case RTL_GIGA_MAC_VER_19:
4302 case RTL_GIGA_MAC_VER_20:
4303 case RTL_GIGA_MAC_VER_21:
4304 case RTL_GIGA_MAC_VER_22:
4305 case RTL_GIGA_MAC_VER_23:
4306 case RTL_GIGA_MAC_VER_24:
4307 case RTL_GIGA_MAC_VER_25:
4308 case RTL_GIGA_MAC_VER_26:
4309 case RTL_GIGA_MAC_VER_27:
4310 case RTL_GIGA_MAC_VER_28:
4311 case RTL_GIGA_MAC_VER_31:
4312 rtl_writephy(tp, 0x0e, 0x0000);
4313 break;
4314 default:
4315 break;
4316 }
065c27c1 4317 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4318}
4319
4320static void r8168_phy_power_down(struct rtl8169_private *tp)
4321{
4322 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4323 switch (tp->mac_version) {
4324 case RTL_GIGA_MAC_VER_32:
4325 case RTL_GIGA_MAC_VER_33:
beb330a4 4326 case RTL_GIGA_MAC_VER_40:
4327 case RTL_GIGA_MAC_VER_41:
01dc7fec 4328 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4329 break;
4330
4331 case RTL_GIGA_MAC_VER_11:
4332 case RTL_GIGA_MAC_VER_12:
4333 case RTL_GIGA_MAC_VER_17:
4334 case RTL_GIGA_MAC_VER_18:
4335 case RTL_GIGA_MAC_VER_19:
4336 case RTL_GIGA_MAC_VER_20:
4337 case RTL_GIGA_MAC_VER_21:
4338 case RTL_GIGA_MAC_VER_22:
4339 case RTL_GIGA_MAC_VER_23:
4340 case RTL_GIGA_MAC_VER_24:
4341 case RTL_GIGA_MAC_VER_25:
4342 case RTL_GIGA_MAC_VER_26:
4343 case RTL_GIGA_MAC_VER_27:
4344 case RTL_GIGA_MAC_VER_28:
4345 case RTL_GIGA_MAC_VER_31:
4346 rtl_writephy(tp, 0x0e, 0x0200);
4347 default:
4348 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4349 break;
4350 }
065c27c1 4351}
4352
4353static void r8168_pll_power_down(struct rtl8169_private *tp)
4354{
4355 void __iomem *ioaddr = tp->mmio_addr;
4356
cecb5fd7
FR		 4357 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4358 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4359 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
2f8c040c 4360 r8168_check_dash(tp)) {
065c27c1 4361 return;
5d2e1957 4362 }
065c27c1 4363
cecb5fd7
FR		 4364 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4365 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4366 (RTL_R16(CPlusCmd) & ASF)) {
4367 return;
4368 }
4369
01dc7fec 4370 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4371 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4372 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4373
649b3b8c 4374 if (rtl_wol_pll_power_down(tp))
065c27c1 4375 return;
065c27c1 4376
4377 r8168_phy_power_down(tp);
4378
4379 switch (tp->mac_version) {
4380 case RTL_GIGA_MAC_VER_25:
4381 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4382 case RTL_GIGA_MAC_VER_27:
4383 case RTL_GIGA_MAC_VER_28:
4804b3b3 4384 case RTL_GIGA_MAC_VER_31:
01dc7fec 4385 case RTL_GIGA_MAC_VER_32:
4386 case RTL_GIGA_MAC_VER_33:
42fde737 4387 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4388 case RTL_GIGA_MAC_VER_45:
4389 case RTL_GIGA_MAC_VER_46:
065c27c1 4390 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4391 break;
beb330a4 4392 case RTL_GIGA_MAC_VER_40:
4393 case RTL_GIGA_MAC_VER_41:
706123d0 4394 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4395 0xfc000000, ERIAR_EXGMAC);
b8e5e6ad 4396 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
beb330a4 4397 break;
065c27c1 4398 }
4399}
4400
4401static void r8168_pll_power_up(struct rtl8169_private *tp)
4402{
4403 void __iomem *ioaddr = tp->mmio_addr;
4404
065c27c1 4405 switch (tp->mac_version) {
4406 case RTL_GIGA_MAC_VER_25:
4407 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4408 case RTL_GIGA_MAC_VER_27:
4409 case RTL_GIGA_MAC_VER_28:
4804b3b3 4410 case RTL_GIGA_MAC_VER_31:
01dc7fec 4411 case RTL_GIGA_MAC_VER_32:
4412 case RTL_GIGA_MAC_VER_33:
065c27c1 4413 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4414 break;
42fde737 4415 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4416 case RTL_GIGA_MAC_VER_45:
4417 case RTL_GIGA_MAC_VER_46:
05b9687b 4418 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4419 break;
beb330a4 4420 case RTL_GIGA_MAC_VER_40:
4421 case RTL_GIGA_MAC_VER_41:
b8e5e6ad 4422 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
706123d0 4423 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4424 0x00000000, ERIAR_EXGMAC);
4425 break;
065c27c1 4426 }
4427
4428 r8168_phy_power_up(tp);
4429}
4430
d58d46b5
FR		 4431static void rtl_generic_op(struct rtl8169_private *tp,
4432 void (*op)(struct rtl8169_private *))
065c27c1 4433{
4434 if (op)
4435 op(tp);
4436}
4437
4438static void rtl_pll_power_down(struct rtl8169_private *tp)
4439{
d58d46b5 4440 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4441}
4442
4443static void rtl_pll_power_up(struct rtl8169_private *tp)
4444{
d58d46b5 4445 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4446}
4447
baf63293 4448static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4449{
4450 struct pll_power_ops *ops = &tp->pll_power_ops;
4451
4452 switch (tp->mac_version) {
4453 case RTL_GIGA_MAC_VER_07:
4454 case RTL_GIGA_MAC_VER_08:
4455 case RTL_GIGA_MAC_VER_09:
4456 case RTL_GIGA_MAC_VER_10:
4457 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4458 case RTL_GIGA_MAC_VER_29:
4459 case RTL_GIGA_MAC_VER_30:
7e18dca1 4460 case RTL_GIGA_MAC_VER_37:
5598bfe5 4461 case RTL_GIGA_MAC_VER_39:
58152cd4 4462 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 4463 case RTL_GIGA_MAC_VER_47:
4464 case RTL_GIGA_MAC_VER_48:
065c27c1 4465 ops->down = r810x_pll_power_down;
4466 ops->up = r810x_pll_power_up;
4467 break;
4468
4469 case RTL_GIGA_MAC_VER_11:
4470 case RTL_GIGA_MAC_VER_12:
4471 case RTL_GIGA_MAC_VER_17:
4472 case RTL_GIGA_MAC_VER_18:
4473 case RTL_GIGA_MAC_VER_19:
4474 case RTL_GIGA_MAC_VER_20:
4475 case RTL_GIGA_MAC_VER_21:
4476 case RTL_GIGA_MAC_VER_22:
4477 case RTL_GIGA_MAC_VER_23:
4478 case RTL_GIGA_MAC_VER_24:
4479 case RTL_GIGA_MAC_VER_25:
4480 case RTL_GIGA_MAC_VER_26:
4481 case RTL_GIGA_MAC_VER_27:
e6de30d6 4482 case RTL_GIGA_MAC_VER_28:
4804b3b3 4483 case RTL_GIGA_MAC_VER_31:
01dc7fec 4484 case RTL_GIGA_MAC_VER_32:
4485 case RTL_GIGA_MAC_VER_33:
70090424 4486 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4487 case RTL_GIGA_MAC_VER_35:
4488 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4489 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4490 case RTL_GIGA_MAC_VER_40:
4491 case RTL_GIGA_MAC_VER_41:
57538c4a 4492 case RTL_GIGA_MAC_VER_42:
45dd95c4 4493 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4494 case RTL_GIGA_MAC_VER_45:
4495 case RTL_GIGA_MAC_VER_46:
065c27c1 4496 ops->down = r8168_pll_power_down;
4497 ops->up = r8168_pll_power_up;
4498 break;
4499
4500 default:
4501 ops->down = NULL;
4502 ops->up = NULL;
4503 break;
4504 }
4505}
4506
e542a226
HW		 4507static void rtl_init_rxcfg(struct rtl8169_private *tp)
4508{
4509 void __iomem *ioaddr = tp->mmio_addr;
4510
4511 switch (tp->mac_version) {
4512 case RTL_GIGA_MAC_VER_01:
4513 case RTL_GIGA_MAC_VER_02:
4514 case RTL_GIGA_MAC_VER_03:
4515 case RTL_GIGA_MAC_VER_04:
4516 case RTL_GIGA_MAC_VER_05:
4517 case RTL_GIGA_MAC_VER_06:
4518 case RTL_GIGA_MAC_VER_10:
4519 case RTL_GIGA_MAC_VER_11:
4520 case RTL_GIGA_MAC_VER_12:
4521 case RTL_GIGA_MAC_VER_13:
4522 case RTL_GIGA_MAC_VER_14:
4523 case RTL_GIGA_MAC_VER_15:
4524 case RTL_GIGA_MAC_VER_16:
4525 case RTL_GIGA_MAC_VER_17:
4526 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4527 break;
4528 case RTL_GIGA_MAC_VER_18:
4529 case RTL_GIGA_MAC_VER_19:
4530 case RTL_GIGA_MAC_VER_20:
4531 case RTL_GIGA_MAC_VER_21:
4532 case RTL_GIGA_MAC_VER_22:
4533 case RTL_GIGA_MAC_VER_23:
4534 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4535 case RTL_GIGA_MAC_VER_34:
3ced8c95 4536 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 4537 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4538 break;
beb330a4 4539 case RTL_GIGA_MAC_VER_40:
7a9810e7
MD		 4540 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4541 break;
beb330a4 4542 case RTL_GIGA_MAC_VER_41:
57538c4a 4543 case RTL_GIGA_MAC_VER_42:
58152cd4 4544 case RTL_GIGA_MAC_VER_43:
45dd95c4 4545 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4546 case RTL_GIGA_MAC_VER_45:
4547 case RTL_GIGA_MAC_VER_46:
4548 case RTL_GIGA_MAC_VER_47:
4549 case RTL_GIGA_MAC_VER_48:
beb330a4 4550 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4551 break;
e542a226
HW		 4552 default:
4553 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4554 break;
4555 }
4556}
4557
92fc43b4
HW		 4558static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4559{
9fba0812 4560 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4561}
4562
d58d46b5
FR		 4563static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4564{
9c5028e9 4565 void __iomem *ioaddr = tp->mmio_addr;
4566
4567 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4568 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4569 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4570}
4571
4572static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4573{
9c5028e9 4574 void __iomem *ioaddr = tp->mmio_addr;
4575
4576 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4577 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4578 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4579}
4580
4581static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4582{
4583 void __iomem *ioaddr = tp->mmio_addr;
4584
4585 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4586 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4587 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4588}
4589
4590static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4591{
4592 void __iomem *ioaddr = tp->mmio_addr;
4593
4594 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4595 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4596 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4597}
4598
4599static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4600{
4601 void __iomem *ioaddr = tp->mmio_addr;
4602
4603 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4604}
4605
4606static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4607{
4608 void __iomem *ioaddr = tp->mmio_addr;
4609
4610 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4611}
4612
4613static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4614{
4615 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4616
4617 RTL_W8(MaxTxPacketSize, 0x3f);
4618 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4619 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4620 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4621}
4622
4623static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4624{
4625 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4626
4627 RTL_W8(MaxTxPacketSize, 0x0c);
4628 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4629 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4630 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4631}
4632
4633static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4634{
4635 rtl_tx_performance_tweak(tp->pci_dev,
4636 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4637}
4638
4639static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4640{
4641 rtl_tx_performance_tweak(tp->pci_dev,
4642 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4643}
4644
4645static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4646{
4647 void __iomem *ioaddr = tp->mmio_addr;
4648
4649 r8168b_0_hw_jumbo_enable(tp);
4650
4651 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4652}
4653
4654static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4655{
4656 void __iomem *ioaddr = tp->mmio_addr;
4657
4658 r8168b_0_hw_jumbo_disable(tp);
4659
4660 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4661}
4662
baf63293 4663static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4664{
4665 struct jumbo_ops *ops = &tp->jumbo_ops;
4666
4667 switch (tp->mac_version) {
4668 case RTL_GIGA_MAC_VER_11:
4669 ops->disable = r8168b_0_hw_jumbo_disable;
4670 ops->enable = r8168b_0_hw_jumbo_enable;
4671 break;
4672 case RTL_GIGA_MAC_VER_12:
4673 case RTL_GIGA_MAC_VER_17:
4674 ops->disable = r8168b_1_hw_jumbo_disable;
4675 ops->enable = r8168b_1_hw_jumbo_enable;
4676 break;
4677 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4678 case RTL_GIGA_MAC_VER_19:
4679 case RTL_GIGA_MAC_VER_20:
4680 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4681 case RTL_GIGA_MAC_VER_22:
4682 case RTL_GIGA_MAC_VER_23:
4683 case RTL_GIGA_MAC_VER_24:
4684 case RTL_GIGA_MAC_VER_25:
4685 case RTL_GIGA_MAC_VER_26:
4686 ops->disable = r8168c_hw_jumbo_disable;
4687 ops->enable = r8168c_hw_jumbo_enable;
4688 break;
4689 case RTL_GIGA_MAC_VER_27:
4690 case RTL_GIGA_MAC_VER_28:
4691 ops->disable = r8168dp_hw_jumbo_disable;
4692 ops->enable = r8168dp_hw_jumbo_enable;
4693 break;
4694 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4695 case RTL_GIGA_MAC_VER_32:
4696 case RTL_GIGA_MAC_VER_33:
4697 case RTL_GIGA_MAC_VER_34:
4698 ops->disable = r8168e_hw_jumbo_disable;
4699 ops->enable = r8168e_hw_jumbo_enable;
4700 break;
4701
4702 /*
4703 * No action needed for jumbo frames with 8169.
4704 * No jumbo for 810x at all.
4705 */
c558386b
HW		 4706 case RTL_GIGA_MAC_VER_40:
4707 case RTL_GIGA_MAC_VER_41:
57538c4a 4708 case RTL_GIGA_MAC_VER_42:
58152cd4 4709 case RTL_GIGA_MAC_VER_43:
45dd95c4 4710 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4711 case RTL_GIGA_MAC_VER_45:
4712 case RTL_GIGA_MAC_VER_46:
4713 case RTL_GIGA_MAC_VER_47:
4714 case RTL_GIGA_MAC_VER_48:
d58d46b5
FR		 4715 default:
4716 ops->disable = NULL;
4717 ops->enable = NULL;
4718 break;
4719 }
4720}
4721
ffc46952
FR		 4722DECLARE_RTL_COND(rtl_chipcmd_cond)
4723{
4724 void __iomem *ioaddr = tp->mmio_addr;
4725
4726 return RTL_R8(ChipCmd) & CmdReset;
4727}
4728
6f43adc8
FR		 4729static void rtl_hw_reset(struct rtl8169_private *tp)
4730{
4731 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4732
6f43adc8
FR		 4733 RTL_W8(ChipCmd, CmdReset);
4734
ffc46952 4735 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
1e918876
FW		 4736
4737 netdev_reset_queue(tp->dev);
6f43adc8
FR		 4738}
4739
b6ffd97f 4740static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4741{
b6ffd97f
FR		 4742 struct rtl_fw *rtl_fw;
4743 const char *name;
4744 int rc = -ENOMEM;
953a12cc 4745
b6ffd97f
FR		 4746 name = rtl_lookup_firmware_name(tp);
4747 if (!name)
4748 goto out_no_firmware;
953a12cc 4749
b6ffd97f
FR		 4750 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4751 if (!rtl_fw)
4752 goto err_warn;
31bd204f 4753
b6ffd97f
FR		 4754 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4755 if (rc < 0)
4756 goto err_free;
4757
fd112f2e
FR		 4758 rc = rtl_check_firmware(tp, rtl_fw);
4759 if (rc < 0)
4760 goto err_release_firmware;
4761
b6ffd97f
FR		 4762 tp->rtl_fw = rtl_fw;
4763out:
4764 return;
4765
fd112f2e
FR		 4766err_release_firmware:
4767 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4768err_free:
4769 kfree(rtl_fw);
4770err_warn:
4771 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4772 name, rc);
4773out_no_firmware:
4774 tp->rtl_fw = NULL;
4775 goto out;
4776}
4777
4778static void rtl_request_firmware(struct rtl8169_private *tp)
4779{
4780 if (IS_ERR(tp->rtl_fw))
4781 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4782}
4783
92fc43b4
HW		 4784static void rtl_rx_close(struct rtl8169_private *tp)
4785{
4786 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4787
1687b566 4788 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4789}
4790
ffc46952
FR		 4791DECLARE_RTL_COND(rtl_npq_cond)
4792{
4793 void __iomem *ioaddr = tp->mmio_addr;
4794
4795 return RTL_R8(TxPoll) & NPQ;
4796}
4797
4798DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4799{
4800 void __iomem *ioaddr = tp->mmio_addr;
4801
4802 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4803}
4804
e6de30d6 4805static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4806{
e6de30d6 4807 void __iomem *ioaddr = tp->mmio_addr;
4808
1da177e4 4809 /* Disable interrupts */
811fd301 4810 rtl8169_irq_mask_and_ack(tp);
1da177e4 4811
92fc43b4
HW		 4812 rtl_rx_close(tp);
4813
5d2e1957 4814 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4815 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4816 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4817 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 4818 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 4819 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4820 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4821 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4822 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
4823 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4824 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4825 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4826 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4827 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4828 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
4829 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
4830 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
4831 tp->mac_version == RTL_GIGA_MAC_VER_48) {
c2b0c1e7 4832 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4833 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4834 } else {
4835 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4836 udelay(100);
e6de30d6 4837 }
4838
92fc43b4 4839 rtl_hw_reset(tp);
1da177e4
LT		 4840}
4841
7f796d83 4842static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4843{
4844 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4845
4846 /* Set DMA burst size and Interframe Gap Time */
4847 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4848 (InterFrameGap << TxInterFrameGapShift));
4849}
4850
07ce4064 4851static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4852{
4853 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4854
07ce4064
FR		 4855 tp->hw_start(dev);
4856
da78dbff 4857 rtl_irq_enable_all(tp);
07ce4064
FR		 4858}
4859
7f796d83
FR		 4860static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4861 void __iomem *ioaddr)
4862{
4863 /*
4864 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4865 * register to be written before TxDescAddrLow to work.
4866 * Switching from MMIO to I/O access fixes the issue as well.
4867 */
4868 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4869 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4870 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4871 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4872}
4873
4874static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4875{
4876 u16 cmd;
4877
4878 cmd = RTL_R16(CPlusCmd);
4879 RTL_W16(CPlusCmd, cmd);
4880 return cmd;
4881}
4882
fdd7b4c3 4883static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4884{
4885 /* Low hurts. Let's disable the filtering. */
207d6e87 4886 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4887}
4888
6dccd16b
FR		 4889static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4890{
3744100e 4891 static const struct rtl_cfg2_info {
6dccd16b
FR		 4892 u32 mac_version;
4893 u32 clk;
4894 u32 val;
4895 } cfg2_info [] = {
4896 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4897 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4898 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4899 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4900 };
4901 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4902 unsigned int i;
4903 u32 clk;
4904
4905 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4906 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4907 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4908 RTL_W32(0x7c, p->val);
4909 break;
4910 }
4911 }
4912}
4913
e6b763ea
FR		 4914static void rtl_set_rx_mode(struct net_device *dev)
4915{
4916 struct rtl8169_private *tp = netdev_priv(dev);
4917 void __iomem *ioaddr = tp->mmio_addr;
4918 u32 mc_filter[2]; /* Multicast hash filter */
4919 int rx_mode;
4920 u32 tmp = 0;
4921
4922 if (dev->flags & IFF_PROMISC) {
4923 /* Unconditionally log net taps. */
4924 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4925 rx_mode =
4926 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4927 AcceptAllPhys;
4928 mc_filter[1] = mc_filter[0] = 0xffffffff;
4929 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4930 (dev->flags & IFF_ALLMULTI)) {
4931 /* Too many to filter perfectly -- accept all multicasts. */
4932 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4933 mc_filter[1] = mc_filter[0] = 0xffffffff;
4934 } else {
4935 struct netdev_hw_addr *ha;
4936
4937 rx_mode = AcceptBroadcast | AcceptMyPhys;
4938 mc_filter[1] = mc_filter[0] = 0;
4939 netdev_for_each_mc_addr(ha, dev) {
4940 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4941 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4942 rx_mode |= AcceptMulticast;
4943 }
4944 }
4945
4946 if (dev->features & NETIF_F_RXALL)
4947 rx_mode |= (AcceptErr | AcceptRunt);
4948
4949 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4950
4951 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4952 u32 data = mc_filter[0];
4953
4954 mc_filter[0] = swab32(mc_filter[1]);
4955 mc_filter[1] = swab32(data);
4956 }
4957
0481776b
NW		 4958 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4959 mc_filter[1] = mc_filter[0] = 0xffffffff;
4960
e6b763ea
FR		 4961 RTL_W32(MAR0 + 4, mc_filter[1]);
4962 RTL_W32(MAR0 + 0, mc_filter[0]);
4963
4964 RTL_W32(RxConfig, tmp);
4965}
4966
07ce4064
FR		 4967static void rtl_hw_start_8169(struct net_device *dev)
4968{
4969 struct rtl8169_private *tp = netdev_priv(dev);
4970 void __iomem *ioaddr = tp->mmio_addr;
4971 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4972
9cb427b6
FR		 4973 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4974 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4975 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4976 }
4977
1da177e4 4978 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4979 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4980 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4981 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4982 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4983 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4984
e542a226
HW		 4985 rtl_init_rxcfg(tp);
4986
f0298f81 4987 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4988
6f0333b8 4989 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4990
cecb5fd7
FR		 4991 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4992 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4993 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4994 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4995 rtl_set_rx_tx_config_registers(tp);
1da177e4 4996
7f796d83 4997 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4998
cecb5fd7
FR		 4999 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5000 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5001 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5002 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5003 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5004 }
5005
bcf0bf90
FR		 5006 RTL_W16(CPlusCmd, tp->cp_cmd);
5007
6dccd16b
FR		 5008 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5009
1da177e4
LT		 5010 /*
5011 * Undocumented corner. Supposedly:
5012 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5013 */
5014 RTL_W16(IntrMitigate, 0x0000);
5015
7f796d83 5016 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 5017
cecb5fd7
FR		 5018 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5019 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5020 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5021 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 5022 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5023 rtl_set_rx_tx_config_registers(tp);
5024 }
5025
1da177e4 5026 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5027
5028 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5029 RTL_R8(IntrMask);
1da177e4
LT		 5030
5031 RTL_W32(RxMissed, 0);
5032
07ce4064 5033 rtl_set_rx_mode(dev);
1da177e4
LT		 5034
5035 /* no early-rx interrupts */
05b9687b 5036 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5037}
1da177e4 5038
beb1fe18
HW		 5039static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5040{
5041 if (tp->csi_ops.write)
52989f0e 5042 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5043}
5044
5045static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5046{
52989f0e 5047 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5048}
5049
5050static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5051{
5052 u32 csi;
5053
beb1fe18
HW		 5054 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5055 rtl_csi_write(tp, 0x070c, csi | bits);
5056}
5057
5058static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5059{
5060 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5061}
5062
beb1fe18 5063static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5064{
beb1fe18 5065 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5066}
5067
ffc46952
FR		 5068DECLARE_RTL_COND(rtl_csiar_cond)
5069{
5070 void __iomem *ioaddr = tp->mmio_addr;
5071
5072 return RTL_R32(CSIAR) & CSIAR_FLAG;
5073}
5074
52989f0e 5075static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5076{
52989f0e 5077 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5078
5079 RTL_W32(CSIDR, value);
5080 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5081 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5082
ffc46952 5083 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5084}
5085
52989f0e 5086static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5087{
52989f0e 5088 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5089
5090 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5091 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5092
ffc46952
FR		 5093 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5094 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 5095}
5096
52989f0e 5097static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5098{
52989f0e 5099 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5100
5101 RTL_W32(CSIDR, value);
5102 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5103 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5104 CSIAR_FUNC_NIC);
5105
ffc46952 5106 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5107}
5108
52989f0e 5109static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5110{
52989f0e 5111 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5112
5113 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5114 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5115
ffc46952
FR		 5116 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5117 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 5118}
5119
45dd95c4 5120static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5121{
5122 void __iomem *ioaddr = tp->mmio_addr;
5123
5124 RTL_W32(CSIDR, value);
5125 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5126 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5127 CSIAR_FUNC_NIC2);
5128
5129 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5130}
5131
5132static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5133{
5134 void __iomem *ioaddr = tp->mmio_addr;
5135
5136 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5137 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5138
5139 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5140 RTL_R32(CSIDR) : ~0;
5141}
5142
baf63293 5143static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5144{
5145 struct csi_ops *ops = &tp->csi_ops;
5146
5147 switch (tp->mac_version) {
5148 case RTL_GIGA_MAC_VER_01:
5149 case RTL_GIGA_MAC_VER_02:
5150 case RTL_GIGA_MAC_VER_03:
5151 case RTL_GIGA_MAC_VER_04:
5152 case RTL_GIGA_MAC_VER_05:
5153 case RTL_GIGA_MAC_VER_06:
5154 case RTL_GIGA_MAC_VER_10:
5155 case RTL_GIGA_MAC_VER_11:
5156 case RTL_GIGA_MAC_VER_12:
5157 case RTL_GIGA_MAC_VER_13:
5158 case RTL_GIGA_MAC_VER_14:
5159 case RTL_GIGA_MAC_VER_15:
5160 case RTL_GIGA_MAC_VER_16:
5161 case RTL_GIGA_MAC_VER_17:
5162 ops->write = NULL;
5163 ops->read = NULL;
5164 break;
5165
7e18dca1 5166 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5167 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5168 ops->write = r8402_csi_write;
5169 ops->read = r8402_csi_read;
5170 break;
5171
45dd95c4 5172 case RTL_GIGA_MAC_VER_44:
5173 ops->write = r8411_csi_write;
5174 ops->read = r8411_csi_read;
5175 break;
5176
beb1fe18
HW		 5177 default:
5178 ops->write = r8169_csi_write;
5179 ops->read = r8169_csi_read;
5180 break;
5181 }
dacf8154
FR		 5182}
5183
5184struct ephy_info {
5185 unsigned int offset;
5186 u16 mask;
5187 u16 bits;
5188};
5189
fdf6fc06
FR		 5190static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5191 int len)
dacf8154
FR		 5192{
5193 u16 w;
5194
5195 while (len-- > 0) {
fdf6fc06
FR		 5196 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5197 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5198 e++;
5199 }
5200}
5201
b726e493
FR		 5202static void rtl_disable_clock_request(struct pci_dev *pdev)
5203{
7d7903b2
JL		 5204 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5205 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5206}
5207
e6de30d6 5208static void rtl_enable_clock_request(struct pci_dev *pdev)
5209{
7d7903b2
JL		 5210 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5211 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5212}
5213
b51ecea8 5214static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5215{
5216 void __iomem *ioaddr = tp->mmio_addr;
5217 u8 data;
5218
5219 data = RTL_R8(Config3);
5220
5221 if (enable)
5222 data |= Rdy_to_L23;
5223 else
5224 data &= ~Rdy_to_L23;
5225
5226 RTL_W8(Config3, data);
5227}
5228
b726e493
FR		 5229#define R8168_CPCMD_QUIRK_MASK (\
5230 EnableBist | \
5231 Mac_dbgo_oe | \
5232 Force_half_dup | \
5233 Force_rxflow_en | \
5234 Force_txflow_en | \
5235 Cxpl_dbg_sel | \
5236 ASF | \
5237 PktCntrDisable | \
5238 Mac_dbgo_sel)
5239
beb1fe18 5240static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5241{
beb1fe18
HW		 5242 void __iomem *ioaddr = tp->mmio_addr;
5243 struct pci_dev *pdev = tp->pci_dev;
5244
b726e493
FR		 5245 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5246
5247 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5248
faf1e785 5249 if (tp->dev->mtu <= ETH_DATA_LEN) {
5250 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5251 PCI_EXP_DEVCTL_NOSNOOP_EN);
5252 }
219a1e9d
FR		 5253}
5254
beb1fe18 5255static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5256{
beb1fe18
HW		 5257 void __iomem *ioaddr = tp->mmio_addr;
5258
5259 rtl_hw_start_8168bb(tp);
b726e493 5260
f0298f81 5261 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 5262
5263 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 5264}
5265
beb1fe18 5266static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5267{
beb1fe18
HW		 5268 void __iomem *ioaddr = tp->mmio_addr;
5269 struct pci_dev *pdev = tp->pci_dev;
5270
b726e493
FR		 5271 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5272
5273 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5274
faf1e785 5275 if (tp->dev->mtu <= ETH_DATA_LEN)
5276 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 5277
5278 rtl_disable_clock_request(pdev);
5279
5280 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5281}
5282
beb1fe18 5283static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5284{
350f7596 5285 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5286 { 0x01, 0, 0x0001 },
5287 { 0x02, 0x0800, 0x1000 },
5288 { 0x03, 0, 0x0042 },
5289 { 0x06, 0x0080, 0x0000 },
5290 { 0x07, 0, 0x2000 }
5291 };
5292
beb1fe18 5293 rtl_csi_access_enable_2(tp);
b726e493 5294
fdf6fc06 5295 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5296
beb1fe18 5297 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5298}
5299
beb1fe18 5300static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5301{
beb1fe18
HW		 5302 void __iomem *ioaddr = tp->mmio_addr;
5303 struct pci_dev *pdev = tp->pci_dev;
5304
5305 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 5306
5307 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5308
faf1e785 5309 if (tp->dev->mtu <= ETH_DATA_LEN)
5310 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 5311
5312 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5313}
5314
beb1fe18 5315static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5316{
beb1fe18
HW		 5317 void __iomem *ioaddr = tp->mmio_addr;
5318 struct pci_dev *pdev = tp->pci_dev;
5319
5320 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 5321
5322 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5323
5324 /* Magic. */
5325 RTL_W8(DBG_REG, 0x20);
5326
f0298f81 5327 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5328
faf1e785 5329 if (tp->dev->mtu <= ETH_DATA_LEN)
5330 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5331
5332 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5333}
5334
beb1fe18 5335static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5336{
beb1fe18 5337 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5338 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5339 { 0x02, 0x0800, 0x1000 },
5340 { 0x03, 0, 0x0002 },
5341 { 0x06, 0x0080, 0x0000 }
5342 };
5343
beb1fe18 5344 rtl_csi_access_enable_2(tp);
b726e493
FR		 5345
5346 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5347
fdf6fc06 5348 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5349
beb1fe18 5350 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5351}
5352
beb1fe18 5353static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5354{
350f7596 5355 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5356 { 0x01, 0, 0x0001 },
5357 { 0x03, 0x0400, 0x0220 }
5358 };
5359
beb1fe18 5360 rtl_csi_access_enable_2(tp);
b726e493 5361
fdf6fc06 5362 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5363
beb1fe18 5364 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5365}
5366
beb1fe18 5367static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5368{
beb1fe18 5369 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5370}
5371
beb1fe18 5372static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5373{
beb1fe18 5374 rtl_csi_access_enable_2(tp);
6fb07058 5375
beb1fe18 5376 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5377}
5378
beb1fe18 5379static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5380{
beb1fe18
HW		 5381 void __iomem *ioaddr = tp->mmio_addr;
5382 struct pci_dev *pdev = tp->pci_dev;
5383
5384 rtl_csi_access_enable_2(tp);
5b538df9
FR		 5385
5386 rtl_disable_clock_request(pdev);
5387
f0298f81 5388 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 5389
faf1e785 5390 if (tp->dev->mtu <= ETH_DATA_LEN)
5391 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 5392
5393 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5394}
5395
beb1fe18 5396static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5397{
beb1fe18
HW		 5398 void __iomem *ioaddr = tp->mmio_addr;
5399 struct pci_dev *pdev = tp->pci_dev;
5400
5401 rtl_csi_access_enable_1(tp);
4804b3b3 5402
faf1e785 5403 if (tp->dev->mtu <= ETH_DATA_LEN)
5404 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 5405
5406 RTL_W8(MaxTxPacketSize, TxPacketMax);
5407
5408 rtl_disable_clock_request(pdev);
5409}
5410
beb1fe18 5411static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5412{
beb1fe18
HW		 5413 void __iomem *ioaddr = tp->mmio_addr;
5414 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 5415 static const struct ephy_info e_info_8168d_4[] = {
5416 { 0x0b, ~0, 0x48 },
5417 { 0x19, 0x20, 0x50 },
5418 { 0x0c, ~0, 0x20 }
5419 };
5420 int i;
5421
beb1fe18 5422 rtl_csi_access_enable_1(tp);
e6de30d6 5423
5424 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5425
5426 RTL_W8(MaxTxPacketSize, TxPacketMax);
5427
5428 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5429 const struct ephy_info *e = e_info_8168d_4 + i;
5430 u16 w;
5431
fdf6fc06
FR		 5432 w = rtl_ephy_read(tp, e->offset);
5433 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 5434 }
5435
5436 rtl_enable_clock_request(pdev);
5437}
5438
beb1fe18 5439static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5440{
beb1fe18
HW		 5441 void __iomem *ioaddr = tp->mmio_addr;
5442 struct pci_dev *pdev = tp->pci_dev;
70090424 5443 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5444 { 0x00, 0x0200, 0x0100 },
5445 { 0x00, 0x0000, 0x0004 },
5446 { 0x06, 0x0002, 0x0001 },
5447 { 0x06, 0x0000, 0x0030 },
5448 { 0x07, 0x0000, 0x2000 },
5449 { 0x00, 0x0000, 0x0020 },
5450 { 0x03, 0x5800, 0x2000 },
5451 { 0x03, 0x0000, 0x0001 },
5452 { 0x01, 0x0800, 0x1000 },
5453 { 0x07, 0x0000, 0x4000 },
5454 { 0x1e, 0x0000, 0x2000 },
5455 { 0x19, 0xffff, 0xfe6c },
5456 { 0x0a, 0x0000, 0x0040 }
5457 };
5458
beb1fe18 5459 rtl_csi_access_enable_2(tp);
01dc7fec 5460
fdf6fc06 5461 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5462
faf1e785 5463 if (tp->dev->mtu <= ETH_DATA_LEN)
5464 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5465
5466 RTL_W8(MaxTxPacketSize, TxPacketMax);
5467
5468 rtl_disable_clock_request(pdev);
5469
5470 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5471 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5472 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5473
cecb5fd7 5474 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5475}
5476
beb1fe18 5477static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5478{
beb1fe18
HW		 5479 void __iomem *ioaddr = tp->mmio_addr;
5480 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5481 static const struct ephy_info e_info_8168e_2[] = {
5482 { 0x09, 0x0000, 0x0080 },
5483 { 0x19, 0x0000, 0x0224 }
5484 };
5485
beb1fe18 5486 rtl_csi_access_enable_1(tp);
70090424 5487
fdf6fc06 5488 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5489
faf1e785 5490 if (tp->dev->mtu <= ETH_DATA_LEN)
5491 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5492
fdf6fc06
FR		 5493 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5494 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5495 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5496 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5497 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5498 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5499 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5500 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5501
3090bd9a 5502 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5503
4521e1a9
FR		 5504 rtl_disable_clock_request(pdev);
5505
70090424
HW		 5506 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5507 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5508
5509 /* Adjust EEE LED frequency */
5510 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5511
5512 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5513 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5514 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5515}
5516
5f886e08 5517static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5518{
beb1fe18
HW		 5519 void __iomem *ioaddr = tp->mmio_addr;
5520 struct pci_dev *pdev = tp->pci_dev;
c2218925 5521
5f886e08 5522 rtl_csi_access_enable_2(tp);
c2218925
HW		 5523
5524 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5525
fdf6fc06
FR		 5526 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5527 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5528 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5529 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5530 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5531 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5532 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5533 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5534 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5535 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5536
5537 RTL_W8(MaxTxPacketSize, EarlySize);
5538
4521e1a9
FR		 5539 rtl_disable_clock_request(pdev);
5540
c2218925
HW		 5541 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5542 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5543 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5544 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5545 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5546}
5547
5f886e08
HW		 5548static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5549{
5550 void __iomem *ioaddr = tp->mmio_addr;
5551 static const struct ephy_info e_info_8168f_1[] = {
5552 { 0x06, 0x00c0, 0x0020 },
5553 { 0x08, 0x0001, 0x0002 },
5554 { 0x09, 0x0000, 0x0080 },
5555 { 0x19, 0x0000, 0x0224 }
5556 };
5557
5558 rtl_hw_start_8168f(tp);
5559
fdf6fc06 5560 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5561
706123d0 5562 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5563
5564 /* Adjust EEE LED frequency */
5565 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5566}
5567
b3d7b2f2
HW		 5568static void rtl_hw_start_8411(struct rtl8169_private *tp)
5569{
b3d7b2f2
HW		 5570 static const struct ephy_info e_info_8168f_1[] = {
5571 { 0x06, 0x00c0, 0x0020 },
5572 { 0x0f, 0xffff, 0x5200 },
5573 { 0x1e, 0x0000, 0x4000 },
5574 { 0x19, 0x0000, 0x0224 }
5575 };
5576
5577 rtl_hw_start_8168f(tp);
b51ecea8 5578 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5579
fdf6fc06 5580 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5581
706123d0 5582 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5583}
5584
c558386b
HW		 5585static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5586{
5587 void __iomem *ioaddr = tp->mmio_addr;
5588 struct pci_dev *pdev = tp->pci_dev;
5589
beb330a4 5590 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5591
c558386b
HW		 5592 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5593 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5594 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5595 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5596
5597 rtl_csi_access_enable_1(tp);
5598
5599 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5600
706123d0
CHL		 5601 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5602 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5603 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b
HW		 5604
5605 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4521e1a9 5606 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 5607 RTL_W8(MaxTxPacketSize, EarlySize);
5608
5609 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5610 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5611
5612 /* Adjust EEE LED frequency */
5613 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5614
706123d0
CHL		 5615 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5616 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5617
5618 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5619}
5620
57538c4a 5621static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5622{
5623 void __iomem *ioaddr = tp->mmio_addr;
5624 static const struct ephy_info e_info_8168g_2[] = {
5625 { 0x00, 0x0000, 0x0008 },
5626 { 0x0c, 0x3df0, 0x0200 },
5627 { 0x19, 0xffff, 0xfc00 },
5628 { 0x1e, 0xffff, 0x20eb }
5629 };
5630
5631 rtl_hw_start_8168g_1(tp);
5632
5633 /* disable aspm and clock request before access ephy */
5634 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5635 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5636 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5637}
5638
45dd95c4 5639static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5640{
5641 void __iomem *ioaddr = tp->mmio_addr;
5642 static const struct ephy_info e_info_8411_2[] = {
5643 { 0x00, 0x0000, 0x0008 },
5644 { 0x0c, 0x3df0, 0x0200 },
5645 { 0x0f, 0xffff, 0x5200 },
5646 { 0x19, 0x0020, 0x0000 },
5647 { 0x1e, 0x0000, 0x2000 }
5648 };
5649
5650 rtl_hw_start_8168g_1(tp);
5651
5652 /* disable aspm and clock request before access ephy */
5653 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5654 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5655 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5656}
5657
6e1d0b89
CHL		 5658static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5659{
5660 void __iomem *ioaddr = tp->mmio_addr;
5661 struct pci_dev *pdev = tp->pci_dev;
5662 u16 rg_saw_cnt;
5663 u32 data;
5664 static const struct ephy_info e_info_8168h_1[] = {
5665 { 0x1e, 0x0800, 0x0001 },
5666 { 0x1d, 0x0000, 0x0800 },
5667 { 0x05, 0xffff, 0x2089 },
5668 { 0x06, 0xffff, 0x5881 },
5669 { 0x04, 0xffff, 0x154a },
5670 { 0x01, 0xffff, 0x068b }
5671 };
5672
5673 /* disable aspm and clock request before access ephy */
5674 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5675 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5676 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5677
5678 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5679
5680 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5681 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5682 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5683 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5684
5685 rtl_csi_access_enable_1(tp);
5686
5687 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5688
706123d0
CHL		 5689 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5690 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 5691
706123d0 5692 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 5693
706123d0 5694 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 5695
5696 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5697
5698 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5699 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5700 RTL_W8(MaxTxPacketSize, EarlySize);
5701
5702 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5703 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5704
5705 /* Adjust EEE LED frequency */
5706 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5707
5708 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5709 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
5710
5711 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
5712
706123d0 5713 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 5714
5715 rtl_pcie_state_l2l3_enable(tp, false);
5716
5717 rtl_writephy(tp, 0x1f, 0x0c42);
5718 rg_saw_cnt = rtl_readphy(tp, 0x13);
5719 rtl_writephy(tp, 0x1f, 0x0000);
5720 if (rg_saw_cnt > 0) {
5721 u16 sw_cnt_1ms_ini;
5722
5723 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5724 sw_cnt_1ms_ini &= 0x0fff;
5725 data = r8168_mac_ocp_read(tp, 0xd412);
5726 data &= 0x0fff;
5727 data |= sw_cnt_1ms_ini;
5728 r8168_mac_ocp_write(tp, 0xd412, data);
5729 }
5730
5731 data = r8168_mac_ocp_read(tp, 0xe056);
5732 data &= 0xf0;
5733 data |= 0x07;
5734 r8168_mac_ocp_write(tp, 0xe056, data);
5735
5736 data = r8168_mac_ocp_read(tp, 0xe052);
5737 data &= 0x8008;
5738 data |= 0x6000;
5739 r8168_mac_ocp_write(tp, 0xe052, data);
5740
5741 data = r8168_mac_ocp_read(tp, 0xe0d6);
5742 data &= 0x01ff;
5743 data |= 0x017f;
5744 r8168_mac_ocp_write(tp, 0xe0d6, data);
5745
5746 data = r8168_mac_ocp_read(tp, 0xd420);
5747 data &= 0x0fff;
5748 data |= 0x047f;
5749 r8168_mac_ocp_write(tp, 0xd420, data);
5750
5751 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5752 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5753 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5754 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5755}
5756
07ce4064
FR		 5757static void rtl_hw_start_8168(struct net_device *dev)
5758{
2dd99530
FR		 5759 struct rtl8169_private *tp = netdev_priv(dev);
5760 void __iomem *ioaddr = tp->mmio_addr;
5761
5762 RTL_W8(Cfg9346, Cfg9346_Unlock);
5763
f0298f81 5764 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5765
6f0333b8 5766 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5767
0e485150 5768 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5769
5770 RTL_W16(CPlusCmd, tp->cp_cmd);
5771
0e485150 5772 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5773
0e485150 5774 /* Work around for RxFIFO overflow. */
811fd301 5775 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5776 tp->event_slow |= RxFIFOOver | PCSTimeout;
5777 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5778 }
5779
5780 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5781
1a964649 5782 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 5783
5784 RTL_R8(IntrMask);
5785
219a1e9d
FR		 5786 switch (tp->mac_version) {
5787 case RTL_GIGA_MAC_VER_11:
beb1fe18 5788 rtl_hw_start_8168bb(tp);
4804b3b3 5789 break;
219a1e9d
FR		 5790
5791 case RTL_GIGA_MAC_VER_12:
5792 case RTL_GIGA_MAC_VER_17:
beb1fe18 5793 rtl_hw_start_8168bef(tp);
4804b3b3 5794 break;
219a1e9d
FR		 5795
5796 case RTL_GIGA_MAC_VER_18:
beb1fe18 5797 rtl_hw_start_8168cp_1(tp);
4804b3b3 5798 break;
219a1e9d
FR		 5799
5800 case RTL_GIGA_MAC_VER_19:
beb1fe18 5801 rtl_hw_start_8168c_1(tp);
4804b3b3 5802 break;
219a1e9d
FR		 5803
5804 case RTL_GIGA_MAC_VER_20:
beb1fe18 5805 rtl_hw_start_8168c_2(tp);
4804b3b3 5806 break;
219a1e9d 5807
197ff761 5808 case RTL_GIGA_MAC_VER_21:
beb1fe18 5809 rtl_hw_start_8168c_3(tp);
4804b3b3 5810 break;
197ff761 5811
6fb07058 5812 case RTL_GIGA_MAC_VER_22:
beb1fe18 5813 rtl_hw_start_8168c_4(tp);
4804b3b3 5814 break;
6fb07058 5815
ef3386f0 5816 case RTL_GIGA_MAC_VER_23:
beb1fe18 5817 rtl_hw_start_8168cp_2(tp);
4804b3b3 5818 break;
ef3386f0 5819
7f3e3d3a 5820 case RTL_GIGA_MAC_VER_24:
beb1fe18 5821 rtl_hw_start_8168cp_3(tp);
4804b3b3 5822 break;
7f3e3d3a 5823
5b538df9 5824 case RTL_GIGA_MAC_VER_25:
daf9df6d 5825 case RTL_GIGA_MAC_VER_26:
5826 case RTL_GIGA_MAC_VER_27:
beb1fe18 5827 rtl_hw_start_8168d(tp);
4804b3b3 5828 break;
5b538df9 5829
e6de30d6 5830 case RTL_GIGA_MAC_VER_28:
beb1fe18 5831 rtl_hw_start_8168d_4(tp);
4804b3b3 5832 break;
cecb5fd7 5833
4804b3b3 5834 case RTL_GIGA_MAC_VER_31:
beb1fe18 5835 rtl_hw_start_8168dp(tp);
4804b3b3 5836 break;
5837
01dc7fec 5838 case RTL_GIGA_MAC_VER_32:
5839 case RTL_GIGA_MAC_VER_33:
beb1fe18 5840 rtl_hw_start_8168e_1(tp);
70090424
HW		 5841 break;
5842 case RTL_GIGA_MAC_VER_34:
beb1fe18 5843 rtl_hw_start_8168e_2(tp);
01dc7fec 5844 break;
e6de30d6 5845
c2218925
HW		 5846 case RTL_GIGA_MAC_VER_35:
5847 case RTL_GIGA_MAC_VER_36:
beb1fe18 5848 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5849 break;
5850
b3d7b2f2
HW		 5851 case RTL_GIGA_MAC_VER_38:
5852 rtl_hw_start_8411(tp);
5853 break;
5854
c558386b
HW		 5855 case RTL_GIGA_MAC_VER_40:
5856 case RTL_GIGA_MAC_VER_41:
5857 rtl_hw_start_8168g_1(tp);
5858 break;
57538c4a 5859 case RTL_GIGA_MAC_VER_42:
5860 rtl_hw_start_8168g_2(tp);
5861 break;
c558386b 5862
45dd95c4 5863 case RTL_GIGA_MAC_VER_44:
5864 rtl_hw_start_8411_2(tp);
5865 break;
5866
6e1d0b89
CHL		 5867 case RTL_GIGA_MAC_VER_45:
5868 case RTL_GIGA_MAC_VER_46:
5869 rtl_hw_start_8168h_1(tp);
5870 break;
5871
219a1e9d
FR		 5872 default:
5873 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5874 dev->name, tp->mac_version);
4804b3b3 5875 break;
219a1e9d 5876 }
2dd99530 5877
1a964649 5878 RTL_W8(Cfg9346, Cfg9346_Lock);
5879
0e485150
FR		 5880 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5881
1a964649 5882 rtl_set_rx_mode(dev);
b8363901 5883
05b9687b 5884 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5885}
1da177e4 5886
2857ffb7
FR		 5887#define R810X_CPCMD_QUIRK_MASK (\
5888 EnableBist | \
5889 Mac_dbgo_oe | \
5890 Force_half_dup | \
5edcc537 5891 Force_rxflow_en | \
2857ffb7
FR		 5892 Force_txflow_en | \
5893 Cxpl_dbg_sel | \
5894 ASF | \
5895 PktCntrDisable | \
d24e9aaf 5896 Mac_dbgo_sel)
2857ffb7 5897
beb1fe18 5898static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5899{
beb1fe18
HW		 5900 void __iomem *ioaddr = tp->mmio_addr;
5901 struct pci_dev *pdev = tp->pci_dev;
350f7596 5902 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5903 { 0x01, 0, 0x6e65 },
5904 { 0x02, 0, 0x091f },
5905 { 0x03, 0, 0xc2f9 },
5906 { 0x06, 0, 0xafb5 },
5907 { 0x07, 0, 0x0e00 },
5908 { 0x19, 0, 0xec80 },
5909 { 0x01, 0, 0x2e65 },
5910 { 0x01, 0, 0x6e65 }
5911 };
5912 u8 cfg1;
5913
beb1fe18 5914 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5915
5916 RTL_W8(DBG_REG, FIX_NAK_1);
5917
5918 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5919
5920 RTL_W8(Config1,
5921 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5922 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5923
5924 cfg1 = RTL_R8(Config1);
5925 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5926 RTL_W8(Config1, cfg1 & ~LEDS0);
5927
fdf6fc06 5928 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5929}
5930
beb1fe18 5931static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5932{
beb1fe18
HW		 5933 void __iomem *ioaddr = tp->mmio_addr;
5934 struct pci_dev *pdev = tp->pci_dev;
5935
5936 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5937
5938 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5939
5940 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5941 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5942}
5943
beb1fe18 5944static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5945{
beb1fe18 5946 rtl_hw_start_8102e_2(tp);
2857ffb7 5947
fdf6fc06 5948 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5949}
5950
beb1fe18 5951static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5952{
beb1fe18 5953 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5954 static const struct ephy_info e_info_8105e_1[] = {
5955 { 0x07, 0, 0x4000 },
5956 { 0x19, 0, 0x0200 },
5957 { 0x19, 0, 0x0020 },
5958 { 0x1e, 0, 0x2000 },
5959 { 0x03, 0, 0x0001 },
5960 { 0x19, 0, 0x0100 },
5961 { 0x19, 0, 0x0004 },
5962 { 0x0a, 0, 0x0020 }
5963 };
5964
cecb5fd7 5965 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5966 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5967
cecb5fd7 5968 /* Disable Early Tally Counter */
5a5e4443
HW		 5969 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5970
5971 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5972 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5973
fdf6fc06 5974 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5975
5976 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5977}
5978
beb1fe18 5979static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5980{
beb1fe18 5981 rtl_hw_start_8105e_1(tp);
fdf6fc06 5982 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5983}
5984
7e18dca1
HW		 5985static void rtl_hw_start_8402(struct rtl8169_private *tp)
5986{
5987 void __iomem *ioaddr = tp->mmio_addr;
5988 static const struct ephy_info e_info_8402[] = {
5989 { 0x19, 0xffff, 0xff64 },
5990 { 0x1e, 0, 0x4000 }
5991 };
5992
5993 rtl_csi_access_enable_2(tp);
5994
5995 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5996 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5997
5998 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5999 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6000
fdf6fc06 6001 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 6002
6003 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6004
fdf6fc06
FR		 6005 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6006 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6007 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6008 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6009 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6010 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6011 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6012
6013 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6014}
6015
5598bfe5
HW		 6016static void rtl_hw_start_8106(struct rtl8169_private *tp)
6017{
6018 void __iomem *ioaddr = tp->mmio_addr;
6019
6020 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6021 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6022
4521e1a9 6023 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 6024 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6025 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 6026
6027 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6028}
6029
07ce4064
FR		 6030static void rtl_hw_start_8101(struct net_device *dev)
6031{
cdf1a608
FR		 6032 struct rtl8169_private *tp = netdev_priv(dev);
6033 void __iomem *ioaddr = tp->mmio_addr;
6034 struct pci_dev *pdev = tp->pci_dev;
6035
da78dbff
FR		 6036 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6037 tp->event_slow &= ~RxFIFOOver;
811fd301 6038
cecb5fd7 6039 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6040 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6041 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6042 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6043
d24e9aaf
HW		 6044 RTL_W8(Cfg9346, Cfg9346_Unlock);
6045
1a964649 6046 RTL_W8(MaxTxPacketSize, TxPacketMax);
6047
6048 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6049
6050 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6051 RTL_W16(CPlusCmd, tp->cp_cmd);
6052
6053 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6054
6055 rtl_set_rx_tx_config_registers(tp);
6056
2857ffb7
FR		 6057 switch (tp->mac_version) {
6058 case RTL_GIGA_MAC_VER_07:
beb1fe18 6059 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6060 break;
6061
6062 case RTL_GIGA_MAC_VER_08:
beb1fe18 6063 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6064 break;
6065
6066 case RTL_GIGA_MAC_VER_09:
beb1fe18 6067 rtl_hw_start_8102e_2(tp);
2857ffb7 6068 break;
5a5e4443
HW		 6069
6070 case RTL_GIGA_MAC_VER_29:
beb1fe18 6071 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6072 break;
6073 case RTL_GIGA_MAC_VER_30:
beb1fe18 6074 rtl_hw_start_8105e_2(tp);
5a5e4443 6075 break;
7e18dca1
HW		 6076
6077 case RTL_GIGA_MAC_VER_37:
6078 rtl_hw_start_8402(tp);
6079 break;
5598bfe5
HW		 6080
6081 case RTL_GIGA_MAC_VER_39:
6082 rtl_hw_start_8106(tp);
6083 break;
58152cd4 6084 case RTL_GIGA_MAC_VER_43:
6085 rtl_hw_start_8168g_2(tp);
6086 break;
6e1d0b89
CHL		 6087 case RTL_GIGA_MAC_VER_47:
6088 case RTL_GIGA_MAC_VER_48:
6089 rtl_hw_start_8168h_1(tp);
6090 break;
cdf1a608
FR		 6091 }
6092
d24e9aaf 6093 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 6094
cdf1a608
FR		 6095 RTL_W16(IntrMitigate, 0x0000);
6096
cdf1a608 6097 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6098
cdf1a608
FR		 6099 rtl_set_rx_mode(dev);
6100
1a964649 6101 RTL_R8(IntrMask);
6102
cdf1a608 6103 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 6104}
6105
6106static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6107{
d58d46b5
FR		 6108 struct rtl8169_private *tp = netdev_priv(dev);
6109
6110 if (new_mtu < ETH_ZLEN ||
6111 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 6112 return -EINVAL;
6113
d58d46b5
FR		 6114 if (new_mtu > ETH_DATA_LEN)
6115 rtl_hw_jumbo_enable(tp);
6116 else
6117 rtl_hw_jumbo_disable(tp);
6118
1da177e4 6119 dev->mtu = new_mtu;
350fb32a
MM		 6120 netdev_update_features(dev);
6121
323bb685 6122 return 0;
1da177e4
LT		 6123}
6124
6125static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6126{
95e0918d 6127 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6128 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6129}
6130
6f0333b8
ED		 6131static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6132 void **data_buff, struct RxDesc *desc)
1da177e4 6133{
48addcc9 6134 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 6135 DMA_FROM_DEVICE);
48addcc9 6136
6f0333b8
ED		 6137 kfree(*data_buff);
6138 *data_buff = NULL;
1da177e4
LT		 6139 rtl8169_make_unusable_by_asic(desc);
6140}
6141
6142static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6143{
6144 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6145
6146 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6147}
6148
6149static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6150 u32 rx_buf_sz)
6151{
6152 desc->addr = cpu_to_le64(mapping);
6153 wmb();
6154 rtl8169_mark_to_asic(desc, rx_buf_sz);
6155}
6156
6f0333b8
ED		 6157static inline void *rtl8169_align(void *data)
6158{
6159 return (void *)ALIGN((long)data, 16);
6160}
6161
0ecbe1ca
SG		 6162static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6163 struct RxDesc *desc)
1da177e4 6164{
6f0333b8 6165 void *data;
1da177e4 6166 dma_addr_t mapping;
48addcc9 6167 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 6168 struct net_device *dev = tp->dev;
6f0333b8 6169 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 6170
6f0333b8
ED		 6171 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6172 if (!data)
6173 return NULL;
e9f63f30 6174
6f0333b8
ED		 6175 if (rtl8169_align(data) != data) {
6176 kfree(data);
6177 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6178 if (!data)
6179 return NULL;
6180 }
3eafe507 6181
48addcc9 6182 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 6183 DMA_FROM_DEVICE);
d827d86b
SG		 6184 if (unlikely(dma_mapping_error(d, mapping))) {
6185 if (net_ratelimit())
6186 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6187 goto err_out;
d827d86b 6188 }
1da177e4
LT		 6189
6190 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 6191 return data;
3eafe507
SG		 6192
6193err_out:
6194 kfree(data);
6195 return NULL;
1da177e4
LT		 6196}
6197
6198static void rtl8169_rx_clear(struct rtl8169_private *tp)
6199{
07d3f51f 6200 unsigned int i;
1da177e4
LT		 6201
6202 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6203 if (tp->Rx_databuff[i]) {
6204 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6205 tp->RxDescArray + i);
6206 }
6207 }
6208}
6209
0ecbe1ca 6210static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6211{
0ecbe1ca
SG		 6212 desc->opts1 |= cpu_to_le32(RingEnd);
6213}
5b0384f4 6214
0ecbe1ca
SG		 6215static int rtl8169_rx_fill(struct rtl8169_private *tp)
6216{
6217 unsigned int i;
1da177e4 6218
0ecbe1ca
SG		 6219 for (i = 0; i < NUM_RX_DESC; i++) {
6220 void *data;
4ae47c2d 6221
6f0333b8 6222 if (tp->Rx_databuff[i])
1da177e4 6223 continue;
bcf0bf90 6224
0ecbe1ca 6225 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6226 if (!data) {
6227 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6228 goto err_out;
6f0333b8
ED		 6229 }
6230 tp->Rx_databuff[i] = data;
1da177e4 6231 }
1da177e4 6232
0ecbe1ca
SG		 6233 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6234 return 0;
6235
6236err_out:
6237 rtl8169_rx_clear(tp);
6238 return -ENOMEM;
1da177e4
LT		 6239}
6240
1da177e4
LT		 6241static int rtl8169_init_ring(struct net_device *dev)
6242{
6243 struct rtl8169_private *tp = netdev_priv(dev);
6244
6245 rtl8169_init_ring_indexes(tp);
6246
6247 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 6248 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 6249
0ecbe1ca 6250 return rtl8169_rx_fill(tp);
1da177e4
LT		 6251}
6252
48addcc9 6253static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6254 struct TxDesc *desc)
6255{
6256 unsigned int len = tx_skb->len;
6257
48addcc9
SG		 6258 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6259
1da177e4
LT		 6260 desc->opts1 = 0x00;
6261 desc->opts2 = 0x00;
6262 desc->addr = 0x00;
6263 tx_skb->len = 0;
6264}
6265
3eafe507
SG		 6266static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6267 unsigned int n)
1da177e4
LT		 6268{
6269 unsigned int i;
6270
3eafe507
SG		 6271 for (i = 0; i < n; i++) {
6272 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6273 struct ring_info *tx_skb = tp->tx_skb + entry;
6274 unsigned int len = tx_skb->len;
6275
6276 if (len) {
6277 struct sk_buff *skb = tx_skb->skb;
6278
48addcc9 6279 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 6280 tp->TxDescArray + entry);
6281 if (skb) {
cac4b22f 6282 tp->dev->stats.tx_dropped++;
989c9ba1 6283 dev_kfree_skb_any(skb);
1da177e4
LT		 6284 tx_skb->skb = NULL;
6285 }
1da177e4
LT		 6286 }
6287 }
3eafe507
SG		 6288}
6289
6290static void rtl8169_tx_clear(struct rtl8169_private *tp)
6291{
6292 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6293 tp->cur_tx = tp->dirty_tx = 0;
6294}
6295
4422bcd4 6296static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6297{
c4028958 6298 struct net_device *dev = tp->dev;
56de414c 6299 int i;
1da177e4 6300
da78dbff
FR		 6301 napi_disable(&tp->napi);
6302 netif_stop_queue(dev);
6303 synchronize_sched();
1da177e4 6304
c7c2c39b 6305 rtl8169_hw_reset(tp);
6306
56de414c
FR		 6307 for (i = 0; i < NUM_RX_DESC; i++)
6308 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6309
1da177e4 6310 rtl8169_tx_clear(tp);
c7c2c39b 6311 rtl8169_init_ring_indexes(tp);
1da177e4 6312
da78dbff 6313 napi_enable(&tp->napi);
56de414c
FR		 6314 rtl_hw_start(dev);
6315 netif_wake_queue(dev);
6316 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 6317}
6318
6319static void rtl8169_tx_timeout(struct net_device *dev)
6320{
da78dbff
FR		 6321 struct rtl8169_private *tp = netdev_priv(dev);
6322
6323 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6324}
6325
6326static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6327 u32 *opts)
1da177e4
LT		 6328{
6329 struct skb_shared_info *info = skb_shinfo(skb);
6330 unsigned int cur_frag, entry;
6e1d0b89 6331 struct TxDesc *uninitialized_var(txd);
48addcc9 6332 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6333
6334 entry = tp->cur_tx;
6335 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6336 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6337 dma_addr_t mapping;
6338 u32 status, len;
6339 void *addr;
6340
6341 entry = (entry + 1) % NUM_TX_DESC;
6342
6343 txd = tp->TxDescArray + entry;
9e903e08 6344 len = skb_frag_size(frag);
929f6189 6345 addr = skb_frag_address(frag);
48addcc9 6346 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6347 if (unlikely(dma_mapping_error(d, mapping))) {
6348 if (net_ratelimit())
6349 netif_err(tp, drv, tp->dev,
6350 "Failed to map TX fragments DMA!\n");
3eafe507 6351 goto err_out;
d827d86b 6352 }
1da177e4 6353
cecb5fd7 6354 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6355 status = opts[0] | len |
6356 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6357
6358 txd->opts1 = cpu_to_le32(status);
2b7b4318 6359 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6360 txd->addr = cpu_to_le64(mapping);
6361
6362 tp->tx_skb[entry].len = len;
6363 }
6364
6365 if (cur_frag) {
6366 tp->tx_skb[entry].skb = skb;
6367 txd->opts1 |= cpu_to_le32(LastFrag);
6368 }
6369
6370 return cur_frag;
3eafe507
SG		 6371
6372err_out:
6373 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6374 return -EIO;
1da177e4
LT		 6375}
6376
b423e9ae 6377static bool rtl_skb_pad(struct sk_buff *skb)
6378{
6379 if (skb_padto(skb, ETH_ZLEN))
6380 return false;
6381 skb_put(skb, ETH_ZLEN - skb->len);
6382 return true;
6383}
6384
6385static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6386{
6387 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6388}
6389
e974604b 6390static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6391 struct net_device *dev);
6392/* r8169_csum_workaround()
6393 * The hw limites the value the transport offset. When the offset is out of the
6394 * range, calculate the checksum by sw.
6395 */
6396static void r8169_csum_workaround(struct rtl8169_private *tp,
6397 struct sk_buff *skb)
6398{
6399 if (skb_shinfo(skb)->gso_size) {
6400 netdev_features_t features = tp->dev->features;
6401 struct sk_buff *segs, *nskb;
6402
6403 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6404 segs = skb_gso_segment(skb, features);
6405 if (IS_ERR(segs) || !segs)
6406 goto drop;
6407
6408 do {
6409 nskb = segs;
6410 segs = segs->next;
6411 nskb->next = NULL;
6412 rtl8169_start_xmit(nskb, tp->dev);
6413 } while (segs);
6414
6415 dev_kfree_skb(skb);
6416 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6417 if (skb_checksum_help(skb) < 0)
6418 goto drop;
6419
6420 rtl8169_start_xmit(skb, tp->dev);
6421 } else {
6422 struct net_device_stats *stats;
6423
6424drop:
6425 stats = &tp->dev->stats;
6426 stats->tx_dropped++;
6427 dev_kfree_skb(skb);
6428 }
6429}
6430
6431/* msdn_giant_send_check()
6432 * According to the document of microsoft, the TCP Pseudo Header excludes the
6433 * packet length for IPv6 TCP large packets.
6434 */
6435static int msdn_giant_send_check(struct sk_buff *skb)
6436{
6437 const struct ipv6hdr *ipv6h;
6438 struct tcphdr *th;
6439 int ret;
6440
6441 ret = skb_cow_head(skb, 0);
6442 if (ret)
6443 return ret;
6444
6445 ipv6h = ipv6_hdr(skb);
6446 th = tcp_hdr(skb);
6447
6448 th->check = 0;
6449 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6450
6451 return ret;
6452}
6453
6454static inline __be16 get_protocol(struct sk_buff *skb)
6455{
6456 __be16 protocol;
6457
6458 if (skb->protocol == htons(ETH_P_8021Q))
6459 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6460 else
6461 protocol = skb->protocol;
6462
6463 return protocol;
6464}
6465
5888d3fc 6466static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6467 struct sk_buff *skb, u32 *opts)
1da177e4 6468{
350fb32a
MM		 6469 u32 mss = skb_shinfo(skb)->gso_size;
6470
2b7b4318
FR		 6471 if (mss) {
6472 opts[0] |= TD_LSO;
5888d3fc 6473 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6474 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6475 const struct iphdr *ip = ip_hdr(skb);
6476
6477 if (ip->protocol == IPPROTO_TCP)
6478 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6479 else if (ip->protocol == IPPROTO_UDP)
6480 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6481 else
6482 WARN_ON_ONCE(1);
6483 }
6484
6485 return true;
6486}
6487
6488static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6489 struct sk_buff *skb, u32 *opts)
6490{
bdfa4ed6 6491 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6492 u32 mss = skb_shinfo(skb)->gso_size;
6493
6494 if (mss) {
e974604b 6495 if (transport_offset > GTTCPHO_MAX) {
6496 netif_warn(tp, tx_err, tp->dev,
6497 "Invalid transport offset 0x%x for TSO\n",
6498 transport_offset);
6499 return false;
6500 }
6501
6502 switch (get_protocol(skb)) {
6503 case htons(ETH_P_IP):
6504 opts[0] |= TD1_GTSENV4;
6505 break;
6506
6507 case htons(ETH_P_IPV6):
6508 if (msdn_giant_send_check(skb))
6509 return false;
6510
6511 opts[0] |= TD1_GTSENV6;
6512 break;
6513
6514 default:
6515 WARN_ON_ONCE(1);
6516 break;
6517 }
6518
bdfa4ed6 6519 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6520 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6521 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6522 u8 ip_protocol;
1da177e4 6523
b423e9ae 6524 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6525 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
6526
e974604b 6527 if (transport_offset > TCPHO_MAX) {
6528 netif_warn(tp, tx_err, tp->dev,
6529 "Invalid transport offset 0x%x\n",
6530 transport_offset);
6531 return false;
6532 }
6533
6534 switch (get_protocol(skb)) {
6535 case htons(ETH_P_IP):
6536 opts[1] |= TD1_IPv4_CS;
6537 ip_protocol = ip_hdr(skb)->protocol;
6538 break;
6539
6540 case htons(ETH_P_IPV6):
6541 opts[1] |= TD1_IPv6_CS;
6542 ip_protocol = ipv6_hdr(skb)->nexthdr;
6543 break;
6544
6545 default:
6546 ip_protocol = IPPROTO_RAW;
6547 break;
6548 }
6549
6550 if (ip_protocol == IPPROTO_TCP)
6551 opts[1] |= TD1_TCP_CS;
6552 else if (ip_protocol == IPPROTO_UDP)
6553 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6554 else
6555 WARN_ON_ONCE(1);
e974604b 6556
6557 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6558 } else {
6559 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6560 return rtl_skb_pad(skb);
1da177e4 6561 }
5888d3fc 6562
b423e9ae 6563 return true;
1da177e4
LT		 6564}
6565
61357325
SH		 6566static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6567 struct net_device *dev)
1da177e4
LT		 6568{
6569 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6570 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 6571 struct TxDesc *txd = tp->TxDescArray + entry;
6572 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 6573 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6574 dma_addr_t mapping;
6575 u32 status, len;
2b7b4318 6576 u32 opts[2];
3eafe507 6577 int frags;
5b0384f4 6578
477206a0 6579 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6580 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6581 goto err_stop_0;
1da177e4
LT		 6582 }
6583
6584 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6585 goto err_stop_0;
6586
b423e9ae 6587 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6588 opts[0] = DescOwn;
6589
e974604b 6590 if (!tp->tso_csum(tp, skb, opts)) {
6591 r8169_csum_workaround(tp, skb);
6592 return NETDEV_TX_OK;
6593 }
b423e9ae 6594
3eafe507 6595 len = skb_headlen(skb);
48addcc9 6596 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6597 if (unlikely(dma_mapping_error(d, mapping))) {
6598 if (net_ratelimit())
6599 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6600 goto err_dma_0;
d827d86b 6601 }
3eafe507
SG		 6602
6603 tp->tx_skb[entry].len = len;
6604 txd->addr = cpu_to_le64(mapping);
1da177e4 6605
2b7b4318 6606 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6607 if (frags < 0)
6608 goto err_dma_1;
6609 else if (frags)
2b7b4318 6610 opts[0] |= FirstFrag;
3eafe507 6611 else {
2b7b4318 6612 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6613 tp->tx_skb[entry].skb = skb;
6614 }
6615
2b7b4318
FR		 6616 txd->opts2 = cpu_to_le32(opts[1]);
6617
1e918876
FW		 6618 netdev_sent_queue(dev, skb->len);
6619
5047fb5d
RC		 6620 skb_tx_timestamp(skb);
6621
1da177e4
LT		 6622 wmb();
6623
cecb5fd7 6624 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6625 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6626 txd->opts1 = cpu_to_le32(status);
6627
1da177e4
LT		 6628 tp->cur_tx += frags + 1;
6629
4c020a96 6630 wmb();
1da177e4 6631
cecb5fd7 6632 RTL_W8(TxPoll, NPQ);
1da177e4 6633
da78dbff
FR		 6634 mmiowb();
6635
477206a0 6636 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6637 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6638 * not miss a ring update when it notices a stopped queue.
6639 */
6640 smp_wmb();
1da177e4 6641 netif_stop_queue(dev);
ae1f23fb
FR		 6642 /* Sync with rtl_tx:
6643 * - publish queue status and cur_tx ring index (write barrier)
6644 * - refresh dirty_tx ring index (read barrier).
6645 * May the current thread have a pessimistic view of the ring
6646 * status and forget to wake up queue, a racing rtl_tx thread
6647 * can't.
6648 */
1e874e04 6649 smp_mb();
477206a0 6650 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6651 netif_wake_queue(dev);
6652 }
6653
61357325 6654 return NETDEV_TX_OK;
1da177e4 6655
3eafe507 6656err_dma_1:
48addcc9 6657 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6658err_dma_0:
989c9ba1 6659 dev_kfree_skb_any(skb);
3eafe507
SG		 6660 dev->stats.tx_dropped++;
6661 return NETDEV_TX_OK;
6662
6663err_stop_0:
1da177e4 6664 netif_stop_queue(dev);
cebf8cc7 6665 dev->stats.tx_dropped++;
61357325 6666 return NETDEV_TX_BUSY;
1da177e4
LT		 6667}
6668
6669static void rtl8169_pcierr_interrupt(struct net_device *dev)
6670{
6671 struct rtl8169_private *tp = netdev_priv(dev);
6672 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6673 u16 pci_status, pci_cmd;
6674
6675 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6676 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6677
bf82c189
JP		 6678 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6679 pci_cmd, pci_status);
1da177e4
LT		 6680
6681 /*
6682 * The recovery sequence below admits a very elaborated explanation:
6683 * - it seems to work;
d03902b8
FR		 6684 * - I did not see what else could be done;
6685 * - it makes iop3xx happy.
1da177e4
LT		 6686 *
6687 * Feel free to adjust to your needs.
6688 */
a27993f3 6689 if (pdev->broken_parity_status)
d03902b8
FR		 6690 pci_cmd &= ~PCI_COMMAND_PARITY;
6691 else
6692 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6693
6694 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6695
6696 pci_write_config_word(pdev, PCI_STATUS,
6697 pci_status & (PCI_STATUS_DETECTED_PARITY |
6698 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6699 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6700
6701 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6702 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 6703 void __iomem *ioaddr = tp->mmio_addr;
6704
bf82c189 6705 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 6706 tp->cp_cmd &= ~PCIDAC;
6707 RTL_W16(CPlusCmd, tp->cp_cmd);
6708 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6709 }
6710
e6de30d6 6711 rtl8169_hw_reset(tp);
d03902b8 6712
98ddf986 6713 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6714}
6715
da78dbff 6716static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6717{
6718 unsigned int dirty_tx, tx_left;
1e918876 6719 unsigned int bytes_compl = 0, pkts_compl = 0;
1da177e4 6720
1da177e4
LT		 6721 dirty_tx = tp->dirty_tx;
6722 smp_rmb();
6723 tx_left = tp->cur_tx - dirty_tx;
6724
6725 while (tx_left > 0) {
6726 unsigned int entry = dirty_tx % NUM_TX_DESC;
6727 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6728 u32 status;
6729
6730 rmb();
6731 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6732 if (status & DescOwn)
6733 break;
6734
48addcc9
SG		 6735 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6736 tp->TxDescArray + entry);
1da177e4 6737 if (status & LastFrag) {
1e918876
FW		 6738 pkts_compl++;
6739 bytes_compl += tx_skb->skb->len;
989c9ba1 6740 dev_kfree_skb_any(tx_skb->skb);
1da177e4
LT		 6741 tx_skb->skb = NULL;
6742 }
6743 dirty_tx++;
6744 tx_left--;
6745 }
6746
6747 if (tp->dirty_tx != dirty_tx) {
1e918876
FW		 6748 netdev_completed_queue(tp->dev, pkts_compl, bytes_compl);
6749
6750 u64_stats_update_begin(&tp->tx_stats.syncp);
6751 tp->tx_stats.packets += pkts_compl;
6752 tp->tx_stats.bytes += bytes_compl;
6753 u64_stats_update_end(&tp->tx_stats.syncp);
6754
1da177e4 6755 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6756 /* Sync with rtl8169_start_xmit:
6757 * - publish dirty_tx ring index (write barrier)
6758 * - refresh cur_tx ring index and queue status (read barrier)
6759 * May the current thread miss the stopped queue condition,
6760 * a racing xmit thread can only have a right view of the
6761 * ring status.
6762 */
1e874e04 6763 smp_mb();
1da177e4 6764 if (netif_queue_stopped(dev) &&
477206a0 6765 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6766 netif_wake_queue(dev);
6767 }
d78ae2dc
FR		 6768 /*
6769 * 8168 hack: TxPoll requests are lost when the Tx packets are
6770 * too close. Let's kick an extra TxPoll request when a burst
6771 * of start_xmit activity is detected (if it is not detected,
6772 * it is slow enough). -- FR
6773 */
da78dbff
FR		 6774 if (tp->cur_tx != dirty_tx) {
6775 void __iomem *ioaddr = tp->mmio_addr;
6776
d78ae2dc 6777 RTL_W8(TxPoll, NPQ);
da78dbff 6778 }
1da177e4
LT		 6779 }
6780}
6781
126fa4b9
FR		 6782static inline int rtl8169_fragmented_frame(u32 status)
6783{
6784 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6785}
6786
adea1ac7 6787static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6788{
1da177e4
LT		 6789 u32 status = opts1 & RxProtoMask;
6790
6791 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6792 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6793 skb->ip_summed = CHECKSUM_UNNECESSARY;
6794 else
bc8acf2c 6795 skb_checksum_none_assert(skb);
1da177e4
LT		 6796}
6797
6f0333b8
ED		 6798static struct sk_buff *rtl8169_try_rx_copy(void *data,
6799 struct rtl8169_private *tp,
6800 int pkt_size,
6801 dma_addr_t addr)
1da177e4 6802{
b449655f 6803 struct sk_buff *skb;
48addcc9 6804 struct device *d = &tp->pci_dev->dev;
b449655f 6805
6f0333b8 6806 data = rtl8169_align(data);
48addcc9 6807 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6808 prefetch(data);
6809 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6810 if (skb)
6811 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6812 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6813
6f0333b8 6814 return skb;
1da177e4
LT		 6815}
6816
da78dbff 6817static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6818{
6819 unsigned int cur_rx, rx_left;
6f0333b8 6820 unsigned int count;
1da177e4 6821
1da177e4 6822 cur_rx = tp->cur_rx;
1da177e4 6823
9fba0812 6824 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6825 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6826 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6827 u32 status;
6828
6829 rmb();
e03f33af 6830 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6831
6832 if (status & DescOwn)
6833 break;
4dcb7d33 6834 if (unlikely(status & RxRES)) {
bf82c189
JP		 6835 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6836 status);
cebf8cc7 6837 dev->stats.rx_errors++;
1da177e4 6838 if (status & (RxRWT | RxRUNT))
cebf8cc7 6839 dev->stats.rx_length_errors++;
1da177e4 6840 if (status & RxCRC)
cebf8cc7 6841 dev->stats.rx_crc_errors++;
9dccf611 6842 if (status & RxFOVF) {
da78dbff 6843 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6844 dev->stats.rx_fifo_errors++;
9dccf611 6845 }
6bbe021d
BG		 6846 if ((status & (RxRUNT | RxCRC)) &&
6847 !(status & (RxRWT | RxFOVF)) &&
6848 (dev->features & NETIF_F_RXALL))
6849 goto process_pkt;
1da177e4 6850 } else {
6f0333b8 6851 struct sk_buff *skb;
6bbe021d
BG		 6852 dma_addr_t addr;
6853 int pkt_size;
6854
6855process_pkt:
6856 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6857 if (likely(!(dev->features & NETIF_F_RXFCS)))
6858 pkt_size = (status & 0x00003fff) - 4;
6859 else
6860 pkt_size = status & 0x00003fff;
1da177e4 6861
126fa4b9
FR		 6862 /*
6863 * The driver does not support incoming fragmented
6864 * frames. They are seen as a symptom of over-mtu
6865 * sized frames.
6866 */
6867 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6868 dev->stats.rx_dropped++;
6869 dev->stats.rx_length_errors++;
ce11ff5e 6870 goto release_descriptor;
126fa4b9
FR		 6871 }
6872
6f0333b8
ED		 6873 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6874 tp, pkt_size, addr);
6f0333b8
ED		 6875 if (!skb) {
6876 dev->stats.rx_dropped++;
ce11ff5e 6877 goto release_descriptor;
1da177e4
LT		 6878 }
6879
adea1ac7 6880 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6881 skb_put(skb, pkt_size);
6882 skb->protocol = eth_type_trans(skb, dev);
6883
7a8fc77b
FR		 6884 rtl8169_rx_vlan_tag(desc, skb);
6885
56de414c 6886 napi_gro_receive(&tp->napi, skb);
1da177e4 6887
8027aa24
JW		 6888 u64_stats_update_begin(&tp->rx_stats.syncp);
6889 tp->rx_stats.packets++;
6890 tp->rx_stats.bytes += pkt_size;
6891 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6892 }
ce11ff5e 6893release_descriptor:
6894 desc->opts2 = 0;
6895 wmb();
6896 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 6897 }
6898
6899 count = cur_rx - tp->cur_rx;
6900 tp->cur_rx = cur_rx;
6901
1da177e4
LT		 6902 return count;
6903}
6904
07d3f51f 6905static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6906{
07d3f51f 6907 struct net_device *dev = dev_instance;
1da177e4 6908 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6909 int handled = 0;
9085cdfa 6910 u16 status;
1da177e4 6911
9085cdfa 6912 status = rtl_get_events(tp);
da78dbff
FR		 6913 if (status && status != 0xffff) {
6914 status &= RTL_EVENT_NAPI | tp->event_slow;
6915 if (status) {
6916 handled = 1;
1da177e4 6917
da78dbff
FR		 6918 rtl_irq_disable(tp);
6919 napi_schedule(&tp->napi);
f11a377b 6920 }
da78dbff
FR		 6921 }
6922 return IRQ_RETVAL(handled);
6923}
1da177e4 6924
da78dbff
FR		 6925/*
6926 * Workqueue context.
6927 */
6928static void rtl_slow_event_work(struct rtl8169_private *tp)
6929{
6930 struct net_device *dev = tp->dev;
6931 u16 status;
6932
6933 status = rtl_get_events(tp) & tp->event_slow;
6934 rtl_ack_events(tp, status);
1da177e4 6935
da78dbff
FR		 6936 if (unlikely(status & RxFIFOOver)) {
6937 switch (tp->mac_version) {
6938 /* Work around for rx fifo overflow */
6939 case RTL_GIGA_MAC_VER_11:
6940 netif_stop_queue(dev);
934714d0
FR		 6941 /* XXX - Hack alert. See rtl_task(). */
6942 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6943 default:
f11a377b
DD		 6944 break;
6945 }
da78dbff 6946 }
1da177e4 6947
da78dbff
FR		 6948 if (unlikely(status & SYSErr))
6949 rtl8169_pcierr_interrupt(dev);
0e485150 6950
da78dbff
FR		 6951 if (status & LinkChg)
6952 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6953
7dbb4918 6954 rtl_irq_enable_all(tp);
1da177e4
LT		 6955}
6956
4422bcd4
FR		 6957static void rtl_task(struct work_struct *work)
6958{
da78dbff
FR		 6959 static const struct {
6960 int bitnr;
6961 void (*action)(struct rtl8169_private *);
6962 } rtl_work[] = {
934714d0 6963 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6964 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6965 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6966 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6967 };
4422bcd4
FR		 6968 struct rtl8169_private *tp =
6969 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6970 struct net_device *dev = tp->dev;
6971 int i;
6972
6973 rtl_lock_work(tp);
6974
6c4a70c5
FR		 6975 if (!netif_running(dev) ||
6976 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6977 goto out_unlock;
6978
6979 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6980 bool pending;
6981
da78dbff 6982 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6983 if (pending)
6984 rtl_work[i].action(tp);
6985 }
4422bcd4 6986
da78dbff
FR		 6987out_unlock:
6988 rtl_unlock_work(tp);
4422bcd4
FR		 6989}
6990
bea3348e 6991static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6992{
bea3348e
SH		 6993 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6994 struct net_device *dev = tp->dev;
da78dbff
FR		 6995 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6996 int work_done= 0;
6997 u16 status;
6998
6999 status = rtl_get_events(tp);
7000 rtl_ack_events(tp, status & ~tp->event_slow);
7001
7002 if (status & RTL_EVENT_NAPI_RX)
7003 work_done = rtl_rx(dev, tp, (u32) budget);
7004
7005 if (status & RTL_EVENT_NAPI_TX)
7006 rtl_tx(dev, tp);
1da177e4 7007
da78dbff
FR		 7008 if (status & tp->event_slow) {
7009 enable_mask &= ~tp->event_slow;
7010
7011 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7012 }
1da177e4 7013
bea3348e 7014 if (work_done < budget) {
288379f0 7015 napi_complete(napi);
f11a377b 7016
da78dbff
FR		 7017 rtl_irq_enable(tp, enable_mask);
7018 mmiowb();
1da177e4
LT		 7019 }
7020
bea3348e 7021 return work_done;
1da177e4 7022}
1da177e4 7023
523a6094
FR		 7024static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7025{
7026 struct rtl8169_private *tp = netdev_priv(dev);
7027
7028 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7029 return;
7030
7031 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7032 RTL_W32(RxMissed, 0);
7033}
7034
1da177e4
LT		 7035static void rtl8169_down(struct net_device *dev)
7036{
7037 struct rtl8169_private *tp = netdev_priv(dev);
7038 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 7039
4876cc1e 7040 del_timer_sync(&tp->timer);
1da177e4 7041
93dd79e8 7042 napi_disable(&tp->napi);
da78dbff 7043 netif_stop_queue(dev);
1da177e4 7044
92fc43b4 7045 rtl8169_hw_reset(tp);
323bb685
SG		 7046 /*
7047 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7048 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7049 * and napi is disabled (rtl8169_poll).
323bb685 7050 */
523a6094 7051 rtl8169_rx_missed(dev, ioaddr);
1da177e4 7052
1da177e4 7053 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7054 synchronize_sched();
1da177e4 7055
1da177e4
LT		 7056 rtl8169_tx_clear(tp);
7057
7058 rtl8169_rx_clear(tp);
065c27c1 7059
7060 rtl_pll_power_down(tp);
1da177e4
LT		 7061}
7062
7063static int rtl8169_close(struct net_device *dev)
7064{
7065 struct rtl8169_private *tp = netdev_priv(dev);
7066 struct pci_dev *pdev = tp->pci_dev;
7067
e1759441
RW		 7068 pm_runtime_get_sync(&pdev->dev);
7069
cecb5fd7 7070 /* Update counters before going down */
355423d0
IV		 7071 rtl8169_update_counters(dev);
7072
da78dbff 7073 rtl_lock_work(tp);
6c4a70c5 7074 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7075
1da177e4 7076 rtl8169_down(dev);
da78dbff 7077 rtl_unlock_work(tp);
1da177e4 7078
4ea72445
L		 7079 cancel_work_sync(&tp->wk.work);
7080
92a7c4e7 7081 free_irq(pdev->irq, dev);
1da177e4 7082
82553bb6
SG		 7083 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7084 tp->RxPhyAddr);
7085 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7086 tp->TxPhyAddr);
1da177e4
LT		 7087 tp->TxDescArray = NULL;
7088 tp->RxDescArray = NULL;
7089
e1759441
RW		 7090 pm_runtime_put_sync(&pdev->dev);
7091
1da177e4
LT		 7092 return 0;
7093}
7094
dc1c00ce
FR		 7095#ifdef CONFIG_NET_POLL_CONTROLLER
7096static void rtl8169_netpoll(struct net_device *dev)
7097{
7098 struct rtl8169_private *tp = netdev_priv(dev);
7099
7100 rtl8169_interrupt(tp->pci_dev->irq, dev);
7101}
7102#endif
7103
df43ac78
FR		 7104static int rtl_open(struct net_device *dev)
7105{
7106 struct rtl8169_private *tp = netdev_priv(dev);
7107 void __iomem *ioaddr = tp->mmio_addr;
7108 struct pci_dev *pdev = tp->pci_dev;
7109 int retval = -ENOMEM;
7110
7111 pm_runtime_get_sync(&pdev->dev);
7112
7113 /*
e75d6606 7114 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7115 * dma_alloc_coherent provides more.
7116 */
7117 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7118 &tp->TxPhyAddr, GFP_KERNEL);
7119 if (!tp->TxDescArray)
7120 goto err_pm_runtime_put;
7121
7122 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7123 &tp->RxPhyAddr, GFP_KERNEL);
7124 if (!tp->RxDescArray)
7125 goto err_free_tx_0;
7126
7127 retval = rtl8169_init_ring(dev);
7128 if (retval < 0)
7129 goto err_free_rx_1;
7130
7131 INIT_WORK(&tp->wk.work, rtl_task);
7132
7133 smp_mb();
7134
7135 rtl_request_firmware(tp);
7136
92a7c4e7 7137 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 7138 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7139 dev->name, dev);
7140 if (retval < 0)
7141 goto err_release_fw_2;
7142
7143 rtl_lock_work(tp);
7144
7145 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7146
7147 napi_enable(&tp->napi);
7148
7149 rtl8169_init_phy(dev, tp);
7150
7151 __rtl8169_set_features(dev, dev->features);
7152
7153 rtl_pll_power_up(tp);
7154
7155 rtl_hw_start(dev);
7156
7157 netif_start_queue(dev);
7158
7159 rtl_unlock_work(tp);
7160
7161 tp->saved_wolopts = 0;
7162 pm_runtime_put_noidle(&pdev->dev);
7163
7164 rtl8169_check_link_status(dev, tp, ioaddr);
7165out:
7166 return retval;
7167
7168err_release_fw_2:
7169 rtl_release_firmware(tp);
7170 rtl8169_rx_clear(tp);
7171err_free_rx_1:
7172 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7173 tp->RxPhyAddr);
7174 tp->RxDescArray = NULL;
7175err_free_tx_0:
7176 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7177 tp->TxPhyAddr);
7178 tp->TxDescArray = NULL;
7179err_pm_runtime_put:
7180 pm_runtime_put_noidle(&pdev->dev);
7181 goto out;
7182}
7183
8027aa24
JW		 7184static struct rtnl_link_stats64 *
7185rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7186{
7187 struct rtl8169_private *tp = netdev_priv(dev);
7188 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 7189 unsigned int start;
1da177e4 7190
da78dbff 7191 if (netif_running(dev))
523a6094 7192 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 7193
8027aa24 7194 do {
57a7744e 7195 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7196 stats->rx_packets = tp->rx_stats.packets;
7197 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7198 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24
JW		 7199
7200
7201 do {
57a7744e 7202 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7203 stats->tx_packets = tp->tx_stats.packets;
7204 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7205 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7206
7207 stats->rx_dropped = dev->stats.rx_dropped;
7208 stats->tx_dropped = dev->stats.tx_dropped;
7209 stats->rx_length_errors = dev->stats.rx_length_errors;
7210 stats->rx_errors = dev->stats.rx_errors;
7211 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7212 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7213 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7214
7215 return stats;
1da177e4
LT		 7216}
7217
861ab440 7218static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7219{
065c27c1 7220 struct rtl8169_private *tp = netdev_priv(dev);
7221
5d06a99f 7222 if (!netif_running(dev))
861ab440 7223 return;
5d06a99f
FR		 7224
7225 netif_device_detach(dev);
7226 netif_stop_queue(dev);
da78dbff
FR		 7227
7228 rtl_lock_work(tp);
7229 napi_disable(&tp->napi);
6c4a70c5 7230 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7231 rtl_unlock_work(tp);
7232
7233 rtl_pll_power_down(tp);
861ab440
RW		 7234}
7235
7236#ifdef CONFIG_PM
7237
7238static int rtl8169_suspend(struct device *device)
7239{
7240 struct pci_dev *pdev = to_pci_dev(device);
7241 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7242
861ab440 7243 rtl8169_net_suspend(dev);
1371fa6d 7244
5d06a99f
FR		 7245 return 0;
7246}
7247
e1759441
RW		 7248static void __rtl8169_resume(struct net_device *dev)
7249{
065c27c1 7250 struct rtl8169_private *tp = netdev_priv(dev);
7251
e1759441 7252 netif_device_attach(dev);
065c27c1 7253
7254 rtl_pll_power_up(tp);
7255
cff4c162
AS		 7256 rtl_lock_work(tp);
7257 napi_enable(&tp->napi);
6c4a70c5 7258 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7259 rtl_unlock_work(tp);
da78dbff 7260
98ddf986 7261 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7262}
7263
861ab440 7264static int rtl8169_resume(struct device *device)
5d06a99f 7265{
861ab440 7266 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 7267 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 7268 struct rtl8169_private *tp = netdev_priv(dev);
7269
7270 rtl8169_init_phy(dev, tp);
5d06a99f 7271
e1759441
RW		 7272 if (netif_running(dev))
7273 __rtl8169_resume(dev);
5d06a99f 7274
e1759441
RW		 7275 return 0;
7276}
7277
7278static int rtl8169_runtime_suspend(struct device *device)
7279{
7280 struct pci_dev *pdev = to_pci_dev(device);
7281 struct net_device *dev = pci_get_drvdata(pdev);
7282 struct rtl8169_private *tp = netdev_priv(dev);
7283
7284 if (!tp->TxDescArray)
7285 return 0;
7286
da78dbff 7287 rtl_lock_work(tp);
e1759441
RW		 7288 tp->saved_wolopts = __rtl8169_get_wol(tp);
7289 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7290 rtl_unlock_work(tp);
e1759441
RW		 7291
7292 rtl8169_net_suspend(dev);
7293
7294 return 0;
7295}
7296
7297static int rtl8169_runtime_resume(struct device *device)
7298{
7299 struct pci_dev *pdev = to_pci_dev(device);
7300 struct net_device *dev = pci_get_drvdata(pdev);
7301 struct rtl8169_private *tp = netdev_priv(dev);
7302
7303 if (!tp->TxDescArray)
7304 return 0;
7305
da78dbff 7306 rtl_lock_work(tp);
e1759441
RW		 7307 __rtl8169_set_wol(tp, tp->saved_wolopts);
7308 tp->saved_wolopts = 0;
da78dbff 7309 rtl_unlock_work(tp);
e1759441 7310
fccec10b
SG		 7311 rtl8169_init_phy(dev, tp);
7312
e1759441 7313 __rtl8169_resume(dev);
5d06a99f 7314
5d06a99f
FR		 7315 return 0;
7316}
7317
e1759441
RW		 7318static int rtl8169_runtime_idle(struct device *device)
7319{
7320 struct pci_dev *pdev = to_pci_dev(device);
7321 struct net_device *dev = pci_get_drvdata(pdev);
7322 struct rtl8169_private *tp = netdev_priv(dev);
7323
e4fbce74 7324 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 7325}
7326
47145210 7327static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7328 .suspend = rtl8169_suspend,
7329 .resume = rtl8169_resume,
7330 .freeze = rtl8169_suspend,
7331 .thaw = rtl8169_resume,
7332 .poweroff = rtl8169_suspend,
7333 .restore = rtl8169_resume,
7334 .runtime_suspend = rtl8169_runtime_suspend,
7335 .runtime_resume = rtl8169_runtime_resume,
7336 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7337};
7338
7339#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7340
7341#else /* !CONFIG_PM */
7342
7343#define RTL8169_PM_OPS NULL
7344
7345#endif /* !CONFIG_PM */
7346
649b3b8c 7347static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7348{
7349 void __iomem *ioaddr = tp->mmio_addr;
7350
7351 /* WoL fails with 8168b when the receiver is disabled. */
7352 switch (tp->mac_version) {
7353 case RTL_GIGA_MAC_VER_11:
7354 case RTL_GIGA_MAC_VER_12:
7355 case RTL_GIGA_MAC_VER_17:
7356 pci_clear_master(tp->pci_dev);
7357
7358 RTL_W8(ChipCmd, CmdRxEnb);
7359 /* PCI commit */
7360 RTL_R8(ChipCmd);
7361 break;
7362 default:
7363 break;
7364 }
7365}
7366
1765f95d
FR		 7367static void rtl_shutdown(struct pci_dev *pdev)
7368{
861ab440 7369 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7370 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 7371 struct device *d = &pdev->dev;
7372
7373 pm_runtime_get_sync(d);
861ab440
RW		 7374
7375 rtl8169_net_suspend(dev);
1765f95d 7376
cecb5fd7 7377 /* Restore original MAC address */
cc098dc7
IV		 7378 rtl_rar_set(tp, dev->perm_addr);
7379
92fc43b4 7380 rtl8169_hw_reset(tp);
4bb3f522 7381
861ab440 7382 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 7383 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7384 rtl_wol_suspend_quirk(tp);
7385 rtl_wol_shutdown_quirk(tp);
ca52efd5 7386 }
7387
861ab440
RW		 7388 pci_wake_from_d3(pdev, true);
7389 pci_set_power_state(pdev, PCI_D3hot);
7390 }
2a15cd2f 7391
7392 pm_runtime_put_noidle(d);
861ab440 7393}
5d06a99f 7394
baf63293 7395static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7396{
7397 struct net_device *dev = pci_get_drvdata(pdev);
7398 struct rtl8169_private *tp = netdev_priv(dev);
7399
ee7a1beb
CHL		 7400 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7401 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7402 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
7403 r8168_check_dash(tp)) {
e27566ed
FR		 7404 rtl8168_driver_stop(tp);
7405 }
7406
ad1be8d3
DN		 7407 netif_napi_del(&tp->napi);
7408
e27566ed
FR		 7409 unregister_netdev(dev);
7410
7411 rtl_release_firmware(tp);
7412
7413 if (pci_dev_run_wake(pdev))
7414 pm_runtime_get_noresume(&pdev->dev);
7415
7416 /* restore original MAC address */
7417 rtl_rar_set(tp, dev->perm_addr);
7418
7419 rtl_disable_msi(pdev, tp);
7420 rtl8169_release_board(pdev, dev, tp->mmio_addr);
e27566ed
FR		 7421}
7422
fa9c385e 7423static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7424 .ndo_open = rtl_open,
fa9c385e
FR		 7425 .ndo_stop = rtl8169_close,
7426 .ndo_get_stats64 = rtl8169_get_stats64,
7427 .ndo_start_xmit = rtl8169_start_xmit,
7428 .ndo_tx_timeout = rtl8169_tx_timeout,
7429 .ndo_validate_addr = eth_validate_addr,
7430 .ndo_change_mtu = rtl8169_change_mtu,
7431 .ndo_fix_features = rtl8169_fix_features,
7432 .ndo_set_features = rtl8169_set_features,
7433 .ndo_set_mac_address = rtl_set_mac_address,
7434 .ndo_do_ioctl = rtl8169_ioctl,
7435 .ndo_set_rx_mode = rtl_set_rx_mode,
7436#ifdef CONFIG_NET_POLL_CONTROLLER
7437 .ndo_poll_controller = rtl8169_netpoll,
7438#endif
7439
7440};
7441
31fa8b18
FR		 7442static const struct rtl_cfg_info {
7443 void (*hw_start)(struct net_device *);
7444 unsigned int region;
7445 unsigned int align;
7446 u16 event_slow;
7447 unsigned features;
7448 u8 default_ver;
7449} rtl_cfg_infos [] = {
7450 [RTL_CFG_0] = {
7451 .hw_start = rtl_hw_start_8169,
7452 .region = 1,
7453 .align = 0,
7454 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7455 .features = RTL_FEATURE_GMII,
7456 .default_ver = RTL_GIGA_MAC_VER_01,
7457 },
7458 [RTL_CFG_1] = {
7459 .hw_start = rtl_hw_start_8168,
7460 .region = 2,
7461 .align = 8,
7462 .event_slow = SYSErr | LinkChg | RxOverflow,
7463 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7464 .default_ver = RTL_GIGA_MAC_VER_11,
7465 },
7466 [RTL_CFG_2] = {
7467 .hw_start = rtl_hw_start_8101,
7468 .region = 2,
7469 .align = 8,
7470 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7471 PCSTimeout,
7472 .features = RTL_FEATURE_MSI,
7473 .default_ver = RTL_GIGA_MAC_VER_13,
7474 }
7475};
7476
7477/* Cfg9346_Unlock assumed. */
7478static unsigned rtl_try_msi(struct rtl8169_private *tp,
7479 const struct rtl_cfg_info *cfg)
7480{
7481 void __iomem *ioaddr = tp->mmio_addr;
7482 unsigned msi = 0;
7483 u8 cfg2;
7484
7485 cfg2 = RTL_R8(Config2) & ~MSIEnable;
7486 if (cfg->features & RTL_FEATURE_MSI) {
7487 if (pci_enable_msi(tp->pci_dev)) {
7488 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7489 } else {
7490 cfg2 |= MSIEnable;
7491 msi = RTL_FEATURE_MSI;
7492 }
7493 }
7494 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7495 RTL_W8(Config2, cfg2);
7496 return msi;
7497}
7498
c558386b
HW		 7499DECLARE_RTL_COND(rtl_link_list_ready_cond)
7500{
7501 void __iomem *ioaddr = tp->mmio_addr;
7502
7503 return RTL_R8(MCU) & LINK_LIST_RDY;
7504}
7505
7506DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7507{
7508 void __iomem *ioaddr = tp->mmio_addr;
7509
7510 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7511}
7512
baf63293 7513static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 7514{
7515 void __iomem *ioaddr = tp->mmio_addr;
7516 u32 data;
7517
7518 tp->ocp_base = OCP_STD_PHY_BASE;
7519
7520 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7521
7522 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7523 return;
7524
7525 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7526 return;
7527
7528 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7529 msleep(1);
7530 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7531
5f8bcce9 7532 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7533 data &= ~(1 << 14);
7534 r8168_mac_ocp_write(tp, 0xe8de, data);
7535
7536 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7537 return;
7538
5f8bcce9 7539 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7540 data |= (1 << 15);
7541 r8168_mac_ocp_write(tp, 0xe8de, data);
7542
7543 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7544 return;
7545}
7546
baf63293 7547static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7548{
7549 switch (tp->mac_version) {
7550 case RTL_GIGA_MAC_VER_40:
7551 case RTL_GIGA_MAC_VER_41:
57538c4a 7552 case RTL_GIGA_MAC_VER_42:
58152cd4 7553 case RTL_GIGA_MAC_VER_43:
45dd95c4 7554 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 7555 case RTL_GIGA_MAC_VER_45:
7556 case RTL_GIGA_MAC_VER_46:
7557 case RTL_GIGA_MAC_VER_47:
7558 case RTL_GIGA_MAC_VER_48:
c558386b
HW		 7559 rtl_hw_init_8168g(tp);
7560 break;
7561
7562 default:
7563 break;
7564 }
7565}
7566
929a031d 7567static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7568{
7569 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7570 const unsigned int region = cfg->region;
7571 struct rtl8169_private *tp;
7572 struct mii_if_info *mii;
7573 struct net_device *dev;
7574 void __iomem *ioaddr;
7575 int chipset, i;
7576 int rc;
7577
7578 if (netif_msg_drv(&debug)) {
7579 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7580 MODULENAME, RTL8169_VERSION);
7581 }
7582
7583 dev = alloc_etherdev(sizeof (*tp));
7584 if (!dev) {
7585 rc = -ENOMEM;
7586 goto out;
7587 }
7588
7589 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7590 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7591 tp = netdev_priv(dev);
7592 tp->dev = dev;
7593 tp->pci_dev = pdev;
7594 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7595
7596 mii = &tp->mii;
7597 mii->dev = dev;
7598 mii->mdio_read = rtl_mdio_read;
7599 mii->mdio_write = rtl_mdio_write;
7600 mii->phy_id_mask = 0x1f;
7601 mii->reg_num_mask = 0x1f;
7602 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
7603
7604 /* disable ASPM completely as that cause random device stop working
7605 * problems as well as full system hangs for some PCIe devices users */
7606 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
7607 PCIE_LINK_STATE_CLKPM);
7608
7609 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7610 rc = pci_enable_device(pdev);
7611 if (rc < 0) {
7612 netif_err(tp, probe, dev, "enable failure\n");
7613 goto err_out_free_dev_1;
7614 }
7615
7616 if (pci_set_mwi(pdev) < 0)
7617 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7618
7619 /* make sure PCI base addr 1 is MMIO */
7620 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7621 netif_err(tp, probe, dev,
7622 "region #%d not an MMIO resource, aborting\n",
7623 region);
7624 rc = -ENODEV;
7625 goto err_out_mwi_2;
7626 }
7627
7628 /* check for weird/broken PCI region reporting */
7629 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7630 netif_err(tp, probe, dev,
7631 "Invalid PCI region size(s), aborting\n");
7632 rc = -ENODEV;
7633 goto err_out_mwi_2;
7634 }
7635
7636 rc = pci_request_regions(pdev, MODULENAME);
7637 if (rc < 0) {
7638 netif_err(tp, probe, dev, "could not request regions\n");
7639 goto err_out_mwi_2;
7640 }
7641
929a031d 7642 tp->cp_cmd = 0;
3b6cf25d
FR		 7643
7644 if ((sizeof(dma_addr_t) > 4) &&
7645 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7646 tp->cp_cmd |= PCIDAC;
7647 dev->features |= NETIF_F_HIGHDMA;
7648 } else {
7649 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7650 if (rc < 0) {
7651 netif_err(tp, probe, dev, "DMA configuration failed\n");
7652 goto err_out_free_res_3;
7653 }
7654 }
7655
7656 /* ioremap MMIO region */
7657 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7658 if (!ioaddr) {
7659 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7660 rc = -EIO;
7661 goto err_out_free_res_3;
7662 }
7663 tp->mmio_addr = ioaddr;
7664
7665 if (!pci_is_pcie(pdev))
7666 netif_info(tp, probe, dev, "not PCI Express\n");
7667
7668 /* Identify chip attached to board */
7669 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7670
7671 rtl_init_rxcfg(tp);
7672
7673 rtl_irq_disable(tp);
7674
c558386b
HW		 7675 rtl_hw_initialize(tp);
7676
3b6cf25d
FR		 7677 rtl_hw_reset(tp);
7678
7679 rtl_ack_events(tp, 0xffff);
7680
7681 pci_set_master(pdev);
7682
3b6cf25d
FR		 7683 rtl_init_mdio_ops(tp);
7684 rtl_init_pll_power_ops(tp);
7685 rtl_init_jumbo_ops(tp);
beb1fe18 7686 rtl_init_csi_ops(tp);
3b6cf25d
FR		 7687
7688 rtl8169_print_mac_version(tp);
7689
7690 chipset = tp->mac_version;
7691 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7692
7693 RTL_W8(Cfg9346, Cfg9346_Unlock);
7694 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8f9d5138 7695 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
6e1d0b89 7696 switch (tp->mac_version) {
ac85bcdb
CHL		 7697 case RTL_GIGA_MAC_VER_34:
7698 case RTL_GIGA_MAC_VER_35:
7699 case RTL_GIGA_MAC_VER_36:
7700 case RTL_GIGA_MAC_VER_37:
7701 case RTL_GIGA_MAC_VER_38:
7702 case RTL_GIGA_MAC_VER_40:
7703 case RTL_GIGA_MAC_VER_41:
7704 case RTL_GIGA_MAC_VER_42:
7705 case RTL_GIGA_MAC_VER_43:
7706 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 7707 case RTL_GIGA_MAC_VER_45:
7708 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 7709 case RTL_GIGA_MAC_VER_47:
7710 case RTL_GIGA_MAC_VER_48:
6e1d0b89
CHL		 7711 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
7712 tp->features |= RTL_FEATURE_WOL;
7713 if ((RTL_R8(Config3) & LinkUp) != 0)
7714 tp->features |= RTL_FEATURE_WOL;
7715 break;
7716 default:
7717 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7718 tp->features |= RTL_FEATURE_WOL;
7719 break;
7720 }
3b6cf25d
FR		 7721 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7722 tp->features |= RTL_FEATURE_WOL;
7723 tp->features |= rtl_try_msi(tp, cfg);
7724 RTL_W8(Cfg9346, Cfg9346_Lock);
7725
7726 if (rtl_tbi_enabled(tp)) {
7727 tp->set_speed = rtl8169_set_speed_tbi;
7728 tp->get_settings = rtl8169_gset_tbi;
7729 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7730 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7731 tp->link_ok = rtl8169_tbi_link_ok;
7732 tp->do_ioctl = rtl_tbi_ioctl;
7733 } else {
7734 tp->set_speed = rtl8169_set_speed_xmii;
7735 tp->get_settings = rtl8169_gset_xmii;
7736 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7737 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7738 tp->link_ok = rtl8169_xmii_link_ok;
7739 tp->do_ioctl = rtl_xmii_ioctl;
7740 }
7741
7742 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7743 u64_stats_init(&tp->rx_stats.syncp);
7744 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7745
7746 /* Get MAC address */
89cceb27
CHL		 7747 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7748 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
7749 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
7750 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
7751 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
7752 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
7753 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
7754 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
7755 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
7756 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
6e1d0b89
CHL		 7757 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
7758 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
7759 tp->mac_version == RTL_GIGA_MAC_VER_48) {
7760 u16 mac_addr[3];
7761
05b9687b
CHL		 7762 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7763 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89
CHL		 7764
7765 if (is_valid_ether_addr((u8 *)mac_addr))
7766 rtl_rar_set(tp, (u8 *)mac_addr);
7767 }
3b6cf25d
FR		 7768 for (i = 0; i < ETH_ALEN; i++)
7769 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 7770
7ad24ea4 7771 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7772 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 7773
7774 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7775
7776 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7777 * properly for all devices */
7778 dev->features |= NETIF_F_RXCSUM |
f646968f 7779 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7780
7781 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7782 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7783 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7784 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7785 NETIF_F_HIGHDMA;
7786
929a031d 7787 tp->cp_cmd |= RxChkSum | RxVlan;
7788
7789 /*
7790 * Pretend we are using VLANs; This bypasses a nasty bug where
7791 * Interrupts stop flowing on high load on 8110SCd controllers.
7792 */
3b6cf25d 7793 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7794 /* Disallow toggling */
f646968f 7795 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7796
5888d3fc 7797 if (tp->txd_version == RTL_TD_0)
7798 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 7799 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 7800 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7801 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7802 } else
5888d3fc 7803 WARN_ON_ONCE(1);
7804
3b6cf25d
FR		 7805 dev->hw_features |= NETIF_F_RXALL;
7806 dev->hw_features |= NETIF_F_RXFCS;
7807
7808 tp->hw_start = cfg->hw_start;
7809 tp->event_slow = cfg->event_slow;
7810
7811 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7812 ~(RxBOVF | RxFOVF) : ~0;
7813
7814 init_timer(&tp->timer);
7815 tp->timer.data = (unsigned long) dev;
7816 tp->timer.function = rtl8169_phy_timer;
7817
7818 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7819
7820 rc = register_netdev(dev);
7821 if (rc < 0)
7822 goto err_out_msi_4;
7823
7824 pci_set_drvdata(pdev, dev);
7825
92a7c4e7
FR		 7826 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7827 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7828 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 7829 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7830 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7831 "tx checksumming: %s]\n",
7832 rtl_chip_infos[chipset].jumbo_max,
7833 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7834 }
7835
ee7a1beb
CHL		 7836 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7837 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7838 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
7839 r8168_check_dash(tp)) {
3b6cf25d
FR		 7840 rtl8168_driver_start(tp);
7841 }
7842
7843 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7844
7845 if (pci_dev_run_wake(pdev))
7846 pm_runtime_put_noidle(&pdev->dev);
7847
7848 netif_carrier_off(dev);
7849
7850out:
7851 return rc;
7852
7853err_out_msi_4:
ad1be8d3 7854 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7855 rtl_disable_msi(pdev, tp);
7856 iounmap(ioaddr);
7857err_out_free_res_3:
7858 pci_release_regions(pdev);
7859err_out_mwi_2:
7860 pci_clear_mwi(pdev);
7861 pci_disable_device(pdev);
7862err_out_free_dev_1:
7863 free_netdev(dev);
7864 goto out;
7865}
7866
1da177e4
LT		 7867static struct pci_driver rtl8169_pci_driver = {
7868 .name = MODULENAME,
7869 .id_table = rtl8169_pci_tbl,
3b6cf25d 7870 .probe = rtl_init_one,
baf63293 7871 .remove = rtl_remove_one,
1765f95d 7872 .shutdown = rtl_shutdown,
861ab440 7873 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7874};
7875
3eeb7da9 7876module_pci_driver(rtl8169_pci_driver);
Linux kernel - Deliverables
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