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drivers/net: Remove alloc_etherdev error messages
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 48
1da177e4
LT		 49#ifdef RTL8169_DEBUG
50#define assert(expr) \
5b0384f4
FR		 51 if (!(expr)) { \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 53 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 54 }
06fa7358
JP		 55#define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 57#else
58#define assert(expr) do {} while (0)
59#define dprintk(fmt, args...) do {} while (0)
60#endif /* RTL8169_DEBUG */
61
b57b7e5a 62#define R8169_MSG_DEFAULT \
f0e837d9 63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 64
1da177e4
LT		 65#define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
67
1da177e4
LT		 68/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 70static const int multicast_filter_limit = 32;
1da177e4 71
9c14ceaf 72#define MAX_READ_REQUEST_SHIFT 12
1da177e4 73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 74#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
ea8dbdd1 88#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 90#define RTL_EEPROM_SIG_ADDR 0x0000
91
1da177e4
LT		 92/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 98#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 99
100enum mac_version {
85bffe6c
FR		 101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_33,
70090424 134 RTL_GIGA_MAC_VER_34,
c2218925
HW		 135 RTL_GIGA_MAC_VER_35,
136 RTL_GIGA_MAC_VER_36,
85bffe6c 137 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 138};
139
2b7b4318
FR		 140enum rtl_tx_desc_version {
141 RTL_TD_0 = 0,
142 RTL_TD_1 = 1,
143};
144
d58d46b5
FR		 145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
151#define _R(NAME,TD,FW,SZ,B) { \
152 .name = NAME, \
153 .txd_version = TD, \
154 .fw_name = FW, \
155 .jumbo_max = SZ, \
156 .jumbo_tx_csum = B \
157}
1da177e4 158
3c6bee1d 159static const struct {
1da177e4 160 const char *name;
2b7b4318 161 enum rtl_tx_desc_version txd_version;
953a12cc 162 const char *fw_name;
d58d46b5
FR		 163 u16 jumbo_max;
164 bool jumbo_tx_csum;
85bffe6c
FR		 165} rtl_chip_infos[] = {
166 /* PCI devices. */
167 [RTL_GIGA_MAC_VER_01] =
d58d46b5 168 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 169 [RTL_GIGA_MAC_VER_02] =
d58d46b5 170 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 171 [RTL_GIGA_MAC_VER_03] =
d58d46b5 172 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 173 [RTL_GIGA_MAC_VER_04] =
d58d46b5 174 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_05] =
d58d46b5 176 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_06] =
d58d46b5 178 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 179 /* PCI-E devices. */
180 [RTL_GIGA_MAC_VER_07] =
d58d46b5 181 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 182 [RTL_GIGA_MAC_VER_08] =
d58d46b5 183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 184 [RTL_GIGA_MAC_VER_09] =
d58d46b5 185 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 186 [RTL_GIGA_MAC_VER_10] =
d58d46b5 187 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_11] =
d58d46b5 189 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 190 [RTL_GIGA_MAC_VER_12] =
d58d46b5 191 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 192 [RTL_GIGA_MAC_VER_13] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_14] =
d58d46b5 195 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_15] =
d58d46b5 197 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_16] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_17] =
d58d46b5 201 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 202 [RTL_GIGA_MAC_VER_18] =
d58d46b5 203 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 204 [RTL_GIGA_MAC_VER_19] =
d58d46b5 205 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 206 [RTL_GIGA_MAC_VER_20] =
d58d46b5 207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_21] =
d58d46b5 209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_22] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_23] =
d58d46b5 213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_24] =
d58d46b5 215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 217 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
218 JUMBO_9K, false),
85bffe6c 219 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
221 JUMBO_9K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_27] =
d58d46b5 223 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 224 [RTL_GIGA_MAC_VER_28] =
d58d46b5 225 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 227 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
228 JUMBO_1K, true),
85bffe6c 229 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
231 JUMBO_1K, true),
85bffe6c 232 [RTL_GIGA_MAC_VER_31] =
d58d46b5 233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 235 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
236 JUMBO_9K, false),
85bffe6c 237 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
239 JUMBO_9K, false),
70090424 240 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 241 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
242 JUMBO_9K, false),
c2218925 243 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 244 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
245 JUMBO_9K, false),
c2218925 246 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
248 JUMBO_9K, false),
953a12cc 249};
85bffe6c 250#undef _R
953a12cc 251
bcf0bf90
FR		 252enum cfg_version {
253 RTL_CFG_0 = 0x00,
254 RTL_CFG_1,
255 RTL_CFG_2
256};
257
07ce4064
FR		 258static void rtl_hw_start_8169(struct net_device *);
259static void rtl_hw_start_8168(struct net_device *);
260static void rtl_hw_start_8101(struct net_device *);
261
a3aa1884 262static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 270 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
272 { PCI_VENDOR_ID_LINKSYS, 0x1032,
273 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 274 { 0x0001, 0x8168,
275 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 276 {0,},
277};
278
279MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
280
6f0333b8 281static int rx_buf_sz = 16383;
4300e8c7 282static int use_dac;
b57b7e5a
SH		 283static struct {
284 u32 msg_enable;
285} debug = { -1 };
1da177e4 286
07d3f51f
FR		 287enum rtl_registers {
288 MAC0 = 0, /* Ethernet hardware address. */
773d2021 289 MAC4 = 4,
07d3f51f
FR		 290 MAR0 = 8, /* Multicast filter. */
291 CounterAddrLow = 0x10,
292 CounterAddrHigh = 0x14,
293 TxDescStartAddrLow = 0x20,
294 TxDescStartAddrHigh = 0x24,
295 TxHDescStartAddrLow = 0x28,
296 TxHDescStartAddrHigh = 0x2c,
297 FLASH = 0x30,
298 ERSR = 0x36,
299 ChipCmd = 0x37,
300 TxPoll = 0x38,
301 IntrMask = 0x3c,
302 IntrStatus = 0x3e,
4f6b00e5 303
07d3f51f 304 TxConfig = 0x40,
4f6b00e5
HW		 305#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
306#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 307
4f6b00e5
HW		 308 RxConfig = 0x44,
309#define RX128_INT_EN (1 << 15) /* 8111c and later */
310#define RX_MULTI_EN (1 << 14) /* 8111c only */
311#define RXCFG_FIFO_SHIFT 13
312 /* No threshold before first PCI xfer */
313#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
314#define RXCFG_DMA_SHIFT 8
315 /* Unlimited maximum PCI burst. */
316#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 317
07d3f51f
FR		 318 RxMissed = 0x4c,
319 Cfg9346 = 0x50,
320 Config0 = 0x51,
321 Config1 = 0x52,
322 Config2 = 0x53,
323 Config3 = 0x54,
324 Config4 = 0x55,
325 Config5 = 0x56,
326 MultiIntr = 0x5c,
327 PHYAR = 0x60,
07d3f51f
FR		 328 PHYstatus = 0x6c,
329 RxMaxSize = 0xda,
330 CPlusCmd = 0xe0,
331 IntrMitigate = 0xe2,
332 RxDescAddrLow = 0xe4,
333 RxDescAddrHigh = 0xe8,
f0298f81 334 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
335
336#define NoEarlyTx 0x3f /* Max value : no early transmit. */
337
338 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
339
340#define TxPacketMax (8064 >> 7)
3090bd9a 341#define EarlySize 0x27
f0298f81 342
07d3f51f
FR		 343 FuncEvent = 0xf0,
344 FuncEventMask = 0xf4,
345 FuncPresetState = 0xf8,
346 FuncForceEvent = 0xfc,
1da177e4
LT		 347};
348
f162a5d1
FR		 349enum rtl8110_registers {
350 TBICSR = 0x64,
351 TBI_ANAR = 0x68,
352 TBI_LPAR = 0x6a,
353};
354
355enum rtl8168_8101_registers {
356 CSIDR = 0x64,
357 CSIAR = 0x68,
358#define CSIAR_FLAG 0x80000000
359#define CSIAR_WRITE_CMD 0x80000000
360#define CSIAR_BYTE_ENABLE 0x0f
361#define CSIAR_BYTE_ENABLE_SHIFT 12
362#define CSIAR_ADDR_MASK 0x0fff
065c27c1 363 PMCH = 0x6f,
f162a5d1
FR		 364 EPHYAR = 0x80,
365#define EPHYAR_FLAG 0x80000000
366#define EPHYAR_WRITE_CMD 0x80000000
367#define EPHYAR_REG_MASK 0x1f
368#define EPHYAR_REG_SHIFT 16
369#define EPHYAR_DATA_MASK 0xffff
5a5e4443 370 DLLPR = 0xd0,
4f6b00e5 371#define PFM_EN (1 << 6)
f162a5d1
FR		 372 DBG_REG = 0xd1,
373#define FIX_NAK_1 (1 << 4)
374#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 375 TWSI = 0xd2,
376 MCU = 0xd3,
4f6b00e5 377#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 378#define EN_NDP (1 << 3)
379#define EN_OOB_RESET (1 << 2)
daf9df6d 380 EFUSEAR = 0xdc,
381#define EFUSEAR_FLAG 0x80000000
382#define EFUSEAR_WRITE_CMD 0x80000000
383#define EFUSEAR_READ_CMD 0x00000000
384#define EFUSEAR_REG_MASK 0x03ff
385#define EFUSEAR_REG_SHIFT 8
386#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 387};
388
c0e45c1c 389enum rtl8168_registers {
4f6b00e5
HW		 390 LED_FREQ = 0x1a,
391 EEE_LED = 0x1b,
b646d900 392 ERIDR = 0x70,
393 ERIAR = 0x74,
394#define ERIAR_FLAG 0x80000000
395#define ERIAR_WRITE_CMD 0x80000000
396#define ERIAR_READ_CMD 0x00000000
397#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 398#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 399#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
400#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
401#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
402#define ERIAR_MASK_SHIFT 12
403#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
404#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
405#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 406 EPHY_RXER_NUM = 0x7c,
407 OCPDR = 0xb0, /* OCP GPHY access */
408#define OCPDR_WRITE_CMD 0x80000000
409#define OCPDR_READ_CMD 0x00000000
410#define OCPDR_REG_MASK 0x7f
411#define OCPDR_GPHY_REG_SHIFT 16
412#define OCPDR_DATA_MASK 0xffff
413 OCPAR = 0xb4,
414#define OCPAR_FLAG 0x80000000
415#define OCPAR_GPHY_WRITE_CMD 0x8000f060
416#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 417 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
418 MISC = 0xf0, /* 8168e only. */
cecb5fd7 419#define TXPLA_RST (1 << 29)
4f6b00e5 420#define PWM_EN (1 << 22)
c0e45c1c 421};
422
07d3f51f 423enum rtl_register_content {
1da177e4 424 /* InterruptStatusBits */
07d3f51f
FR		 425 SYSErr = 0x8000,
426 PCSTimeout = 0x4000,
427 SWInt = 0x0100,
428 TxDescUnavail = 0x0080,
429 RxFIFOOver = 0x0040,
430 LinkChg = 0x0020,
431 RxOverflow = 0x0010,
432 TxErr = 0x0008,
433 TxOK = 0x0004,
434 RxErr = 0x0002,
435 RxOK = 0x0001,
1da177e4
LT		 436
437 /* RxStatusDesc */
e03f33af 438 RxBOVF = (1 << 24),
9dccf611
FR		 439 RxFOVF = (1 << 23),
440 RxRWT = (1 << 22),
441 RxRES = (1 << 21),
442 RxRUNT = (1 << 20),
443 RxCRC = (1 << 19),
1da177e4
LT		 444
445 /* ChipCmdBits */
4f6b00e5 446 StopReq = 0x80,
07d3f51f
FR		 447 CmdReset = 0x10,
448 CmdRxEnb = 0x08,
449 CmdTxEnb = 0x04,
450 RxBufEmpty = 0x01,
1da177e4 451
275391a4
FR		 452 /* TXPoll register p.5 */
453 HPQ = 0x80, /* Poll cmd on the high prio queue */
454 NPQ = 0x40, /* Poll cmd on the low prio queue */
455 FSWInt = 0x01, /* Forced software interrupt */
456
1da177e4 457 /* Cfg9346Bits */
07d3f51f
FR		 458 Cfg9346_Lock = 0x00,
459 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 460
461 /* rx_mode_bits */
07d3f51f
FR		 462 AcceptErr = 0x20,
463 AcceptRunt = 0x10,
464 AcceptBroadcast = 0x08,
465 AcceptMulticast = 0x04,
466 AcceptMyPhys = 0x02,
467 AcceptAllPhys = 0x01,
1687b566 468#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 469
1da177e4
LT		 470 /* TxConfigBits */
471 TxInterFrameGapShift = 24,
472 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
473
5d06a99f 474 /* Config1 register p.24 */
f162a5d1
FR		 475 LEDS1 = (1 << 7),
476 LEDS0 = (1 << 6),
f162a5d1
FR		 477 Speed_down = (1 << 4),
478 MEMMAP = (1 << 3),
479 IOMAP = (1 << 2),
480 VPD = (1 << 1),
5d06a99f
FR		 481 PMEnable = (1 << 0), /* Power Management Enable */
482
6dccd16b 483 /* Config2 register p. 25 */
2ca6cf06 484 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 485 PCI_Clock_66MHz = 0x01,
486 PCI_Clock_33MHz = 0x00,
487
61a4dcc2
FR		 488 /* Config3 register p.25 */
489 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
490 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 491 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 492 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 493
d58d46b5
FR		 494 /* Config4 register */
495 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
496
5d06a99f 497 /* Config5 register p.27 */
61a4dcc2
FR		 498 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
499 MWF = (1 << 5), /* Accept Multicast wakeup frame */
500 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 501 Spi_en = (1 << 3),
61a4dcc2 502 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 503 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
504
1da177e4
LT		 505 /* TBICSR p.28 */
506 TBIReset = 0x80000000,
507 TBILoopback = 0x40000000,
508 TBINwEnable = 0x20000000,
509 TBINwRestart = 0x10000000,
510 TBILinkOk = 0x02000000,
511 TBINwComplete = 0x01000000,
512
513 /* CPlusCmd p.31 */
f162a5d1
FR		 514 EnableBist = (1 << 15), // 8168 8101
515 Mac_dbgo_oe = (1 << 14), // 8168 8101
516 Normal_mode = (1 << 13), // unused
517 Force_half_dup = (1 << 12), // 8168 8101
518 Force_rxflow_en = (1 << 11), // 8168 8101
519 Force_txflow_en = (1 << 10), // 8168 8101
520 Cxpl_dbg_sel = (1 << 9), // 8168 8101
521 ASF = (1 << 8), // 8168 8101
522 PktCntrDisable = (1 << 7), // 8168 8101
523 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 524 RxVlan = (1 << 6),
525 RxChkSum = (1 << 5),
526 PCIDAC = (1 << 4),
527 PCIMulRW = (1 << 3),
0e485150
FR		 528 INTT_0 = 0x0000, // 8168
529 INTT_1 = 0x0001, // 8168
530 INTT_2 = 0x0002, // 8168
531 INTT_3 = 0x0003, // 8168
1da177e4
LT		 532
533 /* rtl8169_PHYstatus */
07d3f51f
FR		 534 TBI_Enable = 0x80,
535 TxFlowCtrl = 0x40,
536 RxFlowCtrl = 0x20,
537 _1000bpsF = 0x10,
538 _100bps = 0x08,
539 _10bps = 0x04,
540 LinkStatus = 0x02,
541 FullDup = 0x01,
1da177e4 542
1da177e4 543 /* _TBICSRBit */
07d3f51f 544 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 545
546 /* DumpCounterCommand */
07d3f51f 547 CounterDump = 0x8,
1da177e4
LT		 548};
549
2b7b4318
FR		 550enum rtl_desc_bit {
551 /* First doubleword. */
1da177e4
LT		 552 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
553 RingEnd = (1 << 30), /* End of descriptor ring */
554 FirstFrag = (1 << 29), /* First segment of a packet */
555 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 556};
557
558/* Generic case. */
559enum rtl_tx_desc_bit {
560 /* First doubleword. */
561 TD_LSO = (1 << 27), /* Large Send Offload */
562#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 563
2b7b4318
FR		 564 /* Second doubleword. */
565 TxVlanTag = (1 << 17), /* Add VLAN tag */
566};
567
568/* 8169, 8168b and 810x except 8102e. */
569enum rtl_tx_desc_bit_0 {
570 /* First doubleword. */
571#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
572 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
573 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
574 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
575};
576
577/* 8102e, 8168c and beyond. */
578enum rtl_tx_desc_bit_1 {
579 /* Second doubleword. */
580#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
581 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
582 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
583 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
584};
1da177e4 585
2b7b4318
FR		 586static const struct rtl_tx_desc_info {
587 struct {
588 u32 udp;
589 u32 tcp;
590 } checksum;
591 u16 mss_shift;
592 u16 opts_offset;
593} tx_desc_info [] = {
594 [RTL_TD_0] = {
595 .checksum = {
596 .udp = TD0_IP_CS | TD0_UDP_CS,
597 .tcp = TD0_IP_CS | TD0_TCP_CS
598 },
599 .mss_shift = TD0_MSS_SHIFT,
600 .opts_offset = 0
601 },
602 [RTL_TD_1] = {
603 .checksum = {
604 .udp = TD1_IP_CS | TD1_UDP_CS,
605 .tcp = TD1_IP_CS | TD1_TCP_CS
606 },
607 .mss_shift = TD1_MSS_SHIFT,
608 .opts_offset = 1
609 }
610};
611
612enum rtl_rx_desc_bit {
1da177e4
LT		 613 /* Rx private */
614 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
615 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
616
617#define RxProtoUDP (PID1)
618#define RxProtoTCP (PID0)
619#define RxProtoIP (PID1 | PID0)
620#define RxProtoMask RxProtoIP
621
622 IPFail = (1 << 16), /* IP checksum failed */
623 UDPFail = (1 << 15), /* UDP/IP checksum failed */
624 TCPFail = (1 << 14), /* TCP/IP checksum failed */
625 RxVlanTag = (1 << 16), /* VLAN tag available */
626};
627
628#define RsvdMask 0x3fffc000
629
630struct TxDesc {
6cccd6e7
REB		 631 __le32 opts1;
632 __le32 opts2;
633 __le64 addr;
1da177e4
LT		 634};
635
636struct RxDesc {
6cccd6e7
REB		 637 __le32 opts1;
638 __le32 opts2;
639 __le64 addr;
1da177e4
LT		 640};
641
642struct ring_info {
643 struct sk_buff *skb;
644 u32 len;
645 u8 __pad[sizeof(void *) - sizeof(u32)];
646};
647
f23e7fda 648enum features {
ccdffb9a
FR		 649 RTL_FEATURE_WOL = (1 << 0),
650 RTL_FEATURE_MSI = (1 << 1),
651 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 652};
653
355423d0
IV		 654struct rtl8169_counters {
655 __le64 tx_packets;
656 __le64 rx_packets;
657 __le64 tx_errors;
658 __le32 rx_errors;
659 __le16 rx_missed;
660 __le16 align_errors;
661 __le32 tx_one_collision;
662 __le32 tx_multi_collision;
663 __le64 rx_unicast;
664 __le64 rx_broadcast;
665 __le32 rx_multicast;
666 __le16 tx_aborted;
667 __le16 tx_underun;
668};
669
da78dbff 670enum rtl_flag {
6c4a70c5 671 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 672 RTL_FLAG_TASK_SLOW_PENDING,
673 RTL_FLAG_TASK_RESET_PENDING,
674 RTL_FLAG_TASK_PHY_PENDING,
675 RTL_FLAG_MAX
676};
677
1da177e4
LT		 678struct rtl8169_private {
679 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 680 struct pci_dev *pci_dev;
c4028958 681 struct net_device *dev;
bea3348e 682 struct napi_struct napi;
b57b7e5a 683 u32 msg_enable;
2b7b4318
FR		 684 u16 txd_version;
685 u16 mac_version;
1da177e4
LT		 686 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
687 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
688 u32 dirty_rx;
689 u32 dirty_tx;
690 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
691 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
692 dma_addr_t TxPhyAddr;
693 dma_addr_t RxPhyAddr;
6f0333b8 694 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 695 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 696 struct timer_list timer;
697 u16 cp_cmd;
da78dbff
FR		 698
699 u16 event_slow;
c0e45c1c 700
701 struct mdio_ops {
702 void (*write)(void __iomem *, int, int);
703 int (*read)(void __iomem *, int);
704 } mdio_ops;
705
065c27c1 706 struct pll_power_ops {
707 void (*down)(struct rtl8169_private *);
708 void (*up)(struct rtl8169_private *);
709 } pll_power_ops;
710
d58d46b5
FR		 711 struct jumbo_ops {
712 void (*enable)(struct rtl8169_private *);
713 void (*disable)(struct rtl8169_private *);
714 } jumbo_ops;
715
54405cde 716 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 717 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 718 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 719 void (*hw_start)(struct net_device *);
4da19633 720 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 721 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 722 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 723
724 struct {
da78dbff
FR		 725 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
726 struct mutex mutex;
4422bcd4
FR		 727 struct work_struct work;
728 } wk;
729
f23e7fda 730 unsigned features;
ccdffb9a
FR		 731
732 struct mii_if_info mii;
355423d0 733 struct rtl8169_counters counters;
e1759441 734 u32 saved_wolopts;
e03f33af 735 u32 opts1_mask;
f1e02ed1 736
b6ffd97f
FR		 737 struct rtl_fw {
738 const struct firmware *fw;
1c361efb
FR		 739
740#define RTL_VER_SIZE 32
741
742 char version[RTL_VER_SIZE];
743
744 struct rtl_fw_phy_action {
745 __le32 *code;
746 size_t size;
747 } phy_action;
b6ffd97f 748 } *rtl_fw;
497888cf 749#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
1da177e4
LT		 750};
751
979b6c13 752MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 753MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 754module_param(use_dac, int, 0);
4300e8c7 755MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 756module_param_named(debug, debug.msg_enable, int, 0);
757MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 758MODULE_LICENSE("GPL");
759MODULE_VERSION(RTL8169_VERSION);
bca03d5f 760MODULE_FIRMWARE(FIRMWARE_8168D_1);
761MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 762MODULE_FIRMWARE(FIRMWARE_8168E_1);
763MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 764MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 765MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 766MODULE_FIRMWARE(FIRMWARE_8168F_1);
767MODULE_FIRMWARE(FIRMWARE_8168F_2);
1da177e4
LT		 768
769static int rtl8169_open(struct net_device *dev);
61357325
SH		 770static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
771 struct net_device *dev);
7d12e780 772static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 773static int rtl8169_init_ring(struct net_device *dev);
07ce4064 774static void rtl_hw_start(struct net_device *dev);
1da177e4 775static int rtl8169_close(struct net_device *dev);
07ce4064 776static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 777static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 778static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
4dcb7d33 779static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
99f252b0 780static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 781static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 782
da78dbff
FR		 783static void rtl_lock_work(struct rtl8169_private *tp)
784{
785 mutex_lock(&tp->wk.mutex);
786}
787
788static void rtl_unlock_work(struct rtl8169_private *tp)
789{
790 mutex_unlock(&tp->wk.mutex);
791}
792
d58d46b5
FR		 793static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
794{
795 int cap = pci_pcie_cap(pdev);
796
797 if (cap) {
798 u16 ctl;
799
800 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
801 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
802 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
803 }
804}
805
b646d900 806static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
807{
808 void __iomem *ioaddr = tp->mmio_addr;
809 int i;
810
811 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
812 for (i = 0; i < 20; i++) {
813 udelay(100);
814 if (RTL_R32(OCPAR) & OCPAR_FLAG)
815 break;
816 }
817 return RTL_R32(OCPDR);
818}
819
820static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
821{
822 void __iomem *ioaddr = tp->mmio_addr;
823 int i;
824
825 RTL_W32(OCPDR, data);
826 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
827 for (i = 0; i < 20; i++) {
828 udelay(100);
829 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
830 break;
831 }
832}
833
fac5b3ca 834static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 835{
fac5b3ca 836 void __iomem *ioaddr = tp->mmio_addr;
b646d900 837 int i;
838
839 RTL_W8(ERIDR, cmd);
840 RTL_W32(ERIAR, 0x800010e8);
841 msleep(2);
842 for (i = 0; i < 5; i++) {
843 udelay(100);
1e4e82ba 844 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 845 break;
846 }
847
fac5b3ca 848 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 849}
850
851#define OOB_CMD_RESET 0x00
852#define OOB_CMD_DRIVER_START 0x05
853#define OOB_CMD_DRIVER_STOP 0x06
854
cecb5fd7
FR		 855static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
856{
857 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
858}
859
b646d900 860static void rtl8168_driver_start(struct rtl8169_private *tp)
861{
cecb5fd7 862 u16 reg;
b646d900 863 int i;
864
865 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
866
cecb5fd7 867 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 868
b646d900 869 for (i = 0; i < 10; i++) {
870 msleep(10);
4804b3b3 871 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 872 break;
873 }
874}
875
876static void rtl8168_driver_stop(struct rtl8169_private *tp)
877{
cecb5fd7 878 u16 reg;
b646d900 879 int i;
880
881 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
882
cecb5fd7 883 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 884
b646d900 885 for (i = 0; i < 10; i++) {
886 msleep(10);
4804b3b3 887 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 888 break;
889 }
890}
891
4804b3b3 892static int r8168dp_check_dash(struct rtl8169_private *tp)
893{
cecb5fd7 894 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 895
cecb5fd7 896 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 897}
b646d900 898
4da19633 899static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 900{
901 int i;
902
a6baf3af 903 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 904
2371408c 905 for (i = 20; i > 0; i--) {
07d3f51f
FR		 906 /*
907 * Check if the RTL8169 has completed writing to the specified
908 * MII register.
909 */
5b0384f4 910 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 911 break;
2371408c 912 udelay(25);
1da177e4 913 }
024a07ba 914 /*
81a95f04
TT		 915 * According to hardware specs a 20us delay is required after write
916 * complete indication, but before sending next command.
024a07ba 917 */
81a95f04 918 udelay(20);
1da177e4
LT		 919}
920
4da19633 921static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 922{
923 int i, value = -1;
924
a6baf3af 925 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 926
2371408c 927 for (i = 20; i > 0; i--) {
07d3f51f
FR		 928 /*
929 * Check if the RTL8169 has completed retrieving data from
930 * the specified MII register.
931 */
1da177e4 932 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 933 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 934 break;
935 }
2371408c 936 udelay(25);
1da177e4 937 }
81a95f04
TT		 938 /*
939 * According to hardware specs a 20us delay is required after read
940 * complete indication, but before sending next command.
941 */
942 udelay(20);
943
1da177e4
LT		 944 return value;
945}
946
c0e45c1c 947static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
948{
949 int i;
950
951 RTL_W32(OCPDR, data |
952 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
953 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
954 RTL_W32(EPHY_RXER_NUM, 0);
955
956 for (i = 0; i < 100; i++) {
957 mdelay(1);
958 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
959 break;
960 }
961}
962
963static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
964{
965 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
966 (value & OCPDR_DATA_MASK));
967}
968
969static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
970{
971 int i;
972
973 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
974
975 mdelay(1);
976 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
977 RTL_W32(EPHY_RXER_NUM, 0);
978
979 for (i = 0; i < 100; i++) {
980 mdelay(1);
981 if (RTL_R32(OCPAR) & OCPAR_FLAG)
982 break;
983 }
984
985 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
986}
987
e6de30d6 988#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
989
990static void r8168dp_2_mdio_start(void __iomem *ioaddr)
991{
992 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
993}
994
995static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
996{
997 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
998}
999
1000static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1001{
1002 r8168dp_2_mdio_start(ioaddr);
1003
1004 r8169_mdio_write(ioaddr, reg_addr, value);
1005
1006 r8168dp_2_mdio_stop(ioaddr);
1007}
1008
1009static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1010{
1011 int value;
1012
1013 r8168dp_2_mdio_start(ioaddr);
1014
1015 value = r8169_mdio_read(ioaddr, reg_addr);
1016
1017 r8168dp_2_mdio_stop(ioaddr);
1018
1019 return value;
1020}
1021
4da19633 1022static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1023{
c0e45c1c 1024 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 1025}
1026
4da19633 1027static int rtl_readphy(struct rtl8169_private *tp, int location)
1028{
c0e45c1c 1029 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 1030}
1031
1032static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1033{
1034 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1035}
1036
1037static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1038{
1039 int val;
1040
4da19633 1041 val = rtl_readphy(tp, reg_addr);
1042 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1043}
1044
ccdffb9a
FR		 1045static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1046 int val)
1047{
1048 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1049
4da19633 1050 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1051}
1052
1053static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1054{
1055 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1056
4da19633 1057 return rtl_readphy(tp, location);
ccdffb9a
FR		 1058}
1059
dacf8154
FR		 1060static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1061{
1062 unsigned int i;
1063
1064 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1065 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1066
1067 for (i = 0; i < 100; i++) {
1068 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1069 break;
1070 udelay(10);
1071 }
1072}
1073
1074static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1075{
1076 u16 value = 0xffff;
1077 unsigned int i;
1078
1079 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1080
1081 for (i = 0; i < 100; i++) {
1082 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1083 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1084 break;
1085 }
1086 udelay(10);
1087 }
1088
1089 return value;
1090}
1091
1092static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1093{
1094 unsigned int i;
1095
1096 RTL_W32(CSIDR, value);
1097 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1098 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1099
1100 for (i = 0; i < 100; i++) {
1101 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1102 break;
1103 udelay(10);
1104 }
1105}
1106
1107static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1108{
1109 u32 value = ~0x00;
1110 unsigned int i;
1111
1112 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1113 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1114
1115 for (i = 0; i < 100; i++) {
1116 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1117 value = RTL_R32(CSIDR);
1118 break;
1119 }
1120 udelay(10);
1121 }
1122
1123 return value;
1124}
1125
133ac40a
HW		 1126static
1127void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1128{
1129 unsigned int i;
1130
1131 BUG_ON((addr & 3) || (mask == 0));
1132 RTL_W32(ERIDR, val);
1133 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1134
1135 for (i = 0; i < 100; i++) {
1136 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1137 break;
1138 udelay(100);
1139 }
1140}
1141
1142static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1143{
1144 u32 value = ~0x00;
1145 unsigned int i;
1146
1147 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1148
1149 for (i = 0; i < 100; i++) {
1150 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1151 value = RTL_R32(ERIDR);
1152 break;
1153 }
1154 udelay(100);
1155 }
1156
1157 return value;
1158}
1159
1160static void
1161rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1162{
1163 u32 val;
1164
1165 val = rtl_eri_read(ioaddr, addr, type);
1166 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1167}
1168
c28aa385 1169struct exgmac_reg {
1170 u16 addr;
1171 u16 mask;
1172 u32 val;
1173};
1174
1175static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1176 const struct exgmac_reg *r, int len)
1177{
1178 while (len-- > 0) {
1179 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1180 r++;
1181 }
1182}
1183
daf9df6d 1184static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1185{
1186 u8 value = 0xff;
1187 unsigned int i;
1188
1189 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1190
1191 for (i = 0; i < 300; i++) {
1192 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1193 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1194 break;
1195 }
1196 udelay(100);
1197 }
1198
1199 return value;
1200}
1201
9085cdfa
FR		 1202static u16 rtl_get_events(struct rtl8169_private *tp)
1203{
1204 void __iomem *ioaddr = tp->mmio_addr;
1205
1206 return RTL_R16(IntrStatus);
1207}
1208
1209static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1210{
1211 void __iomem *ioaddr = tp->mmio_addr;
1212
1213 RTL_W16(IntrStatus, bits);
1214 mmiowb();
1215}
1216
1217static void rtl_irq_disable(struct rtl8169_private *tp)
1218{
1219 void __iomem *ioaddr = tp->mmio_addr;
1220
1221 RTL_W16(IntrMask, 0);
1222 mmiowb();
1223}
1224
3e990ff5
FR		 1225static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1226{
1227 void __iomem *ioaddr = tp->mmio_addr;
1228
1229 RTL_W16(IntrMask, bits);
1230}
1231
da78dbff
FR		 1232#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1233#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1234#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1235
1236static void rtl_irq_enable_all(struct rtl8169_private *tp)
1237{
1238 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1239}
1240
811fd301 1241static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1242{
811fd301 1243 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1244
9085cdfa 1245 rtl_irq_disable(tp);
da78dbff 1246 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1247 RTL_R8(ChipCmd);
1da177e4
LT		 1248}
1249
4da19633 1250static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1251{
4da19633 1252 void __iomem *ioaddr = tp->mmio_addr;
1253
1da177e4
LT		 1254 return RTL_R32(TBICSR) & TBIReset;
1255}
1256
4da19633 1257static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1258{
4da19633 1259 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1260}
1261
1262static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1263{
1264 return RTL_R32(TBICSR) & TBILinkOk;
1265}
1266
1267static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1268{
1269 return RTL_R8(PHYstatus) & LinkStatus;
1270}
1271
4da19633 1272static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1273{
4da19633 1274 void __iomem *ioaddr = tp->mmio_addr;
1275
1da177e4
LT		 1276 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1277}
1278
4da19633 1279static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1280{
1281 unsigned int val;
1282
4da19633 1283 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1284 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1285}
1286
70090424
HW		 1287static void rtl_link_chg_patch(struct rtl8169_private *tp)
1288{
1289 void __iomem *ioaddr = tp->mmio_addr;
1290 struct net_device *dev = tp->dev;
1291
1292 if (!netif_running(dev))
1293 return;
1294
1295 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1296 if (RTL_R8(PHYstatus) & _1000bpsF) {
1297 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1298 0x00000011, ERIAR_EXGMAC);
1299 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1300 0x00000005, ERIAR_EXGMAC);
1301 } else if (RTL_R8(PHYstatus) & _100bps) {
1302 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1303 0x0000001f, ERIAR_EXGMAC);
1304 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1305 0x00000005, ERIAR_EXGMAC);
1306 } else {
1307 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1308 0x0000001f, ERIAR_EXGMAC);
1309 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1310 0x0000003f, ERIAR_EXGMAC);
1311 }
1312 /* Reset packet filter */
1313 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1314 ERIAR_EXGMAC);
1315 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1316 ERIAR_EXGMAC);
c2218925
HW		 1317 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1318 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1319 if (RTL_R8(PHYstatus) & _1000bpsF) {
1320 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1321 0x00000011, ERIAR_EXGMAC);
1322 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1323 0x00000005, ERIAR_EXGMAC);
1324 } else {
1325 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1326 0x0000001f, ERIAR_EXGMAC);
1327 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1328 0x0000003f, ERIAR_EXGMAC);
1329 }
70090424
HW		 1330 }
1331}
1332
e4fbce74 1333static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1334 struct rtl8169_private *tp,
1335 void __iomem *ioaddr, bool pm)
1da177e4 1336{
1da177e4 1337 if (tp->link_ok(ioaddr)) {
70090424 1338 rtl_link_chg_patch(tp);
e1759441 1339 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1340 if (pm)
1341 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1342 netif_carrier_on(dev);
1519e57f
FR		 1343 if (net_ratelimit())
1344 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1345 } else {
1da177e4 1346 netif_carrier_off(dev);
bf82c189 1347 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1348 if (pm)
10953db8 1349 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1350 }
1da177e4
LT		 1351}
1352
e4fbce74
RW		 1353static void rtl8169_check_link_status(struct net_device *dev,
1354 struct rtl8169_private *tp,
1355 void __iomem *ioaddr)
1356{
1357 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1358}
1359
e1759441
RW		 1360#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1361
1362static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1363{
61a4dcc2
FR		 1364 void __iomem *ioaddr = tp->mmio_addr;
1365 u8 options;
e1759441 1366 u32 wolopts = 0;
61a4dcc2
FR		 1367
1368 options = RTL_R8(Config1);
1369 if (!(options & PMEnable))
e1759441 1370 return 0;
61a4dcc2
FR		 1371
1372 options = RTL_R8(Config3);
1373 if (options & LinkUp)
e1759441 1374 wolopts |= WAKE_PHY;
61a4dcc2 1375 if (options & MagicPacket)
e1759441 1376 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1377
1378 options = RTL_R8(Config5);
1379 if (options & UWF)
e1759441 1380 wolopts |= WAKE_UCAST;
61a4dcc2 1381 if (options & BWF)
e1759441 1382 wolopts |= WAKE_BCAST;
61a4dcc2 1383 if (options & MWF)
e1759441 1384 wolopts |= WAKE_MCAST;
61a4dcc2 1385
e1759441 1386 return wolopts;
61a4dcc2
FR		 1387}
1388
e1759441 1389static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1390{
1391 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1392
da78dbff 1393 rtl_lock_work(tp);
e1759441
RW		 1394
1395 wol->supported = WAKE_ANY;
1396 wol->wolopts = __rtl8169_get_wol(tp);
1397
da78dbff 1398 rtl_unlock_work(tp);
e1759441
RW		 1399}
1400
1401static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1402{
61a4dcc2 1403 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1404 unsigned int i;
350f7596 1405 static const struct {
61a4dcc2
FR		 1406 u32 opt;
1407 u16 reg;
1408 u8 mask;
1409 } cfg[] = {
1410 { WAKE_ANY, Config1, PMEnable },
1411 { WAKE_PHY, Config3, LinkUp },
1412 { WAKE_MAGIC, Config3, MagicPacket },
1413 { WAKE_UCAST, Config5, UWF },
1414 { WAKE_BCAST, Config5, BWF },
1415 { WAKE_MCAST, Config5, MWF },
1416 { WAKE_ANY, Config5, LanWake }
1417 };
1418
61a4dcc2
FR		 1419 RTL_W8(Cfg9346, Cfg9346_Unlock);
1420
1421 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1422 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1423 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1424 options |= cfg[i].mask;
1425 RTL_W8(cfg[i].reg, options);
1426 }
1427
1428 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1429}
1430
1431static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1432{
1433 struct rtl8169_private *tp = netdev_priv(dev);
1434
da78dbff 1435 rtl_lock_work(tp);
61a4dcc2 1436
f23e7fda
FR		 1437 if (wol->wolopts)
1438 tp->features |= RTL_FEATURE_WOL;
1439 else
1440 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1441 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1442
1443 rtl_unlock_work(tp);
61a4dcc2 1444
ea80907f 1445 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1446
61a4dcc2
FR		 1447 return 0;
1448}
1449
31bd204f
FR		 1450static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1451{
85bffe6c 1452 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1453}
1454
1da177e4
LT		 1455static void rtl8169_get_drvinfo(struct net_device *dev,
1456 struct ethtool_drvinfo *info)
1457{
1458 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1459 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1460
68aad78c
RJ		 1461 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1462 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1463 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1464 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1465 if (!IS_ERR_OR_NULL(rtl_fw))
1466 strlcpy(info->fw_version, rtl_fw->version,
1467 sizeof(info->fw_version));
1da177e4
LT		 1468}
1469
1470static int rtl8169_get_regs_len(struct net_device *dev)
1471{
1472 return R8169_REGS_SIZE;
1473}
1474
1475static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1476 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1477{
1478 struct rtl8169_private *tp = netdev_priv(dev);
1479 void __iomem *ioaddr = tp->mmio_addr;
1480 int ret = 0;
1481 u32 reg;
1482
1483 reg = RTL_R32(TBICSR);
1484 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1485 (duplex == DUPLEX_FULL)) {
1486 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1487 } else if (autoneg == AUTONEG_ENABLE)
1488 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1489 else {
bf82c189
JP		 1490 netif_warn(tp, link, dev,
1491 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1492 ret = -EOPNOTSUPP;
1493 }
1494
1495 return ret;
1496}
1497
1498static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1499 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1500{
1501 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1502 int giga_ctrl, bmcr;
54405cde 1503 int rc = -EINVAL;
1da177e4 1504
716b50a3 1505 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1506
1507 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1508 int auto_nego;
1509
4da19633 1510 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1511 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1512 ADVERTISE_100HALF | ADVERTISE_100FULL);
1513
1514 if (adv & ADVERTISED_10baseT_Half)
1515 auto_nego |= ADVERTISE_10HALF;
1516 if (adv & ADVERTISED_10baseT_Full)
1517 auto_nego |= ADVERTISE_10FULL;
1518 if (adv & ADVERTISED_100baseT_Half)
1519 auto_nego |= ADVERTISE_100HALF;
1520 if (adv & ADVERTISED_100baseT_Full)
1521 auto_nego |= ADVERTISE_100FULL;
1522
3577aa1b 1523 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1524
4da19633 1525 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1526 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1527
3577aa1b 1528 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1529 if (tp->mii.supports_gmii) {
54405cde
ON		 1530 if (adv & ADVERTISED_1000baseT_Half)
1531 giga_ctrl |= ADVERTISE_1000HALF;
1532 if (adv & ADVERTISED_1000baseT_Full)
1533 giga_ctrl |= ADVERTISE_1000FULL;
1534 } else if (adv & (ADVERTISED_1000baseT_Half |
1535 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1536 netif_info(tp, link, dev,
1537 "PHY does not support 1000Mbps\n");
54405cde 1538 goto out;
bcf0bf90 1539 }
1da177e4 1540
3577aa1b 1541 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1542
4da19633 1543 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1544 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1545 } else {
1546 giga_ctrl = 0;
1547
1548 if (speed == SPEED_10)
1549 bmcr = 0;
1550 else if (speed == SPEED_100)
1551 bmcr = BMCR_SPEED100;
1552 else
54405cde 1553 goto out;
3577aa1b 1554
1555 if (duplex == DUPLEX_FULL)
1556 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1557 }
1558
4da19633 1559 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1560
cecb5fd7
FR		 1561 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1562 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1563 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1564 rtl_writephy(tp, 0x17, 0x2138);
1565 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1566 } else {
4da19633 1567 rtl_writephy(tp, 0x17, 0x2108);
1568 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1569 }
1570 }
1571
54405cde
ON		 1572 rc = 0;
1573out:
1574 return rc;
1da177e4
LT		 1575}
1576
1577static int rtl8169_set_speed(struct net_device *dev,
54405cde 1578 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1579{
1580 struct rtl8169_private *tp = netdev_priv(dev);
1581 int ret;
1582
54405cde 1583 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1584 if (ret < 0)
1585 goto out;
1da177e4 1586
4876cc1e
FR		 1587 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1588 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1589 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1590 }
1591out:
1da177e4
LT		 1592 return ret;
1593}
1594
1595static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1596{
1597 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1598 int ret;
1599
4876cc1e
FR		 1600 del_timer_sync(&tp->timer);
1601
da78dbff 1602 rtl_lock_work(tp);
cecb5fd7 1603 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1604 cmd->duplex, cmd->advertising);
da78dbff 1605 rtl_unlock_work(tp);
5b0384f4 1606
1da177e4
LT		 1607 return ret;
1608}
1609
c8f44aff
MM		 1610static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1611 netdev_features_t features)
1da177e4 1612{
d58d46b5
FR		 1613 struct rtl8169_private *tp = netdev_priv(dev);
1614
2b7b4318 1615 if (dev->mtu > TD_MSS_MAX)
350fb32a 1616 features &= ~NETIF_F_ALL_TSO;
1da177e4 1617
d58d46b5
FR		 1618 if (dev->mtu > JUMBO_1K &&
1619 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1620 features &= ~NETIF_F_IP_CSUM;
1621
350fb32a 1622 return features;
1da177e4
LT		 1623}
1624
da78dbff
FR		 1625static void __rtl8169_set_features(struct net_device *dev,
1626 netdev_features_t features)
1da177e4
LT		 1627{
1628 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1629
da78dbff 1630 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1631
350fb32a 1632 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1633 tp->cp_cmd |= RxChkSum;
1634 else
1635 tp->cp_cmd &= ~RxChkSum;
1636
350fb32a
MM		 1637 if (dev->features & NETIF_F_HW_VLAN_RX)
1638 tp->cp_cmd |= RxVlan;
1639 else
1640 tp->cp_cmd &= ~RxVlan;
1641
1da177e4
LT		 1642 RTL_W16(CPlusCmd, tp->cp_cmd);
1643 RTL_R16(CPlusCmd);
da78dbff 1644}
1da177e4 1645
da78dbff
FR		 1646static int rtl8169_set_features(struct net_device *dev,
1647 netdev_features_t features)
1648{
1649 struct rtl8169_private *tp = netdev_priv(dev);
1650
1651 rtl_lock_work(tp);
1652 __rtl8169_set_features(dev, features);
1653 rtl_unlock_work(tp);
1da177e4
LT		 1654
1655 return 0;
1656}
1657
da78dbff 1658
1da177e4
LT		 1659static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1660 struct sk_buff *skb)
1661{
eab6d18d 1662 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1663 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1664}
1665
7a8fc77b 1666static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1667{
1668 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1669
7a8fc77b
FR		 1670 if (opts2 & RxVlanTag)
1671 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1672
1da177e4 1673 desc->opts2 = 0;
1da177e4
LT		 1674}
1675
ccdffb9a 1676static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1677{
1678 struct rtl8169_private *tp = netdev_priv(dev);
1679 void __iomem *ioaddr = tp->mmio_addr;
1680 u32 status;
1681
1682 cmd->supported =
1683 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1684 cmd->port = PORT_FIBRE;
1685 cmd->transceiver = XCVR_INTERNAL;
1686
1687 status = RTL_R32(TBICSR);
1688 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1689 cmd->autoneg = !!(status & TBINwEnable);
1690
70739497 1691 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1692 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1693
1694 return 0;
1da177e4
LT		 1695}
1696
ccdffb9a 1697static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1698{
1699 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1700
1701 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1702}
1703
1704static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1705{
1706 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1707 int rc;
1da177e4 1708
da78dbff 1709 rtl_lock_work(tp);
ccdffb9a 1710 rc = tp->get_settings(dev, cmd);
da78dbff 1711 rtl_unlock_work(tp);
1da177e4 1712
ccdffb9a 1713 return rc;
1da177e4
LT		 1714}
1715
1716static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1717 void *p)
1718{
5b0384f4 1719 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1720
5b0384f4
FR		 1721 if (regs->len > R8169_REGS_SIZE)
1722 regs->len = R8169_REGS_SIZE;
1da177e4 1723
da78dbff 1724 rtl_lock_work(tp);
5b0384f4 1725 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1726 rtl_unlock_work(tp);
1da177e4
LT		 1727}
1728
b57b7e5a
SH		 1729static u32 rtl8169_get_msglevel(struct net_device *dev)
1730{
1731 struct rtl8169_private *tp = netdev_priv(dev);
1732
1733 return tp->msg_enable;
1734}
1735
1736static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1737{
1738 struct rtl8169_private *tp = netdev_priv(dev);
1739
1740 tp->msg_enable = value;
1741}
1742
d4a3a0fc
SH		 1743static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1744 "tx_packets",
1745 "rx_packets",
1746 "tx_errors",
1747 "rx_errors",
1748 "rx_missed",
1749 "align_errors",
1750 "tx_single_collisions",
1751 "tx_multi_collisions",
1752 "unicast",
1753 "broadcast",
1754 "multicast",
1755 "tx_aborted",
1756 "tx_underrun",
1757};
1758
b9f2c044 1759static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1760{
b9f2c044
JG		 1761 switch (sset) {
1762 case ETH_SS_STATS:
1763 return ARRAY_SIZE(rtl8169_gstrings);
1764 default:
1765 return -EOPNOTSUPP;
1766 }
d4a3a0fc
SH		 1767}
1768
355423d0 1769static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1770{
1771 struct rtl8169_private *tp = netdev_priv(dev);
1772 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1773 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1774 struct rtl8169_counters *counters;
1775 dma_addr_t paddr;
1776 u32 cmd;
355423d0 1777 int wait = 1000;
d4a3a0fc 1778
355423d0
IV		 1779 /*
1780 * Some chips are unable to dump tally counters when the receiver
1781 * is disabled.
1782 */
1783 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1784 return;
d4a3a0fc 1785
48addcc9 1786 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1787 if (!counters)
1788 return;
1789
1790 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1791 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1792 RTL_W32(CounterAddrLow, cmd);
1793 RTL_W32(CounterAddrLow, cmd | CounterDump);
1794
355423d0
IV		 1795 while (wait--) {
1796 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1797 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1798 break;
355423d0
IV		 1799 }
1800 udelay(10);
d4a3a0fc
SH		 1801 }
1802
1803 RTL_W32(CounterAddrLow, 0);
1804 RTL_W32(CounterAddrHigh, 0);
1805
48addcc9 1806 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1807}
1808
355423d0
IV		 1809static void rtl8169_get_ethtool_stats(struct net_device *dev,
1810 struct ethtool_stats *stats, u64 *data)
1811{
1812 struct rtl8169_private *tp = netdev_priv(dev);
1813
1814 ASSERT_RTNL();
1815
1816 rtl8169_update_counters(dev);
1817
1818 data[0] = le64_to_cpu(tp->counters.tx_packets);
1819 data[1] = le64_to_cpu(tp->counters.rx_packets);
1820 data[2] = le64_to_cpu(tp->counters.tx_errors);
1821 data[3] = le32_to_cpu(tp->counters.rx_errors);
1822 data[4] = le16_to_cpu(tp->counters.rx_missed);
1823 data[5] = le16_to_cpu(tp->counters.align_errors);
1824 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1825 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1826 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1827 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1828 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1829 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1830 data[12] = le16_to_cpu(tp->counters.tx_underun);
1831}
1832
d4a3a0fc
SH		 1833static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1834{
1835 switch(stringset) {
1836 case ETH_SS_STATS:
1837 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1838 break;
1839 }
1840}
1841
7282d491 1842static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1843 .get_drvinfo = rtl8169_get_drvinfo,
1844 .get_regs_len = rtl8169_get_regs_len,
1845 .get_link = ethtool_op_get_link,
1846 .get_settings = rtl8169_get_settings,
1847 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1848 .get_msglevel = rtl8169_get_msglevel,
1849 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1850 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1851 .get_wol = rtl8169_get_wol,
1852 .set_wol = rtl8169_set_wol,
d4a3a0fc 1853 .get_strings = rtl8169_get_strings,
b9f2c044 1854 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1855 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1856};
1857
07d3f51f 1858static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1859 struct net_device *dev, u8 default_version)
1da177e4 1860{
5d320a20 1861 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1862 /*
1863 * The driver currently handles the 8168Bf and the 8168Be identically
1864 * but they can be identified more specifically through the test below
1865 * if needed:
1866 *
1867 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1868 *
1869 * Same thing for the 8101Eb and the 8101Ec:
1870 *
1871 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1872 */
3744100e 1873 static const struct rtl_mac_info {
1da177e4 1874 u32 mask;
e3cf0cc0 1875 u32 val;
1da177e4
LT		 1876 int mac_version;
1877 } mac_info[] = {
c2218925
HW		 1878 /* 8168F family. */
1879 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1880 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1881
01dc7fec 1882 /* 8168E family. */
70090424 1883 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1884 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1885 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1886 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1887
5b538df9 1888 /* 8168D family. */
daf9df6d 1889 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1890 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1891 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1892
e6de30d6 1893 /* 8168DP family. */
1894 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1895 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1896 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1897
ef808d50 1898 /* 8168C family. */
17c99297 1899 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1900 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1901 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1902 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1903 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1904 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1905 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1906 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1907 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1908
1909 /* 8168B family. */
1910 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1911 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1912 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1913 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1914
1915 /* 8101 family. */
36a0e6c2 1916 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1917 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1918 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1919 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1920 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1921 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1922 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1923 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1924 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1925 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1926 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1927 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1928 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1929 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1930 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1931 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1932 /* FIXME: where did these entries come from ? -- FR */
1933 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1934 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1935
1936 /* 8110 family. */
1937 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1938 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1939 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1940 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1941 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1942 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1943
f21b75e9
JD		 1944 /* Catch-all */
1945 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1946 };
1947 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1948 u32 reg;
1949
e3cf0cc0
FR		 1950 reg = RTL_R32(TxConfig);
1951 while ((reg & p->mask) != p->val)
1da177e4
LT		 1952 p++;
1953 tp->mac_version = p->mac_version;
5d320a20
FR		 1954
1955 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1956 netif_notice(tp, probe, dev,
1957 "unknown MAC, using family default\n");
1958 tp->mac_version = default_version;
1959 }
1da177e4
LT		 1960}
1961
1962static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1963{
bcf0bf90 1964 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1965}
1966
867763c1
FR		 1967struct phy_reg {
1968 u16 reg;
1969 u16 val;
1970};
1971
4da19633 1972static void rtl_writephy_batch(struct rtl8169_private *tp,
1973 const struct phy_reg *regs, int len)
867763c1
FR		 1974{
1975 while (len-- > 0) {
4da19633 1976 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1977 regs++;
1978 }
1979}
1980
bca03d5f 1981#define PHY_READ 0x00000000
1982#define PHY_DATA_OR 0x10000000
1983#define PHY_DATA_AND 0x20000000
1984#define PHY_BJMPN 0x30000000
1985#define PHY_READ_EFUSE 0x40000000
1986#define PHY_READ_MAC_BYTE 0x50000000
1987#define PHY_WRITE_MAC_BYTE 0x60000000
1988#define PHY_CLEAR_READCOUNT 0x70000000
1989#define PHY_WRITE 0x80000000
1990#define PHY_READCOUNT_EQ_SKIP 0x90000000
1991#define PHY_COMP_EQ_SKIPN 0xa0000000
1992#define PHY_COMP_NEQ_SKIPN 0xb0000000
1993#define PHY_WRITE_PREVIOUS 0xc0000000
1994#define PHY_SKIPN 0xd0000000
1995#define PHY_DELAY_MS 0xe0000000
1996#define PHY_WRITE_ERI_WORD 0xf0000000
1997
960aee6c
HW		 1998struct fw_info {
1999 u32 magic;
2000 char version[RTL_VER_SIZE];
2001 __le32 fw_start;
2002 __le32 fw_len;
2003 u8 chksum;
2004} __packed;
2005
1c361efb
FR		 2006#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2007
2008static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2009{
b6ffd97f 2010 const struct firmware *fw = rtl_fw->fw;
960aee6c 2011 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2012 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2013 char *version = rtl_fw->version;
2014 bool rc = false;
2015
2016 if (fw->size < FW_OPCODE_SIZE)
2017 goto out;
960aee6c
HW		 2018
2019 if (!fw_info->magic) {
2020 size_t i, size, start;
2021 u8 checksum = 0;
2022
2023 if (fw->size < sizeof(*fw_info))
2024 goto out;
2025
2026 for (i = 0; i < fw->size; i++)
2027 checksum += fw->data[i];
2028 if (checksum != 0)
2029 goto out;
2030
2031 start = le32_to_cpu(fw_info->fw_start);
2032 if (start > fw->size)
2033 goto out;
2034
2035 size = le32_to_cpu(fw_info->fw_len);
2036 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2037 goto out;
2038
2039 memcpy(version, fw_info->version, RTL_VER_SIZE);
2040
2041 pa->code = (__le32 *)(fw->data + start);
2042 pa->size = size;
2043 } else {
1c361efb
FR		 2044 if (fw->size % FW_OPCODE_SIZE)
2045 goto out;
2046
2047 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2048
2049 pa->code = (__le32 *)fw->data;
2050 pa->size = fw->size / FW_OPCODE_SIZE;
2051 }
2052 version[RTL_VER_SIZE - 1] = 0;
2053
2054 rc = true;
2055out:
2056 return rc;
2057}
2058
fd112f2e
FR		 2059static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2060 struct rtl_fw_phy_action *pa)
1c361efb 2061{
fd112f2e 2062 bool rc = false;
1c361efb 2063 size_t index;
bca03d5f 2064
1c361efb
FR		 2065 for (index = 0; index < pa->size; index++) {
2066 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2067 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2068
42b82dc1 2069 switch(action & 0xf0000000) {
2070 case PHY_READ:
2071 case PHY_DATA_OR:
2072 case PHY_DATA_AND:
2073 case PHY_READ_EFUSE:
2074 case PHY_CLEAR_READCOUNT:
2075 case PHY_WRITE:
2076 case PHY_WRITE_PREVIOUS:
2077 case PHY_DELAY_MS:
2078 break;
2079
2080 case PHY_BJMPN:
2081 if (regno > index) {
fd112f2e 2082 netif_err(tp, ifup, tp->dev,
cecb5fd7 2083 "Out of range of firmware\n");
fd112f2e 2084 goto out;
42b82dc1 2085 }
2086 break;
2087 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2088 if (index + 2 >= pa->size) {
fd112f2e 2089 netif_err(tp, ifup, tp->dev,
cecb5fd7 2090 "Out of range of firmware\n");
fd112f2e 2091 goto out;
42b82dc1 2092 }
2093 break;
2094 case PHY_COMP_EQ_SKIPN:
2095 case PHY_COMP_NEQ_SKIPN:
2096 case PHY_SKIPN:
1c361efb 2097 if (index + 1 + regno >= pa->size) {
fd112f2e 2098 netif_err(tp, ifup, tp->dev,
cecb5fd7 2099 "Out of range of firmware\n");
fd112f2e 2100 goto out;
42b82dc1 2101 }
bca03d5f 2102 break;
2103
42b82dc1 2104 case PHY_READ_MAC_BYTE:
2105 case PHY_WRITE_MAC_BYTE:
2106 case PHY_WRITE_ERI_WORD:
2107 default:
fd112f2e 2108 netif_err(tp, ifup, tp->dev,
42b82dc1 2109 "Invalid action 0x%08x\n", action);
fd112f2e 2110 goto out;
bca03d5f 2111 }
2112 }
fd112f2e
FR		 2113 rc = true;
2114out:
2115 return rc;
2116}
bca03d5f 2117
fd112f2e
FR		 2118static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2119{
2120 struct net_device *dev = tp->dev;
2121 int rc = -EINVAL;
2122
2123 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2124 netif_err(tp, ifup, dev, "invalid firwmare\n");
2125 goto out;
2126 }
2127
2128 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2129 rc = 0;
2130out:
2131 return rc;
2132}
2133
2134static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2135{
2136 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2137 u32 predata, count;
2138 size_t index;
2139
2140 predata = count = 0;
42b82dc1 2141
1c361efb
FR		 2142 for (index = 0; index < pa->size; ) {
2143 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2144 u32 data = action & 0x0000ffff;
42b82dc1 2145 u32 regno = (action & 0x0fff0000) >> 16;
2146
2147 if (!action)
2148 break;
bca03d5f 2149
2150 switch(action & 0xf0000000) {
42b82dc1 2151 case PHY_READ:
2152 predata = rtl_readphy(tp, regno);
2153 count++;
2154 index++;
2155 break;
2156 case PHY_DATA_OR:
2157 predata |= data;
2158 index++;
2159 break;
2160 case PHY_DATA_AND:
2161 predata &= data;
2162 index++;
2163 break;
2164 case PHY_BJMPN:
2165 index -= regno;
2166 break;
2167 case PHY_READ_EFUSE:
2168 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2169 index++;
2170 break;
2171 case PHY_CLEAR_READCOUNT:
2172 count = 0;
2173 index++;
2174 break;
bca03d5f 2175 case PHY_WRITE:
42b82dc1 2176 rtl_writephy(tp, regno, data);
2177 index++;
2178 break;
2179 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2180 index += (count == data) ? 2 : 1;
bca03d5f 2181 break;
42b82dc1 2182 case PHY_COMP_EQ_SKIPN:
2183 if (predata == data)
2184 index += regno;
2185 index++;
2186 break;
2187 case PHY_COMP_NEQ_SKIPN:
2188 if (predata != data)
2189 index += regno;
2190 index++;
2191 break;
2192 case PHY_WRITE_PREVIOUS:
2193 rtl_writephy(tp, regno, predata);
2194 index++;
2195 break;
2196 case PHY_SKIPN:
2197 index += regno + 1;
2198 break;
2199 case PHY_DELAY_MS:
2200 mdelay(data);
2201 index++;
2202 break;
2203
2204 case PHY_READ_MAC_BYTE:
2205 case PHY_WRITE_MAC_BYTE:
2206 case PHY_WRITE_ERI_WORD:
bca03d5f 2207 default:
2208 BUG();
2209 }
2210 }
2211}
2212
f1e02ed1 2213static void rtl_release_firmware(struct rtl8169_private *tp)
2214{
b6ffd97f
FR		 2215 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2216 release_firmware(tp->rtl_fw->fw);
2217 kfree(tp->rtl_fw);
2218 }
2219 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2220}
2221
953a12cc 2222static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2223{
b6ffd97f 2224 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2225
2226 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2227 if (!IS_ERR_OR_NULL(rtl_fw))
2228 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2229}
2230
2231static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2232{
2233 if (rtl_readphy(tp, reg) != val)
2234 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2235 else
2236 rtl_apply_firmware(tp);
f1e02ed1 2237}
2238
4da19633 2239static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2240{
350f7596 2241 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2242 { 0x1f, 0x0001 },
2243 { 0x06, 0x006e },
2244 { 0x08, 0x0708 },
2245 { 0x15, 0x4000 },
2246 { 0x18, 0x65c7 },
1da177e4 2247
0b9b571d 2248 { 0x1f, 0x0001 },
2249 { 0x03, 0x00a1 },
2250 { 0x02, 0x0008 },
2251 { 0x01, 0x0120 },
2252 { 0x00, 0x1000 },
2253 { 0x04, 0x0800 },
2254 { 0x04, 0x0000 },
1da177e4 2255
0b9b571d 2256 { 0x03, 0xff41 },
2257 { 0x02, 0xdf60 },
2258 { 0x01, 0x0140 },
2259 { 0x00, 0x0077 },
2260 { 0x04, 0x7800 },
2261 { 0x04, 0x7000 },
2262
2263 { 0x03, 0x802f },
2264 { 0x02, 0x4f02 },
2265 { 0x01, 0x0409 },
2266 { 0x00, 0xf0f9 },
2267 { 0x04, 0x9800 },
2268 { 0x04, 0x9000 },
2269
2270 { 0x03, 0xdf01 },
2271 { 0x02, 0xdf20 },
2272 { 0x01, 0xff95 },
2273 { 0x00, 0xba00 },
2274 { 0x04, 0xa800 },
2275 { 0x04, 0xa000 },
2276
2277 { 0x03, 0xff41 },
2278 { 0x02, 0xdf20 },
2279 { 0x01, 0x0140 },
2280 { 0x00, 0x00bb },
2281 { 0x04, 0xb800 },
2282 { 0x04, 0xb000 },
2283
2284 { 0x03, 0xdf41 },
2285 { 0x02, 0xdc60 },
2286 { 0x01, 0x6340 },
2287 { 0x00, 0x007d },
2288 { 0x04, 0xd800 },
2289 { 0x04, 0xd000 },
2290
2291 { 0x03, 0xdf01 },
2292 { 0x02, 0xdf20 },
2293 { 0x01, 0x100a },
2294 { 0x00, 0xa0ff },
2295 { 0x04, 0xf800 },
2296 { 0x04, 0xf000 },
2297
2298 { 0x1f, 0x0000 },
2299 { 0x0b, 0x0000 },
2300 { 0x00, 0x9200 }
2301 };
1da177e4 2302
4da19633 2303 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2304}
2305
4da19633 2306static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2307{
350f7596 2308 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2309 { 0x1f, 0x0002 },
2310 { 0x01, 0x90d0 },
2311 { 0x1f, 0x0000 }
2312 };
2313
4da19633 2314 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2315}
2316
4da19633 2317static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2318{
2319 struct pci_dev *pdev = tp->pci_dev;
2e955856 2320
ccbae55e
SS		 2321 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2322 (pdev->subsystem_device != 0xe000))
2e955856 2323 return;
2324
4da19633 2325 rtl_writephy(tp, 0x1f, 0x0001);
2326 rtl_writephy(tp, 0x10, 0xf01b);
2327 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2328}
2329
4da19633 2330static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2331{
350f7596 2332 static const struct phy_reg phy_reg_init[] = {
2e955856 2333 { 0x1f, 0x0001 },
2334 { 0x04, 0x0000 },
2335 { 0x03, 0x00a1 },
2336 { 0x02, 0x0008 },
2337 { 0x01, 0x0120 },
2338 { 0x00, 0x1000 },
2339 { 0x04, 0x0800 },
2340 { 0x04, 0x9000 },
2341 { 0x03, 0x802f },
2342 { 0x02, 0x4f02 },
2343 { 0x01, 0x0409 },
2344 { 0x00, 0xf099 },
2345 { 0x04, 0x9800 },
2346 { 0x04, 0xa000 },
2347 { 0x03, 0xdf01 },
2348 { 0x02, 0xdf20 },
2349 { 0x01, 0xff95 },
2350 { 0x00, 0xba00 },
2351 { 0x04, 0xa800 },
2352 { 0x04, 0xf000 },
2353 { 0x03, 0xdf01 },
2354 { 0x02, 0xdf20 },
2355 { 0x01, 0x101a },
2356 { 0x00, 0xa0ff },
2357 { 0x04, 0xf800 },
2358 { 0x04, 0x0000 },
2359 { 0x1f, 0x0000 },
2360
2361 { 0x1f, 0x0001 },
2362 { 0x10, 0xf41b },
2363 { 0x14, 0xfb54 },
2364 { 0x18, 0xf5c7 },
2365 { 0x1f, 0x0000 },
2366
2367 { 0x1f, 0x0001 },
2368 { 0x17, 0x0cc0 },
2369 { 0x1f, 0x0000 }
2370 };
2371
4da19633 2372 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2373
4da19633 2374 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2375}
2376
4da19633 2377static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2378{
350f7596 2379 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2380 { 0x1f, 0x0001 },
2381 { 0x04, 0x0000 },
2382 { 0x03, 0x00a1 },
2383 { 0x02, 0x0008 },
2384 { 0x01, 0x0120 },
2385 { 0x00, 0x1000 },
2386 { 0x04, 0x0800 },
2387 { 0x04, 0x9000 },
2388 { 0x03, 0x802f },
2389 { 0x02, 0x4f02 },
2390 { 0x01, 0x0409 },
2391 { 0x00, 0xf099 },
2392 { 0x04, 0x9800 },
2393 { 0x04, 0xa000 },
2394 { 0x03, 0xdf01 },
2395 { 0x02, 0xdf20 },
2396 { 0x01, 0xff95 },
2397 { 0x00, 0xba00 },
2398 { 0x04, 0xa800 },
2399 { 0x04, 0xf000 },
2400 { 0x03, 0xdf01 },
2401 { 0x02, 0xdf20 },
2402 { 0x01, 0x101a },
2403 { 0x00, 0xa0ff },
2404 { 0x04, 0xf800 },
2405 { 0x04, 0x0000 },
2406 { 0x1f, 0x0000 },
2407
2408 { 0x1f, 0x0001 },
2409 { 0x0b, 0x8480 },
2410 { 0x1f, 0x0000 },
2411
2412 { 0x1f, 0x0001 },
2413 { 0x18, 0x67c7 },
2414 { 0x04, 0x2000 },
2415 { 0x03, 0x002f },
2416 { 0x02, 0x4360 },
2417 { 0x01, 0x0109 },
2418 { 0x00, 0x3022 },
2419 { 0x04, 0x2800 },
2420 { 0x1f, 0x0000 },
2421
2422 { 0x1f, 0x0001 },
2423 { 0x17, 0x0cc0 },
2424 { 0x1f, 0x0000 }
2425 };
2426
4da19633 2427 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2428}
2429
4da19633 2430static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2431{
350f7596 2432 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2433 { 0x10, 0xf41b },
2434 { 0x1f, 0x0000 }
2435 };
2436
4da19633 2437 rtl_writephy(tp, 0x1f, 0x0001);
2438 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2439
4da19633 2440 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2441}
2442
4da19633 2443static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2444{
350f7596 2445 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2446 { 0x1f, 0x0001 },
2447 { 0x10, 0xf41b },
2448 { 0x1f, 0x0000 }
2449 };
2450
4da19633 2451 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2452}
2453
4da19633 2454static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2455{
350f7596 2456 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2457 { 0x1f, 0x0000 },
2458 { 0x1d, 0x0f00 },
2459 { 0x1f, 0x0002 },
2460 { 0x0c, 0x1ec8 },
2461 { 0x1f, 0x0000 }
2462 };
2463
4da19633 2464 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2465}
2466
4da19633 2467static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2468{
350f7596 2469 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2470 { 0x1f, 0x0001 },
2471 { 0x1d, 0x3d98 },
2472 { 0x1f, 0x0000 }
2473 };
2474
4da19633 2475 rtl_writephy(tp, 0x1f, 0x0000);
2476 rtl_patchphy(tp, 0x14, 1 << 5);
2477 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2478
4da19633 2479 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2480}
2481
4da19633 2482static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2483{
350f7596 2484 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2485 { 0x1f, 0x0001 },
2486 { 0x12, 0x2300 },
867763c1
FR		 2487 { 0x1f, 0x0002 },
2488 { 0x00, 0x88d4 },
2489 { 0x01, 0x82b1 },
2490 { 0x03, 0x7002 },
2491 { 0x08, 0x9e30 },
2492 { 0x09, 0x01f0 },
2493 { 0x0a, 0x5500 },
2494 { 0x0c, 0x00c8 },
2495 { 0x1f, 0x0003 },
2496 { 0x12, 0xc096 },
2497 { 0x16, 0x000a },
f50d4275
FR		 2498 { 0x1f, 0x0000 },
2499 { 0x1f, 0x0000 },
2500 { 0x09, 0x2000 },
2501 { 0x09, 0x0000 }
867763c1
FR		 2502 };
2503
4da19633 2504 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2505
4da19633 2506 rtl_patchphy(tp, 0x14, 1 << 5);
2507 rtl_patchphy(tp, 0x0d, 1 << 5);
2508 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2509}
2510
4da19633 2511static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2512{
350f7596 2513 static const struct phy_reg phy_reg_init[] = {
f50d4275 2514 { 0x1f, 0x0001 },
7da97ec9 2515 { 0x12, 0x2300 },
f50d4275
FR		 2516 { 0x03, 0x802f },
2517 { 0x02, 0x4f02 },
2518 { 0x01, 0x0409 },
2519 { 0x00, 0xf099 },
2520 { 0x04, 0x9800 },
2521 { 0x04, 0x9000 },
2522 { 0x1d, 0x3d98 },
7da97ec9
FR		 2523 { 0x1f, 0x0002 },
2524 { 0x0c, 0x7eb8 },
f50d4275
FR		 2525 { 0x06, 0x0761 },
2526 { 0x1f, 0x0003 },
2527 { 0x16, 0x0f0a },
7da97ec9
FR		 2528 { 0x1f, 0x0000 }
2529 };
2530
4da19633 2531 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2532
4da19633 2533 rtl_patchphy(tp, 0x16, 1 << 0);
2534 rtl_patchphy(tp, 0x14, 1 << 5);
2535 rtl_patchphy(tp, 0x0d, 1 << 5);
2536 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2537}
2538
4da19633 2539static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2540{
350f7596 2541 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2542 { 0x1f, 0x0001 },
2543 { 0x12, 0x2300 },
2544 { 0x1d, 0x3d98 },
2545 { 0x1f, 0x0002 },
2546 { 0x0c, 0x7eb8 },
2547 { 0x06, 0x5461 },
2548 { 0x1f, 0x0003 },
2549 { 0x16, 0x0f0a },
2550 { 0x1f, 0x0000 }
2551 };
2552
4da19633 2553 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2554
4da19633 2555 rtl_patchphy(tp, 0x16, 1 << 0);
2556 rtl_patchphy(tp, 0x14, 1 << 5);
2557 rtl_patchphy(tp, 0x0d, 1 << 5);
2558 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2559}
2560
4da19633 2561static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2562{
4da19633 2563 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2564}
2565
bca03d5f 2566static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2567{
350f7596 2568 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2569 /* Channel Estimation */
5b538df9 2570 { 0x1f, 0x0001 },
daf9df6d 2571 { 0x06, 0x4064 },
2572 { 0x07, 0x2863 },
2573 { 0x08, 0x059c },
2574 { 0x09, 0x26b4 },
2575 { 0x0a, 0x6a19 },
2576 { 0x0b, 0xdcc8 },
2577 { 0x10, 0xf06d },
2578 { 0x14, 0x7f68 },
2579 { 0x18, 0x7fd9 },
2580 { 0x1c, 0xf0ff },
2581 { 0x1d, 0x3d9c },
5b538df9 2582 { 0x1f, 0x0003 },
daf9df6d 2583 { 0x12, 0xf49f },
2584 { 0x13, 0x070b },
2585 { 0x1a, 0x05ad },
bca03d5f 2586 { 0x14, 0x94c0 },
2587
2588 /*
2589 * Tx Error Issue
cecb5fd7 2590 * Enhance line driver power
bca03d5f 2591 */
5b538df9 2592 { 0x1f, 0x0002 },
daf9df6d 2593 { 0x06, 0x5561 },
2594 { 0x1f, 0x0005 },
2595 { 0x05, 0x8332 },
bca03d5f 2596 { 0x06, 0x5561 },
2597
2598 /*
2599 * Can not link to 1Gbps with bad cable
2600 * Decrease SNR threshold form 21.07dB to 19.04dB
2601 */
2602 { 0x1f, 0x0001 },
2603 { 0x17, 0x0cc0 },
daf9df6d 2604
5b538df9 2605 { 0x1f, 0x0000 },
bca03d5f 2606 { 0x0d, 0xf880 }
daf9df6d 2607 };
bca03d5f 2608 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2609
4da19633 2610 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2611
bca03d5f 2612 /*
2613 * Rx Error Issue
2614 * Fine Tune Switching regulator parameter
2615 */
4da19633 2616 rtl_writephy(tp, 0x1f, 0x0002);
2617 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2618 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2619
daf9df6d 2620 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2621 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2622 { 0x1f, 0x0002 },
2623 { 0x05, 0x669a },
2624 { 0x1f, 0x0005 },
2625 { 0x05, 0x8330 },
2626 { 0x06, 0x669a },
2627 { 0x1f, 0x0002 }
2628 };
2629 int val;
2630
4da19633 2631 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2632
4da19633 2633 val = rtl_readphy(tp, 0x0d);
daf9df6d 2634
2635 if ((val & 0x00ff) != 0x006c) {
350f7596 2636 static const u32 set[] = {
daf9df6d 2637 0x0065, 0x0066, 0x0067, 0x0068,
2638 0x0069, 0x006a, 0x006b, 0x006c
2639 };
2640 int i;
2641
4da19633 2642 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2643
2644 val &= 0xff00;
2645 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2646 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2647 }
2648 } else {
350f7596 2649 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2650 { 0x1f, 0x0002 },
2651 { 0x05, 0x6662 },
2652 { 0x1f, 0x0005 },
2653 { 0x05, 0x8330 },
2654 { 0x06, 0x6662 }
2655 };
2656
4da19633 2657 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2658 }
2659
bca03d5f 2660 /* RSET couple improve */
4da19633 2661 rtl_writephy(tp, 0x1f, 0x0002);
2662 rtl_patchphy(tp, 0x0d, 0x0300);
2663 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2664
bca03d5f 2665 /* Fine tune PLL performance */
4da19633 2666 rtl_writephy(tp, 0x1f, 0x0002);
2667 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2668 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2669
4da19633 2670 rtl_writephy(tp, 0x1f, 0x0005);
2671 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2672
2673 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2674
4da19633 2675 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2676}
2677
bca03d5f 2678static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2679{
350f7596 2680 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2681 /* Channel Estimation */
daf9df6d 2682 { 0x1f, 0x0001 },
2683 { 0x06, 0x4064 },
2684 { 0x07, 0x2863 },
2685 { 0x08, 0x059c },
2686 { 0x09, 0x26b4 },
2687 { 0x0a, 0x6a19 },
2688 { 0x0b, 0xdcc8 },
2689 { 0x10, 0xf06d },
2690 { 0x14, 0x7f68 },
2691 { 0x18, 0x7fd9 },
2692 { 0x1c, 0xf0ff },
2693 { 0x1d, 0x3d9c },
2694 { 0x1f, 0x0003 },
2695 { 0x12, 0xf49f },
2696 { 0x13, 0x070b },
2697 { 0x1a, 0x05ad },
2698 { 0x14, 0x94c0 },
2699
bca03d5f 2700 /*
2701 * Tx Error Issue
cecb5fd7 2702 * Enhance line driver power
bca03d5f 2703 */
daf9df6d 2704 { 0x1f, 0x0002 },
2705 { 0x06, 0x5561 },
2706 { 0x1f, 0x0005 },
2707 { 0x05, 0x8332 },
bca03d5f 2708 { 0x06, 0x5561 },
2709
2710 /*
2711 * Can not link to 1Gbps with bad cable
2712 * Decrease SNR threshold form 21.07dB to 19.04dB
2713 */
2714 { 0x1f, 0x0001 },
2715 { 0x17, 0x0cc0 },
daf9df6d 2716
2717 { 0x1f, 0x0000 },
bca03d5f 2718 { 0x0d, 0xf880 }
5b538df9 2719 };
bca03d5f 2720 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2721
4da19633 2722 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2723
daf9df6d 2724 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2725 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2726 { 0x1f, 0x0002 },
2727 { 0x05, 0x669a },
5b538df9 2728 { 0x1f, 0x0005 },
daf9df6d 2729 { 0x05, 0x8330 },
2730 { 0x06, 0x669a },
2731
2732 { 0x1f, 0x0002 }
2733 };
2734 int val;
2735
4da19633 2736 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2737
4da19633 2738 val = rtl_readphy(tp, 0x0d);
daf9df6d 2739 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2740 static const u32 set[] = {
daf9df6d 2741 0x0065, 0x0066, 0x0067, 0x0068,
2742 0x0069, 0x006a, 0x006b, 0x006c
2743 };
2744 int i;
2745
4da19633 2746 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2747
2748 val &= 0xff00;
2749 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2750 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2751 }
2752 } else {
350f7596 2753 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2754 { 0x1f, 0x0002 },
2755 { 0x05, 0x2642 },
5b538df9 2756 { 0x1f, 0x0005 },
daf9df6d 2757 { 0x05, 0x8330 },
2758 { 0x06, 0x2642 }
5b538df9
FR		 2759 };
2760
4da19633 2761 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2762 }
2763
bca03d5f 2764 /* Fine tune PLL performance */
4da19633 2765 rtl_writephy(tp, 0x1f, 0x0002);
2766 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2767 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2768
bca03d5f 2769 /* Switching regulator Slew rate */
4da19633 2770 rtl_writephy(tp, 0x1f, 0x0002);
2771 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2772
4da19633 2773 rtl_writephy(tp, 0x1f, 0x0005);
2774 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2775
2776 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2777
4da19633 2778 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2779}
2780
4da19633 2781static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2782{
350f7596 2783 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2784 { 0x1f, 0x0002 },
2785 { 0x10, 0x0008 },
2786 { 0x0d, 0x006c },
2787
2788 { 0x1f, 0x0000 },
2789 { 0x0d, 0xf880 },
2790
2791 { 0x1f, 0x0001 },
2792 { 0x17, 0x0cc0 },
2793
2794 { 0x1f, 0x0001 },
2795 { 0x0b, 0xa4d8 },
2796 { 0x09, 0x281c },
2797 { 0x07, 0x2883 },
2798 { 0x0a, 0x6b35 },
2799 { 0x1d, 0x3da4 },
2800 { 0x1c, 0xeffd },
2801 { 0x14, 0x7f52 },
2802 { 0x18, 0x7fc6 },
2803 { 0x08, 0x0601 },
2804 { 0x06, 0x4063 },
2805 { 0x10, 0xf074 },
2806 { 0x1f, 0x0003 },
2807 { 0x13, 0x0789 },
2808 { 0x12, 0xf4bd },
2809 { 0x1a, 0x04fd },
2810 { 0x14, 0x84b0 },
2811 { 0x1f, 0x0000 },
2812 { 0x00, 0x9200 },
2813
2814 { 0x1f, 0x0005 },
2815 { 0x01, 0x0340 },
2816 { 0x1f, 0x0001 },
2817 { 0x04, 0x4000 },
2818 { 0x03, 0x1d21 },
2819 { 0x02, 0x0c32 },
2820 { 0x01, 0x0200 },
2821 { 0x00, 0x5554 },
2822 { 0x04, 0x4800 },
2823 { 0x04, 0x4000 },
2824 { 0x04, 0xf000 },
2825 { 0x03, 0xdf01 },
2826 { 0x02, 0xdf20 },
2827 { 0x01, 0x101a },
2828 { 0x00, 0xa0ff },
2829 { 0x04, 0xf800 },
2830 { 0x04, 0xf000 },
2831 { 0x1f, 0x0000 },
2832
2833 { 0x1f, 0x0007 },
2834 { 0x1e, 0x0023 },
2835 { 0x16, 0x0000 },
2836 { 0x1f, 0x0000 }
2837 };
2838
4da19633 2839 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2840}
2841
e6de30d6 2842static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2843{
2844 static const struct phy_reg phy_reg_init[] = {
2845 { 0x1f, 0x0001 },
2846 { 0x17, 0x0cc0 },
2847
2848 { 0x1f, 0x0007 },
2849 { 0x1e, 0x002d },
2850 { 0x18, 0x0040 },
2851 { 0x1f, 0x0000 }
2852 };
2853
2854 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2855 rtl_patchphy(tp, 0x0d, 1 << 5);
2856}
2857
70090424 2858static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2859{
2860 static const struct phy_reg phy_reg_init[] = {
2861 /* Enable Delay cap */
2862 { 0x1f, 0x0005 },
2863 { 0x05, 0x8b80 },
2864 { 0x06, 0xc896 },
2865 { 0x1f, 0x0000 },
2866
2867 /* Channel estimation fine tune */
2868 { 0x1f, 0x0001 },
2869 { 0x0b, 0x6c20 },
2870 { 0x07, 0x2872 },
2871 { 0x1c, 0xefff },
2872 { 0x1f, 0x0003 },
2873 { 0x14, 0x6420 },
2874 { 0x1f, 0x0000 },
2875
2876 /* Update PFM & 10M TX idle timer */
2877 { 0x1f, 0x0007 },
2878 { 0x1e, 0x002f },
2879 { 0x15, 0x1919 },
2880 { 0x1f, 0x0000 },
2881
2882 { 0x1f, 0x0007 },
2883 { 0x1e, 0x00ac },
2884 { 0x18, 0x0006 },
2885 { 0x1f, 0x0000 }
2886 };
2887
15ecd039
FR		 2888 rtl_apply_firmware(tp);
2889
01dc7fec 2890 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2891
2892 /* DCO enable for 10M IDLE Power */
2893 rtl_writephy(tp, 0x1f, 0x0007);
2894 rtl_writephy(tp, 0x1e, 0x0023);
2895 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2896 rtl_writephy(tp, 0x1f, 0x0000);
2897
2898 /* For impedance matching */
2899 rtl_writephy(tp, 0x1f, 0x0002);
2900 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2901 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2902
2903 /* PHY auto speed down */
2904 rtl_writephy(tp, 0x1f, 0x0007);
2905 rtl_writephy(tp, 0x1e, 0x002d);
2906 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2907 rtl_writephy(tp, 0x1f, 0x0000);
2908 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2909
2910 rtl_writephy(tp, 0x1f, 0x0005);
2911 rtl_writephy(tp, 0x05, 0x8b86);
2912 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2913 rtl_writephy(tp, 0x1f, 0x0000);
2914
2915 rtl_writephy(tp, 0x1f, 0x0005);
2916 rtl_writephy(tp, 0x05, 0x8b85);
2917 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2918 rtl_writephy(tp, 0x1f, 0x0007);
2919 rtl_writephy(tp, 0x1e, 0x0020);
2920 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2921 rtl_writephy(tp, 0x1f, 0x0006);
2922 rtl_writephy(tp, 0x00, 0x5a00);
2923 rtl_writephy(tp, 0x1f, 0x0000);
2924 rtl_writephy(tp, 0x0d, 0x0007);
2925 rtl_writephy(tp, 0x0e, 0x003c);
2926 rtl_writephy(tp, 0x0d, 0x4007);
2927 rtl_writephy(tp, 0x0e, 0x0000);
2928 rtl_writephy(tp, 0x0d, 0x0000);
2929}
2930
70090424
HW		 2931static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2932{
2933 static const struct phy_reg phy_reg_init[] = {
2934 /* Enable Delay cap */
2935 { 0x1f, 0x0004 },
2936 { 0x1f, 0x0007 },
2937 { 0x1e, 0x00ac },
2938 { 0x18, 0x0006 },
2939 { 0x1f, 0x0002 },
2940 { 0x1f, 0x0000 },
2941 { 0x1f, 0x0000 },
2942
2943 /* Channel estimation fine tune */
2944 { 0x1f, 0x0003 },
2945 { 0x09, 0xa20f },
2946 { 0x1f, 0x0000 },
2947 { 0x1f, 0x0000 },
2948
2949 /* Green Setting */
2950 { 0x1f, 0x0005 },
2951 { 0x05, 0x8b5b },
2952 { 0x06, 0x9222 },
2953 { 0x05, 0x8b6d },
2954 { 0x06, 0x8000 },
2955 { 0x05, 0x8b76 },
2956 { 0x06, 0x8000 },
2957 { 0x1f, 0x0000 }
2958 };
2959
2960 rtl_apply_firmware(tp);
2961
2962 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2963
2964 /* For 4-corner performance improve */
2965 rtl_writephy(tp, 0x1f, 0x0005);
2966 rtl_writephy(tp, 0x05, 0x8b80);
2967 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2968 rtl_writephy(tp, 0x1f, 0x0000);
2969
2970 /* PHY auto speed down */
2971 rtl_writephy(tp, 0x1f, 0x0004);
2972 rtl_writephy(tp, 0x1f, 0x0007);
2973 rtl_writephy(tp, 0x1e, 0x002d);
2974 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2975 rtl_writephy(tp, 0x1f, 0x0002);
2976 rtl_writephy(tp, 0x1f, 0x0000);
2977 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2978
2979 /* improve 10M EEE waveform */
2980 rtl_writephy(tp, 0x1f, 0x0005);
2981 rtl_writephy(tp, 0x05, 0x8b86);
2982 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2983 rtl_writephy(tp, 0x1f, 0x0000);
2984
2985 /* Improve 2-pair detection performance */
2986 rtl_writephy(tp, 0x1f, 0x0005);
2987 rtl_writephy(tp, 0x05, 0x8b85);
2988 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2989 rtl_writephy(tp, 0x1f, 0x0000);
2990
2991 /* EEE setting */
2992 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2993 ERIAR_EXGMAC);
2994 rtl_writephy(tp, 0x1f, 0x0005);
2995 rtl_writephy(tp, 0x05, 0x8b85);
2996 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2997 rtl_writephy(tp, 0x1f, 0x0004);
2998 rtl_writephy(tp, 0x1f, 0x0007);
2999 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3000 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3001 rtl_writephy(tp, 0x1f, 0x0002);
3002 rtl_writephy(tp, 0x1f, 0x0000);
3003 rtl_writephy(tp, 0x0d, 0x0007);
3004 rtl_writephy(tp, 0x0e, 0x003c);
3005 rtl_writephy(tp, 0x0d, 0x4007);
3006 rtl_writephy(tp, 0x0e, 0x0000);
3007 rtl_writephy(tp, 0x0d, 0x0000);
3008
3009 /* Green feature */
3010 rtl_writephy(tp, 0x1f, 0x0003);
3011 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3012 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3013 rtl_writephy(tp, 0x1f, 0x0000);
3014}
3015
c2218925
HW		 3016static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3017{
3018 static const struct phy_reg phy_reg_init[] = {
3019 /* Channel estimation fine tune */
3020 { 0x1f, 0x0003 },
3021 { 0x09, 0xa20f },
3022 { 0x1f, 0x0000 },
3023
3024 /* Modify green table for giga & fnet */
3025 { 0x1f, 0x0005 },
3026 { 0x05, 0x8b55 },
3027 { 0x06, 0x0000 },
3028 { 0x05, 0x8b5e },
3029 { 0x06, 0x0000 },
3030 { 0x05, 0x8b67 },
3031 { 0x06, 0x0000 },
3032 { 0x05, 0x8b70 },
3033 { 0x06, 0x0000 },
3034 { 0x1f, 0x0000 },
3035 { 0x1f, 0x0007 },
3036 { 0x1e, 0x0078 },
3037 { 0x17, 0x0000 },
3038 { 0x19, 0x00fb },
3039 { 0x1f, 0x0000 },
3040
3041 /* Modify green table for 10M */
3042 { 0x1f, 0x0005 },
3043 { 0x05, 0x8b79 },
3044 { 0x06, 0xaa00 },
3045 { 0x1f, 0x0000 },
3046
3047 /* Disable hiimpedance detection (RTCT) */
3048 { 0x1f, 0x0003 },
3049 { 0x01, 0x328a },
3050 { 0x1f, 0x0000 }
3051 };
3052
3053 rtl_apply_firmware(tp);
3054
3055 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3056
3057 /* For 4-corner performance improve */
3058 rtl_writephy(tp, 0x1f, 0x0005);
3059 rtl_writephy(tp, 0x05, 0x8b80);
3060 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3061 rtl_writephy(tp, 0x1f, 0x0000);
3062
3063 /* PHY auto speed down */
3064 rtl_writephy(tp, 0x1f, 0x0007);
3065 rtl_writephy(tp, 0x1e, 0x002d);
3066 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3067 rtl_writephy(tp, 0x1f, 0x0000);
3068 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3069
3070 /* Improve 10M EEE waveform */
3071 rtl_writephy(tp, 0x1f, 0x0005);
3072 rtl_writephy(tp, 0x05, 0x8b86);
3073 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3074 rtl_writephy(tp, 0x1f, 0x0000);
3075
3076 /* Improve 2-pair detection performance */
3077 rtl_writephy(tp, 0x1f, 0x0005);
3078 rtl_writephy(tp, 0x05, 0x8b85);
3079 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3080 rtl_writephy(tp, 0x1f, 0x0000);
3081}
3082
3083static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3084{
3085 rtl_apply_firmware(tp);
3086
3087 /* For 4-corner performance improve */
3088 rtl_writephy(tp, 0x1f, 0x0005);
3089 rtl_writephy(tp, 0x05, 0x8b80);
3090 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3091 rtl_writephy(tp, 0x1f, 0x0000);
3092
3093 /* PHY auto speed down */
3094 rtl_writephy(tp, 0x1f, 0x0007);
3095 rtl_writephy(tp, 0x1e, 0x002d);
3096 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3097 rtl_writephy(tp, 0x1f, 0x0000);
3098 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3099
3100 /* Improve 10M EEE waveform */
3101 rtl_writephy(tp, 0x1f, 0x0005);
3102 rtl_writephy(tp, 0x05, 0x8b86);
3103 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3104 rtl_writephy(tp, 0x1f, 0x0000);
3105}
3106
4da19633 3107static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3108{
350f7596 3109 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3110 { 0x1f, 0x0003 },
3111 { 0x08, 0x441d },
3112 { 0x01, 0x9100 },
3113 { 0x1f, 0x0000 }
3114 };
3115
4da19633 3116 rtl_writephy(tp, 0x1f, 0x0000);
3117 rtl_patchphy(tp, 0x11, 1 << 12);
3118 rtl_patchphy(tp, 0x19, 1 << 13);
3119 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3120
4da19633 3121 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3122}
3123
5a5e4443
HW		 3124static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3125{
3126 static const struct phy_reg phy_reg_init[] = {
3127 { 0x1f, 0x0005 },
3128 { 0x1a, 0x0000 },
3129 { 0x1f, 0x0000 },
3130
3131 { 0x1f, 0x0004 },
3132 { 0x1c, 0x0000 },
3133 { 0x1f, 0x0000 },
3134
3135 { 0x1f, 0x0001 },
3136 { 0x15, 0x7701 },
3137 { 0x1f, 0x0000 }
3138 };
3139
3140 /* Disable ALDPS before ram code */
3141 rtl_writephy(tp, 0x1f, 0x0000);
3142 rtl_writephy(tp, 0x18, 0x0310);
3143 msleep(100);
3144
953a12cc 3145 rtl_apply_firmware(tp);
5a5e4443
HW		 3146
3147 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3148}
3149
5615d9f1
FR		 3150static void rtl_hw_phy_config(struct net_device *dev)
3151{
3152 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3153
3154 rtl8169_print_mac_version(tp);
3155
3156 switch (tp->mac_version) {
3157 case RTL_GIGA_MAC_VER_01:
3158 break;
3159 case RTL_GIGA_MAC_VER_02:
3160 case RTL_GIGA_MAC_VER_03:
4da19633 3161 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3162 break;
3163 case RTL_GIGA_MAC_VER_04:
4da19633 3164 rtl8169sb_hw_phy_config(tp);
5615d9f1 3165 break;
2e955856 3166 case RTL_GIGA_MAC_VER_05:
4da19633 3167 rtl8169scd_hw_phy_config(tp);
2e955856 3168 break;
8c7006aa 3169 case RTL_GIGA_MAC_VER_06:
4da19633 3170 rtl8169sce_hw_phy_config(tp);
8c7006aa 3171 break;
2857ffb7
FR		 3172 case RTL_GIGA_MAC_VER_07:
3173 case RTL_GIGA_MAC_VER_08:
3174 case RTL_GIGA_MAC_VER_09:
4da19633 3175 rtl8102e_hw_phy_config(tp);
2857ffb7 3176 break;
236b8082 3177 case RTL_GIGA_MAC_VER_11:
4da19633 3178 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3179 break;
3180 case RTL_GIGA_MAC_VER_12:
4da19633 3181 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3182 break;
3183 case RTL_GIGA_MAC_VER_17:
4da19633 3184 rtl8168bef_hw_phy_config(tp);
236b8082 3185 break;
867763c1 3186 case RTL_GIGA_MAC_VER_18:
4da19633 3187 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3188 break;
3189 case RTL_GIGA_MAC_VER_19:
4da19633 3190 rtl8168c_1_hw_phy_config(tp);
867763c1 3191 break;
7da97ec9 3192 case RTL_GIGA_MAC_VER_20:
4da19633 3193 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3194 break;
197ff761 3195 case RTL_GIGA_MAC_VER_21:
4da19633 3196 rtl8168c_3_hw_phy_config(tp);
197ff761 3197 break;
6fb07058 3198 case RTL_GIGA_MAC_VER_22:
4da19633 3199 rtl8168c_4_hw_phy_config(tp);
6fb07058 3200 break;
ef3386f0 3201 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3202 case RTL_GIGA_MAC_VER_24:
4da19633 3203 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3204 break;
5b538df9 3205 case RTL_GIGA_MAC_VER_25:
bca03d5f 3206 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3207 break;
3208 case RTL_GIGA_MAC_VER_26:
bca03d5f 3209 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3210 break;
3211 case RTL_GIGA_MAC_VER_27:
4da19633 3212 rtl8168d_3_hw_phy_config(tp);
5b538df9 3213 break;
e6de30d6 3214 case RTL_GIGA_MAC_VER_28:
3215 rtl8168d_4_hw_phy_config(tp);
3216 break;
5a5e4443
HW		 3217 case RTL_GIGA_MAC_VER_29:
3218 case RTL_GIGA_MAC_VER_30:
3219 rtl8105e_hw_phy_config(tp);
3220 break;
cecb5fd7
FR		 3221 case RTL_GIGA_MAC_VER_31:
3222 /* None. */
3223 break;
01dc7fec 3224 case RTL_GIGA_MAC_VER_32:
01dc7fec 3225 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3226 rtl8168e_1_hw_phy_config(tp);
3227 break;
3228 case RTL_GIGA_MAC_VER_34:
3229 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3230 break;
c2218925
HW		 3231 case RTL_GIGA_MAC_VER_35:
3232 rtl8168f_1_hw_phy_config(tp);
3233 break;
3234 case RTL_GIGA_MAC_VER_36:
3235 rtl8168f_2_hw_phy_config(tp);
3236 break;
ef3386f0 3237
5615d9f1
FR		 3238 default:
3239 break;
3240 }
3241}
3242
da78dbff 3243static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3244{
1da177e4
LT		 3245 struct timer_list *timer = &tp->timer;
3246 void __iomem *ioaddr = tp->mmio_addr;
3247 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3248
bcf0bf90 3249 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3250
4da19633 3251 if (tp->phy_reset_pending(tp)) {
5b0384f4 3252 /*
1da177e4
LT		 3253 * A busy loop could burn quite a few cycles on nowadays CPU.
3254 * Let's delay the execution of the timer for a few ticks.
3255 */
3256 timeout = HZ/10;
3257 goto out_mod_timer;
3258 }
3259
3260 if (tp->link_ok(ioaddr))
da78dbff 3261 return;
1da177e4 3262
da78dbff 3263 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3264
4da19633 3265 tp->phy_reset_enable(tp);
1da177e4
LT		 3266
3267out_mod_timer:
3268 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3269}
3270
3271static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3272{
da78dbff
FR		 3273 if (!test_and_set_bit(flag, tp->wk.flags))
3274 schedule_work(&tp->wk.work);
da78dbff
FR		 3275}
3276
3277static void rtl8169_phy_timer(unsigned long __opaque)
3278{
3279 struct net_device *dev = (struct net_device *)__opaque;
3280 struct rtl8169_private *tp = netdev_priv(dev);
3281
98ddf986 3282 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3283}
3284
1da177e4 3285#ifdef CONFIG_NET_POLL_CONTROLLER
1da177e4
LT		 3286static void rtl8169_netpoll(struct net_device *dev)
3287{
3288 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3289
da78dbff 3290 rtl8169_interrupt(tp->pci_dev->irq, dev);
1da177e4
LT		 3291}
3292#endif
3293
3294static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3295 void __iomem *ioaddr)
3296{
3297 iounmap(ioaddr);
3298 pci_release_regions(pdev);
87aeec76 3299 pci_clear_mwi(pdev);
1da177e4
LT		 3300 pci_disable_device(pdev);
3301 free_netdev(dev);
3302}
3303
bf793295
FR		 3304static void rtl8169_phy_reset(struct net_device *dev,
3305 struct rtl8169_private *tp)
3306{
07d3f51f 3307 unsigned int i;
bf793295 3308
4da19633 3309 tp->phy_reset_enable(tp);
bf793295 3310 for (i = 0; i < 100; i++) {
4da19633 3311 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3312 return;
3313 msleep(1);
3314 }
bf82c189 3315 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3316}
3317
2544bfc0
FR		 3318static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3319{
3320 void __iomem *ioaddr = tp->mmio_addr;
3321
3322 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3323 (RTL_R8(PHYstatus) & TBI_Enable);
3324}
3325
4ff96fa6
FR		 3326static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3327{
3328 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3329
5615d9f1 3330 rtl_hw_phy_config(dev);
4ff96fa6 3331
77332894
MS		 3332 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3333 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3334 RTL_W8(0x82, 0x01);
3335 }
4ff96fa6 3336
6dccd16b
FR		 3337 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3338
3339 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3340 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3341
bcf0bf90 3342 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3343 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3344 RTL_W8(0x82, 0x01);
3345 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3346 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3347 }
3348
bf793295
FR		 3349 rtl8169_phy_reset(dev, tp);
3350
54405cde 3351 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3352 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3353 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3354 (tp->mii.supports_gmii ?
3355 ADVERTISED_1000baseT_Half |
3356 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3357
2544bfc0 3358 if (rtl_tbi_enabled(tp))
bf82c189 3359 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3360}
3361
773d2021
FR		 3362static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3363{
3364 void __iomem *ioaddr = tp->mmio_addr;
3365 u32 high;
3366 u32 low;
3367
3368 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3369 high = addr[4] | (addr[5] << 8);
3370
da78dbff 3371 rtl_lock_work(tp);
773d2021
FR		 3372
3373 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3374
773d2021 3375 RTL_W32(MAC4, high);
908ba2bf 3376 RTL_R32(MAC4);
3377
78f1cd02 3378 RTL_W32(MAC0, low);
908ba2bf 3379 RTL_R32(MAC0);
3380
c28aa385 3381 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3382 const struct exgmac_reg e[] = {
3383 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3384 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3385 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3386 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3387 low >> 16 },
3388 };
3389
3390 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3391 }
3392
773d2021
FR		 3393 RTL_W8(Cfg9346, Cfg9346_Lock);
3394
da78dbff 3395 rtl_unlock_work(tp);
773d2021
FR		 3396}
3397
3398static int rtl_set_mac_address(struct net_device *dev, void *p)
3399{
3400 struct rtl8169_private *tp = netdev_priv(dev);
3401 struct sockaddr *addr = p;
3402
3403 if (!is_valid_ether_addr(addr->sa_data))
3404 return -EADDRNOTAVAIL;
3405
3406 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3407
3408 rtl_rar_set(tp, dev->dev_addr);
3409
3410 return 0;
3411}
3412
5f787a1a
FR		 3413static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3414{
3415 struct rtl8169_private *tp = netdev_priv(dev);
3416 struct mii_ioctl_data *data = if_mii(ifr);
3417
8b4ab28d
FR		 3418 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3419}
5f787a1a 3420
cecb5fd7
FR		 3421static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3422 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3423{
5f787a1a
FR		 3424 switch (cmd) {
3425 case SIOCGMIIPHY:
3426 data->phy_id = 32; /* Internal PHY */
3427 return 0;
3428
3429 case SIOCGMIIREG:
4da19633 3430 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3431 return 0;
3432
3433 case SIOCSMIIREG:
4da19633 3434 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3435 return 0;
3436 }
3437 return -EOPNOTSUPP;
3438}
3439
8b4ab28d
FR		 3440static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3441{
3442 return -EOPNOTSUPP;
3443}
3444
0e485150
FR		 3445static const struct rtl_cfg_info {
3446 void (*hw_start)(struct net_device *);
3447 unsigned int region;
3448 unsigned int align;
da78dbff 3449 u16 event_slow;
ccdffb9a 3450 unsigned features;
f21b75e9 3451 u8 default_ver;
0e485150
FR		 3452} rtl_cfg_infos [] = {
3453 [RTL_CFG_0] = {
3454 .hw_start = rtl_hw_start_8169,
3455 .region = 1,
e9f63f30 3456 .align = 0,
da78dbff 3457 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
f21b75e9
JD		 3458 .features = RTL_FEATURE_GMII,
3459 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3460 },
3461 [RTL_CFG_1] = {
3462 .hw_start = rtl_hw_start_8168,
3463 .region = 2,
3464 .align = 8,
da78dbff 3465 .event_slow = SYSErr | LinkChg | RxOverflow,
f21b75e9
JD		 3466 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3467 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3468 },
3469 [RTL_CFG_2] = {
3470 .hw_start = rtl_hw_start_8101,
3471 .region = 2,
3472 .align = 8,
da78dbff
FR		 3473 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
3474 PCSTimeout,
f21b75e9
JD		 3475 .features = RTL_FEATURE_MSI,
3476 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3477 }
3478};
3479
fbac58fc 3480/* Cfg9346_Unlock assumed. */
2ca6cf06 3481static unsigned rtl_try_msi(struct rtl8169_private *tp,
fbac58fc
FR		 3482 const struct rtl_cfg_info *cfg)
3483{
2ca6cf06 3484 void __iomem *ioaddr = tp->mmio_addr;
fbac58fc
FR		 3485 unsigned msi = 0;
3486 u8 cfg2;
3487
3488 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3489 if (cfg->features & RTL_FEATURE_MSI) {
2ca6cf06 3490 if (pci_enable_msi(tp->pci_dev)) {
3491 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
fbac58fc
FR		 3492 } else {
3493 cfg2 |= MSIEnable;
3494 msi = RTL_FEATURE_MSI;
3495 }
3496 }
2ca6cf06 3497 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3498 RTL_W8(Config2, cfg2);
fbac58fc
FR		 3499 return msi;
3500}
3501
3502static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3503{
3504 if (tp->features & RTL_FEATURE_MSI) {
3505 pci_disable_msi(pdev);
3506 tp->features &= ~RTL_FEATURE_MSI;
3507 }
3508}
3509
8b4ab28d
FR		 3510static const struct net_device_ops rtl8169_netdev_ops = {
3511 .ndo_open = rtl8169_open,
3512 .ndo_stop = rtl8169_close,
3513 .ndo_get_stats = rtl8169_get_stats,
00829823 3514 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3515 .ndo_tx_timeout = rtl8169_tx_timeout,
3516 .ndo_validate_addr = eth_validate_addr,
3517 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3518 .ndo_fix_features = rtl8169_fix_features,
3519 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3520 .ndo_set_mac_address = rtl_set_mac_address,
3521 .ndo_do_ioctl = rtl8169_ioctl,
afc4b13d 3522 .ndo_set_rx_mode = rtl_set_rx_mode,
8b4ab28d
FR		 3523#ifdef CONFIG_NET_POLL_CONTROLLER
3524 .ndo_poll_controller = rtl8169_netpoll,
3525#endif
3526
3527};
3528
c0e45c1c 3529static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3530{
3531 struct mdio_ops *ops = &tp->mdio_ops;
3532
3533 switch (tp->mac_version) {
3534 case RTL_GIGA_MAC_VER_27:
3535 ops->write = r8168dp_1_mdio_write;
3536 ops->read = r8168dp_1_mdio_read;
3537 break;
e6de30d6 3538 case RTL_GIGA_MAC_VER_28:
4804b3b3 3539 case RTL_GIGA_MAC_VER_31:
e6de30d6 3540 ops->write = r8168dp_2_mdio_write;
3541 ops->read = r8168dp_2_mdio_read;
3542 break;
c0e45c1c 3543 default:
3544 ops->write = r8169_mdio_write;
3545 ops->read = r8169_mdio_read;
3546 break;
3547 }
3548}
3549
649b3b8c 3550static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3551{
3552 void __iomem *ioaddr = tp->mmio_addr;
3553
3554 switch (tp->mac_version) {
3555 case RTL_GIGA_MAC_VER_29:
3556 case RTL_GIGA_MAC_VER_30:
3557 case RTL_GIGA_MAC_VER_32:
3558 case RTL_GIGA_MAC_VER_33:
3559 case RTL_GIGA_MAC_VER_34:
3560 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3561 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3562 break;
3563 default:
3564 break;
3565 }
3566}
3567
3568static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3569{
3570 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3571 return false;
3572
3573 rtl_writephy(tp, 0x1f, 0x0000);
3574 rtl_writephy(tp, MII_BMCR, 0x0000);
3575
3576 rtl_wol_suspend_quirk(tp);
3577
3578 return true;
3579}
3580
065c27c1 3581static void r810x_phy_power_down(struct rtl8169_private *tp)
3582{
3583 rtl_writephy(tp, 0x1f, 0x0000);
3584 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3585}
3586
3587static void r810x_phy_power_up(struct rtl8169_private *tp)
3588{
3589 rtl_writephy(tp, 0x1f, 0x0000);
3590 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3591}
3592
3593static void r810x_pll_power_down(struct rtl8169_private *tp)
3594{
649b3b8c 3595 if (rtl_wol_pll_power_down(tp))
065c27c1 3596 return;
065c27c1 3597
3598 r810x_phy_power_down(tp);
3599}
3600
3601static void r810x_pll_power_up(struct rtl8169_private *tp)
3602{
3603 r810x_phy_power_up(tp);
3604}
3605
3606static void r8168_phy_power_up(struct rtl8169_private *tp)
3607{
3608 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3609 switch (tp->mac_version) {
3610 case RTL_GIGA_MAC_VER_11:
3611 case RTL_GIGA_MAC_VER_12:
3612 case RTL_GIGA_MAC_VER_17:
3613 case RTL_GIGA_MAC_VER_18:
3614 case RTL_GIGA_MAC_VER_19:
3615 case RTL_GIGA_MAC_VER_20:
3616 case RTL_GIGA_MAC_VER_21:
3617 case RTL_GIGA_MAC_VER_22:
3618 case RTL_GIGA_MAC_VER_23:
3619 case RTL_GIGA_MAC_VER_24:
3620 case RTL_GIGA_MAC_VER_25:
3621 case RTL_GIGA_MAC_VER_26:
3622 case RTL_GIGA_MAC_VER_27:
3623 case RTL_GIGA_MAC_VER_28:
3624 case RTL_GIGA_MAC_VER_31:
3625 rtl_writephy(tp, 0x0e, 0x0000);
3626 break;
3627 default:
3628 break;
3629 }
065c27c1 3630 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3631}
3632
3633static void r8168_phy_power_down(struct rtl8169_private *tp)
3634{
3635 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3636 switch (tp->mac_version) {
3637 case RTL_GIGA_MAC_VER_32:
3638 case RTL_GIGA_MAC_VER_33:
3639 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3640 break;
3641
3642 case RTL_GIGA_MAC_VER_11:
3643 case RTL_GIGA_MAC_VER_12:
3644 case RTL_GIGA_MAC_VER_17:
3645 case RTL_GIGA_MAC_VER_18:
3646 case RTL_GIGA_MAC_VER_19:
3647 case RTL_GIGA_MAC_VER_20:
3648 case RTL_GIGA_MAC_VER_21:
3649 case RTL_GIGA_MAC_VER_22:
3650 case RTL_GIGA_MAC_VER_23:
3651 case RTL_GIGA_MAC_VER_24:
3652 case RTL_GIGA_MAC_VER_25:
3653 case RTL_GIGA_MAC_VER_26:
3654 case RTL_GIGA_MAC_VER_27:
3655 case RTL_GIGA_MAC_VER_28:
3656 case RTL_GIGA_MAC_VER_31:
3657 rtl_writephy(tp, 0x0e, 0x0200);
3658 default:
3659 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3660 break;
3661 }
065c27c1 3662}
3663
3664static void r8168_pll_power_down(struct rtl8169_private *tp)
3665{
3666 void __iomem *ioaddr = tp->mmio_addr;
3667
cecb5fd7
FR		 3668 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3669 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3670 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3671 r8168dp_check_dash(tp)) {
065c27c1 3672 return;
5d2e1957 3673 }
065c27c1 3674
cecb5fd7
FR		 3675 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3676 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3677 (RTL_R16(CPlusCmd) & ASF)) {
3678 return;
3679 }
3680
01dc7fec 3681 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3682 tp->mac_version == RTL_GIGA_MAC_VER_33)
3683 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3684
649b3b8c 3685 if (rtl_wol_pll_power_down(tp))
065c27c1 3686 return;
065c27c1 3687
3688 r8168_phy_power_down(tp);
3689
3690 switch (tp->mac_version) {
3691 case RTL_GIGA_MAC_VER_25:
3692 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3693 case RTL_GIGA_MAC_VER_27:
3694 case RTL_GIGA_MAC_VER_28:
4804b3b3 3695 case RTL_GIGA_MAC_VER_31:
01dc7fec 3696 case RTL_GIGA_MAC_VER_32:
3697 case RTL_GIGA_MAC_VER_33:
065c27c1 3698 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3699 break;
3700 }
3701}
3702
3703static void r8168_pll_power_up(struct rtl8169_private *tp)
3704{
3705 void __iomem *ioaddr = tp->mmio_addr;
3706
cecb5fd7
FR		 3707 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3708 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3709 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3710 r8168dp_check_dash(tp)) {
065c27c1 3711 return;
5d2e1957 3712 }
065c27c1 3713
3714 switch (tp->mac_version) {
3715 case RTL_GIGA_MAC_VER_25:
3716 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3717 case RTL_GIGA_MAC_VER_27:
3718 case RTL_GIGA_MAC_VER_28:
4804b3b3 3719 case RTL_GIGA_MAC_VER_31:
01dc7fec 3720 case RTL_GIGA_MAC_VER_32:
3721 case RTL_GIGA_MAC_VER_33:
065c27c1 3722 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3723 break;
3724 }
3725
3726 r8168_phy_power_up(tp);
3727}
3728
d58d46b5
FR		 3729static void rtl_generic_op(struct rtl8169_private *tp,
3730 void (*op)(struct rtl8169_private *))
065c27c1 3731{
3732 if (op)
3733 op(tp);
3734}
3735
3736static void rtl_pll_power_down(struct rtl8169_private *tp)
3737{
d58d46b5 3738 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 3739}
3740
3741static void rtl_pll_power_up(struct rtl8169_private *tp)
3742{
d58d46b5 3743 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 3744}
3745
3746static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3747{
3748 struct pll_power_ops *ops = &tp->pll_power_ops;
3749
3750 switch (tp->mac_version) {
3751 case RTL_GIGA_MAC_VER_07:
3752 case RTL_GIGA_MAC_VER_08:
3753 case RTL_GIGA_MAC_VER_09:
3754 case RTL_GIGA_MAC_VER_10:
3755 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3756 case RTL_GIGA_MAC_VER_29:
3757 case RTL_GIGA_MAC_VER_30:
065c27c1 3758 ops->down = r810x_pll_power_down;
3759 ops->up = r810x_pll_power_up;
3760 break;
3761
3762 case RTL_GIGA_MAC_VER_11:
3763 case RTL_GIGA_MAC_VER_12:
3764 case RTL_GIGA_MAC_VER_17:
3765 case RTL_GIGA_MAC_VER_18:
3766 case RTL_GIGA_MAC_VER_19:
3767 case RTL_GIGA_MAC_VER_20:
3768 case RTL_GIGA_MAC_VER_21:
3769 case RTL_GIGA_MAC_VER_22:
3770 case RTL_GIGA_MAC_VER_23:
3771 case RTL_GIGA_MAC_VER_24:
3772 case RTL_GIGA_MAC_VER_25:
3773 case RTL_GIGA_MAC_VER_26:
3774 case RTL_GIGA_MAC_VER_27:
e6de30d6 3775 case RTL_GIGA_MAC_VER_28:
4804b3b3 3776 case RTL_GIGA_MAC_VER_31:
01dc7fec 3777 case RTL_GIGA_MAC_VER_32:
3778 case RTL_GIGA_MAC_VER_33:
70090424 3779 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 3780 case RTL_GIGA_MAC_VER_35:
3781 case RTL_GIGA_MAC_VER_36:
065c27c1 3782 ops->down = r8168_pll_power_down;
3783 ops->up = r8168_pll_power_up;
3784 break;
3785
3786 default:
3787 ops->down = NULL;
3788 ops->up = NULL;
3789 break;
3790 }
3791}
3792
e542a226
HW		 3793static void rtl_init_rxcfg(struct rtl8169_private *tp)
3794{
3795 void __iomem *ioaddr = tp->mmio_addr;
3796
3797 switch (tp->mac_version) {
3798 case RTL_GIGA_MAC_VER_01:
3799 case RTL_GIGA_MAC_VER_02:
3800 case RTL_GIGA_MAC_VER_03:
3801 case RTL_GIGA_MAC_VER_04:
3802 case RTL_GIGA_MAC_VER_05:
3803 case RTL_GIGA_MAC_VER_06:
3804 case RTL_GIGA_MAC_VER_10:
3805 case RTL_GIGA_MAC_VER_11:
3806 case RTL_GIGA_MAC_VER_12:
3807 case RTL_GIGA_MAC_VER_13:
3808 case RTL_GIGA_MAC_VER_14:
3809 case RTL_GIGA_MAC_VER_15:
3810 case RTL_GIGA_MAC_VER_16:
3811 case RTL_GIGA_MAC_VER_17:
3812 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3813 break;
3814 case RTL_GIGA_MAC_VER_18:
3815 case RTL_GIGA_MAC_VER_19:
3816 case RTL_GIGA_MAC_VER_20:
3817 case RTL_GIGA_MAC_VER_21:
3818 case RTL_GIGA_MAC_VER_22:
3819 case RTL_GIGA_MAC_VER_23:
3820 case RTL_GIGA_MAC_VER_24:
3821 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3822 break;
3823 default:
3824 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3825 break;
3826 }
3827}
3828
92fc43b4
HW		 3829static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3830{
3831 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3832}
3833
d58d46b5
FR		 3834static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3835{
3836 rtl_generic_op(tp, tp->jumbo_ops.enable);
3837}
3838
3839static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3840{
3841 rtl_generic_op(tp, tp->jumbo_ops.disable);
3842}
3843
3844static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3845{
3846 void __iomem *ioaddr = tp->mmio_addr;
3847
3848 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3849 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3850 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3851}
3852
3853static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3854{
3855 void __iomem *ioaddr = tp->mmio_addr;
3856
3857 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3858 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3859 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3860}
3861
3862static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3863{
3864 void __iomem *ioaddr = tp->mmio_addr;
3865
3866 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3867}
3868
3869static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3870{
3871 void __iomem *ioaddr = tp->mmio_addr;
3872
3873 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3874}
3875
3876static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3877{
3878 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3879
3880 RTL_W8(MaxTxPacketSize, 0x3f);
3881 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3882 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 3883 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3884}
3885
3886static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3887{
3888 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3889
3890 RTL_W8(MaxTxPacketSize, 0x0c);
3891 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3892 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 3893 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3894}
3895
3896static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3897{
3898 rtl_tx_performance_tweak(tp->pci_dev,
3899 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3900}
3901
3902static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3903{
3904 rtl_tx_performance_tweak(tp->pci_dev,
3905 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3906}
3907
3908static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3909{
3910 void __iomem *ioaddr = tp->mmio_addr;
3911
3912 r8168b_0_hw_jumbo_enable(tp);
3913
3914 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3915}
3916
3917static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3918{
3919 void __iomem *ioaddr = tp->mmio_addr;
3920
3921 r8168b_0_hw_jumbo_disable(tp);
3922
3923 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3924}
3925
3926static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3927{
3928 struct jumbo_ops *ops = &tp->jumbo_ops;
3929
3930 switch (tp->mac_version) {
3931 case RTL_GIGA_MAC_VER_11:
3932 ops->disable = r8168b_0_hw_jumbo_disable;
3933 ops->enable = r8168b_0_hw_jumbo_enable;
3934 break;
3935 case RTL_GIGA_MAC_VER_12:
3936 case RTL_GIGA_MAC_VER_17:
3937 ops->disable = r8168b_1_hw_jumbo_disable;
3938 ops->enable = r8168b_1_hw_jumbo_enable;
3939 break;
3940 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3941 case RTL_GIGA_MAC_VER_19:
3942 case RTL_GIGA_MAC_VER_20:
3943 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3944 case RTL_GIGA_MAC_VER_22:
3945 case RTL_GIGA_MAC_VER_23:
3946 case RTL_GIGA_MAC_VER_24:
3947 case RTL_GIGA_MAC_VER_25:
3948 case RTL_GIGA_MAC_VER_26:
3949 ops->disable = r8168c_hw_jumbo_disable;
3950 ops->enable = r8168c_hw_jumbo_enable;
3951 break;
3952 case RTL_GIGA_MAC_VER_27:
3953 case RTL_GIGA_MAC_VER_28:
3954 ops->disable = r8168dp_hw_jumbo_disable;
3955 ops->enable = r8168dp_hw_jumbo_enable;
3956 break;
3957 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3958 case RTL_GIGA_MAC_VER_32:
3959 case RTL_GIGA_MAC_VER_33:
3960 case RTL_GIGA_MAC_VER_34:
3961 ops->disable = r8168e_hw_jumbo_disable;
3962 ops->enable = r8168e_hw_jumbo_enable;
3963 break;
3964
3965 /*
3966 * No action needed for jumbo frames with 8169.
3967 * No jumbo for 810x at all.
3968 */
3969 default:
3970 ops->disable = NULL;
3971 ops->enable = NULL;
3972 break;
3973 }
3974}
3975
6f43adc8
FR		 3976static void rtl_hw_reset(struct rtl8169_private *tp)
3977{
3978 void __iomem *ioaddr = tp->mmio_addr;
3979 int i;
3980
3981 /* Soft reset the chip. */
3982 RTL_W8(ChipCmd, CmdReset);
3983
3984 /* Check that the chip has finished the reset. */
3985 for (i = 0; i < 100; i++) {
3986 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3987 break;
92fc43b4 3988 udelay(100);
6f43adc8
FR		 3989 }
3990}
3991
1da177e4 3992static int __devinit
4ff96fa6 3993rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3994{
0e485150
FR		 3995 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3996 const unsigned int region = cfg->region;
1da177e4 3997 struct rtl8169_private *tp;
ccdffb9a 3998 struct mii_if_info *mii;
4ff96fa6
FR		 3999 struct net_device *dev;
4000 void __iomem *ioaddr;
2b7b4318 4001 int chipset, i;
07d3f51f 4002 int rc;
1da177e4 4003
4ff96fa6
FR		 4004 if (netif_msg_drv(&debug)) {
4005 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
4006 MODULENAME, RTL8169_VERSION);
4007 }
1da177e4 4008
1da177e4 4009 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 4010 if (!dev) {
4ff96fa6
FR		 4011 rc = -ENOMEM;
4012 goto out;
1da177e4
LT		 4013 }
4014
1da177e4 4015 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 4016 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 4017 tp = netdev_priv(dev);
c4028958 4018 tp->dev = dev;
21e197f2 4019 tp->pci_dev = pdev;
b57b7e5a 4020 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 4021
ccdffb9a
FR		 4022 mii = &tp->mii;
4023 mii->dev = dev;
4024 mii->mdio_read = rtl_mdio_read;
4025 mii->mdio_write = rtl_mdio_write;
4026 mii->phy_id_mask = 0x1f;
4027 mii->reg_num_mask = 0x1f;
4028 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
4029
ba04c7c9
SG		 4030 /* disable ASPM completely as that cause random device stop working
4031 * problems as well as full system hangs for some PCIe devices users */
4032 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4033 PCIE_LINK_STATE_CLKPM);
4034
1da177e4
LT		 4035 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4036 rc = pci_enable_device(pdev);
b57b7e5a 4037 if (rc < 0) {
bf82c189 4038 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 4039 goto err_out_free_dev_1;
1da177e4
LT		 4040 }
4041
87aeec76 4042 if (pci_set_mwi(pdev) < 0)
4043 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 4044
1da177e4 4045 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 4046 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 4047 netif_err(tp, probe, dev,
4048 "region #%d not an MMIO resource, aborting\n",
4049 region);
1da177e4 4050 rc = -ENODEV;
87aeec76 4051 goto err_out_mwi_2;
1da177e4 4052 }
4ff96fa6 4053
1da177e4 4054 /* check for weird/broken PCI region reporting */
bcf0bf90 4055 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 4056 netif_err(tp, probe, dev,
4057 "Invalid PCI region size(s), aborting\n");
1da177e4 4058 rc = -ENODEV;
87aeec76 4059 goto err_out_mwi_2;
1da177e4
LT		 4060 }
4061
4062 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 4063 if (rc < 0) {
bf82c189 4064 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 4065 goto err_out_mwi_2;
1da177e4
LT		 4066 }
4067
d24e9aaf 4068 tp->cp_cmd = RxChkSum;
1da177e4
LT		 4069
4070 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 4071 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 4072 tp->cp_cmd |= PCIDAC;
4073 dev->features |= NETIF_F_HIGHDMA;
4074 } else {
284901a9 4075 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 4076 if (rc < 0) {
bf82c189 4077 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 4078 goto err_out_free_res_3;
1da177e4
LT		 4079 }
4080 }
4081
1da177e4 4082 /* ioremap MMIO region */
bcf0bf90 4083 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 4084 if (!ioaddr) {
bf82c189 4085 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 4086 rc = -EIO;
87aeec76 4087 goto err_out_free_res_3;
1da177e4 4088 }
6f43adc8 4089 tp->mmio_addr = ioaddr;
1da177e4 4090
e44daade
JM		 4091 if (!pci_is_pcie(pdev))
4092 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 4093
e542a226
HW		 4094 /* Identify chip attached to board */
4095 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4096
4097 rtl_init_rxcfg(tp);
4098
9085cdfa 4099 rtl_irq_disable(tp);
1da177e4 4100
6f43adc8 4101 rtl_hw_reset(tp);
1da177e4 4102
9085cdfa 4103 rtl_ack_events(tp, 0xffff);
d78ad8cb 4104
ca52efd5 4105 pci_set_master(pdev);
4106
7a8fc77b
FR		 4107 /*
4108 * Pretend we are using VLANs; This bypasses a nasty bug where
4109 * Interrupts stop flowing on high load on 8110SCd controllers.
4110 */
4111 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4112 tp->cp_cmd |= RxVlan;
4113
c0e45c1c 4114 rtl_init_mdio_ops(tp);
065c27c1 4115 rtl_init_pll_power_ops(tp);
d58d46b5 4116 rtl_init_jumbo_ops(tp);
c0e45c1c 4117
1da177e4 4118 rtl8169_print_mac_version(tp);
1da177e4 4119
85bffe6c
FR		 4120 chipset = tp->mac_version;
4121 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 4122
5d06a99f
FR		 4123 RTL_W8(Cfg9346, Cfg9346_Unlock);
4124 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4125 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 4126 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4127 tp->features |= RTL_FEATURE_WOL;
4128 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4129 tp->features |= RTL_FEATURE_WOL;
2ca6cf06 4130 tp->features |= rtl_try_msi(tp, cfg);
5d06a99f
FR		 4131 RTL_W8(Cfg9346, Cfg9346_Lock);
4132
2544bfc0 4133 if (rtl_tbi_enabled(tp)) {
1da177e4
LT		 4134 tp->set_speed = rtl8169_set_speed_tbi;
4135 tp->get_settings = rtl8169_gset_tbi;
4136 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4137 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4138 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 4139 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 4140 } else {
4141 tp->set_speed = rtl8169_set_speed_xmii;
4142 tp->get_settings = rtl8169_gset_xmii;
4143 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4144 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4145 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 4146 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 4147 }
4148
da78dbff 4149 mutex_init(&tp->wk.mutex);
df58ef51 4150
7bf6bf48 4151 /* Get MAC address */
6a3c910c 4152 for (i = 0; i < ETH_ALEN; i++)
1da177e4 4153 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 4154 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 4155
1da177e4 4156 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 4157 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4158 dev->irq = pdev->irq;
4159 dev->base_addr = (unsigned long) ioaddr;
1da177e4 4160
bea3348e 4161 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 4162
350fb32a
MM		 4163 /* don't enable SG, IP_CSUM and TSO by default - it might not work
4164 * properly for all devices */
4165 dev->features |= NETIF_F_RXCSUM |
4166 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4167
4168 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4169 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4170 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4171 NETIF_F_HIGHDMA;
4172
4173 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4174 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4175 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4 4176
0e485150 4177 tp->hw_start = cfg->hw_start;
da78dbff 4178 tp->event_slow = cfg->event_slow;
1da177e4 4179
e03f33af
FR		 4180 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4181 ~(RxBOVF | RxFOVF) : ~0;
4182
2efa53f3
FR		 4183 init_timer(&tp->timer);
4184 tp->timer.data = (unsigned long) dev;
4185 tp->timer.function = rtl8169_phy_timer;
4186
b6ffd97f 4187 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 4188
1da177e4 4189 rc = register_netdev(dev);
4ff96fa6 4190 if (rc < 0)
87aeec76 4191 goto err_out_msi_4;
1da177e4
LT		 4192
4193 pci_set_drvdata(pdev, dev);
4194
bf82c189 4195 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 4196 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 4197 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
d58d46b5
FR		 4198 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4199 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4200 "tx checksumming: %s]\n",
4201 rtl_chip_infos[chipset].jumbo_max,
4202 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4203 }
1da177e4 4204
cecb5fd7
FR		 4205 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4206 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4207 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 4208 rtl8168_driver_start(tp);
e6de30d6 4209 }
b646d900 4210
8b76ab39 4211 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 4212
f3ec4f87
AS		 4213 if (pci_dev_run_wake(pdev))
4214 pm_runtime_put_noidle(&pdev->dev);
e1759441 4215
0d672e9f
IV		 4216 netif_carrier_off(dev);
4217
4ff96fa6
FR		 4218out:
4219 return rc;
1da177e4 4220
87aeec76 4221err_out_msi_4:
fbac58fc 4222 rtl_disable_msi(pdev, tp);
4ff96fa6 4223 iounmap(ioaddr);
87aeec76 4224err_out_free_res_3:
4ff96fa6 4225 pci_release_regions(pdev);
87aeec76 4226err_out_mwi_2:
4ff96fa6 4227 pci_clear_mwi(pdev);
4ff96fa6
FR		 4228 pci_disable_device(pdev);
4229err_out_free_dev_1:
4230 free_netdev(dev);
4231 goto out;
1da177e4
LT		 4232}
4233
07d3f51f 4234static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 4235{
4236 struct net_device *dev = pci_get_drvdata(pdev);
4237 struct rtl8169_private *tp = netdev_priv(dev);
4238
cecb5fd7
FR		 4239 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4240 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4241 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 4242 rtl8168_driver_stop(tp);
e6de30d6 4243 }
b646d900 4244
4422bcd4 4245 cancel_work_sync(&tp->wk.work);
eb2a021c 4246
1da177e4 4247 unregister_netdev(dev);
cc098dc7 4248
953a12cc
FR		 4249 rtl_release_firmware(tp);
4250
f3ec4f87
AS		 4251 if (pci_dev_run_wake(pdev))
4252 pm_runtime_get_noresume(&pdev->dev);
e1759441 4253
cc098dc7
IV		 4254 /* restore original MAC address */
4255 rtl_rar_set(tp, dev->perm_addr);
4256
fbac58fc 4257 rtl_disable_msi(pdev, tp);
1da177e4
LT		 4258 rtl8169_release_board(pdev, dev, tp->mmio_addr);
4259 pci_set_drvdata(pdev, NULL);
4260}
4261
b6ffd97f 4262static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4263{
b6ffd97f
FR		 4264 struct rtl_fw *rtl_fw;
4265 const char *name;
4266 int rc = -ENOMEM;
953a12cc 4267
b6ffd97f
FR		 4268 name = rtl_lookup_firmware_name(tp);
4269 if (!name)
4270 goto out_no_firmware;
953a12cc 4271
b6ffd97f
FR		 4272 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4273 if (!rtl_fw)
4274 goto err_warn;
31bd204f 4275
b6ffd97f
FR		 4276 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4277 if (rc < 0)
4278 goto err_free;
4279
fd112f2e
FR		 4280 rc = rtl_check_firmware(tp, rtl_fw);
4281 if (rc < 0)
4282 goto err_release_firmware;
4283
b6ffd97f
FR		 4284 tp->rtl_fw = rtl_fw;
4285out:
4286 return;
4287
fd112f2e
FR		 4288err_release_firmware:
4289 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4290err_free:
4291 kfree(rtl_fw);
4292err_warn:
4293 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4294 name, rc);
4295out_no_firmware:
4296 tp->rtl_fw = NULL;
4297 goto out;
4298}
4299
4300static void rtl_request_firmware(struct rtl8169_private *tp)
4301{
4302 if (IS_ERR(tp->rtl_fw))
4303 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4304}
4305
4422bcd4
FR		 4306static void rtl_task(struct work_struct *);
4307
1da177e4
LT		 4308static int rtl8169_open(struct net_device *dev)
4309{
4310 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 4311 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4312 struct pci_dev *pdev = tp->pci_dev;
99f252b0 4313 int retval = -ENOMEM;
1da177e4 4314
e1759441 4315 pm_runtime_get_sync(&pdev->dev);
1da177e4 4316
1da177e4
LT		 4317 /*
4318 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 4319 * dma_alloc_coherent provides more.
1da177e4 4320 */
82553bb6
SG		 4321 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4322 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 4323 if (!tp->TxDescArray)
e1759441 4324 goto err_pm_runtime_put;
1da177e4 4325
82553bb6
SG		 4326 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4327 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 4328 if (!tp->RxDescArray)
99f252b0 4329 goto err_free_tx_0;
1da177e4
LT		 4330
4331 retval = rtl8169_init_ring(dev);
4332 if (retval < 0)
99f252b0 4333 goto err_free_rx_1;
1da177e4 4334
4422bcd4 4335 INIT_WORK(&tp->wk.work, rtl_task);
1da177e4 4336
99f252b0
FR		 4337 smp_mb();
4338
953a12cc
FR		 4339 rtl_request_firmware(tp);
4340
fbac58fc
FR		 4341 retval = request_irq(dev->irq, rtl8169_interrupt,
4342 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 4343 dev->name, dev);
4344 if (retval < 0)
953a12cc 4345 goto err_release_fw_2;
99f252b0 4346
da78dbff
FR		 4347 rtl_lock_work(tp);
4348
6c4a70c5 4349 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 4350
bea3348e 4351 napi_enable(&tp->napi);
bea3348e 4352
eee3a96c 4353 rtl8169_init_phy(dev, tp);
4354
da78dbff 4355 __rtl8169_set_features(dev, dev->features);
eee3a96c 4356
065c27c1 4357 rtl_pll_power_up(tp);
4358
07ce4064 4359 rtl_hw_start(dev);
1da177e4 4360
da78dbff
FR		 4361 netif_start_queue(dev);
4362
4363 rtl_unlock_work(tp);
4364
e1759441
RW		 4365 tp->saved_wolopts = 0;
4366 pm_runtime_put_noidle(&pdev->dev);
4367
eee3a96c 4368 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 4369out:
4370 return retval;
4371
953a12cc
FR		 4372err_release_fw_2:
4373 rtl_release_firmware(tp);
99f252b0
FR		 4374 rtl8169_rx_clear(tp);
4375err_free_rx_1:
82553bb6
SG		 4376 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4377 tp->RxPhyAddr);
e1759441 4378 tp->RxDescArray = NULL;
99f252b0 4379err_free_tx_0:
82553bb6
SG		 4380 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4381 tp->TxPhyAddr);
e1759441
RW		 4382 tp->TxDescArray = NULL;
4383err_pm_runtime_put:
4384 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 4385 goto out;
4386}
4387
92fc43b4
HW		 4388static void rtl_rx_close(struct rtl8169_private *tp)
4389{
4390 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4391
1687b566 4392 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4393}
4394
e6de30d6 4395static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4396{
e6de30d6 4397 void __iomem *ioaddr = tp->mmio_addr;
4398
1da177e4 4399 /* Disable interrupts */
811fd301 4400 rtl8169_irq_mask_and_ack(tp);
1da177e4 4401
92fc43b4
HW		 4402 rtl_rx_close(tp);
4403
5d2e1957 4404 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4405 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4406 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 4407 while (RTL_R8(TxPoll) & NPQ)
4408 udelay(20);
c2218925
HW		 4409 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4410 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4411 tp->mac_version == RTL_GIGA_MAC_VER_36) {
c2b0c1e7 4412 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
70090424
HW		 4413 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4414 udelay(100);
92fc43b4
HW		 4415 } else {
4416 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4417 udelay(100);
e6de30d6 4418 }
4419
92fc43b4 4420 rtl_hw_reset(tp);
1da177e4
LT		 4421}
4422
7f796d83 4423static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4424{
4425 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4426
4427 /* Set DMA burst size and Interframe Gap Time */
4428 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4429 (InterFrameGap << TxInterFrameGapShift));
4430}
4431
07ce4064 4432static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4433{
4434 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4435
07ce4064
FR		 4436 tp->hw_start(dev);
4437
da78dbff 4438 rtl_irq_enable_all(tp);
07ce4064
FR		 4439}
4440
7f796d83
FR		 4441static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4442 void __iomem *ioaddr)
4443{
4444 /*
4445 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4446 * register to be written before TxDescAddrLow to work.
4447 * Switching from MMIO to I/O access fixes the issue as well.
4448 */
4449 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4450 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4451 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4452 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4453}
4454
4455static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4456{
4457 u16 cmd;
4458
4459 cmd = RTL_R16(CPlusCmd);
4460 RTL_W16(CPlusCmd, cmd);
4461 return cmd;
4462}
4463
fdd7b4c3 4464static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4465{
4466 /* Low hurts. Let's disable the filtering. */
207d6e87 4467 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4468}
4469
6dccd16b
FR		 4470static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4471{
3744100e 4472 static const struct rtl_cfg2_info {
6dccd16b
FR		 4473 u32 mac_version;
4474 u32 clk;
4475 u32 val;
4476 } cfg2_info [] = {
4477 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4478 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4479 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4480 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4481 };
4482 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4483 unsigned int i;
4484 u32 clk;
4485
4486 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4487 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4488 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4489 RTL_W32(0x7c, p->val);
4490 break;
4491 }
4492 }
4493}
4494
07ce4064
FR		 4495static void rtl_hw_start_8169(struct net_device *dev)
4496{
4497 struct rtl8169_private *tp = netdev_priv(dev);
4498 void __iomem *ioaddr = tp->mmio_addr;
4499 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4500
9cb427b6
FR		 4501 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4502 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4503 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4504 }
4505
1da177e4 4506 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4507 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4508 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4509 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4510 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4511 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4512
e542a226
HW		 4513 rtl_init_rxcfg(tp);
4514
f0298f81 4515 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4516
6f0333b8 4517 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4518
cecb5fd7
FR		 4519 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4520 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4521 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4522 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4523 rtl_set_rx_tx_config_registers(tp);
1da177e4 4524
7f796d83 4525 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4526
cecb5fd7
FR		 4527 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4528 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4529 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4530 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4531 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4532 }
4533
bcf0bf90
FR		 4534 RTL_W16(CPlusCmd, tp->cp_cmd);
4535
6dccd16b
FR		 4536 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4537
1da177e4
LT		 4538 /*
4539 * Undocumented corner. Supposedly:
4540 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4541 */
4542 RTL_W16(IntrMitigate, 0x0000);
4543
7f796d83 4544 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4545
cecb5fd7
FR		 4546 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4547 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4548 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4549 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4550 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4551 rtl_set_rx_tx_config_registers(tp);
4552 }
4553
1da177e4 4554 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4555
4556 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4557 RTL_R8(IntrMask);
1da177e4
LT		 4558
4559 RTL_W32(RxMissed, 0);
4560
07ce4064 4561 rtl_set_rx_mode(dev);
1da177e4
LT		 4562
4563 /* no early-rx interrupts */
4564 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4565}
1da177e4 4566
650e8d5d 4567static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4568{
4569 u32 csi;
4570
4571 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4572 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4573}
4574
e6de30d6 4575static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4576{
4577 rtl_csi_access_enable(ioaddr, 0x17000000);
4578}
4579
650e8d5d 4580static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4581{
4582 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4583}
4584
4585struct ephy_info {
4586 unsigned int offset;
4587 u16 mask;
4588 u16 bits;
4589};
4590
350f7596 4591static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4592{
4593 u16 w;
4594
4595 while (len-- > 0) {
4596 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4597 rtl_ephy_write(ioaddr, e->offset, w);
4598 e++;
4599 }
4600}
4601
b726e493
FR		 4602static void rtl_disable_clock_request(struct pci_dev *pdev)
4603{
e44daade 4604 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4605
4606 if (cap) {
4607 u16 ctl;
4608
4609 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4610 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4611 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4612 }
4613}
4614
e6de30d6 4615static void rtl_enable_clock_request(struct pci_dev *pdev)
4616{
e44daade 4617 int cap = pci_pcie_cap(pdev);
e6de30d6 4618
4619 if (cap) {
4620 u16 ctl;
4621
4622 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4623 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4624 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4625 }
4626}
4627
b726e493
FR		 4628#define R8168_CPCMD_QUIRK_MASK (\
4629 EnableBist | \
4630 Mac_dbgo_oe | \
4631 Force_half_dup | \
4632 Force_rxflow_en | \
4633 Force_txflow_en | \
4634 Cxpl_dbg_sel | \
4635 ASF | \
4636 PktCntrDisable | \
4637 Mac_dbgo_sel)
4638
219a1e9d
FR		 4639static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4640{
b726e493
FR		 4641 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4642
4643 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4644
2e68ae44
FR		 4645 rtl_tx_performance_tweak(pdev,
4646 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4647}
4648
4649static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4650{
4651 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4652
f0298f81 4653 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4654
4655 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4656}
4657
4658static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4659{
b726e493
FR		 4660 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4661
4662 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4663
219a1e9d 4664 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4665
4666 rtl_disable_clock_request(pdev);
4667
4668 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4669}
4670
ef3386f0 4671static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4672{
350f7596 4673 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4674 { 0x01, 0, 0x0001 },
4675 { 0x02, 0x0800, 0x1000 },
4676 { 0x03, 0, 0x0042 },
4677 { 0x06, 0x0080, 0x0000 },
4678 { 0x07, 0, 0x2000 }
4679 };
4680
650e8d5d 4681 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4682
4683 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4684
219a1e9d
FR		 4685 __rtl_hw_start_8168cp(ioaddr, pdev);
4686}
4687
ef3386f0
FR		 4688static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4689{
650e8d5d 4690 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4691
4692 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4693
4694 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4695
4696 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4697}
4698
7f3e3d3a
FR		 4699static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4700{
650e8d5d 4701 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4702
4703 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4704
4705 /* Magic. */
4706 RTL_W8(DBG_REG, 0x20);
4707
f0298f81 4708 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4709
4710 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4711
4712 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4713}
4714
219a1e9d
FR		 4715static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4716{
350f7596 4717 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4718 { 0x02, 0x0800, 0x1000 },
4719 { 0x03, 0, 0x0002 },
4720 { 0x06, 0x0080, 0x0000 }
4721 };
4722
650e8d5d 4723 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4724
4725 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4726
4727 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4728
219a1e9d
FR		 4729 __rtl_hw_start_8168cp(ioaddr, pdev);
4730}
4731
4732static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4733{
350f7596 4734 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4735 { 0x01, 0, 0x0001 },
4736 { 0x03, 0x0400, 0x0220 }
4737 };
4738
650e8d5d 4739 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4740
4741 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4742
219a1e9d
FR		 4743 __rtl_hw_start_8168cp(ioaddr, pdev);
4744}
4745
197ff761
FR		 4746static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4747{
4748 rtl_hw_start_8168c_2(ioaddr, pdev);
4749}
4750
6fb07058
FR		 4751static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4752{
650e8d5d 4753 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4754
4755 __rtl_hw_start_8168cp(ioaddr, pdev);
4756}
4757
5b538df9
FR		 4758static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4759{
650e8d5d 4760 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4761
4762 rtl_disable_clock_request(pdev);
4763
f0298f81 4764 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4765
4766 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4767
4768 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4769}
4770
4804b3b3 4771static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4772{
4773 rtl_csi_access_enable_1(ioaddr);
4774
4775 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4776
4777 RTL_W8(MaxTxPacketSize, TxPacketMax);
4778
4779 rtl_disable_clock_request(pdev);
4780}
4781
e6de30d6 4782static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4783{
4784 static const struct ephy_info e_info_8168d_4[] = {
4785 { 0x0b, ~0, 0x48 },
4786 { 0x19, 0x20, 0x50 },
4787 { 0x0c, ~0, 0x20 }
4788 };
4789 int i;
4790
4791 rtl_csi_access_enable_1(ioaddr);
4792
4793 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4794
4795 RTL_W8(MaxTxPacketSize, TxPacketMax);
4796
4797 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4798 const struct ephy_info *e = e_info_8168d_4 + i;
4799 u16 w;
4800
4801 w = rtl_ephy_read(ioaddr, e->offset);
4802 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4803 }
4804
4805 rtl_enable_clock_request(pdev);
4806}
4807
70090424 4808static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4809{
70090424 4810 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4811 { 0x00, 0x0200, 0x0100 },
4812 { 0x00, 0x0000, 0x0004 },
4813 { 0x06, 0x0002, 0x0001 },
4814 { 0x06, 0x0000, 0x0030 },
4815 { 0x07, 0x0000, 0x2000 },
4816 { 0x00, 0x0000, 0x0020 },
4817 { 0x03, 0x5800, 0x2000 },
4818 { 0x03, 0x0000, 0x0001 },
4819 { 0x01, 0x0800, 0x1000 },
4820 { 0x07, 0x0000, 0x4000 },
4821 { 0x1e, 0x0000, 0x2000 },
4822 { 0x19, 0xffff, 0xfe6c },
4823 { 0x0a, 0x0000, 0x0040 }
4824 };
4825
4826 rtl_csi_access_enable_2(ioaddr);
4827
70090424 4828 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4829
4830 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4831
4832 RTL_W8(MaxTxPacketSize, TxPacketMax);
4833
4834 rtl_disable_clock_request(pdev);
4835
4836 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4837 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4838 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4839
cecb5fd7 4840 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4841}
4842
70090424
HW		 4843static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4844{
4845 static const struct ephy_info e_info_8168e_2[] = {
4846 { 0x09, 0x0000, 0x0080 },
4847 { 0x19, 0x0000, 0x0224 }
4848 };
4849
4850 rtl_csi_access_enable_1(ioaddr);
4851
4852 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4853
4854 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4855
4856 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4857 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4858 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4859 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4860 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4861 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4862 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4863 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4864 ERIAR_EXGMAC);
4865
3090bd9a 4866 RTL_W8(MaxTxPacketSize, EarlySize);
70090424
HW		 4867
4868 rtl_disable_clock_request(pdev);
4869
4870 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4871 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4872
4873 /* Adjust EEE LED frequency */
4874 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4875
4876 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4877 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4878 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4879}
4880
c2218925
HW		 4881static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4882{
4883 static const struct ephy_info e_info_8168f_1[] = {
4884 { 0x06, 0x00c0, 0x0020 },
4885 { 0x08, 0x0001, 0x0002 },
4886 { 0x09, 0x0000, 0x0080 },
4887 { 0x19, 0x0000, 0x0224 }
4888 };
4889
4890 rtl_csi_access_enable_1(ioaddr);
4891
4892 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4893
4894 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4895
4896 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4897 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4898 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4899 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4900 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4901 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4902 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4903 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4904 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4905 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4906 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4907 ERIAR_EXGMAC);
4908
4909 RTL_W8(MaxTxPacketSize, EarlySize);
4910
4911 rtl_disable_clock_request(pdev);
4912
4913 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4914 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4915
4916 /* Adjust EEE LED frequency */
4917 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4918
4919 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4920 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4921 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4922}
4923
07ce4064
FR		 4924static void rtl_hw_start_8168(struct net_device *dev)
4925{
2dd99530
FR		 4926 struct rtl8169_private *tp = netdev_priv(dev);
4927 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4928 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4929
4930 RTL_W8(Cfg9346, Cfg9346_Unlock);
4931
f0298f81 4932 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4933
6f0333b8 4934 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4935
0e485150 4936 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4937
4938 RTL_W16(CPlusCmd, tp->cp_cmd);
4939
0e485150 4940 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4941
0e485150 4942 /* Work around for RxFIFO overflow. */
811fd301 4943 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 4944 tp->event_slow |= RxFIFOOver | PCSTimeout;
4945 tp->event_slow &= ~RxOverflow;
0e485150
FR		 4946 }
4947
4948 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4949
b8363901
FR		 4950 rtl_set_rx_mode(dev);
4951
4952 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4953 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4954
4955 RTL_R8(IntrMask);
4956
219a1e9d
FR		 4957 switch (tp->mac_version) {
4958 case RTL_GIGA_MAC_VER_11:
4959 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4960 break;
219a1e9d
FR		 4961
4962 case RTL_GIGA_MAC_VER_12:
4963 case RTL_GIGA_MAC_VER_17:
4964 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4965 break;
219a1e9d
FR		 4966
4967 case RTL_GIGA_MAC_VER_18:
ef3386f0 4968 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4969 break;
219a1e9d
FR		 4970
4971 case RTL_GIGA_MAC_VER_19:
4972 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4973 break;
219a1e9d
FR		 4974
4975 case RTL_GIGA_MAC_VER_20:
4976 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4977 break;
219a1e9d 4978
197ff761
FR		 4979 case RTL_GIGA_MAC_VER_21:
4980 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4981 break;
197ff761 4982
6fb07058
FR		 4983 case RTL_GIGA_MAC_VER_22:
4984 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4985 break;
6fb07058 4986
ef3386f0
FR		 4987 case RTL_GIGA_MAC_VER_23:
4988 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4989 break;
ef3386f0 4990
7f3e3d3a
FR		 4991 case RTL_GIGA_MAC_VER_24:
4992 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4993 break;
7f3e3d3a 4994
5b538df9 4995 case RTL_GIGA_MAC_VER_25:
daf9df6d 4996 case RTL_GIGA_MAC_VER_26:
4997 case RTL_GIGA_MAC_VER_27:
5b538df9 4998 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4999 break;
5b538df9 5000
e6de30d6 5001 case RTL_GIGA_MAC_VER_28:
5002 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 5003 break;
cecb5fd7 5004
4804b3b3 5005 case RTL_GIGA_MAC_VER_31:
5006 rtl_hw_start_8168dp(ioaddr, pdev);
5007 break;
5008
01dc7fec 5009 case RTL_GIGA_MAC_VER_32:
5010 case RTL_GIGA_MAC_VER_33:
70090424
HW		 5011 rtl_hw_start_8168e_1(ioaddr, pdev);
5012 break;
5013 case RTL_GIGA_MAC_VER_34:
5014 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 5015 break;
e6de30d6 5016
c2218925
HW		 5017 case RTL_GIGA_MAC_VER_35:
5018 case RTL_GIGA_MAC_VER_36:
5019 rtl_hw_start_8168f_1(ioaddr, pdev);
5020 break;
5021
219a1e9d
FR		 5022 default:
5023 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5024 dev->name, tp->mac_version);
4804b3b3 5025 break;
219a1e9d 5026 }
2dd99530 5027
0e485150
FR		 5028 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5029
b8363901
FR		 5030 RTL_W8(Cfg9346, Cfg9346_Lock);
5031
2dd99530 5032 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5033}
1da177e4 5034
2857ffb7
FR		 5035#define R810X_CPCMD_QUIRK_MASK (\
5036 EnableBist | \
5037 Mac_dbgo_oe | \
5038 Force_half_dup | \
5edcc537 5039 Force_rxflow_en | \
2857ffb7
FR		 5040 Force_txflow_en | \
5041 Cxpl_dbg_sel | \
5042 ASF | \
5043 PktCntrDisable | \
d24e9aaf 5044 Mac_dbgo_sel)
2857ffb7
FR		 5045
5046static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5047{
350f7596 5048 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5049 { 0x01, 0, 0x6e65 },
5050 { 0x02, 0, 0x091f },
5051 { 0x03, 0, 0xc2f9 },
5052 { 0x06, 0, 0xafb5 },
5053 { 0x07, 0, 0x0e00 },
5054 { 0x19, 0, 0xec80 },
5055 { 0x01, 0, 0x2e65 },
5056 { 0x01, 0, 0x6e65 }
5057 };
5058 u8 cfg1;
5059
650e8d5d 5060 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 5061
5062 RTL_W8(DBG_REG, FIX_NAK_1);
5063
5064 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5065
5066 RTL_W8(Config1,
5067 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5068 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5069
5070 cfg1 = RTL_R8(Config1);
5071 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5072 RTL_W8(Config1, cfg1 & ~LEDS0);
5073
2857ffb7
FR		 5074 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5075}
5076
5077static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5078{
650e8d5d 5079 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 5080
5081 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5082
5083 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5084 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5085}
5086
5087static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5088{
5089 rtl_hw_start_8102e_2(ioaddr, pdev);
5090
5091 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5092}
5093
5a5e4443
HW		 5094static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5095{
5096 static const struct ephy_info e_info_8105e_1[] = {
5097 { 0x07, 0, 0x4000 },
5098 { 0x19, 0, 0x0200 },
5099 { 0x19, 0, 0x0020 },
5100 { 0x1e, 0, 0x2000 },
5101 { 0x03, 0, 0x0001 },
5102 { 0x19, 0, 0x0100 },
5103 { 0x19, 0, 0x0004 },
5104 { 0x0a, 0, 0x0020 }
5105 };
5106
cecb5fd7 5107 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5108 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5109
cecb5fd7 5110 /* Disable Early Tally Counter */
5a5e4443
HW		 5111 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5112
5113 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5114 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 5115
5116 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5117}
5118
5119static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5120{
5121 rtl_hw_start_8105e_1(ioaddr, pdev);
5122 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5123}
5124
07ce4064
FR		 5125static void rtl_hw_start_8101(struct net_device *dev)
5126{
cdf1a608
FR		 5127 struct rtl8169_private *tp = netdev_priv(dev);
5128 void __iomem *ioaddr = tp->mmio_addr;
5129 struct pci_dev *pdev = tp->pci_dev;
5130
da78dbff
FR		 5131 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5132 tp->event_slow &= ~RxFIFOOver;
811fd301 5133
cecb5fd7
FR		 5134 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5135 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 5136 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 5137
5138 if (cap) {
5139 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5140 PCI_EXP_DEVCTL_NOSNOOP_EN);
5141 }
cdf1a608
FR		 5142 }
5143
d24e9aaf
HW		 5144 RTL_W8(Cfg9346, Cfg9346_Unlock);
5145
2857ffb7
FR		 5146 switch (tp->mac_version) {
5147 case RTL_GIGA_MAC_VER_07:
5148 rtl_hw_start_8102e_1(ioaddr, pdev);
5149 break;
5150
5151 case RTL_GIGA_MAC_VER_08:
5152 rtl_hw_start_8102e_3(ioaddr, pdev);
5153 break;
5154
5155 case RTL_GIGA_MAC_VER_09:
5156 rtl_hw_start_8102e_2(ioaddr, pdev);
5157 break;
5a5e4443
HW		 5158
5159 case RTL_GIGA_MAC_VER_29:
5160 rtl_hw_start_8105e_1(ioaddr, pdev);
5161 break;
5162 case RTL_GIGA_MAC_VER_30:
5163 rtl_hw_start_8105e_2(ioaddr, pdev);
5164 break;
cdf1a608
FR		 5165 }
5166
d24e9aaf 5167 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5168
f0298f81 5169 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5170
6f0333b8 5171 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5172
d24e9aaf 5173 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5174 RTL_W16(CPlusCmd, tp->cp_cmd);
5175
5176 RTL_W16(IntrMitigate, 0x0000);
5177
5178 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5179
5180 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5181 rtl_set_rx_tx_config_registers(tp);
5182
cdf1a608
FR		 5183 RTL_R8(IntrMask);
5184
cdf1a608
FR		 5185 rtl_set_rx_mode(dev);
5186
5187 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5188}
5189
5190static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5191{
d58d46b5
FR		 5192 struct rtl8169_private *tp = netdev_priv(dev);
5193
5194 if (new_mtu < ETH_ZLEN ||
5195 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5196 return -EINVAL;
5197
d58d46b5
FR		 5198 if (new_mtu > ETH_DATA_LEN)
5199 rtl_hw_jumbo_enable(tp);
5200 else
5201 rtl_hw_jumbo_disable(tp);
5202
1da177e4 5203 dev->mtu = new_mtu;
350fb32a
MM		 5204 netdev_update_features(dev);
5205
323bb685 5206 return 0;
1da177e4
LT		 5207}
5208
5209static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5210{
95e0918d 5211 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5212 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5213}
5214
6f0333b8
ED		 5215static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5216 void **data_buff, struct RxDesc *desc)
1da177e4 5217{
48addcc9 5218 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5219 DMA_FROM_DEVICE);
48addcc9 5220
6f0333b8
ED		 5221 kfree(*data_buff);
5222 *data_buff = NULL;
1da177e4
LT		 5223 rtl8169_make_unusable_by_asic(desc);
5224}
5225
5226static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5227{
5228 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5229
5230 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5231}
5232
5233static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5234 u32 rx_buf_sz)
5235{
5236 desc->addr = cpu_to_le64(mapping);
5237 wmb();
5238 rtl8169_mark_to_asic(desc, rx_buf_sz);
5239}
5240
6f0333b8
ED		 5241static inline void *rtl8169_align(void *data)
5242{
5243 return (void *)ALIGN((long)data, 16);
5244}
5245
0ecbe1ca
SG		 5246static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5247 struct RxDesc *desc)
1da177e4 5248{
6f0333b8 5249 void *data;
1da177e4 5250 dma_addr_t mapping;
48addcc9 5251 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5252 struct net_device *dev = tp->dev;
6f0333b8 5253 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5254
6f0333b8
ED		 5255 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5256 if (!data)
5257 return NULL;
e9f63f30 5258
6f0333b8
ED		 5259 if (rtl8169_align(data) != data) {
5260 kfree(data);
5261 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5262 if (!data)
5263 return NULL;
5264 }
3eafe507 5265
48addcc9 5266 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5267 DMA_FROM_DEVICE);
d827d86b
SG		 5268 if (unlikely(dma_mapping_error(d, mapping))) {
5269 if (net_ratelimit())
5270 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5271 goto err_out;
d827d86b 5272 }
1da177e4
LT		 5273
5274 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5275 return data;
3eafe507
SG		 5276
5277err_out:
5278 kfree(data);
5279 return NULL;
1da177e4
LT		 5280}
5281
5282static void rtl8169_rx_clear(struct rtl8169_private *tp)
5283{
07d3f51f 5284 unsigned int i;
1da177e4
LT		 5285
5286 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5287 if (tp->Rx_databuff[i]) {
5288 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5289 tp->RxDescArray + i);
5290 }
5291 }
5292}
5293
0ecbe1ca 5294static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5295{
0ecbe1ca
SG		 5296 desc->opts1 |= cpu_to_le32(RingEnd);
5297}
5b0384f4 5298
0ecbe1ca
SG		 5299static int rtl8169_rx_fill(struct rtl8169_private *tp)
5300{
5301 unsigned int i;
1da177e4 5302
0ecbe1ca
SG		 5303 for (i = 0; i < NUM_RX_DESC; i++) {
5304 void *data;
4ae47c2d 5305
6f0333b8 5306 if (tp->Rx_databuff[i])
1da177e4 5307 continue;
bcf0bf90 5308
0ecbe1ca 5309 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5310 if (!data) {
5311 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5312 goto err_out;
6f0333b8
ED		 5313 }
5314 tp->Rx_databuff[i] = data;
1da177e4 5315 }
1da177e4 5316
0ecbe1ca
SG		 5317 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5318 return 0;
5319
5320err_out:
5321 rtl8169_rx_clear(tp);
5322 return -ENOMEM;
1da177e4
LT		 5323}
5324
1da177e4
LT		 5325static int rtl8169_init_ring(struct net_device *dev)
5326{
5327 struct rtl8169_private *tp = netdev_priv(dev);
5328
5329 rtl8169_init_ring_indexes(tp);
5330
5331 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5332 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5333
0ecbe1ca 5334 return rtl8169_rx_fill(tp);
1da177e4
LT		 5335}
5336
48addcc9 5337static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5338 struct TxDesc *desc)
5339{
5340 unsigned int len = tx_skb->len;
5341
48addcc9
SG		 5342 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5343
1da177e4
LT		 5344 desc->opts1 = 0x00;
5345 desc->opts2 = 0x00;
5346 desc->addr = 0x00;
5347 tx_skb->len = 0;
5348}
5349
3eafe507
SG		 5350static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5351 unsigned int n)
1da177e4
LT		 5352{
5353 unsigned int i;
5354
3eafe507
SG		 5355 for (i = 0; i < n; i++) {
5356 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5357 struct ring_info *tx_skb = tp->tx_skb + entry;
5358 unsigned int len = tx_skb->len;
5359
5360 if (len) {
5361 struct sk_buff *skb = tx_skb->skb;
5362
48addcc9 5363 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5364 tp->TxDescArray + entry);
5365 if (skb) {
cac4b22f 5366 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5367 dev_kfree_skb(skb);
5368 tx_skb->skb = NULL;
5369 }
1da177e4
LT		 5370 }
5371 }
3eafe507
SG		 5372}
5373
5374static void rtl8169_tx_clear(struct rtl8169_private *tp)
5375{
5376 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5377 tp->cur_tx = tp->dirty_tx = 0;
5378}
5379
4422bcd4 5380static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5381{
c4028958 5382 struct net_device *dev = tp->dev;
56de414c 5383 int i;
1da177e4 5384
da78dbff
FR		 5385 napi_disable(&tp->napi);
5386 netif_stop_queue(dev);
5387 synchronize_sched();
1da177e4 5388
c7c2c39b 5389 rtl8169_hw_reset(tp);
5390
56de414c
FR		 5391 for (i = 0; i < NUM_RX_DESC; i++)
5392 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5393
1da177e4 5394 rtl8169_tx_clear(tp);
c7c2c39b 5395 rtl8169_init_ring_indexes(tp);
1da177e4 5396
da78dbff 5397 napi_enable(&tp->napi);
56de414c
FR		 5398 rtl_hw_start(dev);
5399 netif_wake_queue(dev);
5400 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5401}
5402
5403static void rtl8169_tx_timeout(struct net_device *dev)
5404{
da78dbff
FR		 5405 struct rtl8169_private *tp = netdev_priv(dev);
5406
5407 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5408}
5409
5410static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5411 u32 *opts)
1da177e4
LT		 5412{
5413 struct skb_shared_info *info = skb_shinfo(skb);
5414 unsigned int cur_frag, entry;
a6343afb 5415 struct TxDesc * uninitialized_var(txd);
48addcc9 5416 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5417
5418 entry = tp->cur_tx;
5419 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5420 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5421 dma_addr_t mapping;
5422 u32 status, len;
5423 void *addr;
5424
5425 entry = (entry + 1) % NUM_TX_DESC;
5426
5427 txd = tp->TxDescArray + entry;
9e903e08 5428 len = skb_frag_size(frag);
929f6189 5429 addr = skb_frag_address(frag);
48addcc9 5430 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5431 if (unlikely(dma_mapping_error(d, mapping))) {
5432 if (net_ratelimit())
5433 netif_err(tp, drv, tp->dev,
5434 "Failed to map TX fragments DMA!\n");
3eafe507 5435 goto err_out;
d827d86b 5436 }
1da177e4 5437
cecb5fd7 5438 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5439 status = opts[0] | len |
5440 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5441
5442 txd->opts1 = cpu_to_le32(status);
2b7b4318 5443 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5444 txd->addr = cpu_to_le64(mapping);
5445
5446 tp->tx_skb[entry].len = len;
5447 }
5448
5449 if (cur_frag) {
5450 tp->tx_skb[entry].skb = skb;
5451 txd->opts1 |= cpu_to_le32(LastFrag);
5452 }
5453
5454 return cur_frag;
3eafe507
SG		 5455
5456err_out:
5457 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5458 return -EIO;
1da177e4
LT		 5459}
5460
2b7b4318
FR		 5461static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5462 struct sk_buff *skb, u32 *opts)
1da177e4 5463{
2b7b4318 5464 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5465 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5466 int offset = info->opts_offset;
350fb32a 5467
2b7b4318
FR		 5468 if (mss) {
5469 opts[0] |= TD_LSO;
5470 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5471 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5472 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5473
5474 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5475 opts[offset] |= info->checksum.tcp;
1da177e4 5476 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5477 opts[offset] |= info->checksum.udp;
5478 else
5479 WARN_ON_ONCE(1);
1da177e4 5480 }
1da177e4
LT		 5481}
5482
61357325
SH		 5483static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5484 struct net_device *dev)
1da177e4
LT		 5485{
5486 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5487 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5488 struct TxDesc *txd = tp->TxDescArray + entry;
5489 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5490 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5491 dma_addr_t mapping;
5492 u32 status, len;
2b7b4318 5493 u32 opts[2];
3eafe507 5494 int frags;
5b0384f4 5495
1da177e4 5496 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5497 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5498 goto err_stop_0;
1da177e4
LT		 5499 }
5500
5501 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5502 goto err_stop_0;
5503
5504 len = skb_headlen(skb);
48addcc9 5505 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5506 if (unlikely(dma_mapping_error(d, mapping))) {
5507 if (net_ratelimit())
5508 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5509 goto err_dma_0;
d827d86b 5510 }
3eafe507
SG		 5511
5512 tp->tx_skb[entry].len = len;
5513 txd->addr = cpu_to_le64(mapping);
1da177e4 5514
2b7b4318
FR		 5515 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5516 opts[0] = DescOwn;
1da177e4 5517
2b7b4318
FR		 5518 rtl8169_tso_csum(tp, skb, opts);
5519
5520 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5521 if (frags < 0)
5522 goto err_dma_1;
5523 else if (frags)
2b7b4318 5524 opts[0] |= FirstFrag;
3eafe507 5525 else {
2b7b4318 5526 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5527 tp->tx_skb[entry].skb = skb;
5528 }
5529
2b7b4318
FR		 5530 txd->opts2 = cpu_to_le32(opts[1]);
5531
1da177e4
LT		 5532 wmb();
5533
cecb5fd7 5534 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5535 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5536 txd->opts1 = cpu_to_le32(status);
5537
1da177e4
LT		 5538 tp->cur_tx += frags + 1;
5539
4c020a96 5540 wmb();
1da177e4 5541
cecb5fd7 5542 RTL_W8(TxPoll, NPQ);
1da177e4 5543
da78dbff
FR		 5544 mmiowb();
5545
1da177e4 5546 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
ae1f23fb
FR		 5547 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5548 * not miss a ring update when it notices a stopped queue.
5549 */
5550 smp_wmb();
1da177e4 5551 netif_stop_queue(dev);
ae1f23fb
FR		 5552 /* Sync with rtl_tx:
5553 * - publish queue status and cur_tx ring index (write barrier)
5554 * - refresh dirty_tx ring index (read barrier).
5555 * May the current thread have a pessimistic view of the ring
5556 * status and forget to wake up queue, a racing rtl_tx thread
5557 * can't.
5558 */
1e874e04 5559 smp_mb();
1da177e4
LT		 5560 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5561 netif_wake_queue(dev);
5562 }
5563
61357325 5564 return NETDEV_TX_OK;
1da177e4 5565
3eafe507 5566err_dma_1:
48addcc9 5567 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5568err_dma_0:
5569 dev_kfree_skb(skb);
5570 dev->stats.tx_dropped++;
5571 return NETDEV_TX_OK;
5572
5573err_stop_0:
1da177e4 5574 netif_stop_queue(dev);
cebf8cc7 5575 dev->stats.tx_dropped++;
61357325 5576 return NETDEV_TX_BUSY;
1da177e4
LT		 5577}
5578
5579static void rtl8169_pcierr_interrupt(struct net_device *dev)
5580{
5581 struct rtl8169_private *tp = netdev_priv(dev);
5582 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5583 u16 pci_status, pci_cmd;
5584
5585 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5586 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5587
bf82c189
JP		 5588 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5589 pci_cmd, pci_status);
1da177e4
LT		 5590
5591 /*
5592 * The recovery sequence below admits a very elaborated explanation:
5593 * - it seems to work;
d03902b8
FR		 5594 * - I did not see what else could be done;
5595 * - it makes iop3xx happy.
1da177e4
LT		 5596 *
5597 * Feel free to adjust to your needs.
5598 */
a27993f3 5599 if (pdev->broken_parity_status)
d03902b8
FR		 5600 pci_cmd &= ~PCI_COMMAND_PARITY;
5601 else
5602 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5603
5604 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5605
5606 pci_write_config_word(pdev, PCI_STATUS,
5607 pci_status & (PCI_STATUS_DETECTED_PARITY |
5608 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5609 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5610
5611 /* The infamous DAC f*ckup only happens at boot time */
5612 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5613 void __iomem *ioaddr = tp->mmio_addr;
5614
bf82c189 5615 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5616 tp->cp_cmd &= ~PCIDAC;
5617 RTL_W16(CPlusCmd, tp->cp_cmd);
5618 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5619 }
5620
e6de30d6 5621 rtl8169_hw_reset(tp);
d03902b8 5622
98ddf986 5623 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5624}
5625
da78dbff 5626static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5627{
5628 unsigned int dirty_tx, tx_left;
5629
1da177e4
LT		 5630 dirty_tx = tp->dirty_tx;
5631 smp_rmb();
5632 tx_left = tp->cur_tx - dirty_tx;
5633
5634 while (tx_left > 0) {
5635 unsigned int entry = dirty_tx % NUM_TX_DESC;
5636 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5637 u32 status;
5638
5639 rmb();
5640 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5641 if (status & DescOwn)
5642 break;
5643
48addcc9
SG		 5644 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5645 tp->TxDescArray + entry);
1da177e4 5646 if (status & LastFrag) {
cac4b22f
SG		 5647 dev->stats.tx_packets++;
5648 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 5649 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5650 tx_skb->skb = NULL;
5651 }
5652 dirty_tx++;
5653 tx_left--;
5654 }
5655
5656 if (tp->dirty_tx != dirty_tx) {
5657 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5658 /* Sync with rtl8169_start_xmit:
5659 * - publish dirty_tx ring index (write barrier)
5660 * - refresh cur_tx ring index and queue status (read barrier)
5661 * May the current thread miss the stopped queue condition,
5662 * a racing xmit thread can only have a right view of the
5663 * ring status.
5664 */
1e874e04 5665 smp_mb();
1da177e4
LT		 5666 if (netif_queue_stopped(dev) &&
5667 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5668 netif_wake_queue(dev);
5669 }
d78ae2dc
FR		 5670 /*
5671 * 8168 hack: TxPoll requests are lost when the Tx packets are
5672 * too close. Let's kick an extra TxPoll request when a burst
5673 * of start_xmit activity is detected (if it is not detected,
5674 * it is slow enough). -- FR
5675 */
da78dbff
FR		 5676 if (tp->cur_tx != dirty_tx) {
5677 void __iomem *ioaddr = tp->mmio_addr;
5678
d78ae2dc 5679 RTL_W8(TxPoll, NPQ);
da78dbff 5680 }
1da177e4
LT		 5681 }
5682}
5683
126fa4b9
FR		 5684static inline int rtl8169_fragmented_frame(u32 status)
5685{
5686 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5687}
5688
adea1ac7 5689static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5690{
1da177e4
LT		 5691 u32 status = opts1 & RxProtoMask;
5692
5693 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5694 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5695 skb->ip_summed = CHECKSUM_UNNECESSARY;
5696 else
bc8acf2c 5697 skb_checksum_none_assert(skb);
1da177e4
LT		 5698}
5699
6f0333b8
ED		 5700static struct sk_buff *rtl8169_try_rx_copy(void *data,
5701 struct rtl8169_private *tp,
5702 int pkt_size,
5703 dma_addr_t addr)
1da177e4 5704{
b449655f 5705 struct sk_buff *skb;
48addcc9 5706 struct device *d = &tp->pci_dev->dev;
b449655f 5707
6f0333b8 5708 data = rtl8169_align(data);
48addcc9 5709 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5710 prefetch(data);
5711 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5712 if (skb)
5713 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5714 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5715
6f0333b8 5716 return skb;
1da177e4
LT		 5717}
5718
da78dbff 5719static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 5720{
5721 unsigned int cur_rx, rx_left;
6f0333b8 5722 unsigned int count;
1da177e4 5723
1da177e4
LT		 5724 cur_rx = tp->cur_rx;
5725 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5726 rx_left = min(rx_left, budget);
1da177e4 5727
4dcb7d33 5728 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5729 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5730 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5731 u32 status;
5732
5733 rmb();
e03f33af 5734 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 5735
5736 if (status & DescOwn)
5737 break;
4dcb7d33 5738 if (unlikely(status & RxRES)) {
bf82c189
JP		 5739 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5740 status);
cebf8cc7 5741 dev->stats.rx_errors++;
1da177e4 5742 if (status & (RxRWT | RxRUNT))
cebf8cc7 5743 dev->stats.rx_length_errors++;
1da177e4 5744 if (status & RxCRC)
cebf8cc7 5745 dev->stats.rx_crc_errors++;
9dccf611 5746 if (status & RxFOVF) {
da78dbff 5747 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 5748 dev->stats.rx_fifo_errors++;
9dccf611 5749 }
6f0333b8 5750 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5751 } else {
6f0333b8 5752 struct sk_buff *skb;
b449655f 5753 dma_addr_t addr = le64_to_cpu(desc->addr);
deb9d93c 5754 int pkt_size = (status & 0x00003fff) - 4;
1da177e4 5755
126fa4b9
FR		 5756 /*
5757 * The driver does not support incoming fragmented
5758 * frames. They are seen as a symptom of over-mtu
5759 * sized frames.
5760 */
5761 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5762 dev->stats.rx_dropped++;
5763 dev->stats.rx_length_errors++;
6f0333b8 5764 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5765 continue;
126fa4b9
FR		 5766 }
5767
6f0333b8
ED		 5768 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5769 tp, pkt_size, addr);
5770 rtl8169_mark_to_asic(desc, rx_buf_sz);
5771 if (!skb) {
5772 dev->stats.rx_dropped++;
5773 continue;
1da177e4
LT		 5774 }
5775
adea1ac7 5776 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5777 skb_put(skb, pkt_size);
5778 skb->protocol = eth_type_trans(skb, dev);
5779
7a8fc77b
FR		 5780 rtl8169_rx_vlan_tag(desc, skb);
5781
56de414c 5782 napi_gro_receive(&tp->napi, skb);
1da177e4 5783
cebf8cc7
FR		 5784 dev->stats.rx_bytes += pkt_size;
5785 dev->stats.rx_packets++;
1da177e4 5786 }
6dccd16b
FR		 5787
5788 /* Work around for AMD plateform. */
95e0918d 5789 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5790 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5791 desc->opts2 = 0;
5792 cur_rx++;
5793 }
1da177e4
LT		 5794 }
5795
5796 count = cur_rx - tp->cur_rx;
5797 tp->cur_rx = cur_rx;
5798
6f0333b8 5799 tp->dirty_rx += count;
1da177e4
LT		 5800
5801 return count;
5802}
5803
07d3f51f 5804static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5805{
07d3f51f 5806 struct net_device *dev = dev_instance;
1da177e4 5807 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5808 int handled = 0;
9085cdfa 5809 u16 status;
1da177e4 5810
9085cdfa 5811 status = rtl_get_events(tp);
da78dbff
FR		 5812 if (status && status != 0xffff) {
5813 status &= RTL_EVENT_NAPI | tp->event_slow;
5814 if (status) {
5815 handled = 1;
1da177e4 5816
da78dbff
FR		 5817 rtl_irq_disable(tp);
5818 napi_schedule(&tp->napi);
f11a377b 5819 }
da78dbff
FR		 5820 }
5821 return IRQ_RETVAL(handled);
5822}
1da177e4 5823
da78dbff
FR		 5824/*
5825 * Workqueue context.
5826 */
5827static void rtl_slow_event_work(struct rtl8169_private *tp)
5828{
5829 struct net_device *dev = tp->dev;
5830 u16 status;
5831
5832 status = rtl_get_events(tp) & tp->event_slow;
5833 rtl_ack_events(tp, status);
1da177e4 5834
da78dbff
FR		 5835 if (unlikely(status & RxFIFOOver)) {
5836 switch (tp->mac_version) {
5837 /* Work around for rx fifo overflow */
5838 case RTL_GIGA_MAC_VER_11:
5839 netif_stop_queue(dev);
934714d0
FR		 5840 /* XXX - Hack alert. See rtl_task(). */
5841 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 5842 default:
f11a377b
DD		 5843 break;
5844 }
da78dbff 5845 }
1da177e4 5846
da78dbff
FR		 5847 if (unlikely(status & SYSErr))
5848 rtl8169_pcierr_interrupt(dev);
0e485150 5849
da78dbff
FR		 5850 if (status & LinkChg)
5851 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 5852
da78dbff
FR		 5853 napi_disable(&tp->napi);
5854 rtl_irq_disable(tp);
5855
5856 napi_enable(&tp->napi);
5857 napi_schedule(&tp->napi);
1da177e4
LT		 5858}
5859
4422bcd4
FR		 5860static void rtl_task(struct work_struct *work)
5861{
da78dbff
FR		 5862 static const struct {
5863 int bitnr;
5864 void (*action)(struct rtl8169_private *);
5865 } rtl_work[] = {
934714d0 5866 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 5867 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5868 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5869 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5870 };
4422bcd4
FR		 5871 struct rtl8169_private *tp =
5872 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 5873 struct net_device *dev = tp->dev;
5874 int i;
5875
5876 rtl_lock_work(tp);
5877
6c4a70c5
FR		 5878 if (!netif_running(dev) ||
5879 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 5880 goto out_unlock;
5881
5882 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5883 bool pending;
5884
da78dbff 5885 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 5886 if (pending)
5887 rtl_work[i].action(tp);
5888 }
4422bcd4 5889
da78dbff
FR		 5890out_unlock:
5891 rtl_unlock_work(tp);
4422bcd4
FR		 5892}
5893
bea3348e 5894static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5895{
bea3348e
SH		 5896 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5897 struct net_device *dev = tp->dev;
da78dbff
FR		 5898 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5899 int work_done= 0;
5900 u16 status;
5901
5902 status = rtl_get_events(tp);
5903 rtl_ack_events(tp, status & ~tp->event_slow);
5904
5905 if (status & RTL_EVENT_NAPI_RX)
5906 work_done = rtl_rx(dev, tp, (u32) budget);
5907
5908 if (status & RTL_EVENT_NAPI_TX)
5909 rtl_tx(dev, tp);
1da177e4 5910
da78dbff
FR		 5911 if (status & tp->event_slow) {
5912 enable_mask &= ~tp->event_slow;
5913
5914 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5915 }
1da177e4 5916
bea3348e 5917 if (work_done < budget) {
288379f0 5918 napi_complete(napi);
f11a377b 5919
da78dbff
FR		 5920 rtl_irq_enable(tp, enable_mask);
5921 mmiowb();
1da177e4
LT		 5922 }
5923
bea3348e 5924 return work_done;
1da177e4 5925}
1da177e4 5926
523a6094
FR		 5927static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5928{
5929 struct rtl8169_private *tp = netdev_priv(dev);
5930
5931 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5932 return;
5933
5934 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5935 RTL_W32(RxMissed, 0);
5936}
5937
1da177e4
LT		 5938static void rtl8169_down(struct net_device *dev)
5939{
5940 struct rtl8169_private *tp = netdev_priv(dev);
5941 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5942
4876cc1e 5943 del_timer_sync(&tp->timer);
1da177e4 5944
93dd79e8 5945 napi_disable(&tp->napi);
da78dbff 5946 netif_stop_queue(dev);
1da177e4 5947
92fc43b4 5948 rtl8169_hw_reset(tp);
323bb685
SG		 5949 /*
5950 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 5951 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5952 * and napi is disabled (rtl8169_poll).
323bb685 5953 */
523a6094 5954 rtl8169_rx_missed(dev, ioaddr);
1da177e4 5955
1da177e4 5956 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 5957 synchronize_sched();
1da177e4 5958
1da177e4
LT		 5959 rtl8169_tx_clear(tp);
5960
5961 rtl8169_rx_clear(tp);
065c27c1 5962
5963 rtl_pll_power_down(tp);
1da177e4
LT		 5964}
5965
5966static int rtl8169_close(struct net_device *dev)
5967{
5968 struct rtl8169_private *tp = netdev_priv(dev);
5969 struct pci_dev *pdev = tp->pci_dev;
5970
e1759441
RW		 5971 pm_runtime_get_sync(&pdev->dev);
5972
cecb5fd7 5973 /* Update counters before going down */
355423d0
IV		 5974 rtl8169_update_counters(dev);
5975
da78dbff 5976 rtl_lock_work(tp);
6c4a70c5 5977 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 5978
1da177e4 5979 rtl8169_down(dev);
da78dbff 5980 rtl_unlock_work(tp);
1da177e4
LT		 5981
5982 free_irq(dev->irq, dev);
5983
82553bb6
SG		 5984 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5985 tp->RxPhyAddr);
5986 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5987 tp->TxPhyAddr);
1da177e4
LT		 5988 tp->TxDescArray = NULL;
5989 tp->RxDescArray = NULL;
5990
e1759441
RW		 5991 pm_runtime_put_sync(&pdev->dev);
5992
1da177e4
LT		 5993 return 0;
5994}
5995
07ce4064 5996static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5997{
5998 struct rtl8169_private *tp = netdev_priv(dev);
5999 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6000 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 6001 int rx_mode;
1da177e4
LT		 6002 u32 tmp = 0;
6003
6004 if (dev->flags & IFF_PROMISC) {
6005 /* Unconditionally log net taps. */
bf82c189 6006 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 6007 rx_mode =
6008 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
6009 AcceptAllPhys;
6010 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 6011 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 6012 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 6013 /* Too many to filter perfectly -- accept all multicasts. */
6014 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
6015 mc_filter[1] = mc_filter[0] = 0xffffffff;
6016 } else {
22bedad3 6017 struct netdev_hw_addr *ha;
07d3f51f 6018
1da177e4
LT		 6019 rx_mode = AcceptBroadcast | AcceptMyPhys;
6020 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 6021 netdev_for_each_mc_addr(ha, dev) {
6022 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 6023 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6024 rx_mode |= AcceptMulticast;
6025 }
6026 }
6027
1687b566 6028 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
1da177e4 6029
f887cce8 6030 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 6031 u32 data = mc_filter[0];
6032
6033 mc_filter[0] = swab32(mc_filter[1]);
6034 mc_filter[1] = swab32(data);
bcf0bf90
FR		 6035 }
6036
1da177e4 6037 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 6038 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 6039
57a9f236 6040 RTL_W32(RxConfig, tmp);
1da177e4
LT		 6041}
6042
6043/**
6044 * rtl8169_get_stats - Get rtl8169 read/write statistics
6045 * @dev: The Ethernet Device to get statistics for
6046 *
6047 * Get TX/RX statistics for rtl8169
6048 */
6049static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6050{
6051 struct rtl8169_private *tp = netdev_priv(dev);
6052 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6053
da78dbff 6054 if (netif_running(dev))
523a6094 6055 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6056
cebf8cc7 6057 return &dev->stats;
1da177e4
LT		 6058}
6059
861ab440 6060static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6061{
065c27c1 6062 struct rtl8169_private *tp = netdev_priv(dev);
6063
5d06a99f 6064 if (!netif_running(dev))
861ab440 6065 return;
5d06a99f
FR		 6066
6067 netif_device_detach(dev);
6068 netif_stop_queue(dev);
da78dbff
FR		 6069
6070 rtl_lock_work(tp);
6071 napi_disable(&tp->napi);
6c4a70c5 6072 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6073 rtl_unlock_work(tp);
6074
6075 rtl_pll_power_down(tp);
861ab440
RW		 6076}
6077
6078#ifdef CONFIG_PM
6079
6080static int rtl8169_suspend(struct device *device)
6081{
6082 struct pci_dev *pdev = to_pci_dev(device);
6083 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6084
861ab440 6085 rtl8169_net_suspend(dev);
1371fa6d 6086
5d06a99f
FR		 6087 return 0;
6088}
6089
e1759441
RW		 6090static void __rtl8169_resume(struct net_device *dev)
6091{
065c27c1 6092 struct rtl8169_private *tp = netdev_priv(dev);
6093
e1759441 6094 netif_device_attach(dev);
065c27c1 6095
6096 rtl_pll_power_up(tp);
6097
6c4a70c5 6098 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6099
98ddf986 6100 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6101}
6102
861ab440 6103static int rtl8169_resume(struct device *device)
5d06a99f 6104{
861ab440 6105 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6106 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6107 struct rtl8169_private *tp = netdev_priv(dev);
6108
6109 rtl8169_init_phy(dev, tp);
5d06a99f 6110
e1759441
RW		 6111 if (netif_running(dev))
6112 __rtl8169_resume(dev);
5d06a99f 6113
e1759441
RW		 6114 return 0;
6115}
6116
6117static int rtl8169_runtime_suspend(struct device *device)
6118{
6119 struct pci_dev *pdev = to_pci_dev(device);
6120 struct net_device *dev = pci_get_drvdata(pdev);
6121 struct rtl8169_private *tp = netdev_priv(dev);
6122
6123 if (!tp->TxDescArray)
6124 return 0;
6125
da78dbff 6126 rtl_lock_work(tp);
e1759441
RW		 6127 tp->saved_wolopts = __rtl8169_get_wol(tp);
6128 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6129 rtl_unlock_work(tp);
e1759441
RW		 6130
6131 rtl8169_net_suspend(dev);
6132
6133 return 0;
6134}
6135
6136static int rtl8169_runtime_resume(struct device *device)
6137{
6138 struct pci_dev *pdev = to_pci_dev(device);
6139 struct net_device *dev = pci_get_drvdata(pdev);
6140 struct rtl8169_private *tp = netdev_priv(dev);
6141
6142 if (!tp->TxDescArray)
6143 return 0;
6144
da78dbff 6145 rtl_lock_work(tp);
e1759441
RW		 6146 __rtl8169_set_wol(tp, tp->saved_wolopts);
6147 tp->saved_wolopts = 0;
da78dbff 6148 rtl_unlock_work(tp);
e1759441 6149
fccec10b
SG		 6150 rtl8169_init_phy(dev, tp);
6151
e1759441 6152 __rtl8169_resume(dev);
5d06a99f 6153
5d06a99f
FR		 6154 return 0;
6155}
6156
e1759441
RW		 6157static int rtl8169_runtime_idle(struct device *device)
6158{
6159 struct pci_dev *pdev = to_pci_dev(device);
6160 struct net_device *dev = pci_get_drvdata(pdev);
6161 struct rtl8169_private *tp = netdev_priv(dev);
6162
e4fbce74 6163 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6164}
6165
47145210 6166static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6167 .suspend = rtl8169_suspend,
6168 .resume = rtl8169_resume,
6169 .freeze = rtl8169_suspend,
6170 .thaw = rtl8169_resume,
6171 .poweroff = rtl8169_suspend,
6172 .restore = rtl8169_resume,
6173 .runtime_suspend = rtl8169_runtime_suspend,
6174 .runtime_resume = rtl8169_runtime_resume,
6175 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6176};
6177
6178#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6179
6180#else /* !CONFIG_PM */
6181
6182#define RTL8169_PM_OPS NULL
6183
6184#endif /* !CONFIG_PM */
6185
649b3b8c 6186static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6187{
6188 void __iomem *ioaddr = tp->mmio_addr;
6189
6190 /* WoL fails with 8168b when the receiver is disabled. */
6191 switch (tp->mac_version) {
6192 case RTL_GIGA_MAC_VER_11:
6193 case RTL_GIGA_MAC_VER_12:
6194 case RTL_GIGA_MAC_VER_17:
6195 pci_clear_master(tp->pci_dev);
6196
6197 RTL_W8(ChipCmd, CmdRxEnb);
6198 /* PCI commit */
6199 RTL_R8(ChipCmd);
6200 break;
6201 default:
6202 break;
6203 }
6204}
6205
1765f95d
FR		 6206static void rtl_shutdown(struct pci_dev *pdev)
6207{
861ab440 6208 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6209 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 6210
6211 rtl8169_net_suspend(dev);
1765f95d 6212
cecb5fd7 6213 /* Restore original MAC address */
cc098dc7
IV		 6214 rtl_rar_set(tp, dev->perm_addr);
6215
92fc43b4 6216 rtl8169_hw_reset(tp);
4bb3f522 6217
861ab440 6218 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6219 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6220 rtl_wol_suspend_quirk(tp);
6221 rtl_wol_shutdown_quirk(tp);
ca52efd5 6222 }
6223
861ab440
RW		 6224 pci_wake_from_d3(pdev, true);
6225 pci_set_power_state(pdev, PCI_D3hot);
6226 }
6227}
5d06a99f 6228
1da177e4
LT		 6229static struct pci_driver rtl8169_pci_driver = {
6230 .name = MODULENAME,
6231 .id_table = rtl8169_pci_tbl,
6232 .probe = rtl8169_init_one,
6233 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 6234 .shutdown = rtl_shutdown,
861ab440 6235 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 6236};
6237
07d3f51f 6238static int __init rtl8169_init_module(void)
1da177e4 6239{
29917620 6240 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 6241}
6242
07d3f51f 6243static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 6244{
6245 pci_unregister_driver(&rtl8169_pci_driver);
6246}
6247
6248module_init(rtl8169_init_module);
6249module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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