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ipv6: unify fragment thresh handling code
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
c558386b 50#define FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw"
bca03d5f 51
1da177e4
LT		 52#ifdef RTL8169_DEBUG
53#define assert(expr) \
5b0384f4
FR		 54 if (!(expr)) { \
55 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 56 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 57 }
06fa7358
JP		 58#define dprintk(fmt, args...) \
59 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 60#else
61#define assert(expr) do {} while (0)
62#define dprintk(fmt, args...) do {} while (0)
63#endif /* RTL8169_DEBUG */
64
b57b7e5a 65#define R8169_MSG_DEFAULT \
f0e837d9 66 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 67
477206a0
JD		 68#define TX_SLOTS_AVAIL(tp) \
69 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72#define TX_FRAGS_READY_FOR(tp,nr_frags) \
73 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 74
1da177e4
LT		 75/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 77static const int multicast_filter_limit = 32;
1da177e4 78
9c14ceaf 79#define MAX_READ_REQUEST_SHIFT 12
1da177e4 80#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 81#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
82#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
83
84#define R8169_REGS_SIZE 256
85#define R8169_NAPI_WEIGHT 64
86#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
87#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
88#define RX_BUF_SIZE 1536 /* Rx Buffer size */
89#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
90#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
91
92#define RTL8169_TX_TIMEOUT (6*HZ)
93#define RTL8169_PHY_TIMEOUT (10*HZ)
94
ea8dbdd1 95#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
96#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 97#define RTL_EEPROM_SIG_ADDR 0x0000
98
1da177e4
LT		 99/* write/read MMIO register */
100#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103#define RTL_R8(reg) readb (ioaddr + (reg))
104#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 105#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 106
107enum mac_version {
85bffe6c
FR		 108 RTL_GIGA_MAC_VER_01 = 0,
109 RTL_GIGA_MAC_VER_02,
110 RTL_GIGA_MAC_VER_03,
111 RTL_GIGA_MAC_VER_04,
112 RTL_GIGA_MAC_VER_05,
113 RTL_GIGA_MAC_VER_06,
114 RTL_GIGA_MAC_VER_07,
115 RTL_GIGA_MAC_VER_08,
116 RTL_GIGA_MAC_VER_09,
117 RTL_GIGA_MAC_VER_10,
118 RTL_GIGA_MAC_VER_11,
119 RTL_GIGA_MAC_VER_12,
120 RTL_GIGA_MAC_VER_13,
121 RTL_GIGA_MAC_VER_14,
122 RTL_GIGA_MAC_VER_15,
123 RTL_GIGA_MAC_VER_16,
124 RTL_GIGA_MAC_VER_17,
125 RTL_GIGA_MAC_VER_18,
126 RTL_GIGA_MAC_VER_19,
127 RTL_GIGA_MAC_VER_20,
128 RTL_GIGA_MAC_VER_21,
129 RTL_GIGA_MAC_VER_22,
130 RTL_GIGA_MAC_VER_23,
131 RTL_GIGA_MAC_VER_24,
132 RTL_GIGA_MAC_VER_25,
133 RTL_GIGA_MAC_VER_26,
134 RTL_GIGA_MAC_VER_27,
135 RTL_GIGA_MAC_VER_28,
136 RTL_GIGA_MAC_VER_29,
137 RTL_GIGA_MAC_VER_30,
138 RTL_GIGA_MAC_VER_31,
139 RTL_GIGA_MAC_VER_32,
140 RTL_GIGA_MAC_VER_33,
70090424 141 RTL_GIGA_MAC_VER_34,
c2218925
HW		 142 RTL_GIGA_MAC_VER_35,
143 RTL_GIGA_MAC_VER_36,
7e18dca1 144 RTL_GIGA_MAC_VER_37,
b3d7b2f2 145 RTL_GIGA_MAC_VER_38,
5598bfe5 146 RTL_GIGA_MAC_VER_39,
c558386b
HW		 147 RTL_GIGA_MAC_VER_40,
148 RTL_GIGA_MAC_VER_41,
85bffe6c 149 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 150};
151
2b7b4318
FR		 152enum rtl_tx_desc_version {
153 RTL_TD_0 = 0,
154 RTL_TD_1 = 1,
155};
156
d58d46b5
FR		 157#define JUMBO_1K ETH_DATA_LEN
158#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
159#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
160#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
161#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
162
163#define _R(NAME,TD,FW,SZ,B) { \
164 .name = NAME, \
165 .txd_version = TD, \
166 .fw_name = FW, \
167 .jumbo_max = SZ, \
168 .jumbo_tx_csum = B \
169}
1da177e4 170
3c6bee1d 171static const struct {
1da177e4 172 const char *name;
2b7b4318 173 enum rtl_tx_desc_version txd_version;
953a12cc 174 const char *fw_name;
d58d46b5
FR		 175 u16 jumbo_max;
176 bool jumbo_tx_csum;
85bffe6c
FR		 177} rtl_chip_infos[] = {
178 /* PCI devices. */
179 [RTL_GIGA_MAC_VER_01] =
d58d46b5 180 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_02] =
d58d46b5 182 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_03] =
d58d46b5 184 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 185 [RTL_GIGA_MAC_VER_04] =
d58d46b5 186 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 187 [RTL_GIGA_MAC_VER_05] =
d58d46b5 188 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 189 [RTL_GIGA_MAC_VER_06] =
d58d46b5 190 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 191 /* PCI-E devices. */
192 [RTL_GIGA_MAC_VER_07] =
d58d46b5 193 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_08] =
d58d46b5 195 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_09] =
d58d46b5 197 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_10] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_11] =
d58d46b5 201 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 202 [RTL_GIGA_MAC_VER_12] =
d58d46b5 203 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 204 [RTL_GIGA_MAC_VER_13] =
d58d46b5 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_14] =
d58d46b5 207 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_15] =
d58d46b5 209 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_16] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_17] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_18] =
d58d46b5 215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_19] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_20] =
d58d46b5 219 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_21] =
d58d46b5 221 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_22] =
d58d46b5 223 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 224 [RTL_GIGA_MAC_VER_23] =
d58d46b5 225 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_24] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 229 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
230 JUMBO_9K, false),
85bffe6c 231 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 232 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
233 JUMBO_9K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_27] =
d58d46b5 235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_28] =
d58d46b5 237 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 239 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
240 JUMBO_1K, true),
85bffe6c 241 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 242 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
243 JUMBO_1K, true),
85bffe6c 244 [RTL_GIGA_MAC_VER_31] =
d58d46b5 245 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 247 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
248 JUMBO_9K, false),
85bffe6c 249 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 250 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
251 JUMBO_9K, false),
70090424 252 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 253 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
254 JUMBO_9K, false),
c2218925 255 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 256 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
257 JUMBO_9K, false),
c2218925 258 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 259 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
260 JUMBO_9K, false),
7e18dca1
HW		 261 [RTL_GIGA_MAC_VER_37] =
262 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
263 JUMBO_1K, true),
b3d7b2f2
HW		 264 [RTL_GIGA_MAC_VER_38] =
265 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
266 JUMBO_9K, false),
5598bfe5
HW		 267 [RTL_GIGA_MAC_VER_39] =
268 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
269 JUMBO_1K, true),
c558386b
HW		 270 [RTL_GIGA_MAC_VER_40] =
271 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_1,
272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_41] =
274 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
953a12cc 275};
85bffe6c 276#undef _R
953a12cc 277
bcf0bf90
FR		 278enum cfg_version {
279 RTL_CFG_0 = 0x00,
280 RTL_CFG_1,
281 RTL_CFG_2
282};
283
a3aa1884 284static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 285 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 286 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 287 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 288 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 289 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 290 { PCI_VENDOR_ID_DLINK, 0x4300,
291 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 292 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 293 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 294 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 295 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
296 { PCI_VENDOR_ID_LINKSYS, 0x1032,
297 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 298 { 0x0001, 0x8168,
299 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 300 {0,},
301};
302
303MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
304
6f0333b8 305static int rx_buf_sz = 16383;
4300e8c7 306static int use_dac;
b57b7e5a
SH		 307static struct {
308 u32 msg_enable;
309} debug = { -1 };
1da177e4 310
07d3f51f
FR		 311enum rtl_registers {
312 MAC0 = 0, /* Ethernet hardware address. */
773d2021 313 MAC4 = 4,
07d3f51f
FR		 314 MAR0 = 8, /* Multicast filter. */
315 CounterAddrLow = 0x10,
316 CounterAddrHigh = 0x14,
317 TxDescStartAddrLow = 0x20,
318 TxDescStartAddrHigh = 0x24,
319 TxHDescStartAddrLow = 0x28,
320 TxHDescStartAddrHigh = 0x2c,
321 FLASH = 0x30,
322 ERSR = 0x36,
323 ChipCmd = 0x37,
324 TxPoll = 0x38,
325 IntrMask = 0x3c,
326 IntrStatus = 0x3e,
4f6b00e5 327
07d3f51f 328 TxConfig = 0x40,
4f6b00e5
HW		 329#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
330#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 331
4f6b00e5
HW		 332 RxConfig = 0x44,
333#define RX128_INT_EN (1 << 15) /* 8111c and later */
334#define RX_MULTI_EN (1 << 14) /* 8111c only */
335#define RXCFG_FIFO_SHIFT 13
336 /* No threshold before first PCI xfer */
337#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
338#define RXCFG_DMA_SHIFT 8
339 /* Unlimited maximum PCI burst. */
340#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 341
07d3f51f
FR		 342 RxMissed = 0x4c,
343 Cfg9346 = 0x50,
344 Config0 = 0x51,
345 Config1 = 0x52,
346 Config2 = 0x53,
d387b427
FR		 347#define PME_SIGNAL (1 << 5) /* 8168c and later */
348
07d3f51f
FR		 349 Config3 = 0x54,
350 Config4 = 0x55,
351 Config5 = 0x56,
352 MultiIntr = 0x5c,
353 PHYAR = 0x60,
07d3f51f
FR		 354 PHYstatus = 0x6c,
355 RxMaxSize = 0xda,
356 CPlusCmd = 0xe0,
357 IntrMitigate = 0xe2,
358 RxDescAddrLow = 0xe4,
359 RxDescAddrHigh = 0xe8,
f0298f81 360 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
361
362#define NoEarlyTx 0x3f /* Max value : no early transmit. */
363
364 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
365
366#define TxPacketMax (8064 >> 7)
3090bd9a 367#define EarlySize 0x27
f0298f81 368
07d3f51f
FR		 369 FuncEvent = 0xf0,
370 FuncEventMask = 0xf4,
371 FuncPresetState = 0xf8,
372 FuncForceEvent = 0xfc,
1da177e4
LT		 373};
374
f162a5d1
FR		 375enum rtl8110_registers {
376 TBICSR = 0x64,
377 TBI_ANAR = 0x68,
378 TBI_LPAR = 0x6a,
379};
380
381enum rtl8168_8101_registers {
382 CSIDR = 0x64,
383 CSIAR = 0x68,
384#define CSIAR_FLAG 0x80000000
385#define CSIAR_WRITE_CMD 0x80000000
386#define CSIAR_BYTE_ENABLE 0x0f
387#define CSIAR_BYTE_ENABLE_SHIFT 12
388#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 389#define CSIAR_FUNC_CARD 0x00000000
390#define CSIAR_FUNC_SDIO 0x00010000
391#define CSIAR_FUNC_NIC 0x00020000
065c27c1 392 PMCH = 0x6f,
f162a5d1
FR		 393 EPHYAR = 0x80,
394#define EPHYAR_FLAG 0x80000000
395#define EPHYAR_WRITE_CMD 0x80000000
396#define EPHYAR_REG_MASK 0x1f
397#define EPHYAR_REG_SHIFT 16
398#define EPHYAR_DATA_MASK 0xffff
5a5e4443 399 DLLPR = 0xd0,
4f6b00e5 400#define PFM_EN (1 << 6)
f162a5d1
FR		 401 DBG_REG = 0xd1,
402#define FIX_NAK_1 (1 << 4)
403#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 404 TWSI = 0xd2,
405 MCU = 0xd3,
4f6b00e5 406#define NOW_IS_OOB (1 << 7)
c558386b
HW		 407#define TX_EMPTY (1 << 5)
408#define RX_EMPTY (1 << 4)
409#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 410#define EN_NDP (1 << 3)
411#define EN_OOB_RESET (1 << 2)
c558386b 412#define LINK_LIST_RDY (1 << 1)
daf9df6d 413 EFUSEAR = 0xdc,
414#define EFUSEAR_FLAG 0x80000000
415#define EFUSEAR_WRITE_CMD 0x80000000
416#define EFUSEAR_READ_CMD 0x00000000
417#define EFUSEAR_REG_MASK 0x03ff
418#define EFUSEAR_REG_SHIFT 8
419#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 420};
421
c0e45c1c 422enum rtl8168_registers {
4f6b00e5
HW		 423 LED_FREQ = 0x1a,
424 EEE_LED = 0x1b,
b646d900 425 ERIDR = 0x70,
426 ERIAR = 0x74,
427#define ERIAR_FLAG 0x80000000
428#define ERIAR_WRITE_CMD 0x80000000
429#define ERIAR_READ_CMD 0x00000000
430#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 431#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 432#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
433#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
434#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
435#define ERIAR_MASK_SHIFT 12
436#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
437#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 438#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 439#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 440 EPHY_RXER_NUM = 0x7c,
441 OCPDR = 0xb0, /* OCP GPHY access */
442#define OCPDR_WRITE_CMD 0x80000000
443#define OCPDR_READ_CMD 0x00000000
444#define OCPDR_REG_MASK 0x7f
445#define OCPDR_GPHY_REG_SHIFT 16
446#define OCPDR_DATA_MASK 0xffff
447 OCPAR = 0xb4,
448#define OCPAR_FLAG 0x80000000
449#define OCPAR_GPHY_WRITE_CMD 0x8000f060
450#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 451 GPHY_OCP = 0xb8,
01dc7fec 452 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
453 MISC = 0xf0, /* 8168e only. */
cecb5fd7 454#define TXPLA_RST (1 << 29)
5598bfe5 455#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 456#define PWM_EN (1 << 22)
c558386b 457#define RXDV_GATED_EN (1 << 19)
5598bfe5 458#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 459};
460
07d3f51f 461enum rtl_register_content {
1da177e4 462 /* InterruptStatusBits */
07d3f51f
FR		 463 SYSErr = 0x8000,
464 PCSTimeout = 0x4000,
465 SWInt = 0x0100,
466 TxDescUnavail = 0x0080,
467 RxFIFOOver = 0x0040,
468 LinkChg = 0x0020,
469 RxOverflow = 0x0010,
470 TxErr = 0x0008,
471 TxOK = 0x0004,
472 RxErr = 0x0002,
473 RxOK = 0x0001,
1da177e4
LT		 474
475 /* RxStatusDesc */
e03f33af 476 RxBOVF = (1 << 24),
9dccf611
FR		 477 RxFOVF = (1 << 23),
478 RxRWT = (1 << 22),
479 RxRES = (1 << 21),
480 RxRUNT = (1 << 20),
481 RxCRC = (1 << 19),
1da177e4
LT		 482
483 /* ChipCmdBits */
4f6b00e5 484 StopReq = 0x80,
07d3f51f
FR		 485 CmdReset = 0x10,
486 CmdRxEnb = 0x08,
487 CmdTxEnb = 0x04,
488 RxBufEmpty = 0x01,
1da177e4 489
275391a4
FR		 490 /* TXPoll register p.5 */
491 HPQ = 0x80, /* Poll cmd on the high prio queue */
492 NPQ = 0x40, /* Poll cmd on the low prio queue */
493 FSWInt = 0x01, /* Forced software interrupt */
494
1da177e4 495 /* Cfg9346Bits */
07d3f51f
FR		 496 Cfg9346_Lock = 0x00,
497 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 498
499 /* rx_mode_bits */
07d3f51f
FR		 500 AcceptErr = 0x20,
501 AcceptRunt = 0x10,
502 AcceptBroadcast = 0x08,
503 AcceptMulticast = 0x04,
504 AcceptMyPhys = 0x02,
505 AcceptAllPhys = 0x01,
1687b566 506#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 507
1da177e4
LT		 508 /* TxConfigBits */
509 TxInterFrameGapShift = 24,
510 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
511
5d06a99f 512 /* Config1 register p.24 */
f162a5d1
FR		 513 LEDS1 = (1 << 7),
514 LEDS0 = (1 << 6),
f162a5d1
FR		 515 Speed_down = (1 << 4),
516 MEMMAP = (1 << 3),
517 IOMAP = (1 << 2),
518 VPD = (1 << 1),
5d06a99f
FR		 519 PMEnable = (1 << 0), /* Power Management Enable */
520
6dccd16b 521 /* Config2 register p. 25 */
2ca6cf06 522 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 523 PCI_Clock_66MHz = 0x01,
524 PCI_Clock_33MHz = 0x00,
525
61a4dcc2
FR		 526 /* Config3 register p.25 */
527 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
528 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 529 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 530 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 531
d58d46b5
FR		 532 /* Config4 register */
533 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
534
5d06a99f 535 /* Config5 register p.27 */
61a4dcc2
FR		 536 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
537 MWF = (1 << 5), /* Accept Multicast wakeup frame */
538 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 539 Spi_en = (1 << 3),
61a4dcc2 540 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 541 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
542
1da177e4
LT		 543 /* TBICSR p.28 */
544 TBIReset = 0x80000000,
545 TBILoopback = 0x40000000,
546 TBINwEnable = 0x20000000,
547 TBINwRestart = 0x10000000,
548 TBILinkOk = 0x02000000,
549 TBINwComplete = 0x01000000,
550
551 /* CPlusCmd p.31 */
f162a5d1
FR		 552 EnableBist = (1 << 15), // 8168 8101
553 Mac_dbgo_oe = (1 << 14), // 8168 8101
554 Normal_mode = (1 << 13), // unused
555 Force_half_dup = (1 << 12), // 8168 8101
556 Force_rxflow_en = (1 << 11), // 8168 8101
557 Force_txflow_en = (1 << 10), // 8168 8101
558 Cxpl_dbg_sel = (1 << 9), // 8168 8101
559 ASF = (1 << 8), // 8168 8101
560 PktCntrDisable = (1 << 7), // 8168 8101
561 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 562 RxVlan = (1 << 6),
563 RxChkSum = (1 << 5),
564 PCIDAC = (1 << 4),
565 PCIMulRW = (1 << 3),
0e485150
FR		 566 INTT_0 = 0x0000, // 8168
567 INTT_1 = 0x0001, // 8168
568 INTT_2 = 0x0002, // 8168
569 INTT_3 = 0x0003, // 8168
1da177e4
LT		 570
571 /* rtl8169_PHYstatus */
07d3f51f
FR		 572 TBI_Enable = 0x80,
573 TxFlowCtrl = 0x40,
574 RxFlowCtrl = 0x20,
575 _1000bpsF = 0x10,
576 _100bps = 0x08,
577 _10bps = 0x04,
578 LinkStatus = 0x02,
579 FullDup = 0x01,
1da177e4 580
1da177e4 581 /* _TBICSRBit */
07d3f51f 582 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 583
584 /* DumpCounterCommand */
07d3f51f 585 CounterDump = 0x8,
1da177e4
LT		 586};
587
2b7b4318
FR		 588enum rtl_desc_bit {
589 /* First doubleword. */
1da177e4
LT		 590 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
591 RingEnd = (1 << 30), /* End of descriptor ring */
592 FirstFrag = (1 << 29), /* First segment of a packet */
593 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 594};
595
596/* Generic case. */
597enum rtl_tx_desc_bit {
598 /* First doubleword. */
599 TD_LSO = (1 << 27), /* Large Send Offload */
600#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 601
2b7b4318
FR		 602 /* Second doubleword. */
603 TxVlanTag = (1 << 17), /* Add VLAN tag */
604};
605
606/* 8169, 8168b and 810x except 8102e. */
607enum rtl_tx_desc_bit_0 {
608 /* First doubleword. */
609#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
610 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
611 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
612 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
613};
614
615/* 8102e, 8168c and beyond. */
616enum rtl_tx_desc_bit_1 {
617 /* Second doubleword. */
618#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
619 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
620 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
621 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
622};
1da177e4 623
2b7b4318
FR		 624static const struct rtl_tx_desc_info {
625 struct {
626 u32 udp;
627 u32 tcp;
628 } checksum;
629 u16 mss_shift;
630 u16 opts_offset;
631} tx_desc_info [] = {
632 [RTL_TD_0] = {
633 .checksum = {
634 .udp = TD0_IP_CS | TD0_UDP_CS,
635 .tcp = TD0_IP_CS | TD0_TCP_CS
636 },
637 .mss_shift = TD0_MSS_SHIFT,
638 .opts_offset = 0
639 },
640 [RTL_TD_1] = {
641 .checksum = {
642 .udp = TD1_IP_CS | TD1_UDP_CS,
643 .tcp = TD1_IP_CS | TD1_TCP_CS
644 },
645 .mss_shift = TD1_MSS_SHIFT,
646 .opts_offset = 1
647 }
648};
649
650enum rtl_rx_desc_bit {
1da177e4
LT		 651 /* Rx private */
652 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
653 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
654
655#define RxProtoUDP (PID1)
656#define RxProtoTCP (PID0)
657#define RxProtoIP (PID1 | PID0)
658#define RxProtoMask RxProtoIP
659
660 IPFail = (1 << 16), /* IP checksum failed */
661 UDPFail = (1 << 15), /* UDP/IP checksum failed */
662 TCPFail = (1 << 14), /* TCP/IP checksum failed */
663 RxVlanTag = (1 << 16), /* VLAN tag available */
664};
665
666#define RsvdMask 0x3fffc000
667
668struct TxDesc {
6cccd6e7
REB		 669 __le32 opts1;
670 __le32 opts2;
671 __le64 addr;
1da177e4
LT		 672};
673
674struct RxDesc {
6cccd6e7
REB		 675 __le32 opts1;
676 __le32 opts2;
677 __le64 addr;
1da177e4
LT		 678};
679
680struct ring_info {
681 struct sk_buff *skb;
682 u32 len;
683 u8 __pad[sizeof(void *) - sizeof(u32)];
684};
685
f23e7fda 686enum features {
ccdffb9a
FR		 687 RTL_FEATURE_WOL = (1 << 0),
688 RTL_FEATURE_MSI = (1 << 1),
689 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 690};
691
355423d0
IV		 692struct rtl8169_counters {
693 __le64 tx_packets;
694 __le64 rx_packets;
695 __le64 tx_errors;
696 __le32 rx_errors;
697 __le16 rx_missed;
698 __le16 align_errors;
699 __le32 tx_one_collision;
700 __le32 tx_multi_collision;
701 __le64 rx_unicast;
702 __le64 rx_broadcast;
703 __le32 rx_multicast;
704 __le16 tx_aborted;
705 __le16 tx_underun;
706};
707
da78dbff 708enum rtl_flag {
6c4a70c5 709 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 710 RTL_FLAG_TASK_SLOW_PENDING,
711 RTL_FLAG_TASK_RESET_PENDING,
712 RTL_FLAG_TASK_PHY_PENDING,
713 RTL_FLAG_MAX
714};
715
8027aa24
JW		 716struct rtl8169_stats {
717 u64 packets;
718 u64 bytes;
719 struct u64_stats_sync syncp;
720};
721
1da177e4
LT		 722struct rtl8169_private {
723 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 724 struct pci_dev *pci_dev;
c4028958 725 struct net_device *dev;
bea3348e 726 struct napi_struct napi;
b57b7e5a 727 u32 msg_enable;
2b7b4318
FR		 728 u16 txd_version;
729 u16 mac_version;
1da177e4
LT		 730 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
731 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
732 u32 dirty_rx;
733 u32 dirty_tx;
8027aa24
JW		 734 struct rtl8169_stats rx_stats;
735 struct rtl8169_stats tx_stats;
1da177e4
LT		 736 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
737 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
738 dma_addr_t TxPhyAddr;
739 dma_addr_t RxPhyAddr;
6f0333b8 740 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 741 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 742 struct timer_list timer;
743 u16 cp_cmd;
da78dbff
FR		 744
745 u16 event_slow;
c0e45c1c 746
747 struct mdio_ops {
24192210
FR		 748 void (*write)(struct rtl8169_private *, int, int);
749 int (*read)(struct rtl8169_private *, int);
c0e45c1c 750 } mdio_ops;
751
065c27c1 752 struct pll_power_ops {
753 void (*down)(struct rtl8169_private *);
754 void (*up)(struct rtl8169_private *);
755 } pll_power_ops;
756
d58d46b5
FR		 757 struct jumbo_ops {
758 void (*enable)(struct rtl8169_private *);
759 void (*disable)(struct rtl8169_private *);
760 } jumbo_ops;
761
beb1fe18 762 struct csi_ops {
52989f0e
FR		 763 void (*write)(struct rtl8169_private *, int, int);
764 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 765 } csi_ops;
766
54405cde 767 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 768 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 769 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 770 void (*hw_start)(struct net_device *);
4da19633 771 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 772 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 773 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 774
775 struct {
da78dbff
FR		 776 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
777 struct mutex mutex;
4422bcd4
FR		 778 struct work_struct work;
779 } wk;
780
f23e7fda 781 unsigned features;
ccdffb9a
FR		 782
783 struct mii_if_info mii;
355423d0 784 struct rtl8169_counters counters;
e1759441 785 u32 saved_wolopts;
e03f33af 786 u32 opts1_mask;
f1e02ed1 787
b6ffd97f
FR		 788 struct rtl_fw {
789 const struct firmware *fw;
1c361efb
FR		 790
791#define RTL_VER_SIZE 32
792
793 char version[RTL_VER_SIZE];
794
795 struct rtl_fw_phy_action {
796 __le32 *code;
797 size_t size;
798 } phy_action;
b6ffd97f 799 } *rtl_fw;
497888cf 800#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 801
802 u32 ocp_base;
1da177e4
LT		 803};
804
979b6c13 805MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 806MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 807module_param(use_dac, int, 0);
4300e8c7 808MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 809module_param_named(debug, debug.msg_enable, int, 0);
810MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 811MODULE_LICENSE("GPL");
812MODULE_VERSION(RTL8169_VERSION);
bca03d5f 813MODULE_FIRMWARE(FIRMWARE_8168D_1);
814MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 815MODULE_FIRMWARE(FIRMWARE_8168E_1);
816MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 817MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 818MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 819MODULE_FIRMWARE(FIRMWARE_8168F_1);
820MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 821MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 822MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 823MODULE_FIRMWARE(FIRMWARE_8106E_1);
c558386b 824MODULE_FIRMWARE(FIRMWARE_8168G_1);
1da177e4 825
da78dbff
FR		 826static void rtl_lock_work(struct rtl8169_private *tp)
827{
828 mutex_lock(&tp->wk.mutex);
829}
830
831static void rtl_unlock_work(struct rtl8169_private *tp)
832{
833 mutex_unlock(&tp->wk.mutex);
834}
835
d58d46b5
FR		 836static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
837{
838 int cap = pci_pcie_cap(pdev);
839
840 if (cap) {
841 u16 ctl;
842
843 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
844 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
845 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
846 }
847}
848
ffc46952
FR		 849struct rtl_cond {
850 bool (*check)(struct rtl8169_private *);
851 const char *msg;
852};
853
854static void rtl_udelay(unsigned int d)
855{
856 udelay(d);
857}
858
859static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
860 void (*delay)(unsigned int), unsigned int d, int n,
861 bool high)
862{
863 int i;
864
865 for (i = 0; i < n; i++) {
866 delay(d);
867 if (c->check(tp) == high)
868 return true;
869 }
82e316ef
FR		 870 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
871 c->msg, !high, n, d);
ffc46952
FR		 872 return false;
873}
874
875static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
876 const struct rtl_cond *c,
877 unsigned int d, int n)
878{
879 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
880}
881
882static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
883 const struct rtl_cond *c,
884 unsigned int d, int n)
885{
886 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
887}
888
889static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
890 const struct rtl_cond *c,
891 unsigned int d, int n)
892{
893 return rtl_loop_wait(tp, c, msleep, d, n, true);
894}
895
896static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
897 const struct rtl_cond *c,
898 unsigned int d, int n)
899{
900 return rtl_loop_wait(tp, c, msleep, d, n, false);
901}
902
903#define DECLARE_RTL_COND(name) \
904static bool name ## _check(struct rtl8169_private *); \
905 \
906static const struct rtl_cond name = { \
907 .check = name ## _check, \
908 .msg = #name \
909}; \
910 \
911static bool name ## _check(struct rtl8169_private *tp)
912
913DECLARE_RTL_COND(rtl_ocpar_cond)
914{
915 void __iomem *ioaddr = tp->mmio_addr;
916
917 return RTL_R32(OCPAR) & OCPAR_FLAG;
918}
919
b646d900 920static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
921{
922 void __iomem *ioaddr = tp->mmio_addr;
b646d900 923
924 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 925
926 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
927 RTL_R32(OCPDR) : ~0;
b646d900 928}
929
930static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
931{
932 void __iomem *ioaddr = tp->mmio_addr;
b646d900 933
934 RTL_W32(OCPDR, data);
935 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 936
937 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
938}
939
940DECLARE_RTL_COND(rtl_eriar_cond)
941{
942 void __iomem *ioaddr = tp->mmio_addr;
943
944 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 945}
946
fac5b3ca 947static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 948{
fac5b3ca 949 void __iomem *ioaddr = tp->mmio_addr;
b646d900 950
951 RTL_W8(ERIDR, cmd);
952 RTL_W32(ERIAR, 0x800010e8);
953 msleep(2);
ffc46952
FR		 954
955 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
956 return;
b646d900 957
fac5b3ca 958 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 959}
960
961#define OOB_CMD_RESET 0x00
962#define OOB_CMD_DRIVER_START 0x05
963#define OOB_CMD_DRIVER_STOP 0x06
964
cecb5fd7
FR		 965static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
966{
967 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
968}
969
ffc46952 970DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 971{
cecb5fd7 972 u16 reg;
b646d900 973
cecb5fd7 974 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 975
ffc46952 976 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 977}
978
ffc46952 979static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 980{
ffc46952 981 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 982
ffc46952
FR		 983 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
984}
b646d900 985
ffc46952
FR		 986static void rtl8168_driver_stop(struct rtl8169_private *tp)
987{
988 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 989
ffc46952 990 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 991}
992
4804b3b3 993static int r8168dp_check_dash(struct rtl8169_private *tp)
994{
cecb5fd7 995 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 996
cecb5fd7 997 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 998}
b646d900 999
c558386b
HW		 1000static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1001{
1002 if (reg & 0xffff0001) {
1003 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1004 return true;
1005 }
1006 return false;
1007}
1008
1009DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1010{
1011 void __iomem *ioaddr = tp->mmio_addr;
1012
1013 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1014}
1015
1016static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1017{
1018 void __iomem *ioaddr = tp->mmio_addr;
1019
1020 if (rtl_ocp_reg_failure(tp, reg))
1021 return;
1022
1023 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1024
1025 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1026}
1027
1028static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1029{
1030 void __iomem *ioaddr = tp->mmio_addr;
1031
1032 if (rtl_ocp_reg_failure(tp, reg))
1033 return 0;
1034
1035 RTL_W32(GPHY_OCP, reg << 15);
1036
1037 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1038 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1039}
1040
1041static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
1042{
1043 int val;
1044
1045 val = r8168_phy_ocp_read(tp, reg);
1046 r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
1047}
1048
c558386b
HW		 1049static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1050{
1051 void __iomem *ioaddr = tp->mmio_addr;
1052
1053 if (rtl_ocp_reg_failure(tp, reg))
1054 return;
1055
1056 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1057}
1058
1059static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1060{
1061 void __iomem *ioaddr = tp->mmio_addr;
1062
1063 if (rtl_ocp_reg_failure(tp, reg))
1064 return 0;
1065
1066 RTL_W32(OCPDR, reg << 15);
1067
3a83ad12 1068 return RTL_R32(OCPDR);
c558386b
HW		 1069}
1070
1071#define OCP_STD_PHY_BASE 0xa400
1072
1073static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1074{
1075 if (reg == 0x1f) {
1076 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1077 return;
1078 }
1079
1080 if (tp->ocp_base != OCP_STD_PHY_BASE)
1081 reg -= 0x10;
1082
1083 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1084}
1085
1086static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1087{
1088 if (tp->ocp_base != OCP_STD_PHY_BASE)
1089 reg -= 0x10;
1090
1091 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1092}
1093
ffc46952
FR		 1094DECLARE_RTL_COND(rtl_phyar_cond)
1095{
1096 void __iomem *ioaddr = tp->mmio_addr;
1097
1098 return RTL_R32(PHYAR) & 0x80000000;
1099}
1100
24192210 1101static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1102{
24192210 1103 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1104
24192210 1105 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1106
ffc46952 1107 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1108 /*
81a95f04
TT		 1109 * According to hardware specs a 20us delay is required after write
1110 * complete indication, but before sending next command.
024a07ba 1111 */
81a95f04 1112 udelay(20);
1da177e4
LT		 1113}
1114
24192210 1115static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1116{
24192210 1117 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1118 int value;
1da177e4 1119
24192210 1120 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1121
ffc46952
FR		 1122 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1123 RTL_R32(PHYAR) & 0xffff : ~0;
1124
81a95f04
TT		 1125 /*
1126 * According to hardware specs a 20us delay is required after read
1127 * complete indication, but before sending next command.
1128 */
1129 udelay(20);
1130
1da177e4
LT		 1131 return value;
1132}
1133
24192210 1134static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1135{
24192210 1136 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1137
24192210 1138 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1139 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1140 RTL_W32(EPHY_RXER_NUM, 0);
1141
ffc46952 1142 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1143}
1144
24192210 1145static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1146{
24192210
FR		 1147 r8168dp_1_mdio_access(tp, reg,
1148 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1149}
1150
24192210 1151static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1152{
24192210 1153 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1154
24192210 1155 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1156
1157 mdelay(1);
1158 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1159 RTL_W32(EPHY_RXER_NUM, 0);
1160
ffc46952
FR		 1161 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1162 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1163}
1164
e6de30d6 1165#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1166
1167static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1168{
1169 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1170}
1171
1172static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1173{
1174 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1175}
1176
24192210 1177static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1178{
24192210
FR		 1179 void __iomem *ioaddr = tp->mmio_addr;
1180
e6de30d6 1181 r8168dp_2_mdio_start(ioaddr);
1182
24192210 1183 r8169_mdio_write(tp, reg, value);
e6de30d6 1184
1185 r8168dp_2_mdio_stop(ioaddr);
1186}
1187
24192210 1188static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1189{
24192210 1190 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1191 int value;
1192
1193 r8168dp_2_mdio_start(ioaddr);
1194
24192210 1195 value = r8169_mdio_read(tp, reg);
e6de30d6 1196
1197 r8168dp_2_mdio_stop(ioaddr);
1198
1199 return value;
1200}
1201
4da19633 1202static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1203{
24192210 1204 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1205}
1206
4da19633 1207static int rtl_readphy(struct rtl8169_private *tp, int location)
1208{
24192210 1209 return tp->mdio_ops.read(tp, location);
4da19633 1210}
1211
1212static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1213{
1214 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1215}
1216
1217static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1218{
1219 int val;
1220
4da19633 1221 val = rtl_readphy(tp, reg_addr);
1222 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1223}
1224
ccdffb9a
FR		 1225static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1226 int val)
1227{
1228 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1229
4da19633 1230 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1231}
1232
1233static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1234{
1235 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1236
4da19633 1237 return rtl_readphy(tp, location);
ccdffb9a
FR		 1238}
1239
ffc46952
FR		 1240DECLARE_RTL_COND(rtl_ephyar_cond)
1241{
1242 void __iomem *ioaddr = tp->mmio_addr;
1243
1244 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1245}
1246
fdf6fc06 1247static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1248{
fdf6fc06 1249 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1250
1251 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1252 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1253
ffc46952
FR		 1254 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1255
1256 udelay(10);
dacf8154
FR		 1257}
1258
fdf6fc06 1259static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1260{
fdf6fc06 1261 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1262
1263 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1264
ffc46952
FR		 1265 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1266 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1267}
1268
fdf6fc06
FR		 1269static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1270 u32 val, int type)
133ac40a 1271{
fdf6fc06 1272 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1273
1274 BUG_ON((addr & 3) || (mask == 0));
1275 RTL_W32(ERIDR, val);
1276 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1277
ffc46952 1278 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1279}
1280
fdf6fc06 1281static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1282{
fdf6fc06 1283 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1284
1285 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1286
ffc46952
FR		 1287 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1288 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1289}
1290
fdf6fc06
FR		 1291static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1292 u32 m, int type)
133ac40a
HW		 1293{
1294 u32 val;
1295
fdf6fc06
FR		 1296 val = rtl_eri_read(tp, addr, type);
1297 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1298}
1299
c28aa385 1300struct exgmac_reg {
1301 u16 addr;
1302 u16 mask;
1303 u32 val;
1304};
1305
fdf6fc06 1306static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1307 const struct exgmac_reg *r, int len)
1308{
1309 while (len-- > 0) {
fdf6fc06 1310 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1311 r++;
1312 }
1313}
1314
ffc46952
FR		 1315DECLARE_RTL_COND(rtl_efusear_cond)
1316{
1317 void __iomem *ioaddr = tp->mmio_addr;
1318
1319 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1320}
1321
fdf6fc06 1322static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1323{
fdf6fc06 1324 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1325
1326 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1327
ffc46952
FR		 1328 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1329 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1330}
1331
9085cdfa
FR		 1332static u16 rtl_get_events(struct rtl8169_private *tp)
1333{
1334 void __iomem *ioaddr = tp->mmio_addr;
1335
1336 return RTL_R16(IntrStatus);
1337}
1338
1339static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1340{
1341 void __iomem *ioaddr = tp->mmio_addr;
1342
1343 RTL_W16(IntrStatus, bits);
1344 mmiowb();
1345}
1346
1347static void rtl_irq_disable(struct rtl8169_private *tp)
1348{
1349 void __iomem *ioaddr = tp->mmio_addr;
1350
1351 RTL_W16(IntrMask, 0);
1352 mmiowb();
1353}
1354
3e990ff5
FR		 1355static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1356{
1357 void __iomem *ioaddr = tp->mmio_addr;
1358
1359 RTL_W16(IntrMask, bits);
1360}
1361
da78dbff
FR		 1362#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1363#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1364#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1365
1366static void rtl_irq_enable_all(struct rtl8169_private *tp)
1367{
1368 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1369}
1370
811fd301 1371static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1372{
811fd301 1373 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1374
9085cdfa 1375 rtl_irq_disable(tp);
da78dbff 1376 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1377 RTL_R8(ChipCmd);
1da177e4
LT		 1378}
1379
4da19633 1380static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1381{
4da19633 1382 void __iomem *ioaddr = tp->mmio_addr;
1383
1da177e4
LT		 1384 return RTL_R32(TBICSR) & TBIReset;
1385}
1386
4da19633 1387static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1388{
4da19633 1389 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1390}
1391
1392static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1393{
1394 return RTL_R32(TBICSR) & TBILinkOk;
1395}
1396
1397static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1398{
1399 return RTL_R8(PHYstatus) & LinkStatus;
1400}
1401
4da19633 1402static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1403{
4da19633 1404 void __iomem *ioaddr = tp->mmio_addr;
1405
1da177e4
LT		 1406 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1407}
1408
4da19633 1409static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1410{
1411 unsigned int val;
1412
4da19633 1413 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1414 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1415}
1416
70090424
HW		 1417static void rtl_link_chg_patch(struct rtl8169_private *tp)
1418{
1419 void __iomem *ioaddr = tp->mmio_addr;
1420 struct net_device *dev = tp->dev;
1421
1422 if (!netif_running(dev))
1423 return;
1424
b3d7b2f2
HW		 1425 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1426 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1427 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1428 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1429 ERIAR_EXGMAC);
1430 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1431 ERIAR_EXGMAC);
70090424 1432 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1433 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1434 ERIAR_EXGMAC);
1435 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1436 ERIAR_EXGMAC);
70090424 1437 } else {
fdf6fc06
FR		 1438 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1439 ERIAR_EXGMAC);
1440 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1441 ERIAR_EXGMAC);
70090424
HW		 1442 }
1443 /* Reset packet filter */
fdf6fc06 1444 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1445 ERIAR_EXGMAC);
fdf6fc06 1446 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1447 ERIAR_EXGMAC);
c2218925
HW		 1448 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1449 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1450 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1451 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1452 ERIAR_EXGMAC);
1453 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1454 ERIAR_EXGMAC);
c2218925 1455 } else {
fdf6fc06
FR		 1456 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1457 ERIAR_EXGMAC);
1458 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1459 ERIAR_EXGMAC);
c2218925 1460 }
7e18dca1
HW		 1461 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1462 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1463 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1464 ERIAR_EXGMAC);
1465 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1466 ERIAR_EXGMAC);
7e18dca1 1467 } else {
fdf6fc06
FR		 1468 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1469 ERIAR_EXGMAC);
7e18dca1 1470 }
70090424
HW		 1471 }
1472}
1473
e4fbce74 1474static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1475 struct rtl8169_private *tp,
1476 void __iomem *ioaddr, bool pm)
1da177e4 1477{
1da177e4 1478 if (tp->link_ok(ioaddr)) {
70090424 1479 rtl_link_chg_patch(tp);
e1759441 1480 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1481 if (pm)
1482 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1483 netif_carrier_on(dev);
1519e57f
FR		 1484 if (net_ratelimit())
1485 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1486 } else {
1da177e4 1487 netif_carrier_off(dev);
bf82c189 1488 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1489 if (pm)
10953db8 1490 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1491 }
1da177e4
LT		 1492}
1493
e4fbce74
RW		 1494static void rtl8169_check_link_status(struct net_device *dev,
1495 struct rtl8169_private *tp,
1496 void __iomem *ioaddr)
1497{
1498 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1499}
1500
e1759441
RW		 1501#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1502
1503static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1504{
61a4dcc2
FR		 1505 void __iomem *ioaddr = tp->mmio_addr;
1506 u8 options;
e1759441 1507 u32 wolopts = 0;
61a4dcc2
FR		 1508
1509 options = RTL_R8(Config1);
1510 if (!(options & PMEnable))
e1759441 1511 return 0;
61a4dcc2
FR		 1512
1513 options = RTL_R8(Config3);
1514 if (options & LinkUp)
e1759441 1515 wolopts |= WAKE_PHY;
61a4dcc2 1516 if (options & MagicPacket)
e1759441 1517 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1518
1519 options = RTL_R8(Config5);
1520 if (options & UWF)
e1759441 1521 wolopts |= WAKE_UCAST;
61a4dcc2 1522 if (options & BWF)
e1759441 1523 wolopts |= WAKE_BCAST;
61a4dcc2 1524 if (options & MWF)
e1759441 1525 wolopts |= WAKE_MCAST;
61a4dcc2 1526
e1759441 1527 return wolopts;
61a4dcc2
FR		 1528}
1529
e1759441 1530static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1531{
1532 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1533
da78dbff 1534 rtl_lock_work(tp);
e1759441
RW		 1535
1536 wol->supported = WAKE_ANY;
1537 wol->wolopts = __rtl8169_get_wol(tp);
1538
da78dbff 1539 rtl_unlock_work(tp);
e1759441
RW		 1540}
1541
1542static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1543{
61a4dcc2 1544 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1545 unsigned int i;
350f7596 1546 static const struct {
61a4dcc2
FR		 1547 u32 opt;
1548 u16 reg;
1549 u8 mask;
1550 } cfg[] = {
61a4dcc2
FR		 1551 { WAKE_PHY, Config3, LinkUp },
1552 { WAKE_MAGIC, Config3, MagicPacket },
1553 { WAKE_UCAST, Config5, UWF },
1554 { WAKE_BCAST, Config5, BWF },
1555 { WAKE_MCAST, Config5, MWF },
1556 { WAKE_ANY, Config5, LanWake }
1557 };
851e6022 1558 u8 options;
61a4dcc2 1559
61a4dcc2
FR		 1560 RTL_W8(Cfg9346, Cfg9346_Unlock);
1561
1562 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1563 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1564 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1565 options |= cfg[i].mask;
1566 RTL_W8(cfg[i].reg, options);
1567 }
1568
851e6022
FR		 1569 switch (tp->mac_version) {
1570 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1571 options = RTL_R8(Config1) & ~PMEnable;
1572 if (wolopts)
1573 options |= PMEnable;
1574 RTL_W8(Config1, options);
1575 break;
1576 default:
d387b427
FR		 1577 options = RTL_R8(Config2) & ~PME_SIGNAL;
1578 if (wolopts)
1579 options |= PME_SIGNAL;
1580 RTL_W8(Config2, options);
851e6022
FR		 1581 break;
1582 }
1583
61a4dcc2 1584 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1585}
1586
1587static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1588{
1589 struct rtl8169_private *tp = netdev_priv(dev);
1590
da78dbff 1591 rtl_lock_work(tp);
61a4dcc2 1592
f23e7fda
FR		 1593 if (wol->wolopts)
1594 tp->features |= RTL_FEATURE_WOL;
1595 else
1596 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1597 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1598
1599 rtl_unlock_work(tp);
61a4dcc2 1600
ea80907f 1601 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1602
61a4dcc2
FR		 1603 return 0;
1604}
1605
31bd204f
FR		 1606static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1607{
85bffe6c 1608 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1609}
1610
1da177e4
LT		 1611static void rtl8169_get_drvinfo(struct net_device *dev,
1612 struct ethtool_drvinfo *info)
1613{
1614 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1615 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1616
68aad78c
RJ		 1617 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1618 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1619 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1620 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1621 if (!IS_ERR_OR_NULL(rtl_fw))
1622 strlcpy(info->fw_version, rtl_fw->version,
1623 sizeof(info->fw_version));
1da177e4
LT		 1624}
1625
1626static int rtl8169_get_regs_len(struct net_device *dev)
1627{
1628 return R8169_REGS_SIZE;
1629}
1630
1631static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1632 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1633{
1634 struct rtl8169_private *tp = netdev_priv(dev);
1635 void __iomem *ioaddr = tp->mmio_addr;
1636 int ret = 0;
1637 u32 reg;
1638
1639 reg = RTL_R32(TBICSR);
1640 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1641 (duplex == DUPLEX_FULL)) {
1642 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1643 } else if (autoneg == AUTONEG_ENABLE)
1644 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1645 else {
bf82c189
JP		 1646 netif_warn(tp, link, dev,
1647 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1648 ret = -EOPNOTSUPP;
1649 }
1650
1651 return ret;
1652}
1653
1654static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1655 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1656{
1657 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1658 int giga_ctrl, bmcr;
54405cde 1659 int rc = -EINVAL;
1da177e4 1660
716b50a3 1661 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1662
1663 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1664 int auto_nego;
1665
4da19633 1666 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1667 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1668 ADVERTISE_100HALF | ADVERTISE_100FULL);
1669
1670 if (adv & ADVERTISED_10baseT_Half)
1671 auto_nego |= ADVERTISE_10HALF;
1672 if (adv & ADVERTISED_10baseT_Full)
1673 auto_nego |= ADVERTISE_10FULL;
1674 if (adv & ADVERTISED_100baseT_Half)
1675 auto_nego |= ADVERTISE_100HALF;
1676 if (adv & ADVERTISED_100baseT_Full)
1677 auto_nego |= ADVERTISE_100FULL;
1678
3577aa1b 1679 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1680
4da19633 1681 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1682 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1683
3577aa1b 1684 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1685 if (tp->mii.supports_gmii) {
54405cde
ON		 1686 if (adv & ADVERTISED_1000baseT_Half)
1687 giga_ctrl |= ADVERTISE_1000HALF;
1688 if (adv & ADVERTISED_1000baseT_Full)
1689 giga_ctrl |= ADVERTISE_1000FULL;
1690 } else if (adv & (ADVERTISED_1000baseT_Half |
1691 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1692 netif_info(tp, link, dev,
1693 "PHY does not support 1000Mbps\n");
54405cde 1694 goto out;
bcf0bf90 1695 }
1da177e4 1696
3577aa1b 1697 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1698
4da19633 1699 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1700 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1701 } else {
1702 giga_ctrl = 0;
1703
1704 if (speed == SPEED_10)
1705 bmcr = 0;
1706 else if (speed == SPEED_100)
1707 bmcr = BMCR_SPEED100;
1708 else
54405cde 1709 goto out;
3577aa1b 1710
1711 if (duplex == DUPLEX_FULL)
1712 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1713 }
1714
4da19633 1715 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1716
cecb5fd7
FR		 1717 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1718 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1719 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1720 rtl_writephy(tp, 0x17, 0x2138);
1721 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1722 } else {
4da19633 1723 rtl_writephy(tp, 0x17, 0x2108);
1724 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1725 }
1726 }
1727
54405cde
ON		 1728 rc = 0;
1729out:
1730 return rc;
1da177e4
LT		 1731}
1732
1733static int rtl8169_set_speed(struct net_device *dev,
54405cde 1734 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1735{
1736 struct rtl8169_private *tp = netdev_priv(dev);
1737 int ret;
1738
54405cde 1739 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1740 if (ret < 0)
1741 goto out;
1da177e4 1742
4876cc1e
FR		 1743 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1744 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1745 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1746 }
1747out:
1da177e4
LT		 1748 return ret;
1749}
1750
1751static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1752{
1753 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1754 int ret;
1755
4876cc1e
FR		 1756 del_timer_sync(&tp->timer);
1757
da78dbff 1758 rtl_lock_work(tp);
cecb5fd7 1759 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1760 cmd->duplex, cmd->advertising);
da78dbff 1761 rtl_unlock_work(tp);
5b0384f4 1762
1da177e4
LT		 1763 return ret;
1764}
1765
c8f44aff
MM		 1766static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1767 netdev_features_t features)
1da177e4 1768{
d58d46b5
FR		 1769 struct rtl8169_private *tp = netdev_priv(dev);
1770
2b7b4318 1771 if (dev->mtu > TD_MSS_MAX)
350fb32a 1772 features &= ~NETIF_F_ALL_TSO;
1da177e4 1773
d58d46b5
FR		 1774 if (dev->mtu > JUMBO_1K &&
1775 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1776 features &= ~NETIF_F_IP_CSUM;
1777
350fb32a 1778 return features;
1da177e4
LT		 1779}
1780
da78dbff
FR		 1781static void __rtl8169_set_features(struct net_device *dev,
1782 netdev_features_t features)
1da177e4
LT		 1783{
1784 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1785 netdev_features_t changed = features ^ dev->features;
da78dbff 1786 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1787
6bbe021d
BG		 1788 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1789 return;
1da177e4 1790
6bbe021d
BG		 1791 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1792 if (features & NETIF_F_RXCSUM)
1793 tp->cp_cmd |= RxChkSum;
1794 else
1795 tp->cp_cmd &= ~RxChkSum;
350fb32a 1796
6bbe021d
BG		 1797 if (dev->features & NETIF_F_HW_VLAN_RX)
1798 tp->cp_cmd |= RxVlan;
1799 else
1800 tp->cp_cmd &= ~RxVlan;
1801
1802 RTL_W16(CPlusCmd, tp->cp_cmd);
1803 RTL_R16(CPlusCmd);
1804 }
1805 if (changed & NETIF_F_RXALL) {
1806 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1807 if (features & NETIF_F_RXALL)
1808 tmp |= (AcceptErr | AcceptRunt);
1809 RTL_W32(RxConfig, tmp);
1810 }
da78dbff 1811}
1da177e4 1812
da78dbff
FR		 1813static int rtl8169_set_features(struct net_device *dev,
1814 netdev_features_t features)
1815{
1816 struct rtl8169_private *tp = netdev_priv(dev);
1817
1818 rtl_lock_work(tp);
1819 __rtl8169_set_features(dev, features);
1820 rtl_unlock_work(tp);
1da177e4
LT		 1821
1822 return 0;
1823}
1824
da78dbff 1825
1da177e4
LT		 1826static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1827 struct sk_buff *skb)
1828{
eab6d18d 1829 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1830 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1831}
1832
7a8fc77b 1833static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1834{
1835 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1836
7a8fc77b
FR		 1837 if (opts2 & RxVlanTag)
1838 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1839
1da177e4 1840 desc->opts2 = 0;
1da177e4
LT		 1841}
1842
ccdffb9a 1843static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1844{
1845 struct rtl8169_private *tp = netdev_priv(dev);
1846 void __iomem *ioaddr = tp->mmio_addr;
1847 u32 status;
1848
1849 cmd->supported =
1850 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1851 cmd->port = PORT_FIBRE;
1852 cmd->transceiver = XCVR_INTERNAL;
1853
1854 status = RTL_R32(TBICSR);
1855 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1856 cmd->autoneg = !!(status & TBINwEnable);
1857
70739497 1858 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1859 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1860
1861 return 0;
1da177e4
LT		 1862}
1863
ccdffb9a 1864static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1865{
1866 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1867
1868 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1869}
1870
1871static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1872{
1873 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1874 int rc;
1da177e4 1875
da78dbff 1876 rtl_lock_work(tp);
ccdffb9a 1877 rc = tp->get_settings(dev, cmd);
da78dbff 1878 rtl_unlock_work(tp);
1da177e4 1879
ccdffb9a 1880 return rc;
1da177e4
LT		 1881}
1882
1883static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1884 void *p)
1885{
5b0384f4 1886 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1887
5b0384f4
FR		 1888 if (regs->len > R8169_REGS_SIZE)
1889 regs->len = R8169_REGS_SIZE;
1da177e4 1890
da78dbff 1891 rtl_lock_work(tp);
5b0384f4 1892 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1893 rtl_unlock_work(tp);
1da177e4
LT		 1894}
1895
b57b7e5a
SH		 1896static u32 rtl8169_get_msglevel(struct net_device *dev)
1897{
1898 struct rtl8169_private *tp = netdev_priv(dev);
1899
1900 return tp->msg_enable;
1901}
1902
1903static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1904{
1905 struct rtl8169_private *tp = netdev_priv(dev);
1906
1907 tp->msg_enable = value;
1908}
1909
d4a3a0fc
SH		 1910static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1911 "tx_packets",
1912 "rx_packets",
1913 "tx_errors",
1914 "rx_errors",
1915 "rx_missed",
1916 "align_errors",
1917 "tx_single_collisions",
1918 "tx_multi_collisions",
1919 "unicast",
1920 "broadcast",
1921 "multicast",
1922 "tx_aborted",
1923 "tx_underrun",
1924};
1925
b9f2c044 1926static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1927{
b9f2c044
JG		 1928 switch (sset) {
1929 case ETH_SS_STATS:
1930 return ARRAY_SIZE(rtl8169_gstrings);
1931 default:
1932 return -EOPNOTSUPP;
1933 }
d4a3a0fc
SH		 1934}
1935
ffc46952
FR		 1936DECLARE_RTL_COND(rtl_counters_cond)
1937{
1938 void __iomem *ioaddr = tp->mmio_addr;
1939
1940 return RTL_R32(CounterAddrLow) & CounterDump;
1941}
1942
355423d0 1943static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1944{
1945 struct rtl8169_private *tp = netdev_priv(dev);
1946 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1947 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1948 struct rtl8169_counters *counters;
1949 dma_addr_t paddr;
1950 u32 cmd;
1951
355423d0
IV		 1952 /*
1953 * Some chips are unable to dump tally counters when the receiver
1954 * is disabled.
1955 */
1956 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1957 return;
d4a3a0fc 1958
48addcc9 1959 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1960 if (!counters)
1961 return;
1962
1963 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1964 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1965 RTL_W32(CounterAddrLow, cmd);
1966 RTL_W32(CounterAddrLow, cmd | CounterDump);
1967
ffc46952
FR		 1968 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1969 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1970
1971 RTL_W32(CounterAddrLow, 0);
1972 RTL_W32(CounterAddrHigh, 0);
1973
48addcc9 1974 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1975}
1976
355423d0
IV		 1977static void rtl8169_get_ethtool_stats(struct net_device *dev,
1978 struct ethtool_stats *stats, u64 *data)
1979{
1980 struct rtl8169_private *tp = netdev_priv(dev);
1981
1982 ASSERT_RTNL();
1983
1984 rtl8169_update_counters(dev);
1985
1986 data[0] = le64_to_cpu(tp->counters.tx_packets);
1987 data[1] = le64_to_cpu(tp->counters.rx_packets);
1988 data[2] = le64_to_cpu(tp->counters.tx_errors);
1989 data[3] = le32_to_cpu(tp->counters.rx_errors);
1990 data[4] = le16_to_cpu(tp->counters.rx_missed);
1991 data[5] = le16_to_cpu(tp->counters.align_errors);
1992 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1993 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1994 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1995 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1996 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1997 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1998 data[12] = le16_to_cpu(tp->counters.tx_underun);
1999}
2000
d4a3a0fc
SH		 2001static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2002{
2003 switch(stringset) {
2004 case ETH_SS_STATS:
2005 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2006 break;
2007 }
2008}
2009
7282d491 2010static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2011 .get_drvinfo = rtl8169_get_drvinfo,
2012 .get_regs_len = rtl8169_get_regs_len,
2013 .get_link = ethtool_op_get_link,
2014 .get_settings = rtl8169_get_settings,
2015 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2016 .get_msglevel = rtl8169_get_msglevel,
2017 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2018 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2019 .get_wol = rtl8169_get_wol,
2020 .set_wol = rtl8169_set_wol,
d4a3a0fc 2021 .get_strings = rtl8169_get_strings,
b9f2c044 2022 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2023 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2024 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2025};
2026
07d3f51f 2027static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2028 struct net_device *dev, u8 default_version)
1da177e4 2029{
5d320a20 2030 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2031 /*
2032 * The driver currently handles the 8168Bf and the 8168Be identically
2033 * but they can be identified more specifically through the test below
2034 * if needed:
2035 *
2036 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2037 *
2038 * Same thing for the 8101Eb and the 8101Ec:
2039 *
2040 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2041 */
3744100e 2042 static const struct rtl_mac_info {
1da177e4 2043 u32 mask;
e3cf0cc0 2044 u32 val;
1da177e4
LT		 2045 int mac_version;
2046 } mac_info[] = {
c558386b
HW		 2047 /* 8168G family. */
2048 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2049 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2050
c2218925 2051 /* 8168F family. */
b3d7b2f2 2052 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2053 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2054 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2055
01dc7fec 2056 /* 8168E family. */
70090424 2057 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2058 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2059 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2060 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2061
5b538df9 2062 /* 8168D family. */
daf9df6d 2063 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2064 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2065 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2066
e6de30d6 2067 /* 8168DP family. */
2068 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2069 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2070 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2071
ef808d50 2072 /* 8168C family. */
17c99297 2073 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2074 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2075 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2076 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2077 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2078 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2079 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2080 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2081 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2082
2083 /* 8168B family. */
2084 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2085 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2086 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2087 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2088
2089 /* 8101 family. */
5598bfe5
HW		 2090 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2091 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2092 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2093 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2094 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2095 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2096 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2097 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2098 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2099 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2100 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2101 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2102 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2103 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2104 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2105 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2106 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2107 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2108 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2109 /* FIXME: where did these entries come from ? -- FR */
2110 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2111 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2112
2113 /* 8110 family. */
2114 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2115 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2116 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2117 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2118 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2119 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2120
f21b75e9
JD		 2121 /* Catch-all */
2122 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2123 };
2124 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2125 u32 reg;
2126
e3cf0cc0
FR		 2127 reg = RTL_R32(TxConfig);
2128 while ((reg & p->mask) != p->val)
1da177e4
LT		 2129 p++;
2130 tp->mac_version = p->mac_version;
5d320a20
FR		 2131
2132 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2133 netif_notice(tp, probe, dev,
2134 "unknown MAC, using family default\n");
2135 tp->mac_version = default_version;
2136 }
1da177e4
LT		 2137}
2138
2139static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2140{
bcf0bf90 2141 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2142}
2143
867763c1
FR		 2144struct phy_reg {
2145 u16 reg;
2146 u16 val;
2147};
2148
4da19633 2149static void rtl_writephy_batch(struct rtl8169_private *tp,
2150 const struct phy_reg *regs, int len)
867763c1
FR		 2151{
2152 while (len-- > 0) {
4da19633 2153 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2154 regs++;
2155 }
2156}
2157
bca03d5f 2158#define PHY_READ 0x00000000
2159#define PHY_DATA_OR 0x10000000
2160#define PHY_DATA_AND 0x20000000
2161#define PHY_BJMPN 0x30000000
2162#define PHY_READ_EFUSE 0x40000000
2163#define PHY_READ_MAC_BYTE 0x50000000
2164#define PHY_WRITE_MAC_BYTE 0x60000000
2165#define PHY_CLEAR_READCOUNT 0x70000000
2166#define PHY_WRITE 0x80000000
2167#define PHY_READCOUNT_EQ_SKIP 0x90000000
2168#define PHY_COMP_EQ_SKIPN 0xa0000000
2169#define PHY_COMP_NEQ_SKIPN 0xb0000000
2170#define PHY_WRITE_PREVIOUS 0xc0000000
2171#define PHY_SKIPN 0xd0000000
2172#define PHY_DELAY_MS 0xe0000000
2173#define PHY_WRITE_ERI_WORD 0xf0000000
2174
960aee6c
HW		 2175struct fw_info {
2176 u32 magic;
2177 char version[RTL_VER_SIZE];
2178 __le32 fw_start;
2179 __le32 fw_len;
2180 u8 chksum;
2181} __packed;
2182
1c361efb
FR		 2183#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2184
2185static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2186{
b6ffd97f 2187 const struct firmware *fw = rtl_fw->fw;
960aee6c 2188 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2189 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2190 char *version = rtl_fw->version;
2191 bool rc = false;
2192
2193 if (fw->size < FW_OPCODE_SIZE)
2194 goto out;
960aee6c
HW		 2195
2196 if (!fw_info->magic) {
2197 size_t i, size, start;
2198 u8 checksum = 0;
2199
2200 if (fw->size < sizeof(*fw_info))
2201 goto out;
2202
2203 for (i = 0; i < fw->size; i++)
2204 checksum += fw->data[i];
2205 if (checksum != 0)
2206 goto out;
2207
2208 start = le32_to_cpu(fw_info->fw_start);
2209 if (start > fw->size)
2210 goto out;
2211
2212 size = le32_to_cpu(fw_info->fw_len);
2213 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2214 goto out;
2215
2216 memcpy(version, fw_info->version, RTL_VER_SIZE);
2217
2218 pa->code = (__le32 *)(fw->data + start);
2219 pa->size = size;
2220 } else {
1c361efb
FR		 2221 if (fw->size % FW_OPCODE_SIZE)
2222 goto out;
2223
2224 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2225
2226 pa->code = (__le32 *)fw->data;
2227 pa->size = fw->size / FW_OPCODE_SIZE;
2228 }
2229 version[RTL_VER_SIZE - 1] = 0;
2230
2231 rc = true;
2232out:
2233 return rc;
2234}
2235
fd112f2e
FR		 2236static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2237 struct rtl_fw_phy_action *pa)
1c361efb 2238{
fd112f2e 2239 bool rc = false;
1c361efb 2240 size_t index;
bca03d5f 2241
1c361efb
FR		 2242 for (index = 0; index < pa->size; index++) {
2243 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2244 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2245
42b82dc1 2246 switch(action & 0xf0000000) {
2247 case PHY_READ:
2248 case PHY_DATA_OR:
2249 case PHY_DATA_AND:
2250 case PHY_READ_EFUSE:
2251 case PHY_CLEAR_READCOUNT:
2252 case PHY_WRITE:
2253 case PHY_WRITE_PREVIOUS:
2254 case PHY_DELAY_MS:
2255 break;
2256
2257 case PHY_BJMPN:
2258 if (regno > index) {
fd112f2e 2259 netif_err(tp, ifup, tp->dev,
cecb5fd7 2260 "Out of range of firmware\n");
fd112f2e 2261 goto out;
42b82dc1 2262 }
2263 break;
2264 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2265 if (index + 2 >= pa->size) {
fd112f2e 2266 netif_err(tp, ifup, tp->dev,
cecb5fd7 2267 "Out of range of firmware\n");
fd112f2e 2268 goto out;
42b82dc1 2269 }
2270 break;
2271 case PHY_COMP_EQ_SKIPN:
2272 case PHY_COMP_NEQ_SKIPN:
2273 case PHY_SKIPN:
1c361efb 2274 if (index + 1 + regno >= pa->size) {
fd112f2e 2275 netif_err(tp, ifup, tp->dev,
cecb5fd7 2276 "Out of range of firmware\n");
fd112f2e 2277 goto out;
42b82dc1 2278 }
bca03d5f 2279 break;
2280
42b82dc1 2281 case PHY_READ_MAC_BYTE:
2282 case PHY_WRITE_MAC_BYTE:
2283 case PHY_WRITE_ERI_WORD:
2284 default:
fd112f2e 2285 netif_err(tp, ifup, tp->dev,
42b82dc1 2286 "Invalid action 0x%08x\n", action);
fd112f2e 2287 goto out;
bca03d5f 2288 }
2289 }
fd112f2e
FR		 2290 rc = true;
2291out:
2292 return rc;
2293}
bca03d5f 2294
fd112f2e
FR		 2295static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2296{
2297 struct net_device *dev = tp->dev;
2298 int rc = -EINVAL;
2299
2300 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2301 netif_err(tp, ifup, dev, "invalid firwmare\n");
2302 goto out;
2303 }
2304
2305 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2306 rc = 0;
2307out:
2308 return rc;
2309}
2310
2311static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2312{
2313 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2314 u32 predata, count;
2315 size_t index;
2316
2317 predata = count = 0;
42b82dc1 2318
1c361efb
FR		 2319 for (index = 0; index < pa->size; ) {
2320 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2321 u32 data = action & 0x0000ffff;
42b82dc1 2322 u32 regno = (action & 0x0fff0000) >> 16;
2323
2324 if (!action)
2325 break;
bca03d5f 2326
2327 switch(action & 0xf0000000) {
42b82dc1 2328 case PHY_READ:
2329 predata = rtl_readphy(tp, regno);
2330 count++;
2331 index++;
2332 break;
2333 case PHY_DATA_OR:
2334 predata |= data;
2335 index++;
2336 break;
2337 case PHY_DATA_AND:
2338 predata &= data;
2339 index++;
2340 break;
2341 case PHY_BJMPN:
2342 index -= regno;
2343 break;
2344 case PHY_READ_EFUSE:
fdf6fc06 2345 predata = rtl8168d_efuse_read(tp, regno);
42b82dc1 2346 index++;
2347 break;
2348 case PHY_CLEAR_READCOUNT:
2349 count = 0;
2350 index++;
2351 break;
bca03d5f 2352 case PHY_WRITE:
42b82dc1 2353 rtl_writephy(tp, regno, data);
2354 index++;
2355 break;
2356 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2357 index += (count == data) ? 2 : 1;
bca03d5f 2358 break;
42b82dc1 2359 case PHY_COMP_EQ_SKIPN:
2360 if (predata == data)
2361 index += regno;
2362 index++;
2363 break;
2364 case PHY_COMP_NEQ_SKIPN:
2365 if (predata != data)
2366 index += regno;
2367 index++;
2368 break;
2369 case PHY_WRITE_PREVIOUS:
2370 rtl_writephy(tp, regno, predata);
2371 index++;
2372 break;
2373 case PHY_SKIPN:
2374 index += regno + 1;
2375 break;
2376 case PHY_DELAY_MS:
2377 mdelay(data);
2378 index++;
2379 break;
2380
2381 case PHY_READ_MAC_BYTE:
2382 case PHY_WRITE_MAC_BYTE:
2383 case PHY_WRITE_ERI_WORD:
bca03d5f 2384 default:
2385 BUG();
2386 }
2387 }
2388}
2389
f1e02ed1 2390static void rtl_release_firmware(struct rtl8169_private *tp)
2391{
b6ffd97f
FR		 2392 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2393 release_firmware(tp->rtl_fw->fw);
2394 kfree(tp->rtl_fw);
2395 }
2396 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2397}
2398
953a12cc 2399static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2400{
b6ffd97f 2401 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2402
2403 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2404 if (!IS_ERR_OR_NULL(rtl_fw))
2405 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2406}
2407
2408static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2409{
2410 if (rtl_readphy(tp, reg) != val)
2411 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2412 else
2413 rtl_apply_firmware(tp);
f1e02ed1 2414}
2415
4da19633 2416static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2417{
350f7596 2418 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2419 { 0x1f, 0x0001 },
2420 { 0x06, 0x006e },
2421 { 0x08, 0x0708 },
2422 { 0x15, 0x4000 },
2423 { 0x18, 0x65c7 },
1da177e4 2424
0b9b571d 2425 { 0x1f, 0x0001 },
2426 { 0x03, 0x00a1 },
2427 { 0x02, 0x0008 },
2428 { 0x01, 0x0120 },
2429 { 0x00, 0x1000 },
2430 { 0x04, 0x0800 },
2431 { 0x04, 0x0000 },
1da177e4 2432
0b9b571d 2433 { 0x03, 0xff41 },
2434 { 0x02, 0xdf60 },
2435 { 0x01, 0x0140 },
2436 { 0x00, 0x0077 },
2437 { 0x04, 0x7800 },
2438 { 0x04, 0x7000 },
2439
2440 { 0x03, 0x802f },
2441 { 0x02, 0x4f02 },
2442 { 0x01, 0x0409 },
2443 { 0x00, 0xf0f9 },
2444 { 0x04, 0x9800 },
2445 { 0x04, 0x9000 },
2446
2447 { 0x03, 0xdf01 },
2448 { 0x02, 0xdf20 },
2449 { 0x01, 0xff95 },
2450 { 0x00, 0xba00 },
2451 { 0x04, 0xa800 },
2452 { 0x04, 0xa000 },
2453
2454 { 0x03, 0xff41 },
2455 { 0x02, 0xdf20 },
2456 { 0x01, 0x0140 },
2457 { 0x00, 0x00bb },
2458 { 0x04, 0xb800 },
2459 { 0x04, 0xb000 },
2460
2461 { 0x03, 0xdf41 },
2462 { 0x02, 0xdc60 },
2463 { 0x01, 0x6340 },
2464 { 0x00, 0x007d },
2465 { 0x04, 0xd800 },
2466 { 0x04, 0xd000 },
2467
2468 { 0x03, 0xdf01 },
2469 { 0x02, 0xdf20 },
2470 { 0x01, 0x100a },
2471 { 0x00, 0xa0ff },
2472 { 0x04, 0xf800 },
2473 { 0x04, 0xf000 },
2474
2475 { 0x1f, 0x0000 },
2476 { 0x0b, 0x0000 },
2477 { 0x00, 0x9200 }
2478 };
1da177e4 2479
4da19633 2480 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2481}
2482
4da19633 2483static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2484{
350f7596 2485 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2486 { 0x1f, 0x0002 },
2487 { 0x01, 0x90d0 },
2488 { 0x1f, 0x0000 }
2489 };
2490
4da19633 2491 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2492}
2493
4da19633 2494static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2495{
2496 struct pci_dev *pdev = tp->pci_dev;
2e955856 2497
ccbae55e
SS		 2498 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2499 (pdev->subsystem_device != 0xe000))
2e955856 2500 return;
2501
4da19633 2502 rtl_writephy(tp, 0x1f, 0x0001);
2503 rtl_writephy(tp, 0x10, 0xf01b);
2504 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2505}
2506
4da19633 2507static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2508{
350f7596 2509 static const struct phy_reg phy_reg_init[] = {
2e955856 2510 { 0x1f, 0x0001 },
2511 { 0x04, 0x0000 },
2512 { 0x03, 0x00a1 },
2513 { 0x02, 0x0008 },
2514 { 0x01, 0x0120 },
2515 { 0x00, 0x1000 },
2516 { 0x04, 0x0800 },
2517 { 0x04, 0x9000 },
2518 { 0x03, 0x802f },
2519 { 0x02, 0x4f02 },
2520 { 0x01, 0x0409 },
2521 { 0x00, 0xf099 },
2522 { 0x04, 0x9800 },
2523 { 0x04, 0xa000 },
2524 { 0x03, 0xdf01 },
2525 { 0x02, 0xdf20 },
2526 { 0x01, 0xff95 },
2527 { 0x00, 0xba00 },
2528 { 0x04, 0xa800 },
2529 { 0x04, 0xf000 },
2530 { 0x03, 0xdf01 },
2531 { 0x02, 0xdf20 },
2532 { 0x01, 0x101a },
2533 { 0x00, 0xa0ff },
2534 { 0x04, 0xf800 },
2535 { 0x04, 0x0000 },
2536 { 0x1f, 0x0000 },
2537
2538 { 0x1f, 0x0001 },
2539 { 0x10, 0xf41b },
2540 { 0x14, 0xfb54 },
2541 { 0x18, 0xf5c7 },
2542 { 0x1f, 0x0000 },
2543
2544 { 0x1f, 0x0001 },
2545 { 0x17, 0x0cc0 },
2546 { 0x1f, 0x0000 }
2547 };
2548
4da19633 2549 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2550
4da19633 2551 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2552}
2553
4da19633 2554static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2555{
350f7596 2556 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2557 { 0x1f, 0x0001 },
2558 { 0x04, 0x0000 },
2559 { 0x03, 0x00a1 },
2560 { 0x02, 0x0008 },
2561 { 0x01, 0x0120 },
2562 { 0x00, 0x1000 },
2563 { 0x04, 0x0800 },
2564 { 0x04, 0x9000 },
2565 { 0x03, 0x802f },
2566 { 0x02, 0x4f02 },
2567 { 0x01, 0x0409 },
2568 { 0x00, 0xf099 },
2569 { 0x04, 0x9800 },
2570 { 0x04, 0xa000 },
2571 { 0x03, 0xdf01 },
2572 { 0x02, 0xdf20 },
2573 { 0x01, 0xff95 },
2574 { 0x00, 0xba00 },
2575 { 0x04, 0xa800 },
2576 { 0x04, 0xf000 },
2577 { 0x03, 0xdf01 },
2578 { 0x02, 0xdf20 },
2579 { 0x01, 0x101a },
2580 { 0x00, 0xa0ff },
2581 { 0x04, 0xf800 },
2582 { 0x04, 0x0000 },
2583 { 0x1f, 0x0000 },
2584
2585 { 0x1f, 0x0001 },
2586 { 0x0b, 0x8480 },
2587 { 0x1f, 0x0000 },
2588
2589 { 0x1f, 0x0001 },
2590 { 0x18, 0x67c7 },
2591 { 0x04, 0x2000 },
2592 { 0x03, 0x002f },
2593 { 0x02, 0x4360 },
2594 { 0x01, 0x0109 },
2595 { 0x00, 0x3022 },
2596 { 0x04, 0x2800 },
2597 { 0x1f, 0x0000 },
2598
2599 { 0x1f, 0x0001 },
2600 { 0x17, 0x0cc0 },
2601 { 0x1f, 0x0000 }
2602 };
2603
4da19633 2604 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2605}
2606
4da19633 2607static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2608{
350f7596 2609 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2610 { 0x10, 0xf41b },
2611 { 0x1f, 0x0000 }
2612 };
2613
4da19633 2614 rtl_writephy(tp, 0x1f, 0x0001);
2615 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2616
4da19633 2617 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2618}
2619
4da19633 2620static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2621{
350f7596 2622 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2623 { 0x1f, 0x0001 },
2624 { 0x10, 0xf41b },
2625 { 0x1f, 0x0000 }
2626 };
2627
4da19633 2628 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2629}
2630
4da19633 2631static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2632{
350f7596 2633 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2634 { 0x1f, 0x0000 },
2635 { 0x1d, 0x0f00 },
2636 { 0x1f, 0x0002 },
2637 { 0x0c, 0x1ec8 },
2638 { 0x1f, 0x0000 }
2639 };
2640
4da19633 2641 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2642}
2643
4da19633 2644static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2645{
350f7596 2646 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2647 { 0x1f, 0x0001 },
2648 { 0x1d, 0x3d98 },
2649 { 0x1f, 0x0000 }
2650 };
2651
4da19633 2652 rtl_writephy(tp, 0x1f, 0x0000);
2653 rtl_patchphy(tp, 0x14, 1 << 5);
2654 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2655
4da19633 2656 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2657}
2658
4da19633 2659static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2660{
350f7596 2661 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2662 { 0x1f, 0x0001 },
2663 { 0x12, 0x2300 },
867763c1
FR		 2664 { 0x1f, 0x0002 },
2665 { 0x00, 0x88d4 },
2666 { 0x01, 0x82b1 },
2667 { 0x03, 0x7002 },
2668 { 0x08, 0x9e30 },
2669 { 0x09, 0x01f0 },
2670 { 0x0a, 0x5500 },
2671 { 0x0c, 0x00c8 },
2672 { 0x1f, 0x0003 },
2673 { 0x12, 0xc096 },
2674 { 0x16, 0x000a },
f50d4275
FR		 2675 { 0x1f, 0x0000 },
2676 { 0x1f, 0x0000 },
2677 { 0x09, 0x2000 },
2678 { 0x09, 0x0000 }
867763c1
FR		 2679 };
2680
4da19633 2681 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2682
4da19633 2683 rtl_patchphy(tp, 0x14, 1 << 5);
2684 rtl_patchphy(tp, 0x0d, 1 << 5);
2685 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2686}
2687
4da19633 2688static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2689{
350f7596 2690 static const struct phy_reg phy_reg_init[] = {
f50d4275 2691 { 0x1f, 0x0001 },
7da97ec9 2692 { 0x12, 0x2300 },
f50d4275
FR		 2693 { 0x03, 0x802f },
2694 { 0x02, 0x4f02 },
2695 { 0x01, 0x0409 },
2696 { 0x00, 0xf099 },
2697 { 0x04, 0x9800 },
2698 { 0x04, 0x9000 },
2699 { 0x1d, 0x3d98 },
7da97ec9
FR		 2700 { 0x1f, 0x0002 },
2701 { 0x0c, 0x7eb8 },
f50d4275
FR		 2702 { 0x06, 0x0761 },
2703 { 0x1f, 0x0003 },
2704 { 0x16, 0x0f0a },
7da97ec9
FR		 2705 { 0x1f, 0x0000 }
2706 };
2707
4da19633 2708 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2709
4da19633 2710 rtl_patchphy(tp, 0x16, 1 << 0);
2711 rtl_patchphy(tp, 0x14, 1 << 5);
2712 rtl_patchphy(tp, 0x0d, 1 << 5);
2713 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2714}
2715
4da19633 2716static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2717{
350f7596 2718 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2719 { 0x1f, 0x0001 },
2720 { 0x12, 0x2300 },
2721 { 0x1d, 0x3d98 },
2722 { 0x1f, 0x0002 },
2723 { 0x0c, 0x7eb8 },
2724 { 0x06, 0x5461 },
2725 { 0x1f, 0x0003 },
2726 { 0x16, 0x0f0a },
2727 { 0x1f, 0x0000 }
2728 };
2729
4da19633 2730 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2731
4da19633 2732 rtl_patchphy(tp, 0x16, 1 << 0);
2733 rtl_patchphy(tp, 0x14, 1 << 5);
2734 rtl_patchphy(tp, 0x0d, 1 << 5);
2735 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2736}
2737
4da19633 2738static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2739{
4da19633 2740 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2741}
2742
bca03d5f 2743static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2744{
350f7596 2745 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2746 /* Channel Estimation */
5b538df9 2747 { 0x1f, 0x0001 },
daf9df6d 2748 { 0x06, 0x4064 },
2749 { 0x07, 0x2863 },
2750 { 0x08, 0x059c },
2751 { 0x09, 0x26b4 },
2752 { 0x0a, 0x6a19 },
2753 { 0x0b, 0xdcc8 },
2754 { 0x10, 0xf06d },
2755 { 0x14, 0x7f68 },
2756 { 0x18, 0x7fd9 },
2757 { 0x1c, 0xf0ff },
2758 { 0x1d, 0x3d9c },
5b538df9 2759 { 0x1f, 0x0003 },
daf9df6d 2760 { 0x12, 0xf49f },
2761 { 0x13, 0x070b },
2762 { 0x1a, 0x05ad },
bca03d5f 2763 { 0x14, 0x94c0 },
2764
2765 /*
2766 * Tx Error Issue
cecb5fd7 2767 * Enhance line driver power
bca03d5f 2768 */
5b538df9 2769 { 0x1f, 0x0002 },
daf9df6d 2770 { 0x06, 0x5561 },
2771 { 0x1f, 0x0005 },
2772 { 0x05, 0x8332 },
bca03d5f 2773 { 0x06, 0x5561 },
2774
2775 /*
2776 * Can not link to 1Gbps with bad cable
2777 * Decrease SNR threshold form 21.07dB to 19.04dB
2778 */
2779 { 0x1f, 0x0001 },
2780 { 0x17, 0x0cc0 },
daf9df6d 2781
5b538df9 2782 { 0x1f, 0x0000 },
bca03d5f 2783 { 0x0d, 0xf880 }
daf9df6d 2784 };
2785
4da19633 2786 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2787
bca03d5f 2788 /*
2789 * Rx Error Issue
2790 * Fine Tune Switching regulator parameter
2791 */
4da19633 2792 rtl_writephy(tp, 0x1f, 0x0002);
2793 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2794 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2795
fdf6fc06 2796 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2797 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2798 { 0x1f, 0x0002 },
2799 { 0x05, 0x669a },
2800 { 0x1f, 0x0005 },
2801 { 0x05, 0x8330 },
2802 { 0x06, 0x669a },
2803 { 0x1f, 0x0002 }
2804 };
2805 int val;
2806
4da19633 2807 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2808
4da19633 2809 val = rtl_readphy(tp, 0x0d);
daf9df6d 2810
2811 if ((val & 0x00ff) != 0x006c) {
350f7596 2812 static const u32 set[] = {
daf9df6d 2813 0x0065, 0x0066, 0x0067, 0x0068,
2814 0x0069, 0x006a, 0x006b, 0x006c
2815 };
2816 int i;
2817
4da19633 2818 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2819
2820 val &= 0xff00;
2821 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2822 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2823 }
2824 } else {
350f7596 2825 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2826 { 0x1f, 0x0002 },
2827 { 0x05, 0x6662 },
2828 { 0x1f, 0x0005 },
2829 { 0x05, 0x8330 },
2830 { 0x06, 0x6662 }
2831 };
2832
4da19633 2833 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2834 }
2835
bca03d5f 2836 /* RSET couple improve */
4da19633 2837 rtl_writephy(tp, 0x1f, 0x0002);
2838 rtl_patchphy(tp, 0x0d, 0x0300);
2839 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2840
bca03d5f 2841 /* Fine tune PLL performance */
4da19633 2842 rtl_writephy(tp, 0x1f, 0x0002);
2843 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2844 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2845
4da19633 2846 rtl_writephy(tp, 0x1f, 0x0005);
2847 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2848
2849 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2850
4da19633 2851 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2852}
2853
bca03d5f 2854static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2855{
350f7596 2856 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2857 /* Channel Estimation */
daf9df6d 2858 { 0x1f, 0x0001 },
2859 { 0x06, 0x4064 },
2860 { 0x07, 0x2863 },
2861 { 0x08, 0x059c },
2862 { 0x09, 0x26b4 },
2863 { 0x0a, 0x6a19 },
2864 { 0x0b, 0xdcc8 },
2865 { 0x10, 0xf06d },
2866 { 0x14, 0x7f68 },
2867 { 0x18, 0x7fd9 },
2868 { 0x1c, 0xf0ff },
2869 { 0x1d, 0x3d9c },
2870 { 0x1f, 0x0003 },
2871 { 0x12, 0xf49f },
2872 { 0x13, 0x070b },
2873 { 0x1a, 0x05ad },
2874 { 0x14, 0x94c0 },
2875
bca03d5f 2876 /*
2877 * Tx Error Issue
cecb5fd7 2878 * Enhance line driver power
bca03d5f 2879 */
daf9df6d 2880 { 0x1f, 0x0002 },
2881 { 0x06, 0x5561 },
2882 { 0x1f, 0x0005 },
2883 { 0x05, 0x8332 },
bca03d5f 2884 { 0x06, 0x5561 },
2885
2886 /*
2887 * Can not link to 1Gbps with bad cable
2888 * Decrease SNR threshold form 21.07dB to 19.04dB
2889 */
2890 { 0x1f, 0x0001 },
2891 { 0x17, 0x0cc0 },
daf9df6d 2892
2893 { 0x1f, 0x0000 },
bca03d5f 2894 { 0x0d, 0xf880 }
5b538df9
FR		 2895 };
2896
4da19633 2897 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2898
fdf6fc06 2899 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2900 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2901 { 0x1f, 0x0002 },
2902 { 0x05, 0x669a },
5b538df9 2903 { 0x1f, 0x0005 },
daf9df6d 2904 { 0x05, 0x8330 },
2905 { 0x06, 0x669a },
2906
2907 { 0x1f, 0x0002 }
2908 };
2909 int val;
2910
4da19633 2911 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2912
4da19633 2913 val = rtl_readphy(tp, 0x0d);
daf9df6d 2914 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2915 static const u32 set[] = {
daf9df6d 2916 0x0065, 0x0066, 0x0067, 0x0068,
2917 0x0069, 0x006a, 0x006b, 0x006c
2918 };
2919 int i;
2920
4da19633 2921 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2922
2923 val &= 0xff00;
2924 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2925 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2926 }
2927 } else {
350f7596 2928 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2929 { 0x1f, 0x0002 },
2930 { 0x05, 0x2642 },
5b538df9 2931 { 0x1f, 0x0005 },
daf9df6d 2932 { 0x05, 0x8330 },
2933 { 0x06, 0x2642 }
5b538df9
FR		 2934 };
2935
4da19633 2936 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2937 }
2938
bca03d5f 2939 /* Fine tune PLL performance */
4da19633 2940 rtl_writephy(tp, 0x1f, 0x0002);
2941 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2942 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2943
bca03d5f 2944 /* Switching regulator Slew rate */
4da19633 2945 rtl_writephy(tp, 0x1f, 0x0002);
2946 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2947
4da19633 2948 rtl_writephy(tp, 0x1f, 0x0005);
2949 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2950
2951 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2952
4da19633 2953 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2954}
2955
4da19633 2956static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2957{
350f7596 2958 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2959 { 0x1f, 0x0002 },
2960 { 0x10, 0x0008 },
2961 { 0x0d, 0x006c },
2962
2963 { 0x1f, 0x0000 },
2964 { 0x0d, 0xf880 },
2965
2966 { 0x1f, 0x0001 },
2967 { 0x17, 0x0cc0 },
2968
2969 { 0x1f, 0x0001 },
2970 { 0x0b, 0xa4d8 },
2971 { 0x09, 0x281c },
2972 { 0x07, 0x2883 },
2973 { 0x0a, 0x6b35 },
2974 { 0x1d, 0x3da4 },
2975 { 0x1c, 0xeffd },
2976 { 0x14, 0x7f52 },
2977 { 0x18, 0x7fc6 },
2978 { 0x08, 0x0601 },
2979 { 0x06, 0x4063 },
2980 { 0x10, 0xf074 },
2981 { 0x1f, 0x0003 },
2982 { 0x13, 0x0789 },
2983 { 0x12, 0xf4bd },
2984 { 0x1a, 0x04fd },
2985 { 0x14, 0x84b0 },
2986 { 0x1f, 0x0000 },
2987 { 0x00, 0x9200 },
2988
2989 { 0x1f, 0x0005 },
2990 { 0x01, 0x0340 },
2991 { 0x1f, 0x0001 },
2992 { 0x04, 0x4000 },
2993 { 0x03, 0x1d21 },
2994 { 0x02, 0x0c32 },
2995 { 0x01, 0x0200 },
2996 { 0x00, 0x5554 },
2997 { 0x04, 0x4800 },
2998 { 0x04, 0x4000 },
2999 { 0x04, 0xf000 },
3000 { 0x03, 0xdf01 },
3001 { 0x02, 0xdf20 },
3002 { 0x01, 0x101a },
3003 { 0x00, 0xa0ff },
3004 { 0x04, 0xf800 },
3005 { 0x04, 0xf000 },
3006 { 0x1f, 0x0000 },
3007
3008 { 0x1f, 0x0007 },
3009 { 0x1e, 0x0023 },
3010 { 0x16, 0x0000 },
3011 { 0x1f, 0x0000 }
3012 };
3013
4da19633 3014 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3015}
3016
e6de30d6 3017static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3018{
3019 static const struct phy_reg phy_reg_init[] = {
3020 { 0x1f, 0x0001 },
3021 { 0x17, 0x0cc0 },
3022
3023 { 0x1f, 0x0007 },
3024 { 0x1e, 0x002d },
3025 { 0x18, 0x0040 },
3026 { 0x1f, 0x0000 }
3027 };
3028
3029 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3030 rtl_patchphy(tp, 0x0d, 1 << 5);
3031}
3032
70090424 3033static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3034{
3035 static const struct phy_reg phy_reg_init[] = {
3036 /* Enable Delay cap */
3037 { 0x1f, 0x0005 },
3038 { 0x05, 0x8b80 },
3039 { 0x06, 0xc896 },
3040 { 0x1f, 0x0000 },
3041
3042 /* Channel estimation fine tune */
3043 { 0x1f, 0x0001 },
3044 { 0x0b, 0x6c20 },
3045 { 0x07, 0x2872 },
3046 { 0x1c, 0xefff },
3047 { 0x1f, 0x0003 },
3048 { 0x14, 0x6420 },
3049 { 0x1f, 0x0000 },
3050
3051 /* Update PFM & 10M TX idle timer */
3052 { 0x1f, 0x0007 },
3053 { 0x1e, 0x002f },
3054 { 0x15, 0x1919 },
3055 { 0x1f, 0x0000 },
3056
3057 { 0x1f, 0x0007 },
3058 { 0x1e, 0x00ac },
3059 { 0x18, 0x0006 },
3060 { 0x1f, 0x0000 }
3061 };
3062
15ecd039
FR		 3063 rtl_apply_firmware(tp);
3064
01dc7fec 3065 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3066
3067 /* DCO enable for 10M IDLE Power */
3068 rtl_writephy(tp, 0x1f, 0x0007);
3069 rtl_writephy(tp, 0x1e, 0x0023);
3070 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3071 rtl_writephy(tp, 0x1f, 0x0000);
3072
3073 /* For impedance matching */
3074 rtl_writephy(tp, 0x1f, 0x0002);
3075 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3076 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3077
3078 /* PHY auto speed down */
3079 rtl_writephy(tp, 0x1f, 0x0007);
3080 rtl_writephy(tp, 0x1e, 0x002d);
3081 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3082 rtl_writephy(tp, 0x1f, 0x0000);
3083 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3084
3085 rtl_writephy(tp, 0x1f, 0x0005);
3086 rtl_writephy(tp, 0x05, 0x8b86);
3087 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3088 rtl_writephy(tp, 0x1f, 0x0000);
3089
3090 rtl_writephy(tp, 0x1f, 0x0005);
3091 rtl_writephy(tp, 0x05, 0x8b85);
3092 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3093 rtl_writephy(tp, 0x1f, 0x0007);
3094 rtl_writephy(tp, 0x1e, 0x0020);
3095 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3096 rtl_writephy(tp, 0x1f, 0x0006);
3097 rtl_writephy(tp, 0x00, 0x5a00);
3098 rtl_writephy(tp, 0x1f, 0x0000);
3099 rtl_writephy(tp, 0x0d, 0x0007);
3100 rtl_writephy(tp, 0x0e, 0x003c);
3101 rtl_writephy(tp, 0x0d, 0x4007);
3102 rtl_writephy(tp, 0x0e, 0x0000);
3103 rtl_writephy(tp, 0x0d, 0x0000);
3104}
3105
70090424
HW		 3106static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3107{
3108 static const struct phy_reg phy_reg_init[] = {
3109 /* Enable Delay cap */
3110 { 0x1f, 0x0004 },
3111 { 0x1f, 0x0007 },
3112 { 0x1e, 0x00ac },
3113 { 0x18, 0x0006 },
3114 { 0x1f, 0x0002 },
3115 { 0x1f, 0x0000 },
3116 { 0x1f, 0x0000 },
3117
3118 /* Channel estimation fine tune */
3119 { 0x1f, 0x0003 },
3120 { 0x09, 0xa20f },
3121 { 0x1f, 0x0000 },
3122 { 0x1f, 0x0000 },
3123
3124 /* Green Setting */
3125 { 0x1f, 0x0005 },
3126 { 0x05, 0x8b5b },
3127 { 0x06, 0x9222 },
3128 { 0x05, 0x8b6d },
3129 { 0x06, 0x8000 },
3130 { 0x05, 0x8b76 },
3131 { 0x06, 0x8000 },
3132 { 0x1f, 0x0000 }
3133 };
3134
3135 rtl_apply_firmware(tp);
3136
3137 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3138
3139 /* For 4-corner performance improve */
3140 rtl_writephy(tp, 0x1f, 0x0005);
3141 rtl_writephy(tp, 0x05, 0x8b80);
3142 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3143 rtl_writephy(tp, 0x1f, 0x0000);
3144
3145 /* PHY auto speed down */
3146 rtl_writephy(tp, 0x1f, 0x0004);
3147 rtl_writephy(tp, 0x1f, 0x0007);
3148 rtl_writephy(tp, 0x1e, 0x002d);
3149 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3150 rtl_writephy(tp, 0x1f, 0x0002);
3151 rtl_writephy(tp, 0x1f, 0x0000);
3152 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3153
3154 /* improve 10M EEE waveform */
3155 rtl_writephy(tp, 0x1f, 0x0005);
3156 rtl_writephy(tp, 0x05, 0x8b86);
3157 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3158 rtl_writephy(tp, 0x1f, 0x0000);
3159
3160 /* Improve 2-pair detection performance */
3161 rtl_writephy(tp, 0x1f, 0x0005);
3162 rtl_writephy(tp, 0x05, 0x8b85);
3163 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3164 rtl_writephy(tp, 0x1f, 0x0000);
3165
3166 /* EEE setting */
fdf6fc06 3167 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3168 rtl_writephy(tp, 0x1f, 0x0005);
3169 rtl_writephy(tp, 0x05, 0x8b85);
3170 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3171 rtl_writephy(tp, 0x1f, 0x0004);
3172 rtl_writephy(tp, 0x1f, 0x0007);
3173 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3174 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3175 rtl_writephy(tp, 0x1f, 0x0002);
3176 rtl_writephy(tp, 0x1f, 0x0000);
3177 rtl_writephy(tp, 0x0d, 0x0007);
3178 rtl_writephy(tp, 0x0e, 0x003c);
3179 rtl_writephy(tp, 0x0d, 0x4007);
3180 rtl_writephy(tp, 0x0e, 0x0000);
3181 rtl_writephy(tp, 0x0d, 0x0000);
3182
3183 /* Green feature */
3184 rtl_writephy(tp, 0x1f, 0x0003);
3185 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3186 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3187 rtl_writephy(tp, 0x1f, 0x0000);
3188}
3189
5f886e08
HW		 3190static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3191{
3192 /* For 4-corner performance improve */
3193 rtl_writephy(tp, 0x1f, 0x0005);
3194 rtl_writephy(tp, 0x05, 0x8b80);
3195 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3196 rtl_writephy(tp, 0x1f, 0x0000);
3197
3198 /* PHY auto speed down */
3199 rtl_writephy(tp, 0x1f, 0x0007);
3200 rtl_writephy(tp, 0x1e, 0x002d);
3201 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3202 rtl_writephy(tp, 0x1f, 0x0000);
3203 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3204
3205 /* Improve 10M EEE waveform */
3206 rtl_writephy(tp, 0x1f, 0x0005);
3207 rtl_writephy(tp, 0x05, 0x8b86);
3208 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3209 rtl_writephy(tp, 0x1f, 0x0000);
3210}
3211
c2218925
HW		 3212static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3213{
3214 static const struct phy_reg phy_reg_init[] = {
3215 /* Channel estimation fine tune */
3216 { 0x1f, 0x0003 },
3217 { 0x09, 0xa20f },
3218 { 0x1f, 0x0000 },
3219
3220 /* Modify green table for giga & fnet */
3221 { 0x1f, 0x0005 },
3222 { 0x05, 0x8b55 },
3223 { 0x06, 0x0000 },
3224 { 0x05, 0x8b5e },
3225 { 0x06, 0x0000 },
3226 { 0x05, 0x8b67 },
3227 { 0x06, 0x0000 },
3228 { 0x05, 0x8b70 },
3229 { 0x06, 0x0000 },
3230 { 0x1f, 0x0000 },
3231 { 0x1f, 0x0007 },
3232 { 0x1e, 0x0078 },
3233 { 0x17, 0x0000 },
3234 { 0x19, 0x00fb },
3235 { 0x1f, 0x0000 },
3236
3237 /* Modify green table for 10M */
3238 { 0x1f, 0x0005 },
3239 { 0x05, 0x8b79 },
3240 { 0x06, 0xaa00 },
3241 { 0x1f, 0x0000 },
3242
3243 /* Disable hiimpedance detection (RTCT) */
3244 { 0x1f, 0x0003 },
3245 { 0x01, 0x328a },
3246 { 0x1f, 0x0000 }
3247 };
3248
3249 rtl_apply_firmware(tp);
3250
3251 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3252
5f886e08 3253 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3254
3255 /* Improve 2-pair detection performance */
3256 rtl_writephy(tp, 0x1f, 0x0005);
3257 rtl_writephy(tp, 0x05, 0x8b85);
3258 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3259 rtl_writephy(tp, 0x1f, 0x0000);
3260}
3261
3262static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3263{
3264 rtl_apply_firmware(tp);
3265
5f886e08 3266 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3267}
3268
b3d7b2f2
HW		 3269static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3270{
b3d7b2f2
HW		 3271 static const struct phy_reg phy_reg_init[] = {
3272 /* Channel estimation fine tune */
3273 { 0x1f, 0x0003 },
3274 { 0x09, 0xa20f },
3275 { 0x1f, 0x0000 },
3276
3277 /* Modify green table for giga & fnet */
3278 { 0x1f, 0x0005 },
3279 { 0x05, 0x8b55 },
3280 { 0x06, 0x0000 },
3281 { 0x05, 0x8b5e },
3282 { 0x06, 0x0000 },
3283 { 0x05, 0x8b67 },
3284 { 0x06, 0x0000 },
3285 { 0x05, 0x8b70 },
3286 { 0x06, 0x0000 },
3287 { 0x1f, 0x0000 },
3288 { 0x1f, 0x0007 },
3289 { 0x1e, 0x0078 },
3290 { 0x17, 0x0000 },
3291 { 0x19, 0x00aa },
3292 { 0x1f, 0x0000 },
3293
3294 /* Modify green table for 10M */
3295 { 0x1f, 0x0005 },
3296 { 0x05, 0x8b79 },
3297 { 0x06, 0xaa00 },
3298 { 0x1f, 0x0000 },
3299
3300 /* Disable hiimpedance detection (RTCT) */
3301 { 0x1f, 0x0003 },
3302 { 0x01, 0x328a },
3303 { 0x1f, 0x0000 }
3304 };
3305
3306
3307 rtl_apply_firmware(tp);
3308
3309 rtl8168f_hw_phy_config(tp);
3310
3311 /* Improve 2-pair detection performance */
3312 rtl_writephy(tp, 0x1f, 0x0005);
3313 rtl_writephy(tp, 0x05, 0x8b85);
3314 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3315 rtl_writephy(tp, 0x1f, 0x0000);
3316
3317 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3318
3319 /* Modify green table for giga */
3320 rtl_writephy(tp, 0x1f, 0x0005);
3321 rtl_writephy(tp, 0x05, 0x8b54);
3322 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3323 rtl_writephy(tp, 0x05, 0x8b5d);
3324 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3325 rtl_writephy(tp, 0x05, 0x8a7c);
3326 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3327 rtl_writephy(tp, 0x05, 0x8a7f);
3328 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3329 rtl_writephy(tp, 0x05, 0x8a82);
3330 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3331 rtl_writephy(tp, 0x05, 0x8a85);
3332 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3333 rtl_writephy(tp, 0x05, 0x8a88);
3334 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3335 rtl_writephy(tp, 0x1f, 0x0000);
3336
3337 /* uc same-seed solution */
3338 rtl_writephy(tp, 0x1f, 0x0005);
3339 rtl_writephy(tp, 0x05, 0x8b85);
3340 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3341 rtl_writephy(tp, 0x1f, 0x0000);
3342
3343 /* eee setting */
fdf6fc06 3344 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3345 rtl_writephy(tp, 0x1f, 0x0005);
3346 rtl_writephy(tp, 0x05, 0x8b85);
3347 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3348 rtl_writephy(tp, 0x1f, 0x0004);
3349 rtl_writephy(tp, 0x1f, 0x0007);
3350 rtl_writephy(tp, 0x1e, 0x0020);
3351 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3352 rtl_writephy(tp, 0x1f, 0x0000);
3353 rtl_writephy(tp, 0x0d, 0x0007);
3354 rtl_writephy(tp, 0x0e, 0x003c);
3355 rtl_writephy(tp, 0x0d, 0x4007);
3356 rtl_writephy(tp, 0x0e, 0x0000);
3357 rtl_writephy(tp, 0x0d, 0x0000);
3358
3359 /* Green feature */
3360 rtl_writephy(tp, 0x1f, 0x0003);
3361 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3362 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3363 rtl_writephy(tp, 0x1f, 0x0000);
3364}
3365
c558386b
HW		 3366static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3367{
3368 static const u16 mac_ocp_patch[] = {
3369 0xe008, 0xe01b, 0xe01d, 0xe01f,
3370 0xe021, 0xe023, 0xe025, 0xe027,
3371 0x49d2, 0xf10d, 0x766c, 0x49e2,
3372 0xf00a, 0x1ec0, 0x8ee1, 0xc60a,
3373
3374 0x77c0, 0x4870, 0x9fc0, 0x1ea0,
3375 0xc707, 0x8ee1, 0x9d6c, 0xc603,
3376 0xbe00, 0xb416, 0x0076, 0xe86c,
3377 0xc602, 0xbe00, 0x0000, 0xc602,
3378
3379 0xbe00, 0x0000, 0xc602, 0xbe00,
3380 0x0000, 0xc602, 0xbe00, 0x0000,
3381 0xc602, 0xbe00, 0x0000, 0xc602,
3382 0xbe00, 0x0000, 0xc602, 0xbe00,
3383
3384 0x0000, 0x0000, 0x0000, 0x0000
3385 };
3386 u32 i;
3387
3388 /* Patch code for GPHY reset */
3389 for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++)
3390 r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]);
3391 r8168_mac_ocp_write(tp, 0xfc26, 0x8000);
3392 r8168_mac_ocp_write(tp, 0xfc28, 0x0075);
3393
3394 rtl_apply_firmware(tp);
3395
3396 if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
3397 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
3398 else
3399 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
3400
3401 if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
3402 rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
3403 else
3404 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
3405
3406 rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
3407 rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
3408
3409 r8168_phy_ocp_write(tp, 0xa436, 0x8012);
3410 rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
3411
3412 rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
3413}
3414
4da19633 3415static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3416{
350f7596 3417 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3418 { 0x1f, 0x0003 },
3419 { 0x08, 0x441d },
3420 { 0x01, 0x9100 },
3421 { 0x1f, 0x0000 }
3422 };
3423
4da19633 3424 rtl_writephy(tp, 0x1f, 0x0000);
3425 rtl_patchphy(tp, 0x11, 1 << 12);
3426 rtl_patchphy(tp, 0x19, 1 << 13);
3427 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3428
4da19633 3429 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3430}
3431
5a5e4443
HW		 3432static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3433{
3434 static const struct phy_reg phy_reg_init[] = {
3435 { 0x1f, 0x0005 },
3436 { 0x1a, 0x0000 },
3437 { 0x1f, 0x0000 },
3438
3439 { 0x1f, 0x0004 },
3440 { 0x1c, 0x0000 },
3441 { 0x1f, 0x0000 },
3442
3443 { 0x1f, 0x0001 },
3444 { 0x15, 0x7701 },
3445 { 0x1f, 0x0000 }
3446 };
3447
3448 /* Disable ALDPS before ram code */
3449 rtl_writephy(tp, 0x1f, 0x0000);
3450 rtl_writephy(tp, 0x18, 0x0310);
3451 msleep(100);
3452
953a12cc 3453 rtl_apply_firmware(tp);
5a5e4443
HW		 3454
3455 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3456}
3457
7e18dca1
HW		 3458static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3459{
7e18dca1
HW		 3460 /* Disable ALDPS before setting firmware */
3461 rtl_writephy(tp, 0x1f, 0x0000);
3462 rtl_writephy(tp, 0x18, 0x0310);
3463 msleep(20);
3464
3465 rtl_apply_firmware(tp);
3466
3467 /* EEE setting */
fdf6fc06 3468 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3469 rtl_writephy(tp, 0x1f, 0x0004);
3470 rtl_writephy(tp, 0x10, 0x401f);
3471 rtl_writephy(tp, 0x19, 0x7030);
3472 rtl_writephy(tp, 0x1f, 0x0000);
3473}
3474
5598bfe5
HW		 3475static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3476{
5598bfe5
HW		 3477 static const struct phy_reg phy_reg_init[] = {
3478 { 0x1f, 0x0004 },
3479 { 0x10, 0xc07f },
3480 { 0x19, 0x7030 },
3481 { 0x1f, 0x0000 }
3482 };
3483
3484 /* Disable ALDPS before ram code */
3485 rtl_writephy(tp, 0x1f, 0x0000);
3486 rtl_writephy(tp, 0x18, 0x0310);
3487 msleep(100);
3488
3489 rtl_apply_firmware(tp);
3490
fdf6fc06 3491 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3492 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3493
fdf6fc06 3494 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3495}
3496
5615d9f1
FR		 3497static void rtl_hw_phy_config(struct net_device *dev)
3498{
3499 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3500
3501 rtl8169_print_mac_version(tp);
3502
3503 switch (tp->mac_version) {
3504 case RTL_GIGA_MAC_VER_01:
3505 break;
3506 case RTL_GIGA_MAC_VER_02:
3507 case RTL_GIGA_MAC_VER_03:
4da19633 3508 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3509 break;
3510 case RTL_GIGA_MAC_VER_04:
4da19633 3511 rtl8169sb_hw_phy_config(tp);
5615d9f1 3512 break;
2e955856 3513 case RTL_GIGA_MAC_VER_05:
4da19633 3514 rtl8169scd_hw_phy_config(tp);
2e955856 3515 break;
8c7006aa 3516 case RTL_GIGA_MAC_VER_06:
4da19633 3517 rtl8169sce_hw_phy_config(tp);
8c7006aa 3518 break;
2857ffb7
FR		 3519 case RTL_GIGA_MAC_VER_07:
3520 case RTL_GIGA_MAC_VER_08:
3521 case RTL_GIGA_MAC_VER_09:
4da19633 3522 rtl8102e_hw_phy_config(tp);
2857ffb7 3523 break;
236b8082 3524 case RTL_GIGA_MAC_VER_11:
4da19633 3525 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3526 break;
3527 case RTL_GIGA_MAC_VER_12:
4da19633 3528 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3529 break;
3530 case RTL_GIGA_MAC_VER_17:
4da19633 3531 rtl8168bef_hw_phy_config(tp);
236b8082 3532 break;
867763c1 3533 case RTL_GIGA_MAC_VER_18:
4da19633 3534 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3535 break;
3536 case RTL_GIGA_MAC_VER_19:
4da19633 3537 rtl8168c_1_hw_phy_config(tp);
867763c1 3538 break;
7da97ec9 3539 case RTL_GIGA_MAC_VER_20:
4da19633 3540 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3541 break;
197ff761 3542 case RTL_GIGA_MAC_VER_21:
4da19633 3543 rtl8168c_3_hw_phy_config(tp);
197ff761 3544 break;
6fb07058 3545 case RTL_GIGA_MAC_VER_22:
4da19633 3546 rtl8168c_4_hw_phy_config(tp);
6fb07058 3547 break;
ef3386f0 3548 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3549 case RTL_GIGA_MAC_VER_24:
4da19633 3550 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3551 break;
5b538df9 3552 case RTL_GIGA_MAC_VER_25:
bca03d5f 3553 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3554 break;
3555 case RTL_GIGA_MAC_VER_26:
bca03d5f 3556 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3557 break;
3558 case RTL_GIGA_MAC_VER_27:
4da19633 3559 rtl8168d_3_hw_phy_config(tp);
5b538df9 3560 break;
e6de30d6 3561 case RTL_GIGA_MAC_VER_28:
3562 rtl8168d_4_hw_phy_config(tp);
3563 break;
5a5e4443
HW		 3564 case RTL_GIGA_MAC_VER_29:
3565 case RTL_GIGA_MAC_VER_30:
3566 rtl8105e_hw_phy_config(tp);
3567 break;
cecb5fd7
FR		 3568 case RTL_GIGA_MAC_VER_31:
3569 /* None. */
3570 break;
01dc7fec 3571 case RTL_GIGA_MAC_VER_32:
01dc7fec 3572 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3573 rtl8168e_1_hw_phy_config(tp);
3574 break;
3575 case RTL_GIGA_MAC_VER_34:
3576 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3577 break;
c2218925
HW		 3578 case RTL_GIGA_MAC_VER_35:
3579 rtl8168f_1_hw_phy_config(tp);
3580 break;
3581 case RTL_GIGA_MAC_VER_36:
3582 rtl8168f_2_hw_phy_config(tp);
3583 break;
ef3386f0 3584
7e18dca1
HW		 3585 case RTL_GIGA_MAC_VER_37:
3586 rtl8402_hw_phy_config(tp);
3587 break;
3588
b3d7b2f2
HW		 3589 case RTL_GIGA_MAC_VER_38:
3590 rtl8411_hw_phy_config(tp);
3591 break;
3592
5598bfe5
HW		 3593 case RTL_GIGA_MAC_VER_39:
3594 rtl8106e_hw_phy_config(tp);
3595 break;
3596
c558386b
HW		 3597 case RTL_GIGA_MAC_VER_40:
3598 rtl8168g_1_hw_phy_config(tp);
3599 break;
3600
3601 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3602 default:
3603 break;
3604 }
3605}
3606
da78dbff 3607static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3608{
1da177e4
LT		 3609 struct timer_list *timer = &tp->timer;
3610 void __iomem *ioaddr = tp->mmio_addr;
3611 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3612
bcf0bf90 3613 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3614
4da19633 3615 if (tp->phy_reset_pending(tp)) {
5b0384f4 3616 /*
1da177e4
LT		 3617 * A busy loop could burn quite a few cycles on nowadays CPU.
3618 * Let's delay the execution of the timer for a few ticks.
3619 */
3620 timeout = HZ/10;
3621 goto out_mod_timer;
3622 }
3623
3624 if (tp->link_ok(ioaddr))
da78dbff 3625 return;
1da177e4 3626
da78dbff 3627 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3628
4da19633 3629 tp->phy_reset_enable(tp);
1da177e4
LT		 3630
3631out_mod_timer:
3632 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3633}
3634
3635static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3636{
da78dbff
FR		 3637 if (!test_and_set_bit(flag, tp->wk.flags))
3638 schedule_work(&tp->wk.work);
da78dbff
FR		 3639}
3640
3641static void rtl8169_phy_timer(unsigned long __opaque)
3642{
3643 struct net_device *dev = (struct net_device *)__opaque;
3644 struct rtl8169_private *tp = netdev_priv(dev);
3645
98ddf986 3646 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3647}
3648
1da177e4
LT		 3649static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3650 void __iomem *ioaddr)
3651{
3652 iounmap(ioaddr);
3653 pci_release_regions(pdev);
87aeec76 3654 pci_clear_mwi(pdev);
1da177e4
LT		 3655 pci_disable_device(pdev);
3656 free_netdev(dev);
3657}
3658
ffc46952
FR		 3659DECLARE_RTL_COND(rtl_phy_reset_cond)
3660{
3661 return tp->phy_reset_pending(tp);
3662}
3663
bf793295
FR		 3664static void rtl8169_phy_reset(struct net_device *dev,
3665 struct rtl8169_private *tp)
3666{
4da19633 3667 tp->phy_reset_enable(tp);
ffc46952 3668 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3669}
3670
2544bfc0
FR		 3671static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3672{
3673 void __iomem *ioaddr = tp->mmio_addr;
3674
3675 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3676 (RTL_R8(PHYstatus) & TBI_Enable);
3677}
3678
4ff96fa6
FR		 3679static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3680{
3681 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3682
5615d9f1 3683 rtl_hw_phy_config(dev);
4ff96fa6 3684
77332894
MS		 3685 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3686 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3687 RTL_W8(0x82, 0x01);
3688 }
4ff96fa6 3689
6dccd16b
FR		 3690 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3691
3692 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3693 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3694
bcf0bf90 3695 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3696 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3697 RTL_W8(0x82, 0x01);
3698 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3699 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3700 }
3701
bf793295
FR		 3702 rtl8169_phy_reset(dev, tp);
3703
54405cde 3704 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3705 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3706 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3707 (tp->mii.supports_gmii ?
3708 ADVERTISED_1000baseT_Half |
3709 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3710
2544bfc0 3711 if (rtl_tbi_enabled(tp))
bf82c189 3712 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3713}
3714
773d2021
FR		 3715static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3716{
3717 void __iomem *ioaddr = tp->mmio_addr;
3718 u32 high;
3719 u32 low;
3720
3721 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3722 high = addr[4] | (addr[5] << 8);
3723
da78dbff 3724 rtl_lock_work(tp);
773d2021
FR		 3725
3726 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3727
773d2021 3728 RTL_W32(MAC4, high);
908ba2bf 3729 RTL_R32(MAC4);
3730
78f1cd02 3731 RTL_W32(MAC0, low);
908ba2bf 3732 RTL_R32(MAC0);
3733
c28aa385 3734 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3735 const struct exgmac_reg e[] = {
3736 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3737 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3738 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3739 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3740 low >> 16 },
3741 };
3742
fdf6fc06 3743 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
c28aa385 3744 }
3745
773d2021
FR		 3746 RTL_W8(Cfg9346, Cfg9346_Lock);
3747
da78dbff 3748 rtl_unlock_work(tp);
773d2021
FR		 3749}
3750
3751static int rtl_set_mac_address(struct net_device *dev, void *p)
3752{
3753 struct rtl8169_private *tp = netdev_priv(dev);
3754 struct sockaddr *addr = p;
3755
3756 if (!is_valid_ether_addr(addr->sa_data))
3757 return -EADDRNOTAVAIL;
3758
3759 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3760
3761 rtl_rar_set(tp, dev->dev_addr);
3762
3763 return 0;
3764}
3765
5f787a1a
FR		 3766static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3767{
3768 struct rtl8169_private *tp = netdev_priv(dev);
3769 struct mii_ioctl_data *data = if_mii(ifr);
3770
8b4ab28d
FR		 3771 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3772}
5f787a1a 3773
cecb5fd7
FR		 3774static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3775 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3776{
5f787a1a
FR		 3777 switch (cmd) {
3778 case SIOCGMIIPHY:
3779 data->phy_id = 32; /* Internal PHY */
3780 return 0;
3781
3782 case SIOCGMIIREG:
4da19633 3783 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3784 return 0;
3785
3786 case SIOCSMIIREG:
4da19633 3787 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3788 return 0;
3789 }
3790 return -EOPNOTSUPP;
3791}
3792
8b4ab28d
FR		 3793static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3794{
3795 return -EOPNOTSUPP;
3796}
3797
fbac58fc
FR		 3798static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3799{
3800 if (tp->features & RTL_FEATURE_MSI) {
3801 pci_disable_msi(pdev);
3802 tp->features &= ~RTL_FEATURE_MSI;
3803 }
3804}
3805
c0e45c1c 3806static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3807{
3808 struct mdio_ops *ops = &tp->mdio_ops;
3809
3810 switch (tp->mac_version) {
3811 case RTL_GIGA_MAC_VER_27:
3812 ops->write = r8168dp_1_mdio_write;
3813 ops->read = r8168dp_1_mdio_read;
3814 break;
e6de30d6 3815 case RTL_GIGA_MAC_VER_28:
4804b3b3 3816 case RTL_GIGA_MAC_VER_31:
e6de30d6 3817 ops->write = r8168dp_2_mdio_write;
3818 ops->read = r8168dp_2_mdio_read;
3819 break;
c558386b
HW		 3820 case RTL_GIGA_MAC_VER_40:
3821 case RTL_GIGA_MAC_VER_41:
3822 ops->write = r8168g_mdio_write;
3823 ops->read = r8168g_mdio_read;
3824 break;
c0e45c1c 3825 default:
3826 ops->write = r8169_mdio_write;
3827 ops->read = r8169_mdio_read;
3828 break;
3829 }
3830}
3831
649b3b8c 3832static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3833{
3834 void __iomem *ioaddr = tp->mmio_addr;
3835
3836 switch (tp->mac_version) {
3837 case RTL_GIGA_MAC_VER_29:
3838 case RTL_GIGA_MAC_VER_30:
3839 case RTL_GIGA_MAC_VER_32:
3840 case RTL_GIGA_MAC_VER_33:
3841 case RTL_GIGA_MAC_VER_34:
7e18dca1 3842 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3843 case RTL_GIGA_MAC_VER_38:
5598bfe5 3844 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3845 case RTL_GIGA_MAC_VER_40:
3846 case RTL_GIGA_MAC_VER_41:
649b3b8c 3847 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3848 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3849 break;
3850 default:
3851 break;
3852 }
3853}
3854
3855static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3856{
3857 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3858 return false;
3859
3860 rtl_writephy(tp, 0x1f, 0x0000);
3861 rtl_writephy(tp, MII_BMCR, 0x0000);
3862
3863 rtl_wol_suspend_quirk(tp);
3864
3865 return true;
3866}
3867
065c27c1 3868static void r810x_phy_power_down(struct rtl8169_private *tp)
3869{
3870 rtl_writephy(tp, 0x1f, 0x0000);
3871 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3872}
3873
3874static void r810x_phy_power_up(struct rtl8169_private *tp)
3875{
3876 rtl_writephy(tp, 0x1f, 0x0000);
3877 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3878}
3879
3880static void r810x_pll_power_down(struct rtl8169_private *tp)
3881{
0004299a
HW		 3882 void __iomem *ioaddr = tp->mmio_addr;
3883
649b3b8c 3884 if (rtl_wol_pll_power_down(tp))
065c27c1 3885 return;
065c27c1 3886
3887 r810x_phy_power_down(tp);
0004299a
HW		 3888
3889 switch (tp->mac_version) {
3890 case RTL_GIGA_MAC_VER_07:
3891 case RTL_GIGA_MAC_VER_08:
3892 case RTL_GIGA_MAC_VER_09:
3893 case RTL_GIGA_MAC_VER_10:
3894 case RTL_GIGA_MAC_VER_13:
3895 case RTL_GIGA_MAC_VER_16:
3896 break;
3897 default:
3898 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3899 break;
3900 }
065c27c1 3901}
3902
3903static void r810x_pll_power_up(struct rtl8169_private *tp)
3904{
0004299a
HW		 3905 void __iomem *ioaddr = tp->mmio_addr;
3906
065c27c1 3907 r810x_phy_power_up(tp);
0004299a
HW		 3908
3909 switch (tp->mac_version) {
3910 case RTL_GIGA_MAC_VER_07:
3911 case RTL_GIGA_MAC_VER_08:
3912 case RTL_GIGA_MAC_VER_09:
3913 case RTL_GIGA_MAC_VER_10:
3914 case RTL_GIGA_MAC_VER_13:
3915 case RTL_GIGA_MAC_VER_16:
3916 break;
3917 default:
3918 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3919 break;
3920 }
065c27c1 3921}
3922
3923static void r8168_phy_power_up(struct rtl8169_private *tp)
3924{
3925 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3926 switch (tp->mac_version) {
3927 case RTL_GIGA_MAC_VER_11:
3928 case RTL_GIGA_MAC_VER_12:
3929 case RTL_GIGA_MAC_VER_17:
3930 case RTL_GIGA_MAC_VER_18:
3931 case RTL_GIGA_MAC_VER_19:
3932 case RTL_GIGA_MAC_VER_20:
3933 case RTL_GIGA_MAC_VER_21:
3934 case RTL_GIGA_MAC_VER_22:
3935 case RTL_GIGA_MAC_VER_23:
3936 case RTL_GIGA_MAC_VER_24:
3937 case RTL_GIGA_MAC_VER_25:
3938 case RTL_GIGA_MAC_VER_26:
3939 case RTL_GIGA_MAC_VER_27:
3940 case RTL_GIGA_MAC_VER_28:
3941 case RTL_GIGA_MAC_VER_31:
3942 rtl_writephy(tp, 0x0e, 0x0000);
3943 break;
3944 default:
3945 break;
3946 }
065c27c1 3947 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3948}
3949
3950static void r8168_phy_power_down(struct rtl8169_private *tp)
3951{
3952 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3953 switch (tp->mac_version) {
3954 case RTL_GIGA_MAC_VER_32:
3955 case RTL_GIGA_MAC_VER_33:
3956 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3957 break;
3958
3959 case RTL_GIGA_MAC_VER_11:
3960 case RTL_GIGA_MAC_VER_12:
3961 case RTL_GIGA_MAC_VER_17:
3962 case RTL_GIGA_MAC_VER_18:
3963 case RTL_GIGA_MAC_VER_19:
3964 case RTL_GIGA_MAC_VER_20:
3965 case RTL_GIGA_MAC_VER_21:
3966 case RTL_GIGA_MAC_VER_22:
3967 case RTL_GIGA_MAC_VER_23:
3968 case RTL_GIGA_MAC_VER_24:
3969 case RTL_GIGA_MAC_VER_25:
3970 case RTL_GIGA_MAC_VER_26:
3971 case RTL_GIGA_MAC_VER_27:
3972 case RTL_GIGA_MAC_VER_28:
3973 case RTL_GIGA_MAC_VER_31:
3974 rtl_writephy(tp, 0x0e, 0x0200);
3975 default:
3976 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3977 break;
3978 }
065c27c1 3979}
3980
3981static void r8168_pll_power_down(struct rtl8169_private *tp)
3982{
3983 void __iomem *ioaddr = tp->mmio_addr;
3984
cecb5fd7
FR		 3985 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3986 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3987 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3988 r8168dp_check_dash(tp)) {
065c27c1 3989 return;
5d2e1957 3990 }
065c27c1 3991
cecb5fd7
FR		 3992 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3993 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3994 (RTL_R16(CPlusCmd) & ASF)) {
3995 return;
3996 }
3997
01dc7fec 3998 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3999 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4000 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4001
649b3b8c 4002 if (rtl_wol_pll_power_down(tp))
065c27c1 4003 return;
065c27c1 4004
4005 r8168_phy_power_down(tp);
4006
4007 switch (tp->mac_version) {
4008 case RTL_GIGA_MAC_VER_25:
4009 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4010 case RTL_GIGA_MAC_VER_27:
4011 case RTL_GIGA_MAC_VER_28:
4804b3b3 4012 case RTL_GIGA_MAC_VER_31:
01dc7fec 4013 case RTL_GIGA_MAC_VER_32:
4014 case RTL_GIGA_MAC_VER_33:
065c27c1 4015 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4016 break;
4017 }
4018}
4019
4020static void r8168_pll_power_up(struct rtl8169_private *tp)
4021{
4022 void __iomem *ioaddr = tp->mmio_addr;
4023
065c27c1 4024 switch (tp->mac_version) {
4025 case RTL_GIGA_MAC_VER_25:
4026 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4027 case RTL_GIGA_MAC_VER_27:
4028 case RTL_GIGA_MAC_VER_28:
4804b3b3 4029 case RTL_GIGA_MAC_VER_31:
01dc7fec 4030 case RTL_GIGA_MAC_VER_32:
4031 case RTL_GIGA_MAC_VER_33:
065c27c1 4032 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4033 break;
4034 }
4035
4036 r8168_phy_power_up(tp);
4037}
4038
d58d46b5
FR		 4039static void rtl_generic_op(struct rtl8169_private *tp,
4040 void (*op)(struct rtl8169_private *))
065c27c1 4041{
4042 if (op)
4043 op(tp);
4044}
4045
4046static void rtl_pll_power_down(struct rtl8169_private *tp)
4047{
d58d46b5 4048 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4049}
4050
4051static void rtl_pll_power_up(struct rtl8169_private *tp)
4052{
d58d46b5 4053 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4054}
4055
4056static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
4057{
4058 struct pll_power_ops *ops = &tp->pll_power_ops;
4059
4060 switch (tp->mac_version) {
4061 case RTL_GIGA_MAC_VER_07:
4062 case RTL_GIGA_MAC_VER_08:
4063 case RTL_GIGA_MAC_VER_09:
4064 case RTL_GIGA_MAC_VER_10:
4065 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4066 case RTL_GIGA_MAC_VER_29:
4067 case RTL_GIGA_MAC_VER_30:
7e18dca1 4068 case RTL_GIGA_MAC_VER_37:
5598bfe5 4069 case RTL_GIGA_MAC_VER_39:
065c27c1 4070 ops->down = r810x_pll_power_down;
4071 ops->up = r810x_pll_power_up;
4072 break;
4073
4074 case RTL_GIGA_MAC_VER_11:
4075 case RTL_GIGA_MAC_VER_12:
4076 case RTL_GIGA_MAC_VER_17:
4077 case RTL_GIGA_MAC_VER_18:
4078 case RTL_GIGA_MAC_VER_19:
4079 case RTL_GIGA_MAC_VER_20:
4080 case RTL_GIGA_MAC_VER_21:
4081 case RTL_GIGA_MAC_VER_22:
4082 case RTL_GIGA_MAC_VER_23:
4083 case RTL_GIGA_MAC_VER_24:
4084 case RTL_GIGA_MAC_VER_25:
4085 case RTL_GIGA_MAC_VER_26:
4086 case RTL_GIGA_MAC_VER_27:
e6de30d6 4087 case RTL_GIGA_MAC_VER_28:
4804b3b3 4088 case RTL_GIGA_MAC_VER_31:
01dc7fec 4089 case RTL_GIGA_MAC_VER_32:
4090 case RTL_GIGA_MAC_VER_33:
70090424 4091 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4092 case RTL_GIGA_MAC_VER_35:
4093 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4094 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4095 case RTL_GIGA_MAC_VER_40:
4096 case RTL_GIGA_MAC_VER_41:
065c27c1 4097 ops->down = r8168_pll_power_down;
4098 ops->up = r8168_pll_power_up;
4099 break;
4100
4101 default:
4102 ops->down = NULL;
4103 ops->up = NULL;
4104 break;
4105 }
4106}
4107
e542a226
HW		 4108static void rtl_init_rxcfg(struct rtl8169_private *tp)
4109{
4110 void __iomem *ioaddr = tp->mmio_addr;
4111
4112 switch (tp->mac_version) {
4113 case RTL_GIGA_MAC_VER_01:
4114 case RTL_GIGA_MAC_VER_02:
4115 case RTL_GIGA_MAC_VER_03:
4116 case RTL_GIGA_MAC_VER_04:
4117 case RTL_GIGA_MAC_VER_05:
4118 case RTL_GIGA_MAC_VER_06:
4119 case RTL_GIGA_MAC_VER_10:
4120 case RTL_GIGA_MAC_VER_11:
4121 case RTL_GIGA_MAC_VER_12:
4122 case RTL_GIGA_MAC_VER_13:
4123 case RTL_GIGA_MAC_VER_14:
4124 case RTL_GIGA_MAC_VER_15:
4125 case RTL_GIGA_MAC_VER_16:
4126 case RTL_GIGA_MAC_VER_17:
4127 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4128 break;
4129 case RTL_GIGA_MAC_VER_18:
4130 case RTL_GIGA_MAC_VER_19:
4131 case RTL_GIGA_MAC_VER_20:
4132 case RTL_GIGA_MAC_VER_21:
4133 case RTL_GIGA_MAC_VER_22:
4134 case RTL_GIGA_MAC_VER_23:
4135 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4136 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4137 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4138 break;
4139 default:
4140 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4141 break;
4142 }
4143}
4144
92fc43b4
HW		 4145static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4146{
4147 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4148}
4149
d58d46b5
FR		 4150static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4151{
9c5028e9 4152 void __iomem *ioaddr = tp->mmio_addr;
4153
4154 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4155 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4156 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4157}
4158
4159static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4160{
9c5028e9 4161 void __iomem *ioaddr = tp->mmio_addr;
4162
4163 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4164 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4165 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4166}
4167
4168static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4169{
4170 void __iomem *ioaddr = tp->mmio_addr;
4171
4172 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4173 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4174 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4175}
4176
4177static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4178{
4179 void __iomem *ioaddr = tp->mmio_addr;
4180
4181 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4182 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4183 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4184}
4185
4186static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4187{
4188 void __iomem *ioaddr = tp->mmio_addr;
4189
4190 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4191}
4192
4193static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4194{
4195 void __iomem *ioaddr = tp->mmio_addr;
4196
4197 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4198}
4199
4200static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4201{
4202 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4203
4204 RTL_W8(MaxTxPacketSize, 0x3f);
4205 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4206 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4207 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4208}
4209
4210static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4211{
4212 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4213
4214 RTL_W8(MaxTxPacketSize, 0x0c);
4215 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4216 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4217 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4218}
4219
4220static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4221{
4222 rtl_tx_performance_tweak(tp->pci_dev,
4223 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4224}
4225
4226static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4227{
4228 rtl_tx_performance_tweak(tp->pci_dev,
4229 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4230}
4231
4232static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4233{
4234 void __iomem *ioaddr = tp->mmio_addr;
4235
4236 r8168b_0_hw_jumbo_enable(tp);
4237
4238 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4239}
4240
4241static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4242{
4243 void __iomem *ioaddr = tp->mmio_addr;
4244
4245 r8168b_0_hw_jumbo_disable(tp);
4246
4247 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4248}
4249
4250static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
4251{
4252 struct jumbo_ops *ops = &tp->jumbo_ops;
4253
4254 switch (tp->mac_version) {
4255 case RTL_GIGA_MAC_VER_11:
4256 ops->disable = r8168b_0_hw_jumbo_disable;
4257 ops->enable = r8168b_0_hw_jumbo_enable;
4258 break;
4259 case RTL_GIGA_MAC_VER_12:
4260 case RTL_GIGA_MAC_VER_17:
4261 ops->disable = r8168b_1_hw_jumbo_disable;
4262 ops->enable = r8168b_1_hw_jumbo_enable;
4263 break;
4264 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4265 case RTL_GIGA_MAC_VER_19:
4266 case RTL_GIGA_MAC_VER_20:
4267 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4268 case RTL_GIGA_MAC_VER_22:
4269 case RTL_GIGA_MAC_VER_23:
4270 case RTL_GIGA_MAC_VER_24:
4271 case RTL_GIGA_MAC_VER_25:
4272 case RTL_GIGA_MAC_VER_26:
4273 ops->disable = r8168c_hw_jumbo_disable;
4274 ops->enable = r8168c_hw_jumbo_enable;
4275 break;
4276 case RTL_GIGA_MAC_VER_27:
4277 case RTL_GIGA_MAC_VER_28:
4278 ops->disable = r8168dp_hw_jumbo_disable;
4279 ops->enable = r8168dp_hw_jumbo_enable;
4280 break;
4281 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4282 case RTL_GIGA_MAC_VER_32:
4283 case RTL_GIGA_MAC_VER_33:
4284 case RTL_GIGA_MAC_VER_34:
4285 ops->disable = r8168e_hw_jumbo_disable;
4286 ops->enable = r8168e_hw_jumbo_enable;
4287 break;
4288
4289 /*
4290 * No action needed for jumbo frames with 8169.
4291 * No jumbo for 810x at all.
4292 */
c558386b
HW		 4293 case RTL_GIGA_MAC_VER_40:
4294 case RTL_GIGA_MAC_VER_41:
d58d46b5
FR		 4295 default:
4296 ops->disable = NULL;
4297 ops->enable = NULL;
4298 break;
4299 }
4300}
4301
ffc46952
FR		 4302DECLARE_RTL_COND(rtl_chipcmd_cond)
4303{
4304 void __iomem *ioaddr = tp->mmio_addr;
4305
4306 return RTL_R8(ChipCmd) & CmdReset;
4307}
4308
6f43adc8
FR		 4309static void rtl_hw_reset(struct rtl8169_private *tp)
4310{
4311 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4312
6f43adc8
FR		 4313 RTL_W8(ChipCmd, CmdReset);
4314
ffc46952 4315 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4316}
4317
b6ffd97f 4318static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4319{
b6ffd97f
FR		 4320 struct rtl_fw *rtl_fw;
4321 const char *name;
4322 int rc = -ENOMEM;
953a12cc 4323
b6ffd97f
FR		 4324 name = rtl_lookup_firmware_name(tp);
4325 if (!name)
4326 goto out_no_firmware;
953a12cc 4327
b6ffd97f
FR		 4328 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4329 if (!rtl_fw)
4330 goto err_warn;
31bd204f 4331
b6ffd97f
FR		 4332 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4333 if (rc < 0)
4334 goto err_free;
4335
fd112f2e
FR		 4336 rc = rtl_check_firmware(tp, rtl_fw);
4337 if (rc < 0)
4338 goto err_release_firmware;
4339
b6ffd97f
FR		 4340 tp->rtl_fw = rtl_fw;
4341out:
4342 return;
4343
fd112f2e
FR		 4344err_release_firmware:
4345 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4346err_free:
4347 kfree(rtl_fw);
4348err_warn:
4349 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4350 name, rc);
4351out_no_firmware:
4352 tp->rtl_fw = NULL;
4353 goto out;
4354}
4355
4356static void rtl_request_firmware(struct rtl8169_private *tp)
4357{
4358 if (IS_ERR(tp->rtl_fw))
4359 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4360}
4361
92fc43b4
HW		 4362static void rtl_rx_close(struct rtl8169_private *tp)
4363{
4364 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4365
1687b566 4366 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4367}
4368
ffc46952
FR		 4369DECLARE_RTL_COND(rtl_npq_cond)
4370{
4371 void __iomem *ioaddr = tp->mmio_addr;
4372
4373 return RTL_R8(TxPoll) & NPQ;
4374}
4375
4376DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4377{
4378 void __iomem *ioaddr = tp->mmio_addr;
4379
4380 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4381}
4382
e6de30d6 4383static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4384{
e6de30d6 4385 void __iomem *ioaddr = tp->mmio_addr;
4386
1da177e4 4387 /* Disable interrupts */
811fd301 4388 rtl8169_irq_mask_and_ack(tp);
1da177e4 4389
92fc43b4
HW		 4390 rtl_rx_close(tp);
4391
5d2e1957 4392 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4393 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4394 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4395 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4396 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4397 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4398 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4399 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4400 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4401 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
b3d7b2f2 4402 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4403 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4404 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4405 } else {
4406 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4407 udelay(100);
e6de30d6 4408 }
4409
92fc43b4 4410 rtl_hw_reset(tp);
1da177e4
LT		 4411}
4412
7f796d83 4413static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4414{
4415 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4416
4417 /* Set DMA burst size and Interframe Gap Time */
4418 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4419 (InterFrameGap << TxInterFrameGapShift));
4420}
4421
07ce4064 4422static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4423{
4424 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4425
07ce4064
FR		 4426 tp->hw_start(dev);
4427
da78dbff 4428 rtl_irq_enable_all(tp);
07ce4064
FR		 4429}
4430
7f796d83
FR		 4431static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4432 void __iomem *ioaddr)
4433{
4434 /*
4435 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4436 * register to be written before TxDescAddrLow to work.
4437 * Switching from MMIO to I/O access fixes the issue as well.
4438 */
4439 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4440 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4441 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4442 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4443}
4444
4445static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4446{
4447 u16 cmd;
4448
4449 cmd = RTL_R16(CPlusCmd);
4450 RTL_W16(CPlusCmd, cmd);
4451 return cmd;
4452}
4453
fdd7b4c3 4454static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4455{
4456 /* Low hurts. Let's disable the filtering. */
207d6e87 4457 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4458}
4459
6dccd16b
FR		 4460static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4461{
3744100e 4462 static const struct rtl_cfg2_info {
6dccd16b
FR		 4463 u32 mac_version;
4464 u32 clk;
4465 u32 val;
4466 } cfg2_info [] = {
4467 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4468 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4469 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4470 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4471 };
4472 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4473 unsigned int i;
4474 u32 clk;
4475
4476 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4477 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4478 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4479 RTL_W32(0x7c, p->val);
4480 break;
4481 }
4482 }
4483}
4484
e6b763ea
FR		 4485static void rtl_set_rx_mode(struct net_device *dev)
4486{
4487 struct rtl8169_private *tp = netdev_priv(dev);
4488 void __iomem *ioaddr = tp->mmio_addr;
4489 u32 mc_filter[2]; /* Multicast hash filter */
4490 int rx_mode;
4491 u32 tmp = 0;
4492
4493 if (dev->flags & IFF_PROMISC) {
4494 /* Unconditionally log net taps. */
4495 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4496 rx_mode =
4497 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4498 AcceptAllPhys;
4499 mc_filter[1] = mc_filter[0] = 0xffffffff;
4500 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4501 (dev->flags & IFF_ALLMULTI)) {
4502 /* Too many to filter perfectly -- accept all multicasts. */
4503 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4504 mc_filter[1] = mc_filter[0] = 0xffffffff;
4505 } else {
4506 struct netdev_hw_addr *ha;
4507
4508 rx_mode = AcceptBroadcast | AcceptMyPhys;
4509 mc_filter[1] = mc_filter[0] = 0;
4510 netdev_for_each_mc_addr(ha, dev) {
4511 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4512 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4513 rx_mode |= AcceptMulticast;
4514 }
4515 }
4516
4517 if (dev->features & NETIF_F_RXALL)
4518 rx_mode |= (AcceptErr | AcceptRunt);
4519
4520 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4521
4522 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4523 u32 data = mc_filter[0];
4524
4525 mc_filter[0] = swab32(mc_filter[1]);
4526 mc_filter[1] = swab32(data);
4527 }
4528
4529 RTL_W32(MAR0 + 4, mc_filter[1]);
4530 RTL_W32(MAR0 + 0, mc_filter[0]);
4531
4532 RTL_W32(RxConfig, tmp);
4533}
4534
07ce4064
FR		 4535static void rtl_hw_start_8169(struct net_device *dev)
4536{
4537 struct rtl8169_private *tp = netdev_priv(dev);
4538 void __iomem *ioaddr = tp->mmio_addr;
4539 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4540
9cb427b6
FR		 4541 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4542 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4543 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4544 }
4545
1da177e4 4546 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4547 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4548 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4549 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4550 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4551 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4552
e542a226
HW		 4553 rtl_init_rxcfg(tp);
4554
f0298f81 4555 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4556
6f0333b8 4557 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4558
cecb5fd7
FR		 4559 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4560 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4561 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4562 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4563 rtl_set_rx_tx_config_registers(tp);
1da177e4 4564
7f796d83 4565 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4566
cecb5fd7
FR		 4567 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4568 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4569 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4570 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4571 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4572 }
4573
bcf0bf90
FR		 4574 RTL_W16(CPlusCmd, tp->cp_cmd);
4575
6dccd16b
FR		 4576 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4577
1da177e4
LT		 4578 /*
4579 * Undocumented corner. Supposedly:
4580 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4581 */
4582 RTL_W16(IntrMitigate, 0x0000);
4583
7f796d83 4584 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4585
cecb5fd7
FR		 4586 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4587 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4588 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4589 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4590 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4591 rtl_set_rx_tx_config_registers(tp);
4592 }
4593
1da177e4 4594 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4595
4596 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4597 RTL_R8(IntrMask);
1da177e4
LT		 4598
4599 RTL_W32(RxMissed, 0);
4600
07ce4064 4601 rtl_set_rx_mode(dev);
1da177e4
LT		 4602
4603 /* no early-rx interrupts */
4604 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4605}
1da177e4 4606
beb1fe18
HW		 4607static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4608{
4609 if (tp->csi_ops.write)
52989f0e 4610 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4611}
4612
4613static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4614{
52989f0e 4615 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4616}
4617
4618static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4619{
4620 u32 csi;
4621
beb1fe18
HW		 4622 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4623 rtl_csi_write(tp, 0x070c, csi | bits);
4624}
4625
4626static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4627{
4628 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4629}
4630
beb1fe18 4631static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4632{
beb1fe18 4633 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4634}
4635
ffc46952
FR		 4636DECLARE_RTL_COND(rtl_csiar_cond)
4637{
4638 void __iomem *ioaddr = tp->mmio_addr;
4639
4640 return RTL_R32(CSIAR) & CSIAR_FLAG;
4641}
4642
52989f0e 4643static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4644{
52989f0e 4645 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4646
4647 RTL_W32(CSIDR, value);
4648 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4649 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4650
ffc46952 4651 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4652}
4653
52989f0e 4654static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4655{
52989f0e 4656 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4657
4658 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4659 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4660
ffc46952
FR		 4661 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4662 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4663}
4664
52989f0e 4665static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4666{
52989f0e 4667 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4668
4669 RTL_W32(CSIDR, value);
4670 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4671 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4672 CSIAR_FUNC_NIC);
4673
ffc46952 4674 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4675}
4676
52989f0e 4677static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4678{
52989f0e 4679 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4680
4681 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4682 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4683
ffc46952
FR		 4684 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4685 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4686}
4687
beb1fe18
HW		 4688static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
4689{
4690 struct csi_ops *ops = &tp->csi_ops;
4691
4692 switch (tp->mac_version) {
4693 case RTL_GIGA_MAC_VER_01:
4694 case RTL_GIGA_MAC_VER_02:
4695 case RTL_GIGA_MAC_VER_03:
4696 case RTL_GIGA_MAC_VER_04:
4697 case RTL_GIGA_MAC_VER_05:
4698 case RTL_GIGA_MAC_VER_06:
4699 case RTL_GIGA_MAC_VER_10:
4700 case RTL_GIGA_MAC_VER_11:
4701 case RTL_GIGA_MAC_VER_12:
4702 case RTL_GIGA_MAC_VER_13:
4703 case RTL_GIGA_MAC_VER_14:
4704 case RTL_GIGA_MAC_VER_15:
4705 case RTL_GIGA_MAC_VER_16:
4706 case RTL_GIGA_MAC_VER_17:
4707 ops->write = NULL;
4708 ops->read = NULL;
4709 break;
4710
7e18dca1 4711 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4712 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4713 ops->write = r8402_csi_write;
4714 ops->read = r8402_csi_read;
4715 break;
4716
beb1fe18
HW		 4717 default:
4718 ops->write = r8169_csi_write;
4719 ops->read = r8169_csi_read;
4720 break;
4721 }
dacf8154
FR		 4722}
4723
4724struct ephy_info {
4725 unsigned int offset;
4726 u16 mask;
4727 u16 bits;
4728};
4729
fdf6fc06
FR		 4730static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4731 int len)
dacf8154
FR		 4732{
4733 u16 w;
4734
4735 while (len-- > 0) {
fdf6fc06
FR		 4736 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4737 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4738 e++;
4739 }
4740}
4741
b726e493
FR		 4742static void rtl_disable_clock_request(struct pci_dev *pdev)
4743{
e44daade 4744 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4745
4746 if (cap) {
4747 u16 ctl;
4748
4749 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4750 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4751 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4752 }
4753}
4754
e6de30d6 4755static void rtl_enable_clock_request(struct pci_dev *pdev)
4756{
e44daade 4757 int cap = pci_pcie_cap(pdev);
e6de30d6 4758
4759 if (cap) {
4760 u16 ctl;
4761
4762 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4763 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4764 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4765 }
4766}
4767
b726e493
FR		 4768#define R8168_CPCMD_QUIRK_MASK (\
4769 EnableBist | \
4770 Mac_dbgo_oe | \
4771 Force_half_dup | \
4772 Force_rxflow_en | \
4773 Force_txflow_en | \
4774 Cxpl_dbg_sel | \
4775 ASF | \
4776 PktCntrDisable | \
4777 Mac_dbgo_sel)
4778
beb1fe18 4779static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4780{
beb1fe18
HW		 4781 void __iomem *ioaddr = tp->mmio_addr;
4782 struct pci_dev *pdev = tp->pci_dev;
4783
b726e493
FR		 4784 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4785
4786 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4787
2e68ae44
FR		 4788 rtl_tx_performance_tweak(pdev,
4789 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4790}
4791
beb1fe18 4792static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4793{
beb1fe18
HW		 4794 void __iomem *ioaddr = tp->mmio_addr;
4795
4796 rtl_hw_start_8168bb(tp);
b726e493 4797
f0298f81 4798 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4799
4800 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4801}
4802
beb1fe18 4803static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4804{
beb1fe18
HW		 4805 void __iomem *ioaddr = tp->mmio_addr;
4806 struct pci_dev *pdev = tp->pci_dev;
4807
b726e493
FR		 4808 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4809
4810 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4811
219a1e9d 4812 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4813
4814 rtl_disable_clock_request(pdev);
4815
4816 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4817}
4818
beb1fe18 4819static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4820{
350f7596 4821 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4822 { 0x01, 0, 0x0001 },
4823 { 0x02, 0x0800, 0x1000 },
4824 { 0x03, 0, 0x0042 },
4825 { 0x06, 0x0080, 0x0000 },
4826 { 0x07, 0, 0x2000 }
4827 };
4828
beb1fe18 4829 rtl_csi_access_enable_2(tp);
b726e493 4830
fdf6fc06 4831 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4832
beb1fe18 4833 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4834}
4835
beb1fe18 4836static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4837{
beb1fe18
HW		 4838 void __iomem *ioaddr = tp->mmio_addr;
4839 struct pci_dev *pdev = tp->pci_dev;
4840
4841 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4842
4843 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4844
4845 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4846
4847 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4848}
4849
beb1fe18 4850static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4851{
beb1fe18
HW		 4852 void __iomem *ioaddr = tp->mmio_addr;
4853 struct pci_dev *pdev = tp->pci_dev;
4854
4855 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4856
4857 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4858
4859 /* Magic. */
4860 RTL_W8(DBG_REG, 0x20);
4861
f0298f81 4862 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4863
4864 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4865
4866 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4867}
4868
beb1fe18 4869static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4870{
beb1fe18 4871 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4872 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4873 { 0x02, 0x0800, 0x1000 },
4874 { 0x03, 0, 0x0002 },
4875 { 0x06, 0x0080, 0x0000 }
4876 };
4877
beb1fe18 4878 rtl_csi_access_enable_2(tp);
b726e493
FR		 4879
4880 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4881
fdf6fc06 4882 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4883
beb1fe18 4884 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4885}
4886
beb1fe18 4887static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4888{
350f7596 4889 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4890 { 0x01, 0, 0x0001 },
4891 { 0x03, 0x0400, 0x0220 }
4892 };
4893
beb1fe18 4894 rtl_csi_access_enable_2(tp);
b726e493 4895
fdf6fc06 4896 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4897
beb1fe18 4898 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4899}
4900
beb1fe18 4901static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4902{
beb1fe18 4903 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4904}
4905
beb1fe18 4906static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4907{
beb1fe18 4908 rtl_csi_access_enable_2(tp);
6fb07058 4909
beb1fe18 4910 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4911}
4912
beb1fe18 4913static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4914{
beb1fe18
HW		 4915 void __iomem *ioaddr = tp->mmio_addr;
4916 struct pci_dev *pdev = tp->pci_dev;
4917
4918 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4919
4920 rtl_disable_clock_request(pdev);
4921
f0298f81 4922 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4923
4924 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4925
4926 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4927}
4928
beb1fe18 4929static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4930{
beb1fe18
HW		 4931 void __iomem *ioaddr = tp->mmio_addr;
4932 struct pci_dev *pdev = tp->pci_dev;
4933
4934 rtl_csi_access_enable_1(tp);
4804b3b3 4935
4936 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4937
4938 RTL_W8(MaxTxPacketSize, TxPacketMax);
4939
4940 rtl_disable_clock_request(pdev);
4941}
4942
beb1fe18 4943static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4944{
beb1fe18
HW		 4945 void __iomem *ioaddr = tp->mmio_addr;
4946 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4947 static const struct ephy_info e_info_8168d_4[] = {
4948 { 0x0b, ~0, 0x48 },
4949 { 0x19, 0x20, 0x50 },
4950 { 0x0c, ~0, 0x20 }
4951 };
4952 int i;
4953
beb1fe18 4954 rtl_csi_access_enable_1(tp);
e6de30d6 4955
4956 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4957
4958 RTL_W8(MaxTxPacketSize, TxPacketMax);
4959
4960 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4961 const struct ephy_info *e = e_info_8168d_4 + i;
4962 u16 w;
4963
fdf6fc06
FR		 4964 w = rtl_ephy_read(tp, e->offset);
4965 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 4966 }
4967
4968 rtl_enable_clock_request(pdev);
4969}
4970
beb1fe18 4971static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4972{
beb1fe18
HW		 4973 void __iomem *ioaddr = tp->mmio_addr;
4974 struct pci_dev *pdev = tp->pci_dev;
70090424 4975 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4976 { 0x00, 0x0200, 0x0100 },
4977 { 0x00, 0x0000, 0x0004 },
4978 { 0x06, 0x0002, 0x0001 },
4979 { 0x06, 0x0000, 0x0030 },
4980 { 0x07, 0x0000, 0x2000 },
4981 { 0x00, 0x0000, 0x0020 },
4982 { 0x03, 0x5800, 0x2000 },
4983 { 0x03, 0x0000, 0x0001 },
4984 { 0x01, 0x0800, 0x1000 },
4985 { 0x07, 0x0000, 0x4000 },
4986 { 0x1e, 0x0000, 0x2000 },
4987 { 0x19, 0xffff, 0xfe6c },
4988 { 0x0a, 0x0000, 0x0040 }
4989 };
4990
beb1fe18 4991 rtl_csi_access_enable_2(tp);
01dc7fec 4992
fdf6fc06 4993 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4994
4995 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4996
4997 RTL_W8(MaxTxPacketSize, TxPacketMax);
4998
4999 rtl_disable_clock_request(pdev);
5000
5001 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5002 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5003 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5004
cecb5fd7 5005 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5006}
5007
beb1fe18 5008static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5009{
beb1fe18
HW		 5010 void __iomem *ioaddr = tp->mmio_addr;
5011 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5012 static const struct ephy_info e_info_8168e_2[] = {
5013 { 0x09, 0x0000, 0x0080 },
5014 { 0x19, 0x0000, 0x0224 }
5015 };
5016
beb1fe18 5017 rtl_csi_access_enable_1(tp);
70090424 5018
fdf6fc06 5019 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424
HW		 5020
5021 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5022
fdf6fc06
FR		 5023 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5024 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5025 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5026 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5027 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5028 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5029 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5030 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5031
3090bd9a 5032 RTL_W8(MaxTxPacketSize, EarlySize);
70090424
HW		 5033
5034 rtl_disable_clock_request(pdev);
5035
5036 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5037 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5038
5039 /* Adjust EEE LED frequency */
5040 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5041
5042 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5043 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5044 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5045}
5046
5f886e08 5047static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5048{
beb1fe18
HW		 5049 void __iomem *ioaddr = tp->mmio_addr;
5050 struct pci_dev *pdev = tp->pci_dev;
c2218925 5051
5f886e08 5052 rtl_csi_access_enable_2(tp);
c2218925
HW		 5053
5054 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5055
fdf6fc06
FR		 5056 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5057 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5058 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5059 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5060 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5061 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5062 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5063 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5064 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5065 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5066
5067 RTL_W8(MaxTxPacketSize, EarlySize);
5068
5069 rtl_disable_clock_request(pdev);
5070
5071 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5072 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925
HW		 5073 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5074 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5075 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5076}
5077
5f886e08
HW		 5078static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5079{
5080 void __iomem *ioaddr = tp->mmio_addr;
5081 static const struct ephy_info e_info_8168f_1[] = {
5082 { 0x06, 0x00c0, 0x0020 },
5083 { 0x08, 0x0001, 0x0002 },
5084 { 0x09, 0x0000, 0x0080 },
5085 { 0x19, 0x0000, 0x0224 }
5086 };
5087
5088 rtl_hw_start_8168f(tp);
5089
fdf6fc06 5090 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5091
fdf6fc06 5092 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5093
5094 /* Adjust EEE LED frequency */
5095 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5096}
5097
b3d7b2f2
HW		 5098static void rtl_hw_start_8411(struct rtl8169_private *tp)
5099{
b3d7b2f2
HW		 5100 static const struct ephy_info e_info_8168f_1[] = {
5101 { 0x06, 0x00c0, 0x0020 },
5102 { 0x0f, 0xffff, 0x5200 },
5103 { 0x1e, 0x0000, 0x4000 },
5104 { 0x19, 0x0000, 0x0224 }
5105 };
5106
5107 rtl_hw_start_8168f(tp);
5108
fdf6fc06 5109 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5110
fdf6fc06 5111 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5112}
5113
c558386b
HW		 5114static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5115{
5116 void __iomem *ioaddr = tp->mmio_addr;
5117 struct pci_dev *pdev = tp->pci_dev;
5118
5119 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5120 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5121 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5122 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5123
5124 rtl_csi_access_enable_1(tp);
5125
5126 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5127
5128 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5129 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5130
5131 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5132 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5133 RTL_W8(MaxTxPacketSize, EarlySize);
5134
5135 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5136 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5137
5138 /* Adjust EEE LED frequency */
5139 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5140
5141 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5142}
5143
07ce4064
FR		 5144static void rtl_hw_start_8168(struct net_device *dev)
5145{
2dd99530
FR		 5146 struct rtl8169_private *tp = netdev_priv(dev);
5147 void __iomem *ioaddr = tp->mmio_addr;
5148
5149 RTL_W8(Cfg9346, Cfg9346_Unlock);
5150
f0298f81 5151 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5152
6f0333b8 5153 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5154
0e485150 5155 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5156
5157 RTL_W16(CPlusCmd, tp->cp_cmd);
5158
0e485150 5159 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5160
0e485150 5161 /* Work around for RxFIFO overflow. */
811fd301 5162 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5163 tp->event_slow |= RxFIFOOver | PCSTimeout;
5164 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5165 }
5166
5167 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5168
b8363901
FR		 5169 rtl_set_rx_mode(dev);
5170
5171 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5172 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 5173
5174 RTL_R8(IntrMask);
5175
219a1e9d
FR		 5176 switch (tp->mac_version) {
5177 case RTL_GIGA_MAC_VER_11:
beb1fe18 5178 rtl_hw_start_8168bb(tp);
4804b3b3 5179 break;
219a1e9d
FR		 5180
5181 case RTL_GIGA_MAC_VER_12:
5182 case RTL_GIGA_MAC_VER_17:
beb1fe18 5183 rtl_hw_start_8168bef(tp);
4804b3b3 5184 break;
219a1e9d
FR		 5185
5186 case RTL_GIGA_MAC_VER_18:
beb1fe18 5187 rtl_hw_start_8168cp_1(tp);
4804b3b3 5188 break;
219a1e9d
FR		 5189
5190 case RTL_GIGA_MAC_VER_19:
beb1fe18 5191 rtl_hw_start_8168c_1(tp);
4804b3b3 5192 break;
219a1e9d
FR		 5193
5194 case RTL_GIGA_MAC_VER_20:
beb1fe18 5195 rtl_hw_start_8168c_2(tp);
4804b3b3 5196 break;
219a1e9d 5197
197ff761 5198 case RTL_GIGA_MAC_VER_21:
beb1fe18 5199 rtl_hw_start_8168c_3(tp);
4804b3b3 5200 break;
197ff761 5201
6fb07058 5202 case RTL_GIGA_MAC_VER_22:
beb1fe18 5203 rtl_hw_start_8168c_4(tp);
4804b3b3 5204 break;
6fb07058 5205
ef3386f0 5206 case RTL_GIGA_MAC_VER_23:
beb1fe18 5207 rtl_hw_start_8168cp_2(tp);
4804b3b3 5208 break;
ef3386f0 5209
7f3e3d3a 5210 case RTL_GIGA_MAC_VER_24:
beb1fe18 5211 rtl_hw_start_8168cp_3(tp);
4804b3b3 5212 break;
7f3e3d3a 5213
5b538df9 5214 case RTL_GIGA_MAC_VER_25:
daf9df6d 5215 case RTL_GIGA_MAC_VER_26:
5216 case RTL_GIGA_MAC_VER_27:
beb1fe18 5217 rtl_hw_start_8168d(tp);
4804b3b3 5218 break;
5b538df9 5219
e6de30d6 5220 case RTL_GIGA_MAC_VER_28:
beb1fe18 5221 rtl_hw_start_8168d_4(tp);
4804b3b3 5222 break;
cecb5fd7 5223
4804b3b3 5224 case RTL_GIGA_MAC_VER_31:
beb1fe18 5225 rtl_hw_start_8168dp(tp);
4804b3b3 5226 break;
5227
01dc7fec 5228 case RTL_GIGA_MAC_VER_32:
5229 case RTL_GIGA_MAC_VER_33:
beb1fe18 5230 rtl_hw_start_8168e_1(tp);
70090424
HW		 5231 break;
5232 case RTL_GIGA_MAC_VER_34:
beb1fe18 5233 rtl_hw_start_8168e_2(tp);
01dc7fec 5234 break;
e6de30d6 5235
c2218925
HW		 5236 case RTL_GIGA_MAC_VER_35:
5237 case RTL_GIGA_MAC_VER_36:
beb1fe18 5238 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5239 break;
5240
b3d7b2f2
HW		 5241 case RTL_GIGA_MAC_VER_38:
5242 rtl_hw_start_8411(tp);
5243 break;
5244
c558386b
HW		 5245 case RTL_GIGA_MAC_VER_40:
5246 case RTL_GIGA_MAC_VER_41:
5247 rtl_hw_start_8168g_1(tp);
5248 break;
5249
219a1e9d
FR		 5250 default:
5251 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5252 dev->name, tp->mac_version);
4804b3b3 5253 break;
219a1e9d 5254 }
2dd99530 5255
0e485150
FR		 5256 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5257
b8363901
FR		 5258 RTL_W8(Cfg9346, Cfg9346_Lock);
5259
2dd99530 5260 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5261}
1da177e4 5262
2857ffb7
FR		 5263#define R810X_CPCMD_QUIRK_MASK (\
5264 EnableBist | \
5265 Mac_dbgo_oe | \
5266 Force_half_dup | \
5edcc537 5267 Force_rxflow_en | \
2857ffb7
FR		 5268 Force_txflow_en | \
5269 Cxpl_dbg_sel | \
5270 ASF | \
5271 PktCntrDisable | \
d24e9aaf 5272 Mac_dbgo_sel)
2857ffb7 5273
beb1fe18 5274static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5275{
beb1fe18
HW		 5276 void __iomem *ioaddr = tp->mmio_addr;
5277 struct pci_dev *pdev = tp->pci_dev;
350f7596 5278 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5279 { 0x01, 0, 0x6e65 },
5280 { 0x02, 0, 0x091f },
5281 { 0x03, 0, 0xc2f9 },
5282 { 0x06, 0, 0xafb5 },
5283 { 0x07, 0, 0x0e00 },
5284 { 0x19, 0, 0xec80 },
5285 { 0x01, 0, 0x2e65 },
5286 { 0x01, 0, 0x6e65 }
5287 };
5288 u8 cfg1;
5289
beb1fe18 5290 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5291
5292 RTL_W8(DBG_REG, FIX_NAK_1);
5293
5294 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5295
5296 RTL_W8(Config1,
5297 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5298 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5299
5300 cfg1 = RTL_R8(Config1);
5301 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5302 RTL_W8(Config1, cfg1 & ~LEDS0);
5303
fdf6fc06 5304 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5305}
5306
beb1fe18 5307static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5308{
beb1fe18
HW		 5309 void __iomem *ioaddr = tp->mmio_addr;
5310 struct pci_dev *pdev = tp->pci_dev;
5311
5312 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5313
5314 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5315
5316 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5317 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5318}
5319
beb1fe18 5320static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5321{
beb1fe18 5322 rtl_hw_start_8102e_2(tp);
2857ffb7 5323
fdf6fc06 5324 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5325}
5326
beb1fe18 5327static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5328{
beb1fe18 5329 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5330 static const struct ephy_info e_info_8105e_1[] = {
5331 { 0x07, 0, 0x4000 },
5332 { 0x19, 0, 0x0200 },
5333 { 0x19, 0, 0x0020 },
5334 { 0x1e, 0, 0x2000 },
5335 { 0x03, 0, 0x0001 },
5336 { 0x19, 0, 0x0100 },
5337 { 0x19, 0, 0x0004 },
5338 { 0x0a, 0, 0x0020 }
5339 };
5340
cecb5fd7 5341 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5342 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5343
cecb5fd7 5344 /* Disable Early Tally Counter */
5a5e4443
HW		 5345 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5346
5347 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5348 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5349
fdf6fc06 5350 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5351}
5352
beb1fe18 5353static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5354{
beb1fe18 5355 rtl_hw_start_8105e_1(tp);
fdf6fc06 5356 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5357}
5358
7e18dca1
HW		 5359static void rtl_hw_start_8402(struct rtl8169_private *tp)
5360{
5361 void __iomem *ioaddr = tp->mmio_addr;
5362 static const struct ephy_info e_info_8402[] = {
5363 { 0x19, 0xffff, 0xff64 },
5364 { 0x1e, 0, 0x4000 }
5365 };
5366
5367 rtl_csi_access_enable_2(tp);
5368
5369 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5370 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5371
5372 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5373 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5374
fdf6fc06 5375 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5376
5377 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5378
fdf6fc06
FR		 5379 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5380 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5381 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5382 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5383 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5384 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5385 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5386}
5387
5598bfe5
HW		 5388static void rtl_hw_start_8106(struct rtl8169_private *tp)
5389{
5390 void __iomem *ioaddr = tp->mmio_addr;
5391
5392 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5393 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5394
5395 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5396 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5397 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5398}
5399
07ce4064
FR		 5400static void rtl_hw_start_8101(struct net_device *dev)
5401{
cdf1a608
FR		 5402 struct rtl8169_private *tp = netdev_priv(dev);
5403 void __iomem *ioaddr = tp->mmio_addr;
5404 struct pci_dev *pdev = tp->pci_dev;
5405
da78dbff
FR		 5406 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5407 tp->event_slow &= ~RxFIFOOver;
811fd301 5408
cecb5fd7
FR		 5409 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5410 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 5411 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 5412
5413 if (cap) {
5414 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5415 PCI_EXP_DEVCTL_NOSNOOP_EN);
5416 }
cdf1a608
FR		 5417 }
5418
d24e9aaf
HW		 5419 RTL_W8(Cfg9346, Cfg9346_Unlock);
5420
2857ffb7
FR		 5421 switch (tp->mac_version) {
5422 case RTL_GIGA_MAC_VER_07:
beb1fe18 5423 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5424 break;
5425
5426 case RTL_GIGA_MAC_VER_08:
beb1fe18 5427 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5428 break;
5429
5430 case RTL_GIGA_MAC_VER_09:
beb1fe18 5431 rtl_hw_start_8102e_2(tp);
2857ffb7 5432 break;
5a5e4443
HW		 5433
5434 case RTL_GIGA_MAC_VER_29:
beb1fe18 5435 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5436 break;
5437 case RTL_GIGA_MAC_VER_30:
beb1fe18 5438 rtl_hw_start_8105e_2(tp);
5a5e4443 5439 break;
7e18dca1
HW		 5440
5441 case RTL_GIGA_MAC_VER_37:
5442 rtl_hw_start_8402(tp);
5443 break;
5598bfe5
HW		 5444
5445 case RTL_GIGA_MAC_VER_39:
5446 rtl_hw_start_8106(tp);
5447 break;
cdf1a608
FR		 5448 }
5449
d24e9aaf 5450 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5451
f0298f81 5452 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5453
6f0333b8 5454 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5455
d24e9aaf 5456 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5457 RTL_W16(CPlusCmd, tp->cp_cmd);
5458
5459 RTL_W16(IntrMitigate, 0x0000);
5460
5461 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5462
5463 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5464 rtl_set_rx_tx_config_registers(tp);
5465
cdf1a608
FR		 5466 RTL_R8(IntrMask);
5467
cdf1a608
FR		 5468 rtl_set_rx_mode(dev);
5469
5470 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5471}
5472
5473static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5474{
d58d46b5
FR		 5475 struct rtl8169_private *tp = netdev_priv(dev);
5476
5477 if (new_mtu < ETH_ZLEN ||
5478 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5479 return -EINVAL;
5480
d58d46b5
FR		 5481 if (new_mtu > ETH_DATA_LEN)
5482 rtl_hw_jumbo_enable(tp);
5483 else
5484 rtl_hw_jumbo_disable(tp);
5485
1da177e4 5486 dev->mtu = new_mtu;
350fb32a
MM		 5487 netdev_update_features(dev);
5488
323bb685 5489 return 0;
1da177e4
LT		 5490}
5491
5492static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5493{
95e0918d 5494 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5495 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5496}
5497
6f0333b8
ED		 5498static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5499 void **data_buff, struct RxDesc *desc)
1da177e4 5500{
48addcc9 5501 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5502 DMA_FROM_DEVICE);
48addcc9 5503
6f0333b8
ED		 5504 kfree(*data_buff);
5505 *data_buff = NULL;
1da177e4
LT		 5506 rtl8169_make_unusable_by_asic(desc);
5507}
5508
5509static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5510{
5511 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5512
5513 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5514}
5515
5516static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5517 u32 rx_buf_sz)
5518{
5519 desc->addr = cpu_to_le64(mapping);
5520 wmb();
5521 rtl8169_mark_to_asic(desc, rx_buf_sz);
5522}
5523
6f0333b8
ED		 5524static inline void *rtl8169_align(void *data)
5525{
5526 return (void *)ALIGN((long)data, 16);
5527}
5528
0ecbe1ca
SG		 5529static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5530 struct RxDesc *desc)
1da177e4 5531{
6f0333b8 5532 void *data;
1da177e4 5533 dma_addr_t mapping;
48addcc9 5534 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5535 struct net_device *dev = tp->dev;
6f0333b8 5536 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5537
6f0333b8
ED		 5538 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5539 if (!data)
5540 return NULL;
e9f63f30 5541
6f0333b8
ED		 5542 if (rtl8169_align(data) != data) {
5543 kfree(data);
5544 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5545 if (!data)
5546 return NULL;
5547 }
3eafe507 5548
48addcc9 5549 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5550 DMA_FROM_DEVICE);
d827d86b
SG		 5551 if (unlikely(dma_mapping_error(d, mapping))) {
5552 if (net_ratelimit())
5553 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5554 goto err_out;
d827d86b 5555 }
1da177e4
LT		 5556
5557 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5558 return data;
3eafe507
SG		 5559
5560err_out:
5561 kfree(data);
5562 return NULL;
1da177e4
LT		 5563}
5564
5565static void rtl8169_rx_clear(struct rtl8169_private *tp)
5566{
07d3f51f 5567 unsigned int i;
1da177e4
LT		 5568
5569 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5570 if (tp->Rx_databuff[i]) {
5571 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5572 tp->RxDescArray + i);
5573 }
5574 }
5575}
5576
0ecbe1ca 5577static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5578{
0ecbe1ca
SG		 5579 desc->opts1 |= cpu_to_le32(RingEnd);
5580}
5b0384f4 5581
0ecbe1ca
SG		 5582static int rtl8169_rx_fill(struct rtl8169_private *tp)
5583{
5584 unsigned int i;
1da177e4 5585
0ecbe1ca
SG		 5586 for (i = 0; i < NUM_RX_DESC; i++) {
5587 void *data;
4ae47c2d 5588
6f0333b8 5589 if (tp->Rx_databuff[i])
1da177e4 5590 continue;
bcf0bf90 5591
0ecbe1ca 5592 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5593 if (!data) {
5594 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5595 goto err_out;
6f0333b8
ED		 5596 }
5597 tp->Rx_databuff[i] = data;
1da177e4 5598 }
1da177e4 5599
0ecbe1ca
SG		 5600 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5601 return 0;
5602
5603err_out:
5604 rtl8169_rx_clear(tp);
5605 return -ENOMEM;
1da177e4
LT		 5606}
5607
1da177e4
LT		 5608static int rtl8169_init_ring(struct net_device *dev)
5609{
5610 struct rtl8169_private *tp = netdev_priv(dev);
5611
5612 rtl8169_init_ring_indexes(tp);
5613
5614 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5615 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5616
0ecbe1ca 5617 return rtl8169_rx_fill(tp);
1da177e4
LT		 5618}
5619
48addcc9 5620static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5621 struct TxDesc *desc)
5622{
5623 unsigned int len = tx_skb->len;
5624
48addcc9
SG		 5625 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5626
1da177e4
LT		 5627 desc->opts1 = 0x00;
5628 desc->opts2 = 0x00;
5629 desc->addr = 0x00;
5630 tx_skb->len = 0;
5631}
5632
3eafe507
SG		 5633static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5634 unsigned int n)
1da177e4
LT		 5635{
5636 unsigned int i;
5637
3eafe507
SG		 5638 for (i = 0; i < n; i++) {
5639 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5640 struct ring_info *tx_skb = tp->tx_skb + entry;
5641 unsigned int len = tx_skb->len;
5642
5643 if (len) {
5644 struct sk_buff *skb = tx_skb->skb;
5645
48addcc9 5646 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5647 tp->TxDescArray + entry);
5648 if (skb) {
cac4b22f 5649 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5650 dev_kfree_skb(skb);
5651 tx_skb->skb = NULL;
5652 }
1da177e4
LT		 5653 }
5654 }
3eafe507
SG		 5655}
5656
5657static void rtl8169_tx_clear(struct rtl8169_private *tp)
5658{
5659 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5660 tp->cur_tx = tp->dirty_tx = 0;
5661}
5662
4422bcd4 5663static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5664{
c4028958 5665 struct net_device *dev = tp->dev;
56de414c 5666 int i;
1da177e4 5667
da78dbff
FR		 5668 napi_disable(&tp->napi);
5669 netif_stop_queue(dev);
5670 synchronize_sched();
1da177e4 5671
c7c2c39b 5672 rtl8169_hw_reset(tp);
5673
56de414c
FR		 5674 for (i = 0; i < NUM_RX_DESC; i++)
5675 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5676
1da177e4 5677 rtl8169_tx_clear(tp);
c7c2c39b 5678 rtl8169_init_ring_indexes(tp);
1da177e4 5679
da78dbff 5680 napi_enable(&tp->napi);
56de414c
FR		 5681 rtl_hw_start(dev);
5682 netif_wake_queue(dev);
5683 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5684}
5685
5686static void rtl8169_tx_timeout(struct net_device *dev)
5687{
da78dbff
FR		 5688 struct rtl8169_private *tp = netdev_priv(dev);
5689
5690 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5691}
5692
5693static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5694 u32 *opts)
1da177e4
LT		 5695{
5696 struct skb_shared_info *info = skb_shinfo(skb);
5697 unsigned int cur_frag, entry;
a6343afb 5698 struct TxDesc * uninitialized_var(txd);
48addcc9 5699 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5700
5701 entry = tp->cur_tx;
5702 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5703 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5704 dma_addr_t mapping;
5705 u32 status, len;
5706 void *addr;
5707
5708 entry = (entry + 1) % NUM_TX_DESC;
5709
5710 txd = tp->TxDescArray + entry;
9e903e08 5711 len = skb_frag_size(frag);
929f6189 5712 addr = skb_frag_address(frag);
48addcc9 5713 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5714 if (unlikely(dma_mapping_error(d, mapping))) {
5715 if (net_ratelimit())
5716 netif_err(tp, drv, tp->dev,
5717 "Failed to map TX fragments DMA!\n");
3eafe507 5718 goto err_out;
d827d86b 5719 }
1da177e4 5720
cecb5fd7 5721 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5722 status = opts[0] | len |
5723 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5724
5725 txd->opts1 = cpu_to_le32(status);
2b7b4318 5726 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5727 txd->addr = cpu_to_le64(mapping);
5728
5729 tp->tx_skb[entry].len = len;
5730 }
5731
5732 if (cur_frag) {
5733 tp->tx_skb[entry].skb = skb;
5734 txd->opts1 |= cpu_to_le32(LastFrag);
5735 }
5736
5737 return cur_frag;
3eafe507
SG		 5738
5739err_out:
5740 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5741 return -EIO;
1da177e4
LT		 5742}
5743
2b7b4318
FR		 5744static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5745 struct sk_buff *skb, u32 *opts)
1da177e4 5746{
2b7b4318 5747 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5748 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5749 int offset = info->opts_offset;
350fb32a 5750
2b7b4318
FR		 5751 if (mss) {
5752 opts[0] |= TD_LSO;
5753 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5754 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5755 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5756
5757 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5758 opts[offset] |= info->checksum.tcp;
1da177e4 5759 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5760 opts[offset] |= info->checksum.udp;
5761 else
5762 WARN_ON_ONCE(1);
1da177e4 5763 }
1da177e4
LT		 5764}
5765
61357325
SH		 5766static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5767 struct net_device *dev)
1da177e4
LT		 5768{
5769 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5770 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5771 struct TxDesc *txd = tp->TxDescArray + entry;
5772 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5773 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5774 dma_addr_t mapping;
5775 u32 status, len;
2b7b4318 5776 u32 opts[2];
3eafe507 5777 int frags;
5b0384f4 5778
477206a0 5779 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5780 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5781 goto err_stop_0;
1da177e4
LT		 5782 }
5783
5784 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5785 goto err_stop_0;
5786
5787 len = skb_headlen(skb);
48addcc9 5788 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5789 if (unlikely(dma_mapping_error(d, mapping))) {
5790 if (net_ratelimit())
5791 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5792 goto err_dma_0;
d827d86b 5793 }
3eafe507
SG		 5794
5795 tp->tx_skb[entry].len = len;
5796 txd->addr = cpu_to_le64(mapping);
1da177e4 5797
2b7b4318
FR		 5798 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5799 opts[0] = DescOwn;
1da177e4 5800
2b7b4318
FR		 5801 rtl8169_tso_csum(tp, skb, opts);
5802
5803 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5804 if (frags < 0)
5805 goto err_dma_1;
5806 else if (frags)
2b7b4318 5807 opts[0] |= FirstFrag;
3eafe507 5808 else {
2b7b4318 5809 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5810 tp->tx_skb[entry].skb = skb;
5811 }
5812
2b7b4318
FR		 5813 txd->opts2 = cpu_to_le32(opts[1]);
5814
5047fb5d
RC		 5815 skb_tx_timestamp(skb);
5816
1da177e4
LT		 5817 wmb();
5818
cecb5fd7 5819 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5820 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5821 txd->opts1 = cpu_to_le32(status);
5822
1da177e4
LT		 5823 tp->cur_tx += frags + 1;
5824
4c020a96 5825 wmb();
1da177e4 5826
cecb5fd7 5827 RTL_W8(TxPoll, NPQ);
1da177e4 5828
da78dbff
FR		 5829 mmiowb();
5830
477206a0 5831 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5832 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5833 * not miss a ring update when it notices a stopped queue.
5834 */
5835 smp_wmb();
1da177e4 5836 netif_stop_queue(dev);
ae1f23fb
FR		 5837 /* Sync with rtl_tx:
5838 * - publish queue status and cur_tx ring index (write barrier)
5839 * - refresh dirty_tx ring index (read barrier).
5840 * May the current thread have a pessimistic view of the ring
5841 * status and forget to wake up queue, a racing rtl_tx thread
5842 * can't.
5843 */
1e874e04 5844 smp_mb();
477206a0 5845 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5846 netif_wake_queue(dev);
5847 }
5848
61357325 5849 return NETDEV_TX_OK;
1da177e4 5850
3eafe507 5851err_dma_1:
48addcc9 5852 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5853err_dma_0:
5854 dev_kfree_skb(skb);
5855 dev->stats.tx_dropped++;
5856 return NETDEV_TX_OK;
5857
5858err_stop_0:
1da177e4 5859 netif_stop_queue(dev);
cebf8cc7 5860 dev->stats.tx_dropped++;
61357325 5861 return NETDEV_TX_BUSY;
1da177e4
LT		 5862}
5863
5864static void rtl8169_pcierr_interrupt(struct net_device *dev)
5865{
5866 struct rtl8169_private *tp = netdev_priv(dev);
5867 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5868 u16 pci_status, pci_cmd;
5869
5870 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5871 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5872
bf82c189
JP		 5873 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5874 pci_cmd, pci_status);
1da177e4
LT		 5875
5876 /*
5877 * The recovery sequence below admits a very elaborated explanation:
5878 * - it seems to work;
d03902b8
FR		 5879 * - I did not see what else could be done;
5880 * - it makes iop3xx happy.
1da177e4
LT		 5881 *
5882 * Feel free to adjust to your needs.
5883 */
a27993f3 5884 if (pdev->broken_parity_status)
d03902b8
FR		 5885 pci_cmd &= ~PCI_COMMAND_PARITY;
5886 else
5887 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5888
5889 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5890
5891 pci_write_config_word(pdev, PCI_STATUS,
5892 pci_status & (PCI_STATUS_DETECTED_PARITY |
5893 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5894 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5895
5896 /* The infamous DAC f*ckup only happens at boot time */
5897 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5898 void __iomem *ioaddr = tp->mmio_addr;
5899
bf82c189 5900 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5901 tp->cp_cmd &= ~PCIDAC;
5902 RTL_W16(CPlusCmd, tp->cp_cmd);
5903 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5904 }
5905
e6de30d6 5906 rtl8169_hw_reset(tp);
d03902b8 5907
98ddf986 5908 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5909}
5910
da78dbff 5911static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5912{
5913 unsigned int dirty_tx, tx_left;
5914
1da177e4
LT		 5915 dirty_tx = tp->dirty_tx;
5916 smp_rmb();
5917 tx_left = tp->cur_tx - dirty_tx;
5918
5919 while (tx_left > 0) {
5920 unsigned int entry = dirty_tx % NUM_TX_DESC;
5921 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5922 u32 status;
5923
5924 rmb();
5925 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5926 if (status & DescOwn)
5927 break;
5928
48addcc9
SG		 5929 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5930 tp->TxDescArray + entry);
1da177e4 5931 if (status & LastFrag) {
17bcb684
FR		 5932 u64_stats_update_begin(&tp->tx_stats.syncp);
5933 tp->tx_stats.packets++;
5934 tp->tx_stats.bytes += tx_skb->skb->len;
5935 u64_stats_update_end(&tp->tx_stats.syncp);
5936 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5937 tx_skb->skb = NULL;
5938 }
5939 dirty_tx++;
5940 tx_left--;
5941 }
5942
5943 if (tp->dirty_tx != dirty_tx) {
5944 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5945 /* Sync with rtl8169_start_xmit:
5946 * - publish dirty_tx ring index (write barrier)
5947 * - refresh cur_tx ring index and queue status (read barrier)
5948 * May the current thread miss the stopped queue condition,
5949 * a racing xmit thread can only have a right view of the
5950 * ring status.
5951 */
1e874e04 5952 smp_mb();
1da177e4 5953 if (netif_queue_stopped(dev) &&
477206a0 5954 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5955 netif_wake_queue(dev);
5956 }
d78ae2dc
FR		 5957 /*
5958 * 8168 hack: TxPoll requests are lost when the Tx packets are
5959 * too close. Let's kick an extra TxPoll request when a burst
5960 * of start_xmit activity is detected (if it is not detected,
5961 * it is slow enough). -- FR
5962 */
da78dbff
FR		 5963 if (tp->cur_tx != dirty_tx) {
5964 void __iomem *ioaddr = tp->mmio_addr;
5965
d78ae2dc 5966 RTL_W8(TxPoll, NPQ);
da78dbff 5967 }
1da177e4
LT		 5968 }
5969}
5970
126fa4b9
FR		 5971static inline int rtl8169_fragmented_frame(u32 status)
5972{
5973 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5974}
5975
adea1ac7 5976static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5977{
1da177e4
LT		 5978 u32 status = opts1 & RxProtoMask;
5979
5980 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5981 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5982 skb->ip_summed = CHECKSUM_UNNECESSARY;
5983 else
bc8acf2c 5984 skb_checksum_none_assert(skb);
1da177e4
LT		 5985}
5986
6f0333b8
ED		 5987static struct sk_buff *rtl8169_try_rx_copy(void *data,
5988 struct rtl8169_private *tp,
5989 int pkt_size,
5990 dma_addr_t addr)
1da177e4 5991{
b449655f 5992 struct sk_buff *skb;
48addcc9 5993 struct device *d = &tp->pci_dev->dev;
b449655f 5994
6f0333b8 5995 data = rtl8169_align(data);
48addcc9 5996 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5997 prefetch(data);
5998 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5999 if (skb)
6000 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6001 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6002
6f0333b8 6003 return skb;
1da177e4
LT		 6004}
6005
da78dbff 6006static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6007{
6008 unsigned int cur_rx, rx_left;
6f0333b8 6009 unsigned int count;
1da177e4 6010
1da177e4
LT		 6011 cur_rx = tp->cur_rx;
6012 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 6013 rx_left = min(rx_left, budget);
1da177e4 6014
4dcb7d33 6015 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6016 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6017 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6018 u32 status;
6019
6020 rmb();
e03f33af 6021 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6022
6023 if (status & DescOwn)
6024 break;
4dcb7d33 6025 if (unlikely(status & RxRES)) {
bf82c189
JP		 6026 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6027 status);
cebf8cc7 6028 dev->stats.rx_errors++;
1da177e4 6029 if (status & (RxRWT | RxRUNT))
cebf8cc7 6030 dev->stats.rx_length_errors++;
1da177e4 6031 if (status & RxCRC)
cebf8cc7 6032 dev->stats.rx_crc_errors++;
9dccf611 6033 if (status & RxFOVF) {
da78dbff 6034 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6035 dev->stats.rx_fifo_errors++;
9dccf611 6036 }
6bbe021d
BG		 6037 if ((status & (RxRUNT | RxCRC)) &&
6038 !(status & (RxRWT | RxFOVF)) &&
6039 (dev->features & NETIF_F_RXALL))
6040 goto process_pkt;
6041
6f0333b8 6042 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 6043 } else {
6f0333b8 6044 struct sk_buff *skb;
6bbe021d
BG		 6045 dma_addr_t addr;
6046 int pkt_size;
6047
6048process_pkt:
6049 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6050 if (likely(!(dev->features & NETIF_F_RXFCS)))
6051 pkt_size = (status & 0x00003fff) - 4;
6052 else
6053 pkt_size = status & 0x00003fff;
1da177e4 6054
126fa4b9
FR		 6055 /*
6056 * The driver does not support incoming fragmented
6057 * frames. They are seen as a symptom of over-mtu
6058 * sized frames.
6059 */
6060 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6061 dev->stats.rx_dropped++;
6062 dev->stats.rx_length_errors++;
6f0333b8 6063 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 6064 continue;
126fa4b9
FR		 6065 }
6066
6f0333b8
ED		 6067 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6068 tp, pkt_size, addr);
6069 rtl8169_mark_to_asic(desc, rx_buf_sz);
6070 if (!skb) {
6071 dev->stats.rx_dropped++;
6072 continue;
1da177e4
LT		 6073 }
6074
adea1ac7 6075 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6076 skb_put(skb, pkt_size);
6077 skb->protocol = eth_type_trans(skb, dev);
6078
7a8fc77b
FR		 6079 rtl8169_rx_vlan_tag(desc, skb);
6080
56de414c 6081 napi_gro_receive(&tp->napi, skb);
1da177e4 6082
8027aa24
JW		 6083 u64_stats_update_begin(&tp->rx_stats.syncp);
6084 tp->rx_stats.packets++;
6085 tp->rx_stats.bytes += pkt_size;
6086 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6087 }
6dccd16b
FR		 6088
6089 /* Work around for AMD plateform. */
95e0918d 6090 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 6091 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
6092 desc->opts2 = 0;
6093 cur_rx++;
6094 }
1da177e4
LT		 6095 }
6096
6097 count = cur_rx - tp->cur_rx;
6098 tp->cur_rx = cur_rx;
6099
6f0333b8 6100 tp->dirty_rx += count;
1da177e4
LT		 6101
6102 return count;
6103}
6104
07d3f51f 6105static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6106{
07d3f51f 6107 struct net_device *dev = dev_instance;
1da177e4 6108 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6109 int handled = 0;
9085cdfa 6110 u16 status;
1da177e4 6111
9085cdfa 6112 status = rtl_get_events(tp);
da78dbff
FR		 6113 if (status && status != 0xffff) {
6114 status &= RTL_EVENT_NAPI | tp->event_slow;
6115 if (status) {
6116 handled = 1;
1da177e4 6117
da78dbff
FR		 6118 rtl_irq_disable(tp);
6119 napi_schedule(&tp->napi);
f11a377b 6120 }
da78dbff
FR		 6121 }
6122 return IRQ_RETVAL(handled);
6123}
1da177e4 6124
da78dbff
FR		 6125/*
6126 * Workqueue context.
6127 */
6128static void rtl_slow_event_work(struct rtl8169_private *tp)
6129{
6130 struct net_device *dev = tp->dev;
6131 u16 status;
6132
6133 status = rtl_get_events(tp) & tp->event_slow;
6134 rtl_ack_events(tp, status);
1da177e4 6135
da78dbff
FR		 6136 if (unlikely(status & RxFIFOOver)) {
6137 switch (tp->mac_version) {
6138 /* Work around for rx fifo overflow */
6139 case RTL_GIGA_MAC_VER_11:
6140 netif_stop_queue(dev);
934714d0
FR		 6141 /* XXX - Hack alert. See rtl_task(). */
6142 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6143 default:
f11a377b
DD		 6144 break;
6145 }
da78dbff 6146 }
1da177e4 6147
da78dbff
FR		 6148 if (unlikely(status & SYSErr))
6149 rtl8169_pcierr_interrupt(dev);
0e485150 6150
da78dbff
FR		 6151 if (status & LinkChg)
6152 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6153
7dbb4918 6154 rtl_irq_enable_all(tp);
1da177e4
LT		 6155}
6156
4422bcd4
FR		 6157static void rtl_task(struct work_struct *work)
6158{
da78dbff
FR		 6159 static const struct {
6160 int bitnr;
6161 void (*action)(struct rtl8169_private *);
6162 } rtl_work[] = {
934714d0 6163 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6164 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6165 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6166 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6167 };
4422bcd4
FR		 6168 struct rtl8169_private *tp =
6169 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6170 struct net_device *dev = tp->dev;
6171 int i;
6172
6173 rtl_lock_work(tp);
6174
6c4a70c5
FR		 6175 if (!netif_running(dev) ||
6176 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6177 goto out_unlock;
6178
6179 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6180 bool pending;
6181
da78dbff 6182 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6183 if (pending)
6184 rtl_work[i].action(tp);
6185 }
4422bcd4 6186
da78dbff
FR		 6187out_unlock:
6188 rtl_unlock_work(tp);
4422bcd4
FR		 6189}
6190
bea3348e 6191static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6192{
bea3348e
SH		 6193 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6194 struct net_device *dev = tp->dev;
da78dbff
FR		 6195 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6196 int work_done= 0;
6197 u16 status;
6198
6199 status = rtl_get_events(tp);
6200 rtl_ack_events(tp, status & ~tp->event_slow);
6201
6202 if (status & RTL_EVENT_NAPI_RX)
6203 work_done = rtl_rx(dev, tp, (u32) budget);
6204
6205 if (status & RTL_EVENT_NAPI_TX)
6206 rtl_tx(dev, tp);
1da177e4 6207
da78dbff
FR		 6208 if (status & tp->event_slow) {
6209 enable_mask &= ~tp->event_slow;
6210
6211 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6212 }
1da177e4 6213
bea3348e 6214 if (work_done < budget) {
288379f0 6215 napi_complete(napi);
f11a377b 6216
da78dbff
FR		 6217 rtl_irq_enable(tp, enable_mask);
6218 mmiowb();
1da177e4
LT		 6219 }
6220
bea3348e 6221 return work_done;
1da177e4 6222}
1da177e4 6223
523a6094
FR		 6224static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6225{
6226 struct rtl8169_private *tp = netdev_priv(dev);
6227
6228 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6229 return;
6230
6231 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6232 RTL_W32(RxMissed, 0);
6233}
6234
1da177e4
LT		 6235static void rtl8169_down(struct net_device *dev)
6236{
6237 struct rtl8169_private *tp = netdev_priv(dev);
6238 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6239
4876cc1e 6240 del_timer_sync(&tp->timer);
1da177e4 6241
93dd79e8 6242 napi_disable(&tp->napi);
da78dbff 6243 netif_stop_queue(dev);
1da177e4 6244
92fc43b4 6245 rtl8169_hw_reset(tp);
323bb685
SG		 6246 /*
6247 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6248 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6249 * and napi is disabled (rtl8169_poll).
323bb685 6250 */
523a6094 6251 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6252
1da177e4 6253 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6254 synchronize_sched();
1da177e4 6255
1da177e4
LT		 6256 rtl8169_tx_clear(tp);
6257
6258 rtl8169_rx_clear(tp);
065c27c1 6259
6260 rtl_pll_power_down(tp);
1da177e4
LT		 6261}
6262
6263static int rtl8169_close(struct net_device *dev)
6264{
6265 struct rtl8169_private *tp = netdev_priv(dev);
6266 struct pci_dev *pdev = tp->pci_dev;
6267
e1759441
RW		 6268 pm_runtime_get_sync(&pdev->dev);
6269
cecb5fd7 6270 /* Update counters before going down */
355423d0
IV		 6271 rtl8169_update_counters(dev);
6272
da78dbff 6273 rtl_lock_work(tp);
6c4a70c5 6274 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6275
1da177e4 6276 rtl8169_down(dev);
da78dbff 6277 rtl_unlock_work(tp);
1da177e4 6278
92a7c4e7 6279 free_irq(pdev->irq, dev);
1da177e4 6280
82553bb6
SG		 6281 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6282 tp->RxPhyAddr);
6283 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6284 tp->TxPhyAddr);
1da177e4
LT		 6285 tp->TxDescArray = NULL;
6286 tp->RxDescArray = NULL;
6287
e1759441
RW		 6288 pm_runtime_put_sync(&pdev->dev);
6289
1da177e4
LT		 6290 return 0;
6291}
6292
dc1c00ce
FR		 6293#ifdef CONFIG_NET_POLL_CONTROLLER
6294static void rtl8169_netpoll(struct net_device *dev)
6295{
6296 struct rtl8169_private *tp = netdev_priv(dev);
6297
6298 rtl8169_interrupt(tp->pci_dev->irq, dev);
6299}
6300#endif
6301
df43ac78
FR		 6302static int rtl_open(struct net_device *dev)
6303{
6304 struct rtl8169_private *tp = netdev_priv(dev);
6305 void __iomem *ioaddr = tp->mmio_addr;
6306 struct pci_dev *pdev = tp->pci_dev;
6307 int retval = -ENOMEM;
6308
6309 pm_runtime_get_sync(&pdev->dev);
6310
6311 /*
e75d6606 6312 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6313 * dma_alloc_coherent provides more.
6314 */
6315 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6316 &tp->TxPhyAddr, GFP_KERNEL);
6317 if (!tp->TxDescArray)
6318 goto err_pm_runtime_put;
6319
6320 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6321 &tp->RxPhyAddr, GFP_KERNEL);
6322 if (!tp->RxDescArray)
6323 goto err_free_tx_0;
6324
6325 retval = rtl8169_init_ring(dev);
6326 if (retval < 0)
6327 goto err_free_rx_1;
6328
6329 INIT_WORK(&tp->wk.work, rtl_task);
6330
6331 smp_mb();
6332
6333 rtl_request_firmware(tp);
6334
92a7c4e7 6335 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6336 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6337 dev->name, dev);
6338 if (retval < 0)
6339 goto err_release_fw_2;
6340
6341 rtl_lock_work(tp);
6342
6343 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6344
6345 napi_enable(&tp->napi);
6346
6347 rtl8169_init_phy(dev, tp);
6348
6349 __rtl8169_set_features(dev, dev->features);
6350
6351 rtl_pll_power_up(tp);
6352
6353 rtl_hw_start(dev);
6354
6355 netif_start_queue(dev);
6356
6357 rtl_unlock_work(tp);
6358
6359 tp->saved_wolopts = 0;
6360 pm_runtime_put_noidle(&pdev->dev);
6361
6362 rtl8169_check_link_status(dev, tp, ioaddr);
6363out:
6364 return retval;
6365
6366err_release_fw_2:
6367 rtl_release_firmware(tp);
6368 rtl8169_rx_clear(tp);
6369err_free_rx_1:
6370 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6371 tp->RxPhyAddr);
6372 tp->RxDescArray = NULL;
6373err_free_tx_0:
6374 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6375 tp->TxPhyAddr);
6376 tp->TxDescArray = NULL;
6377err_pm_runtime_put:
6378 pm_runtime_put_noidle(&pdev->dev);
6379 goto out;
6380}
6381
8027aa24
JW		 6382static struct rtnl_link_stats64 *
6383rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6384{
6385 struct rtl8169_private *tp = netdev_priv(dev);
6386 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6387 unsigned int start;
1da177e4 6388
da78dbff 6389 if (netif_running(dev))
523a6094 6390 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6391
8027aa24
JW		 6392 do {
6393 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6394 stats->rx_packets = tp->rx_stats.packets;
6395 stats->rx_bytes = tp->rx_stats.bytes;
6396 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6397
6398
6399 do {
6400 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6401 stats->tx_packets = tp->tx_stats.packets;
6402 stats->tx_bytes = tp->tx_stats.bytes;
6403 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6404
6405 stats->rx_dropped = dev->stats.rx_dropped;
6406 stats->tx_dropped = dev->stats.tx_dropped;
6407 stats->rx_length_errors = dev->stats.rx_length_errors;
6408 stats->rx_errors = dev->stats.rx_errors;
6409 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6410 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6411 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6412
6413 return stats;
1da177e4
LT		 6414}
6415
861ab440 6416static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6417{
065c27c1 6418 struct rtl8169_private *tp = netdev_priv(dev);
6419
5d06a99f 6420 if (!netif_running(dev))
861ab440 6421 return;
5d06a99f
FR		 6422
6423 netif_device_detach(dev);
6424 netif_stop_queue(dev);
da78dbff
FR		 6425
6426 rtl_lock_work(tp);
6427 napi_disable(&tp->napi);
6c4a70c5 6428 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6429 rtl_unlock_work(tp);
6430
6431 rtl_pll_power_down(tp);
861ab440
RW		 6432}
6433
6434#ifdef CONFIG_PM
6435
6436static int rtl8169_suspend(struct device *device)
6437{
6438 struct pci_dev *pdev = to_pci_dev(device);
6439 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6440
861ab440 6441 rtl8169_net_suspend(dev);
1371fa6d 6442
5d06a99f
FR		 6443 return 0;
6444}
6445
e1759441
RW		 6446static void __rtl8169_resume(struct net_device *dev)
6447{
065c27c1 6448 struct rtl8169_private *tp = netdev_priv(dev);
6449
e1759441 6450 netif_device_attach(dev);
065c27c1 6451
6452 rtl_pll_power_up(tp);
6453
cff4c162
AS		 6454 rtl_lock_work(tp);
6455 napi_enable(&tp->napi);
6c4a70c5 6456 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6457 rtl_unlock_work(tp);
da78dbff 6458
98ddf986 6459 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6460}
6461
861ab440 6462static int rtl8169_resume(struct device *device)
5d06a99f 6463{
861ab440 6464 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6465 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6466 struct rtl8169_private *tp = netdev_priv(dev);
6467
6468 rtl8169_init_phy(dev, tp);
5d06a99f 6469
e1759441
RW		 6470 if (netif_running(dev))
6471 __rtl8169_resume(dev);
5d06a99f 6472
e1759441
RW		 6473 return 0;
6474}
6475
6476static int rtl8169_runtime_suspend(struct device *device)
6477{
6478 struct pci_dev *pdev = to_pci_dev(device);
6479 struct net_device *dev = pci_get_drvdata(pdev);
6480 struct rtl8169_private *tp = netdev_priv(dev);
6481
6482 if (!tp->TxDescArray)
6483 return 0;
6484
da78dbff 6485 rtl_lock_work(tp);
e1759441
RW		 6486 tp->saved_wolopts = __rtl8169_get_wol(tp);
6487 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6488 rtl_unlock_work(tp);
e1759441
RW		 6489
6490 rtl8169_net_suspend(dev);
6491
6492 return 0;
6493}
6494
6495static int rtl8169_runtime_resume(struct device *device)
6496{
6497 struct pci_dev *pdev = to_pci_dev(device);
6498 struct net_device *dev = pci_get_drvdata(pdev);
6499 struct rtl8169_private *tp = netdev_priv(dev);
6500
6501 if (!tp->TxDescArray)
6502 return 0;
6503
da78dbff 6504 rtl_lock_work(tp);
e1759441
RW		 6505 __rtl8169_set_wol(tp, tp->saved_wolopts);
6506 tp->saved_wolopts = 0;
da78dbff 6507 rtl_unlock_work(tp);
e1759441 6508
fccec10b
SG		 6509 rtl8169_init_phy(dev, tp);
6510
e1759441 6511 __rtl8169_resume(dev);
5d06a99f 6512
5d06a99f
FR		 6513 return 0;
6514}
6515
e1759441
RW		 6516static int rtl8169_runtime_idle(struct device *device)
6517{
6518 struct pci_dev *pdev = to_pci_dev(device);
6519 struct net_device *dev = pci_get_drvdata(pdev);
6520 struct rtl8169_private *tp = netdev_priv(dev);
6521
e4fbce74 6522 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6523}
6524
47145210 6525static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6526 .suspend = rtl8169_suspend,
6527 .resume = rtl8169_resume,
6528 .freeze = rtl8169_suspend,
6529 .thaw = rtl8169_resume,
6530 .poweroff = rtl8169_suspend,
6531 .restore = rtl8169_resume,
6532 .runtime_suspend = rtl8169_runtime_suspend,
6533 .runtime_resume = rtl8169_runtime_resume,
6534 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6535};
6536
6537#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6538
6539#else /* !CONFIG_PM */
6540
6541#define RTL8169_PM_OPS NULL
6542
6543#endif /* !CONFIG_PM */
6544
649b3b8c 6545static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6546{
6547 void __iomem *ioaddr = tp->mmio_addr;
6548
6549 /* WoL fails with 8168b when the receiver is disabled. */
6550 switch (tp->mac_version) {
6551 case RTL_GIGA_MAC_VER_11:
6552 case RTL_GIGA_MAC_VER_12:
6553 case RTL_GIGA_MAC_VER_17:
6554 pci_clear_master(tp->pci_dev);
6555
6556 RTL_W8(ChipCmd, CmdRxEnb);
6557 /* PCI commit */
6558 RTL_R8(ChipCmd);
6559 break;
6560 default:
6561 break;
6562 }
6563}
6564
1765f95d
FR		 6565static void rtl_shutdown(struct pci_dev *pdev)
6566{
861ab440 6567 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6568 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6569 struct device *d = &pdev->dev;
6570
6571 pm_runtime_get_sync(d);
861ab440
RW		 6572
6573 rtl8169_net_suspend(dev);
1765f95d 6574
cecb5fd7 6575 /* Restore original MAC address */
cc098dc7
IV		 6576 rtl_rar_set(tp, dev->perm_addr);
6577
92fc43b4 6578 rtl8169_hw_reset(tp);
4bb3f522 6579
861ab440 6580 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6581 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6582 rtl_wol_suspend_quirk(tp);
6583 rtl_wol_shutdown_quirk(tp);
ca52efd5 6584 }
6585
861ab440
RW		 6586 pci_wake_from_d3(pdev, true);
6587 pci_set_power_state(pdev, PCI_D3hot);
6588 }
2a15cd2f 6589
6590 pm_runtime_put_noidle(d);
861ab440 6591}
5d06a99f 6592
e27566ed
FR		 6593static void __devexit rtl_remove_one(struct pci_dev *pdev)
6594{
6595 struct net_device *dev = pci_get_drvdata(pdev);
6596 struct rtl8169_private *tp = netdev_priv(dev);
6597
6598 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6599 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6600 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6601 rtl8168_driver_stop(tp);
6602 }
6603
6604 cancel_work_sync(&tp->wk.work);
6605
ad1be8d3
DN		 6606 netif_napi_del(&tp->napi);
6607
e27566ed
FR		 6608 unregister_netdev(dev);
6609
6610 rtl_release_firmware(tp);
6611
6612 if (pci_dev_run_wake(pdev))
6613 pm_runtime_get_noresume(&pdev->dev);
6614
6615 /* restore original MAC address */
6616 rtl_rar_set(tp, dev->perm_addr);
6617
6618 rtl_disable_msi(pdev, tp);
6619 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6620 pci_set_drvdata(pdev, NULL);
6621}
6622
fa9c385e 6623static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6624 .ndo_open = rtl_open,
fa9c385e
FR		 6625 .ndo_stop = rtl8169_close,
6626 .ndo_get_stats64 = rtl8169_get_stats64,
6627 .ndo_start_xmit = rtl8169_start_xmit,
6628 .ndo_tx_timeout = rtl8169_tx_timeout,
6629 .ndo_validate_addr = eth_validate_addr,
6630 .ndo_change_mtu = rtl8169_change_mtu,
6631 .ndo_fix_features = rtl8169_fix_features,
6632 .ndo_set_features = rtl8169_set_features,
6633 .ndo_set_mac_address = rtl_set_mac_address,
6634 .ndo_do_ioctl = rtl8169_ioctl,
6635 .ndo_set_rx_mode = rtl_set_rx_mode,
6636#ifdef CONFIG_NET_POLL_CONTROLLER
6637 .ndo_poll_controller = rtl8169_netpoll,
6638#endif
6639
6640};
6641
31fa8b18
FR		 6642static const struct rtl_cfg_info {
6643 void (*hw_start)(struct net_device *);
6644 unsigned int region;
6645 unsigned int align;
6646 u16 event_slow;
6647 unsigned features;
6648 u8 default_ver;
6649} rtl_cfg_infos [] = {
6650 [RTL_CFG_0] = {
6651 .hw_start = rtl_hw_start_8169,
6652 .region = 1,
6653 .align = 0,
6654 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6655 .features = RTL_FEATURE_GMII,
6656 .default_ver = RTL_GIGA_MAC_VER_01,
6657 },
6658 [RTL_CFG_1] = {
6659 .hw_start = rtl_hw_start_8168,
6660 .region = 2,
6661 .align = 8,
6662 .event_slow = SYSErr | LinkChg | RxOverflow,
6663 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6664 .default_ver = RTL_GIGA_MAC_VER_11,
6665 },
6666 [RTL_CFG_2] = {
6667 .hw_start = rtl_hw_start_8101,
6668 .region = 2,
6669 .align = 8,
6670 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6671 PCSTimeout,
6672 .features = RTL_FEATURE_MSI,
6673 .default_ver = RTL_GIGA_MAC_VER_13,
6674 }
6675};
6676
6677/* Cfg9346_Unlock assumed. */
6678static unsigned rtl_try_msi(struct rtl8169_private *tp,
6679 const struct rtl_cfg_info *cfg)
6680{
6681 void __iomem *ioaddr = tp->mmio_addr;
6682 unsigned msi = 0;
6683 u8 cfg2;
6684
6685 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6686 if (cfg->features & RTL_FEATURE_MSI) {
6687 if (pci_enable_msi(tp->pci_dev)) {
6688 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6689 } else {
6690 cfg2 |= MSIEnable;
6691 msi = RTL_FEATURE_MSI;
6692 }
6693 }
6694 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6695 RTL_W8(Config2, cfg2);
6696 return msi;
6697}
6698
c558386b
HW		 6699DECLARE_RTL_COND(rtl_link_list_ready_cond)
6700{
6701 void __iomem *ioaddr = tp->mmio_addr;
6702
6703 return RTL_R8(MCU) & LINK_LIST_RDY;
6704}
6705
6706DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6707{
6708 void __iomem *ioaddr = tp->mmio_addr;
6709
6710 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6711}
6712
6713static void __devinit rtl_hw_init_8168g(struct rtl8169_private *tp)
6714{
6715 void __iomem *ioaddr = tp->mmio_addr;
6716 u32 data;
6717
6718 tp->ocp_base = OCP_STD_PHY_BASE;
6719
6720 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6721
6722 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6723 return;
6724
6725 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6726 return;
6727
6728 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6729 msleep(1);
6730 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6731
5f8bcce9 6732 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6733 data &= ~(1 << 14);
6734 r8168_mac_ocp_write(tp, 0xe8de, data);
6735
6736 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6737 return;
6738
5f8bcce9 6739 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6740 data |= (1 << 15);
6741 r8168_mac_ocp_write(tp, 0xe8de, data);
6742
6743 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6744 return;
6745}
6746
6747static void __devinit rtl_hw_initialize(struct rtl8169_private *tp)
6748{
6749 switch (tp->mac_version) {
6750 case RTL_GIGA_MAC_VER_40:
6751 case RTL_GIGA_MAC_VER_41:
6752 rtl_hw_init_8168g(tp);
6753 break;
6754
6755 default:
6756 break;
6757 }
6758}
6759
3b6cf25d
FR		 6760static int __devinit
6761rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6762{
6763 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6764 const unsigned int region = cfg->region;
6765 struct rtl8169_private *tp;
6766 struct mii_if_info *mii;
6767 struct net_device *dev;
6768 void __iomem *ioaddr;
6769 int chipset, i;
6770 int rc;
6771
6772 if (netif_msg_drv(&debug)) {
6773 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6774 MODULENAME, RTL8169_VERSION);
6775 }
6776
6777 dev = alloc_etherdev(sizeof (*tp));
6778 if (!dev) {
6779 rc = -ENOMEM;
6780 goto out;
6781 }
6782
6783 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6784 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6785 tp = netdev_priv(dev);
6786 tp->dev = dev;
6787 tp->pci_dev = pdev;
6788 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6789
6790 mii = &tp->mii;
6791 mii->dev = dev;
6792 mii->mdio_read = rtl_mdio_read;
6793 mii->mdio_write = rtl_mdio_write;
6794 mii->phy_id_mask = 0x1f;
6795 mii->reg_num_mask = 0x1f;
6796 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6797
6798 /* disable ASPM completely as that cause random device stop working
6799 * problems as well as full system hangs for some PCIe devices users */
6800 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6801 PCIE_LINK_STATE_CLKPM);
6802
6803 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6804 rc = pci_enable_device(pdev);
6805 if (rc < 0) {
6806 netif_err(tp, probe, dev, "enable failure\n");
6807 goto err_out_free_dev_1;
6808 }
6809
6810 if (pci_set_mwi(pdev) < 0)
6811 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6812
6813 /* make sure PCI base addr 1 is MMIO */
6814 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6815 netif_err(tp, probe, dev,
6816 "region #%d not an MMIO resource, aborting\n",
6817 region);
6818 rc = -ENODEV;
6819 goto err_out_mwi_2;
6820 }
6821
6822 /* check for weird/broken PCI region reporting */
6823 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6824 netif_err(tp, probe, dev,
6825 "Invalid PCI region size(s), aborting\n");
6826 rc = -ENODEV;
6827 goto err_out_mwi_2;
6828 }
6829
6830 rc = pci_request_regions(pdev, MODULENAME);
6831 if (rc < 0) {
6832 netif_err(tp, probe, dev, "could not request regions\n");
6833 goto err_out_mwi_2;
6834 }
6835
6836 tp->cp_cmd = RxChkSum;
6837
6838 if ((sizeof(dma_addr_t) > 4) &&
6839 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6840 tp->cp_cmd |= PCIDAC;
6841 dev->features |= NETIF_F_HIGHDMA;
6842 } else {
6843 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6844 if (rc < 0) {
6845 netif_err(tp, probe, dev, "DMA configuration failed\n");
6846 goto err_out_free_res_3;
6847 }
6848 }
6849
6850 /* ioremap MMIO region */
6851 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6852 if (!ioaddr) {
6853 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6854 rc = -EIO;
6855 goto err_out_free_res_3;
6856 }
6857 tp->mmio_addr = ioaddr;
6858
6859 if (!pci_is_pcie(pdev))
6860 netif_info(tp, probe, dev, "not PCI Express\n");
6861
6862 /* Identify chip attached to board */
6863 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6864
6865 rtl_init_rxcfg(tp);
6866
6867 rtl_irq_disable(tp);
6868
c558386b
HW		 6869 rtl_hw_initialize(tp);
6870
3b6cf25d
FR		 6871 rtl_hw_reset(tp);
6872
6873 rtl_ack_events(tp, 0xffff);
6874
6875 pci_set_master(pdev);
6876
6877 /*
6878 * Pretend we are using VLANs; This bypasses a nasty bug where
6879 * Interrupts stop flowing on high load on 8110SCd controllers.
6880 */
6881 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6882 tp->cp_cmd |= RxVlan;
6883
6884 rtl_init_mdio_ops(tp);
6885 rtl_init_pll_power_ops(tp);
6886 rtl_init_jumbo_ops(tp);
beb1fe18 6887 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6888
6889 rtl8169_print_mac_version(tp);
6890
6891 chipset = tp->mac_version;
6892 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6893
6894 RTL_W8(Cfg9346, Cfg9346_Unlock);
6895 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6896 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6897 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6898 tp->features |= RTL_FEATURE_WOL;
6899 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6900 tp->features |= RTL_FEATURE_WOL;
6901 tp->features |= rtl_try_msi(tp, cfg);
6902 RTL_W8(Cfg9346, Cfg9346_Lock);
6903
6904 if (rtl_tbi_enabled(tp)) {
6905 tp->set_speed = rtl8169_set_speed_tbi;
6906 tp->get_settings = rtl8169_gset_tbi;
6907 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6908 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6909 tp->link_ok = rtl8169_tbi_link_ok;
6910 tp->do_ioctl = rtl_tbi_ioctl;
6911 } else {
6912 tp->set_speed = rtl8169_set_speed_xmii;
6913 tp->get_settings = rtl8169_gset_xmii;
6914 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6915 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6916 tp->link_ok = rtl8169_xmii_link_ok;
6917 tp->do_ioctl = rtl_xmii_ioctl;
6918 }
6919
6920 mutex_init(&tp->wk.mutex);
6921
6922 /* Get MAC address */
6923 for (i = 0; i < ETH_ALEN; i++)
6924 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6925 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6926
6927 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6928 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6929
6930 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6931
6932 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6933 * properly for all devices */
6934 dev->features |= NETIF_F_RXCSUM |
6935 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6936
6937 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6938 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6939 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6940 NETIF_F_HIGHDMA;
6941
6942 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6943 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6944 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6945
6946 dev->hw_features |= NETIF_F_RXALL;
6947 dev->hw_features |= NETIF_F_RXFCS;
6948
6949 tp->hw_start = cfg->hw_start;
6950 tp->event_slow = cfg->event_slow;
6951
6952 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6953 ~(RxBOVF | RxFOVF) : ~0;
6954
6955 init_timer(&tp->timer);
6956 tp->timer.data = (unsigned long) dev;
6957 tp->timer.function = rtl8169_phy_timer;
6958
6959 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6960
6961 rc = register_netdev(dev);
6962 if (rc < 0)
6963 goto err_out_msi_4;
6964
6965 pci_set_drvdata(pdev, dev);
6966
92a7c4e7
FR		 6967 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6968 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6969 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6970 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6971 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6972 "tx checksumming: %s]\n",
6973 rtl_chip_infos[chipset].jumbo_max,
6974 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6975 }
6976
6977 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6978 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6979 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6980 rtl8168_driver_start(tp);
6981 }
6982
6983 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6984
6985 if (pci_dev_run_wake(pdev))
6986 pm_runtime_put_noidle(&pdev->dev);
6987
6988 netif_carrier_off(dev);
6989
6990out:
6991 return rc;
6992
6993err_out_msi_4:
ad1be8d3 6994 netif_napi_del(&tp->napi);
3b6cf25d
FR		 6995 rtl_disable_msi(pdev, tp);
6996 iounmap(ioaddr);
6997err_out_free_res_3:
6998 pci_release_regions(pdev);
6999err_out_mwi_2:
7000 pci_clear_mwi(pdev);
7001 pci_disable_device(pdev);
7002err_out_free_dev_1:
7003 free_netdev(dev);
7004 goto out;
7005}
7006
1da177e4
LT		 7007static struct pci_driver rtl8169_pci_driver = {
7008 .name = MODULENAME,
7009 .id_table = rtl8169_pci_tbl,
3b6cf25d 7010 .probe = rtl_init_one,
e27566ed 7011 .remove = __devexit_p(rtl_remove_one),
1765f95d 7012 .shutdown = rtl_shutdown,
861ab440 7013 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7014};
7015
07d3f51f 7016static int __init rtl8169_init_module(void)
1da177e4 7017{
29917620 7018 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 7019}
7020
07d3f51f 7021static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 7022{
7023 pci_unregister_driver(&rtl8169_pci_driver);
7024}
7025
7026module_init(rtl8169_init_module);
7027module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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