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Merge branch 'sctp_keys'
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
c558386b 50#define FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw"
bca03d5f 51
1da177e4
LT		 52#ifdef RTL8169_DEBUG
53#define assert(expr) \
5b0384f4
FR		 54 if (!(expr)) { \
55 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 56 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 57 }
06fa7358
JP		 58#define dprintk(fmt, args...) \
59 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 60#else
61#define assert(expr) do {} while (0)
62#define dprintk(fmt, args...) do {} while (0)
63#endif /* RTL8169_DEBUG */
64
b57b7e5a 65#define R8169_MSG_DEFAULT \
f0e837d9 66 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 67
477206a0
JD		 68#define TX_SLOTS_AVAIL(tp) \
69 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72#define TX_FRAGS_READY_FOR(tp,nr_frags) \
73 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 74
1da177e4
LT		 75/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 77static const int multicast_filter_limit = 32;
1da177e4 78
9c14ceaf 79#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 80#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 81#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
82
83#define R8169_REGS_SIZE 256
84#define R8169_NAPI_WEIGHT 64
85#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
86#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
1da177e4
LT		 87#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
88#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
89
90#define RTL8169_TX_TIMEOUT (6*HZ)
91#define RTL8169_PHY_TIMEOUT (10*HZ)
92
93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
c2218925
HW		 136 RTL_GIGA_MAC_VER_35,
137 RTL_GIGA_MAC_VER_36,
7e18dca1 138 RTL_GIGA_MAC_VER_37,
b3d7b2f2 139 RTL_GIGA_MAC_VER_38,
5598bfe5 140 RTL_GIGA_MAC_VER_39,
c558386b
HW		 141 RTL_GIGA_MAC_VER_40,
142 RTL_GIGA_MAC_VER_41,
85bffe6c 143 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 144};
145
2b7b4318
FR		 146enum rtl_tx_desc_version {
147 RTL_TD_0 = 0,
148 RTL_TD_1 = 1,
149};
150
d58d46b5
FR		 151#define JUMBO_1K ETH_DATA_LEN
152#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
153#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
154#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
155#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
156
157#define _R(NAME,TD,FW,SZ,B) { \
158 .name = NAME, \
159 .txd_version = TD, \
160 .fw_name = FW, \
161 .jumbo_max = SZ, \
162 .jumbo_tx_csum = B \
163}
1da177e4 164
3c6bee1d 165static const struct {
1da177e4 166 const char *name;
2b7b4318 167 enum rtl_tx_desc_version txd_version;
953a12cc 168 const char *fw_name;
d58d46b5
FR		 169 u16 jumbo_max;
170 bool jumbo_tx_csum;
85bffe6c
FR		 171} rtl_chip_infos[] = {
172 /* PCI devices. */
173 [RTL_GIGA_MAC_VER_01] =
d58d46b5 174 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_02] =
d58d46b5 176 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_03] =
d58d46b5 178 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 179 [RTL_GIGA_MAC_VER_04] =
d58d46b5 180 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_05] =
d58d46b5 182 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_06] =
d58d46b5 184 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 185 /* PCI-E devices. */
186 [RTL_GIGA_MAC_VER_07] =
d58d46b5 187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_08] =
d58d46b5 189 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_09] =
d58d46b5 191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_10] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_11] =
d58d46b5 195 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 196 [RTL_GIGA_MAC_VER_12] =
d58d46b5 197 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 198 [RTL_GIGA_MAC_VER_13] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_14] =
d58d46b5 201 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 202 [RTL_GIGA_MAC_VER_15] =
d58d46b5 203 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 204 [RTL_GIGA_MAC_VER_16] =
d58d46b5 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_17] =
d58d46b5 207 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_18] =
d58d46b5 209 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_19] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_20] =
d58d46b5 213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_21] =
d58d46b5 215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_22] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_23] =
d58d46b5 219 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_24] =
d58d46b5 221 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
224 JUMBO_9K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 226 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
227 JUMBO_9K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_27] =
d58d46b5 229 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_28] =
d58d46b5 231 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
234 JUMBO_1K, true),
85bffe6c 235 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 236 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
237 JUMBO_1K, true),
85bffe6c 238 [RTL_GIGA_MAC_VER_31] =
d58d46b5 239 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 244 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
245 JUMBO_9K, false),
70090424 246 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 247 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
248 JUMBO_9K, false),
c2218925 249 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
251 JUMBO_9K, false),
c2218925 252 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 253 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
254 JUMBO_9K, false),
7e18dca1
HW		 255 [RTL_GIGA_MAC_VER_37] =
256 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
257 JUMBO_1K, true),
b3d7b2f2
HW		 258 [RTL_GIGA_MAC_VER_38] =
259 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
260 JUMBO_9K, false),
5598bfe5
HW		 261 [RTL_GIGA_MAC_VER_39] =
262 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
263 JUMBO_1K, true),
c558386b
HW		 264 [RTL_GIGA_MAC_VER_40] =
265 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_1,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_41] =
268 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
953a12cc 269};
85bffe6c 270#undef _R
953a12cc 271
bcf0bf90
FR		 272enum cfg_version {
273 RTL_CFG_0 = 0x00,
274 RTL_CFG_1,
275 RTL_CFG_2
276};
277
a3aa1884 278static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 279 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 280 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 281 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 282 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 283 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 284 { PCI_VENDOR_ID_DLINK, 0x4300,
285 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 286 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 287 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 288 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 289 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
290 { PCI_VENDOR_ID_LINKSYS, 0x1032,
291 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 292 { 0x0001, 0x8168,
293 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 294 {0,},
295};
296
297MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
298
6f0333b8 299static int rx_buf_sz = 16383;
4300e8c7 300static int use_dac;
b57b7e5a
SH		 301static struct {
302 u32 msg_enable;
303} debug = { -1 };
1da177e4 304
07d3f51f
FR		 305enum rtl_registers {
306 MAC0 = 0, /* Ethernet hardware address. */
773d2021 307 MAC4 = 4,
07d3f51f
FR		 308 MAR0 = 8, /* Multicast filter. */
309 CounterAddrLow = 0x10,
310 CounterAddrHigh = 0x14,
311 TxDescStartAddrLow = 0x20,
312 TxDescStartAddrHigh = 0x24,
313 TxHDescStartAddrLow = 0x28,
314 TxHDescStartAddrHigh = 0x2c,
315 FLASH = 0x30,
316 ERSR = 0x36,
317 ChipCmd = 0x37,
318 TxPoll = 0x38,
319 IntrMask = 0x3c,
320 IntrStatus = 0x3e,
4f6b00e5 321
07d3f51f 322 TxConfig = 0x40,
4f6b00e5
HW		 323#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
324#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 325
4f6b00e5
HW		 326 RxConfig = 0x44,
327#define RX128_INT_EN (1 << 15) /* 8111c and later */
328#define RX_MULTI_EN (1 << 14) /* 8111c only */
329#define RXCFG_FIFO_SHIFT 13
330 /* No threshold before first PCI xfer */
331#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
332#define RXCFG_DMA_SHIFT 8
333 /* Unlimited maximum PCI burst. */
334#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 335
07d3f51f
FR		 336 RxMissed = 0x4c,
337 Cfg9346 = 0x50,
338 Config0 = 0x51,
339 Config1 = 0x52,
340 Config2 = 0x53,
d387b427
FR		 341#define PME_SIGNAL (1 << 5) /* 8168c and later */
342
07d3f51f
FR		 343 Config3 = 0x54,
344 Config4 = 0x55,
345 Config5 = 0x56,
346 MultiIntr = 0x5c,
347 PHYAR = 0x60,
07d3f51f
FR		 348 PHYstatus = 0x6c,
349 RxMaxSize = 0xda,
350 CPlusCmd = 0xe0,
351 IntrMitigate = 0xe2,
352 RxDescAddrLow = 0xe4,
353 RxDescAddrHigh = 0xe8,
f0298f81 354 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
355
356#define NoEarlyTx 0x3f /* Max value : no early transmit. */
357
358 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
359
360#define TxPacketMax (8064 >> 7)
3090bd9a 361#define EarlySize 0x27
f0298f81 362
07d3f51f
FR		 363 FuncEvent = 0xf0,
364 FuncEventMask = 0xf4,
365 FuncPresetState = 0xf8,
366 FuncForceEvent = 0xfc,
1da177e4
LT		 367};
368
f162a5d1
FR		 369enum rtl8110_registers {
370 TBICSR = 0x64,
371 TBI_ANAR = 0x68,
372 TBI_LPAR = 0x6a,
373};
374
375enum rtl8168_8101_registers {
376 CSIDR = 0x64,
377 CSIAR = 0x68,
378#define CSIAR_FLAG 0x80000000
379#define CSIAR_WRITE_CMD 0x80000000
380#define CSIAR_BYTE_ENABLE 0x0f
381#define CSIAR_BYTE_ENABLE_SHIFT 12
382#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 383#define CSIAR_FUNC_CARD 0x00000000
384#define CSIAR_FUNC_SDIO 0x00010000
385#define CSIAR_FUNC_NIC 0x00020000
065c27c1 386 PMCH = 0x6f,
f162a5d1
FR		 387 EPHYAR = 0x80,
388#define EPHYAR_FLAG 0x80000000
389#define EPHYAR_WRITE_CMD 0x80000000
390#define EPHYAR_REG_MASK 0x1f
391#define EPHYAR_REG_SHIFT 16
392#define EPHYAR_DATA_MASK 0xffff
5a5e4443 393 DLLPR = 0xd0,
4f6b00e5 394#define PFM_EN (1 << 6)
f162a5d1
FR		 395 DBG_REG = 0xd1,
396#define FIX_NAK_1 (1 << 4)
397#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 398 TWSI = 0xd2,
399 MCU = 0xd3,
4f6b00e5 400#define NOW_IS_OOB (1 << 7)
c558386b
HW		 401#define TX_EMPTY (1 << 5)
402#define RX_EMPTY (1 << 4)
403#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 404#define EN_NDP (1 << 3)
405#define EN_OOB_RESET (1 << 2)
c558386b 406#define LINK_LIST_RDY (1 << 1)
daf9df6d 407 EFUSEAR = 0xdc,
408#define EFUSEAR_FLAG 0x80000000
409#define EFUSEAR_WRITE_CMD 0x80000000
410#define EFUSEAR_READ_CMD 0x00000000
411#define EFUSEAR_REG_MASK 0x03ff
412#define EFUSEAR_REG_SHIFT 8
413#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 414};
415
c0e45c1c 416enum rtl8168_registers {
4f6b00e5
HW		 417 LED_FREQ = 0x1a,
418 EEE_LED = 0x1b,
b646d900 419 ERIDR = 0x70,
420 ERIAR = 0x74,
421#define ERIAR_FLAG 0x80000000
422#define ERIAR_WRITE_CMD 0x80000000
423#define ERIAR_READ_CMD 0x00000000
424#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 425#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 426#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
427#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
428#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
429#define ERIAR_MASK_SHIFT 12
430#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
431#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 432#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 433#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 434 EPHY_RXER_NUM = 0x7c,
435 OCPDR = 0xb0, /* OCP GPHY access */
436#define OCPDR_WRITE_CMD 0x80000000
437#define OCPDR_READ_CMD 0x00000000
438#define OCPDR_REG_MASK 0x7f
439#define OCPDR_GPHY_REG_SHIFT 16
440#define OCPDR_DATA_MASK 0xffff
441 OCPAR = 0xb4,
442#define OCPAR_FLAG 0x80000000
443#define OCPAR_GPHY_WRITE_CMD 0x8000f060
444#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 445 GPHY_OCP = 0xb8,
01dc7fec 446 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
447 MISC = 0xf0, /* 8168e only. */
cecb5fd7 448#define TXPLA_RST (1 << 29)
5598bfe5 449#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 450#define PWM_EN (1 << 22)
c558386b 451#define RXDV_GATED_EN (1 << 19)
5598bfe5 452#define EARLY_TALLY_EN (1 << 16)
d64ec841 453#define FORCE_CLK (1 << 15) /* force clock request */
c0e45c1c 454};
455
07d3f51f 456enum rtl_register_content {
1da177e4 457 /* InterruptStatusBits */
07d3f51f
FR		 458 SYSErr = 0x8000,
459 PCSTimeout = 0x4000,
460 SWInt = 0x0100,
461 TxDescUnavail = 0x0080,
462 RxFIFOOver = 0x0040,
463 LinkChg = 0x0020,
464 RxOverflow = 0x0010,
465 TxErr = 0x0008,
466 TxOK = 0x0004,
467 RxErr = 0x0002,
468 RxOK = 0x0001,
1da177e4
LT		 469
470 /* RxStatusDesc */
e03f33af 471 RxBOVF = (1 << 24),
9dccf611
FR		 472 RxFOVF = (1 << 23),
473 RxRWT = (1 << 22),
474 RxRES = (1 << 21),
475 RxRUNT = (1 << 20),
476 RxCRC = (1 << 19),
1da177e4
LT		 477
478 /* ChipCmdBits */
4f6b00e5 479 StopReq = 0x80,
07d3f51f
FR		 480 CmdReset = 0x10,
481 CmdRxEnb = 0x08,
482 CmdTxEnb = 0x04,
483 RxBufEmpty = 0x01,
1da177e4 484
275391a4
FR		 485 /* TXPoll register p.5 */
486 HPQ = 0x80, /* Poll cmd on the high prio queue */
487 NPQ = 0x40, /* Poll cmd on the low prio queue */
488 FSWInt = 0x01, /* Forced software interrupt */
489
1da177e4 490 /* Cfg9346Bits */
07d3f51f
FR		 491 Cfg9346_Lock = 0x00,
492 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 493
494 /* rx_mode_bits */
07d3f51f
FR		 495 AcceptErr = 0x20,
496 AcceptRunt = 0x10,
497 AcceptBroadcast = 0x08,
498 AcceptMulticast = 0x04,
499 AcceptMyPhys = 0x02,
500 AcceptAllPhys = 0x01,
1687b566 501#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 502
1da177e4
LT		 503 /* TxConfigBits */
504 TxInterFrameGapShift = 24,
505 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
506
5d06a99f 507 /* Config1 register p.24 */
f162a5d1
FR		 508 LEDS1 = (1 << 7),
509 LEDS0 = (1 << 6),
f162a5d1
FR		 510 Speed_down = (1 << 4),
511 MEMMAP = (1 << 3),
512 IOMAP = (1 << 2),
513 VPD = (1 << 1),
5d06a99f
FR		 514 PMEnable = (1 << 0), /* Power Management Enable */
515
6dccd16b 516 /* Config2 register p. 25 */
d64ec841 517 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 518 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 519 PCI_Clock_66MHz = 0x01,
520 PCI_Clock_33MHz = 0x00,
521
61a4dcc2
FR		 522 /* Config3 register p.25 */
523 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
524 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 525 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 526 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 527
d58d46b5
FR		 528 /* Config4 register */
529 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
530
5d06a99f 531 /* Config5 register p.27 */
61a4dcc2
FR		 532 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
533 MWF = (1 << 5), /* Accept Multicast wakeup frame */
534 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 535 Spi_en = (1 << 3),
61a4dcc2 536 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 537 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
d64ec841 538 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 539
1da177e4
LT		 540 /* TBICSR p.28 */
541 TBIReset = 0x80000000,
542 TBILoopback = 0x40000000,
543 TBINwEnable = 0x20000000,
544 TBINwRestart = 0x10000000,
545 TBILinkOk = 0x02000000,
546 TBINwComplete = 0x01000000,
547
548 /* CPlusCmd p.31 */
f162a5d1
FR		 549 EnableBist = (1 << 15), // 8168 8101
550 Mac_dbgo_oe = (1 << 14), // 8168 8101
551 Normal_mode = (1 << 13), // unused
552 Force_half_dup = (1 << 12), // 8168 8101
553 Force_rxflow_en = (1 << 11), // 8168 8101
554 Force_txflow_en = (1 << 10), // 8168 8101
555 Cxpl_dbg_sel = (1 << 9), // 8168 8101
556 ASF = (1 << 8), // 8168 8101
557 PktCntrDisable = (1 << 7), // 8168 8101
558 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 559 RxVlan = (1 << 6),
560 RxChkSum = (1 << 5),
561 PCIDAC = (1 << 4),
562 PCIMulRW = (1 << 3),
0e485150
FR		 563 INTT_0 = 0x0000, // 8168
564 INTT_1 = 0x0001, // 8168
565 INTT_2 = 0x0002, // 8168
566 INTT_3 = 0x0003, // 8168
1da177e4
LT		 567
568 /* rtl8169_PHYstatus */
07d3f51f
FR		 569 TBI_Enable = 0x80,
570 TxFlowCtrl = 0x40,
571 RxFlowCtrl = 0x20,
572 _1000bpsF = 0x10,
573 _100bps = 0x08,
574 _10bps = 0x04,
575 LinkStatus = 0x02,
576 FullDup = 0x01,
1da177e4 577
1da177e4 578 /* _TBICSRBit */
07d3f51f 579 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 580
581 /* DumpCounterCommand */
07d3f51f 582 CounterDump = 0x8,
1da177e4
LT		 583};
584
2b7b4318
FR		 585enum rtl_desc_bit {
586 /* First doubleword. */
1da177e4
LT		 587 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
588 RingEnd = (1 << 30), /* End of descriptor ring */
589 FirstFrag = (1 << 29), /* First segment of a packet */
590 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 591};
592
593/* Generic case. */
594enum rtl_tx_desc_bit {
595 /* First doubleword. */
596 TD_LSO = (1 << 27), /* Large Send Offload */
597#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 598
2b7b4318
FR		 599 /* Second doubleword. */
600 TxVlanTag = (1 << 17), /* Add VLAN tag */
601};
602
603/* 8169, 8168b and 810x except 8102e. */
604enum rtl_tx_desc_bit_0 {
605 /* First doubleword. */
606#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
607 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
608 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
609 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
610};
611
612/* 8102e, 8168c and beyond. */
613enum rtl_tx_desc_bit_1 {
614 /* Second doubleword. */
615#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
616 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
617 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
618 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
619};
1da177e4 620
2b7b4318
FR		 621static const struct rtl_tx_desc_info {
622 struct {
623 u32 udp;
624 u32 tcp;
625 } checksum;
626 u16 mss_shift;
627 u16 opts_offset;
628} tx_desc_info [] = {
629 [RTL_TD_0] = {
630 .checksum = {
631 .udp = TD0_IP_CS | TD0_UDP_CS,
632 .tcp = TD0_IP_CS | TD0_TCP_CS
633 },
634 .mss_shift = TD0_MSS_SHIFT,
635 .opts_offset = 0
636 },
637 [RTL_TD_1] = {
638 .checksum = {
639 .udp = TD1_IP_CS | TD1_UDP_CS,
640 .tcp = TD1_IP_CS | TD1_TCP_CS
641 },
642 .mss_shift = TD1_MSS_SHIFT,
643 .opts_offset = 1
644 }
645};
646
647enum rtl_rx_desc_bit {
1da177e4
LT		 648 /* Rx private */
649 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
650 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
651
652#define RxProtoUDP (PID1)
653#define RxProtoTCP (PID0)
654#define RxProtoIP (PID1 | PID0)
655#define RxProtoMask RxProtoIP
656
657 IPFail = (1 << 16), /* IP checksum failed */
658 UDPFail = (1 << 15), /* UDP/IP checksum failed */
659 TCPFail = (1 << 14), /* TCP/IP checksum failed */
660 RxVlanTag = (1 << 16), /* VLAN tag available */
661};
662
663#define RsvdMask 0x3fffc000
664
665struct TxDesc {
6cccd6e7
REB		 666 __le32 opts1;
667 __le32 opts2;
668 __le64 addr;
1da177e4
LT		 669};
670
671struct RxDesc {
6cccd6e7
REB		 672 __le32 opts1;
673 __le32 opts2;
674 __le64 addr;
1da177e4
LT		 675};
676
677struct ring_info {
678 struct sk_buff *skb;
679 u32 len;
680 u8 __pad[sizeof(void *) - sizeof(u32)];
681};
682
f23e7fda 683enum features {
ccdffb9a
FR		 684 RTL_FEATURE_WOL = (1 << 0),
685 RTL_FEATURE_MSI = (1 << 1),
686 RTL_FEATURE_GMII = (1 << 2),
e0c07557 687 RTL_FEATURE_FW_LOADED = (1 << 3),
f23e7fda
FR		 688};
689
355423d0
IV		 690struct rtl8169_counters {
691 __le64 tx_packets;
692 __le64 rx_packets;
693 __le64 tx_errors;
694 __le32 rx_errors;
695 __le16 rx_missed;
696 __le16 align_errors;
697 __le32 tx_one_collision;
698 __le32 tx_multi_collision;
699 __le64 rx_unicast;
700 __le64 rx_broadcast;
701 __le32 rx_multicast;
702 __le16 tx_aborted;
703 __le16 tx_underun;
704};
705
da78dbff 706enum rtl_flag {
6c4a70c5 707 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 708 RTL_FLAG_TASK_SLOW_PENDING,
709 RTL_FLAG_TASK_RESET_PENDING,
710 RTL_FLAG_TASK_PHY_PENDING,
711 RTL_FLAG_MAX
712};
713
8027aa24
JW		 714struct rtl8169_stats {
715 u64 packets;
716 u64 bytes;
717 struct u64_stats_sync syncp;
718};
719
1da177e4
LT		 720struct rtl8169_private {
721 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 722 struct pci_dev *pci_dev;
c4028958 723 struct net_device *dev;
bea3348e 724 struct napi_struct napi;
b57b7e5a 725 u32 msg_enable;
2b7b4318
FR		 726 u16 txd_version;
727 u16 mac_version;
1da177e4
LT		 728 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
729 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
730 u32 dirty_rx;
731 u32 dirty_tx;
8027aa24
JW		 732 struct rtl8169_stats rx_stats;
733 struct rtl8169_stats tx_stats;
1da177e4
LT		 734 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
735 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
736 dma_addr_t TxPhyAddr;
737 dma_addr_t RxPhyAddr;
6f0333b8 738 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 739 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 740 struct timer_list timer;
741 u16 cp_cmd;
da78dbff
FR		 742
743 u16 event_slow;
c0e45c1c 744
745 struct mdio_ops {
24192210
FR		 746 void (*write)(struct rtl8169_private *, int, int);
747 int (*read)(struct rtl8169_private *, int);
c0e45c1c 748 } mdio_ops;
749
065c27c1 750 struct pll_power_ops {
751 void (*down)(struct rtl8169_private *);
752 void (*up)(struct rtl8169_private *);
753 } pll_power_ops;
754
d58d46b5
FR		 755 struct jumbo_ops {
756 void (*enable)(struct rtl8169_private *);
757 void (*disable)(struct rtl8169_private *);
758 } jumbo_ops;
759
beb1fe18 760 struct csi_ops {
52989f0e
FR		 761 void (*write)(struct rtl8169_private *, int, int);
762 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 763 } csi_ops;
764
54405cde 765 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 766 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 767 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 768 void (*hw_start)(struct net_device *);
4da19633 769 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 770 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 771 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 772
773 struct {
da78dbff
FR		 774 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
775 struct mutex mutex;
4422bcd4
FR		 776 struct work_struct work;
777 } wk;
778
f23e7fda 779 unsigned features;
ccdffb9a
FR		 780
781 struct mii_if_info mii;
355423d0 782 struct rtl8169_counters counters;
e1759441 783 u32 saved_wolopts;
e03f33af 784 u32 opts1_mask;
f1e02ed1 785
b6ffd97f
FR		 786 struct rtl_fw {
787 const struct firmware *fw;
1c361efb
FR		 788
789#define RTL_VER_SIZE 32
790
791 char version[RTL_VER_SIZE];
792
793 struct rtl_fw_phy_action {
794 __le32 *code;
795 size_t size;
796 } phy_action;
b6ffd97f 797 } *rtl_fw;
497888cf 798#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 799
800 u32 ocp_base;
1da177e4
LT		 801};
802
979b6c13 803MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 804MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 805module_param(use_dac, int, 0);
4300e8c7 806MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 807module_param_named(debug, debug.msg_enable, int, 0);
808MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 809MODULE_LICENSE("GPL");
810MODULE_VERSION(RTL8169_VERSION);
bca03d5f 811MODULE_FIRMWARE(FIRMWARE_8168D_1);
812MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 813MODULE_FIRMWARE(FIRMWARE_8168E_1);
814MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 815MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 816MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 817MODULE_FIRMWARE(FIRMWARE_8168F_1);
818MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 819MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 820MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 821MODULE_FIRMWARE(FIRMWARE_8106E_1);
c558386b 822MODULE_FIRMWARE(FIRMWARE_8168G_1);
1da177e4 823
da78dbff
FR		 824static void rtl_lock_work(struct rtl8169_private *tp)
825{
826 mutex_lock(&tp->wk.mutex);
827}
828
829static void rtl_unlock_work(struct rtl8169_private *tp)
830{
831 mutex_unlock(&tp->wk.mutex);
832}
833
d58d46b5
FR		 834static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
835{
7d7903b2
JL		 836 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
837 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 838}
839
ffc46952
FR		 840struct rtl_cond {
841 bool (*check)(struct rtl8169_private *);
842 const char *msg;
843};
844
845static void rtl_udelay(unsigned int d)
846{
847 udelay(d);
848}
849
850static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
851 void (*delay)(unsigned int), unsigned int d, int n,
852 bool high)
853{
854 int i;
855
856 for (i = 0; i < n; i++) {
857 delay(d);
858 if (c->check(tp) == high)
859 return true;
860 }
82e316ef
FR		 861 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
862 c->msg, !high, n, d);
ffc46952
FR		 863 return false;
864}
865
866static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
867 const struct rtl_cond *c,
868 unsigned int d, int n)
869{
870 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
871}
872
873static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
874 const struct rtl_cond *c,
875 unsigned int d, int n)
876{
877 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
878}
879
880static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
881 const struct rtl_cond *c,
882 unsigned int d, int n)
883{
884 return rtl_loop_wait(tp, c, msleep, d, n, true);
885}
886
887static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
888 const struct rtl_cond *c,
889 unsigned int d, int n)
890{
891 return rtl_loop_wait(tp, c, msleep, d, n, false);
892}
893
894#define DECLARE_RTL_COND(name) \
895static bool name ## _check(struct rtl8169_private *); \
896 \
897static const struct rtl_cond name = { \
898 .check = name ## _check, \
899 .msg = #name \
900}; \
901 \
902static bool name ## _check(struct rtl8169_private *tp)
903
904DECLARE_RTL_COND(rtl_ocpar_cond)
905{
906 void __iomem *ioaddr = tp->mmio_addr;
907
908 return RTL_R32(OCPAR) & OCPAR_FLAG;
909}
910
b646d900 911static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
912{
913 void __iomem *ioaddr = tp->mmio_addr;
b646d900 914
915 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 916
917 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
918 RTL_R32(OCPDR) : ~0;
b646d900 919}
920
921static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
922{
923 void __iomem *ioaddr = tp->mmio_addr;
b646d900 924
925 RTL_W32(OCPDR, data);
926 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 927
928 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
929}
930
931DECLARE_RTL_COND(rtl_eriar_cond)
932{
933 void __iomem *ioaddr = tp->mmio_addr;
934
935 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 936}
937
fac5b3ca 938static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 939{
fac5b3ca 940 void __iomem *ioaddr = tp->mmio_addr;
b646d900 941
942 RTL_W8(ERIDR, cmd);
943 RTL_W32(ERIAR, 0x800010e8);
944 msleep(2);
ffc46952
FR		 945
946 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
947 return;
b646d900 948
fac5b3ca 949 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 950}
951
952#define OOB_CMD_RESET 0x00
953#define OOB_CMD_DRIVER_START 0x05
954#define OOB_CMD_DRIVER_STOP 0x06
955
cecb5fd7
FR		 956static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
957{
958 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
959}
960
ffc46952 961DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 962{
cecb5fd7 963 u16 reg;
b646d900 964
cecb5fd7 965 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 966
ffc46952 967 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 968}
969
ffc46952 970static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 971{
ffc46952 972 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 973
ffc46952
FR		 974 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
975}
b646d900 976
ffc46952
FR		 977static void rtl8168_driver_stop(struct rtl8169_private *tp)
978{
979 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 980
ffc46952 981 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 982}
983
4804b3b3 984static int r8168dp_check_dash(struct rtl8169_private *tp)
985{
cecb5fd7 986 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 987
cecb5fd7 988 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 989}
b646d900 990
c558386b
HW		 991static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
992{
993 if (reg & 0xffff0001) {
994 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
995 return true;
996 }
997 return false;
998}
999
1000DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1001{
1002 void __iomem *ioaddr = tp->mmio_addr;
1003
1004 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1005}
1006
1007static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1008{
1009 void __iomem *ioaddr = tp->mmio_addr;
1010
1011 if (rtl_ocp_reg_failure(tp, reg))
1012 return;
1013
1014 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1015
1016 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1017}
1018
1019static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1020{
1021 void __iomem *ioaddr = tp->mmio_addr;
1022
1023 if (rtl_ocp_reg_failure(tp, reg))
1024 return 0;
1025
1026 RTL_W32(GPHY_OCP, reg << 15);
1027
1028 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1029 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1030}
1031
1032static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
1033{
1034 int val;
1035
1036 val = r8168_phy_ocp_read(tp, reg);
1037 r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
1038}
1039
c558386b
HW		 1040static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1041{
1042 void __iomem *ioaddr = tp->mmio_addr;
1043
1044 if (rtl_ocp_reg_failure(tp, reg))
1045 return;
1046
1047 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1048}
1049
1050static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1051{
1052 void __iomem *ioaddr = tp->mmio_addr;
1053
1054 if (rtl_ocp_reg_failure(tp, reg))
1055 return 0;
1056
1057 RTL_W32(OCPDR, reg << 15);
1058
3a83ad12 1059 return RTL_R32(OCPDR);
c558386b
HW		 1060}
1061
1062#define OCP_STD_PHY_BASE 0xa400
1063
1064static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065{
1066 if (reg == 0x1f) {
1067 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1068 return;
1069 }
1070
1071 if (tp->ocp_base != OCP_STD_PHY_BASE)
1072 reg -= 0x10;
1073
1074 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1075}
1076
1077static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1078{
1079 if (tp->ocp_base != OCP_STD_PHY_BASE)
1080 reg -= 0x10;
1081
1082 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1083}
1084
ffc46952
FR		 1085DECLARE_RTL_COND(rtl_phyar_cond)
1086{
1087 void __iomem *ioaddr = tp->mmio_addr;
1088
1089 return RTL_R32(PHYAR) & 0x80000000;
1090}
1091
24192210 1092static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1093{
24192210 1094 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1095
24192210 1096 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1097
ffc46952 1098 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1099 /*
81a95f04
TT		 1100 * According to hardware specs a 20us delay is required after write
1101 * complete indication, but before sending next command.
024a07ba 1102 */
81a95f04 1103 udelay(20);
1da177e4
LT		 1104}
1105
24192210 1106static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1107{
24192210 1108 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1109 int value;
1da177e4 1110
24192210 1111 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1112
ffc46952
FR		 1113 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1114 RTL_R32(PHYAR) & 0xffff : ~0;
1115
81a95f04
TT		 1116 /*
1117 * According to hardware specs a 20us delay is required after read
1118 * complete indication, but before sending next command.
1119 */
1120 udelay(20);
1121
1da177e4
LT		 1122 return value;
1123}
1124
24192210 1125static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1126{
24192210 1127 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1128
24192210 1129 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1130 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1131 RTL_W32(EPHY_RXER_NUM, 0);
1132
ffc46952 1133 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1134}
1135
24192210 1136static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1137{
24192210
FR		 1138 r8168dp_1_mdio_access(tp, reg,
1139 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1140}
1141
24192210 1142static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1143{
24192210 1144 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1145
24192210 1146 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1147
1148 mdelay(1);
1149 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1150 RTL_W32(EPHY_RXER_NUM, 0);
1151
ffc46952
FR		 1152 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1153 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1154}
1155
e6de30d6 1156#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1157
1158static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1159{
1160 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1161}
1162
1163static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1164{
1165 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1166}
1167
24192210 1168static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1169{
24192210
FR		 1170 void __iomem *ioaddr = tp->mmio_addr;
1171
e6de30d6 1172 r8168dp_2_mdio_start(ioaddr);
1173
24192210 1174 r8169_mdio_write(tp, reg, value);
e6de30d6 1175
1176 r8168dp_2_mdio_stop(ioaddr);
1177}
1178
24192210 1179static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1180{
24192210 1181 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1182 int value;
1183
1184 r8168dp_2_mdio_start(ioaddr);
1185
24192210 1186 value = r8169_mdio_read(tp, reg);
e6de30d6 1187
1188 r8168dp_2_mdio_stop(ioaddr);
1189
1190 return value;
1191}
1192
4da19633 1193static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1194{
24192210 1195 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1196}
1197
4da19633 1198static int rtl_readphy(struct rtl8169_private *tp, int location)
1199{
24192210 1200 return tp->mdio_ops.read(tp, location);
4da19633 1201}
1202
1203static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1204{
1205 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1206}
1207
1208static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1209{
1210 int val;
1211
4da19633 1212 val = rtl_readphy(tp, reg_addr);
1213 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1214}
1215
ccdffb9a
FR		 1216static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1217 int val)
1218{
1219 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1220
4da19633 1221 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1222}
1223
1224static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1225{
1226 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1227
4da19633 1228 return rtl_readphy(tp, location);
ccdffb9a
FR		 1229}
1230
ffc46952
FR		 1231DECLARE_RTL_COND(rtl_ephyar_cond)
1232{
1233 void __iomem *ioaddr = tp->mmio_addr;
1234
1235 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1236}
1237
fdf6fc06 1238static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1239{
fdf6fc06 1240 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1241
1242 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1243 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1244
ffc46952
FR		 1245 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1246
1247 udelay(10);
dacf8154
FR		 1248}
1249
fdf6fc06 1250static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1251{
fdf6fc06 1252 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1253
1254 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1255
ffc46952
FR		 1256 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1257 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1258}
1259
fdf6fc06
FR		 1260static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1261 u32 val, int type)
133ac40a 1262{
fdf6fc06 1263 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1264
1265 BUG_ON((addr & 3) || (mask == 0));
1266 RTL_W32(ERIDR, val);
1267 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1268
ffc46952 1269 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1270}
1271
fdf6fc06 1272static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1273{
fdf6fc06 1274 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1275
1276 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1277
ffc46952
FR		 1278 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1279 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1280}
1281
fdf6fc06
FR		 1282static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1283 u32 m, int type)
133ac40a
HW		 1284{
1285 u32 val;
1286
fdf6fc06
FR		 1287 val = rtl_eri_read(tp, addr, type);
1288 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1289}
1290
c28aa385 1291struct exgmac_reg {
1292 u16 addr;
1293 u16 mask;
1294 u32 val;
1295};
1296
fdf6fc06 1297static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1298 const struct exgmac_reg *r, int len)
1299{
1300 while (len-- > 0) {
fdf6fc06 1301 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1302 r++;
1303 }
1304}
1305
ffc46952
FR		 1306DECLARE_RTL_COND(rtl_efusear_cond)
1307{
1308 void __iomem *ioaddr = tp->mmio_addr;
1309
1310 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1311}
1312
fdf6fc06 1313static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1314{
fdf6fc06 1315 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1316
1317 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1318
ffc46952
FR		 1319 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1320 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1321}
1322
9085cdfa
FR		 1323static u16 rtl_get_events(struct rtl8169_private *tp)
1324{
1325 void __iomem *ioaddr = tp->mmio_addr;
1326
1327 return RTL_R16(IntrStatus);
1328}
1329
1330static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1331{
1332 void __iomem *ioaddr = tp->mmio_addr;
1333
1334 RTL_W16(IntrStatus, bits);
1335 mmiowb();
1336}
1337
1338static void rtl_irq_disable(struct rtl8169_private *tp)
1339{
1340 void __iomem *ioaddr = tp->mmio_addr;
1341
1342 RTL_W16(IntrMask, 0);
1343 mmiowb();
1344}
1345
3e990ff5
FR		 1346static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1347{
1348 void __iomem *ioaddr = tp->mmio_addr;
1349
1350 RTL_W16(IntrMask, bits);
1351}
1352
da78dbff
FR		 1353#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1354#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1355#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1356
1357static void rtl_irq_enable_all(struct rtl8169_private *tp)
1358{
1359 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1360}
1361
811fd301 1362static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1363{
811fd301 1364 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1365
9085cdfa 1366 rtl_irq_disable(tp);
da78dbff 1367 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1368 RTL_R8(ChipCmd);
1da177e4
LT		 1369}
1370
4da19633 1371static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1372{
4da19633 1373 void __iomem *ioaddr = tp->mmio_addr;
1374
1da177e4
LT		 1375 return RTL_R32(TBICSR) & TBIReset;
1376}
1377
4da19633 1378static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1379{
4da19633 1380 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1381}
1382
1383static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1384{
1385 return RTL_R32(TBICSR) & TBILinkOk;
1386}
1387
1388static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1389{
1390 return RTL_R8(PHYstatus) & LinkStatus;
1391}
1392
4da19633 1393static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1394{
4da19633 1395 void __iomem *ioaddr = tp->mmio_addr;
1396
1da177e4
LT		 1397 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1398}
1399
4da19633 1400static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1401{
1402 unsigned int val;
1403
4da19633 1404 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1405 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1406}
1407
70090424
HW		 1408static void rtl_link_chg_patch(struct rtl8169_private *tp)
1409{
1410 void __iomem *ioaddr = tp->mmio_addr;
1411 struct net_device *dev = tp->dev;
1412
1413 if (!netif_running(dev))
1414 return;
1415
b3d7b2f2
HW		 1416 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1417 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1418 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1419 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1420 ERIAR_EXGMAC);
1421 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1422 ERIAR_EXGMAC);
70090424 1423 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1424 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1425 ERIAR_EXGMAC);
1426 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1427 ERIAR_EXGMAC);
70090424 1428 } else {
fdf6fc06
FR		 1429 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1430 ERIAR_EXGMAC);
1431 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1432 ERIAR_EXGMAC);
70090424
HW		 1433 }
1434 /* Reset packet filter */
fdf6fc06 1435 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1436 ERIAR_EXGMAC);
fdf6fc06 1437 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1438 ERIAR_EXGMAC);
c2218925
HW		 1439 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1440 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1441 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1442 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1443 ERIAR_EXGMAC);
1444 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1445 ERIAR_EXGMAC);
c2218925 1446 } else {
fdf6fc06
FR		 1447 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1448 ERIAR_EXGMAC);
1449 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1450 ERIAR_EXGMAC);
c2218925 1451 }
7e18dca1
HW		 1452 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1453 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1454 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1455 ERIAR_EXGMAC);
1456 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1457 ERIAR_EXGMAC);
7e18dca1 1458 } else {
fdf6fc06
FR		 1459 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1460 ERIAR_EXGMAC);
7e18dca1 1461 }
70090424
HW		 1462 }
1463}
1464
e4fbce74 1465static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1466 struct rtl8169_private *tp,
1467 void __iomem *ioaddr, bool pm)
1da177e4 1468{
1da177e4 1469 if (tp->link_ok(ioaddr)) {
70090424 1470 rtl_link_chg_patch(tp);
e1759441 1471 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1472 if (pm)
1473 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1474 netif_carrier_on(dev);
1519e57f
FR		 1475 if (net_ratelimit())
1476 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1477 } else {
1da177e4 1478 netif_carrier_off(dev);
bf82c189 1479 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1480 if (pm)
10953db8 1481 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1482 }
1da177e4
LT		 1483}
1484
e4fbce74
RW		 1485static void rtl8169_check_link_status(struct net_device *dev,
1486 struct rtl8169_private *tp,
1487 void __iomem *ioaddr)
1488{
1489 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1490}
1491
e1759441
RW		 1492#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1493
1494static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1495{
61a4dcc2
FR		 1496 void __iomem *ioaddr = tp->mmio_addr;
1497 u8 options;
e1759441 1498 u32 wolopts = 0;
61a4dcc2
FR		 1499
1500 options = RTL_R8(Config1);
1501 if (!(options & PMEnable))
e1759441 1502 return 0;
61a4dcc2
FR		 1503
1504 options = RTL_R8(Config3);
1505 if (options & LinkUp)
e1759441 1506 wolopts |= WAKE_PHY;
61a4dcc2 1507 if (options & MagicPacket)
e1759441 1508 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1509
1510 options = RTL_R8(Config5);
1511 if (options & UWF)
e1759441 1512 wolopts |= WAKE_UCAST;
61a4dcc2 1513 if (options & BWF)
e1759441 1514 wolopts |= WAKE_BCAST;
61a4dcc2 1515 if (options & MWF)
e1759441 1516 wolopts |= WAKE_MCAST;
61a4dcc2 1517
e1759441 1518 return wolopts;
61a4dcc2
FR		 1519}
1520
e1759441 1521static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1522{
1523 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1524
da78dbff 1525 rtl_lock_work(tp);
e1759441
RW		 1526
1527 wol->supported = WAKE_ANY;
1528 wol->wolopts = __rtl8169_get_wol(tp);
1529
da78dbff 1530 rtl_unlock_work(tp);
e1759441
RW		 1531}
1532
1533static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1534{
61a4dcc2 1535 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1536 unsigned int i;
350f7596 1537 static const struct {
61a4dcc2
FR		 1538 u32 opt;
1539 u16 reg;
1540 u8 mask;
1541 } cfg[] = {
61a4dcc2
FR		 1542 { WAKE_PHY, Config3, LinkUp },
1543 { WAKE_MAGIC, Config3, MagicPacket },
1544 { WAKE_UCAST, Config5, UWF },
1545 { WAKE_BCAST, Config5, BWF },
1546 { WAKE_MCAST, Config5, MWF },
1547 { WAKE_ANY, Config5, LanWake }
1548 };
851e6022 1549 u8 options;
61a4dcc2 1550
61a4dcc2
FR		 1551 RTL_W8(Cfg9346, Cfg9346_Unlock);
1552
1553 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1554 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1555 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1556 options |= cfg[i].mask;
1557 RTL_W8(cfg[i].reg, options);
1558 }
1559
851e6022
FR		 1560 switch (tp->mac_version) {
1561 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1562 options = RTL_R8(Config1) & ~PMEnable;
1563 if (wolopts)
1564 options |= PMEnable;
1565 RTL_W8(Config1, options);
1566 break;
1567 default:
d387b427
FR		 1568 options = RTL_R8(Config2) & ~PME_SIGNAL;
1569 if (wolopts)
1570 options |= PME_SIGNAL;
1571 RTL_W8(Config2, options);
851e6022
FR		 1572 break;
1573 }
1574
61a4dcc2 1575 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1576}
1577
1578static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1579{
1580 struct rtl8169_private *tp = netdev_priv(dev);
1581
da78dbff 1582 rtl_lock_work(tp);
61a4dcc2 1583
f23e7fda
FR		 1584 if (wol->wolopts)
1585 tp->features |= RTL_FEATURE_WOL;
1586 else
1587 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1588 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1589
1590 rtl_unlock_work(tp);
61a4dcc2 1591
ea80907f 1592 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1593
61a4dcc2
FR		 1594 return 0;
1595}
1596
31bd204f
FR		 1597static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1598{
85bffe6c 1599 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1600}
1601
1da177e4
LT		 1602static void rtl8169_get_drvinfo(struct net_device *dev,
1603 struct ethtool_drvinfo *info)
1604{
1605 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1606 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1607
68aad78c
RJ		 1608 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1609 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1610 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1611 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1612 if (!IS_ERR_OR_NULL(rtl_fw))
1613 strlcpy(info->fw_version, rtl_fw->version,
1614 sizeof(info->fw_version));
1da177e4
LT		 1615}
1616
1617static int rtl8169_get_regs_len(struct net_device *dev)
1618{
1619 return R8169_REGS_SIZE;
1620}
1621
1622static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1623 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1624{
1625 struct rtl8169_private *tp = netdev_priv(dev);
1626 void __iomem *ioaddr = tp->mmio_addr;
1627 int ret = 0;
1628 u32 reg;
1629
1630 reg = RTL_R32(TBICSR);
1631 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1632 (duplex == DUPLEX_FULL)) {
1633 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1634 } else if (autoneg == AUTONEG_ENABLE)
1635 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1636 else {
bf82c189
JP		 1637 netif_warn(tp, link, dev,
1638 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1639 ret = -EOPNOTSUPP;
1640 }
1641
1642 return ret;
1643}
1644
1645static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1646 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1647{
1648 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1649 int giga_ctrl, bmcr;
54405cde 1650 int rc = -EINVAL;
1da177e4 1651
716b50a3 1652 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1653
1654 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1655 int auto_nego;
1656
4da19633 1657 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1658 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1659 ADVERTISE_100HALF | ADVERTISE_100FULL);
1660
1661 if (adv & ADVERTISED_10baseT_Half)
1662 auto_nego |= ADVERTISE_10HALF;
1663 if (adv & ADVERTISED_10baseT_Full)
1664 auto_nego |= ADVERTISE_10FULL;
1665 if (adv & ADVERTISED_100baseT_Half)
1666 auto_nego |= ADVERTISE_100HALF;
1667 if (adv & ADVERTISED_100baseT_Full)
1668 auto_nego |= ADVERTISE_100FULL;
1669
3577aa1b 1670 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1671
4da19633 1672 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1673 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1674
3577aa1b 1675 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1676 if (tp->mii.supports_gmii) {
54405cde
ON		 1677 if (adv & ADVERTISED_1000baseT_Half)
1678 giga_ctrl |= ADVERTISE_1000HALF;
1679 if (adv & ADVERTISED_1000baseT_Full)
1680 giga_ctrl |= ADVERTISE_1000FULL;
1681 } else if (adv & (ADVERTISED_1000baseT_Half |
1682 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1683 netif_info(tp, link, dev,
1684 "PHY does not support 1000Mbps\n");
54405cde 1685 goto out;
bcf0bf90 1686 }
1da177e4 1687
3577aa1b 1688 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1689
4da19633 1690 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1691 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1692 } else {
1693 giga_ctrl = 0;
1694
1695 if (speed == SPEED_10)
1696 bmcr = 0;
1697 else if (speed == SPEED_100)
1698 bmcr = BMCR_SPEED100;
1699 else
54405cde 1700 goto out;
3577aa1b 1701
1702 if (duplex == DUPLEX_FULL)
1703 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1704 }
1705
4da19633 1706 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1707
cecb5fd7
FR		 1708 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1709 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1710 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1711 rtl_writephy(tp, 0x17, 0x2138);
1712 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1713 } else {
4da19633 1714 rtl_writephy(tp, 0x17, 0x2108);
1715 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1716 }
1717 }
1718
54405cde
ON		 1719 rc = 0;
1720out:
1721 return rc;
1da177e4
LT		 1722}
1723
1724static int rtl8169_set_speed(struct net_device *dev,
54405cde 1725 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1726{
1727 struct rtl8169_private *tp = netdev_priv(dev);
1728 int ret;
1729
54405cde 1730 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1731 if (ret < 0)
1732 goto out;
1da177e4 1733
4876cc1e
FR		 1734 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1735 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1736 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1737 }
1738out:
1da177e4
LT		 1739 return ret;
1740}
1741
1742static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1743{
1744 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1745 int ret;
1746
4876cc1e
FR		 1747 del_timer_sync(&tp->timer);
1748
da78dbff 1749 rtl_lock_work(tp);
cecb5fd7 1750 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1751 cmd->duplex, cmd->advertising);
da78dbff 1752 rtl_unlock_work(tp);
5b0384f4 1753
1da177e4
LT		 1754 return ret;
1755}
1756
c8f44aff
MM		 1757static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1758 netdev_features_t features)
1da177e4 1759{
d58d46b5
FR		 1760 struct rtl8169_private *tp = netdev_priv(dev);
1761
2b7b4318 1762 if (dev->mtu > TD_MSS_MAX)
350fb32a 1763 features &= ~NETIF_F_ALL_TSO;
1da177e4 1764
d58d46b5
FR		 1765 if (dev->mtu > JUMBO_1K &&
1766 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1767 features &= ~NETIF_F_IP_CSUM;
1768
350fb32a 1769 return features;
1da177e4
LT		 1770}
1771
da78dbff
FR		 1772static void __rtl8169_set_features(struct net_device *dev,
1773 netdev_features_t features)
1da177e4
LT		 1774{
1775 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1776 netdev_features_t changed = features ^ dev->features;
da78dbff 1777 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1778
6bbe021d
BG		 1779 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1780 return;
1da177e4 1781
6bbe021d
BG		 1782 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1783 if (features & NETIF_F_RXCSUM)
1784 tp->cp_cmd |= RxChkSum;
1785 else
1786 tp->cp_cmd &= ~RxChkSum;
350fb32a 1787
6bbe021d
BG		 1788 if (dev->features & NETIF_F_HW_VLAN_RX)
1789 tp->cp_cmd |= RxVlan;
1790 else
1791 tp->cp_cmd &= ~RxVlan;
1792
1793 RTL_W16(CPlusCmd, tp->cp_cmd);
1794 RTL_R16(CPlusCmd);
1795 }
1796 if (changed & NETIF_F_RXALL) {
1797 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1798 if (features & NETIF_F_RXALL)
1799 tmp |= (AcceptErr | AcceptRunt);
1800 RTL_W32(RxConfig, tmp);
1801 }
da78dbff 1802}
1da177e4 1803
da78dbff
FR		 1804static int rtl8169_set_features(struct net_device *dev,
1805 netdev_features_t features)
1806{
1807 struct rtl8169_private *tp = netdev_priv(dev);
1808
1809 rtl_lock_work(tp);
1810 __rtl8169_set_features(dev, features);
1811 rtl_unlock_work(tp);
1da177e4
LT		 1812
1813 return 0;
1814}
1815
da78dbff 1816
810f4893 1817static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1818{
eab6d18d 1819 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1820 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1821}
1822
7a8fc77b 1823static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1824{
1825 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1826
7a8fc77b
FR		 1827 if (opts2 & RxVlanTag)
1828 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1da177e4
LT		 1829}
1830
ccdffb9a 1831static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1832{
1833 struct rtl8169_private *tp = netdev_priv(dev);
1834 void __iomem *ioaddr = tp->mmio_addr;
1835 u32 status;
1836
1837 cmd->supported =
1838 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1839 cmd->port = PORT_FIBRE;
1840 cmd->transceiver = XCVR_INTERNAL;
1841
1842 status = RTL_R32(TBICSR);
1843 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1844 cmd->autoneg = !!(status & TBINwEnable);
1845
70739497 1846 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1847 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1848
1849 return 0;
1da177e4
LT		 1850}
1851
ccdffb9a 1852static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1853{
1854 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1855
1856 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1857}
1858
1859static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1860{
1861 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1862 int rc;
1da177e4 1863
da78dbff 1864 rtl_lock_work(tp);
ccdffb9a 1865 rc = tp->get_settings(dev, cmd);
da78dbff 1866 rtl_unlock_work(tp);
1da177e4 1867
ccdffb9a 1868 return rc;
1da177e4
LT		 1869}
1870
1871static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1872 void *p)
1873{
5b0384f4 1874 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1875
5b0384f4
FR		 1876 if (regs->len > R8169_REGS_SIZE)
1877 regs->len = R8169_REGS_SIZE;
1da177e4 1878
da78dbff 1879 rtl_lock_work(tp);
5b0384f4 1880 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1881 rtl_unlock_work(tp);
1da177e4
LT		 1882}
1883
b57b7e5a
SH		 1884static u32 rtl8169_get_msglevel(struct net_device *dev)
1885{
1886 struct rtl8169_private *tp = netdev_priv(dev);
1887
1888 return tp->msg_enable;
1889}
1890
1891static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1892{
1893 struct rtl8169_private *tp = netdev_priv(dev);
1894
1895 tp->msg_enable = value;
1896}
1897
d4a3a0fc
SH		 1898static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1899 "tx_packets",
1900 "rx_packets",
1901 "tx_errors",
1902 "rx_errors",
1903 "rx_missed",
1904 "align_errors",
1905 "tx_single_collisions",
1906 "tx_multi_collisions",
1907 "unicast",
1908 "broadcast",
1909 "multicast",
1910 "tx_aborted",
1911 "tx_underrun",
1912};
1913
b9f2c044 1914static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1915{
b9f2c044
JG		 1916 switch (sset) {
1917 case ETH_SS_STATS:
1918 return ARRAY_SIZE(rtl8169_gstrings);
1919 default:
1920 return -EOPNOTSUPP;
1921 }
d4a3a0fc
SH		 1922}
1923
ffc46952
FR		 1924DECLARE_RTL_COND(rtl_counters_cond)
1925{
1926 void __iomem *ioaddr = tp->mmio_addr;
1927
1928 return RTL_R32(CounterAddrLow) & CounterDump;
1929}
1930
355423d0 1931static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1932{
1933 struct rtl8169_private *tp = netdev_priv(dev);
1934 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1935 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1936 struct rtl8169_counters *counters;
1937 dma_addr_t paddr;
1938 u32 cmd;
1939
355423d0
IV		 1940 /*
1941 * Some chips are unable to dump tally counters when the receiver
1942 * is disabled.
1943 */
1944 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1945 return;
d4a3a0fc 1946
48addcc9 1947 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1948 if (!counters)
1949 return;
1950
1951 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1952 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1953 RTL_W32(CounterAddrLow, cmd);
1954 RTL_W32(CounterAddrLow, cmd | CounterDump);
1955
ffc46952
FR		 1956 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1957 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1958
1959 RTL_W32(CounterAddrLow, 0);
1960 RTL_W32(CounterAddrHigh, 0);
1961
48addcc9 1962 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1963}
1964
355423d0
IV		 1965static void rtl8169_get_ethtool_stats(struct net_device *dev,
1966 struct ethtool_stats *stats, u64 *data)
1967{
1968 struct rtl8169_private *tp = netdev_priv(dev);
1969
1970 ASSERT_RTNL();
1971
1972 rtl8169_update_counters(dev);
1973
1974 data[0] = le64_to_cpu(tp->counters.tx_packets);
1975 data[1] = le64_to_cpu(tp->counters.rx_packets);
1976 data[2] = le64_to_cpu(tp->counters.tx_errors);
1977 data[3] = le32_to_cpu(tp->counters.rx_errors);
1978 data[4] = le16_to_cpu(tp->counters.rx_missed);
1979 data[5] = le16_to_cpu(tp->counters.align_errors);
1980 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1981 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1982 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1983 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1984 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1985 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1986 data[12] = le16_to_cpu(tp->counters.tx_underun);
1987}
1988
d4a3a0fc
SH		 1989static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1990{
1991 switch(stringset) {
1992 case ETH_SS_STATS:
1993 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1994 break;
1995 }
1996}
1997
7282d491 1998static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1999 .get_drvinfo = rtl8169_get_drvinfo,
2000 .get_regs_len = rtl8169_get_regs_len,
2001 .get_link = ethtool_op_get_link,
2002 .get_settings = rtl8169_get_settings,
2003 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2004 .get_msglevel = rtl8169_get_msglevel,
2005 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2006 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2007 .get_wol = rtl8169_get_wol,
2008 .set_wol = rtl8169_set_wol,
d4a3a0fc 2009 .get_strings = rtl8169_get_strings,
b9f2c044 2010 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2011 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2012 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2013};
2014
07d3f51f 2015static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2016 struct net_device *dev, u8 default_version)
1da177e4 2017{
5d320a20 2018 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2019 /*
2020 * The driver currently handles the 8168Bf and the 8168Be identically
2021 * but they can be identified more specifically through the test below
2022 * if needed:
2023 *
2024 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2025 *
2026 * Same thing for the 8101Eb and the 8101Ec:
2027 *
2028 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2029 */
3744100e 2030 static const struct rtl_mac_info {
1da177e4 2031 u32 mask;
e3cf0cc0 2032 u32 val;
1da177e4
LT		 2033 int mac_version;
2034 } mac_info[] = {
c558386b
HW		 2035 /* 8168G family. */
2036 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2037 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2038
c2218925 2039 /* 8168F family. */
b3d7b2f2 2040 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2041 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2042 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2043
01dc7fec 2044 /* 8168E family. */
70090424 2045 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2046 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2047 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2048 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2049
5b538df9 2050 /* 8168D family. */
daf9df6d 2051 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2052 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2053 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2054
e6de30d6 2055 /* 8168DP family. */
2056 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2057 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2058 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2059
ef808d50 2060 /* 8168C family. */
17c99297 2061 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2062 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2063 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2064 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2065 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2066 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2067 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2068 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2069 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2070
2071 /* 8168B family. */
2072 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2073 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2074 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2075 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2076
2077 /* 8101 family. */
5598bfe5
HW		 2078 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2079 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2080 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2081 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2082 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2083 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2084 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2085 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2086 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2087 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2088 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2089 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2090 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2091 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2092 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2093 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2094 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2095 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2096 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2097 /* FIXME: where did these entries come from ? -- FR */
2098 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2099 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2100
2101 /* 8110 family. */
2102 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2103 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2104 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2105 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2106 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2107 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2108
f21b75e9
JD		 2109 /* Catch-all */
2110 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2111 };
2112 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2113 u32 reg;
2114
e3cf0cc0
FR		 2115 reg = RTL_R32(TxConfig);
2116 while ((reg & p->mask) != p->val)
1da177e4
LT		 2117 p++;
2118 tp->mac_version = p->mac_version;
5d320a20
FR		 2119
2120 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2121 netif_notice(tp, probe, dev,
2122 "unknown MAC, using family default\n");
2123 tp->mac_version = default_version;
2124 }
1da177e4
LT		 2125}
2126
2127static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2128{
bcf0bf90 2129 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2130}
2131
867763c1
FR		 2132struct phy_reg {
2133 u16 reg;
2134 u16 val;
2135};
2136
4da19633 2137static void rtl_writephy_batch(struct rtl8169_private *tp,
2138 const struct phy_reg *regs, int len)
867763c1
FR		 2139{
2140 while (len-- > 0) {
4da19633 2141 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2142 regs++;
2143 }
2144}
2145
bca03d5f 2146#define PHY_READ 0x00000000
2147#define PHY_DATA_OR 0x10000000
2148#define PHY_DATA_AND 0x20000000
2149#define PHY_BJMPN 0x30000000
2150#define PHY_READ_EFUSE 0x40000000
2151#define PHY_READ_MAC_BYTE 0x50000000
2152#define PHY_WRITE_MAC_BYTE 0x60000000
2153#define PHY_CLEAR_READCOUNT 0x70000000
2154#define PHY_WRITE 0x80000000
2155#define PHY_READCOUNT_EQ_SKIP 0x90000000
2156#define PHY_COMP_EQ_SKIPN 0xa0000000
2157#define PHY_COMP_NEQ_SKIPN 0xb0000000
2158#define PHY_WRITE_PREVIOUS 0xc0000000
2159#define PHY_SKIPN 0xd0000000
2160#define PHY_DELAY_MS 0xe0000000
2161#define PHY_WRITE_ERI_WORD 0xf0000000
2162
960aee6c
HW		 2163struct fw_info {
2164 u32 magic;
2165 char version[RTL_VER_SIZE];
2166 __le32 fw_start;
2167 __le32 fw_len;
2168 u8 chksum;
2169} __packed;
2170
1c361efb
FR		 2171#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2172
2173static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2174{
b6ffd97f 2175 const struct firmware *fw = rtl_fw->fw;
960aee6c 2176 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2177 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2178 char *version = rtl_fw->version;
2179 bool rc = false;
2180
2181 if (fw->size < FW_OPCODE_SIZE)
2182 goto out;
960aee6c
HW		 2183
2184 if (!fw_info->magic) {
2185 size_t i, size, start;
2186 u8 checksum = 0;
2187
2188 if (fw->size < sizeof(*fw_info))
2189 goto out;
2190
2191 for (i = 0; i < fw->size; i++)
2192 checksum += fw->data[i];
2193 if (checksum != 0)
2194 goto out;
2195
2196 start = le32_to_cpu(fw_info->fw_start);
2197 if (start > fw->size)
2198 goto out;
2199
2200 size = le32_to_cpu(fw_info->fw_len);
2201 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2202 goto out;
2203
2204 memcpy(version, fw_info->version, RTL_VER_SIZE);
2205
2206 pa->code = (__le32 *)(fw->data + start);
2207 pa->size = size;
2208 } else {
1c361efb
FR		 2209 if (fw->size % FW_OPCODE_SIZE)
2210 goto out;
2211
2212 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2213
2214 pa->code = (__le32 *)fw->data;
2215 pa->size = fw->size / FW_OPCODE_SIZE;
2216 }
2217 version[RTL_VER_SIZE - 1] = 0;
2218
2219 rc = true;
2220out:
2221 return rc;
2222}
2223
fd112f2e
FR		 2224static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2225 struct rtl_fw_phy_action *pa)
1c361efb 2226{
fd112f2e 2227 bool rc = false;
1c361efb 2228 size_t index;
bca03d5f 2229
1c361efb
FR		 2230 for (index = 0; index < pa->size; index++) {
2231 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2232 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2233
42b82dc1 2234 switch(action & 0xf0000000) {
2235 case PHY_READ:
2236 case PHY_DATA_OR:
2237 case PHY_DATA_AND:
2238 case PHY_READ_EFUSE:
2239 case PHY_CLEAR_READCOUNT:
2240 case PHY_WRITE:
2241 case PHY_WRITE_PREVIOUS:
2242 case PHY_DELAY_MS:
2243 break;
2244
2245 case PHY_BJMPN:
2246 if (regno > index) {
fd112f2e 2247 netif_err(tp, ifup, tp->dev,
cecb5fd7 2248 "Out of range of firmware\n");
fd112f2e 2249 goto out;
42b82dc1 2250 }
2251 break;
2252 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2253 if (index + 2 >= pa->size) {
fd112f2e 2254 netif_err(tp, ifup, tp->dev,
cecb5fd7 2255 "Out of range of firmware\n");
fd112f2e 2256 goto out;
42b82dc1 2257 }
2258 break;
2259 case PHY_COMP_EQ_SKIPN:
2260 case PHY_COMP_NEQ_SKIPN:
2261 case PHY_SKIPN:
1c361efb 2262 if (index + 1 + regno >= pa->size) {
fd112f2e 2263 netif_err(tp, ifup, tp->dev,
cecb5fd7 2264 "Out of range of firmware\n");
fd112f2e 2265 goto out;
42b82dc1 2266 }
bca03d5f 2267 break;
2268
42b82dc1 2269 case PHY_READ_MAC_BYTE:
2270 case PHY_WRITE_MAC_BYTE:
2271 case PHY_WRITE_ERI_WORD:
2272 default:
fd112f2e 2273 netif_err(tp, ifup, tp->dev,
42b82dc1 2274 "Invalid action 0x%08x\n", action);
fd112f2e 2275 goto out;
bca03d5f 2276 }
2277 }
fd112f2e
FR		 2278 rc = true;
2279out:
2280 return rc;
2281}
bca03d5f 2282
fd112f2e
FR		 2283static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2284{
2285 struct net_device *dev = tp->dev;
2286 int rc = -EINVAL;
2287
2288 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2289 netif_err(tp, ifup, dev, "invalid firwmare\n");
2290 goto out;
2291 }
2292
2293 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2294 rc = 0;
2295out:
2296 return rc;
2297}
2298
2299static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2300{
2301 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2302 u32 predata, count;
2303 size_t index;
2304
2305 predata = count = 0;
42b82dc1 2306
1c361efb
FR		 2307 for (index = 0; index < pa->size; ) {
2308 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2309 u32 data = action & 0x0000ffff;
42b82dc1 2310 u32 regno = (action & 0x0fff0000) >> 16;
2311
2312 if (!action)
2313 break;
bca03d5f 2314
2315 switch(action & 0xf0000000) {
42b82dc1 2316 case PHY_READ:
2317 predata = rtl_readphy(tp, regno);
2318 count++;
2319 index++;
2320 break;
2321 case PHY_DATA_OR:
2322 predata |= data;
2323 index++;
2324 break;
2325 case PHY_DATA_AND:
2326 predata &= data;
2327 index++;
2328 break;
2329 case PHY_BJMPN:
2330 index -= regno;
2331 break;
2332 case PHY_READ_EFUSE:
fdf6fc06 2333 predata = rtl8168d_efuse_read(tp, regno);
42b82dc1 2334 index++;
2335 break;
2336 case PHY_CLEAR_READCOUNT:
2337 count = 0;
2338 index++;
2339 break;
bca03d5f 2340 case PHY_WRITE:
42b82dc1 2341 rtl_writephy(tp, regno, data);
2342 index++;
2343 break;
2344 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2345 index += (count == data) ? 2 : 1;
bca03d5f 2346 break;
42b82dc1 2347 case PHY_COMP_EQ_SKIPN:
2348 if (predata == data)
2349 index += regno;
2350 index++;
2351 break;
2352 case PHY_COMP_NEQ_SKIPN:
2353 if (predata != data)
2354 index += regno;
2355 index++;
2356 break;
2357 case PHY_WRITE_PREVIOUS:
2358 rtl_writephy(tp, regno, predata);
2359 index++;
2360 break;
2361 case PHY_SKIPN:
2362 index += regno + 1;
2363 break;
2364 case PHY_DELAY_MS:
2365 mdelay(data);
2366 index++;
2367 break;
2368
2369 case PHY_READ_MAC_BYTE:
2370 case PHY_WRITE_MAC_BYTE:
2371 case PHY_WRITE_ERI_WORD:
bca03d5f 2372 default:
2373 BUG();
2374 }
2375 }
2376}
2377
f1e02ed1 2378static void rtl_release_firmware(struct rtl8169_private *tp)
2379{
b6ffd97f
FR		 2380 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2381 release_firmware(tp->rtl_fw->fw);
2382 kfree(tp->rtl_fw);
2383 }
2384 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2385}
2386
953a12cc 2387static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2388{
b6ffd97f 2389 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2390
2391 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
e0c07557 2392 if (!IS_ERR_OR_NULL(rtl_fw)) {
b6ffd97f 2393 rtl_phy_write_fw(tp, rtl_fw);
e0c07557 2394 tp->features |= RTL_FEATURE_FW_LOADED;
2395 }
953a12cc
FR		 2396}
2397
2398static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2399{
2400 if (rtl_readphy(tp, reg) != val)
2401 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2402 else
2403 rtl_apply_firmware(tp);
f1e02ed1 2404}
2405
e0c07557 2406static void r810x_aldps_disable(struct rtl8169_private *tp)
2407{
2408 rtl_writephy(tp, 0x1f, 0x0000);
2409 rtl_writephy(tp, 0x18, 0x0310);
2410 msleep(100);
2411}
2412
2413static void r810x_aldps_enable(struct rtl8169_private *tp)
2414{
2415 if (!(tp->features & RTL_FEATURE_FW_LOADED))
2416 return;
2417
2418 rtl_writephy(tp, 0x1f, 0x0000);
2419 rtl_writephy(tp, 0x18, 0x8310);
2420}
2421
2422static void r8168_aldps_enable_1(struct rtl8169_private *tp)
2423{
2424 if (!(tp->features & RTL_FEATURE_FW_LOADED))
2425 return;
2426
2427 rtl_writephy(tp, 0x1f, 0x0000);
2428 rtl_w1w0_phy(tp, 0x15, 0x1000, 0x0000);
2429}
2430
4da19633 2431static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2432{
350f7596 2433 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2434 { 0x1f, 0x0001 },
2435 { 0x06, 0x006e },
2436 { 0x08, 0x0708 },
2437 { 0x15, 0x4000 },
2438 { 0x18, 0x65c7 },
1da177e4 2439
0b9b571d 2440 { 0x1f, 0x0001 },
2441 { 0x03, 0x00a1 },
2442 { 0x02, 0x0008 },
2443 { 0x01, 0x0120 },
2444 { 0x00, 0x1000 },
2445 { 0x04, 0x0800 },
2446 { 0x04, 0x0000 },
1da177e4 2447
0b9b571d 2448 { 0x03, 0xff41 },
2449 { 0x02, 0xdf60 },
2450 { 0x01, 0x0140 },
2451 { 0x00, 0x0077 },
2452 { 0x04, 0x7800 },
2453 { 0x04, 0x7000 },
2454
2455 { 0x03, 0x802f },
2456 { 0x02, 0x4f02 },
2457 { 0x01, 0x0409 },
2458 { 0x00, 0xf0f9 },
2459 { 0x04, 0x9800 },
2460 { 0x04, 0x9000 },
2461
2462 { 0x03, 0xdf01 },
2463 { 0x02, 0xdf20 },
2464 { 0x01, 0xff95 },
2465 { 0x00, 0xba00 },
2466 { 0x04, 0xa800 },
2467 { 0x04, 0xa000 },
2468
2469 { 0x03, 0xff41 },
2470 { 0x02, 0xdf20 },
2471 { 0x01, 0x0140 },
2472 { 0x00, 0x00bb },
2473 { 0x04, 0xb800 },
2474 { 0x04, 0xb000 },
2475
2476 { 0x03, 0xdf41 },
2477 { 0x02, 0xdc60 },
2478 { 0x01, 0x6340 },
2479 { 0x00, 0x007d },
2480 { 0x04, 0xd800 },
2481 { 0x04, 0xd000 },
2482
2483 { 0x03, 0xdf01 },
2484 { 0x02, 0xdf20 },
2485 { 0x01, 0x100a },
2486 { 0x00, 0xa0ff },
2487 { 0x04, 0xf800 },
2488 { 0x04, 0xf000 },
2489
2490 { 0x1f, 0x0000 },
2491 { 0x0b, 0x0000 },
2492 { 0x00, 0x9200 }
2493 };
1da177e4 2494
4da19633 2495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2496}
2497
4da19633 2498static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2499{
350f7596 2500 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2501 { 0x1f, 0x0002 },
2502 { 0x01, 0x90d0 },
2503 { 0x1f, 0x0000 }
2504 };
2505
4da19633 2506 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2507}
2508
4da19633 2509static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2510{
2511 struct pci_dev *pdev = tp->pci_dev;
2e955856 2512
ccbae55e
SS		 2513 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2514 (pdev->subsystem_device != 0xe000))
2e955856 2515 return;
2516
4da19633 2517 rtl_writephy(tp, 0x1f, 0x0001);
2518 rtl_writephy(tp, 0x10, 0xf01b);
2519 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2520}
2521
4da19633 2522static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2523{
350f7596 2524 static const struct phy_reg phy_reg_init[] = {
2e955856 2525 { 0x1f, 0x0001 },
2526 { 0x04, 0x0000 },
2527 { 0x03, 0x00a1 },
2528 { 0x02, 0x0008 },
2529 { 0x01, 0x0120 },
2530 { 0x00, 0x1000 },
2531 { 0x04, 0x0800 },
2532 { 0x04, 0x9000 },
2533 { 0x03, 0x802f },
2534 { 0x02, 0x4f02 },
2535 { 0x01, 0x0409 },
2536 { 0x00, 0xf099 },
2537 { 0x04, 0x9800 },
2538 { 0x04, 0xa000 },
2539 { 0x03, 0xdf01 },
2540 { 0x02, 0xdf20 },
2541 { 0x01, 0xff95 },
2542 { 0x00, 0xba00 },
2543 { 0x04, 0xa800 },
2544 { 0x04, 0xf000 },
2545 { 0x03, 0xdf01 },
2546 { 0x02, 0xdf20 },
2547 { 0x01, 0x101a },
2548 { 0x00, 0xa0ff },
2549 { 0x04, 0xf800 },
2550 { 0x04, 0x0000 },
2551 { 0x1f, 0x0000 },
2552
2553 { 0x1f, 0x0001 },
2554 { 0x10, 0xf41b },
2555 { 0x14, 0xfb54 },
2556 { 0x18, 0xf5c7 },
2557 { 0x1f, 0x0000 },
2558
2559 { 0x1f, 0x0001 },
2560 { 0x17, 0x0cc0 },
2561 { 0x1f, 0x0000 }
2562 };
2563
4da19633 2564 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2565
4da19633 2566 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2567}
2568
4da19633 2569static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2570{
350f7596 2571 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2572 { 0x1f, 0x0001 },
2573 { 0x04, 0x0000 },
2574 { 0x03, 0x00a1 },
2575 { 0x02, 0x0008 },
2576 { 0x01, 0x0120 },
2577 { 0x00, 0x1000 },
2578 { 0x04, 0x0800 },
2579 { 0x04, 0x9000 },
2580 { 0x03, 0x802f },
2581 { 0x02, 0x4f02 },
2582 { 0x01, 0x0409 },
2583 { 0x00, 0xf099 },
2584 { 0x04, 0x9800 },
2585 { 0x04, 0xa000 },
2586 { 0x03, 0xdf01 },
2587 { 0x02, 0xdf20 },
2588 { 0x01, 0xff95 },
2589 { 0x00, 0xba00 },
2590 { 0x04, 0xa800 },
2591 { 0x04, 0xf000 },
2592 { 0x03, 0xdf01 },
2593 { 0x02, 0xdf20 },
2594 { 0x01, 0x101a },
2595 { 0x00, 0xa0ff },
2596 { 0x04, 0xf800 },
2597 { 0x04, 0x0000 },
2598 { 0x1f, 0x0000 },
2599
2600 { 0x1f, 0x0001 },
2601 { 0x0b, 0x8480 },
2602 { 0x1f, 0x0000 },
2603
2604 { 0x1f, 0x0001 },
2605 { 0x18, 0x67c7 },
2606 { 0x04, 0x2000 },
2607 { 0x03, 0x002f },
2608 { 0x02, 0x4360 },
2609 { 0x01, 0x0109 },
2610 { 0x00, 0x3022 },
2611 { 0x04, 0x2800 },
2612 { 0x1f, 0x0000 },
2613
2614 { 0x1f, 0x0001 },
2615 { 0x17, 0x0cc0 },
2616 { 0x1f, 0x0000 }
2617 };
2618
4da19633 2619 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2620}
2621
4da19633 2622static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2623{
350f7596 2624 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2625 { 0x10, 0xf41b },
2626 { 0x1f, 0x0000 }
2627 };
2628
4da19633 2629 rtl_writephy(tp, 0x1f, 0x0001);
2630 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2631
4da19633 2632 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2633}
2634
4da19633 2635static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2636{
350f7596 2637 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2638 { 0x1f, 0x0001 },
2639 { 0x10, 0xf41b },
2640 { 0x1f, 0x0000 }
2641 };
2642
4da19633 2643 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2644}
2645
4da19633 2646static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2647{
350f7596 2648 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2649 { 0x1f, 0x0000 },
2650 { 0x1d, 0x0f00 },
2651 { 0x1f, 0x0002 },
2652 { 0x0c, 0x1ec8 },
2653 { 0x1f, 0x0000 }
2654 };
2655
4da19633 2656 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2657}
2658
4da19633 2659static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2660{
350f7596 2661 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2662 { 0x1f, 0x0001 },
2663 { 0x1d, 0x3d98 },
2664 { 0x1f, 0x0000 }
2665 };
2666
4da19633 2667 rtl_writephy(tp, 0x1f, 0x0000);
2668 rtl_patchphy(tp, 0x14, 1 << 5);
2669 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2670
4da19633 2671 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2672}
2673
4da19633 2674static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2675{
350f7596 2676 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2677 { 0x1f, 0x0001 },
2678 { 0x12, 0x2300 },
867763c1
FR		 2679 { 0x1f, 0x0002 },
2680 { 0x00, 0x88d4 },
2681 { 0x01, 0x82b1 },
2682 { 0x03, 0x7002 },
2683 { 0x08, 0x9e30 },
2684 { 0x09, 0x01f0 },
2685 { 0x0a, 0x5500 },
2686 { 0x0c, 0x00c8 },
2687 { 0x1f, 0x0003 },
2688 { 0x12, 0xc096 },
2689 { 0x16, 0x000a },
f50d4275
FR		 2690 { 0x1f, 0x0000 },
2691 { 0x1f, 0x0000 },
2692 { 0x09, 0x2000 },
2693 { 0x09, 0x0000 }
867763c1
FR		 2694 };
2695
4da19633 2696 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2697
4da19633 2698 rtl_patchphy(tp, 0x14, 1 << 5);
2699 rtl_patchphy(tp, 0x0d, 1 << 5);
2700 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2701}
2702
4da19633 2703static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2704{
350f7596 2705 static const struct phy_reg phy_reg_init[] = {
f50d4275 2706 { 0x1f, 0x0001 },
7da97ec9 2707 { 0x12, 0x2300 },
f50d4275
FR		 2708 { 0x03, 0x802f },
2709 { 0x02, 0x4f02 },
2710 { 0x01, 0x0409 },
2711 { 0x00, 0xf099 },
2712 { 0x04, 0x9800 },
2713 { 0x04, 0x9000 },
2714 { 0x1d, 0x3d98 },
7da97ec9
FR		 2715 { 0x1f, 0x0002 },
2716 { 0x0c, 0x7eb8 },
f50d4275
FR		 2717 { 0x06, 0x0761 },
2718 { 0x1f, 0x0003 },
2719 { 0x16, 0x0f0a },
7da97ec9
FR		 2720 { 0x1f, 0x0000 }
2721 };
2722
4da19633 2723 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2724
4da19633 2725 rtl_patchphy(tp, 0x16, 1 << 0);
2726 rtl_patchphy(tp, 0x14, 1 << 5);
2727 rtl_patchphy(tp, 0x0d, 1 << 5);
2728 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2729}
2730
4da19633 2731static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2732{
350f7596 2733 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2734 { 0x1f, 0x0001 },
2735 { 0x12, 0x2300 },
2736 { 0x1d, 0x3d98 },
2737 { 0x1f, 0x0002 },
2738 { 0x0c, 0x7eb8 },
2739 { 0x06, 0x5461 },
2740 { 0x1f, 0x0003 },
2741 { 0x16, 0x0f0a },
2742 { 0x1f, 0x0000 }
2743 };
2744
4da19633 2745 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2746
4da19633 2747 rtl_patchphy(tp, 0x16, 1 << 0);
2748 rtl_patchphy(tp, 0x14, 1 << 5);
2749 rtl_patchphy(tp, 0x0d, 1 << 5);
2750 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2751}
2752
4da19633 2753static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2754{
4da19633 2755 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2756}
2757
bca03d5f 2758static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2759{
350f7596 2760 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2761 /* Channel Estimation */
5b538df9 2762 { 0x1f, 0x0001 },
daf9df6d 2763 { 0x06, 0x4064 },
2764 { 0x07, 0x2863 },
2765 { 0x08, 0x059c },
2766 { 0x09, 0x26b4 },
2767 { 0x0a, 0x6a19 },
2768 { 0x0b, 0xdcc8 },
2769 { 0x10, 0xf06d },
2770 { 0x14, 0x7f68 },
2771 { 0x18, 0x7fd9 },
2772 { 0x1c, 0xf0ff },
2773 { 0x1d, 0x3d9c },
5b538df9 2774 { 0x1f, 0x0003 },
daf9df6d 2775 { 0x12, 0xf49f },
2776 { 0x13, 0x070b },
2777 { 0x1a, 0x05ad },
bca03d5f 2778 { 0x14, 0x94c0 },
2779
2780 /*
2781 * Tx Error Issue
cecb5fd7 2782 * Enhance line driver power
bca03d5f 2783 */
5b538df9 2784 { 0x1f, 0x0002 },
daf9df6d 2785 { 0x06, 0x5561 },
2786 { 0x1f, 0x0005 },
2787 { 0x05, 0x8332 },
bca03d5f 2788 { 0x06, 0x5561 },
2789
2790 /*
2791 * Can not link to 1Gbps with bad cable
2792 * Decrease SNR threshold form 21.07dB to 19.04dB
2793 */
2794 { 0x1f, 0x0001 },
2795 { 0x17, 0x0cc0 },
daf9df6d 2796
5b538df9 2797 { 0x1f, 0x0000 },
bca03d5f 2798 { 0x0d, 0xf880 }
daf9df6d 2799 };
2800
4da19633 2801 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2802
bca03d5f 2803 /*
2804 * Rx Error Issue
2805 * Fine Tune Switching regulator parameter
2806 */
4da19633 2807 rtl_writephy(tp, 0x1f, 0x0002);
2808 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2809 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2810
fdf6fc06 2811 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2812 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2813 { 0x1f, 0x0002 },
2814 { 0x05, 0x669a },
2815 { 0x1f, 0x0005 },
2816 { 0x05, 0x8330 },
2817 { 0x06, 0x669a },
2818 { 0x1f, 0x0002 }
2819 };
2820 int val;
2821
4da19633 2822 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2823
4da19633 2824 val = rtl_readphy(tp, 0x0d);
daf9df6d 2825
2826 if ((val & 0x00ff) != 0x006c) {
350f7596 2827 static const u32 set[] = {
daf9df6d 2828 0x0065, 0x0066, 0x0067, 0x0068,
2829 0x0069, 0x006a, 0x006b, 0x006c
2830 };
2831 int i;
2832
4da19633 2833 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2834
2835 val &= 0xff00;
2836 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2837 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2838 }
2839 } else {
350f7596 2840 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2841 { 0x1f, 0x0002 },
2842 { 0x05, 0x6662 },
2843 { 0x1f, 0x0005 },
2844 { 0x05, 0x8330 },
2845 { 0x06, 0x6662 }
2846 };
2847
4da19633 2848 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2849 }
2850
bca03d5f 2851 /* RSET couple improve */
4da19633 2852 rtl_writephy(tp, 0x1f, 0x0002);
2853 rtl_patchphy(tp, 0x0d, 0x0300);
2854 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2855
bca03d5f 2856 /* Fine tune PLL performance */
4da19633 2857 rtl_writephy(tp, 0x1f, 0x0002);
2858 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2859 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2860
4da19633 2861 rtl_writephy(tp, 0x1f, 0x0005);
2862 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2863
2864 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2865
4da19633 2866 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2867}
2868
bca03d5f 2869static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2870{
350f7596 2871 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2872 /* Channel Estimation */
daf9df6d 2873 { 0x1f, 0x0001 },
2874 { 0x06, 0x4064 },
2875 { 0x07, 0x2863 },
2876 { 0x08, 0x059c },
2877 { 0x09, 0x26b4 },
2878 { 0x0a, 0x6a19 },
2879 { 0x0b, 0xdcc8 },
2880 { 0x10, 0xf06d },
2881 { 0x14, 0x7f68 },
2882 { 0x18, 0x7fd9 },
2883 { 0x1c, 0xf0ff },
2884 { 0x1d, 0x3d9c },
2885 { 0x1f, 0x0003 },
2886 { 0x12, 0xf49f },
2887 { 0x13, 0x070b },
2888 { 0x1a, 0x05ad },
2889 { 0x14, 0x94c0 },
2890
bca03d5f 2891 /*
2892 * Tx Error Issue
cecb5fd7 2893 * Enhance line driver power
bca03d5f 2894 */
daf9df6d 2895 { 0x1f, 0x0002 },
2896 { 0x06, 0x5561 },
2897 { 0x1f, 0x0005 },
2898 { 0x05, 0x8332 },
bca03d5f 2899 { 0x06, 0x5561 },
2900
2901 /*
2902 * Can not link to 1Gbps with bad cable
2903 * Decrease SNR threshold form 21.07dB to 19.04dB
2904 */
2905 { 0x1f, 0x0001 },
2906 { 0x17, 0x0cc0 },
daf9df6d 2907
2908 { 0x1f, 0x0000 },
bca03d5f 2909 { 0x0d, 0xf880 }
5b538df9
FR		 2910 };
2911
4da19633 2912 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2913
fdf6fc06 2914 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2915 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2916 { 0x1f, 0x0002 },
2917 { 0x05, 0x669a },
5b538df9 2918 { 0x1f, 0x0005 },
daf9df6d 2919 { 0x05, 0x8330 },
2920 { 0x06, 0x669a },
2921
2922 { 0x1f, 0x0002 }
2923 };
2924 int val;
2925
4da19633 2926 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2927
4da19633 2928 val = rtl_readphy(tp, 0x0d);
daf9df6d 2929 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2930 static const u32 set[] = {
daf9df6d 2931 0x0065, 0x0066, 0x0067, 0x0068,
2932 0x0069, 0x006a, 0x006b, 0x006c
2933 };
2934 int i;
2935
4da19633 2936 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2937
2938 val &= 0xff00;
2939 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2940 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2941 }
2942 } else {
350f7596 2943 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2944 { 0x1f, 0x0002 },
2945 { 0x05, 0x2642 },
5b538df9 2946 { 0x1f, 0x0005 },
daf9df6d 2947 { 0x05, 0x8330 },
2948 { 0x06, 0x2642 }
5b538df9
FR		 2949 };
2950
4da19633 2951 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2952 }
2953
bca03d5f 2954 /* Fine tune PLL performance */
4da19633 2955 rtl_writephy(tp, 0x1f, 0x0002);
2956 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2957 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2958
bca03d5f 2959 /* Switching regulator Slew rate */
4da19633 2960 rtl_writephy(tp, 0x1f, 0x0002);
2961 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2962
4da19633 2963 rtl_writephy(tp, 0x1f, 0x0005);
2964 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2965
2966 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2967
4da19633 2968 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2969}
2970
4da19633 2971static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2972{
350f7596 2973 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2974 { 0x1f, 0x0002 },
2975 { 0x10, 0x0008 },
2976 { 0x0d, 0x006c },
2977
2978 { 0x1f, 0x0000 },
2979 { 0x0d, 0xf880 },
2980
2981 { 0x1f, 0x0001 },
2982 { 0x17, 0x0cc0 },
2983
2984 { 0x1f, 0x0001 },
2985 { 0x0b, 0xa4d8 },
2986 { 0x09, 0x281c },
2987 { 0x07, 0x2883 },
2988 { 0x0a, 0x6b35 },
2989 { 0x1d, 0x3da4 },
2990 { 0x1c, 0xeffd },
2991 { 0x14, 0x7f52 },
2992 { 0x18, 0x7fc6 },
2993 { 0x08, 0x0601 },
2994 { 0x06, 0x4063 },
2995 { 0x10, 0xf074 },
2996 { 0x1f, 0x0003 },
2997 { 0x13, 0x0789 },
2998 { 0x12, 0xf4bd },
2999 { 0x1a, 0x04fd },
3000 { 0x14, 0x84b0 },
3001 { 0x1f, 0x0000 },
3002 { 0x00, 0x9200 },
3003
3004 { 0x1f, 0x0005 },
3005 { 0x01, 0x0340 },
3006 { 0x1f, 0x0001 },
3007 { 0x04, 0x4000 },
3008 { 0x03, 0x1d21 },
3009 { 0x02, 0x0c32 },
3010 { 0x01, 0x0200 },
3011 { 0x00, 0x5554 },
3012 { 0x04, 0x4800 },
3013 { 0x04, 0x4000 },
3014 { 0x04, 0xf000 },
3015 { 0x03, 0xdf01 },
3016 { 0x02, 0xdf20 },
3017 { 0x01, 0x101a },
3018 { 0x00, 0xa0ff },
3019 { 0x04, 0xf800 },
3020 { 0x04, 0xf000 },
3021 { 0x1f, 0x0000 },
3022
3023 { 0x1f, 0x0007 },
3024 { 0x1e, 0x0023 },
3025 { 0x16, 0x0000 },
3026 { 0x1f, 0x0000 }
3027 };
3028
4da19633 3029 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3030}
3031
e6de30d6 3032static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3033{
3034 static const struct phy_reg phy_reg_init[] = {
3035 { 0x1f, 0x0001 },
3036 { 0x17, 0x0cc0 },
3037
3038 { 0x1f, 0x0007 },
3039 { 0x1e, 0x002d },
3040 { 0x18, 0x0040 },
3041 { 0x1f, 0x0000 }
3042 };
3043
3044 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3045 rtl_patchphy(tp, 0x0d, 1 << 5);
3046}
3047
70090424 3048static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3049{
3050 static const struct phy_reg phy_reg_init[] = {
3051 /* Enable Delay cap */
3052 { 0x1f, 0x0005 },
3053 { 0x05, 0x8b80 },
3054 { 0x06, 0xc896 },
3055 { 0x1f, 0x0000 },
3056
3057 /* Channel estimation fine tune */
3058 { 0x1f, 0x0001 },
3059 { 0x0b, 0x6c20 },
3060 { 0x07, 0x2872 },
3061 { 0x1c, 0xefff },
3062 { 0x1f, 0x0003 },
3063 { 0x14, 0x6420 },
3064 { 0x1f, 0x0000 },
3065
3066 /* Update PFM & 10M TX idle timer */
3067 { 0x1f, 0x0007 },
3068 { 0x1e, 0x002f },
3069 { 0x15, 0x1919 },
3070 { 0x1f, 0x0000 },
3071
3072 { 0x1f, 0x0007 },
3073 { 0x1e, 0x00ac },
3074 { 0x18, 0x0006 },
3075 { 0x1f, 0x0000 }
3076 };
3077
15ecd039
FR		 3078 rtl_apply_firmware(tp);
3079
01dc7fec 3080 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3081
3082 /* DCO enable for 10M IDLE Power */
3083 rtl_writephy(tp, 0x1f, 0x0007);
3084 rtl_writephy(tp, 0x1e, 0x0023);
3085 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3086 rtl_writephy(tp, 0x1f, 0x0000);
3087
3088 /* For impedance matching */
3089 rtl_writephy(tp, 0x1f, 0x0002);
3090 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3091 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3092
3093 /* PHY auto speed down */
3094 rtl_writephy(tp, 0x1f, 0x0007);
3095 rtl_writephy(tp, 0x1e, 0x002d);
3096 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3097 rtl_writephy(tp, 0x1f, 0x0000);
3098 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3099
3100 rtl_writephy(tp, 0x1f, 0x0005);
3101 rtl_writephy(tp, 0x05, 0x8b86);
3102 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3103 rtl_writephy(tp, 0x1f, 0x0000);
3104
3105 rtl_writephy(tp, 0x1f, 0x0005);
3106 rtl_writephy(tp, 0x05, 0x8b85);
3107 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3108 rtl_writephy(tp, 0x1f, 0x0007);
3109 rtl_writephy(tp, 0x1e, 0x0020);
3110 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3111 rtl_writephy(tp, 0x1f, 0x0006);
3112 rtl_writephy(tp, 0x00, 0x5a00);
3113 rtl_writephy(tp, 0x1f, 0x0000);
3114 rtl_writephy(tp, 0x0d, 0x0007);
3115 rtl_writephy(tp, 0x0e, 0x003c);
3116 rtl_writephy(tp, 0x0d, 0x4007);
3117 rtl_writephy(tp, 0x0e, 0x0000);
3118 rtl_writephy(tp, 0x0d, 0x0000);
3119}
3120
9ecb9aab 3121static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3122{
3123 const u16 w[] = {
3124 addr[0] | (addr[1] << 8),
3125 addr[2] | (addr[3] << 8),
3126 addr[4] | (addr[5] << 8)
3127 };
3128 const struct exgmac_reg e[] = {
3129 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3130 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3131 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3132 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3133 };
3134
3135 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3136}
3137
70090424
HW		 3138static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3139{
3140 static const struct phy_reg phy_reg_init[] = {
3141 /* Enable Delay cap */
3142 { 0x1f, 0x0004 },
3143 { 0x1f, 0x0007 },
3144 { 0x1e, 0x00ac },
3145 { 0x18, 0x0006 },
3146 { 0x1f, 0x0002 },
3147 { 0x1f, 0x0000 },
3148 { 0x1f, 0x0000 },
3149
3150 /* Channel estimation fine tune */
3151 { 0x1f, 0x0003 },
3152 { 0x09, 0xa20f },
3153 { 0x1f, 0x0000 },
3154 { 0x1f, 0x0000 },
3155
3156 /* Green Setting */
3157 { 0x1f, 0x0005 },
3158 { 0x05, 0x8b5b },
3159 { 0x06, 0x9222 },
3160 { 0x05, 0x8b6d },
3161 { 0x06, 0x8000 },
3162 { 0x05, 0x8b76 },
3163 { 0x06, 0x8000 },
3164 { 0x1f, 0x0000 }
3165 };
3166
3167 rtl_apply_firmware(tp);
3168
3169 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3170
3171 /* For 4-corner performance improve */
3172 rtl_writephy(tp, 0x1f, 0x0005);
3173 rtl_writephy(tp, 0x05, 0x8b80);
3174 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3175 rtl_writephy(tp, 0x1f, 0x0000);
3176
3177 /* PHY auto speed down */
3178 rtl_writephy(tp, 0x1f, 0x0004);
3179 rtl_writephy(tp, 0x1f, 0x0007);
3180 rtl_writephy(tp, 0x1e, 0x002d);
3181 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3182 rtl_writephy(tp, 0x1f, 0x0002);
3183 rtl_writephy(tp, 0x1f, 0x0000);
3184 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3185
3186 /* improve 10M EEE waveform */
3187 rtl_writephy(tp, 0x1f, 0x0005);
3188 rtl_writephy(tp, 0x05, 0x8b86);
3189 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3190 rtl_writephy(tp, 0x1f, 0x0000);
3191
3192 /* Improve 2-pair detection performance */
3193 rtl_writephy(tp, 0x1f, 0x0005);
3194 rtl_writephy(tp, 0x05, 0x8b85);
3195 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3196 rtl_writephy(tp, 0x1f, 0x0000);
3197
3198 /* EEE setting */
fdf6fc06 3199 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3200 rtl_writephy(tp, 0x1f, 0x0005);
3201 rtl_writephy(tp, 0x05, 0x8b85);
3202 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3203 rtl_writephy(tp, 0x1f, 0x0004);
3204 rtl_writephy(tp, 0x1f, 0x0007);
3205 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3206 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3207 rtl_writephy(tp, 0x1f, 0x0002);
3208 rtl_writephy(tp, 0x1f, 0x0000);
3209 rtl_writephy(tp, 0x0d, 0x0007);
3210 rtl_writephy(tp, 0x0e, 0x003c);
3211 rtl_writephy(tp, 0x0d, 0x4007);
3212 rtl_writephy(tp, 0x0e, 0x0000);
3213 rtl_writephy(tp, 0x0d, 0x0000);
3214
3215 /* Green feature */
3216 rtl_writephy(tp, 0x1f, 0x0003);
3217 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3218 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3219 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3220
3221 r8168_aldps_enable_1(tp);
9ecb9aab 3222
3223 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3224 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3225}
3226
5f886e08
HW		 3227static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3228{
3229 /* For 4-corner performance improve */
3230 rtl_writephy(tp, 0x1f, 0x0005);
3231 rtl_writephy(tp, 0x05, 0x8b80);
3232 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3233 rtl_writephy(tp, 0x1f, 0x0000);
3234
3235 /* PHY auto speed down */
3236 rtl_writephy(tp, 0x1f, 0x0007);
3237 rtl_writephy(tp, 0x1e, 0x002d);
3238 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3239 rtl_writephy(tp, 0x1f, 0x0000);
3240 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3241
3242 /* Improve 10M EEE waveform */
3243 rtl_writephy(tp, 0x1f, 0x0005);
3244 rtl_writephy(tp, 0x05, 0x8b86);
3245 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3246 rtl_writephy(tp, 0x1f, 0x0000);
3247}
3248
c2218925
HW		 3249static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3250{
3251 static const struct phy_reg phy_reg_init[] = {
3252 /* Channel estimation fine tune */
3253 { 0x1f, 0x0003 },
3254 { 0x09, 0xa20f },
3255 { 0x1f, 0x0000 },
3256
3257 /* Modify green table for giga & fnet */
3258 { 0x1f, 0x0005 },
3259 { 0x05, 0x8b55 },
3260 { 0x06, 0x0000 },
3261 { 0x05, 0x8b5e },
3262 { 0x06, 0x0000 },
3263 { 0x05, 0x8b67 },
3264 { 0x06, 0x0000 },
3265 { 0x05, 0x8b70 },
3266 { 0x06, 0x0000 },
3267 { 0x1f, 0x0000 },
3268 { 0x1f, 0x0007 },
3269 { 0x1e, 0x0078 },
3270 { 0x17, 0x0000 },
3271 { 0x19, 0x00fb },
3272 { 0x1f, 0x0000 },
3273
3274 /* Modify green table for 10M */
3275 { 0x1f, 0x0005 },
3276 { 0x05, 0x8b79 },
3277 { 0x06, 0xaa00 },
3278 { 0x1f, 0x0000 },
3279
3280 /* Disable hiimpedance detection (RTCT) */
3281 { 0x1f, 0x0003 },
3282 { 0x01, 0x328a },
3283 { 0x1f, 0x0000 }
3284 };
3285
3286 rtl_apply_firmware(tp);
3287
3288 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3289
5f886e08 3290 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3291
3292 /* Improve 2-pair detection performance */
3293 rtl_writephy(tp, 0x1f, 0x0005);
3294 rtl_writephy(tp, 0x05, 0x8b85);
3295 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3296 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3297
3298 r8168_aldps_enable_1(tp);
c2218925
HW		 3299}
3300
3301static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3302{
3303 rtl_apply_firmware(tp);
3304
5f886e08 3305 rtl8168f_hw_phy_config(tp);
e0c07557 3306
3307 r8168_aldps_enable_1(tp);
c2218925
HW		 3308}
3309
b3d7b2f2
HW		 3310static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3311{
b3d7b2f2
HW		 3312 static const struct phy_reg phy_reg_init[] = {
3313 /* Channel estimation fine tune */
3314 { 0x1f, 0x0003 },
3315 { 0x09, 0xa20f },
3316 { 0x1f, 0x0000 },
3317
3318 /* Modify green table for giga & fnet */
3319 { 0x1f, 0x0005 },
3320 { 0x05, 0x8b55 },
3321 { 0x06, 0x0000 },
3322 { 0x05, 0x8b5e },
3323 { 0x06, 0x0000 },
3324 { 0x05, 0x8b67 },
3325 { 0x06, 0x0000 },
3326 { 0x05, 0x8b70 },
3327 { 0x06, 0x0000 },
3328 { 0x1f, 0x0000 },
3329 { 0x1f, 0x0007 },
3330 { 0x1e, 0x0078 },
3331 { 0x17, 0x0000 },
3332 { 0x19, 0x00aa },
3333 { 0x1f, 0x0000 },
3334
3335 /* Modify green table for 10M */
3336 { 0x1f, 0x0005 },
3337 { 0x05, 0x8b79 },
3338 { 0x06, 0xaa00 },
3339 { 0x1f, 0x0000 },
3340
3341 /* Disable hiimpedance detection (RTCT) */
3342 { 0x1f, 0x0003 },
3343 { 0x01, 0x328a },
3344 { 0x1f, 0x0000 }
3345 };
3346
3347
3348 rtl_apply_firmware(tp);
3349
3350 rtl8168f_hw_phy_config(tp);
3351
3352 /* Improve 2-pair detection performance */
3353 rtl_writephy(tp, 0x1f, 0x0005);
3354 rtl_writephy(tp, 0x05, 0x8b85);
3355 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3356 rtl_writephy(tp, 0x1f, 0x0000);
3357
3358 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3359
3360 /* Modify green table for giga */
3361 rtl_writephy(tp, 0x1f, 0x0005);
3362 rtl_writephy(tp, 0x05, 0x8b54);
3363 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3364 rtl_writephy(tp, 0x05, 0x8b5d);
3365 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3366 rtl_writephy(tp, 0x05, 0x8a7c);
3367 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3368 rtl_writephy(tp, 0x05, 0x8a7f);
3369 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3370 rtl_writephy(tp, 0x05, 0x8a82);
3371 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3372 rtl_writephy(tp, 0x05, 0x8a85);
3373 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3374 rtl_writephy(tp, 0x05, 0x8a88);
3375 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3376 rtl_writephy(tp, 0x1f, 0x0000);
3377
3378 /* uc same-seed solution */
3379 rtl_writephy(tp, 0x1f, 0x0005);
3380 rtl_writephy(tp, 0x05, 0x8b85);
3381 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3382 rtl_writephy(tp, 0x1f, 0x0000);
3383
3384 /* eee setting */
fdf6fc06 3385 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3386 rtl_writephy(tp, 0x1f, 0x0005);
3387 rtl_writephy(tp, 0x05, 0x8b85);
3388 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3389 rtl_writephy(tp, 0x1f, 0x0004);
3390 rtl_writephy(tp, 0x1f, 0x0007);
3391 rtl_writephy(tp, 0x1e, 0x0020);
3392 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3393 rtl_writephy(tp, 0x1f, 0x0000);
3394 rtl_writephy(tp, 0x0d, 0x0007);
3395 rtl_writephy(tp, 0x0e, 0x003c);
3396 rtl_writephy(tp, 0x0d, 0x4007);
3397 rtl_writephy(tp, 0x0e, 0x0000);
3398 rtl_writephy(tp, 0x0d, 0x0000);
3399
3400 /* Green feature */
3401 rtl_writephy(tp, 0x1f, 0x0003);
3402 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3403 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3404 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3405
3406 r8168_aldps_enable_1(tp);
b3d7b2f2
HW		 3407}
3408
c558386b
HW		 3409static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3410{
3411 static const u16 mac_ocp_patch[] = {
3412 0xe008, 0xe01b, 0xe01d, 0xe01f,
3413 0xe021, 0xe023, 0xe025, 0xe027,
3414 0x49d2, 0xf10d, 0x766c, 0x49e2,
3415 0xf00a, 0x1ec0, 0x8ee1, 0xc60a,
3416
3417 0x77c0, 0x4870, 0x9fc0, 0x1ea0,
3418 0xc707, 0x8ee1, 0x9d6c, 0xc603,
3419 0xbe00, 0xb416, 0x0076, 0xe86c,
3420 0xc602, 0xbe00, 0x0000, 0xc602,
3421
3422 0xbe00, 0x0000, 0xc602, 0xbe00,
3423 0x0000, 0xc602, 0xbe00, 0x0000,
3424 0xc602, 0xbe00, 0x0000, 0xc602,
3425 0xbe00, 0x0000, 0xc602, 0xbe00,
3426
3427 0x0000, 0x0000, 0x0000, 0x0000
3428 };
3429 u32 i;
3430
3431 /* Patch code for GPHY reset */
3432 for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++)
3433 r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]);
3434 r8168_mac_ocp_write(tp, 0xfc26, 0x8000);
3435 r8168_mac_ocp_write(tp, 0xfc28, 0x0075);
3436
3437 rtl_apply_firmware(tp);
3438
3439 if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
3440 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
3441 else
3442 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
3443
3444 if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
3445 rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
3446 else
3447 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
3448
3449 rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
3450 rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
3451
3452 r8168_phy_ocp_write(tp, 0xa436, 0x8012);
3453 rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
3454
3455 rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
3456}
3457
4da19633 3458static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3459{
350f7596 3460 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3461 { 0x1f, 0x0003 },
3462 { 0x08, 0x441d },
3463 { 0x01, 0x9100 },
3464 { 0x1f, 0x0000 }
3465 };
3466
4da19633 3467 rtl_writephy(tp, 0x1f, 0x0000);
3468 rtl_patchphy(tp, 0x11, 1 << 12);
3469 rtl_patchphy(tp, 0x19, 1 << 13);
3470 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3471
4da19633 3472 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3473}
3474
5a5e4443
HW		 3475static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3476{
3477 static const struct phy_reg phy_reg_init[] = {
3478 { 0x1f, 0x0005 },
3479 { 0x1a, 0x0000 },
3480 { 0x1f, 0x0000 },
3481
3482 { 0x1f, 0x0004 },
3483 { 0x1c, 0x0000 },
3484 { 0x1f, 0x0000 },
3485
3486 { 0x1f, 0x0001 },
3487 { 0x15, 0x7701 },
3488 { 0x1f, 0x0000 }
3489 };
3490
3491 /* Disable ALDPS before ram code */
e0c07557 3492 r810x_aldps_disable(tp);
5a5e4443 3493
953a12cc 3494 rtl_apply_firmware(tp);
5a5e4443
HW		 3495
3496 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
e0c07557 3497
3498 r810x_aldps_enable(tp);
5a5e4443
HW		 3499}
3500
7e18dca1
HW		 3501static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3502{
7e18dca1 3503 /* Disable ALDPS before setting firmware */
e0c07557 3504 r810x_aldps_disable(tp);
7e18dca1
HW		 3505
3506 rtl_apply_firmware(tp);
3507
3508 /* EEE setting */
fdf6fc06 3509 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3510 rtl_writephy(tp, 0x1f, 0x0004);
3511 rtl_writephy(tp, 0x10, 0x401f);
3512 rtl_writephy(tp, 0x19, 0x7030);
3513 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3514
3515 r810x_aldps_enable(tp);
7e18dca1
HW		 3516}
3517
5598bfe5
HW		 3518static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3519{
5598bfe5
HW		 3520 static const struct phy_reg phy_reg_init[] = {
3521 { 0x1f, 0x0004 },
3522 { 0x10, 0xc07f },
3523 { 0x19, 0x7030 },
3524 { 0x1f, 0x0000 }
3525 };
3526
3527 /* Disable ALDPS before ram code */
e0c07557 3528 r810x_aldps_disable(tp);
5598bfe5
HW		 3529
3530 rtl_apply_firmware(tp);
3531
fdf6fc06 3532 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3533 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3534
fdf6fc06 3535 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
e0c07557 3536
3537 r810x_aldps_enable(tp);
5598bfe5
HW		 3538}
3539
5615d9f1
FR		 3540static void rtl_hw_phy_config(struct net_device *dev)
3541{
3542 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3543
3544 rtl8169_print_mac_version(tp);
3545
3546 switch (tp->mac_version) {
3547 case RTL_GIGA_MAC_VER_01:
3548 break;
3549 case RTL_GIGA_MAC_VER_02:
3550 case RTL_GIGA_MAC_VER_03:
4da19633 3551 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3552 break;
3553 case RTL_GIGA_MAC_VER_04:
4da19633 3554 rtl8169sb_hw_phy_config(tp);
5615d9f1 3555 break;
2e955856 3556 case RTL_GIGA_MAC_VER_05:
4da19633 3557 rtl8169scd_hw_phy_config(tp);
2e955856 3558 break;
8c7006aa 3559 case RTL_GIGA_MAC_VER_06:
4da19633 3560 rtl8169sce_hw_phy_config(tp);
8c7006aa 3561 break;
2857ffb7
FR		 3562 case RTL_GIGA_MAC_VER_07:
3563 case RTL_GIGA_MAC_VER_08:
3564 case RTL_GIGA_MAC_VER_09:
4da19633 3565 rtl8102e_hw_phy_config(tp);
2857ffb7 3566 break;
236b8082 3567 case RTL_GIGA_MAC_VER_11:
4da19633 3568 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3569 break;
3570 case RTL_GIGA_MAC_VER_12:
4da19633 3571 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3572 break;
3573 case RTL_GIGA_MAC_VER_17:
4da19633 3574 rtl8168bef_hw_phy_config(tp);
236b8082 3575 break;
867763c1 3576 case RTL_GIGA_MAC_VER_18:
4da19633 3577 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3578 break;
3579 case RTL_GIGA_MAC_VER_19:
4da19633 3580 rtl8168c_1_hw_phy_config(tp);
867763c1 3581 break;
7da97ec9 3582 case RTL_GIGA_MAC_VER_20:
4da19633 3583 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3584 break;
197ff761 3585 case RTL_GIGA_MAC_VER_21:
4da19633 3586 rtl8168c_3_hw_phy_config(tp);
197ff761 3587 break;
6fb07058 3588 case RTL_GIGA_MAC_VER_22:
4da19633 3589 rtl8168c_4_hw_phy_config(tp);
6fb07058 3590 break;
ef3386f0 3591 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3592 case RTL_GIGA_MAC_VER_24:
4da19633 3593 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3594 break;
5b538df9 3595 case RTL_GIGA_MAC_VER_25:
bca03d5f 3596 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3597 break;
3598 case RTL_GIGA_MAC_VER_26:
bca03d5f 3599 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3600 break;
3601 case RTL_GIGA_MAC_VER_27:
4da19633 3602 rtl8168d_3_hw_phy_config(tp);
5b538df9 3603 break;
e6de30d6 3604 case RTL_GIGA_MAC_VER_28:
3605 rtl8168d_4_hw_phy_config(tp);
3606 break;
5a5e4443
HW		 3607 case RTL_GIGA_MAC_VER_29:
3608 case RTL_GIGA_MAC_VER_30:
3609 rtl8105e_hw_phy_config(tp);
3610 break;
cecb5fd7
FR		 3611 case RTL_GIGA_MAC_VER_31:
3612 /* None. */
3613 break;
01dc7fec 3614 case RTL_GIGA_MAC_VER_32:
01dc7fec 3615 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3616 rtl8168e_1_hw_phy_config(tp);
3617 break;
3618 case RTL_GIGA_MAC_VER_34:
3619 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3620 break;
c2218925
HW		 3621 case RTL_GIGA_MAC_VER_35:
3622 rtl8168f_1_hw_phy_config(tp);
3623 break;
3624 case RTL_GIGA_MAC_VER_36:
3625 rtl8168f_2_hw_phy_config(tp);
3626 break;
ef3386f0 3627
7e18dca1
HW		 3628 case RTL_GIGA_MAC_VER_37:
3629 rtl8402_hw_phy_config(tp);
3630 break;
3631
b3d7b2f2
HW		 3632 case RTL_GIGA_MAC_VER_38:
3633 rtl8411_hw_phy_config(tp);
3634 break;
3635
5598bfe5
HW		 3636 case RTL_GIGA_MAC_VER_39:
3637 rtl8106e_hw_phy_config(tp);
3638 break;
3639
c558386b
HW		 3640 case RTL_GIGA_MAC_VER_40:
3641 rtl8168g_1_hw_phy_config(tp);
3642 break;
3643
3644 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3645 default:
3646 break;
3647 }
3648}
3649
da78dbff 3650static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3651{
1da177e4
LT		 3652 struct timer_list *timer = &tp->timer;
3653 void __iomem *ioaddr = tp->mmio_addr;
3654 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3655
bcf0bf90 3656 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3657
4da19633 3658 if (tp->phy_reset_pending(tp)) {
5b0384f4 3659 /*
1da177e4
LT		 3660 * A busy loop could burn quite a few cycles on nowadays CPU.
3661 * Let's delay the execution of the timer for a few ticks.
3662 */
3663 timeout = HZ/10;
3664 goto out_mod_timer;
3665 }
3666
3667 if (tp->link_ok(ioaddr))
da78dbff 3668 return;
1da177e4 3669
da78dbff 3670 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3671
4da19633 3672 tp->phy_reset_enable(tp);
1da177e4
LT		 3673
3674out_mod_timer:
3675 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3676}
3677
3678static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3679{
da78dbff
FR		 3680 if (!test_and_set_bit(flag, tp->wk.flags))
3681 schedule_work(&tp->wk.work);
da78dbff
FR		 3682}
3683
3684static void rtl8169_phy_timer(unsigned long __opaque)
3685{
3686 struct net_device *dev = (struct net_device *)__opaque;
3687 struct rtl8169_private *tp = netdev_priv(dev);
3688
98ddf986 3689 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3690}
3691
1da177e4
LT		 3692static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3693 void __iomem *ioaddr)
3694{
3695 iounmap(ioaddr);
3696 pci_release_regions(pdev);
87aeec76 3697 pci_clear_mwi(pdev);
1da177e4
LT		 3698 pci_disable_device(pdev);
3699 free_netdev(dev);
3700}
3701
ffc46952
FR		 3702DECLARE_RTL_COND(rtl_phy_reset_cond)
3703{
3704 return tp->phy_reset_pending(tp);
3705}
3706
bf793295
FR		 3707static void rtl8169_phy_reset(struct net_device *dev,
3708 struct rtl8169_private *tp)
3709{
4da19633 3710 tp->phy_reset_enable(tp);
ffc46952 3711 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3712}
3713
2544bfc0
FR		 3714static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3715{
3716 void __iomem *ioaddr = tp->mmio_addr;
3717
3718 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3719 (RTL_R8(PHYstatus) & TBI_Enable);
3720}
3721
4ff96fa6
FR		 3722static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3723{
3724 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3725
5615d9f1 3726 rtl_hw_phy_config(dev);
4ff96fa6 3727
77332894
MS		 3728 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3729 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3730 RTL_W8(0x82, 0x01);
3731 }
4ff96fa6 3732
6dccd16b
FR		 3733 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3734
3735 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3736 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3737
bcf0bf90 3738 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3739 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3740 RTL_W8(0x82, 0x01);
3741 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3742 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3743 }
3744
bf793295
FR		 3745 rtl8169_phy_reset(dev, tp);
3746
54405cde 3747 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3748 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3749 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3750 (tp->mii.supports_gmii ?
3751 ADVERTISED_1000baseT_Half |
3752 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3753
2544bfc0 3754 if (rtl_tbi_enabled(tp))
bf82c189 3755 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3756}
3757
773d2021
FR		 3758static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3759{
3760 void __iomem *ioaddr = tp->mmio_addr;
773d2021 3761
da78dbff 3762 rtl_lock_work(tp);
773d2021
FR		 3763
3764 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3765
9ecb9aab 3766 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 3767 RTL_R32(MAC4);
3768
9ecb9aab 3769 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 3770 RTL_R32(MAC0);
3771
9ecb9aab 3772 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3773 rtl_rar_exgmac_set(tp, addr);
c28aa385 3774
773d2021
FR		 3775 RTL_W8(Cfg9346, Cfg9346_Lock);
3776
da78dbff 3777 rtl_unlock_work(tp);
773d2021
FR		 3778}
3779
3780static int rtl_set_mac_address(struct net_device *dev, void *p)
3781{
3782 struct rtl8169_private *tp = netdev_priv(dev);
3783 struct sockaddr *addr = p;
3784
3785 if (!is_valid_ether_addr(addr->sa_data))
3786 return -EADDRNOTAVAIL;
3787
3788 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3789
3790 rtl_rar_set(tp, dev->dev_addr);
3791
3792 return 0;
3793}
3794
5f787a1a
FR		 3795static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3796{
3797 struct rtl8169_private *tp = netdev_priv(dev);
3798 struct mii_ioctl_data *data = if_mii(ifr);
3799
8b4ab28d
FR		 3800 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3801}
5f787a1a 3802
cecb5fd7
FR		 3803static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3804 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3805{
5f787a1a
FR		 3806 switch (cmd) {
3807 case SIOCGMIIPHY:
3808 data->phy_id = 32; /* Internal PHY */
3809 return 0;
3810
3811 case SIOCGMIIREG:
4da19633 3812 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3813 return 0;
3814
3815 case SIOCSMIIREG:
4da19633 3816 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3817 return 0;
3818 }
3819 return -EOPNOTSUPP;
3820}
3821
8b4ab28d
FR		 3822static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3823{
3824 return -EOPNOTSUPP;
3825}
3826
fbac58fc
FR		 3827static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3828{
3829 if (tp->features & RTL_FEATURE_MSI) {
3830 pci_disable_msi(pdev);
3831 tp->features &= ~RTL_FEATURE_MSI;
3832 }
3833}
3834
baf63293 3835static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 3836{
3837 struct mdio_ops *ops = &tp->mdio_ops;
3838
3839 switch (tp->mac_version) {
3840 case RTL_GIGA_MAC_VER_27:
3841 ops->write = r8168dp_1_mdio_write;
3842 ops->read = r8168dp_1_mdio_read;
3843 break;
e6de30d6 3844 case RTL_GIGA_MAC_VER_28:
4804b3b3 3845 case RTL_GIGA_MAC_VER_31:
e6de30d6 3846 ops->write = r8168dp_2_mdio_write;
3847 ops->read = r8168dp_2_mdio_read;
3848 break;
c558386b
HW		 3849 case RTL_GIGA_MAC_VER_40:
3850 case RTL_GIGA_MAC_VER_41:
3851 ops->write = r8168g_mdio_write;
3852 ops->read = r8168g_mdio_read;
3853 break;
c0e45c1c 3854 default:
3855 ops->write = r8169_mdio_write;
3856 ops->read = r8169_mdio_read;
3857 break;
3858 }
3859}
3860
649b3b8c 3861static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3862{
3863 void __iomem *ioaddr = tp->mmio_addr;
3864
3865 switch (tp->mac_version) {
b00e69de
CB		 3866 case RTL_GIGA_MAC_VER_25:
3867 case RTL_GIGA_MAC_VER_26:
649b3b8c 3868 case RTL_GIGA_MAC_VER_29:
3869 case RTL_GIGA_MAC_VER_30:
3870 case RTL_GIGA_MAC_VER_32:
3871 case RTL_GIGA_MAC_VER_33:
3872 case RTL_GIGA_MAC_VER_34:
7e18dca1 3873 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3874 case RTL_GIGA_MAC_VER_38:
5598bfe5 3875 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3876 case RTL_GIGA_MAC_VER_40:
3877 case RTL_GIGA_MAC_VER_41:
649b3b8c 3878 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3879 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3880 break;
3881 default:
3882 break;
3883 }
3884}
3885
3886static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3887{
3888 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3889 return false;
3890
3891 rtl_writephy(tp, 0x1f, 0x0000);
3892 rtl_writephy(tp, MII_BMCR, 0x0000);
3893
3894 rtl_wol_suspend_quirk(tp);
3895
3896 return true;
3897}
3898
065c27c1 3899static void r810x_phy_power_down(struct rtl8169_private *tp)
3900{
3901 rtl_writephy(tp, 0x1f, 0x0000);
3902 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3903}
3904
3905static void r810x_phy_power_up(struct rtl8169_private *tp)
3906{
3907 rtl_writephy(tp, 0x1f, 0x0000);
3908 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3909}
3910
3911static void r810x_pll_power_down(struct rtl8169_private *tp)
3912{
0004299a
HW		 3913 void __iomem *ioaddr = tp->mmio_addr;
3914
649b3b8c 3915 if (rtl_wol_pll_power_down(tp))
065c27c1 3916 return;
065c27c1 3917
3918 r810x_phy_power_down(tp);
0004299a
HW		 3919
3920 switch (tp->mac_version) {
3921 case RTL_GIGA_MAC_VER_07:
3922 case RTL_GIGA_MAC_VER_08:
3923 case RTL_GIGA_MAC_VER_09:
3924 case RTL_GIGA_MAC_VER_10:
3925 case RTL_GIGA_MAC_VER_13:
3926 case RTL_GIGA_MAC_VER_16:
3927 break;
3928 default:
3929 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3930 break;
3931 }
065c27c1 3932}
3933
3934static void r810x_pll_power_up(struct rtl8169_private *tp)
3935{
0004299a
HW		 3936 void __iomem *ioaddr = tp->mmio_addr;
3937
065c27c1 3938 r810x_phy_power_up(tp);
0004299a
HW		 3939
3940 switch (tp->mac_version) {
3941 case RTL_GIGA_MAC_VER_07:
3942 case RTL_GIGA_MAC_VER_08:
3943 case RTL_GIGA_MAC_VER_09:
3944 case RTL_GIGA_MAC_VER_10:
3945 case RTL_GIGA_MAC_VER_13:
3946 case RTL_GIGA_MAC_VER_16:
3947 break;
3948 default:
3949 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3950 break;
3951 }
065c27c1 3952}
3953
3954static void r8168_phy_power_up(struct rtl8169_private *tp)
3955{
3956 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3957 switch (tp->mac_version) {
3958 case RTL_GIGA_MAC_VER_11:
3959 case RTL_GIGA_MAC_VER_12:
3960 case RTL_GIGA_MAC_VER_17:
3961 case RTL_GIGA_MAC_VER_18:
3962 case RTL_GIGA_MAC_VER_19:
3963 case RTL_GIGA_MAC_VER_20:
3964 case RTL_GIGA_MAC_VER_21:
3965 case RTL_GIGA_MAC_VER_22:
3966 case RTL_GIGA_MAC_VER_23:
3967 case RTL_GIGA_MAC_VER_24:
3968 case RTL_GIGA_MAC_VER_25:
3969 case RTL_GIGA_MAC_VER_26:
3970 case RTL_GIGA_MAC_VER_27:
3971 case RTL_GIGA_MAC_VER_28:
3972 case RTL_GIGA_MAC_VER_31:
3973 rtl_writephy(tp, 0x0e, 0x0000);
3974 break;
3975 default:
3976 break;
3977 }
065c27c1 3978 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3979}
3980
3981static void r8168_phy_power_down(struct rtl8169_private *tp)
3982{
3983 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3984 switch (tp->mac_version) {
3985 case RTL_GIGA_MAC_VER_32:
3986 case RTL_GIGA_MAC_VER_33:
3987 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3988 break;
3989
3990 case RTL_GIGA_MAC_VER_11:
3991 case RTL_GIGA_MAC_VER_12:
3992 case RTL_GIGA_MAC_VER_17:
3993 case RTL_GIGA_MAC_VER_18:
3994 case RTL_GIGA_MAC_VER_19:
3995 case RTL_GIGA_MAC_VER_20:
3996 case RTL_GIGA_MAC_VER_21:
3997 case RTL_GIGA_MAC_VER_22:
3998 case RTL_GIGA_MAC_VER_23:
3999 case RTL_GIGA_MAC_VER_24:
4000 case RTL_GIGA_MAC_VER_25:
4001 case RTL_GIGA_MAC_VER_26:
4002 case RTL_GIGA_MAC_VER_27:
4003 case RTL_GIGA_MAC_VER_28:
4004 case RTL_GIGA_MAC_VER_31:
4005 rtl_writephy(tp, 0x0e, 0x0200);
4006 default:
4007 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4008 break;
4009 }
065c27c1 4010}
4011
4012static void r8168_pll_power_down(struct rtl8169_private *tp)
4013{
4014 void __iomem *ioaddr = tp->mmio_addr;
4015
cecb5fd7
FR		 4016 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4017 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4018 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4019 r8168dp_check_dash(tp)) {
065c27c1 4020 return;
5d2e1957 4021 }
065c27c1 4022
cecb5fd7
FR		 4023 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4024 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4025 (RTL_R16(CPlusCmd) & ASF)) {
4026 return;
4027 }
4028
01dc7fec 4029 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4030 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4031 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4032
649b3b8c 4033 if (rtl_wol_pll_power_down(tp))
065c27c1 4034 return;
065c27c1 4035
4036 r8168_phy_power_down(tp);
4037
4038 switch (tp->mac_version) {
4039 case RTL_GIGA_MAC_VER_25:
4040 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4041 case RTL_GIGA_MAC_VER_27:
4042 case RTL_GIGA_MAC_VER_28:
4804b3b3 4043 case RTL_GIGA_MAC_VER_31:
01dc7fec 4044 case RTL_GIGA_MAC_VER_32:
4045 case RTL_GIGA_MAC_VER_33:
065c27c1 4046 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4047 break;
4048 }
4049}
4050
4051static void r8168_pll_power_up(struct rtl8169_private *tp)
4052{
4053 void __iomem *ioaddr = tp->mmio_addr;
4054
065c27c1 4055 switch (tp->mac_version) {
4056 case RTL_GIGA_MAC_VER_25:
4057 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4058 case RTL_GIGA_MAC_VER_27:
4059 case RTL_GIGA_MAC_VER_28:
4804b3b3 4060 case RTL_GIGA_MAC_VER_31:
01dc7fec 4061 case RTL_GIGA_MAC_VER_32:
4062 case RTL_GIGA_MAC_VER_33:
065c27c1 4063 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4064 break;
4065 }
4066
4067 r8168_phy_power_up(tp);
4068}
4069
d58d46b5
FR		 4070static void rtl_generic_op(struct rtl8169_private *tp,
4071 void (*op)(struct rtl8169_private *))
065c27c1 4072{
4073 if (op)
4074 op(tp);
4075}
4076
4077static void rtl_pll_power_down(struct rtl8169_private *tp)
4078{
d58d46b5 4079 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4080}
4081
4082static void rtl_pll_power_up(struct rtl8169_private *tp)
4083{
d58d46b5 4084 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4085}
4086
baf63293 4087static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4088{
4089 struct pll_power_ops *ops = &tp->pll_power_ops;
4090
4091 switch (tp->mac_version) {
4092 case RTL_GIGA_MAC_VER_07:
4093 case RTL_GIGA_MAC_VER_08:
4094 case RTL_GIGA_MAC_VER_09:
4095 case RTL_GIGA_MAC_VER_10:
4096 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4097 case RTL_GIGA_MAC_VER_29:
4098 case RTL_GIGA_MAC_VER_30:
7e18dca1 4099 case RTL_GIGA_MAC_VER_37:
5598bfe5 4100 case RTL_GIGA_MAC_VER_39:
065c27c1 4101 ops->down = r810x_pll_power_down;
4102 ops->up = r810x_pll_power_up;
4103 break;
4104
4105 case RTL_GIGA_MAC_VER_11:
4106 case RTL_GIGA_MAC_VER_12:
4107 case RTL_GIGA_MAC_VER_17:
4108 case RTL_GIGA_MAC_VER_18:
4109 case RTL_GIGA_MAC_VER_19:
4110 case RTL_GIGA_MAC_VER_20:
4111 case RTL_GIGA_MAC_VER_21:
4112 case RTL_GIGA_MAC_VER_22:
4113 case RTL_GIGA_MAC_VER_23:
4114 case RTL_GIGA_MAC_VER_24:
4115 case RTL_GIGA_MAC_VER_25:
4116 case RTL_GIGA_MAC_VER_26:
4117 case RTL_GIGA_MAC_VER_27:
e6de30d6 4118 case RTL_GIGA_MAC_VER_28:
4804b3b3 4119 case RTL_GIGA_MAC_VER_31:
01dc7fec 4120 case RTL_GIGA_MAC_VER_32:
4121 case RTL_GIGA_MAC_VER_33:
70090424 4122 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4123 case RTL_GIGA_MAC_VER_35:
4124 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4125 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4126 case RTL_GIGA_MAC_VER_40:
4127 case RTL_GIGA_MAC_VER_41:
065c27c1 4128 ops->down = r8168_pll_power_down;
4129 ops->up = r8168_pll_power_up;
4130 break;
4131
4132 default:
4133 ops->down = NULL;
4134 ops->up = NULL;
4135 break;
4136 }
4137}
4138
e542a226
HW		 4139static void rtl_init_rxcfg(struct rtl8169_private *tp)
4140{
4141 void __iomem *ioaddr = tp->mmio_addr;
4142
4143 switch (tp->mac_version) {
4144 case RTL_GIGA_MAC_VER_01:
4145 case RTL_GIGA_MAC_VER_02:
4146 case RTL_GIGA_MAC_VER_03:
4147 case RTL_GIGA_MAC_VER_04:
4148 case RTL_GIGA_MAC_VER_05:
4149 case RTL_GIGA_MAC_VER_06:
4150 case RTL_GIGA_MAC_VER_10:
4151 case RTL_GIGA_MAC_VER_11:
4152 case RTL_GIGA_MAC_VER_12:
4153 case RTL_GIGA_MAC_VER_13:
4154 case RTL_GIGA_MAC_VER_14:
4155 case RTL_GIGA_MAC_VER_15:
4156 case RTL_GIGA_MAC_VER_16:
4157 case RTL_GIGA_MAC_VER_17:
4158 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4159 break;
4160 case RTL_GIGA_MAC_VER_18:
4161 case RTL_GIGA_MAC_VER_19:
4162 case RTL_GIGA_MAC_VER_20:
4163 case RTL_GIGA_MAC_VER_21:
4164 case RTL_GIGA_MAC_VER_22:
4165 case RTL_GIGA_MAC_VER_23:
4166 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4167 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4168 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4169 break;
4170 default:
4171 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4172 break;
4173 }
4174}
4175
92fc43b4
HW		 4176static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4177{
4178 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4179}
4180
d58d46b5
FR		 4181static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4182{
9c5028e9 4183 void __iomem *ioaddr = tp->mmio_addr;
4184
4185 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4186 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4187 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4188}
4189
4190static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4191{
9c5028e9 4192 void __iomem *ioaddr = tp->mmio_addr;
4193
4194 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4195 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4196 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4197}
4198
4199static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4200{
4201 void __iomem *ioaddr = tp->mmio_addr;
4202
4203 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4204 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4205 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4206}
4207
4208static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4209{
4210 void __iomem *ioaddr = tp->mmio_addr;
4211
4212 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4213 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4214 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4215}
4216
4217static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4218{
4219 void __iomem *ioaddr = tp->mmio_addr;
4220
4221 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4222}
4223
4224static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4225{
4226 void __iomem *ioaddr = tp->mmio_addr;
4227
4228 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4229}
4230
4231static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4232{
4233 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4234
4235 RTL_W8(MaxTxPacketSize, 0x3f);
4236 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4237 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4238 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4239}
4240
4241static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4242{
4243 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4244
4245 RTL_W8(MaxTxPacketSize, 0x0c);
4246 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4247 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4248 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4249}
4250
4251static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4252{
4253 rtl_tx_performance_tweak(tp->pci_dev,
4254 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4255}
4256
4257static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4258{
4259 rtl_tx_performance_tweak(tp->pci_dev,
4260 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4261}
4262
4263static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4264{
4265 void __iomem *ioaddr = tp->mmio_addr;
4266
4267 r8168b_0_hw_jumbo_enable(tp);
4268
4269 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4270}
4271
4272static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4273{
4274 void __iomem *ioaddr = tp->mmio_addr;
4275
4276 r8168b_0_hw_jumbo_disable(tp);
4277
4278 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4279}
4280
baf63293 4281static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4282{
4283 struct jumbo_ops *ops = &tp->jumbo_ops;
4284
4285 switch (tp->mac_version) {
4286 case RTL_GIGA_MAC_VER_11:
4287 ops->disable = r8168b_0_hw_jumbo_disable;
4288 ops->enable = r8168b_0_hw_jumbo_enable;
4289 break;
4290 case RTL_GIGA_MAC_VER_12:
4291 case RTL_GIGA_MAC_VER_17:
4292 ops->disable = r8168b_1_hw_jumbo_disable;
4293 ops->enable = r8168b_1_hw_jumbo_enable;
4294 break;
4295 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4296 case RTL_GIGA_MAC_VER_19:
4297 case RTL_GIGA_MAC_VER_20:
4298 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4299 case RTL_GIGA_MAC_VER_22:
4300 case RTL_GIGA_MAC_VER_23:
4301 case RTL_GIGA_MAC_VER_24:
4302 case RTL_GIGA_MAC_VER_25:
4303 case RTL_GIGA_MAC_VER_26:
4304 ops->disable = r8168c_hw_jumbo_disable;
4305 ops->enable = r8168c_hw_jumbo_enable;
4306 break;
4307 case RTL_GIGA_MAC_VER_27:
4308 case RTL_GIGA_MAC_VER_28:
4309 ops->disable = r8168dp_hw_jumbo_disable;
4310 ops->enable = r8168dp_hw_jumbo_enable;
4311 break;
4312 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4313 case RTL_GIGA_MAC_VER_32:
4314 case RTL_GIGA_MAC_VER_33:
4315 case RTL_GIGA_MAC_VER_34:
4316 ops->disable = r8168e_hw_jumbo_disable;
4317 ops->enable = r8168e_hw_jumbo_enable;
4318 break;
4319
4320 /*
4321 * No action needed for jumbo frames with 8169.
4322 * No jumbo for 810x at all.
4323 */
c558386b
HW		 4324 case RTL_GIGA_MAC_VER_40:
4325 case RTL_GIGA_MAC_VER_41:
d58d46b5
FR		 4326 default:
4327 ops->disable = NULL;
4328 ops->enable = NULL;
4329 break;
4330 }
4331}
4332
ffc46952
FR		 4333DECLARE_RTL_COND(rtl_chipcmd_cond)
4334{
4335 void __iomem *ioaddr = tp->mmio_addr;
4336
4337 return RTL_R8(ChipCmd) & CmdReset;
4338}
4339
6f43adc8
FR		 4340static void rtl_hw_reset(struct rtl8169_private *tp)
4341{
4342 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4343
6f43adc8
FR		 4344 RTL_W8(ChipCmd, CmdReset);
4345
ffc46952 4346 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4347}
4348
b6ffd97f 4349static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4350{
b6ffd97f
FR		 4351 struct rtl_fw *rtl_fw;
4352 const char *name;
4353 int rc = -ENOMEM;
953a12cc 4354
b6ffd97f
FR		 4355 name = rtl_lookup_firmware_name(tp);
4356 if (!name)
4357 goto out_no_firmware;
953a12cc 4358
b6ffd97f
FR		 4359 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4360 if (!rtl_fw)
4361 goto err_warn;
31bd204f 4362
b6ffd97f
FR		 4363 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4364 if (rc < 0)
4365 goto err_free;
4366
fd112f2e
FR		 4367 rc = rtl_check_firmware(tp, rtl_fw);
4368 if (rc < 0)
4369 goto err_release_firmware;
4370
b6ffd97f
FR		 4371 tp->rtl_fw = rtl_fw;
4372out:
4373 return;
4374
fd112f2e
FR		 4375err_release_firmware:
4376 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4377err_free:
4378 kfree(rtl_fw);
4379err_warn:
4380 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4381 name, rc);
4382out_no_firmware:
4383 tp->rtl_fw = NULL;
4384 goto out;
4385}
4386
4387static void rtl_request_firmware(struct rtl8169_private *tp)
4388{
4389 if (IS_ERR(tp->rtl_fw))
4390 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4391}
4392
92fc43b4
HW		 4393static void rtl_rx_close(struct rtl8169_private *tp)
4394{
4395 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4396
1687b566 4397 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4398}
4399
ffc46952
FR		 4400DECLARE_RTL_COND(rtl_npq_cond)
4401{
4402 void __iomem *ioaddr = tp->mmio_addr;
4403
4404 return RTL_R8(TxPoll) & NPQ;
4405}
4406
4407DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4408{
4409 void __iomem *ioaddr = tp->mmio_addr;
4410
4411 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4412}
4413
e6de30d6 4414static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4415{
e6de30d6 4416 void __iomem *ioaddr = tp->mmio_addr;
4417
1da177e4 4418 /* Disable interrupts */
811fd301 4419 rtl8169_irq_mask_and_ack(tp);
1da177e4 4420
92fc43b4
HW		 4421 rtl_rx_close(tp);
4422
5d2e1957 4423 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4424 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4425 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4426 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4427 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4428 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4429 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4430 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4431 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4432 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
b3d7b2f2 4433 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4434 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4435 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4436 } else {
4437 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4438 udelay(100);
e6de30d6 4439 }
4440
92fc43b4 4441 rtl_hw_reset(tp);
1da177e4
LT		 4442}
4443
7f796d83 4444static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4445{
4446 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4447
4448 /* Set DMA burst size and Interframe Gap Time */
4449 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4450 (InterFrameGap << TxInterFrameGapShift));
4451}
4452
07ce4064 4453static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4454{
4455 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4456
07ce4064
FR		 4457 tp->hw_start(dev);
4458
da78dbff 4459 rtl_irq_enable_all(tp);
07ce4064
FR		 4460}
4461
7f796d83
FR		 4462static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4463 void __iomem *ioaddr)
4464{
4465 /*
4466 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4467 * register to be written before TxDescAddrLow to work.
4468 * Switching from MMIO to I/O access fixes the issue as well.
4469 */
4470 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4471 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4472 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4473 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4474}
4475
4476static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4477{
4478 u16 cmd;
4479
4480 cmd = RTL_R16(CPlusCmd);
4481 RTL_W16(CPlusCmd, cmd);
4482 return cmd;
4483}
4484
fdd7b4c3 4485static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4486{
4487 /* Low hurts. Let's disable the filtering. */
207d6e87 4488 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4489}
4490
6dccd16b
FR		 4491static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4492{
3744100e 4493 static const struct rtl_cfg2_info {
6dccd16b
FR		 4494 u32 mac_version;
4495 u32 clk;
4496 u32 val;
4497 } cfg2_info [] = {
4498 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4499 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4500 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4501 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4502 };
4503 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4504 unsigned int i;
4505 u32 clk;
4506
4507 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4508 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4509 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4510 RTL_W32(0x7c, p->val);
4511 break;
4512 }
4513 }
4514}
4515
e6b763ea
FR		 4516static void rtl_set_rx_mode(struct net_device *dev)
4517{
4518 struct rtl8169_private *tp = netdev_priv(dev);
4519 void __iomem *ioaddr = tp->mmio_addr;
4520 u32 mc_filter[2]; /* Multicast hash filter */
4521 int rx_mode;
4522 u32 tmp = 0;
4523
4524 if (dev->flags & IFF_PROMISC) {
4525 /* Unconditionally log net taps. */
4526 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4527 rx_mode =
4528 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4529 AcceptAllPhys;
4530 mc_filter[1] = mc_filter[0] = 0xffffffff;
4531 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4532 (dev->flags & IFF_ALLMULTI)) {
4533 /* Too many to filter perfectly -- accept all multicasts. */
4534 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4535 mc_filter[1] = mc_filter[0] = 0xffffffff;
4536 } else {
4537 struct netdev_hw_addr *ha;
4538
4539 rx_mode = AcceptBroadcast | AcceptMyPhys;
4540 mc_filter[1] = mc_filter[0] = 0;
4541 netdev_for_each_mc_addr(ha, dev) {
4542 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4543 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4544 rx_mode |= AcceptMulticast;
4545 }
4546 }
4547
4548 if (dev->features & NETIF_F_RXALL)
4549 rx_mode |= (AcceptErr | AcceptRunt);
4550
4551 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4552
4553 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4554 u32 data = mc_filter[0];
4555
4556 mc_filter[0] = swab32(mc_filter[1]);
4557 mc_filter[1] = swab32(data);
4558 }
4559
0481776b
NW		 4560 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4561 mc_filter[1] = mc_filter[0] = 0xffffffff;
4562
e6b763ea
FR		 4563 RTL_W32(MAR0 + 4, mc_filter[1]);
4564 RTL_W32(MAR0 + 0, mc_filter[0]);
4565
4566 RTL_W32(RxConfig, tmp);
4567}
4568
07ce4064
FR		 4569static void rtl_hw_start_8169(struct net_device *dev)
4570{
4571 struct rtl8169_private *tp = netdev_priv(dev);
4572 void __iomem *ioaddr = tp->mmio_addr;
4573 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4574
9cb427b6
FR		 4575 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4576 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4577 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4578 }
4579
1da177e4 4580 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4581 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4582 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4583 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4584 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4585 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4586
e542a226
HW		 4587 rtl_init_rxcfg(tp);
4588
f0298f81 4589 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4590
6f0333b8 4591 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4592
cecb5fd7
FR		 4593 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4594 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4595 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4596 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4597 rtl_set_rx_tx_config_registers(tp);
1da177e4 4598
7f796d83 4599 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4600
cecb5fd7
FR		 4601 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4602 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4603 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4604 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4605 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4606 }
4607
bcf0bf90
FR		 4608 RTL_W16(CPlusCmd, tp->cp_cmd);
4609
6dccd16b
FR		 4610 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4611
1da177e4
LT		 4612 /*
4613 * Undocumented corner. Supposedly:
4614 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4615 */
4616 RTL_W16(IntrMitigate, 0x0000);
4617
7f796d83 4618 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4619
cecb5fd7
FR		 4620 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4621 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4622 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4623 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4624 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4625 rtl_set_rx_tx_config_registers(tp);
4626 }
4627
1da177e4 4628 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4629
4630 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4631 RTL_R8(IntrMask);
1da177e4
LT		 4632
4633 RTL_W32(RxMissed, 0);
4634
07ce4064 4635 rtl_set_rx_mode(dev);
1da177e4
LT		 4636
4637 /* no early-rx interrupts */
4638 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4639}
1da177e4 4640
beb1fe18
HW		 4641static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4642{
4643 if (tp->csi_ops.write)
52989f0e 4644 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4645}
4646
4647static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4648{
52989f0e 4649 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4650}
4651
4652static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4653{
4654 u32 csi;
4655
beb1fe18
HW		 4656 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4657 rtl_csi_write(tp, 0x070c, csi | bits);
4658}
4659
4660static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4661{
4662 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4663}
4664
beb1fe18 4665static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4666{
beb1fe18 4667 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4668}
4669
ffc46952
FR		 4670DECLARE_RTL_COND(rtl_csiar_cond)
4671{
4672 void __iomem *ioaddr = tp->mmio_addr;
4673
4674 return RTL_R32(CSIAR) & CSIAR_FLAG;
4675}
4676
52989f0e 4677static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4678{
52989f0e 4679 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4680
4681 RTL_W32(CSIDR, value);
4682 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4683 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4684
ffc46952 4685 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4686}
4687
52989f0e 4688static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4689{
52989f0e 4690 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4691
4692 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4693 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4694
ffc46952
FR		 4695 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4696 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4697}
4698
52989f0e 4699static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4700{
52989f0e 4701 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4702
4703 RTL_W32(CSIDR, value);
4704 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4705 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4706 CSIAR_FUNC_NIC);
4707
ffc46952 4708 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4709}
4710
52989f0e 4711static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4712{
52989f0e 4713 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4714
4715 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4716 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4717
ffc46952
FR		 4718 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4719 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4720}
4721
baf63293 4722static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 4723{
4724 struct csi_ops *ops = &tp->csi_ops;
4725
4726 switch (tp->mac_version) {
4727 case RTL_GIGA_MAC_VER_01:
4728 case RTL_GIGA_MAC_VER_02:
4729 case RTL_GIGA_MAC_VER_03:
4730 case RTL_GIGA_MAC_VER_04:
4731 case RTL_GIGA_MAC_VER_05:
4732 case RTL_GIGA_MAC_VER_06:
4733 case RTL_GIGA_MAC_VER_10:
4734 case RTL_GIGA_MAC_VER_11:
4735 case RTL_GIGA_MAC_VER_12:
4736 case RTL_GIGA_MAC_VER_13:
4737 case RTL_GIGA_MAC_VER_14:
4738 case RTL_GIGA_MAC_VER_15:
4739 case RTL_GIGA_MAC_VER_16:
4740 case RTL_GIGA_MAC_VER_17:
4741 ops->write = NULL;
4742 ops->read = NULL;
4743 break;
4744
7e18dca1 4745 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4746 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4747 ops->write = r8402_csi_write;
4748 ops->read = r8402_csi_read;
4749 break;
4750
beb1fe18
HW		 4751 default:
4752 ops->write = r8169_csi_write;
4753 ops->read = r8169_csi_read;
4754 break;
4755 }
dacf8154
FR		 4756}
4757
4758struct ephy_info {
4759 unsigned int offset;
4760 u16 mask;
4761 u16 bits;
4762};
4763
fdf6fc06
FR		 4764static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4765 int len)
dacf8154
FR		 4766{
4767 u16 w;
4768
4769 while (len-- > 0) {
fdf6fc06
FR		 4770 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4771 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4772 e++;
4773 }
4774}
4775
b726e493
FR		 4776static void rtl_disable_clock_request(struct pci_dev *pdev)
4777{
7d7903b2
JL		 4778 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4779 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4780}
4781
e6de30d6 4782static void rtl_enable_clock_request(struct pci_dev *pdev)
4783{
7d7903b2
JL		 4784 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4785 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4786}
4787
b726e493
FR		 4788#define R8168_CPCMD_QUIRK_MASK (\
4789 EnableBist | \
4790 Mac_dbgo_oe | \
4791 Force_half_dup | \
4792 Force_rxflow_en | \
4793 Force_txflow_en | \
4794 Cxpl_dbg_sel | \
4795 ASF | \
4796 PktCntrDisable | \
4797 Mac_dbgo_sel)
4798
beb1fe18 4799static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4800{
beb1fe18
HW		 4801 void __iomem *ioaddr = tp->mmio_addr;
4802 struct pci_dev *pdev = tp->pci_dev;
4803
b726e493
FR		 4804 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4805
4806 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4807
2e68ae44
FR		 4808 rtl_tx_performance_tweak(pdev,
4809 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4810}
4811
beb1fe18 4812static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4813{
beb1fe18
HW		 4814 void __iomem *ioaddr = tp->mmio_addr;
4815
4816 rtl_hw_start_8168bb(tp);
b726e493 4817
f0298f81 4818 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4819
4820 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4821}
4822
beb1fe18 4823static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4824{
beb1fe18
HW		 4825 void __iomem *ioaddr = tp->mmio_addr;
4826 struct pci_dev *pdev = tp->pci_dev;
4827
b726e493
FR		 4828 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4829
4830 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4831
219a1e9d 4832 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4833
4834 rtl_disable_clock_request(pdev);
4835
4836 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4837}
4838
beb1fe18 4839static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4840{
350f7596 4841 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4842 { 0x01, 0, 0x0001 },
4843 { 0x02, 0x0800, 0x1000 },
4844 { 0x03, 0, 0x0042 },
4845 { 0x06, 0x0080, 0x0000 },
4846 { 0x07, 0, 0x2000 }
4847 };
4848
beb1fe18 4849 rtl_csi_access_enable_2(tp);
b726e493 4850
fdf6fc06 4851 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4852
beb1fe18 4853 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4854}
4855
beb1fe18 4856static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4857{
beb1fe18
HW		 4858 void __iomem *ioaddr = tp->mmio_addr;
4859 struct pci_dev *pdev = tp->pci_dev;
4860
4861 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4862
4863 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4864
4865 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4866
4867 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4868}
4869
beb1fe18 4870static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4871{
beb1fe18
HW		 4872 void __iomem *ioaddr = tp->mmio_addr;
4873 struct pci_dev *pdev = tp->pci_dev;
4874
4875 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4876
4877 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4878
4879 /* Magic. */
4880 RTL_W8(DBG_REG, 0x20);
4881
f0298f81 4882 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4883
4884 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4885
4886 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4887}
4888
beb1fe18 4889static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4890{
beb1fe18 4891 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4892 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4893 { 0x02, 0x0800, 0x1000 },
4894 { 0x03, 0, 0x0002 },
4895 { 0x06, 0x0080, 0x0000 }
4896 };
4897
beb1fe18 4898 rtl_csi_access_enable_2(tp);
b726e493
FR		 4899
4900 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4901
fdf6fc06 4902 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4903
beb1fe18 4904 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4905}
4906
beb1fe18 4907static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4908{
350f7596 4909 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4910 { 0x01, 0, 0x0001 },
4911 { 0x03, 0x0400, 0x0220 }
4912 };
4913
beb1fe18 4914 rtl_csi_access_enable_2(tp);
b726e493 4915
fdf6fc06 4916 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4917
beb1fe18 4918 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4919}
4920
beb1fe18 4921static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4922{
beb1fe18 4923 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4924}
4925
beb1fe18 4926static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4927{
beb1fe18 4928 rtl_csi_access_enable_2(tp);
6fb07058 4929
beb1fe18 4930 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4931}
4932
beb1fe18 4933static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4934{
beb1fe18
HW		 4935 void __iomem *ioaddr = tp->mmio_addr;
4936 struct pci_dev *pdev = tp->pci_dev;
4937
4938 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4939
4940 rtl_disable_clock_request(pdev);
4941
f0298f81 4942 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4943
4944 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4945
4946 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4947}
4948
beb1fe18 4949static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4950{
beb1fe18
HW		 4951 void __iomem *ioaddr = tp->mmio_addr;
4952 struct pci_dev *pdev = tp->pci_dev;
4953
4954 rtl_csi_access_enable_1(tp);
4804b3b3 4955
4956 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4957
4958 RTL_W8(MaxTxPacketSize, TxPacketMax);
4959
4960 rtl_disable_clock_request(pdev);
4961}
4962
beb1fe18 4963static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4964{
beb1fe18
HW		 4965 void __iomem *ioaddr = tp->mmio_addr;
4966 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4967 static const struct ephy_info e_info_8168d_4[] = {
4968 { 0x0b, ~0, 0x48 },
4969 { 0x19, 0x20, 0x50 },
4970 { 0x0c, ~0, 0x20 }
4971 };
4972 int i;
4973
beb1fe18 4974 rtl_csi_access_enable_1(tp);
e6de30d6 4975
4976 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4977
4978 RTL_W8(MaxTxPacketSize, TxPacketMax);
4979
4980 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4981 const struct ephy_info *e = e_info_8168d_4 + i;
4982 u16 w;
4983
fdf6fc06
FR		 4984 w = rtl_ephy_read(tp, e->offset);
4985 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 4986 }
4987
4988 rtl_enable_clock_request(pdev);
4989}
4990
beb1fe18 4991static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4992{
beb1fe18
HW		 4993 void __iomem *ioaddr = tp->mmio_addr;
4994 struct pci_dev *pdev = tp->pci_dev;
70090424 4995 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4996 { 0x00, 0x0200, 0x0100 },
4997 { 0x00, 0x0000, 0x0004 },
4998 { 0x06, 0x0002, 0x0001 },
4999 { 0x06, 0x0000, 0x0030 },
5000 { 0x07, 0x0000, 0x2000 },
5001 { 0x00, 0x0000, 0x0020 },
5002 { 0x03, 0x5800, 0x2000 },
5003 { 0x03, 0x0000, 0x0001 },
5004 { 0x01, 0x0800, 0x1000 },
5005 { 0x07, 0x0000, 0x4000 },
5006 { 0x1e, 0x0000, 0x2000 },
5007 { 0x19, 0xffff, 0xfe6c },
5008 { 0x0a, 0x0000, 0x0040 }
5009 };
5010
beb1fe18 5011 rtl_csi_access_enable_2(tp);
01dc7fec 5012
fdf6fc06 5013 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5014
5015 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5016
5017 RTL_W8(MaxTxPacketSize, TxPacketMax);
5018
5019 rtl_disable_clock_request(pdev);
5020
5021 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5022 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5023 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5024
cecb5fd7 5025 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5026}
5027
beb1fe18 5028static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5029{
beb1fe18
HW		 5030 void __iomem *ioaddr = tp->mmio_addr;
5031 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5032 static const struct ephy_info e_info_8168e_2[] = {
5033 { 0x09, 0x0000, 0x0080 },
5034 { 0x19, 0x0000, 0x0224 }
5035 };
5036
beb1fe18 5037 rtl_csi_access_enable_1(tp);
70090424 5038
fdf6fc06 5039 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424
HW		 5040
5041 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5042
fdf6fc06
FR		 5043 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5044 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5045 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5046 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5047 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5048 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5049 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5050 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5051
3090bd9a 5052 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5053
70090424
HW		 5054 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5055 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5056
5057 /* Adjust EEE LED frequency */
5058 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5059
5060 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5061 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
d64ec841 5062 RTL_W8(Config5, (RTL_R8(Config5) & ~Spi_en) | ASPM_en);
5063 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
70090424
HW		 5064}
5065
5f886e08 5066static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5067{
beb1fe18
HW		 5068 void __iomem *ioaddr = tp->mmio_addr;
5069 struct pci_dev *pdev = tp->pci_dev;
c2218925 5070
5f886e08 5071 rtl_csi_access_enable_2(tp);
c2218925
HW		 5072
5073 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5074
fdf6fc06
FR		 5075 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5076 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5077 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5078 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5079 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5080 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5081 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5082 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5083 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5084 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5085
5086 RTL_W8(MaxTxPacketSize, EarlySize);
5087
c2218925
HW		 5088 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5089 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5090 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
d64ec841 5091 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN | FORCE_CLK);
5092 RTL_W8(Config5, (RTL_R8(Config5) & ~Spi_en) | ASPM_en);
5093 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
c2218925
HW		 5094}
5095
5f886e08
HW		 5096static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5097{
5098 void __iomem *ioaddr = tp->mmio_addr;
5099 static const struct ephy_info e_info_8168f_1[] = {
5100 { 0x06, 0x00c0, 0x0020 },
5101 { 0x08, 0x0001, 0x0002 },
5102 { 0x09, 0x0000, 0x0080 },
5103 { 0x19, 0x0000, 0x0224 }
5104 };
5105
5106 rtl_hw_start_8168f(tp);
5107
fdf6fc06 5108 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5109
fdf6fc06 5110 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5111
5112 /* Adjust EEE LED frequency */
5113 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5114}
5115
b3d7b2f2
HW		 5116static void rtl_hw_start_8411(struct rtl8169_private *tp)
5117{
b3d7b2f2
HW		 5118 static const struct ephy_info e_info_8168f_1[] = {
5119 { 0x06, 0x00c0, 0x0020 },
5120 { 0x0f, 0xffff, 0x5200 },
5121 { 0x1e, 0x0000, 0x4000 },
5122 { 0x19, 0x0000, 0x0224 }
5123 };
5124
5125 rtl_hw_start_8168f(tp);
5126
fdf6fc06 5127 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5128
fdf6fc06 5129 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5130}
5131
c558386b
HW		 5132static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5133{
5134 void __iomem *ioaddr = tp->mmio_addr;
5135 struct pci_dev *pdev = tp->pci_dev;
5136
5137 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5138 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5139 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5140 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5141
5142 rtl_csi_access_enable_1(tp);
5143
5144 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5145
5146 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5147 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5148
5149 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
d64ec841 5150 RTL_W32(MISC, (RTL_R32(MISC) | FORCE_CLK) & ~RXDV_GATED_EN);
c558386b 5151 RTL_W8(MaxTxPacketSize, EarlySize);
d64ec841 5152 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5153 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
c558386b
HW		 5154
5155 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5156 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5157
5158 /* Adjust EEE LED frequency */
5159 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5160
5161 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5162}
5163
07ce4064
FR		 5164static void rtl_hw_start_8168(struct net_device *dev)
5165{
2dd99530
FR		 5166 struct rtl8169_private *tp = netdev_priv(dev);
5167 void __iomem *ioaddr = tp->mmio_addr;
5168
5169 RTL_W8(Cfg9346, Cfg9346_Unlock);
5170
f0298f81 5171 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5172
6f0333b8 5173 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5174
0e485150 5175 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5176
5177 RTL_W16(CPlusCmd, tp->cp_cmd);
5178
0e485150 5179 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5180
0e485150 5181 /* Work around for RxFIFO overflow. */
811fd301 5182 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5183 tp->event_slow |= RxFIFOOver | PCSTimeout;
5184 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5185 }
5186
5187 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5188
b8363901
FR		 5189 rtl_set_rx_mode(dev);
5190
5191 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5192 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 5193
5194 RTL_R8(IntrMask);
5195
219a1e9d
FR		 5196 switch (tp->mac_version) {
5197 case RTL_GIGA_MAC_VER_11:
beb1fe18 5198 rtl_hw_start_8168bb(tp);
4804b3b3 5199 break;
219a1e9d
FR		 5200
5201 case RTL_GIGA_MAC_VER_12:
5202 case RTL_GIGA_MAC_VER_17:
beb1fe18 5203 rtl_hw_start_8168bef(tp);
4804b3b3 5204 break;
219a1e9d
FR		 5205
5206 case RTL_GIGA_MAC_VER_18:
beb1fe18 5207 rtl_hw_start_8168cp_1(tp);
4804b3b3 5208 break;
219a1e9d
FR		 5209
5210 case RTL_GIGA_MAC_VER_19:
beb1fe18 5211 rtl_hw_start_8168c_1(tp);
4804b3b3 5212 break;
219a1e9d
FR		 5213
5214 case RTL_GIGA_MAC_VER_20:
beb1fe18 5215 rtl_hw_start_8168c_2(tp);
4804b3b3 5216 break;
219a1e9d 5217
197ff761 5218 case RTL_GIGA_MAC_VER_21:
beb1fe18 5219 rtl_hw_start_8168c_3(tp);
4804b3b3 5220 break;
197ff761 5221
6fb07058 5222 case RTL_GIGA_MAC_VER_22:
beb1fe18 5223 rtl_hw_start_8168c_4(tp);
4804b3b3 5224 break;
6fb07058 5225
ef3386f0 5226 case RTL_GIGA_MAC_VER_23:
beb1fe18 5227 rtl_hw_start_8168cp_2(tp);
4804b3b3 5228 break;
ef3386f0 5229
7f3e3d3a 5230 case RTL_GIGA_MAC_VER_24:
beb1fe18 5231 rtl_hw_start_8168cp_3(tp);
4804b3b3 5232 break;
7f3e3d3a 5233
5b538df9 5234 case RTL_GIGA_MAC_VER_25:
daf9df6d 5235 case RTL_GIGA_MAC_VER_26:
5236 case RTL_GIGA_MAC_VER_27:
beb1fe18 5237 rtl_hw_start_8168d(tp);
4804b3b3 5238 break;
5b538df9 5239
e6de30d6 5240 case RTL_GIGA_MAC_VER_28:
beb1fe18 5241 rtl_hw_start_8168d_4(tp);
4804b3b3 5242 break;
cecb5fd7 5243
4804b3b3 5244 case RTL_GIGA_MAC_VER_31:
beb1fe18 5245 rtl_hw_start_8168dp(tp);
4804b3b3 5246 break;
5247
01dc7fec 5248 case RTL_GIGA_MAC_VER_32:
5249 case RTL_GIGA_MAC_VER_33:
beb1fe18 5250 rtl_hw_start_8168e_1(tp);
70090424
HW		 5251 break;
5252 case RTL_GIGA_MAC_VER_34:
beb1fe18 5253 rtl_hw_start_8168e_2(tp);
01dc7fec 5254 break;
e6de30d6 5255
c2218925
HW		 5256 case RTL_GIGA_MAC_VER_35:
5257 case RTL_GIGA_MAC_VER_36:
beb1fe18 5258 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5259 break;
5260
b3d7b2f2
HW		 5261 case RTL_GIGA_MAC_VER_38:
5262 rtl_hw_start_8411(tp);
5263 break;
5264
c558386b
HW		 5265 case RTL_GIGA_MAC_VER_40:
5266 case RTL_GIGA_MAC_VER_41:
5267 rtl_hw_start_8168g_1(tp);
5268 break;
5269
219a1e9d
FR		 5270 default:
5271 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5272 dev->name, tp->mac_version);
4804b3b3 5273 break;
219a1e9d 5274 }
2dd99530 5275
0e485150
FR		 5276 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5277
b8363901
FR		 5278 RTL_W8(Cfg9346, Cfg9346_Lock);
5279
2dd99530 5280 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5281}
1da177e4 5282
2857ffb7
FR		 5283#define R810X_CPCMD_QUIRK_MASK (\
5284 EnableBist | \
5285 Mac_dbgo_oe | \
5286 Force_half_dup | \
5edcc537 5287 Force_rxflow_en | \
2857ffb7
FR		 5288 Force_txflow_en | \
5289 Cxpl_dbg_sel | \
5290 ASF | \
5291 PktCntrDisable | \
d24e9aaf 5292 Mac_dbgo_sel)
2857ffb7 5293
beb1fe18 5294static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5295{
beb1fe18
HW		 5296 void __iomem *ioaddr = tp->mmio_addr;
5297 struct pci_dev *pdev = tp->pci_dev;
350f7596 5298 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5299 { 0x01, 0, 0x6e65 },
5300 { 0x02, 0, 0x091f },
5301 { 0x03, 0, 0xc2f9 },
5302 { 0x06, 0, 0xafb5 },
5303 { 0x07, 0, 0x0e00 },
5304 { 0x19, 0, 0xec80 },
5305 { 0x01, 0, 0x2e65 },
5306 { 0x01, 0, 0x6e65 }
5307 };
5308 u8 cfg1;
5309
beb1fe18 5310 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5311
5312 RTL_W8(DBG_REG, FIX_NAK_1);
5313
5314 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5315
5316 RTL_W8(Config1,
5317 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5318 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5319
5320 cfg1 = RTL_R8(Config1);
5321 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5322 RTL_W8(Config1, cfg1 & ~LEDS0);
5323
fdf6fc06 5324 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5325}
5326
beb1fe18 5327static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5328{
beb1fe18
HW		 5329 void __iomem *ioaddr = tp->mmio_addr;
5330 struct pci_dev *pdev = tp->pci_dev;
5331
5332 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5333
5334 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5335
5336 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5337 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5338}
5339
beb1fe18 5340static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5341{
beb1fe18 5342 rtl_hw_start_8102e_2(tp);
2857ffb7 5343
fdf6fc06 5344 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5345}
5346
beb1fe18 5347static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5348{
beb1fe18 5349 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5350 static const struct ephy_info e_info_8105e_1[] = {
5351 { 0x07, 0, 0x4000 },
5352 { 0x19, 0, 0x0200 },
5353 { 0x19, 0, 0x0020 },
5354 { 0x1e, 0, 0x2000 },
5355 { 0x03, 0, 0x0001 },
5356 { 0x19, 0, 0x0100 },
5357 { 0x19, 0, 0x0004 },
5358 { 0x0a, 0, 0x0020 }
5359 };
5360
cecb5fd7 5361 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5362 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5363
cecb5fd7 5364 /* Disable Early Tally Counter */
5a5e4443
HW		 5365 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5366
5367 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5368 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
d64ec841 5369 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5370 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5371 RTL_W32(MISC, RTL_R32(MISC) | FORCE_CLK);
5a5e4443 5372
fdf6fc06 5373 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5374}
5375
beb1fe18 5376static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5377{
beb1fe18 5378 rtl_hw_start_8105e_1(tp);
fdf6fc06 5379 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5380}
5381
7e18dca1
HW		 5382static void rtl_hw_start_8402(struct rtl8169_private *tp)
5383{
5384 void __iomem *ioaddr = tp->mmio_addr;
5385 static const struct ephy_info e_info_8402[] = {
5386 { 0x19, 0xffff, 0xff64 },
5387 { 0x1e, 0, 0x4000 }
5388 };
5389
5390 rtl_csi_access_enable_2(tp);
5391
5392 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5393 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5394
5395 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5396 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
d64ec841 5397 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5398 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5399 RTL_W32(MISC, RTL_R32(MISC) | FORCE_CLK);
7e18dca1 5400
fdf6fc06 5401 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5402
5403 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5404
fdf6fc06
FR		 5405 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5406 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5407 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5408 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5409 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5410 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5411 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5412}
5413
5598bfe5
HW		 5414static void rtl_hw_start_8106(struct rtl8169_private *tp)
5415{
5416 void __iomem *ioaddr = tp->mmio_addr;
5417
5418 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5419 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5420
d64ec841 5421 RTL_W32(MISC,
5422 (RTL_R32(MISC) | DISABLE_LAN_EN | FORCE_CLK) & ~EARLY_TALLY_EN);
5423 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5424 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5598bfe5
HW		 5425 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5426 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5427}
5428
07ce4064
FR		 5429static void rtl_hw_start_8101(struct net_device *dev)
5430{
cdf1a608
FR		 5431 struct rtl8169_private *tp = netdev_priv(dev);
5432 void __iomem *ioaddr = tp->mmio_addr;
5433 struct pci_dev *pdev = tp->pci_dev;
5434
da78dbff
FR		 5435 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5436 tp->event_slow &= ~RxFIFOOver;
811fd301 5437
cecb5fd7 5438 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5439 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 5440 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5441 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5442
d24e9aaf
HW		 5443 RTL_W8(Cfg9346, Cfg9346_Unlock);
5444
2857ffb7
FR		 5445 switch (tp->mac_version) {
5446 case RTL_GIGA_MAC_VER_07:
beb1fe18 5447 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5448 break;
5449
5450 case RTL_GIGA_MAC_VER_08:
beb1fe18 5451 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5452 break;
5453
5454 case RTL_GIGA_MAC_VER_09:
beb1fe18 5455 rtl_hw_start_8102e_2(tp);
2857ffb7 5456 break;
5a5e4443
HW		 5457
5458 case RTL_GIGA_MAC_VER_29:
beb1fe18 5459 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5460 break;
5461 case RTL_GIGA_MAC_VER_30:
beb1fe18 5462 rtl_hw_start_8105e_2(tp);
5a5e4443 5463 break;
7e18dca1
HW		 5464
5465 case RTL_GIGA_MAC_VER_37:
5466 rtl_hw_start_8402(tp);
5467 break;
5598bfe5
HW		 5468
5469 case RTL_GIGA_MAC_VER_39:
5470 rtl_hw_start_8106(tp);
5471 break;
cdf1a608
FR		 5472 }
5473
d24e9aaf 5474 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5475
f0298f81 5476 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5477
6f0333b8 5478 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5479
d24e9aaf 5480 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5481 RTL_W16(CPlusCmd, tp->cp_cmd);
5482
5483 RTL_W16(IntrMitigate, 0x0000);
5484
5485 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5486
5487 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5488 rtl_set_rx_tx_config_registers(tp);
5489
cdf1a608
FR		 5490 RTL_R8(IntrMask);
5491
cdf1a608
FR		 5492 rtl_set_rx_mode(dev);
5493
5494 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5495}
5496
5497static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5498{
d58d46b5
FR		 5499 struct rtl8169_private *tp = netdev_priv(dev);
5500
5501 if (new_mtu < ETH_ZLEN ||
5502 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5503 return -EINVAL;
5504
d58d46b5
FR		 5505 if (new_mtu > ETH_DATA_LEN)
5506 rtl_hw_jumbo_enable(tp);
5507 else
5508 rtl_hw_jumbo_disable(tp);
5509
1da177e4 5510 dev->mtu = new_mtu;
350fb32a
MM		 5511 netdev_update_features(dev);
5512
323bb685 5513 return 0;
1da177e4
LT		 5514}
5515
5516static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5517{
95e0918d 5518 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5519 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5520}
5521
6f0333b8
ED		 5522static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5523 void **data_buff, struct RxDesc *desc)
1da177e4 5524{
48addcc9 5525 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5526 DMA_FROM_DEVICE);
48addcc9 5527
6f0333b8
ED		 5528 kfree(*data_buff);
5529 *data_buff = NULL;
1da177e4
LT		 5530 rtl8169_make_unusable_by_asic(desc);
5531}
5532
5533static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5534{
5535 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5536
5537 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5538}
5539
5540static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5541 u32 rx_buf_sz)
5542{
5543 desc->addr = cpu_to_le64(mapping);
5544 wmb();
5545 rtl8169_mark_to_asic(desc, rx_buf_sz);
5546}
5547
6f0333b8
ED		 5548static inline void *rtl8169_align(void *data)
5549{
5550 return (void *)ALIGN((long)data, 16);
5551}
5552
0ecbe1ca
SG		 5553static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5554 struct RxDesc *desc)
1da177e4 5555{
6f0333b8 5556 void *data;
1da177e4 5557 dma_addr_t mapping;
48addcc9 5558 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5559 struct net_device *dev = tp->dev;
6f0333b8 5560 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5561
6f0333b8
ED		 5562 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5563 if (!data)
5564 return NULL;
e9f63f30 5565
6f0333b8
ED		 5566 if (rtl8169_align(data) != data) {
5567 kfree(data);
5568 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5569 if (!data)
5570 return NULL;
5571 }
3eafe507 5572
48addcc9 5573 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5574 DMA_FROM_DEVICE);
d827d86b
SG		 5575 if (unlikely(dma_mapping_error(d, mapping))) {
5576 if (net_ratelimit())
5577 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5578 goto err_out;
d827d86b 5579 }
1da177e4
LT		 5580
5581 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5582 return data;
3eafe507
SG		 5583
5584err_out:
5585 kfree(data);
5586 return NULL;
1da177e4
LT		 5587}
5588
5589static void rtl8169_rx_clear(struct rtl8169_private *tp)
5590{
07d3f51f 5591 unsigned int i;
1da177e4
LT		 5592
5593 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5594 if (tp->Rx_databuff[i]) {
5595 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5596 tp->RxDescArray + i);
5597 }
5598 }
5599}
5600
0ecbe1ca 5601static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5602{
0ecbe1ca
SG		 5603 desc->opts1 |= cpu_to_le32(RingEnd);
5604}
5b0384f4 5605
0ecbe1ca
SG		 5606static int rtl8169_rx_fill(struct rtl8169_private *tp)
5607{
5608 unsigned int i;
1da177e4 5609
0ecbe1ca
SG		 5610 for (i = 0; i < NUM_RX_DESC; i++) {
5611 void *data;
4ae47c2d 5612
6f0333b8 5613 if (tp->Rx_databuff[i])
1da177e4 5614 continue;
bcf0bf90 5615
0ecbe1ca 5616 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5617 if (!data) {
5618 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5619 goto err_out;
6f0333b8
ED		 5620 }
5621 tp->Rx_databuff[i] = data;
1da177e4 5622 }
1da177e4 5623
0ecbe1ca
SG		 5624 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5625 return 0;
5626
5627err_out:
5628 rtl8169_rx_clear(tp);
5629 return -ENOMEM;
1da177e4
LT		 5630}
5631
1da177e4
LT		 5632static int rtl8169_init_ring(struct net_device *dev)
5633{
5634 struct rtl8169_private *tp = netdev_priv(dev);
5635
5636 rtl8169_init_ring_indexes(tp);
5637
5638 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5639 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5640
0ecbe1ca 5641 return rtl8169_rx_fill(tp);
1da177e4
LT		 5642}
5643
48addcc9 5644static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5645 struct TxDesc *desc)
5646{
5647 unsigned int len = tx_skb->len;
5648
48addcc9
SG		 5649 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5650
1da177e4
LT		 5651 desc->opts1 = 0x00;
5652 desc->opts2 = 0x00;
5653 desc->addr = 0x00;
5654 tx_skb->len = 0;
5655}
5656
3eafe507
SG		 5657static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5658 unsigned int n)
1da177e4
LT		 5659{
5660 unsigned int i;
5661
3eafe507
SG		 5662 for (i = 0; i < n; i++) {
5663 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5664 struct ring_info *tx_skb = tp->tx_skb + entry;
5665 unsigned int len = tx_skb->len;
5666
5667 if (len) {
5668 struct sk_buff *skb = tx_skb->skb;
5669
48addcc9 5670 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5671 tp->TxDescArray + entry);
5672 if (skb) {
cac4b22f 5673 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5674 dev_kfree_skb(skb);
5675 tx_skb->skb = NULL;
5676 }
1da177e4
LT		 5677 }
5678 }
3eafe507
SG		 5679}
5680
5681static void rtl8169_tx_clear(struct rtl8169_private *tp)
5682{
5683 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5684 tp->cur_tx = tp->dirty_tx = 0;
5685}
5686
4422bcd4 5687static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5688{
c4028958 5689 struct net_device *dev = tp->dev;
56de414c 5690 int i;
1da177e4 5691
da78dbff
FR		 5692 napi_disable(&tp->napi);
5693 netif_stop_queue(dev);
5694 synchronize_sched();
1da177e4 5695
c7c2c39b 5696 rtl8169_hw_reset(tp);
5697
56de414c
FR		 5698 for (i = 0; i < NUM_RX_DESC; i++)
5699 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5700
1da177e4 5701 rtl8169_tx_clear(tp);
c7c2c39b 5702 rtl8169_init_ring_indexes(tp);
1da177e4 5703
da78dbff 5704 napi_enable(&tp->napi);
56de414c
FR		 5705 rtl_hw_start(dev);
5706 netif_wake_queue(dev);
5707 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5708}
5709
5710static void rtl8169_tx_timeout(struct net_device *dev)
5711{
da78dbff
FR		 5712 struct rtl8169_private *tp = netdev_priv(dev);
5713
5714 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5715}
5716
5717static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5718 u32 *opts)
1da177e4
LT		 5719{
5720 struct skb_shared_info *info = skb_shinfo(skb);
5721 unsigned int cur_frag, entry;
a6343afb 5722 struct TxDesc * uninitialized_var(txd);
48addcc9 5723 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5724
5725 entry = tp->cur_tx;
5726 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5727 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5728 dma_addr_t mapping;
5729 u32 status, len;
5730 void *addr;
5731
5732 entry = (entry + 1) % NUM_TX_DESC;
5733
5734 txd = tp->TxDescArray + entry;
9e903e08 5735 len = skb_frag_size(frag);
929f6189 5736 addr = skb_frag_address(frag);
48addcc9 5737 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5738 if (unlikely(dma_mapping_error(d, mapping))) {
5739 if (net_ratelimit())
5740 netif_err(tp, drv, tp->dev,
5741 "Failed to map TX fragments DMA!\n");
3eafe507 5742 goto err_out;
d827d86b 5743 }
1da177e4 5744
cecb5fd7 5745 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5746 status = opts[0] | len |
5747 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5748
5749 txd->opts1 = cpu_to_le32(status);
2b7b4318 5750 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5751 txd->addr = cpu_to_le64(mapping);
5752
5753 tp->tx_skb[entry].len = len;
5754 }
5755
5756 if (cur_frag) {
5757 tp->tx_skb[entry].skb = skb;
5758 txd->opts1 |= cpu_to_le32(LastFrag);
5759 }
5760
5761 return cur_frag;
3eafe507
SG		 5762
5763err_out:
5764 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5765 return -EIO;
1da177e4
LT		 5766}
5767
2b7b4318
FR		 5768static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5769 struct sk_buff *skb, u32 *opts)
1da177e4 5770{
2b7b4318 5771 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5772 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5773 int offset = info->opts_offset;
350fb32a 5774
2b7b4318
FR		 5775 if (mss) {
5776 opts[0] |= TD_LSO;
5777 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5778 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5779 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5780
5781 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5782 opts[offset] |= info->checksum.tcp;
1da177e4 5783 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5784 opts[offset] |= info->checksum.udp;
5785 else
5786 WARN_ON_ONCE(1);
1da177e4 5787 }
1da177e4
LT		 5788}
5789
61357325
SH		 5790static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5791 struct net_device *dev)
1da177e4
LT		 5792{
5793 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5794 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5795 struct TxDesc *txd = tp->TxDescArray + entry;
5796 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5797 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5798 dma_addr_t mapping;
5799 u32 status, len;
2b7b4318 5800 u32 opts[2];
3eafe507 5801 int frags;
5b0384f4 5802
477206a0 5803 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5804 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5805 goto err_stop_0;
1da177e4
LT		 5806 }
5807
5808 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5809 goto err_stop_0;
5810
5811 len = skb_headlen(skb);
48addcc9 5812 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5813 if (unlikely(dma_mapping_error(d, mapping))) {
5814 if (net_ratelimit())
5815 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5816 goto err_dma_0;
d827d86b 5817 }
3eafe507
SG		 5818
5819 tp->tx_skb[entry].len = len;
5820 txd->addr = cpu_to_le64(mapping);
1da177e4 5821
810f4893 5822 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
2b7b4318 5823 opts[0] = DescOwn;
1da177e4 5824
2b7b4318
FR		 5825 rtl8169_tso_csum(tp, skb, opts);
5826
5827 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5828 if (frags < 0)
5829 goto err_dma_1;
5830 else if (frags)
2b7b4318 5831 opts[0] |= FirstFrag;
3eafe507 5832 else {
2b7b4318 5833 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5834 tp->tx_skb[entry].skb = skb;
5835 }
5836
2b7b4318
FR		 5837 txd->opts2 = cpu_to_le32(opts[1]);
5838
5047fb5d
RC		 5839 skb_tx_timestamp(skb);
5840
1da177e4
LT		 5841 wmb();
5842
cecb5fd7 5843 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5844 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5845 txd->opts1 = cpu_to_le32(status);
5846
1da177e4
LT		 5847 tp->cur_tx += frags + 1;
5848
4c020a96 5849 wmb();
1da177e4 5850
cecb5fd7 5851 RTL_W8(TxPoll, NPQ);
1da177e4 5852
da78dbff
FR		 5853 mmiowb();
5854
477206a0 5855 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5856 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5857 * not miss a ring update when it notices a stopped queue.
5858 */
5859 smp_wmb();
1da177e4 5860 netif_stop_queue(dev);
ae1f23fb
FR		 5861 /* Sync with rtl_tx:
5862 * - publish queue status and cur_tx ring index (write barrier)
5863 * - refresh dirty_tx ring index (read barrier).
5864 * May the current thread have a pessimistic view of the ring
5865 * status and forget to wake up queue, a racing rtl_tx thread
5866 * can't.
5867 */
1e874e04 5868 smp_mb();
477206a0 5869 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5870 netif_wake_queue(dev);
5871 }
5872
61357325 5873 return NETDEV_TX_OK;
1da177e4 5874
3eafe507 5875err_dma_1:
48addcc9 5876 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5877err_dma_0:
5878 dev_kfree_skb(skb);
5879 dev->stats.tx_dropped++;
5880 return NETDEV_TX_OK;
5881
5882err_stop_0:
1da177e4 5883 netif_stop_queue(dev);
cebf8cc7 5884 dev->stats.tx_dropped++;
61357325 5885 return NETDEV_TX_BUSY;
1da177e4
LT		 5886}
5887
5888static void rtl8169_pcierr_interrupt(struct net_device *dev)
5889{
5890 struct rtl8169_private *tp = netdev_priv(dev);
5891 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5892 u16 pci_status, pci_cmd;
5893
5894 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5895 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5896
bf82c189
JP		 5897 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5898 pci_cmd, pci_status);
1da177e4
LT		 5899
5900 /*
5901 * The recovery sequence below admits a very elaborated explanation:
5902 * - it seems to work;
d03902b8
FR		 5903 * - I did not see what else could be done;
5904 * - it makes iop3xx happy.
1da177e4
LT		 5905 *
5906 * Feel free to adjust to your needs.
5907 */
a27993f3 5908 if (pdev->broken_parity_status)
d03902b8
FR		 5909 pci_cmd &= ~PCI_COMMAND_PARITY;
5910 else
5911 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5912
5913 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5914
5915 pci_write_config_word(pdev, PCI_STATUS,
5916 pci_status & (PCI_STATUS_DETECTED_PARITY |
5917 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5918 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5919
5920 /* The infamous DAC f*ckup only happens at boot time */
5921 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5922 void __iomem *ioaddr = tp->mmio_addr;
5923
bf82c189 5924 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5925 tp->cp_cmd &= ~PCIDAC;
5926 RTL_W16(CPlusCmd, tp->cp_cmd);
5927 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5928 }
5929
e6de30d6 5930 rtl8169_hw_reset(tp);
d03902b8 5931
98ddf986 5932 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5933}
5934
da78dbff 5935static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5936{
5937 unsigned int dirty_tx, tx_left;
5938
1da177e4
LT		 5939 dirty_tx = tp->dirty_tx;
5940 smp_rmb();
5941 tx_left = tp->cur_tx - dirty_tx;
5942
5943 while (tx_left > 0) {
5944 unsigned int entry = dirty_tx % NUM_TX_DESC;
5945 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5946 u32 status;
5947
5948 rmb();
5949 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5950 if (status & DescOwn)
5951 break;
5952
48addcc9
SG		 5953 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5954 tp->TxDescArray + entry);
1da177e4 5955 if (status & LastFrag) {
17bcb684
FR		 5956 u64_stats_update_begin(&tp->tx_stats.syncp);
5957 tp->tx_stats.packets++;
5958 tp->tx_stats.bytes += tx_skb->skb->len;
5959 u64_stats_update_end(&tp->tx_stats.syncp);
5960 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5961 tx_skb->skb = NULL;
5962 }
5963 dirty_tx++;
5964 tx_left--;
5965 }
5966
5967 if (tp->dirty_tx != dirty_tx) {
5968 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5969 /* Sync with rtl8169_start_xmit:
5970 * - publish dirty_tx ring index (write barrier)
5971 * - refresh cur_tx ring index and queue status (read barrier)
5972 * May the current thread miss the stopped queue condition,
5973 * a racing xmit thread can only have a right view of the
5974 * ring status.
5975 */
1e874e04 5976 smp_mb();
1da177e4 5977 if (netif_queue_stopped(dev) &&
477206a0 5978 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5979 netif_wake_queue(dev);
5980 }
d78ae2dc
FR		 5981 /*
5982 * 8168 hack: TxPoll requests are lost when the Tx packets are
5983 * too close. Let's kick an extra TxPoll request when a burst
5984 * of start_xmit activity is detected (if it is not detected,
5985 * it is slow enough). -- FR
5986 */
da78dbff
FR		 5987 if (tp->cur_tx != dirty_tx) {
5988 void __iomem *ioaddr = tp->mmio_addr;
5989
d78ae2dc 5990 RTL_W8(TxPoll, NPQ);
da78dbff 5991 }
1da177e4
LT		 5992 }
5993}
5994
126fa4b9
FR		 5995static inline int rtl8169_fragmented_frame(u32 status)
5996{
5997 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5998}
5999
adea1ac7 6000static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6001{
1da177e4
LT		 6002 u32 status = opts1 & RxProtoMask;
6003
6004 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6005 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6006 skb->ip_summed = CHECKSUM_UNNECESSARY;
6007 else
bc8acf2c 6008 skb_checksum_none_assert(skb);
1da177e4
LT		 6009}
6010
6f0333b8
ED		 6011static struct sk_buff *rtl8169_try_rx_copy(void *data,
6012 struct rtl8169_private *tp,
6013 int pkt_size,
6014 dma_addr_t addr)
1da177e4 6015{
b449655f 6016 struct sk_buff *skb;
48addcc9 6017 struct device *d = &tp->pci_dev->dev;
b449655f 6018
6f0333b8 6019 data = rtl8169_align(data);
48addcc9 6020 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6021 prefetch(data);
6022 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6023 if (skb)
6024 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6025 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6026
6f0333b8 6027 return skb;
1da177e4
LT		 6028}
6029
da78dbff 6030static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6031{
6032 unsigned int cur_rx, rx_left;
6f0333b8 6033 unsigned int count;
1da177e4 6034
1da177e4
LT		 6035 cur_rx = tp->cur_rx;
6036 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 6037 rx_left = min(rx_left, budget);
1da177e4 6038
4dcb7d33 6039 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6040 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6041 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6042 u32 status;
6043
6044 rmb();
e03f33af 6045 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6046
6047 if (status & DescOwn)
6048 break;
4dcb7d33 6049 if (unlikely(status & RxRES)) {
bf82c189
JP		 6050 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6051 status);
cebf8cc7 6052 dev->stats.rx_errors++;
1da177e4 6053 if (status & (RxRWT | RxRUNT))
cebf8cc7 6054 dev->stats.rx_length_errors++;
1da177e4 6055 if (status & RxCRC)
cebf8cc7 6056 dev->stats.rx_crc_errors++;
9dccf611 6057 if (status & RxFOVF) {
da78dbff 6058 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6059 dev->stats.rx_fifo_errors++;
9dccf611 6060 }
6bbe021d
BG		 6061 if ((status & (RxRUNT | RxCRC)) &&
6062 !(status & (RxRWT | RxFOVF)) &&
6063 (dev->features & NETIF_F_RXALL))
6064 goto process_pkt;
1da177e4 6065 } else {
6f0333b8 6066 struct sk_buff *skb;
6bbe021d
BG		 6067 dma_addr_t addr;
6068 int pkt_size;
6069
6070process_pkt:
6071 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6072 if (likely(!(dev->features & NETIF_F_RXFCS)))
6073 pkt_size = (status & 0x00003fff) - 4;
6074 else
6075 pkt_size = status & 0x00003fff;
1da177e4 6076
126fa4b9
FR		 6077 /*
6078 * The driver does not support incoming fragmented
6079 * frames. They are seen as a symptom of over-mtu
6080 * sized frames.
6081 */
6082 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6083 dev->stats.rx_dropped++;
6084 dev->stats.rx_length_errors++;
ce11ff5e 6085 goto release_descriptor;
126fa4b9
FR		 6086 }
6087
6f0333b8
ED		 6088 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6089 tp, pkt_size, addr);
6f0333b8
ED		 6090 if (!skb) {
6091 dev->stats.rx_dropped++;
ce11ff5e 6092 goto release_descriptor;
1da177e4
LT		 6093 }
6094
adea1ac7 6095 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6096 skb_put(skb, pkt_size);
6097 skb->protocol = eth_type_trans(skb, dev);
6098
7a8fc77b
FR		 6099 rtl8169_rx_vlan_tag(desc, skb);
6100
56de414c 6101 napi_gro_receive(&tp->napi, skb);
1da177e4 6102
8027aa24
JW		 6103 u64_stats_update_begin(&tp->rx_stats.syncp);
6104 tp->rx_stats.packets++;
6105 tp->rx_stats.bytes += pkt_size;
6106 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6107 }
ce11ff5e 6108release_descriptor:
6109 desc->opts2 = 0;
6110 wmb();
6111 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 6112 }
6113
6114 count = cur_rx - tp->cur_rx;
6115 tp->cur_rx = cur_rx;
6116
6f0333b8 6117 tp->dirty_rx += count;
1da177e4
LT		 6118
6119 return count;
6120}
6121
07d3f51f 6122static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6123{
07d3f51f 6124 struct net_device *dev = dev_instance;
1da177e4 6125 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6126 int handled = 0;
9085cdfa 6127 u16 status;
1da177e4 6128
9085cdfa 6129 status = rtl_get_events(tp);
da78dbff
FR		 6130 if (status && status != 0xffff) {
6131 status &= RTL_EVENT_NAPI | tp->event_slow;
6132 if (status) {
6133 handled = 1;
1da177e4 6134
da78dbff
FR		 6135 rtl_irq_disable(tp);
6136 napi_schedule(&tp->napi);
f11a377b 6137 }
da78dbff
FR		 6138 }
6139 return IRQ_RETVAL(handled);
6140}
1da177e4 6141
da78dbff
FR		 6142/*
6143 * Workqueue context.
6144 */
6145static void rtl_slow_event_work(struct rtl8169_private *tp)
6146{
6147 struct net_device *dev = tp->dev;
6148 u16 status;
6149
6150 status = rtl_get_events(tp) & tp->event_slow;
6151 rtl_ack_events(tp, status);
1da177e4 6152
da78dbff
FR		 6153 if (unlikely(status & RxFIFOOver)) {
6154 switch (tp->mac_version) {
6155 /* Work around for rx fifo overflow */
6156 case RTL_GIGA_MAC_VER_11:
6157 netif_stop_queue(dev);
934714d0
FR		 6158 /* XXX - Hack alert. See rtl_task(). */
6159 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6160 default:
f11a377b
DD		 6161 break;
6162 }
da78dbff 6163 }
1da177e4 6164
da78dbff
FR		 6165 if (unlikely(status & SYSErr))
6166 rtl8169_pcierr_interrupt(dev);
0e485150 6167
da78dbff
FR		 6168 if (status & LinkChg)
6169 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6170
7dbb4918 6171 rtl_irq_enable_all(tp);
1da177e4
LT		 6172}
6173
4422bcd4
FR		 6174static void rtl_task(struct work_struct *work)
6175{
da78dbff
FR		 6176 static const struct {
6177 int bitnr;
6178 void (*action)(struct rtl8169_private *);
6179 } rtl_work[] = {
934714d0 6180 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6181 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6182 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6183 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6184 };
4422bcd4
FR		 6185 struct rtl8169_private *tp =
6186 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6187 struct net_device *dev = tp->dev;
6188 int i;
6189
6190 rtl_lock_work(tp);
6191
6c4a70c5
FR		 6192 if (!netif_running(dev) ||
6193 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6194 goto out_unlock;
6195
6196 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6197 bool pending;
6198
da78dbff 6199 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6200 if (pending)
6201 rtl_work[i].action(tp);
6202 }
4422bcd4 6203
da78dbff
FR		 6204out_unlock:
6205 rtl_unlock_work(tp);
4422bcd4
FR		 6206}
6207
bea3348e 6208static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6209{
bea3348e
SH		 6210 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6211 struct net_device *dev = tp->dev;
da78dbff
FR		 6212 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6213 int work_done= 0;
6214 u16 status;
6215
6216 status = rtl_get_events(tp);
6217 rtl_ack_events(tp, status & ~tp->event_slow);
6218
6219 if (status & RTL_EVENT_NAPI_RX)
6220 work_done = rtl_rx(dev, tp, (u32) budget);
6221
6222 if (status & RTL_EVENT_NAPI_TX)
6223 rtl_tx(dev, tp);
1da177e4 6224
da78dbff
FR		 6225 if (status & tp->event_slow) {
6226 enable_mask &= ~tp->event_slow;
6227
6228 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6229 }
1da177e4 6230
bea3348e 6231 if (work_done < budget) {
288379f0 6232 napi_complete(napi);
f11a377b 6233
da78dbff
FR		 6234 rtl_irq_enable(tp, enable_mask);
6235 mmiowb();
1da177e4
LT		 6236 }
6237
bea3348e 6238 return work_done;
1da177e4 6239}
1da177e4 6240
523a6094
FR		 6241static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6242{
6243 struct rtl8169_private *tp = netdev_priv(dev);
6244
6245 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6246 return;
6247
6248 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6249 RTL_W32(RxMissed, 0);
6250}
6251
1da177e4
LT		 6252static void rtl8169_down(struct net_device *dev)
6253{
6254 struct rtl8169_private *tp = netdev_priv(dev);
6255 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6256
4876cc1e 6257 del_timer_sync(&tp->timer);
1da177e4 6258
93dd79e8 6259 napi_disable(&tp->napi);
da78dbff 6260 netif_stop_queue(dev);
1da177e4 6261
92fc43b4 6262 rtl8169_hw_reset(tp);
323bb685
SG		 6263 /*
6264 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6265 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6266 * and napi is disabled (rtl8169_poll).
323bb685 6267 */
523a6094 6268 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6269
1da177e4 6270 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6271 synchronize_sched();
1da177e4 6272
1da177e4
LT		 6273 rtl8169_tx_clear(tp);
6274
6275 rtl8169_rx_clear(tp);
065c27c1 6276
6277 rtl_pll_power_down(tp);
1da177e4
LT		 6278}
6279
6280static int rtl8169_close(struct net_device *dev)
6281{
6282 struct rtl8169_private *tp = netdev_priv(dev);
6283 struct pci_dev *pdev = tp->pci_dev;
6284
e1759441
RW		 6285 pm_runtime_get_sync(&pdev->dev);
6286
cecb5fd7 6287 /* Update counters before going down */
355423d0
IV		 6288 rtl8169_update_counters(dev);
6289
da78dbff 6290 rtl_lock_work(tp);
6c4a70c5 6291 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6292
1da177e4 6293 rtl8169_down(dev);
da78dbff 6294 rtl_unlock_work(tp);
1da177e4 6295
92a7c4e7 6296 free_irq(pdev->irq, dev);
1da177e4 6297
82553bb6
SG		 6298 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6299 tp->RxPhyAddr);
6300 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6301 tp->TxPhyAddr);
1da177e4
LT		 6302 tp->TxDescArray = NULL;
6303 tp->RxDescArray = NULL;
6304
e1759441
RW		 6305 pm_runtime_put_sync(&pdev->dev);
6306
1da177e4
LT		 6307 return 0;
6308}
6309
dc1c00ce
FR		 6310#ifdef CONFIG_NET_POLL_CONTROLLER
6311static void rtl8169_netpoll(struct net_device *dev)
6312{
6313 struct rtl8169_private *tp = netdev_priv(dev);
6314
6315 rtl8169_interrupt(tp->pci_dev->irq, dev);
6316}
6317#endif
6318
df43ac78
FR		 6319static int rtl_open(struct net_device *dev)
6320{
6321 struct rtl8169_private *tp = netdev_priv(dev);
6322 void __iomem *ioaddr = tp->mmio_addr;
6323 struct pci_dev *pdev = tp->pci_dev;
6324 int retval = -ENOMEM;
6325
6326 pm_runtime_get_sync(&pdev->dev);
6327
6328 /*
e75d6606 6329 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6330 * dma_alloc_coherent provides more.
6331 */
6332 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6333 &tp->TxPhyAddr, GFP_KERNEL);
6334 if (!tp->TxDescArray)
6335 goto err_pm_runtime_put;
6336
6337 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6338 &tp->RxPhyAddr, GFP_KERNEL);
6339 if (!tp->RxDescArray)
6340 goto err_free_tx_0;
6341
6342 retval = rtl8169_init_ring(dev);
6343 if (retval < 0)
6344 goto err_free_rx_1;
6345
6346 INIT_WORK(&tp->wk.work, rtl_task);
6347
6348 smp_mb();
6349
6350 rtl_request_firmware(tp);
6351
92a7c4e7 6352 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6353 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6354 dev->name, dev);
6355 if (retval < 0)
6356 goto err_release_fw_2;
6357
6358 rtl_lock_work(tp);
6359
6360 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6361
6362 napi_enable(&tp->napi);
6363
6364 rtl8169_init_phy(dev, tp);
6365
6366 __rtl8169_set_features(dev, dev->features);
6367
6368 rtl_pll_power_up(tp);
6369
6370 rtl_hw_start(dev);
6371
6372 netif_start_queue(dev);
6373
6374 rtl_unlock_work(tp);
6375
6376 tp->saved_wolopts = 0;
6377 pm_runtime_put_noidle(&pdev->dev);
6378
6379 rtl8169_check_link_status(dev, tp, ioaddr);
6380out:
6381 return retval;
6382
6383err_release_fw_2:
6384 rtl_release_firmware(tp);
6385 rtl8169_rx_clear(tp);
6386err_free_rx_1:
6387 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6388 tp->RxPhyAddr);
6389 tp->RxDescArray = NULL;
6390err_free_tx_0:
6391 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6392 tp->TxPhyAddr);
6393 tp->TxDescArray = NULL;
6394err_pm_runtime_put:
6395 pm_runtime_put_noidle(&pdev->dev);
6396 goto out;
6397}
6398
8027aa24
JW		 6399static struct rtnl_link_stats64 *
6400rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6401{
6402 struct rtl8169_private *tp = netdev_priv(dev);
6403 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6404 unsigned int start;
1da177e4 6405
da78dbff 6406 if (netif_running(dev))
523a6094 6407 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6408
8027aa24
JW		 6409 do {
6410 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6411 stats->rx_packets = tp->rx_stats.packets;
6412 stats->rx_bytes = tp->rx_stats.bytes;
6413 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6414
6415
6416 do {
6417 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6418 stats->tx_packets = tp->tx_stats.packets;
6419 stats->tx_bytes = tp->tx_stats.bytes;
6420 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6421
6422 stats->rx_dropped = dev->stats.rx_dropped;
6423 stats->tx_dropped = dev->stats.tx_dropped;
6424 stats->rx_length_errors = dev->stats.rx_length_errors;
6425 stats->rx_errors = dev->stats.rx_errors;
6426 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6427 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6428 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6429
6430 return stats;
1da177e4
LT		 6431}
6432
861ab440 6433static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6434{
065c27c1 6435 struct rtl8169_private *tp = netdev_priv(dev);
6436
5d06a99f 6437 if (!netif_running(dev))
861ab440 6438 return;
5d06a99f
FR		 6439
6440 netif_device_detach(dev);
6441 netif_stop_queue(dev);
da78dbff
FR		 6442
6443 rtl_lock_work(tp);
6444 napi_disable(&tp->napi);
6c4a70c5 6445 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6446 rtl_unlock_work(tp);
6447
6448 rtl_pll_power_down(tp);
861ab440
RW		 6449}
6450
6451#ifdef CONFIG_PM
6452
6453static int rtl8169_suspend(struct device *device)
6454{
6455 struct pci_dev *pdev = to_pci_dev(device);
6456 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6457
861ab440 6458 rtl8169_net_suspend(dev);
1371fa6d 6459
5d06a99f
FR		 6460 return 0;
6461}
6462
e1759441
RW		 6463static void __rtl8169_resume(struct net_device *dev)
6464{
065c27c1 6465 struct rtl8169_private *tp = netdev_priv(dev);
6466
e1759441 6467 netif_device_attach(dev);
065c27c1 6468
6469 rtl_pll_power_up(tp);
6470
cff4c162
AS		 6471 rtl_lock_work(tp);
6472 napi_enable(&tp->napi);
6c4a70c5 6473 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6474 rtl_unlock_work(tp);
da78dbff 6475
98ddf986 6476 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6477}
6478
861ab440 6479static int rtl8169_resume(struct device *device)
5d06a99f 6480{
861ab440 6481 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6482 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6483 struct rtl8169_private *tp = netdev_priv(dev);
6484
6485 rtl8169_init_phy(dev, tp);
5d06a99f 6486
e1759441
RW		 6487 if (netif_running(dev))
6488 __rtl8169_resume(dev);
5d06a99f 6489
e1759441
RW		 6490 return 0;
6491}
6492
6493static int rtl8169_runtime_suspend(struct device *device)
6494{
6495 struct pci_dev *pdev = to_pci_dev(device);
6496 struct net_device *dev = pci_get_drvdata(pdev);
6497 struct rtl8169_private *tp = netdev_priv(dev);
6498
6499 if (!tp->TxDescArray)
6500 return 0;
6501
da78dbff 6502 rtl_lock_work(tp);
e1759441
RW		 6503 tp->saved_wolopts = __rtl8169_get_wol(tp);
6504 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6505 rtl_unlock_work(tp);
e1759441
RW		 6506
6507 rtl8169_net_suspend(dev);
6508
6509 return 0;
6510}
6511
6512static int rtl8169_runtime_resume(struct device *device)
6513{
6514 struct pci_dev *pdev = to_pci_dev(device);
6515 struct net_device *dev = pci_get_drvdata(pdev);
6516 struct rtl8169_private *tp = netdev_priv(dev);
6517
6518 if (!tp->TxDescArray)
6519 return 0;
6520
da78dbff 6521 rtl_lock_work(tp);
e1759441
RW		 6522 __rtl8169_set_wol(tp, tp->saved_wolopts);
6523 tp->saved_wolopts = 0;
da78dbff 6524 rtl_unlock_work(tp);
e1759441 6525
fccec10b
SG		 6526 rtl8169_init_phy(dev, tp);
6527
e1759441 6528 __rtl8169_resume(dev);
5d06a99f 6529
5d06a99f
FR		 6530 return 0;
6531}
6532
e1759441
RW		 6533static int rtl8169_runtime_idle(struct device *device)
6534{
6535 struct pci_dev *pdev = to_pci_dev(device);
6536 struct net_device *dev = pci_get_drvdata(pdev);
6537 struct rtl8169_private *tp = netdev_priv(dev);
6538
e4fbce74 6539 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6540}
6541
47145210 6542static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6543 .suspend = rtl8169_suspend,
6544 .resume = rtl8169_resume,
6545 .freeze = rtl8169_suspend,
6546 .thaw = rtl8169_resume,
6547 .poweroff = rtl8169_suspend,
6548 .restore = rtl8169_resume,
6549 .runtime_suspend = rtl8169_runtime_suspend,
6550 .runtime_resume = rtl8169_runtime_resume,
6551 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6552};
6553
6554#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6555
6556#else /* !CONFIG_PM */
6557
6558#define RTL8169_PM_OPS NULL
6559
6560#endif /* !CONFIG_PM */
6561
649b3b8c 6562static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6563{
6564 void __iomem *ioaddr = tp->mmio_addr;
6565
6566 /* WoL fails with 8168b when the receiver is disabled. */
6567 switch (tp->mac_version) {
6568 case RTL_GIGA_MAC_VER_11:
6569 case RTL_GIGA_MAC_VER_12:
6570 case RTL_GIGA_MAC_VER_17:
6571 pci_clear_master(tp->pci_dev);
6572
6573 RTL_W8(ChipCmd, CmdRxEnb);
6574 /* PCI commit */
6575 RTL_R8(ChipCmd);
6576 break;
6577 default:
6578 break;
6579 }
6580}
6581
1765f95d
FR		 6582static void rtl_shutdown(struct pci_dev *pdev)
6583{
861ab440 6584 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6585 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6586 struct device *d = &pdev->dev;
6587
6588 pm_runtime_get_sync(d);
861ab440
RW		 6589
6590 rtl8169_net_suspend(dev);
1765f95d 6591
cecb5fd7 6592 /* Restore original MAC address */
cc098dc7
IV		 6593 rtl_rar_set(tp, dev->perm_addr);
6594
92fc43b4 6595 rtl8169_hw_reset(tp);
4bb3f522 6596
861ab440 6597 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6598 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6599 rtl_wol_suspend_quirk(tp);
6600 rtl_wol_shutdown_quirk(tp);
ca52efd5 6601 }
6602
861ab440
RW		 6603 pci_wake_from_d3(pdev, true);
6604 pci_set_power_state(pdev, PCI_D3hot);
6605 }
2a15cd2f 6606
6607 pm_runtime_put_noidle(d);
861ab440 6608}
5d06a99f 6609
baf63293 6610static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6611{
6612 struct net_device *dev = pci_get_drvdata(pdev);
6613 struct rtl8169_private *tp = netdev_priv(dev);
6614
6615 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6616 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6617 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6618 rtl8168_driver_stop(tp);
6619 }
6620
6621 cancel_work_sync(&tp->wk.work);
6622
ad1be8d3
DN		 6623 netif_napi_del(&tp->napi);
6624
e27566ed
FR		 6625 unregister_netdev(dev);
6626
6627 rtl_release_firmware(tp);
6628
6629 if (pci_dev_run_wake(pdev))
6630 pm_runtime_get_noresume(&pdev->dev);
6631
6632 /* restore original MAC address */
6633 rtl_rar_set(tp, dev->perm_addr);
6634
6635 rtl_disable_msi(pdev, tp);
6636 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6637 pci_set_drvdata(pdev, NULL);
6638}
6639
fa9c385e 6640static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6641 .ndo_open = rtl_open,
fa9c385e
FR		 6642 .ndo_stop = rtl8169_close,
6643 .ndo_get_stats64 = rtl8169_get_stats64,
6644 .ndo_start_xmit = rtl8169_start_xmit,
6645 .ndo_tx_timeout = rtl8169_tx_timeout,
6646 .ndo_validate_addr = eth_validate_addr,
6647 .ndo_change_mtu = rtl8169_change_mtu,
6648 .ndo_fix_features = rtl8169_fix_features,
6649 .ndo_set_features = rtl8169_set_features,
6650 .ndo_set_mac_address = rtl_set_mac_address,
6651 .ndo_do_ioctl = rtl8169_ioctl,
6652 .ndo_set_rx_mode = rtl_set_rx_mode,
6653#ifdef CONFIG_NET_POLL_CONTROLLER
6654 .ndo_poll_controller = rtl8169_netpoll,
6655#endif
6656
6657};
6658
31fa8b18
FR		 6659static const struct rtl_cfg_info {
6660 void (*hw_start)(struct net_device *);
6661 unsigned int region;
6662 unsigned int align;
6663 u16 event_slow;
6664 unsigned features;
6665 u8 default_ver;
6666} rtl_cfg_infos [] = {
6667 [RTL_CFG_0] = {
6668 .hw_start = rtl_hw_start_8169,
6669 .region = 1,
6670 .align = 0,
6671 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6672 .features = RTL_FEATURE_GMII,
6673 .default_ver = RTL_GIGA_MAC_VER_01,
6674 },
6675 [RTL_CFG_1] = {
6676 .hw_start = rtl_hw_start_8168,
6677 .region = 2,
6678 .align = 8,
6679 .event_slow = SYSErr | LinkChg | RxOverflow,
6680 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6681 .default_ver = RTL_GIGA_MAC_VER_11,
6682 },
6683 [RTL_CFG_2] = {
6684 .hw_start = rtl_hw_start_8101,
6685 .region = 2,
6686 .align = 8,
6687 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6688 PCSTimeout,
6689 .features = RTL_FEATURE_MSI,
6690 .default_ver = RTL_GIGA_MAC_VER_13,
6691 }
6692};
6693
6694/* Cfg9346_Unlock assumed. */
6695static unsigned rtl_try_msi(struct rtl8169_private *tp,
6696 const struct rtl_cfg_info *cfg)
6697{
6698 void __iomem *ioaddr = tp->mmio_addr;
6699 unsigned msi = 0;
6700 u8 cfg2;
6701
6702 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6703 if (cfg->features & RTL_FEATURE_MSI) {
6704 if (pci_enable_msi(tp->pci_dev)) {
6705 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6706 } else {
6707 cfg2 |= MSIEnable;
6708 msi = RTL_FEATURE_MSI;
6709 }
6710 }
6711 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6712 RTL_W8(Config2, cfg2);
6713 return msi;
6714}
6715
c558386b
HW		 6716DECLARE_RTL_COND(rtl_link_list_ready_cond)
6717{
6718 void __iomem *ioaddr = tp->mmio_addr;
6719
6720 return RTL_R8(MCU) & LINK_LIST_RDY;
6721}
6722
6723DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6724{
6725 void __iomem *ioaddr = tp->mmio_addr;
6726
6727 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6728}
6729
baf63293 6730static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 6731{
6732 void __iomem *ioaddr = tp->mmio_addr;
6733 u32 data;
6734
6735 tp->ocp_base = OCP_STD_PHY_BASE;
6736
6737 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6738
6739 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6740 return;
6741
6742 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6743 return;
6744
6745 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6746 msleep(1);
6747 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6748
5f8bcce9 6749 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6750 data &= ~(1 << 14);
6751 r8168_mac_ocp_write(tp, 0xe8de, data);
6752
6753 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6754 return;
6755
5f8bcce9 6756 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6757 data |= (1 << 15);
6758 r8168_mac_ocp_write(tp, 0xe8de, data);
6759
6760 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6761 return;
6762}
6763
baf63293 6764static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 6765{
6766 switch (tp->mac_version) {
6767 case RTL_GIGA_MAC_VER_40:
6768 case RTL_GIGA_MAC_VER_41:
6769 rtl_hw_init_8168g(tp);
6770 break;
6771
6772 default:
6773 break;
6774 }
6775}
6776
baf63293 6777static int
3b6cf25d
FR		 6778rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6779{
6780 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6781 const unsigned int region = cfg->region;
6782 struct rtl8169_private *tp;
6783 struct mii_if_info *mii;
6784 struct net_device *dev;
6785 void __iomem *ioaddr;
6786 int chipset, i;
6787 int rc;
6788
6789 if (netif_msg_drv(&debug)) {
6790 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6791 MODULENAME, RTL8169_VERSION);
6792 }
6793
6794 dev = alloc_etherdev(sizeof (*tp));
6795 if (!dev) {
6796 rc = -ENOMEM;
6797 goto out;
6798 }
6799
6800 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6801 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6802 tp = netdev_priv(dev);
6803 tp->dev = dev;
6804 tp->pci_dev = pdev;
6805 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6806
6807 mii = &tp->mii;
6808 mii->dev = dev;
6809 mii->mdio_read = rtl_mdio_read;
6810 mii->mdio_write = rtl_mdio_write;
6811 mii->phy_id_mask = 0x1f;
6812 mii->reg_num_mask = 0x1f;
6813 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6814
6815 /* disable ASPM completely as that cause random device stop working
6816 * problems as well as full system hangs for some PCIe devices users */
6817 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6818 PCIE_LINK_STATE_CLKPM);
6819
6820 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6821 rc = pci_enable_device(pdev);
6822 if (rc < 0) {
6823 netif_err(tp, probe, dev, "enable failure\n");
6824 goto err_out_free_dev_1;
6825 }
6826
6827 if (pci_set_mwi(pdev) < 0)
6828 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6829
6830 /* make sure PCI base addr 1 is MMIO */
6831 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6832 netif_err(tp, probe, dev,
6833 "region #%d not an MMIO resource, aborting\n",
6834 region);
6835 rc = -ENODEV;
6836 goto err_out_mwi_2;
6837 }
6838
6839 /* check for weird/broken PCI region reporting */
6840 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6841 netif_err(tp, probe, dev,
6842 "Invalid PCI region size(s), aborting\n");
6843 rc = -ENODEV;
6844 goto err_out_mwi_2;
6845 }
6846
6847 rc = pci_request_regions(pdev, MODULENAME);
6848 if (rc < 0) {
6849 netif_err(tp, probe, dev, "could not request regions\n");
6850 goto err_out_mwi_2;
6851 }
6852
6853 tp->cp_cmd = RxChkSum;
6854
6855 if ((sizeof(dma_addr_t) > 4) &&
6856 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6857 tp->cp_cmd |= PCIDAC;
6858 dev->features |= NETIF_F_HIGHDMA;
6859 } else {
6860 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6861 if (rc < 0) {
6862 netif_err(tp, probe, dev, "DMA configuration failed\n");
6863 goto err_out_free_res_3;
6864 }
6865 }
6866
6867 /* ioremap MMIO region */
6868 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6869 if (!ioaddr) {
6870 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6871 rc = -EIO;
6872 goto err_out_free_res_3;
6873 }
6874 tp->mmio_addr = ioaddr;
6875
6876 if (!pci_is_pcie(pdev))
6877 netif_info(tp, probe, dev, "not PCI Express\n");
6878
6879 /* Identify chip attached to board */
6880 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6881
6882 rtl_init_rxcfg(tp);
6883
6884 rtl_irq_disable(tp);
6885
c558386b
HW		 6886 rtl_hw_initialize(tp);
6887
3b6cf25d
FR		 6888 rtl_hw_reset(tp);
6889
6890 rtl_ack_events(tp, 0xffff);
6891
6892 pci_set_master(pdev);
6893
6894 /*
6895 * Pretend we are using VLANs; This bypasses a nasty bug where
6896 * Interrupts stop flowing on high load on 8110SCd controllers.
6897 */
6898 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6899 tp->cp_cmd |= RxVlan;
6900
6901 rtl_init_mdio_ops(tp);
6902 rtl_init_pll_power_ops(tp);
6903 rtl_init_jumbo_ops(tp);
beb1fe18 6904 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6905
6906 rtl8169_print_mac_version(tp);
6907
6908 chipset = tp->mac_version;
6909 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6910
6911 RTL_W8(Cfg9346, Cfg9346_Unlock);
6912 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6913 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6914 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6915 tp->features |= RTL_FEATURE_WOL;
6916 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6917 tp->features |= RTL_FEATURE_WOL;
6918 tp->features |= rtl_try_msi(tp, cfg);
6919 RTL_W8(Cfg9346, Cfg9346_Lock);
6920
6921 if (rtl_tbi_enabled(tp)) {
6922 tp->set_speed = rtl8169_set_speed_tbi;
6923 tp->get_settings = rtl8169_gset_tbi;
6924 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6925 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6926 tp->link_ok = rtl8169_tbi_link_ok;
6927 tp->do_ioctl = rtl_tbi_ioctl;
6928 } else {
6929 tp->set_speed = rtl8169_set_speed_xmii;
6930 tp->get_settings = rtl8169_gset_xmii;
6931 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6932 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6933 tp->link_ok = rtl8169_xmii_link_ok;
6934 tp->do_ioctl = rtl_xmii_ioctl;
6935 }
6936
6937 mutex_init(&tp->wk.mutex);
6938
6939 /* Get MAC address */
6940 for (i = 0; i < ETH_ALEN; i++)
6941 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6942 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6943
6944 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6945 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6946
6947 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6948
6949 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6950 * properly for all devices */
6951 dev->features |= NETIF_F_RXCSUM |
6952 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6953
6954 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6955 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6956 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6957 NETIF_F_HIGHDMA;
6958
6959 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6960 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6961 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6962
6963 dev->hw_features |= NETIF_F_RXALL;
6964 dev->hw_features |= NETIF_F_RXFCS;
6965
6966 tp->hw_start = cfg->hw_start;
6967 tp->event_slow = cfg->event_slow;
6968
6969 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6970 ~(RxBOVF | RxFOVF) : ~0;
6971
6972 init_timer(&tp->timer);
6973 tp->timer.data = (unsigned long) dev;
6974 tp->timer.function = rtl8169_phy_timer;
6975
6976 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6977
6978 rc = register_netdev(dev);
6979 if (rc < 0)
6980 goto err_out_msi_4;
6981
6982 pci_set_drvdata(pdev, dev);
6983
92a7c4e7
FR		 6984 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6985 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6986 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6987 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6988 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6989 "tx checksumming: %s]\n",
6990 rtl_chip_infos[chipset].jumbo_max,
6991 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6992 }
6993
6994 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6995 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6996 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6997 rtl8168_driver_start(tp);
6998 }
6999
7000 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7001
7002 if (pci_dev_run_wake(pdev))
7003 pm_runtime_put_noidle(&pdev->dev);
7004
7005 netif_carrier_off(dev);
7006
7007out:
7008 return rc;
7009
7010err_out_msi_4:
ad1be8d3 7011 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7012 rtl_disable_msi(pdev, tp);
7013 iounmap(ioaddr);
7014err_out_free_res_3:
7015 pci_release_regions(pdev);
7016err_out_mwi_2:
7017 pci_clear_mwi(pdev);
7018 pci_disable_device(pdev);
7019err_out_free_dev_1:
7020 free_netdev(dev);
7021 goto out;
7022}
7023
1da177e4
LT		 7024static struct pci_driver rtl8169_pci_driver = {
7025 .name = MODULENAME,
7026 .id_table = rtl8169_pci_tbl,
3b6cf25d 7027 .probe = rtl_init_one,
baf63293 7028 .remove = rtl_remove_one,
1765f95d 7029 .shutdown = rtl_shutdown,
861ab440 7030 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7031};
7032
3eeb7da9 7033module_pci_driver(rtl8169_pci_driver);
Linux kernel - Deliverables
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