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Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/bwh/sfc...
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 48
1da177e4
LT		 49#ifdef RTL8169_DEBUG
50#define assert(expr) \
5b0384f4
FR		 51 if (!(expr)) { \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 53 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 54 }
06fa7358
JP		 55#define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 57#else
58#define assert(expr) do {} while (0)
59#define dprintk(fmt, args...) do {} while (0)
60#endif /* RTL8169_DEBUG */
61
b57b7e5a 62#define R8169_MSG_DEFAULT \
f0e837d9 63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 64
1da177e4
LT		 65#define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
67
1da177e4
LT		 68/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 70static const int multicast_filter_limit = 32;
1da177e4 71
9c14ceaf 72#define MAX_READ_REQUEST_SHIFT 12
1da177e4 73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 74#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
ea8dbdd1 88#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 90#define RTL_EEPROM_SIG_ADDR 0x0000
91
1da177e4
LT		 92/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 98#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 99
100enum mac_version {
85bffe6c
FR		 101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_33,
70090424 134 RTL_GIGA_MAC_VER_34,
c2218925
HW		 135 RTL_GIGA_MAC_VER_35,
136 RTL_GIGA_MAC_VER_36,
85bffe6c 137 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 138};
139
2b7b4318
FR		 140enum rtl_tx_desc_version {
141 RTL_TD_0 = 0,
142 RTL_TD_1 = 1,
143};
144
d58d46b5
FR		 145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
151#define _R(NAME,TD,FW,SZ,B) { \
152 .name = NAME, \
153 .txd_version = TD, \
154 .fw_name = FW, \
155 .jumbo_max = SZ, \
156 .jumbo_tx_csum = B \
157}
1da177e4 158
3c6bee1d 159static const struct {
1da177e4 160 const char *name;
2b7b4318 161 enum rtl_tx_desc_version txd_version;
953a12cc 162 const char *fw_name;
d58d46b5
FR		 163 u16 jumbo_max;
164 bool jumbo_tx_csum;
85bffe6c
FR		 165} rtl_chip_infos[] = {
166 /* PCI devices. */
167 [RTL_GIGA_MAC_VER_01] =
d58d46b5 168 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 169 [RTL_GIGA_MAC_VER_02] =
d58d46b5 170 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 171 [RTL_GIGA_MAC_VER_03] =
d58d46b5 172 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 173 [RTL_GIGA_MAC_VER_04] =
d58d46b5 174 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_05] =
d58d46b5 176 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_06] =
d58d46b5 178 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 179 /* PCI-E devices. */
180 [RTL_GIGA_MAC_VER_07] =
d58d46b5 181 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 182 [RTL_GIGA_MAC_VER_08] =
d58d46b5 183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 184 [RTL_GIGA_MAC_VER_09] =
d58d46b5 185 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 186 [RTL_GIGA_MAC_VER_10] =
d58d46b5 187 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_11] =
d58d46b5 189 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 190 [RTL_GIGA_MAC_VER_12] =
d58d46b5 191 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 192 [RTL_GIGA_MAC_VER_13] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_14] =
d58d46b5 195 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_15] =
d58d46b5 197 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_16] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_17] =
d58d46b5 201 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 202 [RTL_GIGA_MAC_VER_18] =
d58d46b5 203 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 204 [RTL_GIGA_MAC_VER_19] =
d58d46b5 205 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 206 [RTL_GIGA_MAC_VER_20] =
d58d46b5 207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_21] =
d58d46b5 209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_22] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_23] =
d58d46b5 213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_24] =
d58d46b5 215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 217 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
218 JUMBO_9K, false),
85bffe6c 219 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
221 JUMBO_9K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_27] =
d58d46b5 223 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 224 [RTL_GIGA_MAC_VER_28] =
d58d46b5 225 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 227 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
228 JUMBO_1K, true),
85bffe6c 229 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
231 JUMBO_1K, true),
85bffe6c 232 [RTL_GIGA_MAC_VER_31] =
d58d46b5 233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 235 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
236 JUMBO_9K, false),
85bffe6c 237 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
239 JUMBO_9K, false),
70090424 240 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 241 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
242 JUMBO_9K, false),
c2218925 243 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 244 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
245 JUMBO_9K, false),
c2218925 246 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
248 JUMBO_9K, false),
953a12cc 249};
85bffe6c 250#undef _R
953a12cc 251
bcf0bf90
FR		 252enum cfg_version {
253 RTL_CFG_0 = 0x00,
254 RTL_CFG_1,
255 RTL_CFG_2
256};
257
07ce4064
FR		 258static void rtl_hw_start_8169(struct net_device *);
259static void rtl_hw_start_8168(struct net_device *);
260static void rtl_hw_start_8101(struct net_device *);
261
a3aa1884 262static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 270 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
272 { PCI_VENDOR_ID_LINKSYS, 0x1032,
273 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 274 { 0x0001, 0x8168,
275 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 276 {0,},
277};
278
279MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
280
6f0333b8 281static int rx_buf_sz = 16383;
4300e8c7 282static int use_dac;
b57b7e5a
SH		 283static struct {
284 u32 msg_enable;
285} debug = { -1 };
1da177e4 286
07d3f51f
FR		 287enum rtl_registers {
288 MAC0 = 0, /* Ethernet hardware address. */
773d2021 289 MAC4 = 4,
07d3f51f
FR		 290 MAR0 = 8, /* Multicast filter. */
291 CounterAddrLow = 0x10,
292 CounterAddrHigh = 0x14,
293 TxDescStartAddrLow = 0x20,
294 TxDescStartAddrHigh = 0x24,
295 TxHDescStartAddrLow = 0x28,
296 TxHDescStartAddrHigh = 0x2c,
297 FLASH = 0x30,
298 ERSR = 0x36,
299 ChipCmd = 0x37,
300 TxPoll = 0x38,
301 IntrMask = 0x3c,
302 IntrStatus = 0x3e,
4f6b00e5 303
07d3f51f 304 TxConfig = 0x40,
4f6b00e5
HW		 305#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
306#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 307
4f6b00e5
HW		 308 RxConfig = 0x44,
309#define RX128_INT_EN (1 << 15) /* 8111c and later */
310#define RX_MULTI_EN (1 << 14) /* 8111c only */
311#define RXCFG_FIFO_SHIFT 13
312 /* No threshold before first PCI xfer */
313#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
314#define RXCFG_DMA_SHIFT 8
315 /* Unlimited maximum PCI burst. */
316#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 317
07d3f51f
FR		 318 RxMissed = 0x4c,
319 Cfg9346 = 0x50,
320 Config0 = 0x51,
321 Config1 = 0x52,
322 Config2 = 0x53,
323 Config3 = 0x54,
324 Config4 = 0x55,
325 Config5 = 0x56,
326 MultiIntr = 0x5c,
327 PHYAR = 0x60,
07d3f51f
FR		 328 PHYstatus = 0x6c,
329 RxMaxSize = 0xda,
330 CPlusCmd = 0xe0,
331 IntrMitigate = 0xe2,
332 RxDescAddrLow = 0xe4,
333 RxDescAddrHigh = 0xe8,
f0298f81 334 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
335
336#define NoEarlyTx 0x3f /* Max value : no early transmit. */
337
338 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
339
340#define TxPacketMax (8064 >> 7)
3090bd9a 341#define EarlySize 0x27
f0298f81 342
07d3f51f
FR		 343 FuncEvent = 0xf0,
344 FuncEventMask = 0xf4,
345 FuncPresetState = 0xf8,
346 FuncForceEvent = 0xfc,
1da177e4
LT		 347};
348
f162a5d1
FR		 349enum rtl8110_registers {
350 TBICSR = 0x64,
351 TBI_ANAR = 0x68,
352 TBI_LPAR = 0x6a,
353};
354
355enum rtl8168_8101_registers {
356 CSIDR = 0x64,
357 CSIAR = 0x68,
358#define CSIAR_FLAG 0x80000000
359#define CSIAR_WRITE_CMD 0x80000000
360#define CSIAR_BYTE_ENABLE 0x0f
361#define CSIAR_BYTE_ENABLE_SHIFT 12
362#define CSIAR_ADDR_MASK 0x0fff
065c27c1 363 PMCH = 0x6f,
f162a5d1
FR		 364 EPHYAR = 0x80,
365#define EPHYAR_FLAG 0x80000000
366#define EPHYAR_WRITE_CMD 0x80000000
367#define EPHYAR_REG_MASK 0x1f
368#define EPHYAR_REG_SHIFT 16
369#define EPHYAR_DATA_MASK 0xffff
5a5e4443 370 DLLPR = 0xd0,
4f6b00e5 371#define PFM_EN (1 << 6)
f162a5d1
FR		 372 DBG_REG = 0xd1,
373#define FIX_NAK_1 (1 << 4)
374#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 375 TWSI = 0xd2,
376 MCU = 0xd3,
4f6b00e5 377#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 378#define EN_NDP (1 << 3)
379#define EN_OOB_RESET (1 << 2)
daf9df6d 380 EFUSEAR = 0xdc,
381#define EFUSEAR_FLAG 0x80000000
382#define EFUSEAR_WRITE_CMD 0x80000000
383#define EFUSEAR_READ_CMD 0x00000000
384#define EFUSEAR_REG_MASK 0x03ff
385#define EFUSEAR_REG_SHIFT 8
386#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 387};
388
c0e45c1c 389enum rtl8168_registers {
4f6b00e5
HW		 390 LED_FREQ = 0x1a,
391 EEE_LED = 0x1b,
b646d900 392 ERIDR = 0x70,
393 ERIAR = 0x74,
394#define ERIAR_FLAG 0x80000000
395#define ERIAR_WRITE_CMD 0x80000000
396#define ERIAR_READ_CMD 0x00000000
397#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 398#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 399#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
400#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
401#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
402#define ERIAR_MASK_SHIFT 12
403#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
404#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
405#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 406 EPHY_RXER_NUM = 0x7c,
407 OCPDR = 0xb0, /* OCP GPHY access */
408#define OCPDR_WRITE_CMD 0x80000000
409#define OCPDR_READ_CMD 0x00000000
410#define OCPDR_REG_MASK 0x7f
411#define OCPDR_GPHY_REG_SHIFT 16
412#define OCPDR_DATA_MASK 0xffff
413 OCPAR = 0xb4,
414#define OCPAR_FLAG 0x80000000
415#define OCPAR_GPHY_WRITE_CMD 0x8000f060
416#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 417 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
418 MISC = 0xf0, /* 8168e only. */
cecb5fd7 419#define TXPLA_RST (1 << 29)
4f6b00e5 420#define PWM_EN (1 << 22)
c0e45c1c 421};
422
07d3f51f 423enum rtl_register_content {
1da177e4 424 /* InterruptStatusBits */
07d3f51f
FR		 425 SYSErr = 0x8000,
426 PCSTimeout = 0x4000,
427 SWInt = 0x0100,
428 TxDescUnavail = 0x0080,
429 RxFIFOOver = 0x0040,
430 LinkChg = 0x0020,
431 RxOverflow = 0x0010,
432 TxErr = 0x0008,
433 TxOK = 0x0004,
434 RxErr = 0x0002,
435 RxOK = 0x0001,
1da177e4
LT		 436
437 /* RxStatusDesc */
e03f33af 438 RxBOVF = (1 << 24),
9dccf611
FR		 439 RxFOVF = (1 << 23),
440 RxRWT = (1 << 22),
441 RxRES = (1 << 21),
442 RxRUNT = (1 << 20),
443 RxCRC = (1 << 19),
1da177e4
LT		 444
445 /* ChipCmdBits */
4f6b00e5 446 StopReq = 0x80,
07d3f51f
FR		 447 CmdReset = 0x10,
448 CmdRxEnb = 0x08,
449 CmdTxEnb = 0x04,
450 RxBufEmpty = 0x01,
1da177e4 451
275391a4
FR		 452 /* TXPoll register p.5 */
453 HPQ = 0x80, /* Poll cmd on the high prio queue */
454 NPQ = 0x40, /* Poll cmd on the low prio queue */
455 FSWInt = 0x01, /* Forced software interrupt */
456
1da177e4 457 /* Cfg9346Bits */
07d3f51f
FR		 458 Cfg9346_Lock = 0x00,
459 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 460
461 /* rx_mode_bits */
07d3f51f
FR		 462 AcceptErr = 0x20,
463 AcceptRunt = 0x10,
464 AcceptBroadcast = 0x08,
465 AcceptMulticast = 0x04,
466 AcceptMyPhys = 0x02,
467 AcceptAllPhys = 0x01,
1687b566 468#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 469
1da177e4
LT		 470 /* TxConfigBits */
471 TxInterFrameGapShift = 24,
472 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
473
5d06a99f 474 /* Config1 register p.24 */
f162a5d1
FR		 475 LEDS1 = (1 << 7),
476 LEDS0 = (1 << 6),
f162a5d1
FR		 477 Speed_down = (1 << 4),
478 MEMMAP = (1 << 3),
479 IOMAP = (1 << 2),
480 VPD = (1 << 1),
5d06a99f
FR		 481 PMEnable = (1 << 0), /* Power Management Enable */
482
6dccd16b 483 /* Config2 register p. 25 */
2ca6cf06 484 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 485 PCI_Clock_66MHz = 0x01,
486 PCI_Clock_33MHz = 0x00,
487
61a4dcc2
FR		 488 /* Config3 register p.25 */
489 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
490 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 491 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 492 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 493
d58d46b5
FR		 494 /* Config4 register */
495 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
496
5d06a99f 497 /* Config5 register p.27 */
61a4dcc2
FR		 498 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
499 MWF = (1 << 5), /* Accept Multicast wakeup frame */
500 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 501 Spi_en = (1 << 3),
61a4dcc2 502 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 503 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
504
1da177e4
LT		 505 /* TBICSR p.28 */
506 TBIReset = 0x80000000,
507 TBILoopback = 0x40000000,
508 TBINwEnable = 0x20000000,
509 TBINwRestart = 0x10000000,
510 TBILinkOk = 0x02000000,
511 TBINwComplete = 0x01000000,
512
513 /* CPlusCmd p.31 */
f162a5d1
FR		 514 EnableBist = (1 << 15), // 8168 8101
515 Mac_dbgo_oe = (1 << 14), // 8168 8101
516 Normal_mode = (1 << 13), // unused
517 Force_half_dup = (1 << 12), // 8168 8101
518 Force_rxflow_en = (1 << 11), // 8168 8101
519 Force_txflow_en = (1 << 10), // 8168 8101
520 Cxpl_dbg_sel = (1 << 9), // 8168 8101
521 ASF = (1 << 8), // 8168 8101
522 PktCntrDisable = (1 << 7), // 8168 8101
523 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 524 RxVlan = (1 << 6),
525 RxChkSum = (1 << 5),
526 PCIDAC = (1 << 4),
527 PCIMulRW = (1 << 3),
0e485150
FR		 528 INTT_0 = 0x0000, // 8168
529 INTT_1 = 0x0001, // 8168
530 INTT_2 = 0x0002, // 8168
531 INTT_3 = 0x0003, // 8168
1da177e4
LT		 532
533 /* rtl8169_PHYstatus */
07d3f51f
FR		 534 TBI_Enable = 0x80,
535 TxFlowCtrl = 0x40,
536 RxFlowCtrl = 0x20,
537 _1000bpsF = 0x10,
538 _100bps = 0x08,
539 _10bps = 0x04,
540 LinkStatus = 0x02,
541 FullDup = 0x01,
1da177e4 542
1da177e4 543 /* _TBICSRBit */
07d3f51f 544 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 545
546 /* DumpCounterCommand */
07d3f51f 547 CounterDump = 0x8,
1da177e4
LT		 548};
549
2b7b4318
FR		 550enum rtl_desc_bit {
551 /* First doubleword. */
1da177e4
LT		 552 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
553 RingEnd = (1 << 30), /* End of descriptor ring */
554 FirstFrag = (1 << 29), /* First segment of a packet */
555 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 556};
557
558/* Generic case. */
559enum rtl_tx_desc_bit {
560 /* First doubleword. */
561 TD_LSO = (1 << 27), /* Large Send Offload */
562#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 563
2b7b4318
FR		 564 /* Second doubleword. */
565 TxVlanTag = (1 << 17), /* Add VLAN tag */
566};
567
568/* 8169, 8168b and 810x except 8102e. */
569enum rtl_tx_desc_bit_0 {
570 /* First doubleword. */
571#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
572 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
573 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
574 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
575};
576
577/* 8102e, 8168c and beyond. */
578enum rtl_tx_desc_bit_1 {
579 /* Second doubleword. */
580#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
581 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
582 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
583 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
584};
1da177e4 585
2b7b4318
FR		 586static const struct rtl_tx_desc_info {
587 struct {
588 u32 udp;
589 u32 tcp;
590 } checksum;
591 u16 mss_shift;
592 u16 opts_offset;
593} tx_desc_info [] = {
594 [RTL_TD_0] = {
595 .checksum = {
596 .udp = TD0_IP_CS | TD0_UDP_CS,
597 .tcp = TD0_IP_CS | TD0_TCP_CS
598 },
599 .mss_shift = TD0_MSS_SHIFT,
600 .opts_offset = 0
601 },
602 [RTL_TD_1] = {
603 .checksum = {
604 .udp = TD1_IP_CS | TD1_UDP_CS,
605 .tcp = TD1_IP_CS | TD1_TCP_CS
606 },
607 .mss_shift = TD1_MSS_SHIFT,
608 .opts_offset = 1
609 }
610};
611
612enum rtl_rx_desc_bit {
1da177e4
LT		 613 /* Rx private */
614 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
615 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
616
617#define RxProtoUDP (PID1)
618#define RxProtoTCP (PID0)
619#define RxProtoIP (PID1 | PID0)
620#define RxProtoMask RxProtoIP
621
622 IPFail = (1 << 16), /* IP checksum failed */
623 UDPFail = (1 << 15), /* UDP/IP checksum failed */
624 TCPFail = (1 << 14), /* TCP/IP checksum failed */
625 RxVlanTag = (1 << 16), /* VLAN tag available */
626};
627
628#define RsvdMask 0x3fffc000
629
630struct TxDesc {
6cccd6e7
REB		 631 __le32 opts1;
632 __le32 opts2;
633 __le64 addr;
1da177e4
LT		 634};
635
636struct RxDesc {
6cccd6e7
REB		 637 __le32 opts1;
638 __le32 opts2;
639 __le64 addr;
1da177e4
LT		 640};
641
642struct ring_info {
643 struct sk_buff *skb;
644 u32 len;
645 u8 __pad[sizeof(void *) - sizeof(u32)];
646};
647
f23e7fda 648enum features {
ccdffb9a
FR		 649 RTL_FEATURE_WOL = (1 << 0),
650 RTL_FEATURE_MSI = (1 << 1),
651 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 652};
653
355423d0
IV		 654struct rtl8169_counters {
655 __le64 tx_packets;
656 __le64 rx_packets;
657 __le64 tx_errors;
658 __le32 rx_errors;
659 __le16 rx_missed;
660 __le16 align_errors;
661 __le32 tx_one_collision;
662 __le32 tx_multi_collision;
663 __le64 rx_unicast;
664 __le64 rx_broadcast;
665 __le32 rx_multicast;
666 __le16 tx_aborted;
667 __le16 tx_underun;
668};
669
da78dbff
FR		 670enum rtl_flag {
671 RTL_FLAG_TASK_SLOW_PENDING,
672 RTL_FLAG_TASK_RESET_PENDING,
673 RTL_FLAG_TASK_PHY_PENDING,
674 RTL_FLAG_MAX
675};
676
1da177e4
LT		 677struct rtl8169_private {
678 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 679 struct pci_dev *pci_dev;
c4028958 680 struct net_device *dev;
bea3348e 681 struct napi_struct napi;
cecb5fd7 682 spinlock_t lock;
b57b7e5a 683 u32 msg_enable;
2b7b4318
FR		 684 u16 txd_version;
685 u16 mac_version;
1da177e4
LT		 686 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
687 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
688 u32 dirty_rx;
689 u32 dirty_tx;
690 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
691 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
692 dma_addr_t TxPhyAddr;
693 dma_addr_t RxPhyAddr;
6f0333b8 694 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 695 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 696 struct timer_list timer;
697 u16 cp_cmd;
da78dbff
FR		 698
699 u16 event_slow;
c0e45c1c 700
701 struct mdio_ops {
702 void (*write)(void __iomem *, int, int);
703 int (*read)(void __iomem *, int);
704 } mdio_ops;
705
065c27c1 706 struct pll_power_ops {
707 void (*down)(struct rtl8169_private *);
708 void (*up)(struct rtl8169_private *);
709 } pll_power_ops;
710
d58d46b5
FR		 711 struct jumbo_ops {
712 void (*enable)(struct rtl8169_private *);
713 void (*disable)(struct rtl8169_private *);
714 } jumbo_ops;
715
54405cde 716 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 717 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 718 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 719 void (*hw_start)(struct net_device *);
4da19633 720 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 721 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 722 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 723
724 struct {
da78dbff
FR		 725 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
726 struct mutex mutex;
4422bcd4 727 struct work_struct work;
da78dbff 728 bool enabled;
4422bcd4
FR		 729 } wk;
730
f23e7fda 731 unsigned features;
ccdffb9a
FR		 732
733 struct mii_if_info mii;
355423d0 734 struct rtl8169_counters counters;
e1759441 735 u32 saved_wolopts;
e03f33af 736 u32 opts1_mask;
f1e02ed1 737
b6ffd97f
FR		 738 struct rtl_fw {
739 const struct firmware *fw;
1c361efb
FR		 740
741#define RTL_VER_SIZE 32
742
743 char version[RTL_VER_SIZE];
744
745 struct rtl_fw_phy_action {
746 __le32 *code;
747 size_t size;
748 } phy_action;
b6ffd97f 749 } *rtl_fw;
497888cf 750#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
1da177e4
LT		 751};
752
979b6c13 753MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 754MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 755module_param(use_dac, int, 0);
4300e8c7 756MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 757module_param_named(debug, debug.msg_enable, int, 0);
758MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 759MODULE_LICENSE("GPL");
760MODULE_VERSION(RTL8169_VERSION);
bca03d5f 761MODULE_FIRMWARE(FIRMWARE_8168D_1);
762MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 763MODULE_FIRMWARE(FIRMWARE_8168E_1);
764MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 765MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 766MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 767MODULE_FIRMWARE(FIRMWARE_8168F_1);
768MODULE_FIRMWARE(FIRMWARE_8168F_2);
1da177e4
LT		 769
770static int rtl8169_open(struct net_device *dev);
61357325
SH		 771static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
772 struct net_device *dev);
7d12e780 773static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 774static int rtl8169_init_ring(struct net_device *dev);
07ce4064 775static void rtl_hw_start(struct net_device *dev);
1da177e4 776static int rtl8169_close(struct net_device *dev);
07ce4064 777static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 778static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 779static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
4dcb7d33 780static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
99f252b0 781static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 782static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 783
da78dbff
FR		 784static void rtl_lock_work(struct rtl8169_private *tp)
785{
786 mutex_lock(&tp->wk.mutex);
787}
788
789static void rtl_unlock_work(struct rtl8169_private *tp)
790{
791 mutex_unlock(&tp->wk.mutex);
792}
793
d58d46b5
FR		 794static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
795{
796 int cap = pci_pcie_cap(pdev);
797
798 if (cap) {
799 u16 ctl;
800
801 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
802 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
803 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
804 }
805}
806
b646d900 807static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
808{
809 void __iomem *ioaddr = tp->mmio_addr;
810 int i;
811
812 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
813 for (i = 0; i < 20; i++) {
814 udelay(100);
815 if (RTL_R32(OCPAR) & OCPAR_FLAG)
816 break;
817 }
818 return RTL_R32(OCPDR);
819}
820
821static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
822{
823 void __iomem *ioaddr = tp->mmio_addr;
824 int i;
825
826 RTL_W32(OCPDR, data);
827 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
828 for (i = 0; i < 20; i++) {
829 udelay(100);
830 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
831 break;
832 }
833}
834
fac5b3ca 835static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 836{
fac5b3ca 837 void __iomem *ioaddr = tp->mmio_addr;
b646d900 838 int i;
839
840 RTL_W8(ERIDR, cmd);
841 RTL_W32(ERIAR, 0x800010e8);
842 msleep(2);
843 for (i = 0; i < 5; i++) {
844 udelay(100);
1e4e82ba 845 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 846 break;
847 }
848
fac5b3ca 849 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 850}
851
852#define OOB_CMD_RESET 0x00
853#define OOB_CMD_DRIVER_START 0x05
854#define OOB_CMD_DRIVER_STOP 0x06
855
cecb5fd7
FR		 856static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
857{
858 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
859}
860
b646d900 861static void rtl8168_driver_start(struct rtl8169_private *tp)
862{
cecb5fd7 863 u16 reg;
b646d900 864 int i;
865
866 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
867
cecb5fd7 868 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 869
b646d900 870 for (i = 0; i < 10; i++) {
871 msleep(10);
4804b3b3 872 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 873 break;
874 }
875}
876
877static void rtl8168_driver_stop(struct rtl8169_private *tp)
878{
cecb5fd7 879 u16 reg;
b646d900 880 int i;
881
882 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
883
cecb5fd7 884 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 885
b646d900 886 for (i = 0; i < 10; i++) {
887 msleep(10);
4804b3b3 888 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 889 break;
890 }
891}
892
4804b3b3 893static int r8168dp_check_dash(struct rtl8169_private *tp)
894{
cecb5fd7 895 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 896
cecb5fd7 897 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 898}
b646d900 899
4da19633 900static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 901{
902 int i;
903
a6baf3af 904 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 905
2371408c 906 for (i = 20; i > 0; i--) {
07d3f51f
FR		 907 /*
908 * Check if the RTL8169 has completed writing to the specified
909 * MII register.
910 */
5b0384f4 911 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 912 break;
2371408c 913 udelay(25);
1da177e4 914 }
024a07ba 915 /*
81a95f04
TT		 916 * According to hardware specs a 20us delay is required after write
917 * complete indication, but before sending next command.
024a07ba 918 */
81a95f04 919 udelay(20);
1da177e4
LT		 920}
921
4da19633 922static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 923{
924 int i, value = -1;
925
a6baf3af 926 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 927
2371408c 928 for (i = 20; i > 0; i--) {
07d3f51f
FR		 929 /*
930 * Check if the RTL8169 has completed retrieving data from
931 * the specified MII register.
932 */
1da177e4 933 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 934 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 935 break;
936 }
2371408c 937 udelay(25);
1da177e4 938 }
81a95f04
TT		 939 /*
940 * According to hardware specs a 20us delay is required after read
941 * complete indication, but before sending next command.
942 */
943 udelay(20);
944
1da177e4
LT		 945 return value;
946}
947
c0e45c1c 948static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
949{
950 int i;
951
952 RTL_W32(OCPDR, data |
953 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
954 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
955 RTL_W32(EPHY_RXER_NUM, 0);
956
957 for (i = 0; i < 100; i++) {
958 mdelay(1);
959 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
960 break;
961 }
962}
963
964static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
965{
966 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
967 (value & OCPDR_DATA_MASK));
968}
969
970static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
971{
972 int i;
973
974 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
975
976 mdelay(1);
977 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
978 RTL_W32(EPHY_RXER_NUM, 0);
979
980 for (i = 0; i < 100; i++) {
981 mdelay(1);
982 if (RTL_R32(OCPAR) & OCPAR_FLAG)
983 break;
984 }
985
986 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
987}
988
e6de30d6 989#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
990
991static void r8168dp_2_mdio_start(void __iomem *ioaddr)
992{
993 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
994}
995
996static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
997{
998 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
999}
1000
1001static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1002{
1003 r8168dp_2_mdio_start(ioaddr);
1004
1005 r8169_mdio_write(ioaddr, reg_addr, value);
1006
1007 r8168dp_2_mdio_stop(ioaddr);
1008}
1009
1010static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1011{
1012 int value;
1013
1014 r8168dp_2_mdio_start(ioaddr);
1015
1016 value = r8169_mdio_read(ioaddr, reg_addr);
1017
1018 r8168dp_2_mdio_stop(ioaddr);
1019
1020 return value;
1021}
1022
4da19633 1023static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1024{
c0e45c1c 1025 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 1026}
1027
4da19633 1028static int rtl_readphy(struct rtl8169_private *tp, int location)
1029{
c0e45c1c 1030 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 1031}
1032
1033static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1034{
1035 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1036}
1037
1038static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1039{
1040 int val;
1041
4da19633 1042 val = rtl_readphy(tp, reg_addr);
1043 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1044}
1045
ccdffb9a
FR		 1046static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1047 int val)
1048{
1049 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1050
4da19633 1051 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1052}
1053
1054static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1055{
1056 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1057
4da19633 1058 return rtl_readphy(tp, location);
ccdffb9a
FR		 1059}
1060
dacf8154
FR		 1061static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1062{
1063 unsigned int i;
1064
1065 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1066 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1067
1068 for (i = 0; i < 100; i++) {
1069 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1070 break;
1071 udelay(10);
1072 }
1073}
1074
1075static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1076{
1077 u16 value = 0xffff;
1078 unsigned int i;
1079
1080 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1081
1082 for (i = 0; i < 100; i++) {
1083 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1084 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1085 break;
1086 }
1087 udelay(10);
1088 }
1089
1090 return value;
1091}
1092
1093static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1094{
1095 unsigned int i;
1096
1097 RTL_W32(CSIDR, value);
1098 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1099 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1100
1101 for (i = 0; i < 100; i++) {
1102 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1103 break;
1104 udelay(10);
1105 }
1106}
1107
1108static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1109{
1110 u32 value = ~0x00;
1111 unsigned int i;
1112
1113 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1114 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1115
1116 for (i = 0; i < 100; i++) {
1117 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1118 value = RTL_R32(CSIDR);
1119 break;
1120 }
1121 udelay(10);
1122 }
1123
1124 return value;
1125}
1126
133ac40a
HW		 1127static
1128void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1129{
1130 unsigned int i;
1131
1132 BUG_ON((addr & 3) || (mask == 0));
1133 RTL_W32(ERIDR, val);
1134 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1135
1136 for (i = 0; i < 100; i++) {
1137 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1138 break;
1139 udelay(100);
1140 }
1141}
1142
1143static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1144{
1145 u32 value = ~0x00;
1146 unsigned int i;
1147
1148 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1149
1150 for (i = 0; i < 100; i++) {
1151 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1152 value = RTL_R32(ERIDR);
1153 break;
1154 }
1155 udelay(100);
1156 }
1157
1158 return value;
1159}
1160
1161static void
1162rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1163{
1164 u32 val;
1165
1166 val = rtl_eri_read(ioaddr, addr, type);
1167 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1168}
1169
c28aa385 1170struct exgmac_reg {
1171 u16 addr;
1172 u16 mask;
1173 u32 val;
1174};
1175
1176static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1177 const struct exgmac_reg *r, int len)
1178{
1179 while (len-- > 0) {
1180 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1181 r++;
1182 }
1183}
1184
daf9df6d 1185static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1186{
1187 u8 value = 0xff;
1188 unsigned int i;
1189
1190 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1191
1192 for (i = 0; i < 300; i++) {
1193 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1194 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1195 break;
1196 }
1197 udelay(100);
1198 }
1199
1200 return value;
1201}
1202
9085cdfa
FR		 1203static u16 rtl_get_events(struct rtl8169_private *tp)
1204{
1205 void __iomem *ioaddr = tp->mmio_addr;
1206
1207 return RTL_R16(IntrStatus);
1208}
1209
1210static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1211{
1212 void __iomem *ioaddr = tp->mmio_addr;
1213
1214 RTL_W16(IntrStatus, bits);
1215 mmiowb();
1216}
1217
1218static void rtl_irq_disable(struct rtl8169_private *tp)
1219{
1220 void __iomem *ioaddr = tp->mmio_addr;
1221
1222 RTL_W16(IntrMask, 0);
1223 mmiowb();
1224}
1225
3e990ff5
FR		 1226static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1227{
1228 void __iomem *ioaddr = tp->mmio_addr;
1229
1230 RTL_W16(IntrMask, bits);
1231}
1232
da78dbff
FR		 1233#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1234#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1235#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1236
1237static void rtl_irq_enable_all(struct rtl8169_private *tp)
1238{
1239 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1240}
1241
811fd301 1242static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1243{
811fd301 1244 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1245
9085cdfa 1246 rtl_irq_disable(tp);
da78dbff 1247 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1248 RTL_R8(ChipCmd);
1da177e4
LT		 1249}
1250
4da19633 1251static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1252{
4da19633 1253 void __iomem *ioaddr = tp->mmio_addr;
1254
1da177e4
LT		 1255 return RTL_R32(TBICSR) & TBIReset;
1256}
1257
4da19633 1258static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1259{
4da19633 1260 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1261}
1262
1263static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1264{
1265 return RTL_R32(TBICSR) & TBILinkOk;
1266}
1267
1268static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1269{
1270 return RTL_R8(PHYstatus) & LinkStatus;
1271}
1272
4da19633 1273static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1274{
4da19633 1275 void __iomem *ioaddr = tp->mmio_addr;
1276
1da177e4
LT		 1277 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1278}
1279
4da19633 1280static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1281{
1282 unsigned int val;
1283
4da19633 1284 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1285 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1286}
1287
70090424
HW		 1288static void rtl_link_chg_patch(struct rtl8169_private *tp)
1289{
1290 void __iomem *ioaddr = tp->mmio_addr;
1291 struct net_device *dev = tp->dev;
1292
1293 if (!netif_running(dev))
1294 return;
1295
1296 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1297 if (RTL_R8(PHYstatus) & _1000bpsF) {
1298 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1299 0x00000011, ERIAR_EXGMAC);
1300 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1301 0x00000005, ERIAR_EXGMAC);
1302 } else if (RTL_R8(PHYstatus) & _100bps) {
1303 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1304 0x0000001f, ERIAR_EXGMAC);
1305 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1306 0x00000005, ERIAR_EXGMAC);
1307 } else {
1308 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1309 0x0000001f, ERIAR_EXGMAC);
1310 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1311 0x0000003f, ERIAR_EXGMAC);
1312 }
1313 /* Reset packet filter */
1314 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1315 ERIAR_EXGMAC);
1316 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1317 ERIAR_EXGMAC);
c2218925
HW		 1318 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1319 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1320 if (RTL_R8(PHYstatus) & _1000bpsF) {
1321 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1322 0x00000011, ERIAR_EXGMAC);
1323 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1324 0x00000005, ERIAR_EXGMAC);
1325 } else {
1326 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1327 0x0000001f, ERIAR_EXGMAC);
1328 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1329 0x0000003f, ERIAR_EXGMAC);
1330 }
70090424
HW		 1331 }
1332}
1333
e4fbce74 1334static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1335 struct rtl8169_private *tp,
1336 void __iomem *ioaddr, bool pm)
1da177e4 1337{
1da177e4 1338 if (tp->link_ok(ioaddr)) {
70090424 1339 rtl_link_chg_patch(tp);
e1759441 1340 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1341 if (pm)
1342 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1343 netif_carrier_on(dev);
1519e57f
FR		 1344 if (net_ratelimit())
1345 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1346 } else {
1da177e4 1347 netif_carrier_off(dev);
bf82c189 1348 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1349 if (pm)
10953db8 1350 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1351 }
1da177e4
LT		 1352}
1353
e4fbce74
RW		 1354static void rtl8169_check_link_status(struct net_device *dev,
1355 struct rtl8169_private *tp,
1356 void __iomem *ioaddr)
1357{
1358 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1359}
1360
e1759441
RW		 1361#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1362
1363static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1364{
61a4dcc2
FR		 1365 void __iomem *ioaddr = tp->mmio_addr;
1366 u8 options;
e1759441 1367 u32 wolopts = 0;
61a4dcc2
FR		 1368
1369 options = RTL_R8(Config1);
1370 if (!(options & PMEnable))
e1759441 1371 return 0;
61a4dcc2
FR		 1372
1373 options = RTL_R8(Config3);
1374 if (options & LinkUp)
e1759441 1375 wolopts |= WAKE_PHY;
61a4dcc2 1376 if (options & MagicPacket)
e1759441 1377 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1378
1379 options = RTL_R8(Config5);
1380 if (options & UWF)
e1759441 1381 wolopts |= WAKE_UCAST;
61a4dcc2 1382 if (options & BWF)
e1759441 1383 wolopts |= WAKE_BCAST;
61a4dcc2 1384 if (options & MWF)
e1759441 1385 wolopts |= WAKE_MCAST;
61a4dcc2 1386
e1759441 1387 return wolopts;
61a4dcc2
FR		 1388}
1389
e1759441 1390static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1391{
1392 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1393
da78dbff 1394 rtl_lock_work(tp);
e1759441
RW		 1395
1396 wol->supported = WAKE_ANY;
1397 wol->wolopts = __rtl8169_get_wol(tp);
1398
da78dbff 1399 rtl_unlock_work(tp);
e1759441
RW		 1400}
1401
1402static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1403{
61a4dcc2 1404 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1405 unsigned int i;
350f7596 1406 static const struct {
61a4dcc2
FR		 1407 u32 opt;
1408 u16 reg;
1409 u8 mask;
1410 } cfg[] = {
1411 { WAKE_ANY, Config1, PMEnable },
1412 { WAKE_PHY, Config3, LinkUp },
1413 { WAKE_MAGIC, Config3, MagicPacket },
1414 { WAKE_UCAST, Config5, UWF },
1415 { WAKE_BCAST, Config5, BWF },
1416 { WAKE_MCAST, Config5, MWF },
1417 { WAKE_ANY, Config5, LanWake }
1418 };
1419
61a4dcc2
FR		 1420 RTL_W8(Cfg9346, Cfg9346_Unlock);
1421
1422 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1423 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1424 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1425 options |= cfg[i].mask;
1426 RTL_W8(cfg[i].reg, options);
1427 }
1428
1429 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1430}
1431
1432static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1433{
1434 struct rtl8169_private *tp = netdev_priv(dev);
1435
da78dbff 1436 rtl_lock_work(tp);
61a4dcc2 1437
f23e7fda
FR		 1438 if (wol->wolopts)
1439 tp->features |= RTL_FEATURE_WOL;
1440 else
1441 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1442 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1443
1444 rtl_unlock_work(tp);
61a4dcc2 1445
ea80907f 1446 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1447
61a4dcc2
FR		 1448 return 0;
1449}
1450
31bd204f
FR		 1451static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1452{
85bffe6c 1453 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1454}
1455
1da177e4
LT		 1456static void rtl8169_get_drvinfo(struct net_device *dev,
1457 struct ethtool_drvinfo *info)
1458{
1459 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1460 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1461
68aad78c
RJ		 1462 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1463 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1464 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1465 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1466 if (!IS_ERR_OR_NULL(rtl_fw))
1467 strlcpy(info->fw_version, rtl_fw->version,
1468 sizeof(info->fw_version));
1da177e4
LT		 1469}
1470
1471static int rtl8169_get_regs_len(struct net_device *dev)
1472{
1473 return R8169_REGS_SIZE;
1474}
1475
1476static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1477 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1478{
1479 struct rtl8169_private *tp = netdev_priv(dev);
1480 void __iomem *ioaddr = tp->mmio_addr;
1481 int ret = 0;
1482 u32 reg;
1483
1484 reg = RTL_R32(TBICSR);
1485 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1486 (duplex == DUPLEX_FULL)) {
1487 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1488 } else if (autoneg == AUTONEG_ENABLE)
1489 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1490 else {
bf82c189
JP		 1491 netif_warn(tp, link, dev,
1492 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1493 ret = -EOPNOTSUPP;
1494 }
1495
1496 return ret;
1497}
1498
1499static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1500 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1501{
1502 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1503 int giga_ctrl, bmcr;
54405cde 1504 int rc = -EINVAL;
1da177e4 1505
716b50a3 1506 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1507
1508 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1509 int auto_nego;
1510
4da19633 1511 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1512 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1513 ADVERTISE_100HALF | ADVERTISE_100FULL);
1514
1515 if (adv & ADVERTISED_10baseT_Half)
1516 auto_nego |= ADVERTISE_10HALF;
1517 if (adv & ADVERTISED_10baseT_Full)
1518 auto_nego |= ADVERTISE_10FULL;
1519 if (adv & ADVERTISED_100baseT_Half)
1520 auto_nego |= ADVERTISE_100HALF;
1521 if (adv & ADVERTISED_100baseT_Full)
1522 auto_nego |= ADVERTISE_100FULL;
1523
3577aa1b 1524 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1525
4da19633 1526 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1527 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1528
3577aa1b 1529 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1530 if (tp->mii.supports_gmii) {
54405cde
ON		 1531 if (adv & ADVERTISED_1000baseT_Half)
1532 giga_ctrl |= ADVERTISE_1000HALF;
1533 if (adv & ADVERTISED_1000baseT_Full)
1534 giga_ctrl |= ADVERTISE_1000FULL;
1535 } else if (adv & (ADVERTISED_1000baseT_Half |
1536 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1537 netif_info(tp, link, dev,
1538 "PHY does not support 1000Mbps\n");
54405cde 1539 goto out;
bcf0bf90 1540 }
1da177e4 1541
3577aa1b 1542 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1543
4da19633 1544 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1545 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1546 } else {
1547 giga_ctrl = 0;
1548
1549 if (speed == SPEED_10)
1550 bmcr = 0;
1551 else if (speed == SPEED_100)
1552 bmcr = BMCR_SPEED100;
1553 else
54405cde 1554 goto out;
3577aa1b 1555
1556 if (duplex == DUPLEX_FULL)
1557 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1558 }
1559
4da19633 1560 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1561
cecb5fd7
FR		 1562 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1563 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1564 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1565 rtl_writephy(tp, 0x17, 0x2138);
1566 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1567 } else {
4da19633 1568 rtl_writephy(tp, 0x17, 0x2108);
1569 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1570 }
1571 }
1572
54405cde
ON		 1573 rc = 0;
1574out:
1575 return rc;
1da177e4
LT		 1576}
1577
1578static int rtl8169_set_speed(struct net_device *dev,
54405cde 1579 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1580{
1581 struct rtl8169_private *tp = netdev_priv(dev);
1582 int ret;
1583
54405cde 1584 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1585 if (ret < 0)
1586 goto out;
1da177e4 1587
4876cc1e
FR		 1588 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1589 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1590 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1591 }
1592out:
1da177e4
LT		 1593 return ret;
1594}
1595
1596static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1597{
1598 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1599 int ret;
1600
4876cc1e
FR		 1601 del_timer_sync(&tp->timer);
1602
da78dbff 1603 rtl_lock_work(tp);
cecb5fd7 1604 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1605 cmd->duplex, cmd->advertising);
da78dbff 1606 rtl_unlock_work(tp);
5b0384f4 1607
1da177e4
LT		 1608 return ret;
1609}
1610
c8f44aff
MM		 1611static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1612 netdev_features_t features)
1da177e4 1613{
d58d46b5
FR		 1614 struct rtl8169_private *tp = netdev_priv(dev);
1615
2b7b4318 1616 if (dev->mtu > TD_MSS_MAX)
350fb32a 1617 features &= ~NETIF_F_ALL_TSO;
1da177e4 1618
d58d46b5
FR		 1619 if (dev->mtu > JUMBO_1K &&
1620 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1621 features &= ~NETIF_F_IP_CSUM;
1622
350fb32a 1623 return features;
1da177e4
LT		 1624}
1625
da78dbff
FR		 1626static void __rtl8169_set_features(struct net_device *dev,
1627 netdev_features_t features)
1da177e4
LT		 1628{
1629 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1630
da78dbff 1631 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1632
350fb32a 1633 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1634 tp->cp_cmd |= RxChkSum;
1635 else
1636 tp->cp_cmd &= ~RxChkSum;
1637
350fb32a
MM		 1638 if (dev->features & NETIF_F_HW_VLAN_RX)
1639 tp->cp_cmd |= RxVlan;
1640 else
1641 tp->cp_cmd &= ~RxVlan;
1642
1da177e4
LT		 1643 RTL_W16(CPlusCmd, tp->cp_cmd);
1644 RTL_R16(CPlusCmd);
da78dbff 1645}
1da177e4 1646
da78dbff
FR		 1647static int rtl8169_set_features(struct net_device *dev,
1648 netdev_features_t features)
1649{
1650 struct rtl8169_private *tp = netdev_priv(dev);
1651
1652 rtl_lock_work(tp);
1653 __rtl8169_set_features(dev, features);
1654 rtl_unlock_work(tp);
1da177e4
LT		 1655
1656 return 0;
1657}
1658
da78dbff 1659
1da177e4
LT		 1660static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1661 struct sk_buff *skb)
1662{
eab6d18d 1663 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1664 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1665}
1666
7a8fc77b 1667static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1668{
1669 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1670
7a8fc77b
FR		 1671 if (opts2 & RxVlanTag)
1672 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1673
1da177e4 1674 desc->opts2 = 0;
1da177e4
LT		 1675}
1676
ccdffb9a 1677static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1678{
1679 struct rtl8169_private *tp = netdev_priv(dev);
1680 void __iomem *ioaddr = tp->mmio_addr;
1681 u32 status;
1682
1683 cmd->supported =
1684 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1685 cmd->port = PORT_FIBRE;
1686 cmd->transceiver = XCVR_INTERNAL;
1687
1688 status = RTL_R32(TBICSR);
1689 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1690 cmd->autoneg = !!(status & TBINwEnable);
1691
70739497 1692 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1693 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1694
1695 return 0;
1da177e4
LT		 1696}
1697
ccdffb9a 1698static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1699{
1700 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1701
1702 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1703}
1704
1705static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1706{
1707 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1708 int rc;
1da177e4 1709
da78dbff 1710 rtl_lock_work(tp);
ccdffb9a 1711 rc = tp->get_settings(dev, cmd);
da78dbff 1712 rtl_unlock_work(tp);
1da177e4 1713
ccdffb9a 1714 return rc;
1da177e4
LT		 1715}
1716
1717static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1718 void *p)
1719{
5b0384f4 1720 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1721
5b0384f4
FR		 1722 if (regs->len > R8169_REGS_SIZE)
1723 regs->len = R8169_REGS_SIZE;
1da177e4 1724
da78dbff
FR		 1725 rtl_lock_work(tp);
1726 spin_lock_bh(&tp->lock);
5b0384f4 1727 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff
FR		 1728 spin_unlock_bh(&tp->lock);
1729 rtl_unlock_work(tp);
1da177e4
LT		 1730}
1731
b57b7e5a
SH		 1732static u32 rtl8169_get_msglevel(struct net_device *dev)
1733{
1734 struct rtl8169_private *tp = netdev_priv(dev);
1735
1736 return tp->msg_enable;
1737}
1738
1739static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1740{
1741 struct rtl8169_private *tp = netdev_priv(dev);
1742
1743 tp->msg_enable = value;
1744}
1745
d4a3a0fc
SH		 1746static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1747 "tx_packets",
1748 "rx_packets",
1749 "tx_errors",
1750 "rx_errors",
1751 "rx_missed",
1752 "align_errors",
1753 "tx_single_collisions",
1754 "tx_multi_collisions",
1755 "unicast",
1756 "broadcast",
1757 "multicast",
1758 "tx_aborted",
1759 "tx_underrun",
1760};
1761
b9f2c044 1762static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1763{
b9f2c044
JG		 1764 switch (sset) {
1765 case ETH_SS_STATS:
1766 return ARRAY_SIZE(rtl8169_gstrings);
1767 default:
1768 return -EOPNOTSUPP;
1769 }
d4a3a0fc
SH		 1770}
1771
355423d0 1772static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1773{
1774 struct rtl8169_private *tp = netdev_priv(dev);
1775 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1776 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1777 struct rtl8169_counters *counters;
1778 dma_addr_t paddr;
1779 u32 cmd;
355423d0 1780 int wait = 1000;
d4a3a0fc 1781
355423d0
IV		 1782 /*
1783 * Some chips are unable to dump tally counters when the receiver
1784 * is disabled.
1785 */
1786 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1787 return;
d4a3a0fc 1788
48addcc9 1789 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1790 if (!counters)
1791 return;
1792
1793 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1794 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1795 RTL_W32(CounterAddrLow, cmd);
1796 RTL_W32(CounterAddrLow, cmd | CounterDump);
1797
355423d0
IV		 1798 while (wait--) {
1799 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1800 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1801 break;
355423d0
IV		 1802 }
1803 udelay(10);
d4a3a0fc
SH		 1804 }
1805
1806 RTL_W32(CounterAddrLow, 0);
1807 RTL_W32(CounterAddrHigh, 0);
1808
48addcc9 1809 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1810}
1811
355423d0
IV		 1812static void rtl8169_get_ethtool_stats(struct net_device *dev,
1813 struct ethtool_stats *stats, u64 *data)
1814{
1815 struct rtl8169_private *tp = netdev_priv(dev);
1816
1817 ASSERT_RTNL();
1818
1819 rtl8169_update_counters(dev);
1820
1821 data[0] = le64_to_cpu(tp->counters.tx_packets);
1822 data[1] = le64_to_cpu(tp->counters.rx_packets);
1823 data[2] = le64_to_cpu(tp->counters.tx_errors);
1824 data[3] = le32_to_cpu(tp->counters.rx_errors);
1825 data[4] = le16_to_cpu(tp->counters.rx_missed);
1826 data[5] = le16_to_cpu(tp->counters.align_errors);
1827 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1828 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1829 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1830 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1831 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1832 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1833 data[12] = le16_to_cpu(tp->counters.tx_underun);
1834}
1835
d4a3a0fc
SH		 1836static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1837{
1838 switch(stringset) {
1839 case ETH_SS_STATS:
1840 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1841 break;
1842 }
1843}
1844
7282d491 1845static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1846 .get_drvinfo = rtl8169_get_drvinfo,
1847 .get_regs_len = rtl8169_get_regs_len,
1848 .get_link = ethtool_op_get_link,
1849 .get_settings = rtl8169_get_settings,
1850 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1851 .get_msglevel = rtl8169_get_msglevel,
1852 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1853 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1854 .get_wol = rtl8169_get_wol,
1855 .set_wol = rtl8169_set_wol,
d4a3a0fc 1856 .get_strings = rtl8169_get_strings,
b9f2c044 1857 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1858 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1859};
1860
07d3f51f 1861static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1862 struct net_device *dev, u8 default_version)
1da177e4 1863{
5d320a20 1864 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1865 /*
1866 * The driver currently handles the 8168Bf and the 8168Be identically
1867 * but they can be identified more specifically through the test below
1868 * if needed:
1869 *
1870 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1871 *
1872 * Same thing for the 8101Eb and the 8101Ec:
1873 *
1874 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1875 */
3744100e 1876 static const struct rtl_mac_info {
1da177e4 1877 u32 mask;
e3cf0cc0 1878 u32 val;
1da177e4
LT		 1879 int mac_version;
1880 } mac_info[] = {
c2218925
HW		 1881 /* 8168F family. */
1882 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1883 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1884
01dc7fec 1885 /* 8168E family. */
70090424 1886 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1887 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1888 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1889 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1890
5b538df9 1891 /* 8168D family. */
daf9df6d 1892 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1893 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1894 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1895
e6de30d6 1896 /* 8168DP family. */
1897 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1898 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1899 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1900
ef808d50 1901 /* 8168C family. */
17c99297 1902 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1903 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1904 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1905 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1906 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1907 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1908 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1909 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1910 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1911
1912 /* 8168B family. */
1913 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1914 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1915 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1916 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1917
1918 /* 8101 family. */
36a0e6c2 1919 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1920 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1921 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1922 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1923 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1924 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1925 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1926 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1927 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1928 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1929 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1930 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1931 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1932 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1933 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1934 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1935 /* FIXME: where did these entries come from ? -- FR */
1936 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1937 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1938
1939 /* 8110 family. */
1940 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1941 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1942 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1943 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1944 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1945 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1946
f21b75e9
JD		 1947 /* Catch-all */
1948 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1949 };
1950 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1951 u32 reg;
1952
e3cf0cc0
FR		 1953 reg = RTL_R32(TxConfig);
1954 while ((reg & p->mask) != p->val)
1da177e4
LT		 1955 p++;
1956 tp->mac_version = p->mac_version;
5d320a20
FR		 1957
1958 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1959 netif_notice(tp, probe, dev,
1960 "unknown MAC, using family default\n");
1961 tp->mac_version = default_version;
1962 }
1da177e4
LT		 1963}
1964
1965static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1966{
bcf0bf90 1967 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1968}
1969
867763c1
FR		 1970struct phy_reg {
1971 u16 reg;
1972 u16 val;
1973};
1974
4da19633 1975static void rtl_writephy_batch(struct rtl8169_private *tp,
1976 const struct phy_reg *regs, int len)
867763c1
FR		 1977{
1978 while (len-- > 0) {
4da19633 1979 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1980 regs++;
1981 }
1982}
1983
bca03d5f 1984#define PHY_READ 0x00000000
1985#define PHY_DATA_OR 0x10000000
1986#define PHY_DATA_AND 0x20000000
1987#define PHY_BJMPN 0x30000000
1988#define PHY_READ_EFUSE 0x40000000
1989#define PHY_READ_MAC_BYTE 0x50000000
1990#define PHY_WRITE_MAC_BYTE 0x60000000
1991#define PHY_CLEAR_READCOUNT 0x70000000
1992#define PHY_WRITE 0x80000000
1993#define PHY_READCOUNT_EQ_SKIP 0x90000000
1994#define PHY_COMP_EQ_SKIPN 0xa0000000
1995#define PHY_COMP_NEQ_SKIPN 0xb0000000
1996#define PHY_WRITE_PREVIOUS 0xc0000000
1997#define PHY_SKIPN 0xd0000000
1998#define PHY_DELAY_MS 0xe0000000
1999#define PHY_WRITE_ERI_WORD 0xf0000000
2000
960aee6c
HW		 2001struct fw_info {
2002 u32 magic;
2003 char version[RTL_VER_SIZE];
2004 __le32 fw_start;
2005 __le32 fw_len;
2006 u8 chksum;
2007} __packed;
2008
1c361efb
FR		 2009#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2010
2011static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2012{
b6ffd97f 2013 const struct firmware *fw = rtl_fw->fw;
960aee6c 2014 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2015 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2016 char *version = rtl_fw->version;
2017 bool rc = false;
2018
2019 if (fw->size < FW_OPCODE_SIZE)
2020 goto out;
960aee6c
HW		 2021
2022 if (!fw_info->magic) {
2023 size_t i, size, start;
2024 u8 checksum = 0;
2025
2026 if (fw->size < sizeof(*fw_info))
2027 goto out;
2028
2029 for (i = 0; i < fw->size; i++)
2030 checksum += fw->data[i];
2031 if (checksum != 0)
2032 goto out;
2033
2034 start = le32_to_cpu(fw_info->fw_start);
2035 if (start > fw->size)
2036 goto out;
2037
2038 size = le32_to_cpu(fw_info->fw_len);
2039 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2040 goto out;
2041
2042 memcpy(version, fw_info->version, RTL_VER_SIZE);
2043
2044 pa->code = (__le32 *)(fw->data + start);
2045 pa->size = size;
2046 } else {
1c361efb
FR		 2047 if (fw->size % FW_OPCODE_SIZE)
2048 goto out;
2049
2050 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2051
2052 pa->code = (__le32 *)fw->data;
2053 pa->size = fw->size / FW_OPCODE_SIZE;
2054 }
2055 version[RTL_VER_SIZE - 1] = 0;
2056
2057 rc = true;
2058out:
2059 return rc;
2060}
2061
fd112f2e
FR		 2062static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2063 struct rtl_fw_phy_action *pa)
1c361efb 2064{
fd112f2e 2065 bool rc = false;
1c361efb 2066 size_t index;
bca03d5f 2067
1c361efb
FR		 2068 for (index = 0; index < pa->size; index++) {
2069 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2070 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2071
42b82dc1 2072 switch(action & 0xf0000000) {
2073 case PHY_READ:
2074 case PHY_DATA_OR:
2075 case PHY_DATA_AND:
2076 case PHY_READ_EFUSE:
2077 case PHY_CLEAR_READCOUNT:
2078 case PHY_WRITE:
2079 case PHY_WRITE_PREVIOUS:
2080 case PHY_DELAY_MS:
2081 break;
2082
2083 case PHY_BJMPN:
2084 if (regno > index) {
fd112f2e 2085 netif_err(tp, ifup, tp->dev,
cecb5fd7 2086 "Out of range of firmware\n");
fd112f2e 2087 goto out;
42b82dc1 2088 }
2089 break;
2090 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2091 if (index + 2 >= pa->size) {
fd112f2e 2092 netif_err(tp, ifup, tp->dev,
cecb5fd7 2093 "Out of range of firmware\n");
fd112f2e 2094 goto out;
42b82dc1 2095 }
2096 break;
2097 case PHY_COMP_EQ_SKIPN:
2098 case PHY_COMP_NEQ_SKIPN:
2099 case PHY_SKIPN:
1c361efb 2100 if (index + 1 + regno >= pa->size) {
fd112f2e 2101 netif_err(tp, ifup, tp->dev,
cecb5fd7 2102 "Out of range of firmware\n");
fd112f2e 2103 goto out;
42b82dc1 2104 }
bca03d5f 2105 break;
2106
42b82dc1 2107 case PHY_READ_MAC_BYTE:
2108 case PHY_WRITE_MAC_BYTE:
2109 case PHY_WRITE_ERI_WORD:
2110 default:
fd112f2e 2111 netif_err(tp, ifup, tp->dev,
42b82dc1 2112 "Invalid action 0x%08x\n", action);
fd112f2e 2113 goto out;
bca03d5f 2114 }
2115 }
fd112f2e
FR		 2116 rc = true;
2117out:
2118 return rc;
2119}
bca03d5f 2120
fd112f2e
FR		 2121static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2122{
2123 struct net_device *dev = tp->dev;
2124 int rc = -EINVAL;
2125
2126 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2127 netif_err(tp, ifup, dev, "invalid firwmare\n");
2128 goto out;
2129 }
2130
2131 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2132 rc = 0;
2133out:
2134 return rc;
2135}
2136
2137static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2138{
2139 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2140 u32 predata, count;
2141 size_t index;
2142
2143 predata = count = 0;
42b82dc1 2144
1c361efb
FR		 2145 for (index = 0; index < pa->size; ) {
2146 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2147 u32 data = action & 0x0000ffff;
42b82dc1 2148 u32 regno = (action & 0x0fff0000) >> 16;
2149
2150 if (!action)
2151 break;
bca03d5f 2152
2153 switch(action & 0xf0000000) {
42b82dc1 2154 case PHY_READ:
2155 predata = rtl_readphy(tp, regno);
2156 count++;
2157 index++;
2158 break;
2159 case PHY_DATA_OR:
2160 predata |= data;
2161 index++;
2162 break;
2163 case PHY_DATA_AND:
2164 predata &= data;
2165 index++;
2166 break;
2167 case PHY_BJMPN:
2168 index -= regno;
2169 break;
2170 case PHY_READ_EFUSE:
2171 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2172 index++;
2173 break;
2174 case PHY_CLEAR_READCOUNT:
2175 count = 0;
2176 index++;
2177 break;
bca03d5f 2178 case PHY_WRITE:
42b82dc1 2179 rtl_writephy(tp, regno, data);
2180 index++;
2181 break;
2182 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2183 index += (count == data) ? 2 : 1;
bca03d5f 2184 break;
42b82dc1 2185 case PHY_COMP_EQ_SKIPN:
2186 if (predata == data)
2187 index += regno;
2188 index++;
2189 break;
2190 case PHY_COMP_NEQ_SKIPN:
2191 if (predata != data)
2192 index += regno;
2193 index++;
2194 break;
2195 case PHY_WRITE_PREVIOUS:
2196 rtl_writephy(tp, regno, predata);
2197 index++;
2198 break;
2199 case PHY_SKIPN:
2200 index += regno + 1;
2201 break;
2202 case PHY_DELAY_MS:
2203 mdelay(data);
2204 index++;
2205 break;
2206
2207 case PHY_READ_MAC_BYTE:
2208 case PHY_WRITE_MAC_BYTE:
2209 case PHY_WRITE_ERI_WORD:
bca03d5f 2210 default:
2211 BUG();
2212 }
2213 }
2214}
2215
f1e02ed1 2216static void rtl_release_firmware(struct rtl8169_private *tp)
2217{
b6ffd97f
FR		 2218 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2219 release_firmware(tp->rtl_fw->fw);
2220 kfree(tp->rtl_fw);
2221 }
2222 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2223}
2224
953a12cc 2225static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2226{
b6ffd97f 2227 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2228
2229 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2230 if (!IS_ERR_OR_NULL(rtl_fw))
2231 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2232}
2233
2234static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2235{
2236 if (rtl_readphy(tp, reg) != val)
2237 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2238 else
2239 rtl_apply_firmware(tp);
f1e02ed1 2240}
2241
4da19633 2242static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2243{
350f7596 2244 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2245 { 0x1f, 0x0001 },
2246 { 0x06, 0x006e },
2247 { 0x08, 0x0708 },
2248 { 0x15, 0x4000 },
2249 { 0x18, 0x65c7 },
1da177e4 2250
0b9b571d 2251 { 0x1f, 0x0001 },
2252 { 0x03, 0x00a1 },
2253 { 0x02, 0x0008 },
2254 { 0x01, 0x0120 },
2255 { 0x00, 0x1000 },
2256 { 0x04, 0x0800 },
2257 { 0x04, 0x0000 },
1da177e4 2258
0b9b571d 2259 { 0x03, 0xff41 },
2260 { 0x02, 0xdf60 },
2261 { 0x01, 0x0140 },
2262 { 0x00, 0x0077 },
2263 { 0x04, 0x7800 },
2264 { 0x04, 0x7000 },
2265
2266 { 0x03, 0x802f },
2267 { 0x02, 0x4f02 },
2268 { 0x01, 0x0409 },
2269 { 0x00, 0xf0f9 },
2270 { 0x04, 0x9800 },
2271 { 0x04, 0x9000 },
2272
2273 { 0x03, 0xdf01 },
2274 { 0x02, 0xdf20 },
2275 { 0x01, 0xff95 },
2276 { 0x00, 0xba00 },
2277 { 0x04, 0xa800 },
2278 { 0x04, 0xa000 },
2279
2280 { 0x03, 0xff41 },
2281 { 0x02, 0xdf20 },
2282 { 0x01, 0x0140 },
2283 { 0x00, 0x00bb },
2284 { 0x04, 0xb800 },
2285 { 0x04, 0xb000 },
2286
2287 { 0x03, 0xdf41 },
2288 { 0x02, 0xdc60 },
2289 { 0x01, 0x6340 },
2290 { 0x00, 0x007d },
2291 { 0x04, 0xd800 },
2292 { 0x04, 0xd000 },
2293
2294 { 0x03, 0xdf01 },
2295 { 0x02, 0xdf20 },
2296 { 0x01, 0x100a },
2297 { 0x00, 0xa0ff },
2298 { 0x04, 0xf800 },
2299 { 0x04, 0xf000 },
2300
2301 { 0x1f, 0x0000 },
2302 { 0x0b, 0x0000 },
2303 { 0x00, 0x9200 }
2304 };
1da177e4 2305
4da19633 2306 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2307}
2308
4da19633 2309static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2310{
350f7596 2311 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2312 { 0x1f, 0x0002 },
2313 { 0x01, 0x90d0 },
2314 { 0x1f, 0x0000 }
2315 };
2316
4da19633 2317 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2318}
2319
4da19633 2320static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2321{
2322 struct pci_dev *pdev = tp->pci_dev;
2e955856 2323
ccbae55e
SS		 2324 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2325 (pdev->subsystem_device != 0xe000))
2e955856 2326 return;
2327
4da19633 2328 rtl_writephy(tp, 0x1f, 0x0001);
2329 rtl_writephy(tp, 0x10, 0xf01b);
2330 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2331}
2332
4da19633 2333static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2334{
350f7596 2335 static const struct phy_reg phy_reg_init[] = {
2e955856 2336 { 0x1f, 0x0001 },
2337 { 0x04, 0x0000 },
2338 { 0x03, 0x00a1 },
2339 { 0x02, 0x0008 },
2340 { 0x01, 0x0120 },
2341 { 0x00, 0x1000 },
2342 { 0x04, 0x0800 },
2343 { 0x04, 0x9000 },
2344 { 0x03, 0x802f },
2345 { 0x02, 0x4f02 },
2346 { 0x01, 0x0409 },
2347 { 0x00, 0xf099 },
2348 { 0x04, 0x9800 },
2349 { 0x04, 0xa000 },
2350 { 0x03, 0xdf01 },
2351 { 0x02, 0xdf20 },
2352 { 0x01, 0xff95 },
2353 { 0x00, 0xba00 },
2354 { 0x04, 0xa800 },
2355 { 0x04, 0xf000 },
2356 { 0x03, 0xdf01 },
2357 { 0x02, 0xdf20 },
2358 { 0x01, 0x101a },
2359 { 0x00, 0xa0ff },
2360 { 0x04, 0xf800 },
2361 { 0x04, 0x0000 },
2362 { 0x1f, 0x0000 },
2363
2364 { 0x1f, 0x0001 },
2365 { 0x10, 0xf41b },
2366 { 0x14, 0xfb54 },
2367 { 0x18, 0xf5c7 },
2368 { 0x1f, 0x0000 },
2369
2370 { 0x1f, 0x0001 },
2371 { 0x17, 0x0cc0 },
2372 { 0x1f, 0x0000 }
2373 };
2374
4da19633 2375 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2376
4da19633 2377 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2378}
2379
4da19633 2380static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2381{
350f7596 2382 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2383 { 0x1f, 0x0001 },
2384 { 0x04, 0x0000 },
2385 { 0x03, 0x00a1 },
2386 { 0x02, 0x0008 },
2387 { 0x01, 0x0120 },
2388 { 0x00, 0x1000 },
2389 { 0x04, 0x0800 },
2390 { 0x04, 0x9000 },
2391 { 0x03, 0x802f },
2392 { 0x02, 0x4f02 },
2393 { 0x01, 0x0409 },
2394 { 0x00, 0xf099 },
2395 { 0x04, 0x9800 },
2396 { 0x04, 0xa000 },
2397 { 0x03, 0xdf01 },
2398 { 0x02, 0xdf20 },
2399 { 0x01, 0xff95 },
2400 { 0x00, 0xba00 },
2401 { 0x04, 0xa800 },
2402 { 0x04, 0xf000 },
2403 { 0x03, 0xdf01 },
2404 { 0x02, 0xdf20 },
2405 { 0x01, 0x101a },
2406 { 0x00, 0xa0ff },
2407 { 0x04, 0xf800 },
2408 { 0x04, 0x0000 },
2409 { 0x1f, 0x0000 },
2410
2411 { 0x1f, 0x0001 },
2412 { 0x0b, 0x8480 },
2413 { 0x1f, 0x0000 },
2414
2415 { 0x1f, 0x0001 },
2416 { 0x18, 0x67c7 },
2417 { 0x04, 0x2000 },
2418 { 0x03, 0x002f },
2419 { 0x02, 0x4360 },
2420 { 0x01, 0x0109 },
2421 { 0x00, 0x3022 },
2422 { 0x04, 0x2800 },
2423 { 0x1f, 0x0000 },
2424
2425 { 0x1f, 0x0001 },
2426 { 0x17, 0x0cc0 },
2427 { 0x1f, 0x0000 }
2428 };
2429
4da19633 2430 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2431}
2432
4da19633 2433static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2434{
350f7596 2435 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2436 { 0x10, 0xf41b },
2437 { 0x1f, 0x0000 }
2438 };
2439
4da19633 2440 rtl_writephy(tp, 0x1f, 0x0001);
2441 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2442
4da19633 2443 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2444}
2445
4da19633 2446static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2447{
350f7596 2448 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2449 { 0x1f, 0x0001 },
2450 { 0x10, 0xf41b },
2451 { 0x1f, 0x0000 }
2452 };
2453
4da19633 2454 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2455}
2456
4da19633 2457static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2458{
350f7596 2459 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2460 { 0x1f, 0x0000 },
2461 { 0x1d, 0x0f00 },
2462 { 0x1f, 0x0002 },
2463 { 0x0c, 0x1ec8 },
2464 { 0x1f, 0x0000 }
2465 };
2466
4da19633 2467 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2468}
2469
4da19633 2470static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2471{
350f7596 2472 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2473 { 0x1f, 0x0001 },
2474 { 0x1d, 0x3d98 },
2475 { 0x1f, 0x0000 }
2476 };
2477
4da19633 2478 rtl_writephy(tp, 0x1f, 0x0000);
2479 rtl_patchphy(tp, 0x14, 1 << 5);
2480 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2481
4da19633 2482 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2483}
2484
4da19633 2485static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2486{
350f7596 2487 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2488 { 0x1f, 0x0001 },
2489 { 0x12, 0x2300 },
867763c1
FR		 2490 { 0x1f, 0x0002 },
2491 { 0x00, 0x88d4 },
2492 { 0x01, 0x82b1 },
2493 { 0x03, 0x7002 },
2494 { 0x08, 0x9e30 },
2495 { 0x09, 0x01f0 },
2496 { 0x0a, 0x5500 },
2497 { 0x0c, 0x00c8 },
2498 { 0x1f, 0x0003 },
2499 { 0x12, 0xc096 },
2500 { 0x16, 0x000a },
f50d4275
FR		 2501 { 0x1f, 0x0000 },
2502 { 0x1f, 0x0000 },
2503 { 0x09, 0x2000 },
2504 { 0x09, 0x0000 }
867763c1
FR		 2505 };
2506
4da19633 2507 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2508
4da19633 2509 rtl_patchphy(tp, 0x14, 1 << 5);
2510 rtl_patchphy(tp, 0x0d, 1 << 5);
2511 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2512}
2513
4da19633 2514static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2515{
350f7596 2516 static const struct phy_reg phy_reg_init[] = {
f50d4275 2517 { 0x1f, 0x0001 },
7da97ec9 2518 { 0x12, 0x2300 },
f50d4275
FR		 2519 { 0x03, 0x802f },
2520 { 0x02, 0x4f02 },
2521 { 0x01, 0x0409 },
2522 { 0x00, 0xf099 },
2523 { 0x04, 0x9800 },
2524 { 0x04, 0x9000 },
2525 { 0x1d, 0x3d98 },
7da97ec9
FR		 2526 { 0x1f, 0x0002 },
2527 { 0x0c, 0x7eb8 },
f50d4275
FR		 2528 { 0x06, 0x0761 },
2529 { 0x1f, 0x0003 },
2530 { 0x16, 0x0f0a },
7da97ec9
FR		 2531 { 0x1f, 0x0000 }
2532 };
2533
4da19633 2534 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2535
4da19633 2536 rtl_patchphy(tp, 0x16, 1 << 0);
2537 rtl_patchphy(tp, 0x14, 1 << 5);
2538 rtl_patchphy(tp, 0x0d, 1 << 5);
2539 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2540}
2541
4da19633 2542static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2543{
350f7596 2544 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2545 { 0x1f, 0x0001 },
2546 { 0x12, 0x2300 },
2547 { 0x1d, 0x3d98 },
2548 { 0x1f, 0x0002 },
2549 { 0x0c, 0x7eb8 },
2550 { 0x06, 0x5461 },
2551 { 0x1f, 0x0003 },
2552 { 0x16, 0x0f0a },
2553 { 0x1f, 0x0000 }
2554 };
2555
4da19633 2556 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2557
4da19633 2558 rtl_patchphy(tp, 0x16, 1 << 0);
2559 rtl_patchphy(tp, 0x14, 1 << 5);
2560 rtl_patchphy(tp, 0x0d, 1 << 5);
2561 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2562}
2563
4da19633 2564static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2565{
4da19633 2566 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2567}
2568
bca03d5f 2569static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2570{
350f7596 2571 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2572 /* Channel Estimation */
5b538df9 2573 { 0x1f, 0x0001 },
daf9df6d 2574 { 0x06, 0x4064 },
2575 { 0x07, 0x2863 },
2576 { 0x08, 0x059c },
2577 { 0x09, 0x26b4 },
2578 { 0x0a, 0x6a19 },
2579 { 0x0b, 0xdcc8 },
2580 { 0x10, 0xf06d },
2581 { 0x14, 0x7f68 },
2582 { 0x18, 0x7fd9 },
2583 { 0x1c, 0xf0ff },
2584 { 0x1d, 0x3d9c },
5b538df9 2585 { 0x1f, 0x0003 },
daf9df6d 2586 { 0x12, 0xf49f },
2587 { 0x13, 0x070b },
2588 { 0x1a, 0x05ad },
bca03d5f 2589 { 0x14, 0x94c0 },
2590
2591 /*
2592 * Tx Error Issue
cecb5fd7 2593 * Enhance line driver power
bca03d5f 2594 */
5b538df9 2595 { 0x1f, 0x0002 },
daf9df6d 2596 { 0x06, 0x5561 },
2597 { 0x1f, 0x0005 },
2598 { 0x05, 0x8332 },
bca03d5f 2599 { 0x06, 0x5561 },
2600
2601 /*
2602 * Can not link to 1Gbps with bad cable
2603 * Decrease SNR threshold form 21.07dB to 19.04dB
2604 */
2605 { 0x1f, 0x0001 },
2606 { 0x17, 0x0cc0 },
daf9df6d 2607
5b538df9 2608 { 0x1f, 0x0000 },
bca03d5f 2609 { 0x0d, 0xf880 }
daf9df6d 2610 };
bca03d5f 2611 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2612
4da19633 2613 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2614
bca03d5f 2615 /*
2616 * Rx Error Issue
2617 * Fine Tune Switching regulator parameter
2618 */
4da19633 2619 rtl_writephy(tp, 0x1f, 0x0002);
2620 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2621 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2622
daf9df6d 2623 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2624 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2625 { 0x1f, 0x0002 },
2626 { 0x05, 0x669a },
2627 { 0x1f, 0x0005 },
2628 { 0x05, 0x8330 },
2629 { 0x06, 0x669a },
2630 { 0x1f, 0x0002 }
2631 };
2632 int val;
2633
4da19633 2634 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2635
4da19633 2636 val = rtl_readphy(tp, 0x0d);
daf9df6d 2637
2638 if ((val & 0x00ff) != 0x006c) {
350f7596 2639 static const u32 set[] = {
daf9df6d 2640 0x0065, 0x0066, 0x0067, 0x0068,
2641 0x0069, 0x006a, 0x006b, 0x006c
2642 };
2643 int i;
2644
4da19633 2645 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2646
2647 val &= 0xff00;
2648 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2649 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2650 }
2651 } else {
350f7596 2652 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2653 { 0x1f, 0x0002 },
2654 { 0x05, 0x6662 },
2655 { 0x1f, 0x0005 },
2656 { 0x05, 0x8330 },
2657 { 0x06, 0x6662 }
2658 };
2659
4da19633 2660 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2661 }
2662
bca03d5f 2663 /* RSET couple improve */
4da19633 2664 rtl_writephy(tp, 0x1f, 0x0002);
2665 rtl_patchphy(tp, 0x0d, 0x0300);
2666 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2667
bca03d5f 2668 /* Fine tune PLL performance */
4da19633 2669 rtl_writephy(tp, 0x1f, 0x0002);
2670 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2671 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2672
4da19633 2673 rtl_writephy(tp, 0x1f, 0x0005);
2674 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2675
2676 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2677
4da19633 2678 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2679}
2680
bca03d5f 2681static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2682{
350f7596 2683 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2684 /* Channel Estimation */
daf9df6d 2685 { 0x1f, 0x0001 },
2686 { 0x06, 0x4064 },
2687 { 0x07, 0x2863 },
2688 { 0x08, 0x059c },
2689 { 0x09, 0x26b4 },
2690 { 0x0a, 0x6a19 },
2691 { 0x0b, 0xdcc8 },
2692 { 0x10, 0xf06d },
2693 { 0x14, 0x7f68 },
2694 { 0x18, 0x7fd9 },
2695 { 0x1c, 0xf0ff },
2696 { 0x1d, 0x3d9c },
2697 { 0x1f, 0x0003 },
2698 { 0x12, 0xf49f },
2699 { 0x13, 0x070b },
2700 { 0x1a, 0x05ad },
2701 { 0x14, 0x94c0 },
2702
bca03d5f 2703 /*
2704 * Tx Error Issue
cecb5fd7 2705 * Enhance line driver power
bca03d5f 2706 */
daf9df6d 2707 { 0x1f, 0x0002 },
2708 { 0x06, 0x5561 },
2709 { 0x1f, 0x0005 },
2710 { 0x05, 0x8332 },
bca03d5f 2711 { 0x06, 0x5561 },
2712
2713 /*
2714 * Can not link to 1Gbps with bad cable
2715 * Decrease SNR threshold form 21.07dB to 19.04dB
2716 */
2717 { 0x1f, 0x0001 },
2718 { 0x17, 0x0cc0 },
daf9df6d 2719
2720 { 0x1f, 0x0000 },
bca03d5f 2721 { 0x0d, 0xf880 }
5b538df9 2722 };
bca03d5f 2723 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2724
4da19633 2725 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2726
daf9df6d 2727 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2728 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2729 { 0x1f, 0x0002 },
2730 { 0x05, 0x669a },
5b538df9 2731 { 0x1f, 0x0005 },
daf9df6d 2732 { 0x05, 0x8330 },
2733 { 0x06, 0x669a },
2734
2735 { 0x1f, 0x0002 }
2736 };
2737 int val;
2738
4da19633 2739 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2740
4da19633 2741 val = rtl_readphy(tp, 0x0d);
daf9df6d 2742 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2743 static const u32 set[] = {
daf9df6d 2744 0x0065, 0x0066, 0x0067, 0x0068,
2745 0x0069, 0x006a, 0x006b, 0x006c
2746 };
2747 int i;
2748
4da19633 2749 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2750
2751 val &= 0xff00;
2752 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2753 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2754 }
2755 } else {
350f7596 2756 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2757 { 0x1f, 0x0002 },
2758 { 0x05, 0x2642 },
5b538df9 2759 { 0x1f, 0x0005 },
daf9df6d 2760 { 0x05, 0x8330 },
2761 { 0x06, 0x2642 }
5b538df9
FR		 2762 };
2763
4da19633 2764 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2765 }
2766
bca03d5f 2767 /* Fine tune PLL performance */
4da19633 2768 rtl_writephy(tp, 0x1f, 0x0002);
2769 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2770 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2771
bca03d5f 2772 /* Switching regulator Slew rate */
4da19633 2773 rtl_writephy(tp, 0x1f, 0x0002);
2774 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2775
4da19633 2776 rtl_writephy(tp, 0x1f, 0x0005);
2777 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2778
2779 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2780
4da19633 2781 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2782}
2783
4da19633 2784static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2785{
350f7596 2786 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2787 { 0x1f, 0x0002 },
2788 { 0x10, 0x0008 },
2789 { 0x0d, 0x006c },
2790
2791 { 0x1f, 0x0000 },
2792 { 0x0d, 0xf880 },
2793
2794 { 0x1f, 0x0001 },
2795 { 0x17, 0x0cc0 },
2796
2797 { 0x1f, 0x0001 },
2798 { 0x0b, 0xa4d8 },
2799 { 0x09, 0x281c },
2800 { 0x07, 0x2883 },
2801 { 0x0a, 0x6b35 },
2802 { 0x1d, 0x3da4 },
2803 { 0x1c, 0xeffd },
2804 { 0x14, 0x7f52 },
2805 { 0x18, 0x7fc6 },
2806 { 0x08, 0x0601 },
2807 { 0x06, 0x4063 },
2808 { 0x10, 0xf074 },
2809 { 0x1f, 0x0003 },
2810 { 0x13, 0x0789 },
2811 { 0x12, 0xf4bd },
2812 { 0x1a, 0x04fd },
2813 { 0x14, 0x84b0 },
2814 { 0x1f, 0x0000 },
2815 { 0x00, 0x9200 },
2816
2817 { 0x1f, 0x0005 },
2818 { 0x01, 0x0340 },
2819 { 0x1f, 0x0001 },
2820 { 0x04, 0x4000 },
2821 { 0x03, 0x1d21 },
2822 { 0x02, 0x0c32 },
2823 { 0x01, 0x0200 },
2824 { 0x00, 0x5554 },
2825 { 0x04, 0x4800 },
2826 { 0x04, 0x4000 },
2827 { 0x04, 0xf000 },
2828 { 0x03, 0xdf01 },
2829 { 0x02, 0xdf20 },
2830 { 0x01, 0x101a },
2831 { 0x00, 0xa0ff },
2832 { 0x04, 0xf800 },
2833 { 0x04, 0xf000 },
2834 { 0x1f, 0x0000 },
2835
2836 { 0x1f, 0x0007 },
2837 { 0x1e, 0x0023 },
2838 { 0x16, 0x0000 },
2839 { 0x1f, 0x0000 }
2840 };
2841
4da19633 2842 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2843}
2844
e6de30d6 2845static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2846{
2847 static const struct phy_reg phy_reg_init[] = {
2848 { 0x1f, 0x0001 },
2849 { 0x17, 0x0cc0 },
2850
2851 { 0x1f, 0x0007 },
2852 { 0x1e, 0x002d },
2853 { 0x18, 0x0040 },
2854 { 0x1f, 0x0000 }
2855 };
2856
2857 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2858 rtl_patchphy(tp, 0x0d, 1 << 5);
2859}
2860
70090424 2861static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2862{
2863 static const struct phy_reg phy_reg_init[] = {
2864 /* Enable Delay cap */
2865 { 0x1f, 0x0005 },
2866 { 0x05, 0x8b80 },
2867 { 0x06, 0xc896 },
2868 { 0x1f, 0x0000 },
2869
2870 /* Channel estimation fine tune */
2871 { 0x1f, 0x0001 },
2872 { 0x0b, 0x6c20 },
2873 { 0x07, 0x2872 },
2874 { 0x1c, 0xefff },
2875 { 0x1f, 0x0003 },
2876 { 0x14, 0x6420 },
2877 { 0x1f, 0x0000 },
2878
2879 /* Update PFM & 10M TX idle timer */
2880 { 0x1f, 0x0007 },
2881 { 0x1e, 0x002f },
2882 { 0x15, 0x1919 },
2883 { 0x1f, 0x0000 },
2884
2885 { 0x1f, 0x0007 },
2886 { 0x1e, 0x00ac },
2887 { 0x18, 0x0006 },
2888 { 0x1f, 0x0000 }
2889 };
2890
15ecd039
FR		 2891 rtl_apply_firmware(tp);
2892
01dc7fec 2893 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2894
2895 /* DCO enable for 10M IDLE Power */
2896 rtl_writephy(tp, 0x1f, 0x0007);
2897 rtl_writephy(tp, 0x1e, 0x0023);
2898 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2899 rtl_writephy(tp, 0x1f, 0x0000);
2900
2901 /* For impedance matching */
2902 rtl_writephy(tp, 0x1f, 0x0002);
2903 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2904 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2905
2906 /* PHY auto speed down */
2907 rtl_writephy(tp, 0x1f, 0x0007);
2908 rtl_writephy(tp, 0x1e, 0x002d);
2909 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2910 rtl_writephy(tp, 0x1f, 0x0000);
2911 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2912
2913 rtl_writephy(tp, 0x1f, 0x0005);
2914 rtl_writephy(tp, 0x05, 0x8b86);
2915 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2916 rtl_writephy(tp, 0x1f, 0x0000);
2917
2918 rtl_writephy(tp, 0x1f, 0x0005);
2919 rtl_writephy(tp, 0x05, 0x8b85);
2920 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2921 rtl_writephy(tp, 0x1f, 0x0007);
2922 rtl_writephy(tp, 0x1e, 0x0020);
2923 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2924 rtl_writephy(tp, 0x1f, 0x0006);
2925 rtl_writephy(tp, 0x00, 0x5a00);
2926 rtl_writephy(tp, 0x1f, 0x0000);
2927 rtl_writephy(tp, 0x0d, 0x0007);
2928 rtl_writephy(tp, 0x0e, 0x003c);
2929 rtl_writephy(tp, 0x0d, 0x4007);
2930 rtl_writephy(tp, 0x0e, 0x0000);
2931 rtl_writephy(tp, 0x0d, 0x0000);
2932}
2933
70090424
HW		 2934static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2935{
2936 static const struct phy_reg phy_reg_init[] = {
2937 /* Enable Delay cap */
2938 { 0x1f, 0x0004 },
2939 { 0x1f, 0x0007 },
2940 { 0x1e, 0x00ac },
2941 { 0x18, 0x0006 },
2942 { 0x1f, 0x0002 },
2943 { 0x1f, 0x0000 },
2944 { 0x1f, 0x0000 },
2945
2946 /* Channel estimation fine tune */
2947 { 0x1f, 0x0003 },
2948 { 0x09, 0xa20f },
2949 { 0x1f, 0x0000 },
2950 { 0x1f, 0x0000 },
2951
2952 /* Green Setting */
2953 { 0x1f, 0x0005 },
2954 { 0x05, 0x8b5b },
2955 { 0x06, 0x9222 },
2956 { 0x05, 0x8b6d },
2957 { 0x06, 0x8000 },
2958 { 0x05, 0x8b76 },
2959 { 0x06, 0x8000 },
2960 { 0x1f, 0x0000 }
2961 };
2962
2963 rtl_apply_firmware(tp);
2964
2965 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2966
2967 /* For 4-corner performance improve */
2968 rtl_writephy(tp, 0x1f, 0x0005);
2969 rtl_writephy(tp, 0x05, 0x8b80);
2970 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2971 rtl_writephy(tp, 0x1f, 0x0000);
2972
2973 /* PHY auto speed down */
2974 rtl_writephy(tp, 0x1f, 0x0004);
2975 rtl_writephy(tp, 0x1f, 0x0007);
2976 rtl_writephy(tp, 0x1e, 0x002d);
2977 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2978 rtl_writephy(tp, 0x1f, 0x0002);
2979 rtl_writephy(tp, 0x1f, 0x0000);
2980 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2981
2982 /* improve 10M EEE waveform */
2983 rtl_writephy(tp, 0x1f, 0x0005);
2984 rtl_writephy(tp, 0x05, 0x8b86);
2985 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2986 rtl_writephy(tp, 0x1f, 0x0000);
2987
2988 /* Improve 2-pair detection performance */
2989 rtl_writephy(tp, 0x1f, 0x0005);
2990 rtl_writephy(tp, 0x05, 0x8b85);
2991 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2992 rtl_writephy(tp, 0x1f, 0x0000);
2993
2994 /* EEE setting */
2995 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2996 ERIAR_EXGMAC);
2997 rtl_writephy(tp, 0x1f, 0x0005);
2998 rtl_writephy(tp, 0x05, 0x8b85);
2999 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3000 rtl_writephy(tp, 0x1f, 0x0004);
3001 rtl_writephy(tp, 0x1f, 0x0007);
3002 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3003 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3004 rtl_writephy(tp, 0x1f, 0x0002);
3005 rtl_writephy(tp, 0x1f, 0x0000);
3006 rtl_writephy(tp, 0x0d, 0x0007);
3007 rtl_writephy(tp, 0x0e, 0x003c);
3008 rtl_writephy(tp, 0x0d, 0x4007);
3009 rtl_writephy(tp, 0x0e, 0x0000);
3010 rtl_writephy(tp, 0x0d, 0x0000);
3011
3012 /* Green feature */
3013 rtl_writephy(tp, 0x1f, 0x0003);
3014 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3015 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3016 rtl_writephy(tp, 0x1f, 0x0000);
3017}
3018
c2218925
HW		 3019static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3020{
3021 static const struct phy_reg phy_reg_init[] = {
3022 /* Channel estimation fine tune */
3023 { 0x1f, 0x0003 },
3024 { 0x09, 0xa20f },
3025 { 0x1f, 0x0000 },
3026
3027 /* Modify green table for giga & fnet */
3028 { 0x1f, 0x0005 },
3029 { 0x05, 0x8b55 },
3030 { 0x06, 0x0000 },
3031 { 0x05, 0x8b5e },
3032 { 0x06, 0x0000 },
3033 { 0x05, 0x8b67 },
3034 { 0x06, 0x0000 },
3035 { 0x05, 0x8b70 },
3036 { 0x06, 0x0000 },
3037 { 0x1f, 0x0000 },
3038 { 0x1f, 0x0007 },
3039 { 0x1e, 0x0078 },
3040 { 0x17, 0x0000 },
3041 { 0x19, 0x00fb },
3042 { 0x1f, 0x0000 },
3043
3044 /* Modify green table for 10M */
3045 { 0x1f, 0x0005 },
3046 { 0x05, 0x8b79 },
3047 { 0x06, 0xaa00 },
3048 { 0x1f, 0x0000 },
3049
3050 /* Disable hiimpedance detection (RTCT) */
3051 { 0x1f, 0x0003 },
3052 { 0x01, 0x328a },
3053 { 0x1f, 0x0000 }
3054 };
3055
3056 rtl_apply_firmware(tp);
3057
3058 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3059
3060 /* For 4-corner performance improve */
3061 rtl_writephy(tp, 0x1f, 0x0005);
3062 rtl_writephy(tp, 0x05, 0x8b80);
3063 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3064 rtl_writephy(tp, 0x1f, 0x0000);
3065
3066 /* PHY auto speed down */
3067 rtl_writephy(tp, 0x1f, 0x0007);
3068 rtl_writephy(tp, 0x1e, 0x002d);
3069 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3070 rtl_writephy(tp, 0x1f, 0x0000);
3071 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3072
3073 /* Improve 10M EEE waveform */
3074 rtl_writephy(tp, 0x1f, 0x0005);
3075 rtl_writephy(tp, 0x05, 0x8b86);
3076 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3077 rtl_writephy(tp, 0x1f, 0x0000);
3078
3079 /* Improve 2-pair detection performance */
3080 rtl_writephy(tp, 0x1f, 0x0005);
3081 rtl_writephy(tp, 0x05, 0x8b85);
3082 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3083 rtl_writephy(tp, 0x1f, 0x0000);
3084}
3085
3086static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3087{
3088 rtl_apply_firmware(tp);
3089
3090 /* For 4-corner performance improve */
3091 rtl_writephy(tp, 0x1f, 0x0005);
3092 rtl_writephy(tp, 0x05, 0x8b80);
3093 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3094 rtl_writephy(tp, 0x1f, 0x0000);
3095
3096 /* PHY auto speed down */
3097 rtl_writephy(tp, 0x1f, 0x0007);
3098 rtl_writephy(tp, 0x1e, 0x002d);
3099 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3100 rtl_writephy(tp, 0x1f, 0x0000);
3101 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3102
3103 /* Improve 10M EEE waveform */
3104 rtl_writephy(tp, 0x1f, 0x0005);
3105 rtl_writephy(tp, 0x05, 0x8b86);
3106 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3107 rtl_writephy(tp, 0x1f, 0x0000);
3108}
3109
4da19633 3110static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3111{
350f7596 3112 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3113 { 0x1f, 0x0003 },
3114 { 0x08, 0x441d },
3115 { 0x01, 0x9100 },
3116 { 0x1f, 0x0000 }
3117 };
3118
4da19633 3119 rtl_writephy(tp, 0x1f, 0x0000);
3120 rtl_patchphy(tp, 0x11, 1 << 12);
3121 rtl_patchphy(tp, 0x19, 1 << 13);
3122 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3123
4da19633 3124 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3125}
3126
5a5e4443
HW		 3127static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3128{
3129 static const struct phy_reg phy_reg_init[] = {
3130 { 0x1f, 0x0005 },
3131 { 0x1a, 0x0000 },
3132 { 0x1f, 0x0000 },
3133
3134 { 0x1f, 0x0004 },
3135 { 0x1c, 0x0000 },
3136 { 0x1f, 0x0000 },
3137
3138 { 0x1f, 0x0001 },
3139 { 0x15, 0x7701 },
3140 { 0x1f, 0x0000 }
3141 };
3142
3143 /* Disable ALDPS before ram code */
3144 rtl_writephy(tp, 0x1f, 0x0000);
3145 rtl_writephy(tp, 0x18, 0x0310);
3146 msleep(100);
3147
953a12cc 3148 rtl_apply_firmware(tp);
5a5e4443
HW		 3149
3150 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3151}
3152
5615d9f1
FR		 3153static void rtl_hw_phy_config(struct net_device *dev)
3154{
3155 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3156
3157 rtl8169_print_mac_version(tp);
3158
3159 switch (tp->mac_version) {
3160 case RTL_GIGA_MAC_VER_01:
3161 break;
3162 case RTL_GIGA_MAC_VER_02:
3163 case RTL_GIGA_MAC_VER_03:
4da19633 3164 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3165 break;
3166 case RTL_GIGA_MAC_VER_04:
4da19633 3167 rtl8169sb_hw_phy_config(tp);
5615d9f1 3168 break;
2e955856 3169 case RTL_GIGA_MAC_VER_05:
4da19633 3170 rtl8169scd_hw_phy_config(tp);
2e955856 3171 break;
8c7006aa 3172 case RTL_GIGA_MAC_VER_06:
4da19633 3173 rtl8169sce_hw_phy_config(tp);
8c7006aa 3174 break;
2857ffb7
FR		 3175 case RTL_GIGA_MAC_VER_07:
3176 case RTL_GIGA_MAC_VER_08:
3177 case RTL_GIGA_MAC_VER_09:
4da19633 3178 rtl8102e_hw_phy_config(tp);
2857ffb7 3179 break;
236b8082 3180 case RTL_GIGA_MAC_VER_11:
4da19633 3181 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3182 break;
3183 case RTL_GIGA_MAC_VER_12:
4da19633 3184 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3185 break;
3186 case RTL_GIGA_MAC_VER_17:
4da19633 3187 rtl8168bef_hw_phy_config(tp);
236b8082 3188 break;
867763c1 3189 case RTL_GIGA_MAC_VER_18:
4da19633 3190 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3191 break;
3192 case RTL_GIGA_MAC_VER_19:
4da19633 3193 rtl8168c_1_hw_phy_config(tp);
867763c1 3194 break;
7da97ec9 3195 case RTL_GIGA_MAC_VER_20:
4da19633 3196 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3197 break;
197ff761 3198 case RTL_GIGA_MAC_VER_21:
4da19633 3199 rtl8168c_3_hw_phy_config(tp);
197ff761 3200 break;
6fb07058 3201 case RTL_GIGA_MAC_VER_22:
4da19633 3202 rtl8168c_4_hw_phy_config(tp);
6fb07058 3203 break;
ef3386f0 3204 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3205 case RTL_GIGA_MAC_VER_24:
4da19633 3206 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3207 break;
5b538df9 3208 case RTL_GIGA_MAC_VER_25:
bca03d5f 3209 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3210 break;
3211 case RTL_GIGA_MAC_VER_26:
bca03d5f 3212 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3213 break;
3214 case RTL_GIGA_MAC_VER_27:
4da19633 3215 rtl8168d_3_hw_phy_config(tp);
5b538df9 3216 break;
e6de30d6 3217 case RTL_GIGA_MAC_VER_28:
3218 rtl8168d_4_hw_phy_config(tp);
3219 break;
5a5e4443
HW		 3220 case RTL_GIGA_MAC_VER_29:
3221 case RTL_GIGA_MAC_VER_30:
3222 rtl8105e_hw_phy_config(tp);
3223 break;
cecb5fd7
FR		 3224 case RTL_GIGA_MAC_VER_31:
3225 /* None. */
3226 break;
01dc7fec 3227 case RTL_GIGA_MAC_VER_32:
01dc7fec 3228 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3229 rtl8168e_1_hw_phy_config(tp);
3230 break;
3231 case RTL_GIGA_MAC_VER_34:
3232 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3233 break;
c2218925
HW		 3234 case RTL_GIGA_MAC_VER_35:
3235 rtl8168f_1_hw_phy_config(tp);
3236 break;
3237 case RTL_GIGA_MAC_VER_36:
3238 rtl8168f_2_hw_phy_config(tp);
3239 break;
ef3386f0 3240
5615d9f1
FR		 3241 default:
3242 break;
3243 }
3244}
3245
da78dbff 3246static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3247{
1da177e4
LT		 3248 struct timer_list *timer = &tp->timer;
3249 void __iomem *ioaddr = tp->mmio_addr;
3250 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3251
bcf0bf90 3252 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3253
4da19633 3254 if (tp->phy_reset_pending(tp)) {
5b0384f4 3255 /*
1da177e4
LT		 3256 * A busy loop could burn quite a few cycles on nowadays CPU.
3257 * Let's delay the execution of the timer for a few ticks.
3258 */
3259 timeout = HZ/10;
3260 goto out_mod_timer;
3261 }
3262
3263 if (tp->link_ok(ioaddr))
da78dbff 3264 return;
1da177e4 3265
da78dbff 3266 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3267
4da19633 3268 tp->phy_reset_enable(tp);
1da177e4
LT		 3269
3270out_mod_timer:
3271 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3272}
3273
3274static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3275{
3276 spin_lock(&tp->lock);
3277 if (!test_and_set_bit(flag, tp->wk.flags))
3278 schedule_work(&tp->wk.work);
3279 spin_unlock(&tp->lock);
3280}
3281
3282static void rtl_schedule_task_bh(struct rtl8169_private *tp, enum rtl_flag flag)
3283{
3284 local_bh_disable();
3285 rtl_schedule_task(tp, flag);
3286 local_bh_enable();
3287}
3288
3289static void rtl8169_phy_timer(unsigned long __opaque)
3290{
3291 struct net_device *dev = (struct net_device *)__opaque;
3292 struct rtl8169_private *tp = netdev_priv(dev);
3293
3294 rtl_schedule_task_bh(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3295}
3296
1da177e4 3297#ifdef CONFIG_NET_POLL_CONTROLLER
1da177e4
LT		 3298static void rtl8169_netpoll(struct net_device *dev)
3299{
3300 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3301
da78dbff 3302 rtl8169_interrupt(tp->pci_dev->irq, dev);
1da177e4
LT		 3303}
3304#endif
3305
3306static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3307 void __iomem *ioaddr)
3308{
3309 iounmap(ioaddr);
3310 pci_release_regions(pdev);
87aeec76 3311 pci_clear_mwi(pdev);
1da177e4
LT		 3312 pci_disable_device(pdev);
3313 free_netdev(dev);
3314}
3315
bf793295
FR		 3316static void rtl8169_phy_reset(struct net_device *dev,
3317 struct rtl8169_private *tp)
3318{
07d3f51f 3319 unsigned int i;
bf793295 3320
4da19633 3321 tp->phy_reset_enable(tp);
bf793295 3322 for (i = 0; i < 100; i++) {
4da19633 3323 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3324 return;
3325 msleep(1);
3326 }
bf82c189 3327 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3328}
3329
2544bfc0
FR		 3330static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3331{
3332 void __iomem *ioaddr = tp->mmio_addr;
3333
3334 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3335 (RTL_R8(PHYstatus) & TBI_Enable);
3336}
3337
4ff96fa6
FR		 3338static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3339{
3340 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3341
5615d9f1 3342 rtl_hw_phy_config(dev);
4ff96fa6 3343
77332894
MS		 3344 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3345 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3346 RTL_W8(0x82, 0x01);
3347 }
4ff96fa6 3348
6dccd16b
FR		 3349 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3350
3351 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3352 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3353
bcf0bf90 3354 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3355 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3356 RTL_W8(0x82, 0x01);
3357 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3358 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3359 }
3360
bf793295
FR		 3361 rtl8169_phy_reset(dev, tp);
3362
54405cde 3363 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3364 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3365 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3366 (tp->mii.supports_gmii ?
3367 ADVERTISED_1000baseT_Half |
3368 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3369
2544bfc0 3370 if (rtl_tbi_enabled(tp))
bf82c189 3371 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3372}
3373
773d2021
FR		 3374static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3375{
3376 void __iomem *ioaddr = tp->mmio_addr;
3377 u32 high;
3378 u32 low;
3379
3380 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3381 high = addr[4] | (addr[5] << 8);
3382
da78dbff 3383 rtl_lock_work(tp);
773d2021
FR		 3384
3385 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3386
773d2021 3387 RTL_W32(MAC4, high);
908ba2bf 3388 RTL_R32(MAC4);
3389
78f1cd02 3390 RTL_W32(MAC0, low);
908ba2bf 3391 RTL_R32(MAC0);
3392
c28aa385 3393 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3394 const struct exgmac_reg e[] = {
3395 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3396 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3397 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3398 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3399 low >> 16 },
3400 };
3401
3402 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3403 }
3404
773d2021
FR		 3405 RTL_W8(Cfg9346, Cfg9346_Lock);
3406
da78dbff 3407 rtl_unlock_work(tp);
773d2021
FR		 3408}
3409
3410static int rtl_set_mac_address(struct net_device *dev, void *p)
3411{
3412 struct rtl8169_private *tp = netdev_priv(dev);
3413 struct sockaddr *addr = p;
3414
3415 if (!is_valid_ether_addr(addr->sa_data))
3416 return -EADDRNOTAVAIL;
3417
3418 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3419
3420 rtl_rar_set(tp, dev->dev_addr);
3421
3422 return 0;
3423}
3424
5f787a1a
FR		 3425static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3426{
3427 struct rtl8169_private *tp = netdev_priv(dev);
3428 struct mii_ioctl_data *data = if_mii(ifr);
3429
8b4ab28d
FR		 3430 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3431}
5f787a1a 3432
cecb5fd7
FR		 3433static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3434 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3435{
5f787a1a
FR		 3436 switch (cmd) {
3437 case SIOCGMIIPHY:
3438 data->phy_id = 32; /* Internal PHY */
3439 return 0;
3440
3441 case SIOCGMIIREG:
4da19633 3442 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3443 return 0;
3444
3445 case SIOCSMIIREG:
4da19633 3446 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3447 return 0;
3448 }
3449 return -EOPNOTSUPP;
3450}
3451
8b4ab28d
FR		 3452static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3453{
3454 return -EOPNOTSUPP;
3455}
3456
0e485150
FR		 3457static const struct rtl_cfg_info {
3458 void (*hw_start)(struct net_device *);
3459 unsigned int region;
3460 unsigned int align;
da78dbff 3461 u16 event_slow;
ccdffb9a 3462 unsigned features;
f21b75e9 3463 u8 default_ver;
0e485150
FR		 3464} rtl_cfg_infos [] = {
3465 [RTL_CFG_0] = {
3466 .hw_start = rtl_hw_start_8169,
3467 .region = 1,
e9f63f30 3468 .align = 0,
da78dbff 3469 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
f21b75e9
JD		 3470 .features = RTL_FEATURE_GMII,
3471 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3472 },
3473 [RTL_CFG_1] = {
3474 .hw_start = rtl_hw_start_8168,
3475 .region = 2,
3476 .align = 8,
da78dbff 3477 .event_slow = SYSErr | LinkChg | RxOverflow,
f21b75e9
JD		 3478 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3479 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3480 },
3481 [RTL_CFG_2] = {
3482 .hw_start = rtl_hw_start_8101,
3483 .region = 2,
3484 .align = 8,
da78dbff
FR		 3485 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
3486 PCSTimeout,
f21b75e9
JD		 3487 .features = RTL_FEATURE_MSI,
3488 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3489 }
3490};
3491
fbac58fc 3492/* Cfg9346_Unlock assumed. */
2ca6cf06 3493static unsigned rtl_try_msi(struct rtl8169_private *tp,
fbac58fc
FR		 3494 const struct rtl_cfg_info *cfg)
3495{
2ca6cf06 3496 void __iomem *ioaddr = tp->mmio_addr;
fbac58fc
FR		 3497 unsigned msi = 0;
3498 u8 cfg2;
3499
3500 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3501 if (cfg->features & RTL_FEATURE_MSI) {
2ca6cf06 3502 if (pci_enable_msi(tp->pci_dev)) {
3503 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
fbac58fc
FR		 3504 } else {
3505 cfg2 |= MSIEnable;
3506 msi = RTL_FEATURE_MSI;
3507 }
3508 }
2ca6cf06 3509 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3510 RTL_W8(Config2, cfg2);
fbac58fc
FR		 3511 return msi;
3512}
3513
3514static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3515{
3516 if (tp->features & RTL_FEATURE_MSI) {
3517 pci_disable_msi(pdev);
3518 tp->features &= ~RTL_FEATURE_MSI;
3519 }
3520}
3521
8b4ab28d
FR		 3522static const struct net_device_ops rtl8169_netdev_ops = {
3523 .ndo_open = rtl8169_open,
3524 .ndo_stop = rtl8169_close,
3525 .ndo_get_stats = rtl8169_get_stats,
00829823 3526 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3527 .ndo_tx_timeout = rtl8169_tx_timeout,
3528 .ndo_validate_addr = eth_validate_addr,
3529 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3530 .ndo_fix_features = rtl8169_fix_features,
3531 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3532 .ndo_set_mac_address = rtl_set_mac_address,
3533 .ndo_do_ioctl = rtl8169_ioctl,
afc4b13d 3534 .ndo_set_rx_mode = rtl_set_rx_mode,
8b4ab28d
FR		 3535#ifdef CONFIG_NET_POLL_CONTROLLER
3536 .ndo_poll_controller = rtl8169_netpoll,
3537#endif
3538
3539};
3540
c0e45c1c 3541static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3542{
3543 struct mdio_ops *ops = &tp->mdio_ops;
3544
3545 switch (tp->mac_version) {
3546 case RTL_GIGA_MAC_VER_27:
3547 ops->write = r8168dp_1_mdio_write;
3548 ops->read = r8168dp_1_mdio_read;
3549 break;
e6de30d6 3550 case RTL_GIGA_MAC_VER_28:
4804b3b3 3551 case RTL_GIGA_MAC_VER_31:
e6de30d6 3552 ops->write = r8168dp_2_mdio_write;
3553 ops->read = r8168dp_2_mdio_read;
3554 break;
c0e45c1c 3555 default:
3556 ops->write = r8169_mdio_write;
3557 ops->read = r8169_mdio_read;
3558 break;
3559 }
3560}
3561
649b3b8c 3562static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3563{
3564 void __iomem *ioaddr = tp->mmio_addr;
3565
3566 switch (tp->mac_version) {
3567 case RTL_GIGA_MAC_VER_29:
3568 case RTL_GIGA_MAC_VER_30:
3569 case RTL_GIGA_MAC_VER_32:
3570 case RTL_GIGA_MAC_VER_33:
3571 case RTL_GIGA_MAC_VER_34:
3572 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3573 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3574 break;
3575 default:
3576 break;
3577 }
3578}
3579
3580static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3581{
3582 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3583 return false;
3584
3585 rtl_writephy(tp, 0x1f, 0x0000);
3586 rtl_writephy(tp, MII_BMCR, 0x0000);
3587
3588 rtl_wol_suspend_quirk(tp);
3589
3590 return true;
3591}
3592
065c27c1 3593static void r810x_phy_power_down(struct rtl8169_private *tp)
3594{
3595 rtl_writephy(tp, 0x1f, 0x0000);
3596 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3597}
3598
3599static void r810x_phy_power_up(struct rtl8169_private *tp)
3600{
3601 rtl_writephy(tp, 0x1f, 0x0000);
3602 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3603}
3604
3605static void r810x_pll_power_down(struct rtl8169_private *tp)
3606{
649b3b8c 3607 if (rtl_wol_pll_power_down(tp))
065c27c1 3608 return;
065c27c1 3609
3610 r810x_phy_power_down(tp);
3611}
3612
3613static void r810x_pll_power_up(struct rtl8169_private *tp)
3614{
3615 r810x_phy_power_up(tp);
3616}
3617
3618static void r8168_phy_power_up(struct rtl8169_private *tp)
3619{
3620 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3621 switch (tp->mac_version) {
3622 case RTL_GIGA_MAC_VER_11:
3623 case RTL_GIGA_MAC_VER_12:
3624 case RTL_GIGA_MAC_VER_17:
3625 case RTL_GIGA_MAC_VER_18:
3626 case RTL_GIGA_MAC_VER_19:
3627 case RTL_GIGA_MAC_VER_20:
3628 case RTL_GIGA_MAC_VER_21:
3629 case RTL_GIGA_MAC_VER_22:
3630 case RTL_GIGA_MAC_VER_23:
3631 case RTL_GIGA_MAC_VER_24:
3632 case RTL_GIGA_MAC_VER_25:
3633 case RTL_GIGA_MAC_VER_26:
3634 case RTL_GIGA_MAC_VER_27:
3635 case RTL_GIGA_MAC_VER_28:
3636 case RTL_GIGA_MAC_VER_31:
3637 rtl_writephy(tp, 0x0e, 0x0000);
3638 break;
3639 default:
3640 break;
3641 }
065c27c1 3642 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3643}
3644
3645static void r8168_phy_power_down(struct rtl8169_private *tp)
3646{
3647 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3648 switch (tp->mac_version) {
3649 case RTL_GIGA_MAC_VER_32:
3650 case RTL_GIGA_MAC_VER_33:
3651 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3652 break;
3653
3654 case RTL_GIGA_MAC_VER_11:
3655 case RTL_GIGA_MAC_VER_12:
3656 case RTL_GIGA_MAC_VER_17:
3657 case RTL_GIGA_MAC_VER_18:
3658 case RTL_GIGA_MAC_VER_19:
3659 case RTL_GIGA_MAC_VER_20:
3660 case RTL_GIGA_MAC_VER_21:
3661 case RTL_GIGA_MAC_VER_22:
3662 case RTL_GIGA_MAC_VER_23:
3663 case RTL_GIGA_MAC_VER_24:
3664 case RTL_GIGA_MAC_VER_25:
3665 case RTL_GIGA_MAC_VER_26:
3666 case RTL_GIGA_MAC_VER_27:
3667 case RTL_GIGA_MAC_VER_28:
3668 case RTL_GIGA_MAC_VER_31:
3669 rtl_writephy(tp, 0x0e, 0x0200);
3670 default:
3671 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3672 break;
3673 }
065c27c1 3674}
3675
3676static void r8168_pll_power_down(struct rtl8169_private *tp)
3677{
3678 void __iomem *ioaddr = tp->mmio_addr;
3679
cecb5fd7
FR		 3680 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3681 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3682 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3683 r8168dp_check_dash(tp)) {
065c27c1 3684 return;
5d2e1957 3685 }
065c27c1 3686
cecb5fd7
FR		 3687 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3688 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3689 (RTL_R16(CPlusCmd) & ASF)) {
3690 return;
3691 }
3692
01dc7fec 3693 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3694 tp->mac_version == RTL_GIGA_MAC_VER_33)
3695 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3696
649b3b8c 3697 if (rtl_wol_pll_power_down(tp))
065c27c1 3698 return;
065c27c1 3699
3700 r8168_phy_power_down(tp);
3701
3702 switch (tp->mac_version) {
3703 case RTL_GIGA_MAC_VER_25:
3704 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3705 case RTL_GIGA_MAC_VER_27:
3706 case RTL_GIGA_MAC_VER_28:
4804b3b3 3707 case RTL_GIGA_MAC_VER_31:
01dc7fec 3708 case RTL_GIGA_MAC_VER_32:
3709 case RTL_GIGA_MAC_VER_33:
065c27c1 3710 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3711 break;
3712 }
3713}
3714
3715static void r8168_pll_power_up(struct rtl8169_private *tp)
3716{
3717 void __iomem *ioaddr = tp->mmio_addr;
3718
cecb5fd7
FR		 3719 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3720 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3721 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3722 r8168dp_check_dash(tp)) {
065c27c1 3723 return;
5d2e1957 3724 }
065c27c1 3725
3726 switch (tp->mac_version) {
3727 case RTL_GIGA_MAC_VER_25:
3728 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3729 case RTL_GIGA_MAC_VER_27:
3730 case RTL_GIGA_MAC_VER_28:
4804b3b3 3731 case RTL_GIGA_MAC_VER_31:
01dc7fec 3732 case RTL_GIGA_MAC_VER_32:
3733 case RTL_GIGA_MAC_VER_33:
065c27c1 3734 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3735 break;
3736 }
3737
3738 r8168_phy_power_up(tp);
3739}
3740
d58d46b5
FR		 3741static void rtl_generic_op(struct rtl8169_private *tp,
3742 void (*op)(struct rtl8169_private *))
065c27c1 3743{
3744 if (op)
3745 op(tp);
3746}
3747
3748static void rtl_pll_power_down(struct rtl8169_private *tp)
3749{
d58d46b5 3750 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 3751}
3752
3753static void rtl_pll_power_up(struct rtl8169_private *tp)
3754{
d58d46b5 3755 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 3756}
3757
3758static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3759{
3760 struct pll_power_ops *ops = &tp->pll_power_ops;
3761
3762 switch (tp->mac_version) {
3763 case RTL_GIGA_MAC_VER_07:
3764 case RTL_GIGA_MAC_VER_08:
3765 case RTL_GIGA_MAC_VER_09:
3766 case RTL_GIGA_MAC_VER_10:
3767 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3768 case RTL_GIGA_MAC_VER_29:
3769 case RTL_GIGA_MAC_VER_30:
065c27c1 3770 ops->down = r810x_pll_power_down;
3771 ops->up = r810x_pll_power_up;
3772 break;
3773
3774 case RTL_GIGA_MAC_VER_11:
3775 case RTL_GIGA_MAC_VER_12:
3776 case RTL_GIGA_MAC_VER_17:
3777 case RTL_GIGA_MAC_VER_18:
3778 case RTL_GIGA_MAC_VER_19:
3779 case RTL_GIGA_MAC_VER_20:
3780 case RTL_GIGA_MAC_VER_21:
3781 case RTL_GIGA_MAC_VER_22:
3782 case RTL_GIGA_MAC_VER_23:
3783 case RTL_GIGA_MAC_VER_24:
3784 case RTL_GIGA_MAC_VER_25:
3785 case RTL_GIGA_MAC_VER_26:
3786 case RTL_GIGA_MAC_VER_27:
e6de30d6 3787 case RTL_GIGA_MAC_VER_28:
4804b3b3 3788 case RTL_GIGA_MAC_VER_31:
01dc7fec 3789 case RTL_GIGA_MAC_VER_32:
3790 case RTL_GIGA_MAC_VER_33:
70090424 3791 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 3792 case RTL_GIGA_MAC_VER_35:
3793 case RTL_GIGA_MAC_VER_36:
065c27c1 3794 ops->down = r8168_pll_power_down;
3795 ops->up = r8168_pll_power_up;
3796 break;
3797
3798 default:
3799 ops->down = NULL;
3800 ops->up = NULL;
3801 break;
3802 }
3803}
3804
e542a226
HW		 3805static void rtl_init_rxcfg(struct rtl8169_private *tp)
3806{
3807 void __iomem *ioaddr = tp->mmio_addr;
3808
3809 switch (tp->mac_version) {
3810 case RTL_GIGA_MAC_VER_01:
3811 case RTL_GIGA_MAC_VER_02:
3812 case RTL_GIGA_MAC_VER_03:
3813 case RTL_GIGA_MAC_VER_04:
3814 case RTL_GIGA_MAC_VER_05:
3815 case RTL_GIGA_MAC_VER_06:
3816 case RTL_GIGA_MAC_VER_10:
3817 case RTL_GIGA_MAC_VER_11:
3818 case RTL_GIGA_MAC_VER_12:
3819 case RTL_GIGA_MAC_VER_13:
3820 case RTL_GIGA_MAC_VER_14:
3821 case RTL_GIGA_MAC_VER_15:
3822 case RTL_GIGA_MAC_VER_16:
3823 case RTL_GIGA_MAC_VER_17:
3824 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3825 break;
3826 case RTL_GIGA_MAC_VER_18:
3827 case RTL_GIGA_MAC_VER_19:
3828 case RTL_GIGA_MAC_VER_20:
3829 case RTL_GIGA_MAC_VER_21:
3830 case RTL_GIGA_MAC_VER_22:
3831 case RTL_GIGA_MAC_VER_23:
3832 case RTL_GIGA_MAC_VER_24:
3833 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3834 break;
3835 default:
3836 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3837 break;
3838 }
3839}
3840
92fc43b4
HW		 3841static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3842{
3843 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3844}
3845
d58d46b5
FR		 3846static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3847{
3848 rtl_generic_op(tp, tp->jumbo_ops.enable);
3849}
3850
3851static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3852{
3853 rtl_generic_op(tp, tp->jumbo_ops.disable);
3854}
3855
3856static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3857{
3858 void __iomem *ioaddr = tp->mmio_addr;
3859
3860 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3861 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3862 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3863}
3864
3865static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3866{
3867 void __iomem *ioaddr = tp->mmio_addr;
3868
3869 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3870 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3871 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3872}
3873
3874static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3875{
3876 void __iomem *ioaddr = tp->mmio_addr;
3877
3878 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3879}
3880
3881static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3882{
3883 void __iomem *ioaddr = tp->mmio_addr;
3884
3885 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3886}
3887
3888static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3889{
3890 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3891
3892 RTL_W8(MaxTxPacketSize, 0x3f);
3893 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3894 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 3895 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3896}
3897
3898static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3899{
3900 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3901
3902 RTL_W8(MaxTxPacketSize, 0x0c);
3903 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3904 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 3905 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3906}
3907
3908static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3909{
3910 rtl_tx_performance_tweak(tp->pci_dev,
3911 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3912}
3913
3914static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3915{
3916 rtl_tx_performance_tweak(tp->pci_dev,
3917 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3918}
3919
3920static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3921{
3922 void __iomem *ioaddr = tp->mmio_addr;
3923
3924 r8168b_0_hw_jumbo_enable(tp);
3925
3926 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3927}
3928
3929static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3930{
3931 void __iomem *ioaddr = tp->mmio_addr;
3932
3933 r8168b_0_hw_jumbo_disable(tp);
3934
3935 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3936}
3937
3938static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3939{
3940 struct jumbo_ops *ops = &tp->jumbo_ops;
3941
3942 switch (tp->mac_version) {
3943 case RTL_GIGA_MAC_VER_11:
3944 ops->disable = r8168b_0_hw_jumbo_disable;
3945 ops->enable = r8168b_0_hw_jumbo_enable;
3946 break;
3947 case RTL_GIGA_MAC_VER_12:
3948 case RTL_GIGA_MAC_VER_17:
3949 ops->disable = r8168b_1_hw_jumbo_disable;
3950 ops->enable = r8168b_1_hw_jumbo_enable;
3951 break;
3952 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3953 case RTL_GIGA_MAC_VER_19:
3954 case RTL_GIGA_MAC_VER_20:
3955 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3956 case RTL_GIGA_MAC_VER_22:
3957 case RTL_GIGA_MAC_VER_23:
3958 case RTL_GIGA_MAC_VER_24:
3959 case RTL_GIGA_MAC_VER_25:
3960 case RTL_GIGA_MAC_VER_26:
3961 ops->disable = r8168c_hw_jumbo_disable;
3962 ops->enable = r8168c_hw_jumbo_enable;
3963 break;
3964 case RTL_GIGA_MAC_VER_27:
3965 case RTL_GIGA_MAC_VER_28:
3966 ops->disable = r8168dp_hw_jumbo_disable;
3967 ops->enable = r8168dp_hw_jumbo_enable;
3968 break;
3969 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3970 case RTL_GIGA_MAC_VER_32:
3971 case RTL_GIGA_MAC_VER_33:
3972 case RTL_GIGA_MAC_VER_34:
3973 ops->disable = r8168e_hw_jumbo_disable;
3974 ops->enable = r8168e_hw_jumbo_enable;
3975 break;
3976
3977 /*
3978 * No action needed for jumbo frames with 8169.
3979 * No jumbo for 810x at all.
3980 */
3981 default:
3982 ops->disable = NULL;
3983 ops->enable = NULL;
3984 break;
3985 }
3986}
3987
6f43adc8
FR		 3988static void rtl_hw_reset(struct rtl8169_private *tp)
3989{
3990 void __iomem *ioaddr = tp->mmio_addr;
3991 int i;
3992
3993 /* Soft reset the chip. */
3994 RTL_W8(ChipCmd, CmdReset);
3995
3996 /* Check that the chip has finished the reset. */
3997 for (i = 0; i < 100; i++) {
3998 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3999 break;
92fc43b4 4000 udelay(100);
6f43adc8
FR		 4001 }
4002}
4003
1da177e4 4004static int __devinit
4ff96fa6 4005rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 4006{
0e485150
FR		 4007 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
4008 const unsigned int region = cfg->region;
1da177e4 4009 struct rtl8169_private *tp;
ccdffb9a 4010 struct mii_if_info *mii;
4ff96fa6
FR		 4011 struct net_device *dev;
4012 void __iomem *ioaddr;
2b7b4318 4013 int chipset, i;
07d3f51f 4014 int rc;
1da177e4 4015
4ff96fa6
FR		 4016 if (netif_msg_drv(&debug)) {
4017 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
4018 MODULENAME, RTL8169_VERSION);
4019 }
1da177e4 4020
1da177e4 4021 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 4022 if (!dev) {
b57b7e5a 4023 if (netif_msg_drv(&debug))
9b91cf9d 4024 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 4025 rc = -ENOMEM;
4026 goto out;
1da177e4
LT		 4027 }
4028
1da177e4 4029 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 4030 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 4031 tp = netdev_priv(dev);
c4028958 4032 tp->dev = dev;
21e197f2 4033 tp->pci_dev = pdev;
b57b7e5a 4034 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 4035
ccdffb9a
FR		 4036 mii = &tp->mii;
4037 mii->dev = dev;
4038 mii->mdio_read = rtl_mdio_read;
4039 mii->mdio_write = rtl_mdio_write;
4040 mii->phy_id_mask = 0x1f;
4041 mii->reg_num_mask = 0x1f;
4042 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
4043
ba04c7c9
SG		 4044 /* disable ASPM completely as that cause random device stop working
4045 * problems as well as full system hangs for some PCIe devices users */
4046 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4047 PCIE_LINK_STATE_CLKPM);
4048
1da177e4
LT		 4049 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4050 rc = pci_enable_device(pdev);
b57b7e5a 4051 if (rc < 0) {
bf82c189 4052 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 4053 goto err_out_free_dev_1;
1da177e4
LT		 4054 }
4055
87aeec76 4056 if (pci_set_mwi(pdev) < 0)
4057 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 4058
1da177e4 4059 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 4060 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 4061 netif_err(tp, probe, dev,
4062 "region #%d not an MMIO resource, aborting\n",
4063 region);
1da177e4 4064 rc = -ENODEV;
87aeec76 4065 goto err_out_mwi_2;
1da177e4 4066 }
4ff96fa6 4067
1da177e4 4068 /* check for weird/broken PCI region reporting */
bcf0bf90 4069 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 4070 netif_err(tp, probe, dev,
4071 "Invalid PCI region size(s), aborting\n");
1da177e4 4072 rc = -ENODEV;
87aeec76 4073 goto err_out_mwi_2;
1da177e4
LT		 4074 }
4075
4076 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 4077 if (rc < 0) {
bf82c189 4078 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 4079 goto err_out_mwi_2;
1da177e4
LT		 4080 }
4081
d24e9aaf 4082 tp->cp_cmd = RxChkSum;
1da177e4
LT		 4083
4084 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 4085 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 4086 tp->cp_cmd |= PCIDAC;
4087 dev->features |= NETIF_F_HIGHDMA;
4088 } else {
284901a9 4089 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 4090 if (rc < 0) {
bf82c189 4091 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 4092 goto err_out_free_res_3;
1da177e4
LT		 4093 }
4094 }
4095
1da177e4 4096 /* ioremap MMIO region */
bcf0bf90 4097 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 4098 if (!ioaddr) {
bf82c189 4099 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 4100 rc = -EIO;
87aeec76 4101 goto err_out_free_res_3;
1da177e4 4102 }
6f43adc8 4103 tp->mmio_addr = ioaddr;
1da177e4 4104
e44daade
JM		 4105 if (!pci_is_pcie(pdev))
4106 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 4107
e542a226
HW		 4108 /* Identify chip attached to board */
4109 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4110
4111 rtl_init_rxcfg(tp);
4112
9085cdfa 4113 rtl_irq_disable(tp);
1da177e4 4114
6f43adc8 4115 rtl_hw_reset(tp);
1da177e4 4116
9085cdfa 4117 rtl_ack_events(tp, 0xffff);
d78ad8cb 4118
ca52efd5 4119 pci_set_master(pdev);
4120
7a8fc77b
FR		 4121 /*
4122 * Pretend we are using VLANs; This bypasses a nasty bug where
4123 * Interrupts stop flowing on high load on 8110SCd controllers.
4124 */
4125 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4126 tp->cp_cmd |= RxVlan;
4127
c0e45c1c 4128 rtl_init_mdio_ops(tp);
065c27c1 4129 rtl_init_pll_power_ops(tp);
d58d46b5 4130 rtl_init_jumbo_ops(tp);
c0e45c1c 4131
1da177e4 4132 rtl8169_print_mac_version(tp);
1da177e4 4133
85bffe6c
FR		 4134 chipset = tp->mac_version;
4135 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 4136
5d06a99f
FR		 4137 RTL_W8(Cfg9346, Cfg9346_Unlock);
4138 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4139 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 4140 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4141 tp->features |= RTL_FEATURE_WOL;
4142 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4143 tp->features |= RTL_FEATURE_WOL;
2ca6cf06 4144 tp->features |= rtl_try_msi(tp, cfg);
5d06a99f
FR		 4145 RTL_W8(Cfg9346, Cfg9346_Lock);
4146
2544bfc0 4147 if (rtl_tbi_enabled(tp)) {
1da177e4
LT		 4148 tp->set_speed = rtl8169_set_speed_tbi;
4149 tp->get_settings = rtl8169_gset_tbi;
4150 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4151 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4152 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 4153 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 4154 } else {
4155 tp->set_speed = rtl8169_set_speed_xmii;
4156 tp->get_settings = rtl8169_gset_xmii;
4157 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4158 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4159 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 4160 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 4161 }
4162
df58ef51 4163 spin_lock_init(&tp->lock);
da78dbff 4164 mutex_init(&tp->wk.mutex);
df58ef51 4165
7bf6bf48 4166 /* Get MAC address */
6a3c910c 4167 for (i = 0; i < ETH_ALEN; i++)
1da177e4 4168 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 4169 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 4170
1da177e4 4171 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 4172 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4173 dev->irq = pdev->irq;
4174 dev->base_addr = (unsigned long) ioaddr;
1da177e4 4175
bea3348e 4176 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 4177
350fb32a
MM		 4178 /* don't enable SG, IP_CSUM and TSO by default - it might not work
4179 * properly for all devices */
4180 dev->features |= NETIF_F_RXCSUM |
4181 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4182
4183 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4184 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4185 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4186 NETIF_F_HIGHDMA;
4187
4188 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4189 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4190 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4 4191
0e485150 4192 tp->hw_start = cfg->hw_start;
da78dbff 4193 tp->event_slow = cfg->event_slow;
1da177e4 4194
e03f33af
FR		 4195 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4196 ~(RxBOVF | RxFOVF) : ~0;
4197
2efa53f3
FR		 4198 init_timer(&tp->timer);
4199 tp->timer.data = (unsigned long) dev;
4200 tp->timer.function = rtl8169_phy_timer;
4201
b6ffd97f 4202 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 4203
1da177e4 4204 rc = register_netdev(dev);
4ff96fa6 4205 if (rc < 0)
87aeec76 4206 goto err_out_msi_4;
1da177e4
LT		 4207
4208 pci_set_drvdata(pdev, dev);
4209
bf82c189 4210 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 4211 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 4212 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
d58d46b5
FR		 4213 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4214 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4215 "tx checksumming: %s]\n",
4216 rtl_chip_infos[chipset].jumbo_max,
4217 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4218 }
1da177e4 4219
cecb5fd7
FR		 4220 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4221 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4222 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 4223 rtl8168_driver_start(tp);
e6de30d6 4224 }
b646d900 4225
8b76ab39 4226 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 4227
f3ec4f87
AS		 4228 if (pci_dev_run_wake(pdev))
4229 pm_runtime_put_noidle(&pdev->dev);
e1759441 4230
0d672e9f
IV		 4231 netif_carrier_off(dev);
4232
4ff96fa6
FR		 4233out:
4234 return rc;
1da177e4 4235
87aeec76 4236err_out_msi_4:
fbac58fc 4237 rtl_disable_msi(pdev, tp);
4ff96fa6 4238 iounmap(ioaddr);
87aeec76 4239err_out_free_res_3:
4ff96fa6 4240 pci_release_regions(pdev);
87aeec76 4241err_out_mwi_2:
4ff96fa6 4242 pci_clear_mwi(pdev);
4ff96fa6
FR		 4243 pci_disable_device(pdev);
4244err_out_free_dev_1:
4245 free_netdev(dev);
4246 goto out;
1da177e4
LT		 4247}
4248
07d3f51f 4249static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 4250{
4251 struct net_device *dev = pci_get_drvdata(pdev);
4252 struct rtl8169_private *tp = netdev_priv(dev);
4253
cecb5fd7
FR		 4254 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4255 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4256 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 4257 rtl8168_driver_stop(tp);
e6de30d6 4258 }
b646d900 4259
4422bcd4 4260 cancel_work_sync(&tp->wk.work);
eb2a021c 4261
1da177e4 4262 unregister_netdev(dev);
cc098dc7 4263
953a12cc
FR		 4264 rtl_release_firmware(tp);
4265
f3ec4f87
AS		 4266 if (pci_dev_run_wake(pdev))
4267 pm_runtime_get_noresume(&pdev->dev);
e1759441 4268
cc098dc7
IV		 4269 /* restore original MAC address */
4270 rtl_rar_set(tp, dev->perm_addr);
4271
fbac58fc 4272 rtl_disable_msi(pdev, tp);
1da177e4
LT		 4273 rtl8169_release_board(pdev, dev, tp->mmio_addr);
4274 pci_set_drvdata(pdev, NULL);
4275}
4276
b6ffd97f 4277static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4278{
b6ffd97f
FR		 4279 struct rtl_fw *rtl_fw;
4280 const char *name;
4281 int rc = -ENOMEM;
953a12cc 4282
b6ffd97f
FR		 4283 name = rtl_lookup_firmware_name(tp);
4284 if (!name)
4285 goto out_no_firmware;
953a12cc 4286
b6ffd97f
FR		 4287 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4288 if (!rtl_fw)
4289 goto err_warn;
31bd204f 4290
b6ffd97f
FR		 4291 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4292 if (rc < 0)
4293 goto err_free;
4294
fd112f2e
FR		 4295 rc = rtl_check_firmware(tp, rtl_fw);
4296 if (rc < 0)
4297 goto err_release_firmware;
4298
b6ffd97f
FR		 4299 tp->rtl_fw = rtl_fw;
4300out:
4301 return;
4302
fd112f2e
FR		 4303err_release_firmware:
4304 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4305err_free:
4306 kfree(rtl_fw);
4307err_warn:
4308 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4309 name, rc);
4310out_no_firmware:
4311 tp->rtl_fw = NULL;
4312 goto out;
4313}
4314
4315static void rtl_request_firmware(struct rtl8169_private *tp)
4316{
4317 if (IS_ERR(tp->rtl_fw))
4318 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4319}
4320
4422bcd4
FR		 4321static void rtl_task(struct work_struct *);
4322
1da177e4
LT		 4323static int rtl8169_open(struct net_device *dev)
4324{
4325 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 4326 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4327 struct pci_dev *pdev = tp->pci_dev;
99f252b0 4328 int retval = -ENOMEM;
1da177e4 4329
e1759441 4330 pm_runtime_get_sync(&pdev->dev);
1da177e4 4331
1da177e4
LT		 4332 /*
4333 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 4334 * dma_alloc_coherent provides more.
1da177e4 4335 */
82553bb6
SG		 4336 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4337 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 4338 if (!tp->TxDescArray)
e1759441 4339 goto err_pm_runtime_put;
1da177e4 4340
82553bb6
SG		 4341 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4342 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 4343 if (!tp->RxDescArray)
99f252b0 4344 goto err_free_tx_0;
1da177e4
LT		 4345
4346 retval = rtl8169_init_ring(dev);
4347 if (retval < 0)
99f252b0 4348 goto err_free_rx_1;
1da177e4 4349
4422bcd4 4350 INIT_WORK(&tp->wk.work, rtl_task);
1da177e4 4351
99f252b0
FR		 4352 smp_mb();
4353
953a12cc
FR		 4354 rtl_request_firmware(tp);
4355
fbac58fc
FR		 4356 retval = request_irq(dev->irq, rtl8169_interrupt,
4357 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 4358 dev->name, dev);
4359 if (retval < 0)
953a12cc 4360 goto err_release_fw_2;
99f252b0 4361
da78dbff
FR		 4362 rtl_lock_work(tp);
4363
4364 tp->wk.enabled = true;
4365
bea3348e 4366 napi_enable(&tp->napi);
bea3348e 4367
eee3a96c 4368 rtl8169_init_phy(dev, tp);
4369
da78dbff 4370 __rtl8169_set_features(dev, dev->features);
eee3a96c 4371
065c27c1 4372 rtl_pll_power_up(tp);
4373
07ce4064 4374 rtl_hw_start(dev);
1da177e4 4375
da78dbff
FR		 4376 netif_start_queue(dev);
4377
4378 rtl_unlock_work(tp);
4379
e1759441
RW		 4380 tp->saved_wolopts = 0;
4381 pm_runtime_put_noidle(&pdev->dev);
4382
eee3a96c 4383 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 4384out:
4385 return retval;
4386
953a12cc
FR		 4387err_release_fw_2:
4388 rtl_release_firmware(tp);
99f252b0
FR		 4389 rtl8169_rx_clear(tp);
4390err_free_rx_1:
82553bb6
SG		 4391 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4392 tp->RxPhyAddr);
e1759441 4393 tp->RxDescArray = NULL;
99f252b0 4394err_free_tx_0:
82553bb6
SG		 4395 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4396 tp->TxPhyAddr);
e1759441
RW		 4397 tp->TxDescArray = NULL;
4398err_pm_runtime_put:
4399 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 4400 goto out;
4401}
4402
92fc43b4
HW		 4403static void rtl_rx_close(struct rtl8169_private *tp)
4404{
4405 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4406
1687b566 4407 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4408}
4409
e6de30d6 4410static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4411{
e6de30d6 4412 void __iomem *ioaddr = tp->mmio_addr;
4413
1da177e4 4414 /* Disable interrupts */
811fd301 4415 rtl8169_irq_mask_and_ack(tp);
1da177e4 4416
92fc43b4
HW		 4417 rtl_rx_close(tp);
4418
5d2e1957 4419 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4420 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4421 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 4422 while (RTL_R8(TxPoll) & NPQ)
4423 udelay(20);
c2218925
HW		 4424 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4425 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4426 tp->mac_version == RTL_GIGA_MAC_VER_36) {
c2b0c1e7 4427 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
70090424
HW		 4428 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4429 udelay(100);
92fc43b4
HW		 4430 } else {
4431 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4432 udelay(100);
e6de30d6 4433 }
4434
92fc43b4 4435 rtl_hw_reset(tp);
1da177e4
LT		 4436}
4437
7f796d83 4438static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4439{
4440 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4441
4442 /* Set DMA burst size and Interframe Gap Time */
4443 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4444 (InterFrameGap << TxInterFrameGapShift));
4445}
4446
07ce4064 4447static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4448{
4449 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4450
07ce4064
FR		 4451 tp->hw_start(dev);
4452
da78dbff 4453 rtl_irq_enable_all(tp);
07ce4064
FR		 4454}
4455
7f796d83
FR		 4456static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4457 void __iomem *ioaddr)
4458{
4459 /*
4460 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4461 * register to be written before TxDescAddrLow to work.
4462 * Switching from MMIO to I/O access fixes the issue as well.
4463 */
4464 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4465 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4466 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4467 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4468}
4469
4470static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4471{
4472 u16 cmd;
4473
4474 cmd = RTL_R16(CPlusCmd);
4475 RTL_W16(CPlusCmd, cmd);
4476 return cmd;
4477}
4478
fdd7b4c3 4479static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4480{
4481 /* Low hurts. Let's disable the filtering. */
207d6e87 4482 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4483}
4484
6dccd16b
FR		 4485static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4486{
3744100e 4487 static const struct rtl_cfg2_info {
6dccd16b
FR		 4488 u32 mac_version;
4489 u32 clk;
4490 u32 val;
4491 } cfg2_info [] = {
4492 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4493 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4494 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4495 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4496 };
4497 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4498 unsigned int i;
4499 u32 clk;
4500
4501 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4502 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4503 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4504 RTL_W32(0x7c, p->val);
4505 break;
4506 }
4507 }
4508}
4509
07ce4064
FR		 4510static void rtl_hw_start_8169(struct net_device *dev)
4511{
4512 struct rtl8169_private *tp = netdev_priv(dev);
4513 void __iomem *ioaddr = tp->mmio_addr;
4514 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4515
9cb427b6
FR		 4516 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4517 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4518 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4519 }
4520
1da177e4 4521 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4522 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4523 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4524 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4525 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4526 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4527
e542a226
HW		 4528 rtl_init_rxcfg(tp);
4529
f0298f81 4530 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4531
6f0333b8 4532 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4533
cecb5fd7
FR		 4534 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4535 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4536 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4537 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4538 rtl_set_rx_tx_config_registers(tp);
1da177e4 4539
7f796d83 4540 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4541
cecb5fd7
FR		 4542 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4543 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4544 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4545 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4546 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4547 }
4548
bcf0bf90
FR		 4549 RTL_W16(CPlusCmd, tp->cp_cmd);
4550
6dccd16b
FR		 4551 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4552
1da177e4
LT		 4553 /*
4554 * Undocumented corner. Supposedly:
4555 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4556 */
4557 RTL_W16(IntrMitigate, 0x0000);
4558
7f796d83 4559 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4560
cecb5fd7
FR		 4561 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4562 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4563 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4564 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4565 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4566 rtl_set_rx_tx_config_registers(tp);
4567 }
4568
1da177e4 4569 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4570
4571 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4572 RTL_R8(IntrMask);
1da177e4
LT		 4573
4574 RTL_W32(RxMissed, 0);
4575
07ce4064 4576 rtl_set_rx_mode(dev);
1da177e4
LT		 4577
4578 /* no early-rx interrupts */
4579 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4580}
1da177e4 4581
650e8d5d 4582static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4583{
4584 u32 csi;
4585
4586 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4587 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4588}
4589
e6de30d6 4590static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4591{
4592 rtl_csi_access_enable(ioaddr, 0x17000000);
4593}
4594
650e8d5d 4595static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4596{
4597 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4598}
4599
4600struct ephy_info {
4601 unsigned int offset;
4602 u16 mask;
4603 u16 bits;
4604};
4605
350f7596 4606static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4607{
4608 u16 w;
4609
4610 while (len-- > 0) {
4611 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4612 rtl_ephy_write(ioaddr, e->offset, w);
4613 e++;
4614 }
4615}
4616
b726e493
FR		 4617static void rtl_disable_clock_request(struct pci_dev *pdev)
4618{
e44daade 4619 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4620
4621 if (cap) {
4622 u16 ctl;
4623
4624 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4625 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4626 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4627 }
4628}
4629
e6de30d6 4630static void rtl_enable_clock_request(struct pci_dev *pdev)
4631{
e44daade 4632 int cap = pci_pcie_cap(pdev);
e6de30d6 4633
4634 if (cap) {
4635 u16 ctl;
4636
4637 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4638 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4639 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4640 }
4641}
4642
b726e493
FR		 4643#define R8168_CPCMD_QUIRK_MASK (\
4644 EnableBist | \
4645 Mac_dbgo_oe | \
4646 Force_half_dup | \
4647 Force_rxflow_en | \
4648 Force_txflow_en | \
4649 Cxpl_dbg_sel | \
4650 ASF | \
4651 PktCntrDisable | \
4652 Mac_dbgo_sel)
4653
219a1e9d
FR		 4654static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4655{
b726e493
FR		 4656 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4657
4658 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4659
2e68ae44
FR		 4660 rtl_tx_performance_tweak(pdev,
4661 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4662}
4663
4664static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4665{
4666 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4667
f0298f81 4668 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4669
4670 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4671}
4672
4673static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4674{
b726e493
FR		 4675 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4676
4677 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4678
219a1e9d 4679 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4680
4681 rtl_disable_clock_request(pdev);
4682
4683 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4684}
4685
ef3386f0 4686static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4687{
350f7596 4688 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4689 { 0x01, 0, 0x0001 },
4690 { 0x02, 0x0800, 0x1000 },
4691 { 0x03, 0, 0x0042 },
4692 { 0x06, 0x0080, 0x0000 },
4693 { 0x07, 0, 0x2000 }
4694 };
4695
650e8d5d 4696 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4697
4698 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4699
219a1e9d
FR		 4700 __rtl_hw_start_8168cp(ioaddr, pdev);
4701}
4702
ef3386f0
FR		 4703static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4704{
650e8d5d 4705 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4706
4707 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4708
4709 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4710
4711 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4712}
4713
7f3e3d3a
FR		 4714static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4715{
650e8d5d 4716 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4717
4718 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4719
4720 /* Magic. */
4721 RTL_W8(DBG_REG, 0x20);
4722
f0298f81 4723 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4724
4725 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4726
4727 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4728}
4729
219a1e9d
FR		 4730static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4731{
350f7596 4732 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4733 { 0x02, 0x0800, 0x1000 },
4734 { 0x03, 0, 0x0002 },
4735 { 0x06, 0x0080, 0x0000 }
4736 };
4737
650e8d5d 4738 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4739
4740 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4741
4742 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4743
219a1e9d
FR		 4744 __rtl_hw_start_8168cp(ioaddr, pdev);
4745}
4746
4747static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4748{
350f7596 4749 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4750 { 0x01, 0, 0x0001 },
4751 { 0x03, 0x0400, 0x0220 }
4752 };
4753
650e8d5d 4754 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4755
4756 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4757
219a1e9d
FR		 4758 __rtl_hw_start_8168cp(ioaddr, pdev);
4759}
4760
197ff761
FR		 4761static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4762{
4763 rtl_hw_start_8168c_2(ioaddr, pdev);
4764}
4765
6fb07058
FR		 4766static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4767{
650e8d5d 4768 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4769
4770 __rtl_hw_start_8168cp(ioaddr, pdev);
4771}
4772
5b538df9
FR		 4773static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4774{
650e8d5d 4775 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4776
4777 rtl_disable_clock_request(pdev);
4778
f0298f81 4779 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4780
4781 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4782
4783 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4784}
4785
4804b3b3 4786static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4787{
4788 rtl_csi_access_enable_1(ioaddr);
4789
4790 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4791
4792 RTL_W8(MaxTxPacketSize, TxPacketMax);
4793
4794 rtl_disable_clock_request(pdev);
4795}
4796
e6de30d6 4797static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4798{
4799 static const struct ephy_info e_info_8168d_4[] = {
4800 { 0x0b, ~0, 0x48 },
4801 { 0x19, 0x20, 0x50 },
4802 { 0x0c, ~0, 0x20 }
4803 };
4804 int i;
4805
4806 rtl_csi_access_enable_1(ioaddr);
4807
4808 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4809
4810 RTL_W8(MaxTxPacketSize, TxPacketMax);
4811
4812 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4813 const struct ephy_info *e = e_info_8168d_4 + i;
4814 u16 w;
4815
4816 w = rtl_ephy_read(ioaddr, e->offset);
4817 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4818 }
4819
4820 rtl_enable_clock_request(pdev);
4821}
4822
70090424 4823static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4824{
70090424 4825 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4826 { 0x00, 0x0200, 0x0100 },
4827 { 0x00, 0x0000, 0x0004 },
4828 { 0x06, 0x0002, 0x0001 },
4829 { 0x06, 0x0000, 0x0030 },
4830 { 0x07, 0x0000, 0x2000 },
4831 { 0x00, 0x0000, 0x0020 },
4832 { 0x03, 0x5800, 0x2000 },
4833 { 0x03, 0x0000, 0x0001 },
4834 { 0x01, 0x0800, 0x1000 },
4835 { 0x07, 0x0000, 0x4000 },
4836 { 0x1e, 0x0000, 0x2000 },
4837 { 0x19, 0xffff, 0xfe6c },
4838 { 0x0a, 0x0000, 0x0040 }
4839 };
4840
4841 rtl_csi_access_enable_2(ioaddr);
4842
70090424 4843 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4844
4845 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4846
4847 RTL_W8(MaxTxPacketSize, TxPacketMax);
4848
4849 rtl_disable_clock_request(pdev);
4850
4851 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4852 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4853 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4854
cecb5fd7 4855 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4856}
4857
70090424
HW		 4858static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4859{
4860 static const struct ephy_info e_info_8168e_2[] = {
4861 { 0x09, 0x0000, 0x0080 },
4862 { 0x19, 0x0000, 0x0224 }
4863 };
4864
4865 rtl_csi_access_enable_1(ioaddr);
4866
4867 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4868
4869 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4870
4871 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4872 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4873 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4874 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4875 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4876 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4877 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4878 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4879 ERIAR_EXGMAC);
4880
3090bd9a 4881 RTL_W8(MaxTxPacketSize, EarlySize);
70090424
HW		 4882
4883 rtl_disable_clock_request(pdev);
4884
4885 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4886 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4887
4888 /* Adjust EEE LED frequency */
4889 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4890
4891 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4892 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4893 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4894}
4895
c2218925
HW		 4896static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4897{
4898 static const struct ephy_info e_info_8168f_1[] = {
4899 { 0x06, 0x00c0, 0x0020 },
4900 { 0x08, 0x0001, 0x0002 },
4901 { 0x09, 0x0000, 0x0080 },
4902 { 0x19, 0x0000, 0x0224 }
4903 };
4904
4905 rtl_csi_access_enable_1(ioaddr);
4906
4907 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4908
4909 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4910
4911 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4912 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4913 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4914 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4915 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4916 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4917 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4918 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4919 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4920 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4921 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4922 ERIAR_EXGMAC);
4923
4924 RTL_W8(MaxTxPacketSize, EarlySize);
4925
4926 rtl_disable_clock_request(pdev);
4927
4928 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4929 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4930
4931 /* Adjust EEE LED frequency */
4932 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4933
4934 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4935 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4936 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4937}
4938
07ce4064
FR		 4939static void rtl_hw_start_8168(struct net_device *dev)
4940{
2dd99530
FR		 4941 struct rtl8169_private *tp = netdev_priv(dev);
4942 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4943 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4944
4945 RTL_W8(Cfg9346, Cfg9346_Unlock);
4946
f0298f81 4947 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4948
6f0333b8 4949 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4950
0e485150 4951 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4952
4953 RTL_W16(CPlusCmd, tp->cp_cmd);
4954
0e485150 4955 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4956
0e485150 4957 /* Work around for RxFIFO overflow. */
811fd301 4958 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 4959 tp->event_slow |= RxFIFOOver | PCSTimeout;
4960 tp->event_slow &= ~RxOverflow;
0e485150
FR		 4961 }
4962
4963 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4964
b8363901
FR		 4965 rtl_set_rx_mode(dev);
4966
4967 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4968 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4969
4970 RTL_R8(IntrMask);
4971
219a1e9d
FR		 4972 switch (tp->mac_version) {
4973 case RTL_GIGA_MAC_VER_11:
4974 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4975 break;
219a1e9d
FR		 4976
4977 case RTL_GIGA_MAC_VER_12:
4978 case RTL_GIGA_MAC_VER_17:
4979 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4980 break;
219a1e9d
FR		 4981
4982 case RTL_GIGA_MAC_VER_18:
ef3386f0 4983 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4984 break;
219a1e9d
FR		 4985
4986 case RTL_GIGA_MAC_VER_19:
4987 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4988 break;
219a1e9d
FR		 4989
4990 case RTL_GIGA_MAC_VER_20:
4991 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4992 break;
219a1e9d 4993
197ff761
FR		 4994 case RTL_GIGA_MAC_VER_21:
4995 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4996 break;
197ff761 4997
6fb07058
FR		 4998 case RTL_GIGA_MAC_VER_22:
4999 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 5000 break;
6fb07058 5001
ef3386f0
FR		 5002 case RTL_GIGA_MAC_VER_23:
5003 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 5004 break;
ef3386f0 5005
7f3e3d3a
FR		 5006 case RTL_GIGA_MAC_VER_24:
5007 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 5008 break;
7f3e3d3a 5009
5b538df9 5010 case RTL_GIGA_MAC_VER_25:
daf9df6d 5011 case RTL_GIGA_MAC_VER_26:
5012 case RTL_GIGA_MAC_VER_27:
5b538df9 5013 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 5014 break;
5b538df9 5015
e6de30d6 5016 case RTL_GIGA_MAC_VER_28:
5017 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 5018 break;
cecb5fd7 5019
4804b3b3 5020 case RTL_GIGA_MAC_VER_31:
5021 rtl_hw_start_8168dp(ioaddr, pdev);
5022 break;
5023
01dc7fec 5024 case RTL_GIGA_MAC_VER_32:
5025 case RTL_GIGA_MAC_VER_33:
70090424
HW		 5026 rtl_hw_start_8168e_1(ioaddr, pdev);
5027 break;
5028 case RTL_GIGA_MAC_VER_34:
5029 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 5030 break;
e6de30d6 5031
c2218925
HW		 5032 case RTL_GIGA_MAC_VER_35:
5033 case RTL_GIGA_MAC_VER_36:
5034 rtl_hw_start_8168f_1(ioaddr, pdev);
5035 break;
5036
219a1e9d
FR		 5037 default:
5038 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5039 dev->name, tp->mac_version);
4804b3b3 5040 break;
219a1e9d 5041 }
2dd99530 5042
0e485150
FR		 5043 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5044
b8363901
FR		 5045 RTL_W8(Cfg9346, Cfg9346_Lock);
5046
2dd99530 5047 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5048}
1da177e4 5049
2857ffb7
FR		 5050#define R810X_CPCMD_QUIRK_MASK (\
5051 EnableBist | \
5052 Mac_dbgo_oe | \
5053 Force_half_dup | \
5edcc537 5054 Force_rxflow_en | \
2857ffb7
FR		 5055 Force_txflow_en | \
5056 Cxpl_dbg_sel | \
5057 ASF | \
5058 PktCntrDisable | \
d24e9aaf 5059 Mac_dbgo_sel)
2857ffb7
FR		 5060
5061static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5062{
350f7596 5063 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5064 { 0x01, 0, 0x6e65 },
5065 { 0x02, 0, 0x091f },
5066 { 0x03, 0, 0xc2f9 },
5067 { 0x06, 0, 0xafb5 },
5068 { 0x07, 0, 0x0e00 },
5069 { 0x19, 0, 0xec80 },
5070 { 0x01, 0, 0x2e65 },
5071 { 0x01, 0, 0x6e65 }
5072 };
5073 u8 cfg1;
5074
650e8d5d 5075 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 5076
5077 RTL_W8(DBG_REG, FIX_NAK_1);
5078
5079 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5080
5081 RTL_W8(Config1,
5082 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5083 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5084
5085 cfg1 = RTL_R8(Config1);
5086 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5087 RTL_W8(Config1, cfg1 & ~LEDS0);
5088
2857ffb7
FR		 5089 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5090}
5091
5092static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5093{
650e8d5d 5094 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 5095
5096 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5097
5098 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5099 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5100}
5101
5102static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5103{
5104 rtl_hw_start_8102e_2(ioaddr, pdev);
5105
5106 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5107}
5108
5a5e4443
HW		 5109static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5110{
5111 static const struct ephy_info e_info_8105e_1[] = {
5112 { 0x07, 0, 0x4000 },
5113 { 0x19, 0, 0x0200 },
5114 { 0x19, 0, 0x0020 },
5115 { 0x1e, 0, 0x2000 },
5116 { 0x03, 0, 0x0001 },
5117 { 0x19, 0, 0x0100 },
5118 { 0x19, 0, 0x0004 },
5119 { 0x0a, 0, 0x0020 }
5120 };
5121
cecb5fd7 5122 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5123 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5124
cecb5fd7 5125 /* Disable Early Tally Counter */
5a5e4443
HW		 5126 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5127
5128 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5129 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 5130
5131 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5132}
5133
5134static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5135{
5136 rtl_hw_start_8105e_1(ioaddr, pdev);
5137 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5138}
5139
07ce4064
FR		 5140static void rtl_hw_start_8101(struct net_device *dev)
5141{
cdf1a608
FR		 5142 struct rtl8169_private *tp = netdev_priv(dev);
5143 void __iomem *ioaddr = tp->mmio_addr;
5144 struct pci_dev *pdev = tp->pci_dev;
5145
da78dbff
FR		 5146 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5147 tp->event_slow &= ~RxFIFOOver;
811fd301 5148
cecb5fd7
FR		 5149 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5150 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 5151 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 5152
5153 if (cap) {
5154 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5155 PCI_EXP_DEVCTL_NOSNOOP_EN);
5156 }
cdf1a608
FR		 5157 }
5158
d24e9aaf
HW		 5159 RTL_W8(Cfg9346, Cfg9346_Unlock);
5160
2857ffb7
FR		 5161 switch (tp->mac_version) {
5162 case RTL_GIGA_MAC_VER_07:
5163 rtl_hw_start_8102e_1(ioaddr, pdev);
5164 break;
5165
5166 case RTL_GIGA_MAC_VER_08:
5167 rtl_hw_start_8102e_3(ioaddr, pdev);
5168 break;
5169
5170 case RTL_GIGA_MAC_VER_09:
5171 rtl_hw_start_8102e_2(ioaddr, pdev);
5172 break;
5a5e4443
HW		 5173
5174 case RTL_GIGA_MAC_VER_29:
5175 rtl_hw_start_8105e_1(ioaddr, pdev);
5176 break;
5177 case RTL_GIGA_MAC_VER_30:
5178 rtl_hw_start_8105e_2(ioaddr, pdev);
5179 break;
cdf1a608
FR		 5180 }
5181
d24e9aaf 5182 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5183
f0298f81 5184 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5185
6f0333b8 5186 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5187
d24e9aaf 5188 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5189 RTL_W16(CPlusCmd, tp->cp_cmd);
5190
5191 RTL_W16(IntrMitigate, 0x0000);
5192
5193 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5194
5195 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5196 rtl_set_rx_tx_config_registers(tp);
5197
cdf1a608
FR		 5198 RTL_R8(IntrMask);
5199
cdf1a608
FR		 5200 rtl_set_rx_mode(dev);
5201
5202 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5203}
5204
5205static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5206{
d58d46b5
FR		 5207 struct rtl8169_private *tp = netdev_priv(dev);
5208
5209 if (new_mtu < ETH_ZLEN ||
5210 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5211 return -EINVAL;
5212
d58d46b5
FR		 5213 if (new_mtu > ETH_DATA_LEN)
5214 rtl_hw_jumbo_enable(tp);
5215 else
5216 rtl_hw_jumbo_disable(tp);
5217
1da177e4 5218 dev->mtu = new_mtu;
350fb32a
MM		 5219 netdev_update_features(dev);
5220
323bb685 5221 return 0;
1da177e4
LT		 5222}
5223
5224static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5225{
95e0918d 5226 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5227 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5228}
5229
6f0333b8
ED		 5230static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5231 void **data_buff, struct RxDesc *desc)
1da177e4 5232{
48addcc9 5233 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5234 DMA_FROM_DEVICE);
48addcc9 5235
6f0333b8
ED		 5236 kfree(*data_buff);
5237 *data_buff = NULL;
1da177e4
LT		 5238 rtl8169_make_unusable_by_asic(desc);
5239}
5240
5241static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5242{
5243 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5244
5245 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5246}
5247
5248static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5249 u32 rx_buf_sz)
5250{
5251 desc->addr = cpu_to_le64(mapping);
5252 wmb();
5253 rtl8169_mark_to_asic(desc, rx_buf_sz);
5254}
5255
6f0333b8
ED		 5256static inline void *rtl8169_align(void *data)
5257{
5258 return (void *)ALIGN((long)data, 16);
5259}
5260
0ecbe1ca
SG		 5261static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5262 struct RxDesc *desc)
1da177e4 5263{
6f0333b8 5264 void *data;
1da177e4 5265 dma_addr_t mapping;
48addcc9 5266 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5267 struct net_device *dev = tp->dev;
6f0333b8 5268 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5269
6f0333b8
ED		 5270 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5271 if (!data)
5272 return NULL;
e9f63f30 5273
6f0333b8
ED		 5274 if (rtl8169_align(data) != data) {
5275 kfree(data);
5276 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5277 if (!data)
5278 return NULL;
5279 }
3eafe507 5280
48addcc9 5281 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5282 DMA_FROM_DEVICE);
d827d86b
SG		 5283 if (unlikely(dma_mapping_error(d, mapping))) {
5284 if (net_ratelimit())
5285 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5286 goto err_out;
d827d86b 5287 }
1da177e4
LT		 5288
5289 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5290 return data;
3eafe507
SG		 5291
5292err_out:
5293 kfree(data);
5294 return NULL;
1da177e4
LT		 5295}
5296
5297static void rtl8169_rx_clear(struct rtl8169_private *tp)
5298{
07d3f51f 5299 unsigned int i;
1da177e4
LT		 5300
5301 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5302 if (tp->Rx_databuff[i]) {
5303 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5304 tp->RxDescArray + i);
5305 }
5306 }
5307}
5308
0ecbe1ca 5309static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5310{
0ecbe1ca
SG		 5311 desc->opts1 |= cpu_to_le32(RingEnd);
5312}
5b0384f4 5313
0ecbe1ca
SG		 5314static int rtl8169_rx_fill(struct rtl8169_private *tp)
5315{
5316 unsigned int i;
1da177e4 5317
0ecbe1ca
SG		 5318 for (i = 0; i < NUM_RX_DESC; i++) {
5319 void *data;
4ae47c2d 5320
6f0333b8 5321 if (tp->Rx_databuff[i])
1da177e4 5322 continue;
bcf0bf90 5323
0ecbe1ca 5324 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5325 if (!data) {
5326 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5327 goto err_out;
6f0333b8
ED		 5328 }
5329 tp->Rx_databuff[i] = data;
1da177e4 5330 }
1da177e4 5331
0ecbe1ca
SG		 5332 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5333 return 0;
5334
5335err_out:
5336 rtl8169_rx_clear(tp);
5337 return -ENOMEM;
1da177e4
LT		 5338}
5339
1da177e4
LT		 5340static int rtl8169_init_ring(struct net_device *dev)
5341{
5342 struct rtl8169_private *tp = netdev_priv(dev);
5343
5344 rtl8169_init_ring_indexes(tp);
5345
5346 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5347 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5348
0ecbe1ca 5349 return rtl8169_rx_fill(tp);
1da177e4
LT		 5350}
5351
48addcc9 5352static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5353 struct TxDesc *desc)
5354{
5355 unsigned int len = tx_skb->len;
5356
48addcc9
SG		 5357 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5358
1da177e4
LT		 5359 desc->opts1 = 0x00;
5360 desc->opts2 = 0x00;
5361 desc->addr = 0x00;
5362 tx_skb->len = 0;
5363}
5364
3eafe507
SG		 5365static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5366 unsigned int n)
1da177e4
LT		 5367{
5368 unsigned int i;
5369
3eafe507
SG		 5370 for (i = 0; i < n; i++) {
5371 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5372 struct ring_info *tx_skb = tp->tx_skb + entry;
5373 unsigned int len = tx_skb->len;
5374
5375 if (len) {
5376 struct sk_buff *skb = tx_skb->skb;
5377
48addcc9 5378 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5379 tp->TxDescArray + entry);
5380 if (skb) {
cac4b22f 5381 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5382 dev_kfree_skb(skb);
5383 tx_skb->skb = NULL;
5384 }
1da177e4
LT		 5385 }
5386 }
3eafe507
SG		 5387}
5388
5389static void rtl8169_tx_clear(struct rtl8169_private *tp)
5390{
5391 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5392 tp->cur_tx = tp->dirty_tx = 0;
5393}
5394
4422bcd4 5395static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5396{
c4028958 5397 struct net_device *dev = tp->dev;
56de414c 5398 int i;
1da177e4 5399
da78dbff
FR		 5400 napi_disable(&tp->napi);
5401 netif_stop_queue(dev);
5402 synchronize_sched();
1da177e4 5403
c7c2c39b 5404 rtl8169_hw_reset(tp);
5405
56de414c
FR		 5406 for (i = 0; i < NUM_RX_DESC; i++)
5407 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5408
1da177e4 5409 rtl8169_tx_clear(tp);
c7c2c39b 5410 rtl8169_init_ring_indexes(tp);
1da177e4 5411
da78dbff 5412 napi_enable(&tp->napi);
56de414c
FR		 5413 rtl_hw_start(dev);
5414 netif_wake_queue(dev);
5415 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5416}
5417
5418static void rtl8169_tx_timeout(struct net_device *dev)
5419{
da78dbff
FR		 5420 struct rtl8169_private *tp = netdev_priv(dev);
5421
5422 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5423}
5424
5425static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5426 u32 *opts)
1da177e4
LT		 5427{
5428 struct skb_shared_info *info = skb_shinfo(skb);
5429 unsigned int cur_frag, entry;
a6343afb 5430 struct TxDesc * uninitialized_var(txd);
48addcc9 5431 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5432
5433 entry = tp->cur_tx;
5434 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5435 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5436 dma_addr_t mapping;
5437 u32 status, len;
5438 void *addr;
5439
5440 entry = (entry + 1) % NUM_TX_DESC;
5441
5442 txd = tp->TxDescArray + entry;
9e903e08 5443 len = skb_frag_size(frag);
929f6189 5444 addr = skb_frag_address(frag);
48addcc9 5445 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5446 if (unlikely(dma_mapping_error(d, mapping))) {
5447 if (net_ratelimit())
5448 netif_err(tp, drv, tp->dev,
5449 "Failed to map TX fragments DMA!\n");
3eafe507 5450 goto err_out;
d827d86b 5451 }
1da177e4 5452
cecb5fd7 5453 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5454 status = opts[0] | len |
5455 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5456
5457 txd->opts1 = cpu_to_le32(status);
2b7b4318 5458 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5459 txd->addr = cpu_to_le64(mapping);
5460
5461 tp->tx_skb[entry].len = len;
5462 }
5463
5464 if (cur_frag) {
5465 tp->tx_skb[entry].skb = skb;
5466 txd->opts1 |= cpu_to_le32(LastFrag);
5467 }
5468
5469 return cur_frag;
3eafe507
SG		 5470
5471err_out:
5472 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5473 return -EIO;
1da177e4
LT		 5474}
5475
2b7b4318
FR		 5476static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5477 struct sk_buff *skb, u32 *opts)
1da177e4 5478{
2b7b4318 5479 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5480 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5481 int offset = info->opts_offset;
350fb32a 5482
2b7b4318
FR		 5483 if (mss) {
5484 opts[0] |= TD_LSO;
5485 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5486 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5487 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5488
5489 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5490 opts[offset] |= info->checksum.tcp;
1da177e4 5491 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5492 opts[offset] |= info->checksum.udp;
5493 else
5494 WARN_ON_ONCE(1);
1da177e4 5495 }
1da177e4
LT		 5496}
5497
61357325
SH		 5498static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5499 struct net_device *dev)
1da177e4
LT		 5500{
5501 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5502 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5503 struct TxDesc *txd = tp->TxDescArray + entry;
5504 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5505 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5506 dma_addr_t mapping;
5507 u32 status, len;
2b7b4318 5508 u32 opts[2];
3eafe507 5509 int frags;
5b0384f4 5510
1da177e4 5511 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5512 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5513 goto err_stop_0;
1da177e4
LT		 5514 }
5515
5516 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5517 goto err_stop_0;
5518
5519 len = skb_headlen(skb);
48addcc9 5520 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5521 if (unlikely(dma_mapping_error(d, mapping))) {
5522 if (net_ratelimit())
5523 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5524 goto err_dma_0;
d827d86b 5525 }
3eafe507
SG		 5526
5527 tp->tx_skb[entry].len = len;
5528 txd->addr = cpu_to_le64(mapping);
1da177e4 5529
2b7b4318
FR		 5530 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5531 opts[0] = DescOwn;
1da177e4 5532
2b7b4318
FR		 5533 rtl8169_tso_csum(tp, skb, opts);
5534
5535 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5536 if (frags < 0)
5537 goto err_dma_1;
5538 else if (frags)
2b7b4318 5539 opts[0] |= FirstFrag;
3eafe507 5540 else {
2b7b4318 5541 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5542 tp->tx_skb[entry].skb = skb;
5543 }
5544
2b7b4318
FR		 5545 txd->opts2 = cpu_to_le32(opts[1]);
5546
1da177e4
LT		 5547 wmb();
5548
cecb5fd7 5549 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5550 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5551 txd->opts1 = cpu_to_le32(status);
5552
1da177e4
LT		 5553 tp->cur_tx += frags + 1;
5554
4c020a96 5555 wmb();
1da177e4 5556
cecb5fd7 5557 RTL_W8(TxPoll, NPQ);
1da177e4 5558
da78dbff
FR		 5559 mmiowb();
5560
1da177e4
LT		 5561 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5562 netif_stop_queue(dev);
1e874e04 5563 smp_mb();
1da177e4
LT		 5564 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5565 netif_wake_queue(dev);
5566 }
5567
61357325 5568 return NETDEV_TX_OK;
1da177e4 5569
3eafe507 5570err_dma_1:
48addcc9 5571 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5572err_dma_0:
5573 dev_kfree_skb(skb);
5574 dev->stats.tx_dropped++;
5575 return NETDEV_TX_OK;
5576
5577err_stop_0:
1da177e4 5578 netif_stop_queue(dev);
cebf8cc7 5579 dev->stats.tx_dropped++;
61357325 5580 return NETDEV_TX_BUSY;
1da177e4
LT		 5581}
5582
5583static void rtl8169_pcierr_interrupt(struct net_device *dev)
5584{
5585 struct rtl8169_private *tp = netdev_priv(dev);
5586 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5587 u16 pci_status, pci_cmd;
5588
5589 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5590 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5591
bf82c189
JP		 5592 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5593 pci_cmd, pci_status);
1da177e4
LT		 5594
5595 /*
5596 * The recovery sequence below admits a very elaborated explanation:
5597 * - it seems to work;
d03902b8
FR		 5598 * - I did not see what else could be done;
5599 * - it makes iop3xx happy.
1da177e4
LT		 5600 *
5601 * Feel free to adjust to your needs.
5602 */
a27993f3 5603 if (pdev->broken_parity_status)
d03902b8
FR		 5604 pci_cmd &= ~PCI_COMMAND_PARITY;
5605 else
5606 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5607
5608 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5609
5610 pci_write_config_word(pdev, PCI_STATUS,
5611 pci_status & (PCI_STATUS_DETECTED_PARITY |
5612 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5613 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5614
5615 /* The infamous DAC f*ckup only happens at boot time */
5616 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5617 void __iomem *ioaddr = tp->mmio_addr;
5618
bf82c189 5619 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5620 tp->cp_cmd &= ~PCIDAC;
5621 RTL_W16(CPlusCmd, tp->cp_cmd);
5622 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5623 }
5624
e6de30d6 5625 rtl8169_hw_reset(tp);
d03902b8 5626
da78dbff 5627 rtl_schedule_task_bh(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5628}
5629
da78dbff 5630static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5631{
5632 unsigned int dirty_tx, tx_left;
5633
1da177e4
LT		 5634 dirty_tx = tp->dirty_tx;
5635 smp_rmb();
5636 tx_left = tp->cur_tx - dirty_tx;
5637
5638 while (tx_left > 0) {
5639 unsigned int entry = dirty_tx % NUM_TX_DESC;
5640 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5641 u32 status;
5642
5643 rmb();
5644 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5645 if (status & DescOwn)
5646 break;
5647
48addcc9
SG		 5648 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5649 tp->TxDescArray + entry);
1da177e4 5650 if (status & LastFrag) {
cac4b22f
SG		 5651 dev->stats.tx_packets++;
5652 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 5653 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5654 tx_skb->skb = NULL;
5655 }
5656 dirty_tx++;
5657 tx_left--;
5658 }
5659
5660 if (tp->dirty_tx != dirty_tx) {
5661 tp->dirty_tx = dirty_tx;
1e874e04 5662 smp_mb();
1da177e4
LT		 5663 if (netif_queue_stopped(dev) &&
5664 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5665 netif_wake_queue(dev);
5666 }
d78ae2dc
FR		 5667 /*
5668 * 8168 hack: TxPoll requests are lost when the Tx packets are
5669 * too close. Let's kick an extra TxPoll request when a burst
5670 * of start_xmit activity is detected (if it is not detected,
5671 * it is slow enough). -- FR
5672 */
da78dbff
FR		 5673 if (tp->cur_tx != dirty_tx) {
5674 void __iomem *ioaddr = tp->mmio_addr;
5675
d78ae2dc 5676 RTL_W8(TxPoll, NPQ);
da78dbff 5677 }
1da177e4
LT		 5678 }
5679}
5680
126fa4b9
FR		 5681static inline int rtl8169_fragmented_frame(u32 status)
5682{
5683 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5684}
5685
adea1ac7 5686static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5687{
1da177e4
LT		 5688 u32 status = opts1 & RxProtoMask;
5689
5690 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5691 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5692 skb->ip_summed = CHECKSUM_UNNECESSARY;
5693 else
bc8acf2c 5694 skb_checksum_none_assert(skb);
1da177e4
LT		 5695}
5696
6f0333b8
ED		 5697static struct sk_buff *rtl8169_try_rx_copy(void *data,
5698 struct rtl8169_private *tp,
5699 int pkt_size,
5700 dma_addr_t addr)
1da177e4 5701{
b449655f 5702 struct sk_buff *skb;
48addcc9 5703 struct device *d = &tp->pci_dev->dev;
b449655f 5704
6f0333b8 5705 data = rtl8169_align(data);
48addcc9 5706 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5707 prefetch(data);
5708 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5709 if (skb)
5710 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5711 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5712
6f0333b8 5713 return skb;
1da177e4
LT		 5714}
5715
da78dbff 5716static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 5717{
5718 unsigned int cur_rx, rx_left;
6f0333b8 5719 unsigned int count;
1da177e4 5720
1da177e4
LT		 5721 cur_rx = tp->cur_rx;
5722 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5723 rx_left = min(rx_left, budget);
1da177e4 5724
4dcb7d33 5725 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5726 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5727 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5728 u32 status;
5729
5730 rmb();
e03f33af 5731 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 5732
5733 if (status & DescOwn)
5734 break;
4dcb7d33 5735 if (unlikely(status & RxRES)) {
bf82c189
JP		 5736 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5737 status);
cebf8cc7 5738 dev->stats.rx_errors++;
1da177e4 5739 if (status & (RxRWT | RxRUNT))
cebf8cc7 5740 dev->stats.rx_length_errors++;
1da177e4 5741 if (status & RxCRC)
cebf8cc7 5742 dev->stats.rx_crc_errors++;
9dccf611 5743 if (status & RxFOVF) {
da78dbff 5744 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 5745 dev->stats.rx_fifo_errors++;
9dccf611 5746 }
6f0333b8 5747 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5748 } else {
6f0333b8 5749 struct sk_buff *skb;
b449655f 5750 dma_addr_t addr = le64_to_cpu(desc->addr);
deb9d93c 5751 int pkt_size = (status & 0x00003fff) - 4;
1da177e4 5752
126fa4b9
FR		 5753 /*
5754 * The driver does not support incoming fragmented
5755 * frames. They are seen as a symptom of over-mtu
5756 * sized frames.
5757 */
5758 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5759 dev->stats.rx_dropped++;
5760 dev->stats.rx_length_errors++;
6f0333b8 5761 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5762 continue;
126fa4b9
FR		 5763 }
5764
6f0333b8
ED		 5765 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5766 tp, pkt_size, addr);
5767 rtl8169_mark_to_asic(desc, rx_buf_sz);
5768 if (!skb) {
5769 dev->stats.rx_dropped++;
5770 continue;
1da177e4
LT		 5771 }
5772
adea1ac7 5773 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5774 skb_put(skb, pkt_size);
5775 skb->protocol = eth_type_trans(skb, dev);
5776
7a8fc77b
FR		 5777 rtl8169_rx_vlan_tag(desc, skb);
5778
56de414c 5779 napi_gro_receive(&tp->napi, skb);
1da177e4 5780
cebf8cc7
FR		 5781 dev->stats.rx_bytes += pkt_size;
5782 dev->stats.rx_packets++;
1da177e4 5783 }
6dccd16b
FR		 5784
5785 /* Work around for AMD plateform. */
95e0918d 5786 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5787 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5788 desc->opts2 = 0;
5789 cur_rx++;
5790 }
1da177e4
LT		 5791 }
5792
5793 count = cur_rx - tp->cur_rx;
5794 tp->cur_rx = cur_rx;
5795
6f0333b8 5796 tp->dirty_rx += count;
1da177e4
LT		 5797
5798 return count;
5799}
5800
07d3f51f 5801static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5802{
07d3f51f 5803 struct net_device *dev = dev_instance;
1da177e4 5804 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5805 int handled = 0;
9085cdfa 5806 u16 status;
1da177e4 5807
9085cdfa 5808 status = rtl_get_events(tp);
da78dbff
FR		 5809 if (status && status != 0xffff) {
5810 status &= RTL_EVENT_NAPI | tp->event_slow;
5811 if (status) {
5812 handled = 1;
1da177e4 5813
da78dbff
FR		 5814 rtl_irq_disable(tp);
5815 napi_schedule(&tp->napi);
f11a377b 5816 }
da78dbff
FR		 5817 }
5818 return IRQ_RETVAL(handled);
5819}
1da177e4 5820
da78dbff
FR		 5821/*
5822 * Workqueue context.
5823 */
5824static void rtl_slow_event_work(struct rtl8169_private *tp)
5825{
5826 struct net_device *dev = tp->dev;
5827 u16 status;
5828
5829 status = rtl_get_events(tp) & tp->event_slow;
5830 rtl_ack_events(tp, status);
1da177e4 5831
da78dbff
FR		 5832 if (unlikely(status & RxFIFOOver)) {
5833 switch (tp->mac_version) {
5834 /* Work around for rx fifo overflow */
5835 case RTL_GIGA_MAC_VER_11:
5836 netif_stop_queue(dev);
5837 rtl_schedule_task_bh(tp, RTL_FLAG_TASK_RESET_PENDING);
5838 default:
f11a377b
DD		 5839 break;
5840 }
da78dbff 5841 }
1da177e4 5842
da78dbff
FR		 5843 if (unlikely(status & SYSErr))
5844 rtl8169_pcierr_interrupt(dev);
0e485150 5845
da78dbff
FR		 5846 if (status & LinkChg)
5847 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 5848
da78dbff
FR		 5849 napi_disable(&tp->napi);
5850 rtl_irq_disable(tp);
5851
5852 napi_enable(&tp->napi);
5853 napi_schedule(&tp->napi);
1da177e4
LT		 5854}
5855
4422bcd4
FR		 5856static void rtl_task(struct work_struct *work)
5857{
da78dbff
FR		 5858 static const struct {
5859 int bitnr;
5860 void (*action)(struct rtl8169_private *);
5861 } rtl_work[] = {
5862 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5863 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5864 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5865 };
4422bcd4
FR		 5866 struct rtl8169_private *tp =
5867 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 5868 struct net_device *dev = tp->dev;
5869 int i;
5870
5871 rtl_lock_work(tp);
5872
5873 if (!netif_running(dev) || !tp->wk.enabled)
5874 goto out_unlock;
5875
5876 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5877 bool pending;
5878
5879 spin_lock_bh(&tp->lock);
5880 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5881 spin_unlock_bh(&tp->lock);
5882
5883 if (pending)
5884 rtl_work[i].action(tp);
5885 }
4422bcd4 5886
da78dbff
FR		 5887out_unlock:
5888 rtl_unlock_work(tp);
4422bcd4
FR		 5889}
5890
bea3348e 5891static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5892{
bea3348e
SH		 5893 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5894 struct net_device *dev = tp->dev;
da78dbff
FR		 5895 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5896 int work_done= 0;
5897 u16 status;
5898
5899 status = rtl_get_events(tp);
5900 rtl_ack_events(tp, status & ~tp->event_slow);
5901
5902 if (status & RTL_EVENT_NAPI_RX)
5903 work_done = rtl_rx(dev, tp, (u32) budget);
5904
5905 if (status & RTL_EVENT_NAPI_TX)
5906 rtl_tx(dev, tp);
1da177e4 5907
da78dbff
FR		 5908 if (status & tp->event_slow) {
5909 enable_mask &= ~tp->event_slow;
5910
5911 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5912 }
1da177e4 5913
bea3348e 5914 if (work_done < budget) {
288379f0 5915 napi_complete(napi);
f11a377b 5916
da78dbff
FR		 5917 rtl_irq_enable(tp, enable_mask);
5918 mmiowb();
1da177e4
LT		 5919 }
5920
bea3348e 5921 return work_done;
1da177e4 5922}
1da177e4 5923
523a6094
FR		 5924static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5925{
5926 struct rtl8169_private *tp = netdev_priv(dev);
5927
5928 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5929 return;
5930
5931 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5932 RTL_W32(RxMissed, 0);
5933}
5934
1da177e4
LT		 5935static void rtl8169_down(struct net_device *dev)
5936{
5937 struct rtl8169_private *tp = netdev_priv(dev);
5938 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5939
4876cc1e 5940 del_timer_sync(&tp->timer);
1da177e4 5941
93dd79e8 5942 napi_disable(&tp->napi);
da78dbff 5943 netif_stop_queue(dev);
1da177e4 5944
92fc43b4 5945 rtl8169_hw_reset(tp);
323bb685
SG		 5946 /*
5947 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 5948 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5949 * and napi is disabled (rtl8169_poll).
323bb685 5950 */
523a6094 5951 rtl8169_rx_missed(dev, ioaddr);
1da177e4 5952
1da177e4 5953 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 5954 synchronize_sched();
1da177e4 5955
1da177e4
LT		 5956 rtl8169_tx_clear(tp);
5957
5958 rtl8169_rx_clear(tp);
065c27c1 5959
5960 rtl_pll_power_down(tp);
1da177e4
LT		 5961}
5962
5963static int rtl8169_close(struct net_device *dev)
5964{
5965 struct rtl8169_private *tp = netdev_priv(dev);
5966 struct pci_dev *pdev = tp->pci_dev;
5967
e1759441
RW		 5968 pm_runtime_get_sync(&pdev->dev);
5969
cecb5fd7 5970 /* Update counters before going down */
355423d0
IV		 5971 rtl8169_update_counters(dev);
5972
da78dbff
FR		 5973 rtl_lock_work(tp);
5974 tp->wk.enabled = false;
5975
1da177e4 5976 rtl8169_down(dev);
da78dbff 5977 rtl_unlock_work(tp);
1da177e4
LT		 5978
5979 free_irq(dev->irq, dev);
5980
82553bb6
SG		 5981 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5982 tp->RxPhyAddr);
5983 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5984 tp->TxPhyAddr);
1da177e4
LT		 5985 tp->TxDescArray = NULL;
5986 tp->RxDescArray = NULL;
5987
e1759441
RW		 5988 pm_runtime_put_sync(&pdev->dev);
5989
1da177e4
LT		 5990 return 0;
5991}
5992
07ce4064 5993static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5994{
5995 struct rtl8169_private *tp = netdev_priv(dev);
5996 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5997 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5998 int rx_mode;
1da177e4
LT		 5999 u32 tmp = 0;
6000
6001 if (dev->flags & IFF_PROMISC) {
6002 /* Unconditionally log net taps. */
bf82c189 6003 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 6004 rx_mode =
6005 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
6006 AcceptAllPhys;
6007 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 6008 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 6009 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 6010 /* Too many to filter perfectly -- accept all multicasts. */
6011 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
6012 mc_filter[1] = mc_filter[0] = 0xffffffff;
6013 } else {
22bedad3 6014 struct netdev_hw_addr *ha;
07d3f51f 6015
1da177e4
LT		 6016 rx_mode = AcceptBroadcast | AcceptMyPhys;
6017 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 6018 netdev_for_each_mc_addr(ha, dev) {
6019 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 6020 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6021 rx_mode |= AcceptMulticast;
6022 }
6023 }
6024
da78dbff 6025 spin_lock_bh(&tp->lock);
1da177e4 6026
1687b566 6027 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
1da177e4 6028
f887cce8 6029 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 6030 u32 data = mc_filter[0];
6031
6032 mc_filter[0] = swab32(mc_filter[1]);
6033 mc_filter[1] = swab32(data);
bcf0bf90
FR		 6034 }
6035
1da177e4 6036 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 6037 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 6038
57a9f236
FR		 6039 RTL_W32(RxConfig, tmp);
6040
da78dbff 6041 spin_unlock_bh(&tp->lock);
1da177e4
LT		 6042}
6043
6044/**
6045 * rtl8169_get_stats - Get rtl8169 read/write statistics
6046 * @dev: The Ethernet Device to get statistics for
6047 *
6048 * Get TX/RX statistics for rtl8169
6049 */
6050static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6051{
6052 struct rtl8169_private *tp = netdev_priv(dev);
6053 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6054
da78dbff 6055 if (netif_running(dev))
523a6094 6056 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6057
cebf8cc7 6058 return &dev->stats;
1da177e4
LT		 6059}
6060
861ab440 6061static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6062{
065c27c1 6063 struct rtl8169_private *tp = netdev_priv(dev);
6064
5d06a99f 6065 if (!netif_running(dev))
861ab440 6066 return;
5d06a99f
FR		 6067
6068 netif_device_detach(dev);
6069 netif_stop_queue(dev);
da78dbff
FR		 6070
6071 rtl_lock_work(tp);
6072 napi_disable(&tp->napi);
6073 tp->wk.enabled = false;
6074 rtl_unlock_work(tp);
6075
6076 rtl_pll_power_down(tp);
861ab440
RW		 6077}
6078
6079#ifdef CONFIG_PM
6080
6081static int rtl8169_suspend(struct device *device)
6082{
6083 struct pci_dev *pdev = to_pci_dev(device);
6084 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6085
861ab440 6086 rtl8169_net_suspend(dev);
1371fa6d 6087
5d06a99f
FR		 6088 return 0;
6089}
6090
e1759441
RW		 6091static void __rtl8169_resume(struct net_device *dev)
6092{
065c27c1 6093 struct rtl8169_private *tp = netdev_priv(dev);
6094
e1759441 6095 netif_device_attach(dev);
065c27c1 6096
6097 rtl_pll_power_up(tp);
6098
da78dbff
FR		 6099 tp->wk.enabled = true;
6100
6101 rtl_schedule_task_bh(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6102}
6103
861ab440 6104static int rtl8169_resume(struct device *device)
5d06a99f 6105{
861ab440 6106 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6107 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6108 struct rtl8169_private *tp = netdev_priv(dev);
6109
6110 rtl8169_init_phy(dev, tp);
5d06a99f 6111
e1759441
RW		 6112 if (netif_running(dev))
6113 __rtl8169_resume(dev);
5d06a99f 6114
e1759441
RW		 6115 return 0;
6116}
6117
6118static int rtl8169_runtime_suspend(struct device *device)
6119{
6120 struct pci_dev *pdev = to_pci_dev(device);
6121 struct net_device *dev = pci_get_drvdata(pdev);
6122 struct rtl8169_private *tp = netdev_priv(dev);
6123
6124 if (!tp->TxDescArray)
6125 return 0;
6126
da78dbff 6127 rtl_lock_work(tp);
e1759441
RW		 6128 tp->saved_wolopts = __rtl8169_get_wol(tp);
6129 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6130 rtl_unlock_work(tp);
e1759441
RW		 6131
6132 rtl8169_net_suspend(dev);
6133
6134 return 0;
6135}
6136
6137static int rtl8169_runtime_resume(struct device *device)
6138{
6139 struct pci_dev *pdev = to_pci_dev(device);
6140 struct net_device *dev = pci_get_drvdata(pdev);
6141 struct rtl8169_private *tp = netdev_priv(dev);
6142
6143 if (!tp->TxDescArray)
6144 return 0;
6145
da78dbff 6146 rtl_lock_work(tp);
e1759441
RW		 6147 __rtl8169_set_wol(tp, tp->saved_wolopts);
6148 tp->saved_wolopts = 0;
da78dbff 6149 rtl_unlock_work(tp);
e1759441 6150
fccec10b
SG		 6151 rtl8169_init_phy(dev, tp);
6152
e1759441 6153 __rtl8169_resume(dev);
5d06a99f 6154
5d06a99f
FR		 6155 return 0;
6156}
6157
e1759441
RW		 6158static int rtl8169_runtime_idle(struct device *device)
6159{
6160 struct pci_dev *pdev = to_pci_dev(device);
6161 struct net_device *dev = pci_get_drvdata(pdev);
6162 struct rtl8169_private *tp = netdev_priv(dev);
6163
e4fbce74 6164 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6165}
6166
47145210 6167static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6168 .suspend = rtl8169_suspend,
6169 .resume = rtl8169_resume,
6170 .freeze = rtl8169_suspend,
6171 .thaw = rtl8169_resume,
6172 .poweroff = rtl8169_suspend,
6173 .restore = rtl8169_resume,
6174 .runtime_suspend = rtl8169_runtime_suspend,
6175 .runtime_resume = rtl8169_runtime_resume,
6176 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6177};
6178
6179#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6180
6181#else /* !CONFIG_PM */
6182
6183#define RTL8169_PM_OPS NULL
6184
6185#endif /* !CONFIG_PM */
6186
649b3b8c 6187static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6188{
6189 void __iomem *ioaddr = tp->mmio_addr;
6190
6191 /* WoL fails with 8168b when the receiver is disabled. */
6192 switch (tp->mac_version) {
6193 case RTL_GIGA_MAC_VER_11:
6194 case RTL_GIGA_MAC_VER_12:
6195 case RTL_GIGA_MAC_VER_17:
6196 pci_clear_master(tp->pci_dev);
6197
6198 RTL_W8(ChipCmd, CmdRxEnb);
6199 /* PCI commit */
6200 RTL_R8(ChipCmd);
6201 break;
6202 default:
6203 break;
6204 }
6205}
6206
1765f95d
FR		 6207static void rtl_shutdown(struct pci_dev *pdev)
6208{
861ab440 6209 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6210 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 6211
6212 rtl8169_net_suspend(dev);
1765f95d 6213
cecb5fd7 6214 /* Restore original MAC address */
cc098dc7
IV		 6215 rtl_rar_set(tp, dev->perm_addr);
6216
92fc43b4 6217 rtl8169_hw_reset(tp);
4bb3f522 6218
861ab440 6219 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6220 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6221 rtl_wol_suspend_quirk(tp);
6222 rtl_wol_shutdown_quirk(tp);
ca52efd5 6223 }
6224
861ab440
RW		 6225 pci_wake_from_d3(pdev, true);
6226 pci_set_power_state(pdev, PCI_D3hot);
6227 }
6228}
5d06a99f 6229
1da177e4
LT		 6230static struct pci_driver rtl8169_pci_driver = {
6231 .name = MODULENAME,
6232 .id_table = rtl8169_pci_tbl,
6233 .probe = rtl8169_init_one,
6234 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 6235 .shutdown = rtl_shutdown,
861ab440 6236 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 6237};
6238
07d3f51f 6239static int __init rtl8169_init_module(void)
1da177e4 6240{
29917620 6241 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 6242}
6243
07d3f51f 6244static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 6245{
6246 pci_unregister_driver(&rtl8169_pci_driver);
6247}
6248
6249module_init(rtl8169_init_module);
6250module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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