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r8169: Update the RTL8111G parameters
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
beb330a4 50#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
bca03d5f 51
1da177e4
LT		 52#ifdef RTL8169_DEBUG
53#define assert(expr) \
5b0384f4
FR		 54 if (!(expr)) { \
55 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 56 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 57 }
06fa7358
JP		 58#define dprintk(fmt, args...) \
59 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 60#else
61#define assert(expr) do {} while (0)
62#define dprintk(fmt, args...) do {} while (0)
63#endif /* RTL8169_DEBUG */
64
b57b7e5a 65#define R8169_MSG_DEFAULT \
f0e837d9 66 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 67
477206a0
JD		 68#define TX_SLOTS_AVAIL(tp) \
69 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72#define TX_FRAGS_READY_FOR(tp,nr_frags) \
73 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 74
1da177e4
LT		 75/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 77static const int multicast_filter_limit = 32;
1da177e4 78
9c14ceaf 79#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 80#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 81#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
82
83#define R8169_REGS_SIZE 256
84#define R8169_NAPI_WEIGHT 64
85#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 86#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 87#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
88#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
89
90#define RTL8169_TX_TIMEOUT (6*HZ)
91#define RTL8169_PHY_TIMEOUT (10*HZ)
92
93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
c2218925
HW		 136 RTL_GIGA_MAC_VER_35,
137 RTL_GIGA_MAC_VER_36,
7e18dca1 138 RTL_GIGA_MAC_VER_37,
b3d7b2f2 139 RTL_GIGA_MAC_VER_38,
5598bfe5 140 RTL_GIGA_MAC_VER_39,
c558386b
HW		 141 RTL_GIGA_MAC_VER_40,
142 RTL_GIGA_MAC_VER_41,
85bffe6c 143 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 144};
145
2b7b4318
FR		 146enum rtl_tx_desc_version {
147 RTL_TD_0 = 0,
148 RTL_TD_1 = 1,
149};
150
d58d46b5
FR		 151#define JUMBO_1K ETH_DATA_LEN
152#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
153#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
154#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
155#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
156
157#define _R(NAME,TD,FW,SZ,B) { \
158 .name = NAME, \
159 .txd_version = TD, \
160 .fw_name = FW, \
161 .jumbo_max = SZ, \
162 .jumbo_tx_csum = B \
163}
1da177e4 164
3c6bee1d 165static const struct {
1da177e4 166 const char *name;
2b7b4318 167 enum rtl_tx_desc_version txd_version;
953a12cc 168 const char *fw_name;
d58d46b5
FR		 169 u16 jumbo_max;
170 bool jumbo_tx_csum;
85bffe6c
FR		 171} rtl_chip_infos[] = {
172 /* PCI devices. */
173 [RTL_GIGA_MAC_VER_01] =
d58d46b5 174 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_02] =
d58d46b5 176 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_03] =
d58d46b5 178 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 179 [RTL_GIGA_MAC_VER_04] =
d58d46b5 180 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_05] =
d58d46b5 182 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_06] =
d58d46b5 184 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 185 /* PCI-E devices. */
186 [RTL_GIGA_MAC_VER_07] =
d58d46b5 187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_08] =
d58d46b5 189 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_09] =
d58d46b5 191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_10] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_11] =
d58d46b5 195 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 196 [RTL_GIGA_MAC_VER_12] =
d58d46b5 197 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 198 [RTL_GIGA_MAC_VER_13] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_14] =
d58d46b5 201 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 202 [RTL_GIGA_MAC_VER_15] =
d58d46b5 203 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 204 [RTL_GIGA_MAC_VER_16] =
d58d46b5 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_17] =
d58d46b5 207 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_18] =
d58d46b5 209 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_19] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_20] =
d58d46b5 213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_21] =
d58d46b5 215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_22] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_23] =
d58d46b5 219 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_24] =
d58d46b5 221 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
224 JUMBO_9K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 226 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
227 JUMBO_9K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_27] =
d58d46b5 229 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_28] =
d58d46b5 231 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
234 JUMBO_1K, true),
85bffe6c 235 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 236 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
237 JUMBO_1K, true),
85bffe6c 238 [RTL_GIGA_MAC_VER_31] =
d58d46b5 239 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 244 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
245 JUMBO_9K, false),
70090424 246 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 247 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
248 JUMBO_9K, false),
c2218925 249 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
251 JUMBO_9K, false),
c2218925 252 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 253 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
254 JUMBO_9K, false),
7e18dca1
HW		 255 [RTL_GIGA_MAC_VER_37] =
256 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
257 JUMBO_1K, true),
b3d7b2f2
HW		 258 [RTL_GIGA_MAC_VER_38] =
259 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
260 JUMBO_9K, false),
5598bfe5
HW		 261 [RTL_GIGA_MAC_VER_39] =
262 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
263 JUMBO_1K, true),
c558386b 264 [RTL_GIGA_MAC_VER_40] =
beb330a4 265 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_41] =
268 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
953a12cc 269};
85bffe6c 270#undef _R
953a12cc 271
bcf0bf90
FR		 272enum cfg_version {
273 RTL_CFG_0 = 0x00,
274 RTL_CFG_1,
275 RTL_CFG_2
276};
277
a3aa1884 278static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 279 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 280 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 281 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 282 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 283 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 284 { PCI_VENDOR_ID_DLINK, 0x4300,
285 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 286 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 287 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 288 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 289 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
290 { PCI_VENDOR_ID_LINKSYS, 0x1032,
291 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 292 { 0x0001, 0x8168,
293 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 294 {0,},
295};
296
297MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
298
6f0333b8 299static int rx_buf_sz = 16383;
4300e8c7 300static int use_dac;
b57b7e5a
SH		 301static struct {
302 u32 msg_enable;
303} debug = { -1 };
1da177e4 304
07d3f51f
FR		 305enum rtl_registers {
306 MAC0 = 0, /* Ethernet hardware address. */
773d2021 307 MAC4 = 4,
07d3f51f
FR		 308 MAR0 = 8, /* Multicast filter. */
309 CounterAddrLow = 0x10,
310 CounterAddrHigh = 0x14,
311 TxDescStartAddrLow = 0x20,
312 TxDescStartAddrHigh = 0x24,
313 TxHDescStartAddrLow = 0x28,
314 TxHDescStartAddrHigh = 0x2c,
315 FLASH = 0x30,
316 ERSR = 0x36,
317 ChipCmd = 0x37,
318 TxPoll = 0x38,
319 IntrMask = 0x3c,
320 IntrStatus = 0x3e,
4f6b00e5 321
07d3f51f 322 TxConfig = 0x40,
4f6b00e5
HW		 323#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
324#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 325
4f6b00e5
HW		 326 RxConfig = 0x44,
327#define RX128_INT_EN (1 << 15) /* 8111c and later */
328#define RX_MULTI_EN (1 << 14) /* 8111c only */
329#define RXCFG_FIFO_SHIFT 13
330 /* No threshold before first PCI xfer */
331#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 332#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 333#define RXCFG_DMA_SHIFT 8
334 /* Unlimited maximum PCI burst. */
335#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 336
07d3f51f
FR		 337 RxMissed = 0x4c,
338 Cfg9346 = 0x50,
339 Config0 = 0x51,
340 Config1 = 0x52,
341 Config2 = 0x53,
d387b427
FR		 342#define PME_SIGNAL (1 << 5) /* 8168c and later */
343
07d3f51f
FR		 344 Config3 = 0x54,
345 Config4 = 0x55,
346 Config5 = 0x56,
347 MultiIntr = 0x5c,
348 PHYAR = 0x60,
07d3f51f
FR		 349 PHYstatus = 0x6c,
350 RxMaxSize = 0xda,
351 CPlusCmd = 0xe0,
352 IntrMitigate = 0xe2,
353 RxDescAddrLow = 0xe4,
354 RxDescAddrHigh = 0xe8,
f0298f81 355 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
356
357#define NoEarlyTx 0x3f /* Max value : no early transmit. */
358
359 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
360
361#define TxPacketMax (8064 >> 7)
3090bd9a 362#define EarlySize 0x27
f0298f81 363
07d3f51f
FR		 364 FuncEvent = 0xf0,
365 FuncEventMask = 0xf4,
366 FuncPresetState = 0xf8,
367 FuncForceEvent = 0xfc,
1da177e4
LT		 368};
369
f162a5d1
FR		 370enum rtl8110_registers {
371 TBICSR = 0x64,
372 TBI_ANAR = 0x68,
373 TBI_LPAR = 0x6a,
374};
375
376enum rtl8168_8101_registers {
377 CSIDR = 0x64,
378 CSIAR = 0x68,
379#define CSIAR_FLAG 0x80000000
380#define CSIAR_WRITE_CMD 0x80000000
381#define CSIAR_BYTE_ENABLE 0x0f
382#define CSIAR_BYTE_ENABLE_SHIFT 12
383#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 384#define CSIAR_FUNC_CARD 0x00000000
385#define CSIAR_FUNC_SDIO 0x00010000
386#define CSIAR_FUNC_NIC 0x00020000
065c27c1 387 PMCH = 0x6f,
f162a5d1
FR		 388 EPHYAR = 0x80,
389#define EPHYAR_FLAG 0x80000000
390#define EPHYAR_WRITE_CMD 0x80000000
391#define EPHYAR_REG_MASK 0x1f
392#define EPHYAR_REG_SHIFT 16
393#define EPHYAR_DATA_MASK 0xffff
5a5e4443 394 DLLPR = 0xd0,
4f6b00e5 395#define PFM_EN (1 << 6)
f162a5d1
FR		 396 DBG_REG = 0xd1,
397#define FIX_NAK_1 (1 << 4)
398#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 399 TWSI = 0xd2,
400 MCU = 0xd3,
4f6b00e5 401#define NOW_IS_OOB (1 << 7)
c558386b
HW		 402#define TX_EMPTY (1 << 5)
403#define RX_EMPTY (1 << 4)
404#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 405#define EN_NDP (1 << 3)
406#define EN_OOB_RESET (1 << 2)
c558386b 407#define LINK_LIST_RDY (1 << 1)
daf9df6d 408 EFUSEAR = 0xdc,
409#define EFUSEAR_FLAG 0x80000000
410#define EFUSEAR_WRITE_CMD 0x80000000
411#define EFUSEAR_READ_CMD 0x00000000
412#define EFUSEAR_REG_MASK 0x03ff
413#define EFUSEAR_REG_SHIFT 8
414#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 415};
416
c0e45c1c 417enum rtl8168_registers {
4f6b00e5
HW		 418 LED_FREQ = 0x1a,
419 EEE_LED = 0x1b,
b646d900 420 ERIDR = 0x70,
421 ERIAR = 0x74,
422#define ERIAR_FLAG 0x80000000
423#define ERIAR_WRITE_CMD 0x80000000
424#define ERIAR_READ_CMD 0x00000000
425#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 426#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 427#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
428#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
429#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
430#define ERIAR_MASK_SHIFT 12
431#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
432#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 433#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 434#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 435 EPHY_RXER_NUM = 0x7c,
436 OCPDR = 0xb0, /* OCP GPHY access */
437#define OCPDR_WRITE_CMD 0x80000000
438#define OCPDR_READ_CMD 0x00000000
439#define OCPDR_REG_MASK 0x7f
440#define OCPDR_GPHY_REG_SHIFT 16
441#define OCPDR_DATA_MASK 0xffff
442 OCPAR = 0xb4,
443#define OCPAR_FLAG 0x80000000
444#define OCPAR_GPHY_WRITE_CMD 0x8000f060
445#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 446 GPHY_OCP = 0xb8,
01dc7fec 447 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
448 MISC = 0xf0, /* 8168e only. */
cecb5fd7 449#define TXPLA_RST (1 << 29)
5598bfe5 450#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 451#define PWM_EN (1 << 22)
c558386b 452#define RXDV_GATED_EN (1 << 19)
5598bfe5 453#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 454};
455
07d3f51f 456enum rtl_register_content {
1da177e4 457 /* InterruptStatusBits */
07d3f51f
FR		 458 SYSErr = 0x8000,
459 PCSTimeout = 0x4000,
460 SWInt = 0x0100,
461 TxDescUnavail = 0x0080,
462 RxFIFOOver = 0x0040,
463 LinkChg = 0x0020,
464 RxOverflow = 0x0010,
465 TxErr = 0x0008,
466 TxOK = 0x0004,
467 RxErr = 0x0002,
468 RxOK = 0x0001,
1da177e4
LT		 469
470 /* RxStatusDesc */
e03f33af 471 RxBOVF = (1 << 24),
9dccf611
FR		 472 RxFOVF = (1 << 23),
473 RxRWT = (1 << 22),
474 RxRES = (1 << 21),
475 RxRUNT = (1 << 20),
476 RxCRC = (1 << 19),
1da177e4
LT		 477
478 /* ChipCmdBits */
4f6b00e5 479 StopReq = 0x80,
07d3f51f
FR		 480 CmdReset = 0x10,
481 CmdRxEnb = 0x08,
482 CmdTxEnb = 0x04,
483 RxBufEmpty = 0x01,
1da177e4 484
275391a4
FR		 485 /* TXPoll register p.5 */
486 HPQ = 0x80, /* Poll cmd on the high prio queue */
487 NPQ = 0x40, /* Poll cmd on the low prio queue */
488 FSWInt = 0x01, /* Forced software interrupt */
489
1da177e4 490 /* Cfg9346Bits */
07d3f51f
FR		 491 Cfg9346_Lock = 0x00,
492 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 493
494 /* rx_mode_bits */
07d3f51f
FR		 495 AcceptErr = 0x20,
496 AcceptRunt = 0x10,
497 AcceptBroadcast = 0x08,
498 AcceptMulticast = 0x04,
499 AcceptMyPhys = 0x02,
500 AcceptAllPhys = 0x01,
1687b566 501#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 502
1da177e4
LT		 503 /* TxConfigBits */
504 TxInterFrameGapShift = 24,
505 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
506
5d06a99f 507 /* Config1 register p.24 */
f162a5d1
FR		 508 LEDS1 = (1 << 7),
509 LEDS0 = (1 << 6),
f162a5d1
FR		 510 Speed_down = (1 << 4),
511 MEMMAP = (1 << 3),
512 IOMAP = (1 << 2),
513 VPD = (1 << 1),
5d06a99f
FR		 514 PMEnable = (1 << 0), /* Power Management Enable */
515
6dccd16b 516 /* Config2 register p. 25 */
2ca6cf06 517 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 518 PCI_Clock_66MHz = 0x01,
519 PCI_Clock_33MHz = 0x00,
520
61a4dcc2
FR		 521 /* Config3 register p.25 */
522 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
523 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 524 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 525 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 526
d58d46b5
FR		 527 /* Config4 register */
528 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
529
5d06a99f 530 /* Config5 register p.27 */
61a4dcc2
FR		 531 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
532 MWF = (1 << 5), /* Accept Multicast wakeup frame */
533 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 534 Spi_en = (1 << 3),
61a4dcc2 535 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 536 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
537
1da177e4
LT		 538 /* TBICSR p.28 */
539 TBIReset = 0x80000000,
540 TBILoopback = 0x40000000,
541 TBINwEnable = 0x20000000,
542 TBINwRestart = 0x10000000,
543 TBILinkOk = 0x02000000,
544 TBINwComplete = 0x01000000,
545
546 /* CPlusCmd p.31 */
f162a5d1
FR		 547 EnableBist = (1 << 15), // 8168 8101
548 Mac_dbgo_oe = (1 << 14), // 8168 8101
549 Normal_mode = (1 << 13), // unused
550 Force_half_dup = (1 << 12), // 8168 8101
551 Force_rxflow_en = (1 << 11), // 8168 8101
552 Force_txflow_en = (1 << 10), // 8168 8101
553 Cxpl_dbg_sel = (1 << 9), // 8168 8101
554 ASF = (1 << 8), // 8168 8101
555 PktCntrDisable = (1 << 7), // 8168 8101
556 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 557 RxVlan = (1 << 6),
558 RxChkSum = (1 << 5),
559 PCIDAC = (1 << 4),
560 PCIMulRW = (1 << 3),
0e485150
FR		 561 INTT_0 = 0x0000, // 8168
562 INTT_1 = 0x0001, // 8168
563 INTT_2 = 0x0002, // 8168
564 INTT_3 = 0x0003, // 8168
1da177e4
LT		 565
566 /* rtl8169_PHYstatus */
07d3f51f
FR		 567 TBI_Enable = 0x80,
568 TxFlowCtrl = 0x40,
569 RxFlowCtrl = 0x20,
570 _1000bpsF = 0x10,
571 _100bps = 0x08,
572 _10bps = 0x04,
573 LinkStatus = 0x02,
574 FullDup = 0x01,
1da177e4 575
1da177e4 576 /* _TBICSRBit */
07d3f51f 577 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 578
579 /* DumpCounterCommand */
07d3f51f 580 CounterDump = 0x8,
1da177e4
LT		 581};
582
2b7b4318
FR		 583enum rtl_desc_bit {
584 /* First doubleword. */
1da177e4
LT		 585 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
586 RingEnd = (1 << 30), /* End of descriptor ring */
587 FirstFrag = (1 << 29), /* First segment of a packet */
588 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 589};
590
591/* Generic case. */
592enum rtl_tx_desc_bit {
593 /* First doubleword. */
594 TD_LSO = (1 << 27), /* Large Send Offload */
595#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 596
2b7b4318
FR		 597 /* Second doubleword. */
598 TxVlanTag = (1 << 17), /* Add VLAN tag */
599};
600
601/* 8169, 8168b and 810x except 8102e. */
602enum rtl_tx_desc_bit_0 {
603 /* First doubleword. */
604#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
605 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
606 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
607 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
608};
609
610/* 8102e, 8168c and beyond. */
611enum rtl_tx_desc_bit_1 {
612 /* Second doubleword. */
613#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
614 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
615 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
616 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
617};
1da177e4 618
2b7b4318
FR		 619static const struct rtl_tx_desc_info {
620 struct {
621 u32 udp;
622 u32 tcp;
623 } checksum;
624 u16 mss_shift;
625 u16 opts_offset;
626} tx_desc_info [] = {
627 [RTL_TD_0] = {
628 .checksum = {
629 .udp = TD0_IP_CS | TD0_UDP_CS,
630 .tcp = TD0_IP_CS | TD0_TCP_CS
631 },
632 .mss_shift = TD0_MSS_SHIFT,
633 .opts_offset = 0
634 },
635 [RTL_TD_1] = {
636 .checksum = {
637 .udp = TD1_IP_CS | TD1_UDP_CS,
638 .tcp = TD1_IP_CS | TD1_TCP_CS
639 },
640 .mss_shift = TD1_MSS_SHIFT,
641 .opts_offset = 1
642 }
643};
644
645enum rtl_rx_desc_bit {
1da177e4
LT		 646 /* Rx private */
647 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
648 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
649
650#define RxProtoUDP (PID1)
651#define RxProtoTCP (PID0)
652#define RxProtoIP (PID1 | PID0)
653#define RxProtoMask RxProtoIP
654
655 IPFail = (1 << 16), /* IP checksum failed */
656 UDPFail = (1 << 15), /* UDP/IP checksum failed */
657 TCPFail = (1 << 14), /* TCP/IP checksum failed */
658 RxVlanTag = (1 << 16), /* VLAN tag available */
659};
660
661#define RsvdMask 0x3fffc000
662
663struct TxDesc {
6cccd6e7
REB		 664 __le32 opts1;
665 __le32 opts2;
666 __le64 addr;
1da177e4
LT		 667};
668
669struct RxDesc {
6cccd6e7
REB		 670 __le32 opts1;
671 __le32 opts2;
672 __le64 addr;
1da177e4
LT		 673};
674
675struct ring_info {
676 struct sk_buff *skb;
677 u32 len;
678 u8 __pad[sizeof(void *) - sizeof(u32)];
679};
680
f23e7fda 681enum features {
ccdffb9a
FR		 682 RTL_FEATURE_WOL = (1 << 0),
683 RTL_FEATURE_MSI = (1 << 1),
684 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 685};
686
355423d0
IV		 687struct rtl8169_counters {
688 __le64 tx_packets;
689 __le64 rx_packets;
690 __le64 tx_errors;
691 __le32 rx_errors;
692 __le16 rx_missed;
693 __le16 align_errors;
694 __le32 tx_one_collision;
695 __le32 tx_multi_collision;
696 __le64 rx_unicast;
697 __le64 rx_broadcast;
698 __le32 rx_multicast;
699 __le16 tx_aborted;
700 __le16 tx_underun;
701};
702
da78dbff 703enum rtl_flag {
6c4a70c5 704 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 705 RTL_FLAG_TASK_SLOW_PENDING,
706 RTL_FLAG_TASK_RESET_PENDING,
707 RTL_FLAG_TASK_PHY_PENDING,
708 RTL_FLAG_MAX
709};
710
8027aa24
JW		 711struct rtl8169_stats {
712 u64 packets;
713 u64 bytes;
714 struct u64_stats_sync syncp;
715};
716
1da177e4
LT		 717struct rtl8169_private {
718 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 719 struct pci_dev *pci_dev;
c4028958 720 struct net_device *dev;
bea3348e 721 struct napi_struct napi;
b57b7e5a 722 u32 msg_enable;
2b7b4318
FR		 723 u16 txd_version;
724 u16 mac_version;
1da177e4
LT		 725 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
726 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 727 u32 dirty_tx;
8027aa24
JW		 728 struct rtl8169_stats rx_stats;
729 struct rtl8169_stats tx_stats;
1da177e4
LT		 730 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
731 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
732 dma_addr_t TxPhyAddr;
733 dma_addr_t RxPhyAddr;
6f0333b8 734 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 735 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 736 struct timer_list timer;
737 u16 cp_cmd;
da78dbff
FR		 738
739 u16 event_slow;
c0e45c1c 740
741 struct mdio_ops {
24192210
FR		 742 void (*write)(struct rtl8169_private *, int, int);
743 int (*read)(struct rtl8169_private *, int);
c0e45c1c 744 } mdio_ops;
745
065c27c1 746 struct pll_power_ops {
747 void (*down)(struct rtl8169_private *);
748 void (*up)(struct rtl8169_private *);
749 } pll_power_ops;
750
d58d46b5
FR		 751 struct jumbo_ops {
752 void (*enable)(struct rtl8169_private *);
753 void (*disable)(struct rtl8169_private *);
754 } jumbo_ops;
755
beb1fe18 756 struct csi_ops {
52989f0e
FR		 757 void (*write)(struct rtl8169_private *, int, int);
758 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 759 } csi_ops;
760
54405cde 761 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 762 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 763 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 764 void (*hw_start)(struct net_device *);
4da19633 765 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 766 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 767 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 768
769 struct {
da78dbff
FR		 770 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
771 struct mutex mutex;
4422bcd4
FR		 772 struct work_struct work;
773 } wk;
774
f23e7fda 775 unsigned features;
ccdffb9a
FR		 776
777 struct mii_if_info mii;
355423d0 778 struct rtl8169_counters counters;
e1759441 779 u32 saved_wolopts;
e03f33af 780 u32 opts1_mask;
f1e02ed1 781
b6ffd97f
FR		 782 struct rtl_fw {
783 const struct firmware *fw;
1c361efb
FR		 784
785#define RTL_VER_SIZE 32
786
787 char version[RTL_VER_SIZE];
788
789 struct rtl_fw_phy_action {
790 __le32 *code;
791 size_t size;
792 } phy_action;
b6ffd97f 793 } *rtl_fw;
497888cf 794#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 795
796 u32 ocp_base;
1da177e4
LT		 797};
798
979b6c13 799MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 800MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 801module_param(use_dac, int, 0);
4300e8c7 802MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 803module_param_named(debug, debug.msg_enable, int, 0);
804MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 805MODULE_LICENSE("GPL");
806MODULE_VERSION(RTL8169_VERSION);
bca03d5f 807MODULE_FIRMWARE(FIRMWARE_8168D_1);
808MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 809MODULE_FIRMWARE(FIRMWARE_8168E_1);
810MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 811MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 812MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 813MODULE_FIRMWARE(FIRMWARE_8168F_1);
814MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 815MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 816MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 817MODULE_FIRMWARE(FIRMWARE_8106E_1);
beb330a4 818MODULE_FIRMWARE(FIRMWARE_8168G_2);
1da177e4 819
da78dbff
FR		 820static void rtl_lock_work(struct rtl8169_private *tp)
821{
822 mutex_lock(&tp->wk.mutex);
823}
824
825static void rtl_unlock_work(struct rtl8169_private *tp)
826{
827 mutex_unlock(&tp->wk.mutex);
828}
829
d58d46b5
FR		 830static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
831{
7d7903b2
JL		 832 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
833 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 834}
835
ffc46952
FR		 836struct rtl_cond {
837 bool (*check)(struct rtl8169_private *);
838 const char *msg;
839};
840
841static void rtl_udelay(unsigned int d)
842{
843 udelay(d);
844}
845
846static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
847 void (*delay)(unsigned int), unsigned int d, int n,
848 bool high)
849{
850 int i;
851
852 for (i = 0; i < n; i++) {
853 delay(d);
854 if (c->check(tp) == high)
855 return true;
856 }
82e316ef
FR		 857 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
858 c->msg, !high, n, d);
ffc46952
FR		 859 return false;
860}
861
862static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
863 const struct rtl_cond *c,
864 unsigned int d, int n)
865{
866 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
867}
868
869static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
870 const struct rtl_cond *c,
871 unsigned int d, int n)
872{
873 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
874}
875
876static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
877 const struct rtl_cond *c,
878 unsigned int d, int n)
879{
880 return rtl_loop_wait(tp, c, msleep, d, n, true);
881}
882
883static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
884 const struct rtl_cond *c,
885 unsigned int d, int n)
886{
887 return rtl_loop_wait(tp, c, msleep, d, n, false);
888}
889
890#define DECLARE_RTL_COND(name) \
891static bool name ## _check(struct rtl8169_private *); \
892 \
893static const struct rtl_cond name = { \
894 .check = name ## _check, \
895 .msg = #name \
896}; \
897 \
898static bool name ## _check(struct rtl8169_private *tp)
899
900DECLARE_RTL_COND(rtl_ocpar_cond)
901{
902 void __iomem *ioaddr = tp->mmio_addr;
903
904 return RTL_R32(OCPAR) & OCPAR_FLAG;
905}
906
b646d900 907static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
908{
909 void __iomem *ioaddr = tp->mmio_addr;
b646d900 910
911 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 912
913 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
914 RTL_R32(OCPDR) : ~0;
b646d900 915}
916
917static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
918{
919 void __iomem *ioaddr = tp->mmio_addr;
b646d900 920
921 RTL_W32(OCPDR, data);
922 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 923
924 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
925}
926
927DECLARE_RTL_COND(rtl_eriar_cond)
928{
929 void __iomem *ioaddr = tp->mmio_addr;
930
931 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 932}
933
fac5b3ca 934static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 935{
fac5b3ca 936 void __iomem *ioaddr = tp->mmio_addr;
b646d900 937
938 RTL_W8(ERIDR, cmd);
939 RTL_W32(ERIAR, 0x800010e8);
940 msleep(2);
ffc46952
FR		 941
942 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
943 return;
b646d900 944
fac5b3ca 945 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 946}
947
948#define OOB_CMD_RESET 0x00
949#define OOB_CMD_DRIVER_START 0x05
950#define OOB_CMD_DRIVER_STOP 0x06
951
cecb5fd7
FR		 952static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
953{
954 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
955}
956
ffc46952 957DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 958{
cecb5fd7 959 u16 reg;
b646d900 960
cecb5fd7 961 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 962
ffc46952 963 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 964}
965
ffc46952 966static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 967{
ffc46952 968 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 969
ffc46952
FR		 970 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
971}
b646d900 972
ffc46952
FR		 973static void rtl8168_driver_stop(struct rtl8169_private *tp)
974{
975 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 976
ffc46952 977 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 978}
979
4804b3b3 980static int r8168dp_check_dash(struct rtl8169_private *tp)
981{
cecb5fd7 982 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 983
cecb5fd7 984 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 985}
b646d900 986
c558386b
HW		 987static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
988{
989 if (reg & 0xffff0001) {
990 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
991 return true;
992 }
993 return false;
994}
995
996DECLARE_RTL_COND(rtl_ocp_gphy_cond)
997{
998 void __iomem *ioaddr = tp->mmio_addr;
999
1000 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1001}
1002
1003static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1004{
1005 void __iomem *ioaddr = tp->mmio_addr;
1006
1007 if (rtl_ocp_reg_failure(tp, reg))
1008 return;
1009
1010 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1011
1012 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1013}
1014
1015static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1016{
1017 void __iomem *ioaddr = tp->mmio_addr;
1018
1019 if (rtl_ocp_reg_failure(tp, reg))
1020 return 0;
1021
1022 RTL_W32(GPHY_OCP, reg << 15);
1023
1024 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1025 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1026}
1027
c558386b
HW		 1028static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1029{
1030 void __iomem *ioaddr = tp->mmio_addr;
1031
1032 if (rtl_ocp_reg_failure(tp, reg))
1033 return;
1034
1035 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1036}
1037
1038static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1039{
1040 void __iomem *ioaddr = tp->mmio_addr;
1041
1042 if (rtl_ocp_reg_failure(tp, reg))
1043 return 0;
1044
1045 RTL_W32(OCPDR, reg << 15);
1046
3a83ad12 1047 return RTL_R32(OCPDR);
c558386b
HW		 1048}
1049
1050#define OCP_STD_PHY_BASE 0xa400
1051
1052static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1053{
1054 if (reg == 0x1f) {
1055 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1056 return;
1057 }
1058
1059 if (tp->ocp_base != OCP_STD_PHY_BASE)
1060 reg -= 0x10;
1061
1062 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1063}
1064
1065static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1066{
1067 if (tp->ocp_base != OCP_STD_PHY_BASE)
1068 reg -= 0x10;
1069
1070 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1071}
1072
eee3786f 1073static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1074{
1075 if (reg == 0x1f) {
1076 tp->ocp_base = value << 4;
1077 return;
1078 }
1079
1080 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1081}
1082
1083static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1084{
1085 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1086}
1087
ffc46952
FR		 1088DECLARE_RTL_COND(rtl_phyar_cond)
1089{
1090 void __iomem *ioaddr = tp->mmio_addr;
1091
1092 return RTL_R32(PHYAR) & 0x80000000;
1093}
1094
24192210 1095static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1096{
24192210 1097 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1098
24192210 1099 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1100
ffc46952 1101 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1102 /*
81a95f04
TT		 1103 * According to hardware specs a 20us delay is required after write
1104 * complete indication, but before sending next command.
024a07ba 1105 */
81a95f04 1106 udelay(20);
1da177e4
LT		 1107}
1108
24192210 1109static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1110{
24192210 1111 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1112 int value;
1da177e4 1113
24192210 1114 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1115
ffc46952
FR		 1116 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1117 RTL_R32(PHYAR) & 0xffff : ~0;
1118
81a95f04
TT		 1119 /*
1120 * According to hardware specs a 20us delay is required after read
1121 * complete indication, but before sending next command.
1122 */
1123 udelay(20);
1124
1da177e4
LT		 1125 return value;
1126}
1127
24192210 1128static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1129{
24192210 1130 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1131
24192210 1132 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1133 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1134 RTL_W32(EPHY_RXER_NUM, 0);
1135
ffc46952 1136 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1137}
1138
24192210 1139static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1140{
24192210
FR		 1141 r8168dp_1_mdio_access(tp, reg,
1142 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1143}
1144
24192210 1145static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1146{
24192210 1147 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1148
24192210 1149 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1150
1151 mdelay(1);
1152 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1153 RTL_W32(EPHY_RXER_NUM, 0);
1154
ffc46952
FR		 1155 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1156 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1157}
1158
e6de30d6 1159#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1160
1161static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1162{
1163 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1164}
1165
1166static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1167{
1168 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1169}
1170
24192210 1171static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1172{
24192210
FR		 1173 void __iomem *ioaddr = tp->mmio_addr;
1174
e6de30d6 1175 r8168dp_2_mdio_start(ioaddr);
1176
24192210 1177 r8169_mdio_write(tp, reg, value);
e6de30d6 1178
1179 r8168dp_2_mdio_stop(ioaddr);
1180}
1181
24192210 1182static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1183{
24192210 1184 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1185 int value;
1186
1187 r8168dp_2_mdio_start(ioaddr);
1188
24192210 1189 value = r8169_mdio_read(tp, reg);
e6de30d6 1190
1191 r8168dp_2_mdio_stop(ioaddr);
1192
1193 return value;
1194}
1195
4da19633 1196static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1197{
24192210 1198 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1199}
1200
4da19633 1201static int rtl_readphy(struct rtl8169_private *tp, int location)
1202{
24192210 1203 return tp->mdio_ops.read(tp, location);
4da19633 1204}
1205
1206static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1207{
1208 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1209}
1210
1211static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1212{
1213 int val;
1214
4da19633 1215 val = rtl_readphy(tp, reg_addr);
1216 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1217}
1218
ccdffb9a
FR		 1219static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1220 int val)
1221{
1222 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1223
4da19633 1224 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1225}
1226
1227static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1228{
1229 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1230
4da19633 1231 return rtl_readphy(tp, location);
ccdffb9a
FR		 1232}
1233
ffc46952
FR		 1234DECLARE_RTL_COND(rtl_ephyar_cond)
1235{
1236 void __iomem *ioaddr = tp->mmio_addr;
1237
1238 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1239}
1240
fdf6fc06 1241static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1242{
fdf6fc06 1243 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1244
1245 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1246 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1247
ffc46952
FR		 1248 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1249
1250 udelay(10);
dacf8154
FR		 1251}
1252
fdf6fc06 1253static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1254{
fdf6fc06 1255 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1256
1257 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1258
ffc46952
FR		 1259 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1260 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1261}
1262
fdf6fc06
FR		 1263static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1264 u32 val, int type)
133ac40a 1265{
fdf6fc06 1266 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1267
1268 BUG_ON((addr & 3) || (mask == 0));
1269 RTL_W32(ERIDR, val);
1270 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1271
ffc46952 1272 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1273}
1274
fdf6fc06 1275static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1276{
fdf6fc06 1277 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1278
1279 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1280
ffc46952
FR		 1281 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1282 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1283}
1284
fdf6fc06
FR		 1285static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1286 u32 m, int type)
133ac40a
HW		 1287{
1288 u32 val;
1289
fdf6fc06
FR		 1290 val = rtl_eri_read(tp, addr, type);
1291 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1292}
1293
c28aa385 1294struct exgmac_reg {
1295 u16 addr;
1296 u16 mask;
1297 u32 val;
1298};
1299
fdf6fc06 1300static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1301 const struct exgmac_reg *r, int len)
1302{
1303 while (len-- > 0) {
fdf6fc06 1304 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1305 r++;
1306 }
1307}
1308
ffc46952
FR		 1309DECLARE_RTL_COND(rtl_efusear_cond)
1310{
1311 void __iomem *ioaddr = tp->mmio_addr;
1312
1313 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1314}
1315
fdf6fc06 1316static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1317{
fdf6fc06 1318 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1319
1320 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1321
ffc46952
FR		 1322 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1323 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1324}
1325
9085cdfa
FR		 1326static u16 rtl_get_events(struct rtl8169_private *tp)
1327{
1328 void __iomem *ioaddr = tp->mmio_addr;
1329
1330 return RTL_R16(IntrStatus);
1331}
1332
1333static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1334{
1335 void __iomem *ioaddr = tp->mmio_addr;
1336
1337 RTL_W16(IntrStatus, bits);
1338 mmiowb();
1339}
1340
1341static void rtl_irq_disable(struct rtl8169_private *tp)
1342{
1343 void __iomem *ioaddr = tp->mmio_addr;
1344
1345 RTL_W16(IntrMask, 0);
1346 mmiowb();
1347}
1348
3e990ff5
FR		 1349static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1350{
1351 void __iomem *ioaddr = tp->mmio_addr;
1352
1353 RTL_W16(IntrMask, bits);
1354}
1355
da78dbff
FR		 1356#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1357#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1358#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1359
1360static void rtl_irq_enable_all(struct rtl8169_private *tp)
1361{
1362 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1363}
1364
811fd301 1365static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1366{
811fd301 1367 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1368
9085cdfa 1369 rtl_irq_disable(tp);
da78dbff 1370 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1371 RTL_R8(ChipCmd);
1da177e4
LT		 1372}
1373
4da19633 1374static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1375{
4da19633 1376 void __iomem *ioaddr = tp->mmio_addr;
1377
1da177e4
LT		 1378 return RTL_R32(TBICSR) & TBIReset;
1379}
1380
4da19633 1381static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1382{
4da19633 1383 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1384}
1385
1386static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1387{
1388 return RTL_R32(TBICSR) & TBILinkOk;
1389}
1390
1391static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1392{
1393 return RTL_R8(PHYstatus) & LinkStatus;
1394}
1395
4da19633 1396static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1397{
4da19633 1398 void __iomem *ioaddr = tp->mmio_addr;
1399
1da177e4
LT		 1400 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1401}
1402
4da19633 1403static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1404{
1405 unsigned int val;
1406
4da19633 1407 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1408 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1409}
1410
70090424
HW		 1411static void rtl_link_chg_patch(struct rtl8169_private *tp)
1412{
1413 void __iomem *ioaddr = tp->mmio_addr;
1414 struct net_device *dev = tp->dev;
1415
1416 if (!netif_running(dev))
1417 return;
1418
b3d7b2f2
HW		 1419 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1420 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1421 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1422 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1423 ERIAR_EXGMAC);
1424 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1425 ERIAR_EXGMAC);
70090424 1426 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1427 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1428 ERIAR_EXGMAC);
1429 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1430 ERIAR_EXGMAC);
70090424 1431 } else {
fdf6fc06
FR		 1432 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1433 ERIAR_EXGMAC);
1434 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1435 ERIAR_EXGMAC);
70090424
HW		 1436 }
1437 /* Reset packet filter */
fdf6fc06 1438 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1439 ERIAR_EXGMAC);
fdf6fc06 1440 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1441 ERIAR_EXGMAC);
c2218925
HW		 1442 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1443 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1444 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1445 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1446 ERIAR_EXGMAC);
1447 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1448 ERIAR_EXGMAC);
c2218925 1449 } else {
fdf6fc06
FR		 1450 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1451 ERIAR_EXGMAC);
1452 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1453 ERIAR_EXGMAC);
c2218925 1454 }
7e18dca1
HW		 1455 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1456 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1457 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1458 ERIAR_EXGMAC);
1459 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1460 ERIAR_EXGMAC);
7e18dca1 1461 } else {
fdf6fc06
FR		 1462 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1463 ERIAR_EXGMAC);
7e18dca1 1464 }
70090424
HW		 1465 }
1466}
1467
e4fbce74 1468static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1469 struct rtl8169_private *tp,
1470 void __iomem *ioaddr, bool pm)
1da177e4 1471{
1da177e4 1472 if (tp->link_ok(ioaddr)) {
70090424 1473 rtl_link_chg_patch(tp);
e1759441 1474 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1475 if (pm)
1476 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1477 netif_carrier_on(dev);
1519e57f
FR		 1478 if (net_ratelimit())
1479 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1480 } else {
1da177e4 1481 netif_carrier_off(dev);
bf82c189 1482 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1483 if (pm)
10953db8 1484 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1485 }
1da177e4
LT		 1486}
1487
e4fbce74
RW		 1488static void rtl8169_check_link_status(struct net_device *dev,
1489 struct rtl8169_private *tp,
1490 void __iomem *ioaddr)
1491{
1492 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1493}
1494
e1759441
RW		 1495#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1496
1497static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1498{
61a4dcc2
FR		 1499 void __iomem *ioaddr = tp->mmio_addr;
1500 u8 options;
e1759441 1501 u32 wolopts = 0;
61a4dcc2
FR		 1502
1503 options = RTL_R8(Config1);
1504 if (!(options & PMEnable))
e1759441 1505 return 0;
61a4dcc2
FR		 1506
1507 options = RTL_R8(Config3);
1508 if (options & LinkUp)
e1759441 1509 wolopts |= WAKE_PHY;
61a4dcc2 1510 if (options & MagicPacket)
e1759441 1511 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1512
1513 options = RTL_R8(Config5);
1514 if (options & UWF)
e1759441 1515 wolopts |= WAKE_UCAST;
61a4dcc2 1516 if (options & BWF)
e1759441 1517 wolopts |= WAKE_BCAST;
61a4dcc2 1518 if (options & MWF)
e1759441 1519 wolopts |= WAKE_MCAST;
61a4dcc2 1520
e1759441 1521 return wolopts;
61a4dcc2
FR		 1522}
1523
e1759441 1524static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1525{
1526 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1527
da78dbff 1528 rtl_lock_work(tp);
e1759441
RW		 1529
1530 wol->supported = WAKE_ANY;
1531 wol->wolopts = __rtl8169_get_wol(tp);
1532
da78dbff 1533 rtl_unlock_work(tp);
e1759441
RW		 1534}
1535
1536static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1537{
61a4dcc2 1538 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1539 unsigned int i;
350f7596 1540 static const struct {
61a4dcc2
FR		 1541 u32 opt;
1542 u16 reg;
1543 u8 mask;
1544 } cfg[] = {
61a4dcc2
FR		 1545 { WAKE_PHY, Config3, LinkUp },
1546 { WAKE_MAGIC, Config3, MagicPacket },
1547 { WAKE_UCAST, Config5, UWF },
1548 { WAKE_BCAST, Config5, BWF },
1549 { WAKE_MCAST, Config5, MWF },
1550 { WAKE_ANY, Config5, LanWake }
1551 };
851e6022 1552 u8 options;
61a4dcc2 1553
61a4dcc2
FR		 1554 RTL_W8(Cfg9346, Cfg9346_Unlock);
1555
1556 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1557 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1558 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1559 options |= cfg[i].mask;
1560 RTL_W8(cfg[i].reg, options);
1561 }
1562
851e6022
FR		 1563 switch (tp->mac_version) {
1564 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1565 options = RTL_R8(Config1) & ~PMEnable;
1566 if (wolopts)
1567 options |= PMEnable;
1568 RTL_W8(Config1, options);
1569 break;
1570 default:
d387b427
FR		 1571 options = RTL_R8(Config2) & ~PME_SIGNAL;
1572 if (wolopts)
1573 options |= PME_SIGNAL;
1574 RTL_W8(Config2, options);
851e6022
FR		 1575 break;
1576 }
1577
61a4dcc2 1578 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1579}
1580
1581static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1582{
1583 struct rtl8169_private *tp = netdev_priv(dev);
1584
da78dbff 1585 rtl_lock_work(tp);
61a4dcc2 1586
f23e7fda
FR		 1587 if (wol->wolopts)
1588 tp->features |= RTL_FEATURE_WOL;
1589 else
1590 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1591 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1592
1593 rtl_unlock_work(tp);
61a4dcc2 1594
ea80907f 1595 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1596
61a4dcc2
FR		 1597 return 0;
1598}
1599
31bd204f
FR		 1600static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1601{
85bffe6c 1602 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1603}
1604
1da177e4
LT		 1605static void rtl8169_get_drvinfo(struct net_device *dev,
1606 struct ethtool_drvinfo *info)
1607{
1608 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1609 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1610
68aad78c
RJ		 1611 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1612 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1613 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1614 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1615 if (!IS_ERR_OR_NULL(rtl_fw))
1616 strlcpy(info->fw_version, rtl_fw->version,
1617 sizeof(info->fw_version));
1da177e4
LT		 1618}
1619
1620static int rtl8169_get_regs_len(struct net_device *dev)
1621{
1622 return R8169_REGS_SIZE;
1623}
1624
1625static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1626 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1627{
1628 struct rtl8169_private *tp = netdev_priv(dev);
1629 void __iomem *ioaddr = tp->mmio_addr;
1630 int ret = 0;
1631 u32 reg;
1632
1633 reg = RTL_R32(TBICSR);
1634 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1635 (duplex == DUPLEX_FULL)) {
1636 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1637 } else if (autoneg == AUTONEG_ENABLE)
1638 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1639 else {
bf82c189
JP		 1640 netif_warn(tp, link, dev,
1641 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1642 ret = -EOPNOTSUPP;
1643 }
1644
1645 return ret;
1646}
1647
1648static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1649 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1650{
1651 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1652 int giga_ctrl, bmcr;
54405cde 1653 int rc = -EINVAL;
1da177e4 1654
716b50a3 1655 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1656
1657 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1658 int auto_nego;
1659
4da19633 1660 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1661 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1662 ADVERTISE_100HALF | ADVERTISE_100FULL);
1663
1664 if (adv & ADVERTISED_10baseT_Half)
1665 auto_nego |= ADVERTISE_10HALF;
1666 if (adv & ADVERTISED_10baseT_Full)
1667 auto_nego |= ADVERTISE_10FULL;
1668 if (adv & ADVERTISED_100baseT_Half)
1669 auto_nego |= ADVERTISE_100HALF;
1670 if (adv & ADVERTISED_100baseT_Full)
1671 auto_nego |= ADVERTISE_100FULL;
1672
3577aa1b 1673 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1674
4da19633 1675 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1676 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1677
3577aa1b 1678 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1679 if (tp->mii.supports_gmii) {
54405cde
ON		 1680 if (adv & ADVERTISED_1000baseT_Half)
1681 giga_ctrl |= ADVERTISE_1000HALF;
1682 if (adv & ADVERTISED_1000baseT_Full)
1683 giga_ctrl |= ADVERTISE_1000FULL;
1684 } else if (adv & (ADVERTISED_1000baseT_Half |
1685 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1686 netif_info(tp, link, dev,
1687 "PHY does not support 1000Mbps\n");
54405cde 1688 goto out;
bcf0bf90 1689 }
1da177e4 1690
3577aa1b 1691 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1692
4da19633 1693 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1694 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1695 } else {
1696 giga_ctrl = 0;
1697
1698 if (speed == SPEED_10)
1699 bmcr = 0;
1700 else if (speed == SPEED_100)
1701 bmcr = BMCR_SPEED100;
1702 else
54405cde 1703 goto out;
3577aa1b 1704
1705 if (duplex == DUPLEX_FULL)
1706 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1707 }
1708
4da19633 1709 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1710
cecb5fd7
FR		 1711 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1712 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1713 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1714 rtl_writephy(tp, 0x17, 0x2138);
1715 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1716 } else {
4da19633 1717 rtl_writephy(tp, 0x17, 0x2108);
1718 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1719 }
1720 }
1721
54405cde
ON		 1722 rc = 0;
1723out:
1724 return rc;
1da177e4
LT		 1725}
1726
1727static int rtl8169_set_speed(struct net_device *dev,
54405cde 1728 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1729{
1730 struct rtl8169_private *tp = netdev_priv(dev);
1731 int ret;
1732
54405cde 1733 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1734 if (ret < 0)
1735 goto out;
1da177e4 1736
4876cc1e
FR		 1737 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1738 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1739 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1740 }
1741out:
1da177e4
LT		 1742 return ret;
1743}
1744
1745static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1746{
1747 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1748 int ret;
1749
4876cc1e
FR		 1750 del_timer_sync(&tp->timer);
1751
da78dbff 1752 rtl_lock_work(tp);
cecb5fd7 1753 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1754 cmd->duplex, cmd->advertising);
da78dbff 1755 rtl_unlock_work(tp);
5b0384f4 1756
1da177e4
LT		 1757 return ret;
1758}
1759
c8f44aff
MM		 1760static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1761 netdev_features_t features)
1da177e4 1762{
d58d46b5
FR		 1763 struct rtl8169_private *tp = netdev_priv(dev);
1764
2b7b4318 1765 if (dev->mtu > TD_MSS_MAX)
350fb32a 1766 features &= ~NETIF_F_ALL_TSO;
1da177e4 1767
d58d46b5
FR		 1768 if (dev->mtu > JUMBO_1K &&
1769 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1770 features &= ~NETIF_F_IP_CSUM;
1771
350fb32a 1772 return features;
1da177e4
LT		 1773}
1774
da78dbff
FR		 1775static void __rtl8169_set_features(struct net_device *dev,
1776 netdev_features_t features)
1da177e4
LT		 1777{
1778 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1779 netdev_features_t changed = features ^ dev->features;
da78dbff 1780 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1781
6bbe021d
BG		 1782 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1783 return;
1da177e4 1784
6bbe021d
BG		 1785 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1786 if (features & NETIF_F_RXCSUM)
1787 tp->cp_cmd |= RxChkSum;
1788 else
1789 tp->cp_cmd &= ~RxChkSum;
350fb32a 1790
6bbe021d
BG		 1791 if (dev->features & NETIF_F_HW_VLAN_RX)
1792 tp->cp_cmd |= RxVlan;
1793 else
1794 tp->cp_cmd &= ~RxVlan;
1795
1796 RTL_W16(CPlusCmd, tp->cp_cmd);
1797 RTL_R16(CPlusCmd);
1798 }
1799 if (changed & NETIF_F_RXALL) {
1800 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1801 if (features & NETIF_F_RXALL)
1802 tmp |= (AcceptErr | AcceptRunt);
1803 RTL_W32(RxConfig, tmp);
1804 }
da78dbff 1805}
1da177e4 1806
da78dbff
FR		 1807static int rtl8169_set_features(struct net_device *dev,
1808 netdev_features_t features)
1809{
1810 struct rtl8169_private *tp = netdev_priv(dev);
1811
1812 rtl_lock_work(tp);
1813 __rtl8169_set_features(dev, features);
1814 rtl_unlock_work(tp);
1da177e4
LT		 1815
1816 return 0;
1817}
1818
da78dbff 1819
810f4893 1820static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1821{
eab6d18d 1822 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1823 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1824}
1825
7a8fc77b 1826static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1827{
1828 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1829
7a8fc77b
FR		 1830 if (opts2 & RxVlanTag)
1831 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1da177e4
LT		 1832}
1833
ccdffb9a 1834static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1835{
1836 struct rtl8169_private *tp = netdev_priv(dev);
1837 void __iomem *ioaddr = tp->mmio_addr;
1838 u32 status;
1839
1840 cmd->supported =
1841 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1842 cmd->port = PORT_FIBRE;
1843 cmd->transceiver = XCVR_INTERNAL;
1844
1845 status = RTL_R32(TBICSR);
1846 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1847 cmd->autoneg = !!(status & TBINwEnable);
1848
70739497 1849 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1850 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1851
1852 return 0;
1da177e4
LT		 1853}
1854
ccdffb9a 1855static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1856{
1857 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1858
1859 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1860}
1861
1862static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1863{
1864 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1865 int rc;
1da177e4 1866
da78dbff 1867 rtl_lock_work(tp);
ccdffb9a 1868 rc = tp->get_settings(dev, cmd);
da78dbff 1869 rtl_unlock_work(tp);
1da177e4 1870
ccdffb9a 1871 return rc;
1da177e4
LT		 1872}
1873
1874static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1875 void *p)
1876{
5b0384f4 1877 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1878
5b0384f4
FR		 1879 if (regs->len > R8169_REGS_SIZE)
1880 regs->len = R8169_REGS_SIZE;
1da177e4 1881
da78dbff 1882 rtl_lock_work(tp);
5b0384f4 1883 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1884 rtl_unlock_work(tp);
1da177e4
LT		 1885}
1886
b57b7e5a
SH		 1887static u32 rtl8169_get_msglevel(struct net_device *dev)
1888{
1889 struct rtl8169_private *tp = netdev_priv(dev);
1890
1891 return tp->msg_enable;
1892}
1893
1894static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1895{
1896 struct rtl8169_private *tp = netdev_priv(dev);
1897
1898 tp->msg_enable = value;
1899}
1900
d4a3a0fc
SH		 1901static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1902 "tx_packets",
1903 "rx_packets",
1904 "tx_errors",
1905 "rx_errors",
1906 "rx_missed",
1907 "align_errors",
1908 "tx_single_collisions",
1909 "tx_multi_collisions",
1910 "unicast",
1911 "broadcast",
1912 "multicast",
1913 "tx_aborted",
1914 "tx_underrun",
1915};
1916
b9f2c044 1917static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1918{
b9f2c044
JG		 1919 switch (sset) {
1920 case ETH_SS_STATS:
1921 return ARRAY_SIZE(rtl8169_gstrings);
1922 default:
1923 return -EOPNOTSUPP;
1924 }
d4a3a0fc
SH		 1925}
1926
ffc46952
FR		 1927DECLARE_RTL_COND(rtl_counters_cond)
1928{
1929 void __iomem *ioaddr = tp->mmio_addr;
1930
1931 return RTL_R32(CounterAddrLow) & CounterDump;
1932}
1933
355423d0 1934static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1935{
1936 struct rtl8169_private *tp = netdev_priv(dev);
1937 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1938 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1939 struct rtl8169_counters *counters;
1940 dma_addr_t paddr;
1941 u32 cmd;
1942
355423d0
IV		 1943 /*
1944 * Some chips are unable to dump tally counters when the receiver
1945 * is disabled.
1946 */
1947 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1948 return;
d4a3a0fc 1949
48addcc9 1950 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1951 if (!counters)
1952 return;
1953
1954 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1955 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1956 RTL_W32(CounterAddrLow, cmd);
1957 RTL_W32(CounterAddrLow, cmd | CounterDump);
1958
ffc46952
FR		 1959 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1960 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1961
1962 RTL_W32(CounterAddrLow, 0);
1963 RTL_W32(CounterAddrHigh, 0);
1964
48addcc9 1965 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1966}
1967
355423d0
IV		 1968static void rtl8169_get_ethtool_stats(struct net_device *dev,
1969 struct ethtool_stats *stats, u64 *data)
1970{
1971 struct rtl8169_private *tp = netdev_priv(dev);
1972
1973 ASSERT_RTNL();
1974
1975 rtl8169_update_counters(dev);
1976
1977 data[0] = le64_to_cpu(tp->counters.tx_packets);
1978 data[1] = le64_to_cpu(tp->counters.rx_packets);
1979 data[2] = le64_to_cpu(tp->counters.tx_errors);
1980 data[3] = le32_to_cpu(tp->counters.rx_errors);
1981 data[4] = le16_to_cpu(tp->counters.rx_missed);
1982 data[5] = le16_to_cpu(tp->counters.align_errors);
1983 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1984 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1985 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1986 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1987 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1988 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1989 data[12] = le16_to_cpu(tp->counters.tx_underun);
1990}
1991
d4a3a0fc
SH		 1992static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1993{
1994 switch(stringset) {
1995 case ETH_SS_STATS:
1996 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1997 break;
1998 }
1999}
2000
7282d491 2001static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2002 .get_drvinfo = rtl8169_get_drvinfo,
2003 .get_regs_len = rtl8169_get_regs_len,
2004 .get_link = ethtool_op_get_link,
2005 .get_settings = rtl8169_get_settings,
2006 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2007 .get_msglevel = rtl8169_get_msglevel,
2008 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2009 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2010 .get_wol = rtl8169_get_wol,
2011 .set_wol = rtl8169_set_wol,
d4a3a0fc 2012 .get_strings = rtl8169_get_strings,
b9f2c044 2013 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2014 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2015 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2016};
2017
07d3f51f 2018static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2019 struct net_device *dev, u8 default_version)
1da177e4 2020{
5d320a20 2021 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2022 /*
2023 * The driver currently handles the 8168Bf and the 8168Be identically
2024 * but they can be identified more specifically through the test below
2025 * if needed:
2026 *
2027 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2028 *
2029 * Same thing for the 8101Eb and the 8101Ec:
2030 *
2031 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2032 */
3744100e 2033 static const struct rtl_mac_info {
1da177e4 2034 u32 mask;
e3cf0cc0 2035 u32 val;
1da177e4
LT		 2036 int mac_version;
2037 } mac_info[] = {
c558386b
HW		 2038 /* 8168G family. */
2039 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2040 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2041
c2218925 2042 /* 8168F family. */
b3d7b2f2 2043 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2044 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2045 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2046
01dc7fec 2047 /* 8168E family. */
70090424 2048 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2049 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2050 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2051 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2052
5b538df9 2053 /* 8168D family. */
daf9df6d 2054 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2055 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2056 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2057
e6de30d6 2058 /* 8168DP family. */
2059 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2060 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2061 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2062
ef808d50 2063 /* 8168C family. */
17c99297 2064 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2065 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2066 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2067 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2068 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2069 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2070 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2071 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2072 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2073
2074 /* 8168B family. */
2075 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2076 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2077 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2078 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2079
2080 /* 8101 family. */
5598bfe5
HW		 2081 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2082 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2083 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2084 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2085 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2086 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2087 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2088 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2089 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2090 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2091 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2092 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2093 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2094 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2095 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2096 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2097 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2098 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2099 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2100 /* FIXME: where did these entries come from ? -- FR */
2101 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2102 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2103
2104 /* 8110 family. */
2105 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2106 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2107 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2108 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2109 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2110 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2111
f21b75e9
JD		 2112 /* Catch-all */
2113 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2114 };
2115 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2116 u32 reg;
2117
e3cf0cc0
FR		 2118 reg = RTL_R32(TxConfig);
2119 while ((reg & p->mask) != p->val)
1da177e4
LT		 2120 p++;
2121 tp->mac_version = p->mac_version;
5d320a20
FR		 2122
2123 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2124 netif_notice(tp, probe, dev,
2125 "unknown MAC, using family default\n");
2126 tp->mac_version = default_version;
2127 }
1da177e4
LT		 2128}
2129
2130static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2131{
bcf0bf90 2132 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2133}
2134
867763c1
FR		 2135struct phy_reg {
2136 u16 reg;
2137 u16 val;
2138};
2139
4da19633 2140static void rtl_writephy_batch(struct rtl8169_private *tp,
2141 const struct phy_reg *regs, int len)
867763c1
FR		 2142{
2143 while (len-- > 0) {
4da19633 2144 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2145 regs++;
2146 }
2147}
2148
bca03d5f 2149#define PHY_READ 0x00000000
2150#define PHY_DATA_OR 0x10000000
2151#define PHY_DATA_AND 0x20000000
2152#define PHY_BJMPN 0x30000000
eee3786f 2153#define PHY_MDIO_CHG 0x40000000
bca03d5f 2154#define PHY_CLEAR_READCOUNT 0x70000000
2155#define PHY_WRITE 0x80000000
2156#define PHY_READCOUNT_EQ_SKIP 0x90000000
2157#define PHY_COMP_EQ_SKIPN 0xa0000000
2158#define PHY_COMP_NEQ_SKIPN 0xb0000000
2159#define PHY_WRITE_PREVIOUS 0xc0000000
2160#define PHY_SKIPN 0xd0000000
2161#define PHY_DELAY_MS 0xe0000000
bca03d5f 2162
960aee6c
HW		 2163struct fw_info {
2164 u32 magic;
2165 char version[RTL_VER_SIZE];
2166 __le32 fw_start;
2167 __le32 fw_len;
2168 u8 chksum;
2169} __packed;
2170
1c361efb
FR		 2171#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2172
2173static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2174{
b6ffd97f 2175 const struct firmware *fw = rtl_fw->fw;
960aee6c 2176 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2177 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2178 char *version = rtl_fw->version;
2179 bool rc = false;
2180
2181 if (fw->size < FW_OPCODE_SIZE)
2182 goto out;
960aee6c
HW		 2183
2184 if (!fw_info->magic) {
2185 size_t i, size, start;
2186 u8 checksum = 0;
2187
2188 if (fw->size < sizeof(*fw_info))
2189 goto out;
2190
2191 for (i = 0; i < fw->size; i++)
2192 checksum += fw->data[i];
2193 if (checksum != 0)
2194 goto out;
2195
2196 start = le32_to_cpu(fw_info->fw_start);
2197 if (start > fw->size)
2198 goto out;
2199
2200 size = le32_to_cpu(fw_info->fw_len);
2201 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2202 goto out;
2203
2204 memcpy(version, fw_info->version, RTL_VER_SIZE);
2205
2206 pa->code = (__le32 *)(fw->data + start);
2207 pa->size = size;
2208 } else {
1c361efb
FR		 2209 if (fw->size % FW_OPCODE_SIZE)
2210 goto out;
2211
2212 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2213
2214 pa->code = (__le32 *)fw->data;
2215 pa->size = fw->size / FW_OPCODE_SIZE;
2216 }
2217 version[RTL_VER_SIZE - 1] = 0;
2218
2219 rc = true;
2220out:
2221 return rc;
2222}
2223
fd112f2e
FR		 2224static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2225 struct rtl_fw_phy_action *pa)
1c361efb 2226{
fd112f2e 2227 bool rc = false;
1c361efb 2228 size_t index;
bca03d5f 2229
1c361efb
FR		 2230 for (index = 0; index < pa->size; index++) {
2231 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2232 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2233
42b82dc1 2234 switch(action & 0xf0000000) {
2235 case PHY_READ:
2236 case PHY_DATA_OR:
2237 case PHY_DATA_AND:
eee3786f 2238 case PHY_MDIO_CHG:
42b82dc1 2239 case PHY_CLEAR_READCOUNT:
2240 case PHY_WRITE:
2241 case PHY_WRITE_PREVIOUS:
2242 case PHY_DELAY_MS:
2243 break;
2244
2245 case PHY_BJMPN:
2246 if (regno > index) {
fd112f2e 2247 netif_err(tp, ifup, tp->dev,
cecb5fd7 2248 "Out of range of firmware\n");
fd112f2e 2249 goto out;
42b82dc1 2250 }
2251 break;
2252 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2253 if (index + 2 >= pa->size) {
fd112f2e 2254 netif_err(tp, ifup, tp->dev,
cecb5fd7 2255 "Out of range of firmware\n");
fd112f2e 2256 goto out;
42b82dc1 2257 }
2258 break;
2259 case PHY_COMP_EQ_SKIPN:
2260 case PHY_COMP_NEQ_SKIPN:
2261 case PHY_SKIPN:
1c361efb 2262 if (index + 1 + regno >= pa->size) {
fd112f2e 2263 netif_err(tp, ifup, tp->dev,
cecb5fd7 2264 "Out of range of firmware\n");
fd112f2e 2265 goto out;
42b82dc1 2266 }
bca03d5f 2267 break;
2268
42b82dc1 2269 default:
fd112f2e 2270 netif_err(tp, ifup, tp->dev,
42b82dc1 2271 "Invalid action 0x%08x\n", action);
fd112f2e 2272 goto out;
bca03d5f 2273 }
2274 }
fd112f2e
FR		 2275 rc = true;
2276out:
2277 return rc;
2278}
bca03d5f 2279
fd112f2e
FR		 2280static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2281{
2282 struct net_device *dev = tp->dev;
2283 int rc = -EINVAL;
2284
2285 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2286 netif_err(tp, ifup, dev, "invalid firwmare\n");
2287 goto out;
2288 }
2289
2290 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2291 rc = 0;
2292out:
2293 return rc;
2294}
2295
2296static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2297{
2298 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2299 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2300 u32 predata, count;
2301 size_t index;
2302
2303 predata = count = 0;
eee3786f 2304 org.write = ops->write;
2305 org.read = ops->read;
42b82dc1 2306
1c361efb
FR		 2307 for (index = 0; index < pa->size; ) {
2308 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2309 u32 data = action & 0x0000ffff;
42b82dc1 2310 u32 regno = (action & 0x0fff0000) >> 16;
2311
2312 if (!action)
2313 break;
bca03d5f 2314
2315 switch(action & 0xf0000000) {
42b82dc1 2316 case PHY_READ:
2317 predata = rtl_readphy(tp, regno);
2318 count++;
2319 index++;
2320 break;
2321 case PHY_DATA_OR:
2322 predata |= data;
2323 index++;
2324 break;
2325 case PHY_DATA_AND:
2326 predata &= data;
2327 index++;
2328 break;
2329 case PHY_BJMPN:
2330 index -= regno;
2331 break;
eee3786f 2332 case PHY_MDIO_CHG:
2333 if (data == 0) {
2334 ops->write = org.write;
2335 ops->read = org.read;
2336 } else if (data == 1) {
2337 ops->write = mac_mcu_write;
2338 ops->read = mac_mcu_read;
2339 }
2340
42b82dc1 2341 index++;
2342 break;
2343 case PHY_CLEAR_READCOUNT:
2344 count = 0;
2345 index++;
2346 break;
bca03d5f 2347 case PHY_WRITE:
42b82dc1 2348 rtl_writephy(tp, regno, data);
2349 index++;
2350 break;
2351 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2352 index += (count == data) ? 2 : 1;
bca03d5f 2353 break;
42b82dc1 2354 case PHY_COMP_EQ_SKIPN:
2355 if (predata == data)
2356 index += regno;
2357 index++;
2358 break;
2359 case PHY_COMP_NEQ_SKIPN:
2360 if (predata != data)
2361 index += regno;
2362 index++;
2363 break;
2364 case PHY_WRITE_PREVIOUS:
2365 rtl_writephy(tp, regno, predata);
2366 index++;
2367 break;
2368 case PHY_SKIPN:
2369 index += regno + 1;
2370 break;
2371 case PHY_DELAY_MS:
2372 mdelay(data);
2373 index++;
2374 break;
2375
bca03d5f 2376 default:
2377 BUG();
2378 }
2379 }
eee3786f 2380
2381 ops->write = org.write;
2382 ops->read = org.read;
bca03d5f 2383}
2384
f1e02ed1 2385static void rtl_release_firmware(struct rtl8169_private *tp)
2386{
b6ffd97f
FR		 2387 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2388 release_firmware(tp->rtl_fw->fw);
2389 kfree(tp->rtl_fw);
2390 }
2391 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2392}
2393
953a12cc 2394static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2395{
b6ffd97f 2396 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2397
2398 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2399 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2400 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2401}
2402
2403static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2404{
2405 if (rtl_readphy(tp, reg) != val)
2406 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2407 else
2408 rtl_apply_firmware(tp);
f1e02ed1 2409}
2410
4da19633 2411static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2412{
350f7596 2413 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2414 { 0x1f, 0x0001 },
2415 { 0x06, 0x006e },
2416 { 0x08, 0x0708 },
2417 { 0x15, 0x4000 },
2418 { 0x18, 0x65c7 },
1da177e4 2419
0b9b571d 2420 { 0x1f, 0x0001 },
2421 { 0x03, 0x00a1 },
2422 { 0x02, 0x0008 },
2423 { 0x01, 0x0120 },
2424 { 0x00, 0x1000 },
2425 { 0x04, 0x0800 },
2426 { 0x04, 0x0000 },
1da177e4 2427
0b9b571d 2428 { 0x03, 0xff41 },
2429 { 0x02, 0xdf60 },
2430 { 0x01, 0x0140 },
2431 { 0x00, 0x0077 },
2432 { 0x04, 0x7800 },
2433 { 0x04, 0x7000 },
2434
2435 { 0x03, 0x802f },
2436 { 0x02, 0x4f02 },
2437 { 0x01, 0x0409 },
2438 { 0x00, 0xf0f9 },
2439 { 0x04, 0x9800 },
2440 { 0x04, 0x9000 },
2441
2442 { 0x03, 0xdf01 },
2443 { 0x02, 0xdf20 },
2444 { 0x01, 0xff95 },
2445 { 0x00, 0xba00 },
2446 { 0x04, 0xa800 },
2447 { 0x04, 0xa000 },
2448
2449 { 0x03, 0xff41 },
2450 { 0x02, 0xdf20 },
2451 { 0x01, 0x0140 },
2452 { 0x00, 0x00bb },
2453 { 0x04, 0xb800 },
2454 { 0x04, 0xb000 },
2455
2456 { 0x03, 0xdf41 },
2457 { 0x02, 0xdc60 },
2458 { 0x01, 0x6340 },
2459 { 0x00, 0x007d },
2460 { 0x04, 0xd800 },
2461 { 0x04, 0xd000 },
2462
2463 { 0x03, 0xdf01 },
2464 { 0x02, 0xdf20 },
2465 { 0x01, 0x100a },
2466 { 0x00, 0xa0ff },
2467 { 0x04, 0xf800 },
2468 { 0x04, 0xf000 },
2469
2470 { 0x1f, 0x0000 },
2471 { 0x0b, 0x0000 },
2472 { 0x00, 0x9200 }
2473 };
1da177e4 2474
4da19633 2475 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2476}
2477
4da19633 2478static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2479{
350f7596 2480 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2481 { 0x1f, 0x0002 },
2482 { 0x01, 0x90d0 },
2483 { 0x1f, 0x0000 }
2484 };
2485
4da19633 2486 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2487}
2488
4da19633 2489static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2490{
2491 struct pci_dev *pdev = tp->pci_dev;
2e955856 2492
ccbae55e
SS		 2493 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2494 (pdev->subsystem_device != 0xe000))
2e955856 2495 return;
2496
4da19633 2497 rtl_writephy(tp, 0x1f, 0x0001);
2498 rtl_writephy(tp, 0x10, 0xf01b);
2499 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2500}
2501
4da19633 2502static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2503{
350f7596 2504 static const struct phy_reg phy_reg_init[] = {
2e955856 2505 { 0x1f, 0x0001 },
2506 { 0x04, 0x0000 },
2507 { 0x03, 0x00a1 },
2508 { 0x02, 0x0008 },
2509 { 0x01, 0x0120 },
2510 { 0x00, 0x1000 },
2511 { 0x04, 0x0800 },
2512 { 0x04, 0x9000 },
2513 { 0x03, 0x802f },
2514 { 0x02, 0x4f02 },
2515 { 0x01, 0x0409 },
2516 { 0x00, 0xf099 },
2517 { 0x04, 0x9800 },
2518 { 0x04, 0xa000 },
2519 { 0x03, 0xdf01 },
2520 { 0x02, 0xdf20 },
2521 { 0x01, 0xff95 },
2522 { 0x00, 0xba00 },
2523 { 0x04, 0xa800 },
2524 { 0x04, 0xf000 },
2525 { 0x03, 0xdf01 },
2526 { 0x02, 0xdf20 },
2527 { 0x01, 0x101a },
2528 { 0x00, 0xa0ff },
2529 { 0x04, 0xf800 },
2530 { 0x04, 0x0000 },
2531 { 0x1f, 0x0000 },
2532
2533 { 0x1f, 0x0001 },
2534 { 0x10, 0xf41b },
2535 { 0x14, 0xfb54 },
2536 { 0x18, 0xf5c7 },
2537 { 0x1f, 0x0000 },
2538
2539 { 0x1f, 0x0001 },
2540 { 0x17, 0x0cc0 },
2541 { 0x1f, 0x0000 }
2542 };
2543
4da19633 2544 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2545
4da19633 2546 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2547}
2548
4da19633 2549static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2550{
350f7596 2551 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2552 { 0x1f, 0x0001 },
2553 { 0x04, 0x0000 },
2554 { 0x03, 0x00a1 },
2555 { 0x02, 0x0008 },
2556 { 0x01, 0x0120 },
2557 { 0x00, 0x1000 },
2558 { 0x04, 0x0800 },
2559 { 0x04, 0x9000 },
2560 { 0x03, 0x802f },
2561 { 0x02, 0x4f02 },
2562 { 0x01, 0x0409 },
2563 { 0x00, 0xf099 },
2564 { 0x04, 0x9800 },
2565 { 0x04, 0xa000 },
2566 { 0x03, 0xdf01 },
2567 { 0x02, 0xdf20 },
2568 { 0x01, 0xff95 },
2569 { 0x00, 0xba00 },
2570 { 0x04, 0xa800 },
2571 { 0x04, 0xf000 },
2572 { 0x03, 0xdf01 },
2573 { 0x02, 0xdf20 },
2574 { 0x01, 0x101a },
2575 { 0x00, 0xa0ff },
2576 { 0x04, 0xf800 },
2577 { 0x04, 0x0000 },
2578 { 0x1f, 0x0000 },
2579
2580 { 0x1f, 0x0001 },
2581 { 0x0b, 0x8480 },
2582 { 0x1f, 0x0000 },
2583
2584 { 0x1f, 0x0001 },
2585 { 0x18, 0x67c7 },
2586 { 0x04, 0x2000 },
2587 { 0x03, 0x002f },
2588 { 0x02, 0x4360 },
2589 { 0x01, 0x0109 },
2590 { 0x00, 0x3022 },
2591 { 0x04, 0x2800 },
2592 { 0x1f, 0x0000 },
2593
2594 { 0x1f, 0x0001 },
2595 { 0x17, 0x0cc0 },
2596 { 0x1f, 0x0000 }
2597 };
2598
4da19633 2599 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2600}
2601
4da19633 2602static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2603{
350f7596 2604 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2605 { 0x10, 0xf41b },
2606 { 0x1f, 0x0000 }
2607 };
2608
4da19633 2609 rtl_writephy(tp, 0x1f, 0x0001);
2610 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2611
4da19633 2612 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2613}
2614
4da19633 2615static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2616{
350f7596 2617 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2618 { 0x1f, 0x0001 },
2619 { 0x10, 0xf41b },
2620 { 0x1f, 0x0000 }
2621 };
2622
4da19633 2623 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2624}
2625
4da19633 2626static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2627{
350f7596 2628 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2629 { 0x1f, 0x0000 },
2630 { 0x1d, 0x0f00 },
2631 { 0x1f, 0x0002 },
2632 { 0x0c, 0x1ec8 },
2633 { 0x1f, 0x0000 }
2634 };
2635
4da19633 2636 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2637}
2638
4da19633 2639static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2640{
350f7596 2641 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2642 { 0x1f, 0x0001 },
2643 { 0x1d, 0x3d98 },
2644 { 0x1f, 0x0000 }
2645 };
2646
4da19633 2647 rtl_writephy(tp, 0x1f, 0x0000);
2648 rtl_patchphy(tp, 0x14, 1 << 5);
2649 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2650
4da19633 2651 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2652}
2653
4da19633 2654static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2655{
350f7596 2656 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2657 { 0x1f, 0x0001 },
2658 { 0x12, 0x2300 },
867763c1
FR		 2659 { 0x1f, 0x0002 },
2660 { 0x00, 0x88d4 },
2661 { 0x01, 0x82b1 },
2662 { 0x03, 0x7002 },
2663 { 0x08, 0x9e30 },
2664 { 0x09, 0x01f0 },
2665 { 0x0a, 0x5500 },
2666 { 0x0c, 0x00c8 },
2667 { 0x1f, 0x0003 },
2668 { 0x12, 0xc096 },
2669 { 0x16, 0x000a },
f50d4275
FR		 2670 { 0x1f, 0x0000 },
2671 { 0x1f, 0x0000 },
2672 { 0x09, 0x2000 },
2673 { 0x09, 0x0000 }
867763c1
FR		 2674 };
2675
4da19633 2676 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2677
4da19633 2678 rtl_patchphy(tp, 0x14, 1 << 5);
2679 rtl_patchphy(tp, 0x0d, 1 << 5);
2680 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2681}
2682
4da19633 2683static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2684{
350f7596 2685 static const struct phy_reg phy_reg_init[] = {
f50d4275 2686 { 0x1f, 0x0001 },
7da97ec9 2687 { 0x12, 0x2300 },
f50d4275
FR		 2688 { 0x03, 0x802f },
2689 { 0x02, 0x4f02 },
2690 { 0x01, 0x0409 },
2691 { 0x00, 0xf099 },
2692 { 0x04, 0x9800 },
2693 { 0x04, 0x9000 },
2694 { 0x1d, 0x3d98 },
7da97ec9
FR		 2695 { 0x1f, 0x0002 },
2696 { 0x0c, 0x7eb8 },
f50d4275
FR		 2697 { 0x06, 0x0761 },
2698 { 0x1f, 0x0003 },
2699 { 0x16, 0x0f0a },
7da97ec9
FR		 2700 { 0x1f, 0x0000 }
2701 };
2702
4da19633 2703 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2704
4da19633 2705 rtl_patchphy(tp, 0x16, 1 << 0);
2706 rtl_patchphy(tp, 0x14, 1 << 5);
2707 rtl_patchphy(tp, 0x0d, 1 << 5);
2708 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2709}
2710
4da19633 2711static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2712{
350f7596 2713 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2714 { 0x1f, 0x0001 },
2715 { 0x12, 0x2300 },
2716 { 0x1d, 0x3d98 },
2717 { 0x1f, 0x0002 },
2718 { 0x0c, 0x7eb8 },
2719 { 0x06, 0x5461 },
2720 { 0x1f, 0x0003 },
2721 { 0x16, 0x0f0a },
2722 { 0x1f, 0x0000 }
2723 };
2724
4da19633 2725 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2726
4da19633 2727 rtl_patchphy(tp, 0x16, 1 << 0);
2728 rtl_patchphy(tp, 0x14, 1 << 5);
2729 rtl_patchphy(tp, 0x0d, 1 << 5);
2730 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2731}
2732
4da19633 2733static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2734{
4da19633 2735 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2736}
2737
bca03d5f 2738static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2739{
350f7596 2740 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2741 /* Channel Estimation */
5b538df9 2742 { 0x1f, 0x0001 },
daf9df6d 2743 { 0x06, 0x4064 },
2744 { 0x07, 0x2863 },
2745 { 0x08, 0x059c },
2746 { 0x09, 0x26b4 },
2747 { 0x0a, 0x6a19 },
2748 { 0x0b, 0xdcc8 },
2749 { 0x10, 0xf06d },
2750 { 0x14, 0x7f68 },
2751 { 0x18, 0x7fd9 },
2752 { 0x1c, 0xf0ff },
2753 { 0x1d, 0x3d9c },
5b538df9 2754 { 0x1f, 0x0003 },
daf9df6d 2755 { 0x12, 0xf49f },
2756 { 0x13, 0x070b },
2757 { 0x1a, 0x05ad },
bca03d5f 2758 { 0x14, 0x94c0 },
2759
2760 /*
2761 * Tx Error Issue
cecb5fd7 2762 * Enhance line driver power
bca03d5f 2763 */
5b538df9 2764 { 0x1f, 0x0002 },
daf9df6d 2765 { 0x06, 0x5561 },
2766 { 0x1f, 0x0005 },
2767 { 0x05, 0x8332 },
bca03d5f 2768 { 0x06, 0x5561 },
2769
2770 /*
2771 * Can not link to 1Gbps with bad cable
2772 * Decrease SNR threshold form 21.07dB to 19.04dB
2773 */
2774 { 0x1f, 0x0001 },
2775 { 0x17, 0x0cc0 },
daf9df6d 2776
5b538df9 2777 { 0x1f, 0x0000 },
bca03d5f 2778 { 0x0d, 0xf880 }
daf9df6d 2779 };
2780
4da19633 2781 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2782
bca03d5f 2783 /*
2784 * Rx Error Issue
2785 * Fine Tune Switching regulator parameter
2786 */
4da19633 2787 rtl_writephy(tp, 0x1f, 0x0002);
2788 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2789 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2790
fdf6fc06 2791 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2792 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2793 { 0x1f, 0x0002 },
2794 { 0x05, 0x669a },
2795 { 0x1f, 0x0005 },
2796 { 0x05, 0x8330 },
2797 { 0x06, 0x669a },
2798 { 0x1f, 0x0002 }
2799 };
2800 int val;
2801
4da19633 2802 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2803
4da19633 2804 val = rtl_readphy(tp, 0x0d);
daf9df6d 2805
2806 if ((val & 0x00ff) != 0x006c) {
350f7596 2807 static const u32 set[] = {
daf9df6d 2808 0x0065, 0x0066, 0x0067, 0x0068,
2809 0x0069, 0x006a, 0x006b, 0x006c
2810 };
2811 int i;
2812
4da19633 2813 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2814
2815 val &= 0xff00;
2816 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2817 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2818 }
2819 } else {
350f7596 2820 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2821 { 0x1f, 0x0002 },
2822 { 0x05, 0x6662 },
2823 { 0x1f, 0x0005 },
2824 { 0x05, 0x8330 },
2825 { 0x06, 0x6662 }
2826 };
2827
4da19633 2828 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2829 }
2830
bca03d5f 2831 /* RSET couple improve */
4da19633 2832 rtl_writephy(tp, 0x1f, 0x0002);
2833 rtl_patchphy(tp, 0x0d, 0x0300);
2834 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2835
bca03d5f 2836 /* Fine tune PLL performance */
4da19633 2837 rtl_writephy(tp, 0x1f, 0x0002);
2838 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2839 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2840
4da19633 2841 rtl_writephy(tp, 0x1f, 0x0005);
2842 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2843
2844 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2845
4da19633 2846 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2847}
2848
bca03d5f 2849static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2850{
350f7596 2851 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2852 /* Channel Estimation */
daf9df6d 2853 { 0x1f, 0x0001 },
2854 { 0x06, 0x4064 },
2855 { 0x07, 0x2863 },
2856 { 0x08, 0x059c },
2857 { 0x09, 0x26b4 },
2858 { 0x0a, 0x6a19 },
2859 { 0x0b, 0xdcc8 },
2860 { 0x10, 0xf06d },
2861 { 0x14, 0x7f68 },
2862 { 0x18, 0x7fd9 },
2863 { 0x1c, 0xf0ff },
2864 { 0x1d, 0x3d9c },
2865 { 0x1f, 0x0003 },
2866 { 0x12, 0xf49f },
2867 { 0x13, 0x070b },
2868 { 0x1a, 0x05ad },
2869 { 0x14, 0x94c0 },
2870
bca03d5f 2871 /*
2872 * Tx Error Issue
cecb5fd7 2873 * Enhance line driver power
bca03d5f 2874 */
daf9df6d 2875 { 0x1f, 0x0002 },
2876 { 0x06, 0x5561 },
2877 { 0x1f, 0x0005 },
2878 { 0x05, 0x8332 },
bca03d5f 2879 { 0x06, 0x5561 },
2880
2881 /*
2882 * Can not link to 1Gbps with bad cable
2883 * Decrease SNR threshold form 21.07dB to 19.04dB
2884 */
2885 { 0x1f, 0x0001 },
2886 { 0x17, 0x0cc0 },
daf9df6d 2887
2888 { 0x1f, 0x0000 },
bca03d5f 2889 { 0x0d, 0xf880 }
5b538df9
FR		 2890 };
2891
4da19633 2892 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2893
fdf6fc06 2894 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2895 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2896 { 0x1f, 0x0002 },
2897 { 0x05, 0x669a },
5b538df9 2898 { 0x1f, 0x0005 },
daf9df6d 2899 { 0x05, 0x8330 },
2900 { 0x06, 0x669a },
2901
2902 { 0x1f, 0x0002 }
2903 };
2904 int val;
2905
4da19633 2906 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2907
4da19633 2908 val = rtl_readphy(tp, 0x0d);
daf9df6d 2909 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2910 static const u32 set[] = {
daf9df6d 2911 0x0065, 0x0066, 0x0067, 0x0068,
2912 0x0069, 0x006a, 0x006b, 0x006c
2913 };
2914 int i;
2915
4da19633 2916 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2917
2918 val &= 0xff00;
2919 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2920 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2921 }
2922 } else {
350f7596 2923 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2924 { 0x1f, 0x0002 },
2925 { 0x05, 0x2642 },
5b538df9 2926 { 0x1f, 0x0005 },
daf9df6d 2927 { 0x05, 0x8330 },
2928 { 0x06, 0x2642 }
5b538df9
FR		 2929 };
2930
4da19633 2931 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2932 }
2933
bca03d5f 2934 /* Fine tune PLL performance */
4da19633 2935 rtl_writephy(tp, 0x1f, 0x0002);
2936 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2937 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2938
bca03d5f 2939 /* Switching regulator Slew rate */
4da19633 2940 rtl_writephy(tp, 0x1f, 0x0002);
2941 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2942
4da19633 2943 rtl_writephy(tp, 0x1f, 0x0005);
2944 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2945
2946 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2947
4da19633 2948 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2949}
2950
4da19633 2951static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2952{
350f7596 2953 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2954 { 0x1f, 0x0002 },
2955 { 0x10, 0x0008 },
2956 { 0x0d, 0x006c },
2957
2958 { 0x1f, 0x0000 },
2959 { 0x0d, 0xf880 },
2960
2961 { 0x1f, 0x0001 },
2962 { 0x17, 0x0cc0 },
2963
2964 { 0x1f, 0x0001 },
2965 { 0x0b, 0xa4d8 },
2966 { 0x09, 0x281c },
2967 { 0x07, 0x2883 },
2968 { 0x0a, 0x6b35 },
2969 { 0x1d, 0x3da4 },
2970 { 0x1c, 0xeffd },
2971 { 0x14, 0x7f52 },
2972 { 0x18, 0x7fc6 },
2973 { 0x08, 0x0601 },
2974 { 0x06, 0x4063 },
2975 { 0x10, 0xf074 },
2976 { 0x1f, 0x0003 },
2977 { 0x13, 0x0789 },
2978 { 0x12, 0xf4bd },
2979 { 0x1a, 0x04fd },
2980 { 0x14, 0x84b0 },
2981 { 0x1f, 0x0000 },
2982 { 0x00, 0x9200 },
2983
2984 { 0x1f, 0x0005 },
2985 { 0x01, 0x0340 },
2986 { 0x1f, 0x0001 },
2987 { 0x04, 0x4000 },
2988 { 0x03, 0x1d21 },
2989 { 0x02, 0x0c32 },
2990 { 0x01, 0x0200 },
2991 { 0x00, 0x5554 },
2992 { 0x04, 0x4800 },
2993 { 0x04, 0x4000 },
2994 { 0x04, 0xf000 },
2995 { 0x03, 0xdf01 },
2996 { 0x02, 0xdf20 },
2997 { 0x01, 0x101a },
2998 { 0x00, 0xa0ff },
2999 { 0x04, 0xf800 },
3000 { 0x04, 0xf000 },
3001 { 0x1f, 0x0000 },
3002
3003 { 0x1f, 0x0007 },
3004 { 0x1e, 0x0023 },
3005 { 0x16, 0x0000 },
3006 { 0x1f, 0x0000 }
3007 };
3008
4da19633 3009 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3010}
3011
e6de30d6 3012static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3013{
3014 static const struct phy_reg phy_reg_init[] = {
3015 { 0x1f, 0x0001 },
3016 { 0x17, 0x0cc0 },
3017
3018 { 0x1f, 0x0007 },
3019 { 0x1e, 0x002d },
3020 { 0x18, 0x0040 },
3021 { 0x1f, 0x0000 }
3022 };
3023
3024 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3025 rtl_patchphy(tp, 0x0d, 1 << 5);
3026}
3027
70090424 3028static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3029{
3030 static const struct phy_reg phy_reg_init[] = {
3031 /* Enable Delay cap */
3032 { 0x1f, 0x0005 },
3033 { 0x05, 0x8b80 },
3034 { 0x06, 0xc896 },
3035 { 0x1f, 0x0000 },
3036
3037 /* Channel estimation fine tune */
3038 { 0x1f, 0x0001 },
3039 { 0x0b, 0x6c20 },
3040 { 0x07, 0x2872 },
3041 { 0x1c, 0xefff },
3042 { 0x1f, 0x0003 },
3043 { 0x14, 0x6420 },
3044 { 0x1f, 0x0000 },
3045
3046 /* Update PFM & 10M TX idle timer */
3047 { 0x1f, 0x0007 },
3048 { 0x1e, 0x002f },
3049 { 0x15, 0x1919 },
3050 { 0x1f, 0x0000 },
3051
3052 { 0x1f, 0x0007 },
3053 { 0x1e, 0x00ac },
3054 { 0x18, 0x0006 },
3055 { 0x1f, 0x0000 }
3056 };
3057
15ecd039
FR		 3058 rtl_apply_firmware(tp);
3059
01dc7fec 3060 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3061
3062 /* DCO enable for 10M IDLE Power */
3063 rtl_writephy(tp, 0x1f, 0x0007);
3064 rtl_writephy(tp, 0x1e, 0x0023);
3065 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3066 rtl_writephy(tp, 0x1f, 0x0000);
3067
3068 /* For impedance matching */
3069 rtl_writephy(tp, 0x1f, 0x0002);
3070 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3071 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3072
3073 /* PHY auto speed down */
3074 rtl_writephy(tp, 0x1f, 0x0007);
3075 rtl_writephy(tp, 0x1e, 0x002d);
3076 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3077 rtl_writephy(tp, 0x1f, 0x0000);
3078 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3079
3080 rtl_writephy(tp, 0x1f, 0x0005);
3081 rtl_writephy(tp, 0x05, 0x8b86);
3082 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3083 rtl_writephy(tp, 0x1f, 0x0000);
3084
3085 rtl_writephy(tp, 0x1f, 0x0005);
3086 rtl_writephy(tp, 0x05, 0x8b85);
3087 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3088 rtl_writephy(tp, 0x1f, 0x0007);
3089 rtl_writephy(tp, 0x1e, 0x0020);
3090 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3091 rtl_writephy(tp, 0x1f, 0x0006);
3092 rtl_writephy(tp, 0x00, 0x5a00);
3093 rtl_writephy(tp, 0x1f, 0x0000);
3094 rtl_writephy(tp, 0x0d, 0x0007);
3095 rtl_writephy(tp, 0x0e, 0x003c);
3096 rtl_writephy(tp, 0x0d, 0x4007);
3097 rtl_writephy(tp, 0x0e, 0x0000);
3098 rtl_writephy(tp, 0x0d, 0x0000);
3099}
3100
9ecb9aab 3101static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3102{
3103 const u16 w[] = {
3104 addr[0] | (addr[1] << 8),
3105 addr[2] | (addr[3] << 8),
3106 addr[4] | (addr[5] << 8)
3107 };
3108 const struct exgmac_reg e[] = {
3109 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3110 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3111 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3112 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3113 };
3114
3115 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3116}
3117
70090424
HW		 3118static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3119{
3120 static const struct phy_reg phy_reg_init[] = {
3121 /* Enable Delay cap */
3122 { 0x1f, 0x0004 },
3123 { 0x1f, 0x0007 },
3124 { 0x1e, 0x00ac },
3125 { 0x18, 0x0006 },
3126 { 0x1f, 0x0002 },
3127 { 0x1f, 0x0000 },
3128 { 0x1f, 0x0000 },
3129
3130 /* Channel estimation fine tune */
3131 { 0x1f, 0x0003 },
3132 { 0x09, 0xa20f },
3133 { 0x1f, 0x0000 },
3134 { 0x1f, 0x0000 },
3135
3136 /* Green Setting */
3137 { 0x1f, 0x0005 },
3138 { 0x05, 0x8b5b },
3139 { 0x06, 0x9222 },
3140 { 0x05, 0x8b6d },
3141 { 0x06, 0x8000 },
3142 { 0x05, 0x8b76 },
3143 { 0x06, 0x8000 },
3144 { 0x1f, 0x0000 }
3145 };
3146
3147 rtl_apply_firmware(tp);
3148
3149 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3150
3151 /* For 4-corner performance improve */
3152 rtl_writephy(tp, 0x1f, 0x0005);
3153 rtl_writephy(tp, 0x05, 0x8b80);
3154 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3155 rtl_writephy(tp, 0x1f, 0x0000);
3156
3157 /* PHY auto speed down */
3158 rtl_writephy(tp, 0x1f, 0x0004);
3159 rtl_writephy(tp, 0x1f, 0x0007);
3160 rtl_writephy(tp, 0x1e, 0x002d);
3161 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3162 rtl_writephy(tp, 0x1f, 0x0002);
3163 rtl_writephy(tp, 0x1f, 0x0000);
3164 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3165
3166 /* improve 10M EEE waveform */
3167 rtl_writephy(tp, 0x1f, 0x0005);
3168 rtl_writephy(tp, 0x05, 0x8b86);
3169 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3170 rtl_writephy(tp, 0x1f, 0x0000);
3171
3172 /* Improve 2-pair detection performance */
3173 rtl_writephy(tp, 0x1f, 0x0005);
3174 rtl_writephy(tp, 0x05, 0x8b85);
3175 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3176 rtl_writephy(tp, 0x1f, 0x0000);
3177
3178 /* EEE setting */
fdf6fc06 3179 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3180 rtl_writephy(tp, 0x1f, 0x0005);
3181 rtl_writephy(tp, 0x05, 0x8b85);
3182 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3183 rtl_writephy(tp, 0x1f, 0x0004);
3184 rtl_writephy(tp, 0x1f, 0x0007);
3185 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3186 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3187 rtl_writephy(tp, 0x1f, 0x0002);
3188 rtl_writephy(tp, 0x1f, 0x0000);
3189 rtl_writephy(tp, 0x0d, 0x0007);
3190 rtl_writephy(tp, 0x0e, 0x003c);
3191 rtl_writephy(tp, 0x0d, 0x4007);
3192 rtl_writephy(tp, 0x0e, 0x0000);
3193 rtl_writephy(tp, 0x0d, 0x0000);
3194
3195 /* Green feature */
3196 rtl_writephy(tp, 0x1f, 0x0003);
3197 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3198 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3199 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3200
9ecb9aab 3201 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3202 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3203}
3204
5f886e08
HW		 3205static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3206{
3207 /* For 4-corner performance improve */
3208 rtl_writephy(tp, 0x1f, 0x0005);
3209 rtl_writephy(tp, 0x05, 0x8b80);
3210 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3211 rtl_writephy(tp, 0x1f, 0x0000);
3212
3213 /* PHY auto speed down */
3214 rtl_writephy(tp, 0x1f, 0x0007);
3215 rtl_writephy(tp, 0x1e, 0x002d);
3216 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3217 rtl_writephy(tp, 0x1f, 0x0000);
3218 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3219
3220 /* Improve 10M EEE waveform */
3221 rtl_writephy(tp, 0x1f, 0x0005);
3222 rtl_writephy(tp, 0x05, 0x8b86);
3223 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3224 rtl_writephy(tp, 0x1f, 0x0000);
3225}
3226
c2218925
HW		 3227static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3228{
3229 static const struct phy_reg phy_reg_init[] = {
3230 /* Channel estimation fine tune */
3231 { 0x1f, 0x0003 },
3232 { 0x09, 0xa20f },
3233 { 0x1f, 0x0000 },
3234
3235 /* Modify green table for giga & fnet */
3236 { 0x1f, 0x0005 },
3237 { 0x05, 0x8b55 },
3238 { 0x06, 0x0000 },
3239 { 0x05, 0x8b5e },
3240 { 0x06, 0x0000 },
3241 { 0x05, 0x8b67 },
3242 { 0x06, 0x0000 },
3243 { 0x05, 0x8b70 },
3244 { 0x06, 0x0000 },
3245 { 0x1f, 0x0000 },
3246 { 0x1f, 0x0007 },
3247 { 0x1e, 0x0078 },
3248 { 0x17, 0x0000 },
3249 { 0x19, 0x00fb },
3250 { 0x1f, 0x0000 },
3251
3252 /* Modify green table for 10M */
3253 { 0x1f, 0x0005 },
3254 { 0x05, 0x8b79 },
3255 { 0x06, 0xaa00 },
3256 { 0x1f, 0x0000 },
3257
3258 /* Disable hiimpedance detection (RTCT) */
3259 { 0x1f, 0x0003 },
3260 { 0x01, 0x328a },
3261 { 0x1f, 0x0000 }
3262 };
3263
3264 rtl_apply_firmware(tp);
3265
3266 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3267
5f886e08 3268 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3269
3270 /* Improve 2-pair detection performance */
3271 rtl_writephy(tp, 0x1f, 0x0005);
3272 rtl_writephy(tp, 0x05, 0x8b85);
3273 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3274 rtl_writephy(tp, 0x1f, 0x0000);
3275}
3276
3277static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3278{
3279 rtl_apply_firmware(tp);
3280
5f886e08 3281 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3282}
3283
b3d7b2f2
HW		 3284static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3285{
b3d7b2f2
HW		 3286 static const struct phy_reg phy_reg_init[] = {
3287 /* Channel estimation fine tune */
3288 { 0x1f, 0x0003 },
3289 { 0x09, 0xa20f },
3290 { 0x1f, 0x0000 },
3291
3292 /* Modify green table for giga & fnet */
3293 { 0x1f, 0x0005 },
3294 { 0x05, 0x8b55 },
3295 { 0x06, 0x0000 },
3296 { 0x05, 0x8b5e },
3297 { 0x06, 0x0000 },
3298 { 0x05, 0x8b67 },
3299 { 0x06, 0x0000 },
3300 { 0x05, 0x8b70 },
3301 { 0x06, 0x0000 },
3302 { 0x1f, 0x0000 },
3303 { 0x1f, 0x0007 },
3304 { 0x1e, 0x0078 },
3305 { 0x17, 0x0000 },
3306 { 0x19, 0x00aa },
3307 { 0x1f, 0x0000 },
3308
3309 /* Modify green table for 10M */
3310 { 0x1f, 0x0005 },
3311 { 0x05, 0x8b79 },
3312 { 0x06, 0xaa00 },
3313 { 0x1f, 0x0000 },
3314
3315 /* Disable hiimpedance detection (RTCT) */
3316 { 0x1f, 0x0003 },
3317 { 0x01, 0x328a },
3318 { 0x1f, 0x0000 }
3319 };
3320
3321
3322 rtl_apply_firmware(tp);
3323
3324 rtl8168f_hw_phy_config(tp);
3325
3326 /* Improve 2-pair detection performance */
3327 rtl_writephy(tp, 0x1f, 0x0005);
3328 rtl_writephy(tp, 0x05, 0x8b85);
3329 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3330 rtl_writephy(tp, 0x1f, 0x0000);
3331
3332 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3333
3334 /* Modify green table for giga */
3335 rtl_writephy(tp, 0x1f, 0x0005);
3336 rtl_writephy(tp, 0x05, 0x8b54);
3337 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3338 rtl_writephy(tp, 0x05, 0x8b5d);
3339 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3340 rtl_writephy(tp, 0x05, 0x8a7c);
3341 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3342 rtl_writephy(tp, 0x05, 0x8a7f);
3343 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3344 rtl_writephy(tp, 0x05, 0x8a82);
3345 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3346 rtl_writephy(tp, 0x05, 0x8a85);
3347 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3348 rtl_writephy(tp, 0x05, 0x8a88);
3349 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3350 rtl_writephy(tp, 0x1f, 0x0000);
3351
3352 /* uc same-seed solution */
3353 rtl_writephy(tp, 0x1f, 0x0005);
3354 rtl_writephy(tp, 0x05, 0x8b85);
3355 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3356 rtl_writephy(tp, 0x1f, 0x0000);
3357
3358 /* eee setting */
fdf6fc06 3359 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3360 rtl_writephy(tp, 0x1f, 0x0005);
3361 rtl_writephy(tp, 0x05, 0x8b85);
3362 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3363 rtl_writephy(tp, 0x1f, 0x0004);
3364 rtl_writephy(tp, 0x1f, 0x0007);
3365 rtl_writephy(tp, 0x1e, 0x0020);
3366 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3367 rtl_writephy(tp, 0x1f, 0x0000);
3368 rtl_writephy(tp, 0x0d, 0x0007);
3369 rtl_writephy(tp, 0x0e, 0x003c);
3370 rtl_writephy(tp, 0x0d, 0x4007);
3371 rtl_writephy(tp, 0x0e, 0x0000);
3372 rtl_writephy(tp, 0x0d, 0x0000);
3373
3374 /* Green feature */
3375 rtl_writephy(tp, 0x1f, 0x0003);
3376 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3377 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3378 rtl_writephy(tp, 0x1f, 0x0000);
3379}
3380
c558386b
HW		 3381static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3382{
c558386b
HW		 3383 rtl_apply_firmware(tp);
3384
41f44d13 3385 rtl_writephy(tp, 0x1f, 0x0a46);
3386 if (rtl_readphy(tp, 0x10) & 0x0100) {
3387 rtl_writephy(tp, 0x1f, 0x0bcc);
3388 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3389 } else {
3390 rtl_writephy(tp, 0x1f, 0x0bcc);
3391 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3392 }
c558386b 3393
41f44d13 3394 rtl_writephy(tp, 0x1f, 0x0a46);
3395 if (rtl_readphy(tp, 0x13) & 0x0100) {
3396 rtl_writephy(tp, 0x1f, 0x0c41);
3397 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3398 } else {
fe7524c0 3399 rtl_writephy(tp, 0x1f, 0x0c41);
3400 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3401 }
c558386b 3402
41f44d13 3403 /* Enable PHY auto speed down */
3404 rtl_writephy(tp, 0x1f, 0x0a44);
3405 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3406
fe7524c0 3407 rtl_writephy(tp, 0x1f, 0x0bcc);
3408 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3409 rtl_writephy(tp, 0x1f, 0x0a44);
3410 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3411 rtl_writephy(tp, 0x1f, 0x0a43);
3412 rtl_writephy(tp, 0x13, 0x8084);
3413 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3414 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3415
41f44d13 3416 /* EEE auto-fallback function */
3417 rtl_writephy(tp, 0x1f, 0x0a4b);
3418 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3419
41f44d13 3420 /* Enable UC LPF tune function */
3421 rtl_writephy(tp, 0x1f, 0x0a43);
3422 rtl_writephy(tp, 0x13, 0x8012);
3423 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3424
3425 rtl_writephy(tp, 0x1f, 0x0c42);
3426 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3427
fe7524c0 3428 /* Improve SWR Efficiency */
3429 rtl_writephy(tp, 0x1f, 0x0bcd);
3430 rtl_writephy(tp, 0x14, 0x5065);
3431 rtl_writephy(tp, 0x14, 0xd065);
3432 rtl_writephy(tp, 0x1f, 0x0bc8);
3433 rtl_writephy(tp, 0x11, 0x5655);
3434 rtl_writephy(tp, 0x1f, 0x0bcd);
3435 rtl_writephy(tp, 0x14, 0x1065);
3436 rtl_writephy(tp, 0x14, 0x9065);
3437 rtl_writephy(tp, 0x14, 0x1065);
3438
41f44d13 3439 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3440}
3441
4da19633 3442static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3443{
350f7596 3444 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3445 { 0x1f, 0x0003 },
3446 { 0x08, 0x441d },
3447 { 0x01, 0x9100 },
3448 { 0x1f, 0x0000 }
3449 };
3450
4da19633 3451 rtl_writephy(tp, 0x1f, 0x0000);
3452 rtl_patchphy(tp, 0x11, 1 << 12);
3453 rtl_patchphy(tp, 0x19, 1 << 13);
3454 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3455
4da19633 3456 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3457}
3458
5a5e4443
HW		 3459static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3460{
3461 static const struct phy_reg phy_reg_init[] = {
3462 { 0x1f, 0x0005 },
3463 { 0x1a, 0x0000 },
3464 { 0x1f, 0x0000 },
3465
3466 { 0x1f, 0x0004 },
3467 { 0x1c, 0x0000 },
3468 { 0x1f, 0x0000 },
3469
3470 { 0x1f, 0x0001 },
3471 { 0x15, 0x7701 },
3472 { 0x1f, 0x0000 }
3473 };
3474
3475 /* Disable ALDPS before ram code */
eef63cc1
FR		 3476 rtl_writephy(tp, 0x1f, 0x0000);
3477 rtl_writephy(tp, 0x18, 0x0310);
3478 msleep(100);
5a5e4443 3479
953a12cc 3480 rtl_apply_firmware(tp);
5a5e4443
HW		 3481
3482 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3483}
3484
7e18dca1
HW		 3485static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3486{
7e18dca1 3487 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3488 rtl_writephy(tp, 0x1f, 0x0000);
3489 rtl_writephy(tp, 0x18, 0x0310);
3490 msleep(20);
7e18dca1
HW		 3491
3492 rtl_apply_firmware(tp);
3493
3494 /* EEE setting */
fdf6fc06 3495 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3496 rtl_writephy(tp, 0x1f, 0x0004);
3497 rtl_writephy(tp, 0x10, 0x401f);
3498 rtl_writephy(tp, 0x19, 0x7030);
3499 rtl_writephy(tp, 0x1f, 0x0000);
3500}
3501
5598bfe5
HW		 3502static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3503{
5598bfe5
HW		 3504 static const struct phy_reg phy_reg_init[] = {
3505 { 0x1f, 0x0004 },
3506 { 0x10, 0xc07f },
3507 { 0x19, 0x7030 },
3508 { 0x1f, 0x0000 }
3509 };
3510
3511 /* Disable ALDPS before ram code */
eef63cc1
FR		 3512 rtl_writephy(tp, 0x1f, 0x0000);
3513 rtl_writephy(tp, 0x18, 0x0310);
3514 msleep(100);
5598bfe5
HW		 3515
3516 rtl_apply_firmware(tp);
3517
fdf6fc06 3518 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3519 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3520
fdf6fc06 3521 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3522}
3523
5615d9f1
FR		 3524static void rtl_hw_phy_config(struct net_device *dev)
3525{
3526 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3527
3528 rtl8169_print_mac_version(tp);
3529
3530 switch (tp->mac_version) {
3531 case RTL_GIGA_MAC_VER_01:
3532 break;
3533 case RTL_GIGA_MAC_VER_02:
3534 case RTL_GIGA_MAC_VER_03:
4da19633 3535 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3536 break;
3537 case RTL_GIGA_MAC_VER_04:
4da19633 3538 rtl8169sb_hw_phy_config(tp);
5615d9f1 3539 break;
2e955856 3540 case RTL_GIGA_MAC_VER_05:
4da19633 3541 rtl8169scd_hw_phy_config(tp);
2e955856 3542 break;
8c7006aa 3543 case RTL_GIGA_MAC_VER_06:
4da19633 3544 rtl8169sce_hw_phy_config(tp);
8c7006aa 3545 break;
2857ffb7
FR		 3546 case RTL_GIGA_MAC_VER_07:
3547 case RTL_GIGA_MAC_VER_08:
3548 case RTL_GIGA_MAC_VER_09:
4da19633 3549 rtl8102e_hw_phy_config(tp);
2857ffb7 3550 break;
236b8082 3551 case RTL_GIGA_MAC_VER_11:
4da19633 3552 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3553 break;
3554 case RTL_GIGA_MAC_VER_12:
4da19633 3555 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3556 break;
3557 case RTL_GIGA_MAC_VER_17:
4da19633 3558 rtl8168bef_hw_phy_config(tp);
236b8082 3559 break;
867763c1 3560 case RTL_GIGA_MAC_VER_18:
4da19633 3561 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3562 break;
3563 case RTL_GIGA_MAC_VER_19:
4da19633 3564 rtl8168c_1_hw_phy_config(tp);
867763c1 3565 break;
7da97ec9 3566 case RTL_GIGA_MAC_VER_20:
4da19633 3567 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3568 break;
197ff761 3569 case RTL_GIGA_MAC_VER_21:
4da19633 3570 rtl8168c_3_hw_phy_config(tp);
197ff761 3571 break;
6fb07058 3572 case RTL_GIGA_MAC_VER_22:
4da19633 3573 rtl8168c_4_hw_phy_config(tp);
6fb07058 3574 break;
ef3386f0 3575 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3576 case RTL_GIGA_MAC_VER_24:
4da19633 3577 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3578 break;
5b538df9 3579 case RTL_GIGA_MAC_VER_25:
bca03d5f 3580 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3581 break;
3582 case RTL_GIGA_MAC_VER_26:
bca03d5f 3583 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3584 break;
3585 case RTL_GIGA_MAC_VER_27:
4da19633 3586 rtl8168d_3_hw_phy_config(tp);
5b538df9 3587 break;
e6de30d6 3588 case RTL_GIGA_MAC_VER_28:
3589 rtl8168d_4_hw_phy_config(tp);
3590 break;
5a5e4443
HW		 3591 case RTL_GIGA_MAC_VER_29:
3592 case RTL_GIGA_MAC_VER_30:
3593 rtl8105e_hw_phy_config(tp);
3594 break;
cecb5fd7
FR		 3595 case RTL_GIGA_MAC_VER_31:
3596 /* None. */
3597 break;
01dc7fec 3598 case RTL_GIGA_MAC_VER_32:
01dc7fec 3599 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3600 rtl8168e_1_hw_phy_config(tp);
3601 break;
3602 case RTL_GIGA_MAC_VER_34:
3603 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3604 break;
c2218925
HW		 3605 case RTL_GIGA_MAC_VER_35:
3606 rtl8168f_1_hw_phy_config(tp);
3607 break;
3608 case RTL_GIGA_MAC_VER_36:
3609 rtl8168f_2_hw_phy_config(tp);
3610 break;
ef3386f0 3611
7e18dca1
HW		 3612 case RTL_GIGA_MAC_VER_37:
3613 rtl8402_hw_phy_config(tp);
3614 break;
3615
b3d7b2f2
HW		 3616 case RTL_GIGA_MAC_VER_38:
3617 rtl8411_hw_phy_config(tp);
3618 break;
3619
5598bfe5
HW		 3620 case RTL_GIGA_MAC_VER_39:
3621 rtl8106e_hw_phy_config(tp);
3622 break;
3623
c558386b
HW		 3624 case RTL_GIGA_MAC_VER_40:
3625 rtl8168g_1_hw_phy_config(tp);
3626 break;
3627
3628 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3629 default:
3630 break;
3631 }
3632}
3633
da78dbff 3634static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3635{
1da177e4
LT		 3636 struct timer_list *timer = &tp->timer;
3637 void __iomem *ioaddr = tp->mmio_addr;
3638 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3639
bcf0bf90 3640 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3641
4da19633 3642 if (tp->phy_reset_pending(tp)) {
5b0384f4 3643 /*
1da177e4
LT		 3644 * A busy loop could burn quite a few cycles on nowadays CPU.
3645 * Let's delay the execution of the timer for a few ticks.
3646 */
3647 timeout = HZ/10;
3648 goto out_mod_timer;
3649 }
3650
3651 if (tp->link_ok(ioaddr))
da78dbff 3652 return;
1da177e4 3653
da78dbff 3654 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3655
4da19633 3656 tp->phy_reset_enable(tp);
1da177e4
LT		 3657
3658out_mod_timer:
3659 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3660}
3661
3662static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3663{
da78dbff
FR		 3664 if (!test_and_set_bit(flag, tp->wk.flags))
3665 schedule_work(&tp->wk.work);
da78dbff
FR		 3666}
3667
3668static void rtl8169_phy_timer(unsigned long __opaque)
3669{
3670 struct net_device *dev = (struct net_device *)__opaque;
3671 struct rtl8169_private *tp = netdev_priv(dev);
3672
98ddf986 3673 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3674}
3675
1da177e4
LT		 3676static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3677 void __iomem *ioaddr)
3678{
3679 iounmap(ioaddr);
3680 pci_release_regions(pdev);
87aeec76 3681 pci_clear_mwi(pdev);
1da177e4
LT		 3682 pci_disable_device(pdev);
3683 free_netdev(dev);
3684}
3685
ffc46952
FR		 3686DECLARE_RTL_COND(rtl_phy_reset_cond)
3687{
3688 return tp->phy_reset_pending(tp);
3689}
3690
bf793295
FR		 3691static void rtl8169_phy_reset(struct net_device *dev,
3692 struct rtl8169_private *tp)
3693{
4da19633 3694 tp->phy_reset_enable(tp);
ffc46952 3695 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3696}
3697
2544bfc0
FR		 3698static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3699{
3700 void __iomem *ioaddr = tp->mmio_addr;
3701
3702 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3703 (RTL_R8(PHYstatus) & TBI_Enable);
3704}
3705
4ff96fa6
FR		 3706static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3707{
3708 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3709
5615d9f1 3710 rtl_hw_phy_config(dev);
4ff96fa6 3711
77332894
MS		 3712 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3713 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3714 RTL_W8(0x82, 0x01);
3715 }
4ff96fa6 3716
6dccd16b
FR		 3717 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3718
3719 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3720 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3721
bcf0bf90 3722 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3723 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3724 RTL_W8(0x82, 0x01);
3725 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3726 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3727 }
3728
bf793295
FR		 3729 rtl8169_phy_reset(dev, tp);
3730
54405cde 3731 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3732 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3733 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3734 (tp->mii.supports_gmii ?
3735 ADVERTISED_1000baseT_Half |
3736 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3737
2544bfc0 3738 if (rtl_tbi_enabled(tp))
bf82c189 3739 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3740}
3741
773d2021
FR		 3742static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3743{
3744 void __iomem *ioaddr = tp->mmio_addr;
773d2021 3745
da78dbff 3746 rtl_lock_work(tp);
773d2021
FR		 3747
3748 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3749
9ecb9aab 3750 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 3751 RTL_R32(MAC4);
3752
9ecb9aab 3753 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 3754 RTL_R32(MAC0);
3755
9ecb9aab 3756 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3757 rtl_rar_exgmac_set(tp, addr);
c28aa385 3758
773d2021
FR		 3759 RTL_W8(Cfg9346, Cfg9346_Lock);
3760
da78dbff 3761 rtl_unlock_work(tp);
773d2021
FR		 3762}
3763
3764static int rtl_set_mac_address(struct net_device *dev, void *p)
3765{
3766 struct rtl8169_private *tp = netdev_priv(dev);
3767 struct sockaddr *addr = p;
3768
3769 if (!is_valid_ether_addr(addr->sa_data))
3770 return -EADDRNOTAVAIL;
3771
3772 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3773
3774 rtl_rar_set(tp, dev->dev_addr);
3775
3776 return 0;
3777}
3778
5f787a1a
FR		 3779static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3780{
3781 struct rtl8169_private *tp = netdev_priv(dev);
3782 struct mii_ioctl_data *data = if_mii(ifr);
3783
8b4ab28d
FR		 3784 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3785}
5f787a1a 3786
cecb5fd7
FR		 3787static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3788 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3789{
5f787a1a
FR		 3790 switch (cmd) {
3791 case SIOCGMIIPHY:
3792 data->phy_id = 32; /* Internal PHY */
3793 return 0;
3794
3795 case SIOCGMIIREG:
4da19633 3796 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3797 return 0;
3798
3799 case SIOCSMIIREG:
4da19633 3800 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3801 return 0;
3802 }
3803 return -EOPNOTSUPP;
3804}
3805
8b4ab28d
FR		 3806static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3807{
3808 return -EOPNOTSUPP;
3809}
3810
fbac58fc
FR		 3811static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3812{
3813 if (tp->features & RTL_FEATURE_MSI) {
3814 pci_disable_msi(pdev);
3815 tp->features &= ~RTL_FEATURE_MSI;
3816 }
3817}
3818
baf63293 3819static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 3820{
3821 struct mdio_ops *ops = &tp->mdio_ops;
3822
3823 switch (tp->mac_version) {
3824 case RTL_GIGA_MAC_VER_27:
3825 ops->write = r8168dp_1_mdio_write;
3826 ops->read = r8168dp_1_mdio_read;
3827 break;
e6de30d6 3828 case RTL_GIGA_MAC_VER_28:
4804b3b3 3829 case RTL_GIGA_MAC_VER_31:
e6de30d6 3830 ops->write = r8168dp_2_mdio_write;
3831 ops->read = r8168dp_2_mdio_read;
3832 break;
c558386b
HW		 3833 case RTL_GIGA_MAC_VER_40:
3834 case RTL_GIGA_MAC_VER_41:
3835 ops->write = r8168g_mdio_write;
3836 ops->read = r8168g_mdio_read;
3837 break;
c0e45c1c 3838 default:
3839 ops->write = r8169_mdio_write;
3840 ops->read = r8169_mdio_read;
3841 break;
3842 }
3843}
3844
649b3b8c 3845static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3846{
3847 void __iomem *ioaddr = tp->mmio_addr;
3848
3849 switch (tp->mac_version) {
b00e69de
CB		 3850 case RTL_GIGA_MAC_VER_25:
3851 case RTL_GIGA_MAC_VER_26:
649b3b8c 3852 case RTL_GIGA_MAC_VER_29:
3853 case RTL_GIGA_MAC_VER_30:
3854 case RTL_GIGA_MAC_VER_32:
3855 case RTL_GIGA_MAC_VER_33:
3856 case RTL_GIGA_MAC_VER_34:
7e18dca1 3857 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3858 case RTL_GIGA_MAC_VER_38:
5598bfe5 3859 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3860 case RTL_GIGA_MAC_VER_40:
3861 case RTL_GIGA_MAC_VER_41:
649b3b8c 3862 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3863 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3864 break;
3865 default:
3866 break;
3867 }
3868}
3869
3870static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3871{
3872 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3873 return false;
3874
3875 rtl_writephy(tp, 0x1f, 0x0000);
3876 rtl_writephy(tp, MII_BMCR, 0x0000);
3877
3878 rtl_wol_suspend_quirk(tp);
3879
3880 return true;
3881}
3882
065c27c1 3883static void r810x_phy_power_down(struct rtl8169_private *tp)
3884{
3885 rtl_writephy(tp, 0x1f, 0x0000);
3886 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3887}
3888
3889static void r810x_phy_power_up(struct rtl8169_private *tp)
3890{
3891 rtl_writephy(tp, 0x1f, 0x0000);
3892 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3893}
3894
3895static void r810x_pll_power_down(struct rtl8169_private *tp)
3896{
0004299a
HW		 3897 void __iomem *ioaddr = tp->mmio_addr;
3898
649b3b8c 3899 if (rtl_wol_pll_power_down(tp))
065c27c1 3900 return;
065c27c1 3901
3902 r810x_phy_power_down(tp);
0004299a
HW		 3903
3904 switch (tp->mac_version) {
3905 case RTL_GIGA_MAC_VER_07:
3906 case RTL_GIGA_MAC_VER_08:
3907 case RTL_GIGA_MAC_VER_09:
3908 case RTL_GIGA_MAC_VER_10:
3909 case RTL_GIGA_MAC_VER_13:
3910 case RTL_GIGA_MAC_VER_16:
3911 break;
3912 default:
3913 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3914 break;
3915 }
065c27c1 3916}
3917
3918static void r810x_pll_power_up(struct rtl8169_private *tp)
3919{
0004299a
HW		 3920 void __iomem *ioaddr = tp->mmio_addr;
3921
065c27c1 3922 r810x_phy_power_up(tp);
0004299a
HW		 3923
3924 switch (tp->mac_version) {
3925 case RTL_GIGA_MAC_VER_07:
3926 case RTL_GIGA_MAC_VER_08:
3927 case RTL_GIGA_MAC_VER_09:
3928 case RTL_GIGA_MAC_VER_10:
3929 case RTL_GIGA_MAC_VER_13:
3930 case RTL_GIGA_MAC_VER_16:
3931 break;
3932 default:
3933 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3934 break;
3935 }
065c27c1 3936}
3937
3938static void r8168_phy_power_up(struct rtl8169_private *tp)
3939{
3940 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3941 switch (tp->mac_version) {
3942 case RTL_GIGA_MAC_VER_11:
3943 case RTL_GIGA_MAC_VER_12:
3944 case RTL_GIGA_MAC_VER_17:
3945 case RTL_GIGA_MAC_VER_18:
3946 case RTL_GIGA_MAC_VER_19:
3947 case RTL_GIGA_MAC_VER_20:
3948 case RTL_GIGA_MAC_VER_21:
3949 case RTL_GIGA_MAC_VER_22:
3950 case RTL_GIGA_MAC_VER_23:
3951 case RTL_GIGA_MAC_VER_24:
3952 case RTL_GIGA_MAC_VER_25:
3953 case RTL_GIGA_MAC_VER_26:
3954 case RTL_GIGA_MAC_VER_27:
3955 case RTL_GIGA_MAC_VER_28:
3956 case RTL_GIGA_MAC_VER_31:
3957 rtl_writephy(tp, 0x0e, 0x0000);
3958 break;
3959 default:
3960 break;
3961 }
065c27c1 3962 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3963}
3964
3965static void r8168_phy_power_down(struct rtl8169_private *tp)
3966{
3967 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3968 switch (tp->mac_version) {
3969 case RTL_GIGA_MAC_VER_32:
3970 case RTL_GIGA_MAC_VER_33:
beb330a4 3971 case RTL_GIGA_MAC_VER_40:
3972 case RTL_GIGA_MAC_VER_41:
01dc7fec 3973 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3974 break;
3975
3976 case RTL_GIGA_MAC_VER_11:
3977 case RTL_GIGA_MAC_VER_12:
3978 case RTL_GIGA_MAC_VER_17:
3979 case RTL_GIGA_MAC_VER_18:
3980 case RTL_GIGA_MAC_VER_19:
3981 case RTL_GIGA_MAC_VER_20:
3982 case RTL_GIGA_MAC_VER_21:
3983 case RTL_GIGA_MAC_VER_22:
3984 case RTL_GIGA_MAC_VER_23:
3985 case RTL_GIGA_MAC_VER_24:
3986 case RTL_GIGA_MAC_VER_25:
3987 case RTL_GIGA_MAC_VER_26:
3988 case RTL_GIGA_MAC_VER_27:
3989 case RTL_GIGA_MAC_VER_28:
3990 case RTL_GIGA_MAC_VER_31:
3991 rtl_writephy(tp, 0x0e, 0x0200);
3992 default:
3993 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3994 break;
3995 }
065c27c1 3996}
3997
3998static void r8168_pll_power_down(struct rtl8169_private *tp)
3999{
4000 void __iomem *ioaddr = tp->mmio_addr;
4001
cecb5fd7
FR		 4002 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4003 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4004 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4005 r8168dp_check_dash(tp)) {
065c27c1 4006 return;
5d2e1957 4007 }
065c27c1 4008
cecb5fd7
FR		 4009 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4010 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4011 (RTL_R16(CPlusCmd) & ASF)) {
4012 return;
4013 }
4014
01dc7fec 4015 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4016 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4017 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4018
649b3b8c 4019 if (rtl_wol_pll_power_down(tp))
065c27c1 4020 return;
065c27c1 4021
4022 r8168_phy_power_down(tp);
4023
4024 switch (tp->mac_version) {
4025 case RTL_GIGA_MAC_VER_25:
4026 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4027 case RTL_GIGA_MAC_VER_27:
4028 case RTL_GIGA_MAC_VER_28:
4804b3b3 4029 case RTL_GIGA_MAC_VER_31:
01dc7fec 4030 case RTL_GIGA_MAC_VER_32:
4031 case RTL_GIGA_MAC_VER_33:
065c27c1 4032 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4033 break;
beb330a4 4034 case RTL_GIGA_MAC_VER_40:
4035 case RTL_GIGA_MAC_VER_41:
4036 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4037 0xfc000000, ERIAR_EXGMAC);
4038 break;
065c27c1 4039 }
4040}
4041
4042static void r8168_pll_power_up(struct rtl8169_private *tp)
4043{
4044 void __iomem *ioaddr = tp->mmio_addr;
4045
065c27c1 4046 switch (tp->mac_version) {
4047 case RTL_GIGA_MAC_VER_25:
4048 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4049 case RTL_GIGA_MAC_VER_27:
4050 case RTL_GIGA_MAC_VER_28:
4804b3b3 4051 case RTL_GIGA_MAC_VER_31:
01dc7fec 4052 case RTL_GIGA_MAC_VER_32:
4053 case RTL_GIGA_MAC_VER_33:
065c27c1 4054 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4055 break;
beb330a4 4056 case RTL_GIGA_MAC_VER_40:
4057 case RTL_GIGA_MAC_VER_41:
4058 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4059 0x00000000, ERIAR_EXGMAC);
4060 break;
065c27c1 4061 }
4062
4063 r8168_phy_power_up(tp);
4064}
4065
d58d46b5
FR		 4066static void rtl_generic_op(struct rtl8169_private *tp,
4067 void (*op)(struct rtl8169_private *))
065c27c1 4068{
4069 if (op)
4070 op(tp);
4071}
4072
4073static void rtl_pll_power_down(struct rtl8169_private *tp)
4074{
d58d46b5 4075 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4076}
4077
4078static void rtl_pll_power_up(struct rtl8169_private *tp)
4079{
d58d46b5 4080 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4081}
4082
baf63293 4083static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4084{
4085 struct pll_power_ops *ops = &tp->pll_power_ops;
4086
4087 switch (tp->mac_version) {
4088 case RTL_GIGA_MAC_VER_07:
4089 case RTL_GIGA_MAC_VER_08:
4090 case RTL_GIGA_MAC_VER_09:
4091 case RTL_GIGA_MAC_VER_10:
4092 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4093 case RTL_GIGA_MAC_VER_29:
4094 case RTL_GIGA_MAC_VER_30:
7e18dca1 4095 case RTL_GIGA_MAC_VER_37:
5598bfe5 4096 case RTL_GIGA_MAC_VER_39:
065c27c1 4097 ops->down = r810x_pll_power_down;
4098 ops->up = r810x_pll_power_up;
4099 break;
4100
4101 case RTL_GIGA_MAC_VER_11:
4102 case RTL_GIGA_MAC_VER_12:
4103 case RTL_GIGA_MAC_VER_17:
4104 case RTL_GIGA_MAC_VER_18:
4105 case RTL_GIGA_MAC_VER_19:
4106 case RTL_GIGA_MAC_VER_20:
4107 case RTL_GIGA_MAC_VER_21:
4108 case RTL_GIGA_MAC_VER_22:
4109 case RTL_GIGA_MAC_VER_23:
4110 case RTL_GIGA_MAC_VER_24:
4111 case RTL_GIGA_MAC_VER_25:
4112 case RTL_GIGA_MAC_VER_26:
4113 case RTL_GIGA_MAC_VER_27:
e6de30d6 4114 case RTL_GIGA_MAC_VER_28:
4804b3b3 4115 case RTL_GIGA_MAC_VER_31:
01dc7fec 4116 case RTL_GIGA_MAC_VER_32:
4117 case RTL_GIGA_MAC_VER_33:
70090424 4118 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4119 case RTL_GIGA_MAC_VER_35:
4120 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4121 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4122 case RTL_GIGA_MAC_VER_40:
4123 case RTL_GIGA_MAC_VER_41:
065c27c1 4124 ops->down = r8168_pll_power_down;
4125 ops->up = r8168_pll_power_up;
4126 break;
4127
4128 default:
4129 ops->down = NULL;
4130 ops->up = NULL;
4131 break;
4132 }
4133}
4134
e542a226
HW		 4135static void rtl_init_rxcfg(struct rtl8169_private *tp)
4136{
4137 void __iomem *ioaddr = tp->mmio_addr;
4138
4139 switch (tp->mac_version) {
4140 case RTL_GIGA_MAC_VER_01:
4141 case RTL_GIGA_MAC_VER_02:
4142 case RTL_GIGA_MAC_VER_03:
4143 case RTL_GIGA_MAC_VER_04:
4144 case RTL_GIGA_MAC_VER_05:
4145 case RTL_GIGA_MAC_VER_06:
4146 case RTL_GIGA_MAC_VER_10:
4147 case RTL_GIGA_MAC_VER_11:
4148 case RTL_GIGA_MAC_VER_12:
4149 case RTL_GIGA_MAC_VER_13:
4150 case RTL_GIGA_MAC_VER_14:
4151 case RTL_GIGA_MAC_VER_15:
4152 case RTL_GIGA_MAC_VER_16:
4153 case RTL_GIGA_MAC_VER_17:
4154 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4155 break;
4156 case RTL_GIGA_MAC_VER_18:
4157 case RTL_GIGA_MAC_VER_19:
4158 case RTL_GIGA_MAC_VER_20:
4159 case RTL_GIGA_MAC_VER_21:
4160 case RTL_GIGA_MAC_VER_22:
4161 case RTL_GIGA_MAC_VER_23:
4162 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4163 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4164 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4165 break;
beb330a4 4166 case RTL_GIGA_MAC_VER_40:
4167 case RTL_GIGA_MAC_VER_41:
4168 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4169 break;
e542a226
HW		 4170 default:
4171 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4172 break;
4173 }
4174}
4175
92fc43b4
HW		 4176static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4177{
9fba0812 4178 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4179}
4180
d58d46b5
FR		 4181static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4182{
9c5028e9 4183 void __iomem *ioaddr = tp->mmio_addr;
4184
4185 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4186 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4187 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4188}
4189
4190static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4191{
9c5028e9 4192 void __iomem *ioaddr = tp->mmio_addr;
4193
4194 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4195 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4196 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4197}
4198
4199static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4200{
4201 void __iomem *ioaddr = tp->mmio_addr;
4202
4203 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4204 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4205 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4206}
4207
4208static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4209{
4210 void __iomem *ioaddr = tp->mmio_addr;
4211
4212 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4213 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4214 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4215}
4216
4217static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4218{
4219 void __iomem *ioaddr = tp->mmio_addr;
4220
4221 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4222}
4223
4224static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4225{
4226 void __iomem *ioaddr = tp->mmio_addr;
4227
4228 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4229}
4230
4231static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4232{
4233 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4234
4235 RTL_W8(MaxTxPacketSize, 0x3f);
4236 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4237 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4238 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4239}
4240
4241static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4242{
4243 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4244
4245 RTL_W8(MaxTxPacketSize, 0x0c);
4246 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4247 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4248 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4249}
4250
4251static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4252{
4253 rtl_tx_performance_tweak(tp->pci_dev,
4254 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4255}
4256
4257static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4258{
4259 rtl_tx_performance_tweak(tp->pci_dev,
4260 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4261}
4262
4263static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4264{
4265 void __iomem *ioaddr = tp->mmio_addr;
4266
4267 r8168b_0_hw_jumbo_enable(tp);
4268
4269 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4270}
4271
4272static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4273{
4274 void __iomem *ioaddr = tp->mmio_addr;
4275
4276 r8168b_0_hw_jumbo_disable(tp);
4277
4278 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4279}
4280
baf63293 4281static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4282{
4283 struct jumbo_ops *ops = &tp->jumbo_ops;
4284
4285 switch (tp->mac_version) {
4286 case RTL_GIGA_MAC_VER_11:
4287 ops->disable = r8168b_0_hw_jumbo_disable;
4288 ops->enable = r8168b_0_hw_jumbo_enable;
4289 break;
4290 case RTL_GIGA_MAC_VER_12:
4291 case RTL_GIGA_MAC_VER_17:
4292 ops->disable = r8168b_1_hw_jumbo_disable;
4293 ops->enable = r8168b_1_hw_jumbo_enable;
4294 break;
4295 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4296 case RTL_GIGA_MAC_VER_19:
4297 case RTL_GIGA_MAC_VER_20:
4298 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4299 case RTL_GIGA_MAC_VER_22:
4300 case RTL_GIGA_MAC_VER_23:
4301 case RTL_GIGA_MAC_VER_24:
4302 case RTL_GIGA_MAC_VER_25:
4303 case RTL_GIGA_MAC_VER_26:
4304 ops->disable = r8168c_hw_jumbo_disable;
4305 ops->enable = r8168c_hw_jumbo_enable;
4306 break;
4307 case RTL_GIGA_MAC_VER_27:
4308 case RTL_GIGA_MAC_VER_28:
4309 ops->disable = r8168dp_hw_jumbo_disable;
4310 ops->enable = r8168dp_hw_jumbo_enable;
4311 break;
4312 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4313 case RTL_GIGA_MAC_VER_32:
4314 case RTL_GIGA_MAC_VER_33:
4315 case RTL_GIGA_MAC_VER_34:
4316 ops->disable = r8168e_hw_jumbo_disable;
4317 ops->enable = r8168e_hw_jumbo_enable;
4318 break;
4319
4320 /*
4321 * No action needed for jumbo frames with 8169.
4322 * No jumbo for 810x at all.
4323 */
c558386b
HW		 4324 case RTL_GIGA_MAC_VER_40:
4325 case RTL_GIGA_MAC_VER_41:
d58d46b5
FR		 4326 default:
4327 ops->disable = NULL;
4328 ops->enable = NULL;
4329 break;
4330 }
4331}
4332
ffc46952
FR		 4333DECLARE_RTL_COND(rtl_chipcmd_cond)
4334{
4335 void __iomem *ioaddr = tp->mmio_addr;
4336
4337 return RTL_R8(ChipCmd) & CmdReset;
4338}
4339
6f43adc8
FR		 4340static void rtl_hw_reset(struct rtl8169_private *tp)
4341{
4342 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4343
6f43adc8
FR		 4344 RTL_W8(ChipCmd, CmdReset);
4345
ffc46952 4346 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4347}
4348
b6ffd97f 4349static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4350{
b6ffd97f
FR		 4351 struct rtl_fw *rtl_fw;
4352 const char *name;
4353 int rc = -ENOMEM;
953a12cc 4354
b6ffd97f
FR		 4355 name = rtl_lookup_firmware_name(tp);
4356 if (!name)
4357 goto out_no_firmware;
953a12cc 4358
b6ffd97f
FR		 4359 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4360 if (!rtl_fw)
4361 goto err_warn;
31bd204f 4362
b6ffd97f
FR		 4363 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4364 if (rc < 0)
4365 goto err_free;
4366
fd112f2e
FR		 4367 rc = rtl_check_firmware(tp, rtl_fw);
4368 if (rc < 0)
4369 goto err_release_firmware;
4370
b6ffd97f
FR		 4371 tp->rtl_fw = rtl_fw;
4372out:
4373 return;
4374
fd112f2e
FR		 4375err_release_firmware:
4376 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4377err_free:
4378 kfree(rtl_fw);
4379err_warn:
4380 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4381 name, rc);
4382out_no_firmware:
4383 tp->rtl_fw = NULL;
4384 goto out;
4385}
4386
4387static void rtl_request_firmware(struct rtl8169_private *tp)
4388{
4389 if (IS_ERR(tp->rtl_fw))
4390 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4391}
4392
92fc43b4
HW		 4393static void rtl_rx_close(struct rtl8169_private *tp)
4394{
4395 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4396
1687b566 4397 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4398}
4399
ffc46952
FR		 4400DECLARE_RTL_COND(rtl_npq_cond)
4401{
4402 void __iomem *ioaddr = tp->mmio_addr;
4403
4404 return RTL_R8(TxPoll) & NPQ;
4405}
4406
4407DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4408{
4409 void __iomem *ioaddr = tp->mmio_addr;
4410
4411 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4412}
4413
e6de30d6 4414static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4415{
e6de30d6 4416 void __iomem *ioaddr = tp->mmio_addr;
4417
1da177e4 4418 /* Disable interrupts */
811fd301 4419 rtl8169_irq_mask_and_ack(tp);
1da177e4 4420
92fc43b4
HW		 4421 rtl_rx_close(tp);
4422
5d2e1957 4423 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4424 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4425 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4426 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4427 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4428 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4429 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4430 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4431 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4432 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
b3d7b2f2 4433 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4434 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4435 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4436 } else {
4437 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4438 udelay(100);
e6de30d6 4439 }
4440
92fc43b4 4441 rtl_hw_reset(tp);
1da177e4
LT		 4442}
4443
7f796d83 4444static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4445{
4446 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4447
4448 /* Set DMA burst size and Interframe Gap Time */
4449 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4450 (InterFrameGap << TxInterFrameGapShift));
4451}
4452
07ce4064 4453static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4454{
4455 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4456
07ce4064
FR		 4457 tp->hw_start(dev);
4458
da78dbff 4459 rtl_irq_enable_all(tp);
07ce4064
FR		 4460}
4461
7f796d83
FR		 4462static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4463 void __iomem *ioaddr)
4464{
4465 /*
4466 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4467 * register to be written before TxDescAddrLow to work.
4468 * Switching from MMIO to I/O access fixes the issue as well.
4469 */
4470 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4471 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4472 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4473 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4474}
4475
4476static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4477{
4478 u16 cmd;
4479
4480 cmd = RTL_R16(CPlusCmd);
4481 RTL_W16(CPlusCmd, cmd);
4482 return cmd;
4483}
4484
fdd7b4c3 4485static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4486{
4487 /* Low hurts. Let's disable the filtering. */
207d6e87 4488 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4489}
4490
6dccd16b
FR		 4491static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4492{
3744100e 4493 static const struct rtl_cfg2_info {
6dccd16b
FR		 4494 u32 mac_version;
4495 u32 clk;
4496 u32 val;
4497 } cfg2_info [] = {
4498 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4499 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4500 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4501 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4502 };
4503 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4504 unsigned int i;
4505 u32 clk;
4506
4507 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4508 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4509 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4510 RTL_W32(0x7c, p->val);
4511 break;
4512 }
4513 }
4514}
4515
e6b763ea
FR		 4516static void rtl_set_rx_mode(struct net_device *dev)
4517{
4518 struct rtl8169_private *tp = netdev_priv(dev);
4519 void __iomem *ioaddr = tp->mmio_addr;
4520 u32 mc_filter[2]; /* Multicast hash filter */
4521 int rx_mode;
4522 u32 tmp = 0;
4523
4524 if (dev->flags & IFF_PROMISC) {
4525 /* Unconditionally log net taps. */
4526 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4527 rx_mode =
4528 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4529 AcceptAllPhys;
4530 mc_filter[1] = mc_filter[0] = 0xffffffff;
4531 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4532 (dev->flags & IFF_ALLMULTI)) {
4533 /* Too many to filter perfectly -- accept all multicasts. */
4534 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4535 mc_filter[1] = mc_filter[0] = 0xffffffff;
4536 } else {
4537 struct netdev_hw_addr *ha;
4538
4539 rx_mode = AcceptBroadcast | AcceptMyPhys;
4540 mc_filter[1] = mc_filter[0] = 0;
4541 netdev_for_each_mc_addr(ha, dev) {
4542 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4543 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4544 rx_mode |= AcceptMulticast;
4545 }
4546 }
4547
4548 if (dev->features & NETIF_F_RXALL)
4549 rx_mode |= (AcceptErr | AcceptRunt);
4550
4551 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4552
4553 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4554 u32 data = mc_filter[0];
4555
4556 mc_filter[0] = swab32(mc_filter[1]);
4557 mc_filter[1] = swab32(data);
4558 }
4559
0481776b
NW		 4560 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4561 mc_filter[1] = mc_filter[0] = 0xffffffff;
4562
e6b763ea
FR		 4563 RTL_W32(MAR0 + 4, mc_filter[1]);
4564 RTL_W32(MAR0 + 0, mc_filter[0]);
4565
4566 RTL_W32(RxConfig, tmp);
4567}
4568
07ce4064
FR		 4569static void rtl_hw_start_8169(struct net_device *dev)
4570{
4571 struct rtl8169_private *tp = netdev_priv(dev);
4572 void __iomem *ioaddr = tp->mmio_addr;
4573 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4574
9cb427b6
FR		 4575 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4576 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4577 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4578 }
4579
1da177e4 4580 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4581 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4582 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4583 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4584 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4585 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4586
e542a226
HW		 4587 rtl_init_rxcfg(tp);
4588
f0298f81 4589 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4590
6f0333b8 4591 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4592
cecb5fd7
FR		 4593 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4594 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4595 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4596 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4597 rtl_set_rx_tx_config_registers(tp);
1da177e4 4598
7f796d83 4599 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4600
cecb5fd7
FR		 4601 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4602 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4603 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4604 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4605 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4606 }
4607
bcf0bf90
FR		 4608 RTL_W16(CPlusCmd, tp->cp_cmd);
4609
6dccd16b
FR		 4610 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4611
1da177e4
LT		 4612 /*
4613 * Undocumented corner. Supposedly:
4614 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4615 */
4616 RTL_W16(IntrMitigate, 0x0000);
4617
7f796d83 4618 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4619
cecb5fd7
FR		 4620 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4621 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4622 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4623 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4624 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4625 rtl_set_rx_tx_config_registers(tp);
4626 }
4627
1da177e4 4628 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4629
4630 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4631 RTL_R8(IntrMask);
1da177e4
LT		 4632
4633 RTL_W32(RxMissed, 0);
4634
07ce4064 4635 rtl_set_rx_mode(dev);
1da177e4
LT		 4636
4637 /* no early-rx interrupts */
4638 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4639}
1da177e4 4640
beb1fe18
HW		 4641static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4642{
4643 if (tp->csi_ops.write)
52989f0e 4644 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4645}
4646
4647static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4648{
52989f0e 4649 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4650}
4651
4652static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4653{
4654 u32 csi;
4655
beb1fe18
HW		 4656 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4657 rtl_csi_write(tp, 0x070c, csi | bits);
4658}
4659
4660static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4661{
4662 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4663}
4664
beb1fe18 4665static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4666{
beb1fe18 4667 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4668}
4669
ffc46952
FR		 4670DECLARE_RTL_COND(rtl_csiar_cond)
4671{
4672 void __iomem *ioaddr = tp->mmio_addr;
4673
4674 return RTL_R32(CSIAR) & CSIAR_FLAG;
4675}
4676
52989f0e 4677static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4678{
52989f0e 4679 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4680
4681 RTL_W32(CSIDR, value);
4682 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4683 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4684
ffc46952 4685 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4686}
4687
52989f0e 4688static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4689{
52989f0e 4690 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4691
4692 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4693 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4694
ffc46952
FR		 4695 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4696 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4697}
4698
52989f0e 4699static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4700{
52989f0e 4701 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4702
4703 RTL_W32(CSIDR, value);
4704 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4705 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4706 CSIAR_FUNC_NIC);
4707
ffc46952 4708 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4709}
4710
52989f0e 4711static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4712{
52989f0e 4713 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4714
4715 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4716 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4717
ffc46952
FR		 4718 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4719 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4720}
4721
baf63293 4722static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 4723{
4724 struct csi_ops *ops = &tp->csi_ops;
4725
4726 switch (tp->mac_version) {
4727 case RTL_GIGA_MAC_VER_01:
4728 case RTL_GIGA_MAC_VER_02:
4729 case RTL_GIGA_MAC_VER_03:
4730 case RTL_GIGA_MAC_VER_04:
4731 case RTL_GIGA_MAC_VER_05:
4732 case RTL_GIGA_MAC_VER_06:
4733 case RTL_GIGA_MAC_VER_10:
4734 case RTL_GIGA_MAC_VER_11:
4735 case RTL_GIGA_MAC_VER_12:
4736 case RTL_GIGA_MAC_VER_13:
4737 case RTL_GIGA_MAC_VER_14:
4738 case RTL_GIGA_MAC_VER_15:
4739 case RTL_GIGA_MAC_VER_16:
4740 case RTL_GIGA_MAC_VER_17:
4741 ops->write = NULL;
4742 ops->read = NULL;
4743 break;
4744
7e18dca1 4745 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4746 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4747 ops->write = r8402_csi_write;
4748 ops->read = r8402_csi_read;
4749 break;
4750
beb1fe18
HW		 4751 default:
4752 ops->write = r8169_csi_write;
4753 ops->read = r8169_csi_read;
4754 break;
4755 }
dacf8154
FR		 4756}
4757
4758struct ephy_info {
4759 unsigned int offset;
4760 u16 mask;
4761 u16 bits;
4762};
4763
fdf6fc06
FR		 4764static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4765 int len)
dacf8154
FR		 4766{
4767 u16 w;
4768
4769 while (len-- > 0) {
fdf6fc06
FR		 4770 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4771 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4772 e++;
4773 }
4774}
4775
b726e493
FR		 4776static void rtl_disable_clock_request(struct pci_dev *pdev)
4777{
7d7903b2
JL		 4778 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4779 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4780}
4781
e6de30d6 4782static void rtl_enable_clock_request(struct pci_dev *pdev)
4783{
7d7903b2
JL		 4784 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4785 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4786}
4787
b726e493
FR		 4788#define R8168_CPCMD_QUIRK_MASK (\
4789 EnableBist | \
4790 Mac_dbgo_oe | \
4791 Force_half_dup | \
4792 Force_rxflow_en | \
4793 Force_txflow_en | \
4794 Cxpl_dbg_sel | \
4795 ASF | \
4796 PktCntrDisable | \
4797 Mac_dbgo_sel)
4798
beb1fe18 4799static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4800{
beb1fe18
HW		 4801 void __iomem *ioaddr = tp->mmio_addr;
4802 struct pci_dev *pdev = tp->pci_dev;
4803
b726e493
FR		 4804 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4805
4806 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4807
faf1e785 4808 if (tp->dev->mtu <= ETH_DATA_LEN) {
4809 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4810 PCI_EXP_DEVCTL_NOSNOOP_EN);
4811 }
219a1e9d
FR		 4812}
4813
beb1fe18 4814static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4815{
beb1fe18
HW		 4816 void __iomem *ioaddr = tp->mmio_addr;
4817
4818 rtl_hw_start_8168bb(tp);
b726e493 4819
f0298f81 4820 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4821
4822 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4823}
4824
beb1fe18 4825static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4826{
beb1fe18
HW		 4827 void __iomem *ioaddr = tp->mmio_addr;
4828 struct pci_dev *pdev = tp->pci_dev;
4829
b726e493
FR		 4830 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4831
4832 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4833
faf1e785 4834 if (tp->dev->mtu <= ETH_DATA_LEN)
4835 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4836
4837 rtl_disable_clock_request(pdev);
4838
4839 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4840}
4841
beb1fe18 4842static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4843{
350f7596 4844 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4845 { 0x01, 0, 0x0001 },
4846 { 0x02, 0x0800, 0x1000 },
4847 { 0x03, 0, 0x0042 },
4848 { 0x06, 0x0080, 0x0000 },
4849 { 0x07, 0, 0x2000 }
4850 };
4851
beb1fe18 4852 rtl_csi_access_enable_2(tp);
b726e493 4853
fdf6fc06 4854 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4855
beb1fe18 4856 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4857}
4858
beb1fe18 4859static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4860{
beb1fe18
HW		 4861 void __iomem *ioaddr = tp->mmio_addr;
4862 struct pci_dev *pdev = tp->pci_dev;
4863
4864 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4865
4866 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4867
faf1e785 4868 if (tp->dev->mtu <= ETH_DATA_LEN)
4869 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 4870
4871 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4872}
4873
beb1fe18 4874static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4875{
beb1fe18
HW		 4876 void __iomem *ioaddr = tp->mmio_addr;
4877 struct pci_dev *pdev = tp->pci_dev;
4878
4879 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4880
4881 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4882
4883 /* Magic. */
4884 RTL_W8(DBG_REG, 0x20);
4885
f0298f81 4886 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4887
faf1e785 4888 if (tp->dev->mtu <= ETH_DATA_LEN)
4889 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 4890
4891 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4892}
4893
beb1fe18 4894static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4895{
beb1fe18 4896 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4897 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4898 { 0x02, 0x0800, 0x1000 },
4899 { 0x03, 0, 0x0002 },
4900 { 0x06, 0x0080, 0x0000 }
4901 };
4902
beb1fe18 4903 rtl_csi_access_enable_2(tp);
b726e493
FR		 4904
4905 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4906
fdf6fc06 4907 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4908
beb1fe18 4909 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4910}
4911
beb1fe18 4912static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4913{
350f7596 4914 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4915 { 0x01, 0, 0x0001 },
4916 { 0x03, 0x0400, 0x0220 }
4917 };
4918
beb1fe18 4919 rtl_csi_access_enable_2(tp);
b726e493 4920
fdf6fc06 4921 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4922
beb1fe18 4923 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4924}
4925
beb1fe18 4926static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4927{
beb1fe18 4928 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4929}
4930
beb1fe18 4931static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4932{
beb1fe18 4933 rtl_csi_access_enable_2(tp);
6fb07058 4934
beb1fe18 4935 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4936}
4937
beb1fe18 4938static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4939{
beb1fe18
HW		 4940 void __iomem *ioaddr = tp->mmio_addr;
4941 struct pci_dev *pdev = tp->pci_dev;
4942
4943 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4944
4945 rtl_disable_clock_request(pdev);
4946
f0298f81 4947 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 4948
faf1e785 4949 if (tp->dev->mtu <= ETH_DATA_LEN)
4950 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 4951
4952 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4953}
4954
beb1fe18 4955static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4956{
beb1fe18
HW		 4957 void __iomem *ioaddr = tp->mmio_addr;
4958 struct pci_dev *pdev = tp->pci_dev;
4959
4960 rtl_csi_access_enable_1(tp);
4804b3b3 4961
faf1e785 4962 if (tp->dev->mtu <= ETH_DATA_LEN)
4963 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 4964
4965 RTL_W8(MaxTxPacketSize, TxPacketMax);
4966
4967 rtl_disable_clock_request(pdev);
4968}
4969
beb1fe18 4970static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4971{
beb1fe18
HW		 4972 void __iomem *ioaddr = tp->mmio_addr;
4973 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4974 static const struct ephy_info e_info_8168d_4[] = {
4975 { 0x0b, ~0, 0x48 },
4976 { 0x19, 0x20, 0x50 },
4977 { 0x0c, ~0, 0x20 }
4978 };
4979 int i;
4980
beb1fe18 4981 rtl_csi_access_enable_1(tp);
e6de30d6 4982
4983 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4984
4985 RTL_W8(MaxTxPacketSize, TxPacketMax);
4986
4987 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4988 const struct ephy_info *e = e_info_8168d_4 + i;
4989 u16 w;
4990
fdf6fc06
FR		 4991 w = rtl_ephy_read(tp, e->offset);
4992 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 4993 }
4994
4995 rtl_enable_clock_request(pdev);
4996}
4997
beb1fe18 4998static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4999{
beb1fe18
HW		 5000 void __iomem *ioaddr = tp->mmio_addr;
5001 struct pci_dev *pdev = tp->pci_dev;
70090424 5002 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5003 { 0x00, 0x0200, 0x0100 },
5004 { 0x00, 0x0000, 0x0004 },
5005 { 0x06, 0x0002, 0x0001 },
5006 { 0x06, 0x0000, 0x0030 },
5007 { 0x07, 0x0000, 0x2000 },
5008 { 0x00, 0x0000, 0x0020 },
5009 { 0x03, 0x5800, 0x2000 },
5010 { 0x03, 0x0000, 0x0001 },
5011 { 0x01, 0x0800, 0x1000 },
5012 { 0x07, 0x0000, 0x4000 },
5013 { 0x1e, 0x0000, 0x2000 },
5014 { 0x19, 0xffff, 0xfe6c },
5015 { 0x0a, 0x0000, 0x0040 }
5016 };
5017
beb1fe18 5018 rtl_csi_access_enable_2(tp);
01dc7fec 5019
fdf6fc06 5020 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5021
faf1e785 5022 if (tp->dev->mtu <= ETH_DATA_LEN)
5023 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5024
5025 RTL_W8(MaxTxPacketSize, TxPacketMax);
5026
5027 rtl_disable_clock_request(pdev);
5028
5029 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5030 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5031 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5032
cecb5fd7 5033 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5034}
5035
beb1fe18 5036static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5037{
beb1fe18
HW		 5038 void __iomem *ioaddr = tp->mmio_addr;
5039 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5040 static const struct ephy_info e_info_8168e_2[] = {
5041 { 0x09, 0x0000, 0x0080 },
5042 { 0x19, 0x0000, 0x0224 }
5043 };
5044
beb1fe18 5045 rtl_csi_access_enable_1(tp);
70090424 5046
fdf6fc06 5047 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5048
faf1e785 5049 if (tp->dev->mtu <= ETH_DATA_LEN)
5050 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5051
fdf6fc06
FR		 5052 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5053 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5054 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5055 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5056 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5057 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5058 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5059 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5060
3090bd9a 5061 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5062
4521e1a9
FR		 5063 rtl_disable_clock_request(pdev);
5064
70090424
HW		 5065 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5066 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5067
5068 /* Adjust EEE LED frequency */
5069 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5070
5071 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5072 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5073 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5074}
5075
5f886e08 5076static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5077{
beb1fe18
HW		 5078 void __iomem *ioaddr = tp->mmio_addr;
5079 struct pci_dev *pdev = tp->pci_dev;
c2218925 5080
5f886e08 5081 rtl_csi_access_enable_2(tp);
c2218925
HW		 5082
5083 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5084
fdf6fc06
FR		 5085 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5086 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5087 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5088 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5089 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5090 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5091 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5092 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5093 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5094 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5095
5096 RTL_W8(MaxTxPacketSize, EarlySize);
5097
4521e1a9
FR		 5098 rtl_disable_clock_request(pdev);
5099
c2218925
HW		 5100 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5101 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5102 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5103 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5104 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5105}
5106
5f886e08
HW		 5107static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5108{
5109 void __iomem *ioaddr = tp->mmio_addr;
5110 static const struct ephy_info e_info_8168f_1[] = {
5111 { 0x06, 0x00c0, 0x0020 },
5112 { 0x08, 0x0001, 0x0002 },
5113 { 0x09, 0x0000, 0x0080 },
5114 { 0x19, 0x0000, 0x0224 }
5115 };
5116
5117 rtl_hw_start_8168f(tp);
5118
fdf6fc06 5119 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5120
fdf6fc06 5121 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5122
5123 /* Adjust EEE LED frequency */
5124 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5125}
5126
b3d7b2f2
HW		 5127static void rtl_hw_start_8411(struct rtl8169_private *tp)
5128{
b3d7b2f2
HW		 5129 static const struct ephy_info e_info_8168f_1[] = {
5130 { 0x06, 0x00c0, 0x0020 },
5131 { 0x0f, 0xffff, 0x5200 },
5132 { 0x1e, 0x0000, 0x4000 },
5133 { 0x19, 0x0000, 0x0224 }
5134 };
5135
5136 rtl_hw_start_8168f(tp);
5137
fdf6fc06 5138 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5139
fdf6fc06 5140 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5141}
5142
c558386b
HW		 5143static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5144{
5145 void __iomem *ioaddr = tp->mmio_addr;
5146 struct pci_dev *pdev = tp->pci_dev;
5147
beb330a4 5148 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5149
c558386b
HW		 5150 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5151 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5152 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5153 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5154
5155 rtl_csi_access_enable_1(tp);
5156
5157 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5158
5159 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5160 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5161 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b
HW		 5162
5163 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4521e1a9 5164 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 5165 RTL_W8(MaxTxPacketSize, EarlySize);
5166
5167 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5168 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5169
5170 /* Adjust EEE LED frequency */
5171 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5172
beb330a4 5173 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5174 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
c558386b
HW		 5175}
5176
07ce4064
FR		 5177static void rtl_hw_start_8168(struct net_device *dev)
5178{
2dd99530
FR		 5179 struct rtl8169_private *tp = netdev_priv(dev);
5180 void __iomem *ioaddr = tp->mmio_addr;
5181
5182 RTL_W8(Cfg9346, Cfg9346_Unlock);
5183
f0298f81 5184 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5185
6f0333b8 5186 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5187
0e485150 5188 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5189
5190 RTL_W16(CPlusCmd, tp->cp_cmd);
5191
0e485150 5192 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5193
0e485150 5194 /* Work around for RxFIFO overflow. */
811fd301 5195 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5196 tp->event_slow |= RxFIFOOver | PCSTimeout;
5197 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5198 }
5199
5200 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5201
b8363901
FR		 5202 rtl_set_rx_mode(dev);
5203
5204 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5205 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 5206
5207 RTL_R8(IntrMask);
5208
219a1e9d
FR		 5209 switch (tp->mac_version) {
5210 case RTL_GIGA_MAC_VER_11:
beb1fe18 5211 rtl_hw_start_8168bb(tp);
4804b3b3 5212 break;
219a1e9d
FR		 5213
5214 case RTL_GIGA_MAC_VER_12:
5215 case RTL_GIGA_MAC_VER_17:
beb1fe18 5216 rtl_hw_start_8168bef(tp);
4804b3b3 5217 break;
219a1e9d
FR		 5218
5219 case RTL_GIGA_MAC_VER_18:
beb1fe18 5220 rtl_hw_start_8168cp_1(tp);
4804b3b3 5221 break;
219a1e9d
FR		 5222
5223 case RTL_GIGA_MAC_VER_19:
beb1fe18 5224 rtl_hw_start_8168c_1(tp);
4804b3b3 5225 break;
219a1e9d
FR		 5226
5227 case RTL_GIGA_MAC_VER_20:
beb1fe18 5228 rtl_hw_start_8168c_2(tp);
4804b3b3 5229 break;
219a1e9d 5230
197ff761 5231 case RTL_GIGA_MAC_VER_21:
beb1fe18 5232 rtl_hw_start_8168c_3(tp);
4804b3b3 5233 break;
197ff761 5234
6fb07058 5235 case RTL_GIGA_MAC_VER_22:
beb1fe18 5236 rtl_hw_start_8168c_4(tp);
4804b3b3 5237 break;
6fb07058 5238
ef3386f0 5239 case RTL_GIGA_MAC_VER_23:
beb1fe18 5240 rtl_hw_start_8168cp_2(tp);
4804b3b3 5241 break;
ef3386f0 5242
7f3e3d3a 5243 case RTL_GIGA_MAC_VER_24:
beb1fe18 5244 rtl_hw_start_8168cp_3(tp);
4804b3b3 5245 break;
7f3e3d3a 5246
5b538df9 5247 case RTL_GIGA_MAC_VER_25:
daf9df6d 5248 case RTL_GIGA_MAC_VER_26:
5249 case RTL_GIGA_MAC_VER_27:
beb1fe18 5250 rtl_hw_start_8168d(tp);
4804b3b3 5251 break;
5b538df9 5252
e6de30d6 5253 case RTL_GIGA_MAC_VER_28:
beb1fe18 5254 rtl_hw_start_8168d_4(tp);
4804b3b3 5255 break;
cecb5fd7 5256
4804b3b3 5257 case RTL_GIGA_MAC_VER_31:
beb1fe18 5258 rtl_hw_start_8168dp(tp);
4804b3b3 5259 break;
5260
01dc7fec 5261 case RTL_GIGA_MAC_VER_32:
5262 case RTL_GIGA_MAC_VER_33:
beb1fe18 5263 rtl_hw_start_8168e_1(tp);
70090424
HW		 5264 break;
5265 case RTL_GIGA_MAC_VER_34:
beb1fe18 5266 rtl_hw_start_8168e_2(tp);
01dc7fec 5267 break;
e6de30d6 5268
c2218925
HW		 5269 case RTL_GIGA_MAC_VER_35:
5270 case RTL_GIGA_MAC_VER_36:
beb1fe18 5271 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5272 break;
5273
b3d7b2f2
HW		 5274 case RTL_GIGA_MAC_VER_38:
5275 rtl_hw_start_8411(tp);
5276 break;
5277
c558386b
HW		 5278 case RTL_GIGA_MAC_VER_40:
5279 case RTL_GIGA_MAC_VER_41:
5280 rtl_hw_start_8168g_1(tp);
5281 break;
5282
219a1e9d
FR		 5283 default:
5284 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5285 dev->name, tp->mac_version);
4804b3b3 5286 break;
219a1e9d 5287 }
2dd99530 5288
0e485150
FR		 5289 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5290
b8363901
FR		 5291 RTL_W8(Cfg9346, Cfg9346_Lock);
5292
2dd99530 5293 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5294}
1da177e4 5295
2857ffb7
FR		 5296#define R810X_CPCMD_QUIRK_MASK (\
5297 EnableBist | \
5298 Mac_dbgo_oe | \
5299 Force_half_dup | \
5edcc537 5300 Force_rxflow_en | \
2857ffb7
FR		 5301 Force_txflow_en | \
5302 Cxpl_dbg_sel | \
5303 ASF | \
5304 PktCntrDisable | \
d24e9aaf 5305 Mac_dbgo_sel)
2857ffb7 5306
beb1fe18 5307static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5308{
beb1fe18
HW		 5309 void __iomem *ioaddr = tp->mmio_addr;
5310 struct pci_dev *pdev = tp->pci_dev;
350f7596 5311 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5312 { 0x01, 0, 0x6e65 },
5313 { 0x02, 0, 0x091f },
5314 { 0x03, 0, 0xc2f9 },
5315 { 0x06, 0, 0xafb5 },
5316 { 0x07, 0, 0x0e00 },
5317 { 0x19, 0, 0xec80 },
5318 { 0x01, 0, 0x2e65 },
5319 { 0x01, 0, 0x6e65 }
5320 };
5321 u8 cfg1;
5322
beb1fe18 5323 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5324
5325 RTL_W8(DBG_REG, FIX_NAK_1);
5326
5327 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5328
5329 RTL_W8(Config1,
5330 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5331 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5332
5333 cfg1 = RTL_R8(Config1);
5334 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5335 RTL_W8(Config1, cfg1 & ~LEDS0);
5336
fdf6fc06 5337 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5338}
5339
beb1fe18 5340static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5341{
beb1fe18
HW		 5342 void __iomem *ioaddr = tp->mmio_addr;
5343 struct pci_dev *pdev = tp->pci_dev;
5344
5345 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5346
5347 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5348
5349 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5350 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5351}
5352
beb1fe18 5353static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5354{
beb1fe18 5355 rtl_hw_start_8102e_2(tp);
2857ffb7 5356
fdf6fc06 5357 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5358}
5359
beb1fe18 5360static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5361{
beb1fe18 5362 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5363 static const struct ephy_info e_info_8105e_1[] = {
5364 { 0x07, 0, 0x4000 },
5365 { 0x19, 0, 0x0200 },
5366 { 0x19, 0, 0x0020 },
5367 { 0x1e, 0, 0x2000 },
5368 { 0x03, 0, 0x0001 },
5369 { 0x19, 0, 0x0100 },
5370 { 0x19, 0, 0x0004 },
5371 { 0x0a, 0, 0x0020 }
5372 };
5373
cecb5fd7 5374 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5375 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5376
cecb5fd7 5377 /* Disable Early Tally Counter */
5a5e4443
HW		 5378 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5379
5380 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5381 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5382
fdf6fc06 5383 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5384}
5385
beb1fe18 5386static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5387{
beb1fe18 5388 rtl_hw_start_8105e_1(tp);
fdf6fc06 5389 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5390}
5391
7e18dca1
HW		 5392static void rtl_hw_start_8402(struct rtl8169_private *tp)
5393{
5394 void __iomem *ioaddr = tp->mmio_addr;
5395 static const struct ephy_info e_info_8402[] = {
5396 { 0x19, 0xffff, 0xff64 },
5397 { 0x1e, 0, 0x4000 }
5398 };
5399
5400 rtl_csi_access_enable_2(tp);
5401
5402 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5403 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5404
5405 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5406 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5407
fdf6fc06 5408 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5409
5410 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5411
fdf6fc06
FR		 5412 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5413 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5414 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5415 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5416 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5417 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5418 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5419}
5420
5598bfe5
HW		 5421static void rtl_hw_start_8106(struct rtl8169_private *tp)
5422{
5423 void __iomem *ioaddr = tp->mmio_addr;
5424
5425 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5426 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5427
4521e1a9 5428 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 5429 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5430 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5431}
5432
07ce4064
FR		 5433static void rtl_hw_start_8101(struct net_device *dev)
5434{
cdf1a608
FR		 5435 struct rtl8169_private *tp = netdev_priv(dev);
5436 void __iomem *ioaddr = tp->mmio_addr;
5437 struct pci_dev *pdev = tp->pci_dev;
5438
da78dbff
FR		 5439 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5440 tp->event_slow &= ~RxFIFOOver;
811fd301 5441
cecb5fd7 5442 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5443 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 5444 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5445 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5446
d24e9aaf
HW		 5447 RTL_W8(Cfg9346, Cfg9346_Unlock);
5448
2857ffb7
FR		 5449 switch (tp->mac_version) {
5450 case RTL_GIGA_MAC_VER_07:
beb1fe18 5451 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5452 break;
5453
5454 case RTL_GIGA_MAC_VER_08:
beb1fe18 5455 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5456 break;
5457
5458 case RTL_GIGA_MAC_VER_09:
beb1fe18 5459 rtl_hw_start_8102e_2(tp);
2857ffb7 5460 break;
5a5e4443
HW		 5461
5462 case RTL_GIGA_MAC_VER_29:
beb1fe18 5463 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5464 break;
5465 case RTL_GIGA_MAC_VER_30:
beb1fe18 5466 rtl_hw_start_8105e_2(tp);
5a5e4443 5467 break;
7e18dca1
HW		 5468
5469 case RTL_GIGA_MAC_VER_37:
5470 rtl_hw_start_8402(tp);
5471 break;
5598bfe5
HW		 5472
5473 case RTL_GIGA_MAC_VER_39:
5474 rtl_hw_start_8106(tp);
5475 break;
cdf1a608
FR		 5476 }
5477
d24e9aaf 5478 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5479
f0298f81 5480 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5481
6f0333b8 5482 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5483
d24e9aaf 5484 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5485 RTL_W16(CPlusCmd, tp->cp_cmd);
5486
5487 RTL_W16(IntrMitigate, 0x0000);
5488
5489 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5490
5491 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5492 rtl_set_rx_tx_config_registers(tp);
5493
cdf1a608
FR		 5494 RTL_R8(IntrMask);
5495
cdf1a608
FR		 5496 rtl_set_rx_mode(dev);
5497
5498 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5499}
5500
5501static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5502{
d58d46b5
FR		 5503 struct rtl8169_private *tp = netdev_priv(dev);
5504
5505 if (new_mtu < ETH_ZLEN ||
5506 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5507 return -EINVAL;
5508
d58d46b5
FR		 5509 if (new_mtu > ETH_DATA_LEN)
5510 rtl_hw_jumbo_enable(tp);
5511 else
5512 rtl_hw_jumbo_disable(tp);
5513
1da177e4 5514 dev->mtu = new_mtu;
350fb32a
MM		 5515 netdev_update_features(dev);
5516
323bb685 5517 return 0;
1da177e4
LT		 5518}
5519
5520static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5521{
95e0918d 5522 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5523 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5524}
5525
6f0333b8
ED		 5526static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5527 void **data_buff, struct RxDesc *desc)
1da177e4 5528{
48addcc9 5529 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5530 DMA_FROM_DEVICE);
48addcc9 5531
6f0333b8
ED		 5532 kfree(*data_buff);
5533 *data_buff = NULL;
1da177e4
LT		 5534 rtl8169_make_unusable_by_asic(desc);
5535}
5536
5537static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5538{
5539 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5540
5541 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5542}
5543
5544static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5545 u32 rx_buf_sz)
5546{
5547 desc->addr = cpu_to_le64(mapping);
5548 wmb();
5549 rtl8169_mark_to_asic(desc, rx_buf_sz);
5550}
5551
6f0333b8
ED		 5552static inline void *rtl8169_align(void *data)
5553{
5554 return (void *)ALIGN((long)data, 16);
5555}
5556
0ecbe1ca
SG		 5557static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5558 struct RxDesc *desc)
1da177e4 5559{
6f0333b8 5560 void *data;
1da177e4 5561 dma_addr_t mapping;
48addcc9 5562 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5563 struct net_device *dev = tp->dev;
6f0333b8 5564 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5565
6f0333b8
ED		 5566 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5567 if (!data)
5568 return NULL;
e9f63f30 5569
6f0333b8
ED		 5570 if (rtl8169_align(data) != data) {
5571 kfree(data);
5572 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5573 if (!data)
5574 return NULL;
5575 }
3eafe507 5576
48addcc9 5577 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5578 DMA_FROM_DEVICE);
d827d86b
SG		 5579 if (unlikely(dma_mapping_error(d, mapping))) {
5580 if (net_ratelimit())
5581 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5582 goto err_out;
d827d86b 5583 }
1da177e4
LT		 5584
5585 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5586 return data;
3eafe507
SG		 5587
5588err_out:
5589 kfree(data);
5590 return NULL;
1da177e4
LT		 5591}
5592
5593static void rtl8169_rx_clear(struct rtl8169_private *tp)
5594{
07d3f51f 5595 unsigned int i;
1da177e4
LT		 5596
5597 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5598 if (tp->Rx_databuff[i]) {
5599 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5600 tp->RxDescArray + i);
5601 }
5602 }
5603}
5604
0ecbe1ca 5605static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5606{
0ecbe1ca
SG		 5607 desc->opts1 |= cpu_to_le32(RingEnd);
5608}
5b0384f4 5609
0ecbe1ca
SG		 5610static int rtl8169_rx_fill(struct rtl8169_private *tp)
5611{
5612 unsigned int i;
1da177e4 5613
0ecbe1ca
SG		 5614 for (i = 0; i < NUM_RX_DESC; i++) {
5615 void *data;
4ae47c2d 5616
6f0333b8 5617 if (tp->Rx_databuff[i])
1da177e4 5618 continue;
bcf0bf90 5619
0ecbe1ca 5620 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5621 if (!data) {
5622 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5623 goto err_out;
6f0333b8
ED		 5624 }
5625 tp->Rx_databuff[i] = data;
1da177e4 5626 }
1da177e4 5627
0ecbe1ca
SG		 5628 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5629 return 0;
5630
5631err_out:
5632 rtl8169_rx_clear(tp);
5633 return -ENOMEM;
1da177e4
LT		 5634}
5635
1da177e4
LT		 5636static int rtl8169_init_ring(struct net_device *dev)
5637{
5638 struct rtl8169_private *tp = netdev_priv(dev);
5639
5640 rtl8169_init_ring_indexes(tp);
5641
5642 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5643 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5644
0ecbe1ca 5645 return rtl8169_rx_fill(tp);
1da177e4
LT		 5646}
5647
48addcc9 5648static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5649 struct TxDesc *desc)
5650{
5651 unsigned int len = tx_skb->len;
5652
48addcc9
SG		 5653 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5654
1da177e4
LT		 5655 desc->opts1 = 0x00;
5656 desc->opts2 = 0x00;
5657 desc->addr = 0x00;
5658 tx_skb->len = 0;
5659}
5660
3eafe507
SG		 5661static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5662 unsigned int n)
1da177e4
LT		 5663{
5664 unsigned int i;
5665
3eafe507
SG		 5666 for (i = 0; i < n; i++) {
5667 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5668 struct ring_info *tx_skb = tp->tx_skb + entry;
5669 unsigned int len = tx_skb->len;
5670
5671 if (len) {
5672 struct sk_buff *skb = tx_skb->skb;
5673
48addcc9 5674 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5675 tp->TxDescArray + entry);
5676 if (skb) {
cac4b22f 5677 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5678 dev_kfree_skb(skb);
5679 tx_skb->skb = NULL;
5680 }
1da177e4
LT		 5681 }
5682 }
3eafe507
SG		 5683}
5684
5685static void rtl8169_tx_clear(struct rtl8169_private *tp)
5686{
5687 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5688 tp->cur_tx = tp->dirty_tx = 0;
5689}
5690
4422bcd4 5691static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5692{
c4028958 5693 struct net_device *dev = tp->dev;
56de414c 5694 int i;
1da177e4 5695
da78dbff
FR		 5696 napi_disable(&tp->napi);
5697 netif_stop_queue(dev);
5698 synchronize_sched();
1da177e4 5699
c7c2c39b 5700 rtl8169_hw_reset(tp);
5701
56de414c
FR		 5702 for (i = 0; i < NUM_RX_DESC; i++)
5703 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5704
1da177e4 5705 rtl8169_tx_clear(tp);
c7c2c39b 5706 rtl8169_init_ring_indexes(tp);
1da177e4 5707
da78dbff 5708 napi_enable(&tp->napi);
56de414c
FR		 5709 rtl_hw_start(dev);
5710 netif_wake_queue(dev);
5711 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5712}
5713
5714static void rtl8169_tx_timeout(struct net_device *dev)
5715{
da78dbff
FR		 5716 struct rtl8169_private *tp = netdev_priv(dev);
5717
5718 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5719}
5720
5721static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5722 u32 *opts)
1da177e4
LT		 5723{
5724 struct skb_shared_info *info = skb_shinfo(skb);
5725 unsigned int cur_frag, entry;
a6343afb 5726 struct TxDesc * uninitialized_var(txd);
48addcc9 5727 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5728
5729 entry = tp->cur_tx;
5730 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5731 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5732 dma_addr_t mapping;
5733 u32 status, len;
5734 void *addr;
5735
5736 entry = (entry + 1) % NUM_TX_DESC;
5737
5738 txd = tp->TxDescArray + entry;
9e903e08 5739 len = skb_frag_size(frag);
929f6189 5740 addr = skb_frag_address(frag);
48addcc9 5741 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5742 if (unlikely(dma_mapping_error(d, mapping))) {
5743 if (net_ratelimit())
5744 netif_err(tp, drv, tp->dev,
5745 "Failed to map TX fragments DMA!\n");
3eafe507 5746 goto err_out;
d827d86b 5747 }
1da177e4 5748
cecb5fd7 5749 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5750 status = opts[0] | len |
5751 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5752
5753 txd->opts1 = cpu_to_le32(status);
2b7b4318 5754 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5755 txd->addr = cpu_to_le64(mapping);
5756
5757 tp->tx_skb[entry].len = len;
5758 }
5759
5760 if (cur_frag) {
5761 tp->tx_skb[entry].skb = skb;
5762 txd->opts1 |= cpu_to_le32(LastFrag);
5763 }
5764
5765 return cur_frag;
3eafe507
SG		 5766
5767err_out:
5768 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5769 return -EIO;
1da177e4
LT		 5770}
5771
2b7b4318
FR		 5772static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5773 struct sk_buff *skb, u32 *opts)
1da177e4 5774{
2b7b4318 5775 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5776 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5777 int offset = info->opts_offset;
350fb32a 5778
2b7b4318
FR		 5779 if (mss) {
5780 opts[0] |= TD_LSO;
5781 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5782 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5783 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5784
5785 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5786 opts[offset] |= info->checksum.tcp;
1da177e4 5787 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5788 opts[offset] |= info->checksum.udp;
5789 else
5790 WARN_ON_ONCE(1);
1da177e4 5791 }
1da177e4
LT		 5792}
5793
61357325
SH		 5794static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5795 struct net_device *dev)
1da177e4
LT		 5796{
5797 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5798 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5799 struct TxDesc *txd = tp->TxDescArray + entry;
5800 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5801 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5802 dma_addr_t mapping;
5803 u32 status, len;
2b7b4318 5804 u32 opts[2];
3eafe507 5805 int frags;
5b0384f4 5806
477206a0 5807 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5808 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5809 goto err_stop_0;
1da177e4
LT		 5810 }
5811
5812 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5813 goto err_stop_0;
5814
5815 len = skb_headlen(skb);
48addcc9 5816 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5817 if (unlikely(dma_mapping_error(d, mapping))) {
5818 if (net_ratelimit())
5819 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5820 goto err_dma_0;
d827d86b 5821 }
3eafe507
SG		 5822
5823 tp->tx_skb[entry].len = len;
5824 txd->addr = cpu_to_le64(mapping);
1da177e4 5825
810f4893 5826 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
2b7b4318 5827 opts[0] = DescOwn;
1da177e4 5828
2b7b4318
FR		 5829 rtl8169_tso_csum(tp, skb, opts);
5830
5831 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5832 if (frags < 0)
5833 goto err_dma_1;
5834 else if (frags)
2b7b4318 5835 opts[0] |= FirstFrag;
3eafe507 5836 else {
2b7b4318 5837 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5838 tp->tx_skb[entry].skb = skb;
5839 }
5840
2b7b4318
FR		 5841 txd->opts2 = cpu_to_le32(opts[1]);
5842
5047fb5d
RC		 5843 skb_tx_timestamp(skb);
5844
1da177e4
LT		 5845 wmb();
5846
cecb5fd7 5847 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5848 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5849 txd->opts1 = cpu_to_le32(status);
5850
1da177e4
LT		 5851 tp->cur_tx += frags + 1;
5852
4c020a96 5853 wmb();
1da177e4 5854
cecb5fd7 5855 RTL_W8(TxPoll, NPQ);
1da177e4 5856
da78dbff
FR		 5857 mmiowb();
5858
477206a0 5859 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5860 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5861 * not miss a ring update when it notices a stopped queue.
5862 */
5863 smp_wmb();
1da177e4 5864 netif_stop_queue(dev);
ae1f23fb
FR		 5865 /* Sync with rtl_tx:
5866 * - publish queue status and cur_tx ring index (write barrier)
5867 * - refresh dirty_tx ring index (read barrier).
5868 * May the current thread have a pessimistic view of the ring
5869 * status and forget to wake up queue, a racing rtl_tx thread
5870 * can't.
5871 */
1e874e04 5872 smp_mb();
477206a0 5873 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5874 netif_wake_queue(dev);
5875 }
5876
61357325 5877 return NETDEV_TX_OK;
1da177e4 5878
3eafe507 5879err_dma_1:
48addcc9 5880 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5881err_dma_0:
5882 dev_kfree_skb(skb);
5883 dev->stats.tx_dropped++;
5884 return NETDEV_TX_OK;
5885
5886err_stop_0:
1da177e4 5887 netif_stop_queue(dev);
cebf8cc7 5888 dev->stats.tx_dropped++;
61357325 5889 return NETDEV_TX_BUSY;
1da177e4
LT		 5890}
5891
5892static void rtl8169_pcierr_interrupt(struct net_device *dev)
5893{
5894 struct rtl8169_private *tp = netdev_priv(dev);
5895 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5896 u16 pci_status, pci_cmd;
5897
5898 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5899 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5900
bf82c189
JP		 5901 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5902 pci_cmd, pci_status);
1da177e4
LT		 5903
5904 /*
5905 * The recovery sequence below admits a very elaborated explanation:
5906 * - it seems to work;
d03902b8
FR		 5907 * - I did not see what else could be done;
5908 * - it makes iop3xx happy.
1da177e4
LT		 5909 *
5910 * Feel free to adjust to your needs.
5911 */
a27993f3 5912 if (pdev->broken_parity_status)
d03902b8
FR		 5913 pci_cmd &= ~PCI_COMMAND_PARITY;
5914 else
5915 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5916
5917 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5918
5919 pci_write_config_word(pdev, PCI_STATUS,
5920 pci_status & (PCI_STATUS_DETECTED_PARITY |
5921 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5922 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5923
5924 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 5925 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 5926 void __iomem *ioaddr = tp->mmio_addr;
5927
bf82c189 5928 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5929 tp->cp_cmd &= ~PCIDAC;
5930 RTL_W16(CPlusCmd, tp->cp_cmd);
5931 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5932 }
5933
e6de30d6 5934 rtl8169_hw_reset(tp);
d03902b8 5935
98ddf986 5936 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5937}
5938
da78dbff 5939static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5940{
5941 unsigned int dirty_tx, tx_left;
5942
1da177e4
LT		 5943 dirty_tx = tp->dirty_tx;
5944 smp_rmb();
5945 tx_left = tp->cur_tx - dirty_tx;
5946
5947 while (tx_left > 0) {
5948 unsigned int entry = dirty_tx % NUM_TX_DESC;
5949 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5950 u32 status;
5951
5952 rmb();
5953 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5954 if (status & DescOwn)
5955 break;
5956
48addcc9
SG		 5957 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5958 tp->TxDescArray + entry);
1da177e4 5959 if (status & LastFrag) {
17bcb684
FR		 5960 u64_stats_update_begin(&tp->tx_stats.syncp);
5961 tp->tx_stats.packets++;
5962 tp->tx_stats.bytes += tx_skb->skb->len;
5963 u64_stats_update_end(&tp->tx_stats.syncp);
5964 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5965 tx_skb->skb = NULL;
5966 }
5967 dirty_tx++;
5968 tx_left--;
5969 }
5970
5971 if (tp->dirty_tx != dirty_tx) {
5972 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5973 /* Sync with rtl8169_start_xmit:
5974 * - publish dirty_tx ring index (write barrier)
5975 * - refresh cur_tx ring index and queue status (read barrier)
5976 * May the current thread miss the stopped queue condition,
5977 * a racing xmit thread can only have a right view of the
5978 * ring status.
5979 */
1e874e04 5980 smp_mb();
1da177e4 5981 if (netif_queue_stopped(dev) &&
477206a0 5982 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5983 netif_wake_queue(dev);
5984 }
d78ae2dc
FR		 5985 /*
5986 * 8168 hack: TxPoll requests are lost when the Tx packets are
5987 * too close. Let's kick an extra TxPoll request when a burst
5988 * of start_xmit activity is detected (if it is not detected,
5989 * it is slow enough). -- FR
5990 */
da78dbff
FR		 5991 if (tp->cur_tx != dirty_tx) {
5992 void __iomem *ioaddr = tp->mmio_addr;
5993
d78ae2dc 5994 RTL_W8(TxPoll, NPQ);
da78dbff 5995 }
1da177e4
LT		 5996 }
5997}
5998
126fa4b9
FR		 5999static inline int rtl8169_fragmented_frame(u32 status)
6000{
6001 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6002}
6003
adea1ac7 6004static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6005{
1da177e4
LT		 6006 u32 status = opts1 & RxProtoMask;
6007
6008 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6009 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6010 skb->ip_summed = CHECKSUM_UNNECESSARY;
6011 else
bc8acf2c 6012 skb_checksum_none_assert(skb);
1da177e4
LT		 6013}
6014
6f0333b8
ED		 6015static struct sk_buff *rtl8169_try_rx_copy(void *data,
6016 struct rtl8169_private *tp,
6017 int pkt_size,
6018 dma_addr_t addr)
1da177e4 6019{
b449655f 6020 struct sk_buff *skb;
48addcc9 6021 struct device *d = &tp->pci_dev->dev;
b449655f 6022
6f0333b8 6023 data = rtl8169_align(data);
48addcc9 6024 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6025 prefetch(data);
6026 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6027 if (skb)
6028 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6029 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6030
6f0333b8 6031 return skb;
1da177e4
LT		 6032}
6033
da78dbff 6034static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6035{
6036 unsigned int cur_rx, rx_left;
6f0333b8 6037 unsigned int count;
1da177e4 6038
1da177e4 6039 cur_rx = tp->cur_rx;
1da177e4 6040
9fba0812 6041 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6042 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6043 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6044 u32 status;
6045
6046 rmb();
e03f33af 6047 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6048
6049 if (status & DescOwn)
6050 break;
4dcb7d33 6051 if (unlikely(status & RxRES)) {
bf82c189
JP		 6052 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6053 status);
cebf8cc7 6054 dev->stats.rx_errors++;
1da177e4 6055 if (status & (RxRWT | RxRUNT))
cebf8cc7 6056 dev->stats.rx_length_errors++;
1da177e4 6057 if (status & RxCRC)
cebf8cc7 6058 dev->stats.rx_crc_errors++;
9dccf611 6059 if (status & RxFOVF) {
da78dbff 6060 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6061 dev->stats.rx_fifo_errors++;
9dccf611 6062 }
6bbe021d
BG		 6063 if ((status & (RxRUNT | RxCRC)) &&
6064 !(status & (RxRWT | RxFOVF)) &&
6065 (dev->features & NETIF_F_RXALL))
6066 goto process_pkt;
1da177e4 6067 } else {
6f0333b8 6068 struct sk_buff *skb;
6bbe021d
BG		 6069 dma_addr_t addr;
6070 int pkt_size;
6071
6072process_pkt:
6073 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6074 if (likely(!(dev->features & NETIF_F_RXFCS)))
6075 pkt_size = (status & 0x00003fff) - 4;
6076 else
6077 pkt_size = status & 0x00003fff;
1da177e4 6078
126fa4b9
FR		 6079 /*
6080 * The driver does not support incoming fragmented
6081 * frames. They are seen as a symptom of over-mtu
6082 * sized frames.
6083 */
6084 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6085 dev->stats.rx_dropped++;
6086 dev->stats.rx_length_errors++;
ce11ff5e 6087 goto release_descriptor;
126fa4b9
FR		 6088 }
6089
6f0333b8
ED		 6090 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6091 tp, pkt_size, addr);
6f0333b8
ED		 6092 if (!skb) {
6093 dev->stats.rx_dropped++;
ce11ff5e 6094 goto release_descriptor;
1da177e4
LT		 6095 }
6096
adea1ac7 6097 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6098 skb_put(skb, pkt_size);
6099 skb->protocol = eth_type_trans(skb, dev);
6100
7a8fc77b
FR		 6101 rtl8169_rx_vlan_tag(desc, skb);
6102
56de414c 6103 napi_gro_receive(&tp->napi, skb);
1da177e4 6104
8027aa24
JW		 6105 u64_stats_update_begin(&tp->rx_stats.syncp);
6106 tp->rx_stats.packets++;
6107 tp->rx_stats.bytes += pkt_size;
6108 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6109 }
ce11ff5e 6110release_descriptor:
6111 desc->opts2 = 0;
6112 wmb();
6113 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 6114 }
6115
6116 count = cur_rx - tp->cur_rx;
6117 tp->cur_rx = cur_rx;
6118
1da177e4
LT		 6119 return count;
6120}
6121
07d3f51f 6122static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6123{
07d3f51f 6124 struct net_device *dev = dev_instance;
1da177e4 6125 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6126 int handled = 0;
9085cdfa 6127 u16 status;
1da177e4 6128
9085cdfa 6129 status = rtl_get_events(tp);
da78dbff
FR		 6130 if (status && status != 0xffff) {
6131 status &= RTL_EVENT_NAPI | tp->event_slow;
6132 if (status) {
6133 handled = 1;
1da177e4 6134
da78dbff
FR		 6135 rtl_irq_disable(tp);
6136 napi_schedule(&tp->napi);
f11a377b 6137 }
da78dbff
FR		 6138 }
6139 return IRQ_RETVAL(handled);
6140}
1da177e4 6141
da78dbff
FR		 6142/*
6143 * Workqueue context.
6144 */
6145static void rtl_slow_event_work(struct rtl8169_private *tp)
6146{
6147 struct net_device *dev = tp->dev;
6148 u16 status;
6149
6150 status = rtl_get_events(tp) & tp->event_slow;
6151 rtl_ack_events(tp, status);
1da177e4 6152
da78dbff
FR		 6153 if (unlikely(status & RxFIFOOver)) {
6154 switch (tp->mac_version) {
6155 /* Work around for rx fifo overflow */
6156 case RTL_GIGA_MAC_VER_11:
6157 netif_stop_queue(dev);
934714d0
FR		 6158 /* XXX - Hack alert. See rtl_task(). */
6159 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6160 default:
f11a377b
DD		 6161 break;
6162 }
da78dbff 6163 }
1da177e4 6164
da78dbff
FR		 6165 if (unlikely(status & SYSErr))
6166 rtl8169_pcierr_interrupt(dev);
0e485150 6167
da78dbff
FR		 6168 if (status & LinkChg)
6169 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6170
7dbb4918 6171 rtl_irq_enable_all(tp);
1da177e4
LT		 6172}
6173
4422bcd4
FR		 6174static void rtl_task(struct work_struct *work)
6175{
da78dbff
FR		 6176 static const struct {
6177 int bitnr;
6178 void (*action)(struct rtl8169_private *);
6179 } rtl_work[] = {
934714d0 6180 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6181 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6182 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6183 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6184 };
4422bcd4
FR		 6185 struct rtl8169_private *tp =
6186 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6187 struct net_device *dev = tp->dev;
6188 int i;
6189
6190 rtl_lock_work(tp);
6191
6c4a70c5
FR		 6192 if (!netif_running(dev) ||
6193 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6194 goto out_unlock;
6195
6196 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6197 bool pending;
6198
da78dbff 6199 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6200 if (pending)
6201 rtl_work[i].action(tp);
6202 }
4422bcd4 6203
da78dbff
FR		 6204out_unlock:
6205 rtl_unlock_work(tp);
4422bcd4
FR		 6206}
6207
bea3348e 6208static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6209{
bea3348e
SH		 6210 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6211 struct net_device *dev = tp->dev;
da78dbff
FR		 6212 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6213 int work_done= 0;
6214 u16 status;
6215
6216 status = rtl_get_events(tp);
6217 rtl_ack_events(tp, status & ~tp->event_slow);
6218
6219 if (status & RTL_EVENT_NAPI_RX)
6220 work_done = rtl_rx(dev, tp, (u32) budget);
6221
6222 if (status & RTL_EVENT_NAPI_TX)
6223 rtl_tx(dev, tp);
1da177e4 6224
da78dbff
FR		 6225 if (status & tp->event_slow) {
6226 enable_mask &= ~tp->event_slow;
6227
6228 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6229 }
1da177e4 6230
bea3348e 6231 if (work_done < budget) {
288379f0 6232 napi_complete(napi);
f11a377b 6233
da78dbff
FR		 6234 rtl_irq_enable(tp, enable_mask);
6235 mmiowb();
1da177e4
LT		 6236 }
6237
bea3348e 6238 return work_done;
1da177e4 6239}
1da177e4 6240
523a6094
FR		 6241static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6242{
6243 struct rtl8169_private *tp = netdev_priv(dev);
6244
6245 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6246 return;
6247
6248 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6249 RTL_W32(RxMissed, 0);
6250}
6251
1da177e4
LT		 6252static void rtl8169_down(struct net_device *dev)
6253{
6254 struct rtl8169_private *tp = netdev_priv(dev);
6255 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6256
4876cc1e 6257 del_timer_sync(&tp->timer);
1da177e4 6258
93dd79e8 6259 napi_disable(&tp->napi);
da78dbff 6260 netif_stop_queue(dev);
1da177e4 6261
92fc43b4 6262 rtl8169_hw_reset(tp);
323bb685
SG		 6263 /*
6264 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6265 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6266 * and napi is disabled (rtl8169_poll).
323bb685 6267 */
523a6094 6268 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6269
1da177e4 6270 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6271 synchronize_sched();
1da177e4 6272
1da177e4
LT		 6273 rtl8169_tx_clear(tp);
6274
6275 rtl8169_rx_clear(tp);
065c27c1 6276
6277 rtl_pll_power_down(tp);
1da177e4
LT		 6278}
6279
6280static int rtl8169_close(struct net_device *dev)
6281{
6282 struct rtl8169_private *tp = netdev_priv(dev);
6283 struct pci_dev *pdev = tp->pci_dev;
6284
e1759441
RW		 6285 pm_runtime_get_sync(&pdev->dev);
6286
cecb5fd7 6287 /* Update counters before going down */
355423d0
IV		 6288 rtl8169_update_counters(dev);
6289
da78dbff 6290 rtl_lock_work(tp);
6c4a70c5 6291 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6292
1da177e4 6293 rtl8169_down(dev);
da78dbff 6294 rtl_unlock_work(tp);
1da177e4 6295
92a7c4e7 6296 free_irq(pdev->irq, dev);
1da177e4 6297
82553bb6
SG		 6298 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6299 tp->RxPhyAddr);
6300 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6301 tp->TxPhyAddr);
1da177e4
LT		 6302 tp->TxDescArray = NULL;
6303 tp->RxDescArray = NULL;
6304
e1759441
RW		 6305 pm_runtime_put_sync(&pdev->dev);
6306
1da177e4
LT		 6307 return 0;
6308}
6309
dc1c00ce
FR		 6310#ifdef CONFIG_NET_POLL_CONTROLLER
6311static void rtl8169_netpoll(struct net_device *dev)
6312{
6313 struct rtl8169_private *tp = netdev_priv(dev);
6314
6315 rtl8169_interrupt(tp->pci_dev->irq, dev);
6316}
6317#endif
6318
df43ac78
FR		 6319static int rtl_open(struct net_device *dev)
6320{
6321 struct rtl8169_private *tp = netdev_priv(dev);
6322 void __iomem *ioaddr = tp->mmio_addr;
6323 struct pci_dev *pdev = tp->pci_dev;
6324 int retval = -ENOMEM;
6325
6326 pm_runtime_get_sync(&pdev->dev);
6327
6328 /*
e75d6606 6329 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6330 * dma_alloc_coherent provides more.
6331 */
6332 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6333 &tp->TxPhyAddr, GFP_KERNEL);
6334 if (!tp->TxDescArray)
6335 goto err_pm_runtime_put;
6336
6337 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6338 &tp->RxPhyAddr, GFP_KERNEL);
6339 if (!tp->RxDescArray)
6340 goto err_free_tx_0;
6341
6342 retval = rtl8169_init_ring(dev);
6343 if (retval < 0)
6344 goto err_free_rx_1;
6345
6346 INIT_WORK(&tp->wk.work, rtl_task);
6347
6348 smp_mb();
6349
6350 rtl_request_firmware(tp);
6351
92a7c4e7 6352 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6353 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6354 dev->name, dev);
6355 if (retval < 0)
6356 goto err_release_fw_2;
6357
6358 rtl_lock_work(tp);
6359
6360 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6361
6362 napi_enable(&tp->napi);
6363
6364 rtl8169_init_phy(dev, tp);
6365
6366 __rtl8169_set_features(dev, dev->features);
6367
6368 rtl_pll_power_up(tp);
6369
6370 rtl_hw_start(dev);
6371
6372 netif_start_queue(dev);
6373
6374 rtl_unlock_work(tp);
6375
6376 tp->saved_wolopts = 0;
6377 pm_runtime_put_noidle(&pdev->dev);
6378
6379 rtl8169_check_link_status(dev, tp, ioaddr);
6380out:
6381 return retval;
6382
6383err_release_fw_2:
6384 rtl_release_firmware(tp);
6385 rtl8169_rx_clear(tp);
6386err_free_rx_1:
6387 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6388 tp->RxPhyAddr);
6389 tp->RxDescArray = NULL;
6390err_free_tx_0:
6391 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6392 tp->TxPhyAddr);
6393 tp->TxDescArray = NULL;
6394err_pm_runtime_put:
6395 pm_runtime_put_noidle(&pdev->dev);
6396 goto out;
6397}
6398
8027aa24
JW		 6399static struct rtnl_link_stats64 *
6400rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6401{
6402 struct rtl8169_private *tp = netdev_priv(dev);
6403 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6404 unsigned int start;
1da177e4 6405
da78dbff 6406 if (netif_running(dev))
523a6094 6407 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6408
8027aa24
JW		 6409 do {
6410 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6411 stats->rx_packets = tp->rx_stats.packets;
6412 stats->rx_bytes = tp->rx_stats.bytes;
6413 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6414
6415
6416 do {
6417 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6418 stats->tx_packets = tp->tx_stats.packets;
6419 stats->tx_bytes = tp->tx_stats.bytes;
6420 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6421
6422 stats->rx_dropped = dev->stats.rx_dropped;
6423 stats->tx_dropped = dev->stats.tx_dropped;
6424 stats->rx_length_errors = dev->stats.rx_length_errors;
6425 stats->rx_errors = dev->stats.rx_errors;
6426 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6427 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6428 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6429
6430 return stats;
1da177e4
LT		 6431}
6432
861ab440 6433static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6434{
065c27c1 6435 struct rtl8169_private *tp = netdev_priv(dev);
6436
5d06a99f 6437 if (!netif_running(dev))
861ab440 6438 return;
5d06a99f
FR		 6439
6440 netif_device_detach(dev);
6441 netif_stop_queue(dev);
da78dbff
FR		 6442
6443 rtl_lock_work(tp);
6444 napi_disable(&tp->napi);
6c4a70c5 6445 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6446 rtl_unlock_work(tp);
6447
6448 rtl_pll_power_down(tp);
861ab440
RW		 6449}
6450
6451#ifdef CONFIG_PM
6452
6453static int rtl8169_suspend(struct device *device)
6454{
6455 struct pci_dev *pdev = to_pci_dev(device);
6456 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6457
861ab440 6458 rtl8169_net_suspend(dev);
1371fa6d 6459
5d06a99f
FR		 6460 return 0;
6461}
6462
e1759441
RW		 6463static void __rtl8169_resume(struct net_device *dev)
6464{
065c27c1 6465 struct rtl8169_private *tp = netdev_priv(dev);
6466
e1759441 6467 netif_device_attach(dev);
065c27c1 6468
6469 rtl_pll_power_up(tp);
6470
cff4c162
AS		 6471 rtl_lock_work(tp);
6472 napi_enable(&tp->napi);
6c4a70c5 6473 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6474 rtl_unlock_work(tp);
da78dbff 6475
98ddf986 6476 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6477}
6478
861ab440 6479static int rtl8169_resume(struct device *device)
5d06a99f 6480{
861ab440 6481 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6482 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6483 struct rtl8169_private *tp = netdev_priv(dev);
6484
6485 rtl8169_init_phy(dev, tp);
5d06a99f 6486
e1759441
RW		 6487 if (netif_running(dev))
6488 __rtl8169_resume(dev);
5d06a99f 6489
e1759441
RW		 6490 return 0;
6491}
6492
6493static int rtl8169_runtime_suspend(struct device *device)
6494{
6495 struct pci_dev *pdev = to_pci_dev(device);
6496 struct net_device *dev = pci_get_drvdata(pdev);
6497 struct rtl8169_private *tp = netdev_priv(dev);
6498
6499 if (!tp->TxDescArray)
6500 return 0;
6501
da78dbff 6502 rtl_lock_work(tp);
e1759441
RW		 6503 tp->saved_wolopts = __rtl8169_get_wol(tp);
6504 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6505 rtl_unlock_work(tp);
e1759441
RW		 6506
6507 rtl8169_net_suspend(dev);
6508
6509 return 0;
6510}
6511
6512static int rtl8169_runtime_resume(struct device *device)
6513{
6514 struct pci_dev *pdev = to_pci_dev(device);
6515 struct net_device *dev = pci_get_drvdata(pdev);
6516 struct rtl8169_private *tp = netdev_priv(dev);
6517
6518 if (!tp->TxDescArray)
6519 return 0;
6520
da78dbff 6521 rtl_lock_work(tp);
e1759441
RW		 6522 __rtl8169_set_wol(tp, tp->saved_wolopts);
6523 tp->saved_wolopts = 0;
da78dbff 6524 rtl_unlock_work(tp);
e1759441 6525
fccec10b
SG		 6526 rtl8169_init_phy(dev, tp);
6527
e1759441 6528 __rtl8169_resume(dev);
5d06a99f 6529
5d06a99f
FR		 6530 return 0;
6531}
6532
e1759441
RW		 6533static int rtl8169_runtime_idle(struct device *device)
6534{
6535 struct pci_dev *pdev = to_pci_dev(device);
6536 struct net_device *dev = pci_get_drvdata(pdev);
6537 struct rtl8169_private *tp = netdev_priv(dev);
6538
e4fbce74 6539 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6540}
6541
47145210 6542static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6543 .suspend = rtl8169_suspend,
6544 .resume = rtl8169_resume,
6545 .freeze = rtl8169_suspend,
6546 .thaw = rtl8169_resume,
6547 .poweroff = rtl8169_suspend,
6548 .restore = rtl8169_resume,
6549 .runtime_suspend = rtl8169_runtime_suspend,
6550 .runtime_resume = rtl8169_runtime_resume,
6551 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6552};
6553
6554#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6555
6556#else /* !CONFIG_PM */
6557
6558#define RTL8169_PM_OPS NULL
6559
6560#endif /* !CONFIG_PM */
6561
649b3b8c 6562static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6563{
6564 void __iomem *ioaddr = tp->mmio_addr;
6565
6566 /* WoL fails with 8168b when the receiver is disabled. */
6567 switch (tp->mac_version) {
6568 case RTL_GIGA_MAC_VER_11:
6569 case RTL_GIGA_MAC_VER_12:
6570 case RTL_GIGA_MAC_VER_17:
6571 pci_clear_master(tp->pci_dev);
6572
6573 RTL_W8(ChipCmd, CmdRxEnb);
6574 /* PCI commit */
6575 RTL_R8(ChipCmd);
6576 break;
6577 default:
6578 break;
6579 }
6580}
6581
1765f95d
FR		 6582static void rtl_shutdown(struct pci_dev *pdev)
6583{
861ab440 6584 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6585 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6586 struct device *d = &pdev->dev;
6587
6588 pm_runtime_get_sync(d);
861ab440
RW		 6589
6590 rtl8169_net_suspend(dev);
1765f95d 6591
cecb5fd7 6592 /* Restore original MAC address */
cc098dc7
IV		 6593 rtl_rar_set(tp, dev->perm_addr);
6594
92fc43b4 6595 rtl8169_hw_reset(tp);
4bb3f522 6596
861ab440 6597 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6598 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6599 rtl_wol_suspend_quirk(tp);
6600 rtl_wol_shutdown_quirk(tp);
ca52efd5 6601 }
6602
861ab440
RW		 6603 pci_wake_from_d3(pdev, true);
6604 pci_set_power_state(pdev, PCI_D3hot);
6605 }
2a15cd2f 6606
6607 pm_runtime_put_noidle(d);
861ab440 6608}
5d06a99f 6609
baf63293 6610static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6611{
6612 struct net_device *dev = pci_get_drvdata(pdev);
6613 struct rtl8169_private *tp = netdev_priv(dev);
6614
6615 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6616 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6617 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6618 rtl8168_driver_stop(tp);
6619 }
6620
6621 cancel_work_sync(&tp->wk.work);
6622
ad1be8d3
DN		 6623 netif_napi_del(&tp->napi);
6624
e27566ed
FR		 6625 unregister_netdev(dev);
6626
6627 rtl_release_firmware(tp);
6628
6629 if (pci_dev_run_wake(pdev))
6630 pm_runtime_get_noresume(&pdev->dev);
6631
6632 /* restore original MAC address */
6633 rtl_rar_set(tp, dev->perm_addr);
6634
6635 rtl_disable_msi(pdev, tp);
6636 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6637 pci_set_drvdata(pdev, NULL);
6638}
6639
fa9c385e 6640static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6641 .ndo_open = rtl_open,
fa9c385e
FR		 6642 .ndo_stop = rtl8169_close,
6643 .ndo_get_stats64 = rtl8169_get_stats64,
6644 .ndo_start_xmit = rtl8169_start_xmit,
6645 .ndo_tx_timeout = rtl8169_tx_timeout,
6646 .ndo_validate_addr = eth_validate_addr,
6647 .ndo_change_mtu = rtl8169_change_mtu,
6648 .ndo_fix_features = rtl8169_fix_features,
6649 .ndo_set_features = rtl8169_set_features,
6650 .ndo_set_mac_address = rtl_set_mac_address,
6651 .ndo_do_ioctl = rtl8169_ioctl,
6652 .ndo_set_rx_mode = rtl_set_rx_mode,
6653#ifdef CONFIG_NET_POLL_CONTROLLER
6654 .ndo_poll_controller = rtl8169_netpoll,
6655#endif
6656
6657};
6658
31fa8b18
FR		 6659static const struct rtl_cfg_info {
6660 void (*hw_start)(struct net_device *);
6661 unsigned int region;
6662 unsigned int align;
6663 u16 event_slow;
6664 unsigned features;
6665 u8 default_ver;
6666} rtl_cfg_infos [] = {
6667 [RTL_CFG_0] = {
6668 .hw_start = rtl_hw_start_8169,
6669 .region = 1,
6670 .align = 0,
6671 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6672 .features = RTL_FEATURE_GMII,
6673 .default_ver = RTL_GIGA_MAC_VER_01,
6674 },
6675 [RTL_CFG_1] = {
6676 .hw_start = rtl_hw_start_8168,
6677 .region = 2,
6678 .align = 8,
6679 .event_slow = SYSErr | LinkChg | RxOverflow,
6680 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6681 .default_ver = RTL_GIGA_MAC_VER_11,
6682 },
6683 [RTL_CFG_2] = {
6684 .hw_start = rtl_hw_start_8101,
6685 .region = 2,
6686 .align = 8,
6687 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6688 PCSTimeout,
6689 .features = RTL_FEATURE_MSI,
6690 .default_ver = RTL_GIGA_MAC_VER_13,
6691 }
6692};
6693
6694/* Cfg9346_Unlock assumed. */
6695static unsigned rtl_try_msi(struct rtl8169_private *tp,
6696 const struct rtl_cfg_info *cfg)
6697{
6698 void __iomem *ioaddr = tp->mmio_addr;
6699 unsigned msi = 0;
6700 u8 cfg2;
6701
6702 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6703 if (cfg->features & RTL_FEATURE_MSI) {
6704 if (pci_enable_msi(tp->pci_dev)) {
6705 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6706 } else {
6707 cfg2 |= MSIEnable;
6708 msi = RTL_FEATURE_MSI;
6709 }
6710 }
6711 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6712 RTL_W8(Config2, cfg2);
6713 return msi;
6714}
6715
c558386b
HW		 6716DECLARE_RTL_COND(rtl_link_list_ready_cond)
6717{
6718 void __iomem *ioaddr = tp->mmio_addr;
6719
6720 return RTL_R8(MCU) & LINK_LIST_RDY;
6721}
6722
6723DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6724{
6725 void __iomem *ioaddr = tp->mmio_addr;
6726
6727 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6728}
6729
baf63293 6730static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 6731{
6732 void __iomem *ioaddr = tp->mmio_addr;
6733 u32 data;
6734
6735 tp->ocp_base = OCP_STD_PHY_BASE;
6736
6737 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6738
6739 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6740 return;
6741
6742 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6743 return;
6744
6745 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6746 msleep(1);
6747 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6748
5f8bcce9 6749 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6750 data &= ~(1 << 14);
6751 r8168_mac_ocp_write(tp, 0xe8de, data);
6752
6753 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6754 return;
6755
5f8bcce9 6756 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6757 data |= (1 << 15);
6758 r8168_mac_ocp_write(tp, 0xe8de, data);
6759
6760 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6761 return;
6762}
6763
baf63293 6764static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 6765{
6766 switch (tp->mac_version) {
6767 case RTL_GIGA_MAC_VER_40:
6768 case RTL_GIGA_MAC_VER_41:
6769 rtl_hw_init_8168g(tp);
6770 break;
6771
6772 default:
6773 break;
6774 }
6775}
6776
baf63293 6777static int
3b6cf25d
FR		 6778rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6779{
6780 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6781 const unsigned int region = cfg->region;
6782 struct rtl8169_private *tp;
6783 struct mii_if_info *mii;
6784 struct net_device *dev;
6785 void __iomem *ioaddr;
6786 int chipset, i;
6787 int rc;
6788
6789 if (netif_msg_drv(&debug)) {
6790 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6791 MODULENAME, RTL8169_VERSION);
6792 }
6793
6794 dev = alloc_etherdev(sizeof (*tp));
6795 if (!dev) {
6796 rc = -ENOMEM;
6797 goto out;
6798 }
6799
6800 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6801 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6802 tp = netdev_priv(dev);
6803 tp->dev = dev;
6804 tp->pci_dev = pdev;
6805 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6806
6807 mii = &tp->mii;
6808 mii->dev = dev;
6809 mii->mdio_read = rtl_mdio_read;
6810 mii->mdio_write = rtl_mdio_write;
6811 mii->phy_id_mask = 0x1f;
6812 mii->reg_num_mask = 0x1f;
6813 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6814
6815 /* disable ASPM completely as that cause random device stop working
6816 * problems as well as full system hangs for some PCIe devices users */
6817 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6818 PCIE_LINK_STATE_CLKPM);
6819
6820 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6821 rc = pci_enable_device(pdev);
6822 if (rc < 0) {
6823 netif_err(tp, probe, dev, "enable failure\n");
6824 goto err_out_free_dev_1;
6825 }
6826
6827 if (pci_set_mwi(pdev) < 0)
6828 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6829
6830 /* make sure PCI base addr 1 is MMIO */
6831 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6832 netif_err(tp, probe, dev,
6833 "region #%d not an MMIO resource, aborting\n",
6834 region);
6835 rc = -ENODEV;
6836 goto err_out_mwi_2;
6837 }
6838
6839 /* check for weird/broken PCI region reporting */
6840 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6841 netif_err(tp, probe, dev,
6842 "Invalid PCI region size(s), aborting\n");
6843 rc = -ENODEV;
6844 goto err_out_mwi_2;
6845 }
6846
6847 rc = pci_request_regions(pdev, MODULENAME);
6848 if (rc < 0) {
6849 netif_err(tp, probe, dev, "could not request regions\n");
6850 goto err_out_mwi_2;
6851 }
6852
6853 tp->cp_cmd = RxChkSum;
6854
6855 if ((sizeof(dma_addr_t) > 4) &&
6856 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6857 tp->cp_cmd |= PCIDAC;
6858 dev->features |= NETIF_F_HIGHDMA;
6859 } else {
6860 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6861 if (rc < 0) {
6862 netif_err(tp, probe, dev, "DMA configuration failed\n");
6863 goto err_out_free_res_3;
6864 }
6865 }
6866
6867 /* ioremap MMIO region */
6868 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6869 if (!ioaddr) {
6870 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6871 rc = -EIO;
6872 goto err_out_free_res_3;
6873 }
6874 tp->mmio_addr = ioaddr;
6875
6876 if (!pci_is_pcie(pdev))
6877 netif_info(tp, probe, dev, "not PCI Express\n");
6878
6879 /* Identify chip attached to board */
6880 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6881
6882 rtl_init_rxcfg(tp);
6883
6884 rtl_irq_disable(tp);
6885
c558386b
HW		 6886 rtl_hw_initialize(tp);
6887
3b6cf25d
FR		 6888 rtl_hw_reset(tp);
6889
6890 rtl_ack_events(tp, 0xffff);
6891
6892 pci_set_master(pdev);
6893
6894 /*
6895 * Pretend we are using VLANs; This bypasses a nasty bug where
6896 * Interrupts stop flowing on high load on 8110SCd controllers.
6897 */
6898 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6899 tp->cp_cmd |= RxVlan;
6900
6901 rtl_init_mdio_ops(tp);
6902 rtl_init_pll_power_ops(tp);
6903 rtl_init_jumbo_ops(tp);
beb1fe18 6904 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6905
6906 rtl8169_print_mac_version(tp);
6907
6908 chipset = tp->mac_version;
6909 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6910
6911 RTL_W8(Cfg9346, Cfg9346_Unlock);
6912 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6913 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6914 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6915 tp->features |= RTL_FEATURE_WOL;
6916 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6917 tp->features |= RTL_FEATURE_WOL;
6918 tp->features |= rtl_try_msi(tp, cfg);
6919 RTL_W8(Cfg9346, Cfg9346_Lock);
6920
6921 if (rtl_tbi_enabled(tp)) {
6922 tp->set_speed = rtl8169_set_speed_tbi;
6923 tp->get_settings = rtl8169_gset_tbi;
6924 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6925 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6926 tp->link_ok = rtl8169_tbi_link_ok;
6927 tp->do_ioctl = rtl_tbi_ioctl;
6928 } else {
6929 tp->set_speed = rtl8169_set_speed_xmii;
6930 tp->get_settings = rtl8169_gset_xmii;
6931 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6932 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6933 tp->link_ok = rtl8169_xmii_link_ok;
6934 tp->do_ioctl = rtl_xmii_ioctl;
6935 }
6936
6937 mutex_init(&tp->wk.mutex);
6938
6939 /* Get MAC address */
6940 for (i = 0; i < ETH_ALEN; i++)
6941 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d
FR		 6942
6943 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6944 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6945
6946 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6947
6948 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6949 * properly for all devices */
6950 dev->features |= NETIF_F_RXCSUM |
6951 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6952
6953 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6954 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6955 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6956 NETIF_F_HIGHDMA;
6957
6958 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6959 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6960 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6961
6962 dev->hw_features |= NETIF_F_RXALL;
6963 dev->hw_features |= NETIF_F_RXFCS;
6964
6965 tp->hw_start = cfg->hw_start;
6966 tp->event_slow = cfg->event_slow;
6967
6968 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6969 ~(RxBOVF | RxFOVF) : ~0;
6970
6971 init_timer(&tp->timer);
6972 tp->timer.data = (unsigned long) dev;
6973 tp->timer.function = rtl8169_phy_timer;
6974
6975 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6976
6977 rc = register_netdev(dev);
6978 if (rc < 0)
6979 goto err_out_msi_4;
6980
6981 pci_set_drvdata(pdev, dev);
6982
92a7c4e7
FR		 6983 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6984 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6985 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6986 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6987 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6988 "tx checksumming: %s]\n",
6989 rtl_chip_infos[chipset].jumbo_max,
6990 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6991 }
6992
6993 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6994 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6995 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6996 rtl8168_driver_start(tp);
6997 }
6998
6999 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7000
7001 if (pci_dev_run_wake(pdev))
7002 pm_runtime_put_noidle(&pdev->dev);
7003
7004 netif_carrier_off(dev);
7005
7006out:
7007 return rc;
7008
7009err_out_msi_4:
ad1be8d3 7010 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7011 rtl_disable_msi(pdev, tp);
7012 iounmap(ioaddr);
7013err_out_free_res_3:
7014 pci_release_regions(pdev);
7015err_out_mwi_2:
7016 pci_clear_mwi(pdev);
7017 pci_disable_device(pdev);
7018err_out_free_dev_1:
7019 free_netdev(dev);
7020 goto out;
7021}
7022
1da177e4
LT		 7023static struct pci_driver rtl8169_pci_driver = {
7024 .name = MODULENAME,
7025 .id_table = rtl8169_pci_tbl,
3b6cf25d 7026 .probe = rtl_init_one,
baf63293 7027 .remove = rtl_remove_one,
1765f95d 7028 .shutdown = rtl_shutdown,
861ab440 7029 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7030};
7031
3eeb7da9 7032module_pci_driver(rtl8169_pci_driver);
Linux kernel - Deliverables
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