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r8169: Modify the method for setting firmware
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
c558386b 50#define FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw"
bca03d5f 51
1da177e4
LT		 52#ifdef RTL8169_DEBUG
53#define assert(expr) \
5b0384f4
FR		 54 if (!(expr)) { \
55 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 56 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 57 }
06fa7358
JP		 58#define dprintk(fmt, args...) \
59 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 60#else
61#define assert(expr) do {} while (0)
62#define dprintk(fmt, args...) do {} while (0)
63#endif /* RTL8169_DEBUG */
64
b57b7e5a 65#define R8169_MSG_DEFAULT \
f0e837d9 66 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 67
477206a0
JD		 68#define TX_SLOTS_AVAIL(tp) \
69 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72#define TX_FRAGS_READY_FOR(tp,nr_frags) \
73 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 74
1da177e4
LT		 75/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 77static const int multicast_filter_limit = 32;
1da177e4 78
9c14ceaf 79#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 80#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 81#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
82
83#define R8169_REGS_SIZE 256
84#define R8169_NAPI_WEIGHT 64
85#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 86#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 87#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
88#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
89
90#define RTL8169_TX_TIMEOUT (6*HZ)
91#define RTL8169_PHY_TIMEOUT (10*HZ)
92
93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
c2218925
HW		 136 RTL_GIGA_MAC_VER_35,
137 RTL_GIGA_MAC_VER_36,
7e18dca1 138 RTL_GIGA_MAC_VER_37,
b3d7b2f2 139 RTL_GIGA_MAC_VER_38,
5598bfe5 140 RTL_GIGA_MAC_VER_39,
c558386b
HW		 141 RTL_GIGA_MAC_VER_40,
142 RTL_GIGA_MAC_VER_41,
85bffe6c 143 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 144};
145
2b7b4318
FR		 146enum rtl_tx_desc_version {
147 RTL_TD_0 = 0,
148 RTL_TD_1 = 1,
149};
150
d58d46b5
FR		 151#define JUMBO_1K ETH_DATA_LEN
152#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
153#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
154#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
155#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
156
157#define _R(NAME,TD,FW,SZ,B) { \
158 .name = NAME, \
159 .txd_version = TD, \
160 .fw_name = FW, \
161 .jumbo_max = SZ, \
162 .jumbo_tx_csum = B \
163}
1da177e4 164
3c6bee1d 165static const struct {
1da177e4 166 const char *name;
2b7b4318 167 enum rtl_tx_desc_version txd_version;
953a12cc 168 const char *fw_name;
d58d46b5
FR		 169 u16 jumbo_max;
170 bool jumbo_tx_csum;
85bffe6c
FR		 171} rtl_chip_infos[] = {
172 /* PCI devices. */
173 [RTL_GIGA_MAC_VER_01] =
d58d46b5 174 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_02] =
d58d46b5 176 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_03] =
d58d46b5 178 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 179 [RTL_GIGA_MAC_VER_04] =
d58d46b5 180 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_05] =
d58d46b5 182 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_06] =
d58d46b5 184 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 185 /* PCI-E devices. */
186 [RTL_GIGA_MAC_VER_07] =
d58d46b5 187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_08] =
d58d46b5 189 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_09] =
d58d46b5 191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_10] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_11] =
d58d46b5 195 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 196 [RTL_GIGA_MAC_VER_12] =
d58d46b5 197 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 198 [RTL_GIGA_MAC_VER_13] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_14] =
d58d46b5 201 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 202 [RTL_GIGA_MAC_VER_15] =
d58d46b5 203 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 204 [RTL_GIGA_MAC_VER_16] =
d58d46b5 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_17] =
d58d46b5 207 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_18] =
d58d46b5 209 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_19] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_20] =
d58d46b5 213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_21] =
d58d46b5 215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_22] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_23] =
d58d46b5 219 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_24] =
d58d46b5 221 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
224 JUMBO_9K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 226 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
227 JUMBO_9K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_27] =
d58d46b5 229 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_28] =
d58d46b5 231 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
234 JUMBO_1K, true),
85bffe6c 235 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 236 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
237 JUMBO_1K, true),
85bffe6c 238 [RTL_GIGA_MAC_VER_31] =
d58d46b5 239 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 244 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
245 JUMBO_9K, false),
70090424 246 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 247 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
248 JUMBO_9K, false),
c2218925 249 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
251 JUMBO_9K, false),
c2218925 252 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 253 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
254 JUMBO_9K, false),
7e18dca1
HW		 255 [RTL_GIGA_MAC_VER_37] =
256 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
257 JUMBO_1K, true),
b3d7b2f2
HW		 258 [RTL_GIGA_MAC_VER_38] =
259 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
260 JUMBO_9K, false),
5598bfe5
HW		 261 [RTL_GIGA_MAC_VER_39] =
262 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
263 JUMBO_1K, true),
c558386b
HW		 264 [RTL_GIGA_MAC_VER_40] =
265 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_1,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_41] =
268 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
953a12cc 269};
85bffe6c 270#undef _R
953a12cc 271
bcf0bf90
FR		 272enum cfg_version {
273 RTL_CFG_0 = 0x00,
274 RTL_CFG_1,
275 RTL_CFG_2
276};
277
a3aa1884 278static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 279 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 280 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 281 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 282 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 283 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 284 { PCI_VENDOR_ID_DLINK, 0x4300,
285 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 286 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 287 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 288 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 289 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
290 { PCI_VENDOR_ID_LINKSYS, 0x1032,
291 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 292 { 0x0001, 0x8168,
293 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 294 {0,},
295};
296
297MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
298
6f0333b8 299static int rx_buf_sz = 16383;
4300e8c7 300static int use_dac;
b57b7e5a
SH		 301static struct {
302 u32 msg_enable;
303} debug = { -1 };
1da177e4 304
07d3f51f
FR		 305enum rtl_registers {
306 MAC0 = 0, /* Ethernet hardware address. */
773d2021 307 MAC4 = 4,
07d3f51f
FR		 308 MAR0 = 8, /* Multicast filter. */
309 CounterAddrLow = 0x10,
310 CounterAddrHigh = 0x14,
311 TxDescStartAddrLow = 0x20,
312 TxDescStartAddrHigh = 0x24,
313 TxHDescStartAddrLow = 0x28,
314 TxHDescStartAddrHigh = 0x2c,
315 FLASH = 0x30,
316 ERSR = 0x36,
317 ChipCmd = 0x37,
318 TxPoll = 0x38,
319 IntrMask = 0x3c,
320 IntrStatus = 0x3e,
4f6b00e5 321
07d3f51f 322 TxConfig = 0x40,
4f6b00e5
HW		 323#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
324#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 325
4f6b00e5
HW		 326 RxConfig = 0x44,
327#define RX128_INT_EN (1 << 15) /* 8111c and later */
328#define RX_MULTI_EN (1 << 14) /* 8111c only */
329#define RXCFG_FIFO_SHIFT 13
330 /* No threshold before first PCI xfer */
331#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
332#define RXCFG_DMA_SHIFT 8
333 /* Unlimited maximum PCI burst. */
334#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 335
07d3f51f
FR		 336 RxMissed = 0x4c,
337 Cfg9346 = 0x50,
338 Config0 = 0x51,
339 Config1 = 0x52,
340 Config2 = 0x53,
d387b427
FR		 341#define PME_SIGNAL (1 << 5) /* 8168c and later */
342
07d3f51f
FR		 343 Config3 = 0x54,
344 Config4 = 0x55,
345 Config5 = 0x56,
346 MultiIntr = 0x5c,
347 PHYAR = 0x60,
07d3f51f
FR		 348 PHYstatus = 0x6c,
349 RxMaxSize = 0xda,
350 CPlusCmd = 0xe0,
351 IntrMitigate = 0xe2,
352 RxDescAddrLow = 0xe4,
353 RxDescAddrHigh = 0xe8,
f0298f81 354 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
355
356#define NoEarlyTx 0x3f /* Max value : no early transmit. */
357
358 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
359
360#define TxPacketMax (8064 >> 7)
3090bd9a 361#define EarlySize 0x27
f0298f81 362
07d3f51f
FR		 363 FuncEvent = 0xf0,
364 FuncEventMask = 0xf4,
365 FuncPresetState = 0xf8,
366 FuncForceEvent = 0xfc,
1da177e4
LT		 367};
368
f162a5d1
FR		 369enum rtl8110_registers {
370 TBICSR = 0x64,
371 TBI_ANAR = 0x68,
372 TBI_LPAR = 0x6a,
373};
374
375enum rtl8168_8101_registers {
376 CSIDR = 0x64,
377 CSIAR = 0x68,
378#define CSIAR_FLAG 0x80000000
379#define CSIAR_WRITE_CMD 0x80000000
380#define CSIAR_BYTE_ENABLE 0x0f
381#define CSIAR_BYTE_ENABLE_SHIFT 12
382#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 383#define CSIAR_FUNC_CARD 0x00000000
384#define CSIAR_FUNC_SDIO 0x00010000
385#define CSIAR_FUNC_NIC 0x00020000
065c27c1 386 PMCH = 0x6f,
f162a5d1
FR		 387 EPHYAR = 0x80,
388#define EPHYAR_FLAG 0x80000000
389#define EPHYAR_WRITE_CMD 0x80000000
390#define EPHYAR_REG_MASK 0x1f
391#define EPHYAR_REG_SHIFT 16
392#define EPHYAR_DATA_MASK 0xffff
5a5e4443 393 DLLPR = 0xd0,
4f6b00e5 394#define PFM_EN (1 << 6)
f162a5d1
FR		 395 DBG_REG = 0xd1,
396#define FIX_NAK_1 (1 << 4)
397#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 398 TWSI = 0xd2,
399 MCU = 0xd3,
4f6b00e5 400#define NOW_IS_OOB (1 << 7)
c558386b
HW		 401#define TX_EMPTY (1 << 5)
402#define RX_EMPTY (1 << 4)
403#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 404#define EN_NDP (1 << 3)
405#define EN_OOB_RESET (1 << 2)
c558386b 406#define LINK_LIST_RDY (1 << 1)
daf9df6d 407 EFUSEAR = 0xdc,
408#define EFUSEAR_FLAG 0x80000000
409#define EFUSEAR_WRITE_CMD 0x80000000
410#define EFUSEAR_READ_CMD 0x00000000
411#define EFUSEAR_REG_MASK 0x03ff
412#define EFUSEAR_REG_SHIFT 8
413#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 414};
415
c0e45c1c 416enum rtl8168_registers {
4f6b00e5
HW		 417 LED_FREQ = 0x1a,
418 EEE_LED = 0x1b,
b646d900 419 ERIDR = 0x70,
420 ERIAR = 0x74,
421#define ERIAR_FLAG 0x80000000
422#define ERIAR_WRITE_CMD 0x80000000
423#define ERIAR_READ_CMD 0x00000000
424#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 425#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 426#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
427#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
428#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
429#define ERIAR_MASK_SHIFT 12
430#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
431#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 432#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 433#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 434 EPHY_RXER_NUM = 0x7c,
435 OCPDR = 0xb0, /* OCP GPHY access */
436#define OCPDR_WRITE_CMD 0x80000000
437#define OCPDR_READ_CMD 0x00000000
438#define OCPDR_REG_MASK 0x7f
439#define OCPDR_GPHY_REG_SHIFT 16
440#define OCPDR_DATA_MASK 0xffff
441 OCPAR = 0xb4,
442#define OCPAR_FLAG 0x80000000
443#define OCPAR_GPHY_WRITE_CMD 0x8000f060
444#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 445 GPHY_OCP = 0xb8,
01dc7fec 446 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
447 MISC = 0xf0, /* 8168e only. */
cecb5fd7 448#define TXPLA_RST (1 << 29)
5598bfe5 449#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 450#define PWM_EN (1 << 22)
c558386b 451#define RXDV_GATED_EN (1 << 19)
5598bfe5 452#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 453};
454
07d3f51f 455enum rtl_register_content {
1da177e4 456 /* InterruptStatusBits */
07d3f51f
FR		 457 SYSErr = 0x8000,
458 PCSTimeout = 0x4000,
459 SWInt = 0x0100,
460 TxDescUnavail = 0x0080,
461 RxFIFOOver = 0x0040,
462 LinkChg = 0x0020,
463 RxOverflow = 0x0010,
464 TxErr = 0x0008,
465 TxOK = 0x0004,
466 RxErr = 0x0002,
467 RxOK = 0x0001,
1da177e4
LT		 468
469 /* RxStatusDesc */
e03f33af 470 RxBOVF = (1 << 24),
9dccf611
FR		 471 RxFOVF = (1 << 23),
472 RxRWT = (1 << 22),
473 RxRES = (1 << 21),
474 RxRUNT = (1 << 20),
475 RxCRC = (1 << 19),
1da177e4
LT		 476
477 /* ChipCmdBits */
4f6b00e5 478 StopReq = 0x80,
07d3f51f
FR		 479 CmdReset = 0x10,
480 CmdRxEnb = 0x08,
481 CmdTxEnb = 0x04,
482 RxBufEmpty = 0x01,
1da177e4 483
275391a4
FR		 484 /* TXPoll register p.5 */
485 HPQ = 0x80, /* Poll cmd on the high prio queue */
486 NPQ = 0x40, /* Poll cmd on the low prio queue */
487 FSWInt = 0x01, /* Forced software interrupt */
488
1da177e4 489 /* Cfg9346Bits */
07d3f51f
FR		 490 Cfg9346_Lock = 0x00,
491 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 492
493 /* rx_mode_bits */
07d3f51f
FR		 494 AcceptErr = 0x20,
495 AcceptRunt = 0x10,
496 AcceptBroadcast = 0x08,
497 AcceptMulticast = 0x04,
498 AcceptMyPhys = 0x02,
499 AcceptAllPhys = 0x01,
1687b566 500#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 501
1da177e4
LT		 502 /* TxConfigBits */
503 TxInterFrameGapShift = 24,
504 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
505
5d06a99f 506 /* Config1 register p.24 */
f162a5d1
FR		 507 LEDS1 = (1 << 7),
508 LEDS0 = (1 << 6),
f162a5d1
FR		 509 Speed_down = (1 << 4),
510 MEMMAP = (1 << 3),
511 IOMAP = (1 << 2),
512 VPD = (1 << 1),
5d06a99f
FR		 513 PMEnable = (1 << 0), /* Power Management Enable */
514
6dccd16b 515 /* Config2 register p. 25 */
2ca6cf06 516 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 517 PCI_Clock_66MHz = 0x01,
518 PCI_Clock_33MHz = 0x00,
519
61a4dcc2
FR		 520 /* Config3 register p.25 */
521 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
522 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 523 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 524 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 525
d58d46b5
FR		 526 /* Config4 register */
527 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
528
5d06a99f 529 /* Config5 register p.27 */
61a4dcc2
FR		 530 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
531 MWF = (1 << 5), /* Accept Multicast wakeup frame */
532 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 533 Spi_en = (1 << 3),
61a4dcc2 534 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 535 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
536
1da177e4
LT		 537 /* TBICSR p.28 */
538 TBIReset = 0x80000000,
539 TBILoopback = 0x40000000,
540 TBINwEnable = 0x20000000,
541 TBINwRestart = 0x10000000,
542 TBILinkOk = 0x02000000,
543 TBINwComplete = 0x01000000,
544
545 /* CPlusCmd p.31 */
f162a5d1
FR		 546 EnableBist = (1 << 15), // 8168 8101
547 Mac_dbgo_oe = (1 << 14), // 8168 8101
548 Normal_mode = (1 << 13), // unused
549 Force_half_dup = (1 << 12), // 8168 8101
550 Force_rxflow_en = (1 << 11), // 8168 8101
551 Force_txflow_en = (1 << 10), // 8168 8101
552 Cxpl_dbg_sel = (1 << 9), // 8168 8101
553 ASF = (1 << 8), // 8168 8101
554 PktCntrDisable = (1 << 7), // 8168 8101
555 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 556 RxVlan = (1 << 6),
557 RxChkSum = (1 << 5),
558 PCIDAC = (1 << 4),
559 PCIMulRW = (1 << 3),
0e485150
FR		 560 INTT_0 = 0x0000, // 8168
561 INTT_1 = 0x0001, // 8168
562 INTT_2 = 0x0002, // 8168
563 INTT_3 = 0x0003, // 8168
1da177e4
LT		 564
565 /* rtl8169_PHYstatus */
07d3f51f
FR		 566 TBI_Enable = 0x80,
567 TxFlowCtrl = 0x40,
568 RxFlowCtrl = 0x20,
569 _1000bpsF = 0x10,
570 _100bps = 0x08,
571 _10bps = 0x04,
572 LinkStatus = 0x02,
573 FullDup = 0x01,
1da177e4 574
1da177e4 575 /* _TBICSRBit */
07d3f51f 576 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 577
578 /* DumpCounterCommand */
07d3f51f 579 CounterDump = 0x8,
1da177e4
LT		 580};
581
2b7b4318
FR		 582enum rtl_desc_bit {
583 /* First doubleword. */
1da177e4
LT		 584 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
585 RingEnd = (1 << 30), /* End of descriptor ring */
586 FirstFrag = (1 << 29), /* First segment of a packet */
587 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 588};
589
590/* Generic case. */
591enum rtl_tx_desc_bit {
592 /* First doubleword. */
593 TD_LSO = (1 << 27), /* Large Send Offload */
594#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 595
2b7b4318
FR		 596 /* Second doubleword. */
597 TxVlanTag = (1 << 17), /* Add VLAN tag */
598};
599
600/* 8169, 8168b and 810x except 8102e. */
601enum rtl_tx_desc_bit_0 {
602 /* First doubleword. */
603#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
604 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
605 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
606 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
607};
608
609/* 8102e, 8168c and beyond. */
610enum rtl_tx_desc_bit_1 {
611 /* Second doubleword. */
612#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
613 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
614 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
615 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
616};
1da177e4 617
2b7b4318
FR		 618static const struct rtl_tx_desc_info {
619 struct {
620 u32 udp;
621 u32 tcp;
622 } checksum;
623 u16 mss_shift;
624 u16 opts_offset;
625} tx_desc_info [] = {
626 [RTL_TD_0] = {
627 .checksum = {
628 .udp = TD0_IP_CS | TD0_UDP_CS,
629 .tcp = TD0_IP_CS | TD0_TCP_CS
630 },
631 .mss_shift = TD0_MSS_SHIFT,
632 .opts_offset = 0
633 },
634 [RTL_TD_1] = {
635 .checksum = {
636 .udp = TD1_IP_CS | TD1_UDP_CS,
637 .tcp = TD1_IP_CS | TD1_TCP_CS
638 },
639 .mss_shift = TD1_MSS_SHIFT,
640 .opts_offset = 1
641 }
642};
643
644enum rtl_rx_desc_bit {
1da177e4
LT		 645 /* Rx private */
646 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
647 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
648
649#define RxProtoUDP (PID1)
650#define RxProtoTCP (PID0)
651#define RxProtoIP (PID1 | PID0)
652#define RxProtoMask RxProtoIP
653
654 IPFail = (1 << 16), /* IP checksum failed */
655 UDPFail = (1 << 15), /* UDP/IP checksum failed */
656 TCPFail = (1 << 14), /* TCP/IP checksum failed */
657 RxVlanTag = (1 << 16), /* VLAN tag available */
658};
659
660#define RsvdMask 0x3fffc000
661
662struct TxDesc {
6cccd6e7
REB		 663 __le32 opts1;
664 __le32 opts2;
665 __le64 addr;
1da177e4
LT		 666};
667
668struct RxDesc {
6cccd6e7
REB		 669 __le32 opts1;
670 __le32 opts2;
671 __le64 addr;
1da177e4
LT		 672};
673
674struct ring_info {
675 struct sk_buff *skb;
676 u32 len;
677 u8 __pad[sizeof(void *) - sizeof(u32)];
678};
679
f23e7fda 680enum features {
ccdffb9a
FR		 681 RTL_FEATURE_WOL = (1 << 0),
682 RTL_FEATURE_MSI = (1 << 1),
683 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 684};
685
355423d0
IV		 686struct rtl8169_counters {
687 __le64 tx_packets;
688 __le64 rx_packets;
689 __le64 tx_errors;
690 __le32 rx_errors;
691 __le16 rx_missed;
692 __le16 align_errors;
693 __le32 tx_one_collision;
694 __le32 tx_multi_collision;
695 __le64 rx_unicast;
696 __le64 rx_broadcast;
697 __le32 rx_multicast;
698 __le16 tx_aborted;
699 __le16 tx_underun;
700};
701
da78dbff 702enum rtl_flag {
6c4a70c5 703 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 704 RTL_FLAG_TASK_SLOW_PENDING,
705 RTL_FLAG_TASK_RESET_PENDING,
706 RTL_FLAG_TASK_PHY_PENDING,
707 RTL_FLAG_MAX
708};
709
8027aa24
JW		 710struct rtl8169_stats {
711 u64 packets;
712 u64 bytes;
713 struct u64_stats_sync syncp;
714};
715
1da177e4
LT		 716struct rtl8169_private {
717 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 718 struct pci_dev *pci_dev;
c4028958 719 struct net_device *dev;
bea3348e 720 struct napi_struct napi;
b57b7e5a 721 u32 msg_enable;
2b7b4318
FR		 722 u16 txd_version;
723 u16 mac_version;
1da177e4
LT		 724 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
725 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 726 u32 dirty_tx;
8027aa24
JW		 727 struct rtl8169_stats rx_stats;
728 struct rtl8169_stats tx_stats;
1da177e4
LT		 729 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
730 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
731 dma_addr_t TxPhyAddr;
732 dma_addr_t RxPhyAddr;
6f0333b8 733 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 734 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 735 struct timer_list timer;
736 u16 cp_cmd;
da78dbff
FR		 737
738 u16 event_slow;
c0e45c1c 739
740 struct mdio_ops {
24192210
FR		 741 void (*write)(struct rtl8169_private *, int, int);
742 int (*read)(struct rtl8169_private *, int);
c0e45c1c 743 } mdio_ops;
744
065c27c1 745 struct pll_power_ops {
746 void (*down)(struct rtl8169_private *);
747 void (*up)(struct rtl8169_private *);
748 } pll_power_ops;
749
d58d46b5
FR		 750 struct jumbo_ops {
751 void (*enable)(struct rtl8169_private *);
752 void (*disable)(struct rtl8169_private *);
753 } jumbo_ops;
754
beb1fe18 755 struct csi_ops {
52989f0e
FR		 756 void (*write)(struct rtl8169_private *, int, int);
757 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 758 } csi_ops;
759
54405cde 760 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 761 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 762 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 763 void (*hw_start)(struct net_device *);
4da19633 764 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 765 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 766 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 767
768 struct {
da78dbff
FR		 769 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
770 struct mutex mutex;
4422bcd4
FR		 771 struct work_struct work;
772 } wk;
773
f23e7fda 774 unsigned features;
ccdffb9a
FR		 775
776 struct mii_if_info mii;
355423d0 777 struct rtl8169_counters counters;
e1759441 778 u32 saved_wolopts;
e03f33af 779 u32 opts1_mask;
f1e02ed1 780
b6ffd97f
FR		 781 struct rtl_fw {
782 const struct firmware *fw;
1c361efb
FR		 783
784#define RTL_VER_SIZE 32
785
786 char version[RTL_VER_SIZE];
787
788 struct rtl_fw_phy_action {
789 __le32 *code;
790 size_t size;
791 } phy_action;
b6ffd97f 792 } *rtl_fw;
497888cf 793#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 794
795 u32 ocp_base;
1da177e4
LT		 796};
797
979b6c13 798MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 799MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 800module_param(use_dac, int, 0);
4300e8c7 801MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 802module_param_named(debug, debug.msg_enable, int, 0);
803MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 804MODULE_LICENSE("GPL");
805MODULE_VERSION(RTL8169_VERSION);
bca03d5f 806MODULE_FIRMWARE(FIRMWARE_8168D_1);
807MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 808MODULE_FIRMWARE(FIRMWARE_8168E_1);
809MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 810MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 811MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 812MODULE_FIRMWARE(FIRMWARE_8168F_1);
813MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 814MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 815MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 816MODULE_FIRMWARE(FIRMWARE_8106E_1);
c558386b 817MODULE_FIRMWARE(FIRMWARE_8168G_1);
1da177e4 818
da78dbff
FR		 819static void rtl_lock_work(struct rtl8169_private *tp)
820{
821 mutex_lock(&tp->wk.mutex);
822}
823
824static void rtl_unlock_work(struct rtl8169_private *tp)
825{
826 mutex_unlock(&tp->wk.mutex);
827}
828
d58d46b5
FR		 829static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
830{
7d7903b2
JL		 831 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
832 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 833}
834
ffc46952
FR		 835struct rtl_cond {
836 bool (*check)(struct rtl8169_private *);
837 const char *msg;
838};
839
840static void rtl_udelay(unsigned int d)
841{
842 udelay(d);
843}
844
845static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
846 void (*delay)(unsigned int), unsigned int d, int n,
847 bool high)
848{
849 int i;
850
851 for (i = 0; i < n; i++) {
852 delay(d);
853 if (c->check(tp) == high)
854 return true;
855 }
82e316ef
FR		 856 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
857 c->msg, !high, n, d);
ffc46952
FR		 858 return false;
859}
860
861static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
862 const struct rtl_cond *c,
863 unsigned int d, int n)
864{
865 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
866}
867
868static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
869 const struct rtl_cond *c,
870 unsigned int d, int n)
871{
872 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
873}
874
875static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
876 const struct rtl_cond *c,
877 unsigned int d, int n)
878{
879 return rtl_loop_wait(tp, c, msleep, d, n, true);
880}
881
882static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
883 const struct rtl_cond *c,
884 unsigned int d, int n)
885{
886 return rtl_loop_wait(tp, c, msleep, d, n, false);
887}
888
889#define DECLARE_RTL_COND(name) \
890static bool name ## _check(struct rtl8169_private *); \
891 \
892static const struct rtl_cond name = { \
893 .check = name ## _check, \
894 .msg = #name \
895}; \
896 \
897static bool name ## _check(struct rtl8169_private *tp)
898
899DECLARE_RTL_COND(rtl_ocpar_cond)
900{
901 void __iomem *ioaddr = tp->mmio_addr;
902
903 return RTL_R32(OCPAR) & OCPAR_FLAG;
904}
905
b646d900 906static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
907{
908 void __iomem *ioaddr = tp->mmio_addr;
b646d900 909
910 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 911
912 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
913 RTL_R32(OCPDR) : ~0;
b646d900 914}
915
916static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
917{
918 void __iomem *ioaddr = tp->mmio_addr;
b646d900 919
920 RTL_W32(OCPDR, data);
921 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 922
923 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
924}
925
926DECLARE_RTL_COND(rtl_eriar_cond)
927{
928 void __iomem *ioaddr = tp->mmio_addr;
929
930 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 931}
932
fac5b3ca 933static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 934{
fac5b3ca 935 void __iomem *ioaddr = tp->mmio_addr;
b646d900 936
937 RTL_W8(ERIDR, cmd);
938 RTL_W32(ERIAR, 0x800010e8);
939 msleep(2);
ffc46952
FR		 940
941 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
942 return;
b646d900 943
fac5b3ca 944 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 945}
946
947#define OOB_CMD_RESET 0x00
948#define OOB_CMD_DRIVER_START 0x05
949#define OOB_CMD_DRIVER_STOP 0x06
950
cecb5fd7
FR		 951static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
952{
953 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
954}
955
ffc46952 956DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 957{
cecb5fd7 958 u16 reg;
b646d900 959
cecb5fd7 960 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 961
ffc46952 962 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 963}
964
ffc46952 965static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 966{
ffc46952 967 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 968
ffc46952
FR		 969 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
970}
b646d900 971
ffc46952
FR		 972static void rtl8168_driver_stop(struct rtl8169_private *tp)
973{
974 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 975
ffc46952 976 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 977}
978
4804b3b3 979static int r8168dp_check_dash(struct rtl8169_private *tp)
980{
cecb5fd7 981 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 982
cecb5fd7 983 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 984}
b646d900 985
c558386b
HW		 986static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
987{
988 if (reg & 0xffff0001) {
989 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
990 return true;
991 }
992 return false;
993}
994
995DECLARE_RTL_COND(rtl_ocp_gphy_cond)
996{
997 void __iomem *ioaddr = tp->mmio_addr;
998
999 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1000}
1001
1002static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1003{
1004 void __iomem *ioaddr = tp->mmio_addr;
1005
1006 if (rtl_ocp_reg_failure(tp, reg))
1007 return;
1008
1009 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1010
1011 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1012}
1013
1014static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1015{
1016 void __iomem *ioaddr = tp->mmio_addr;
1017
1018 if (rtl_ocp_reg_failure(tp, reg))
1019 return 0;
1020
1021 RTL_W32(GPHY_OCP, reg << 15);
1022
1023 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1024 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1025}
1026
c558386b
HW		 1027static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1028{
1029 void __iomem *ioaddr = tp->mmio_addr;
1030
1031 if (rtl_ocp_reg_failure(tp, reg))
1032 return;
1033
1034 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1035}
1036
1037static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1038{
1039 void __iomem *ioaddr = tp->mmio_addr;
1040
1041 if (rtl_ocp_reg_failure(tp, reg))
1042 return 0;
1043
1044 RTL_W32(OCPDR, reg << 15);
1045
3a83ad12 1046 return RTL_R32(OCPDR);
c558386b
HW		 1047}
1048
1049#define OCP_STD_PHY_BASE 0xa400
1050
1051static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1052{
1053 if (reg == 0x1f) {
1054 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1055 return;
1056 }
1057
1058 if (tp->ocp_base != OCP_STD_PHY_BASE)
1059 reg -= 0x10;
1060
1061 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1062}
1063
1064static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1065{
1066 if (tp->ocp_base != OCP_STD_PHY_BASE)
1067 reg -= 0x10;
1068
1069 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1070}
1071
eee3786f 1072static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1073{
1074 if (reg == 0x1f) {
1075 tp->ocp_base = value << 4;
1076 return;
1077 }
1078
1079 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1080}
1081
1082static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1083{
1084 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1085}
1086
ffc46952
FR		 1087DECLARE_RTL_COND(rtl_phyar_cond)
1088{
1089 void __iomem *ioaddr = tp->mmio_addr;
1090
1091 return RTL_R32(PHYAR) & 0x80000000;
1092}
1093
24192210 1094static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1095{
24192210 1096 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1097
24192210 1098 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1099
ffc46952 1100 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1101 /*
81a95f04
TT		 1102 * According to hardware specs a 20us delay is required after write
1103 * complete indication, but before sending next command.
024a07ba 1104 */
81a95f04 1105 udelay(20);
1da177e4
LT		 1106}
1107
24192210 1108static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1109{
24192210 1110 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1111 int value;
1da177e4 1112
24192210 1113 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1114
ffc46952
FR		 1115 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1116 RTL_R32(PHYAR) & 0xffff : ~0;
1117
81a95f04
TT		 1118 /*
1119 * According to hardware specs a 20us delay is required after read
1120 * complete indication, but before sending next command.
1121 */
1122 udelay(20);
1123
1da177e4
LT		 1124 return value;
1125}
1126
24192210 1127static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1128{
24192210 1129 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1130
24192210 1131 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1132 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1133 RTL_W32(EPHY_RXER_NUM, 0);
1134
ffc46952 1135 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1136}
1137
24192210 1138static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1139{
24192210
FR		 1140 r8168dp_1_mdio_access(tp, reg,
1141 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1142}
1143
24192210 1144static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1145{
24192210 1146 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1147
24192210 1148 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1149
1150 mdelay(1);
1151 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1152 RTL_W32(EPHY_RXER_NUM, 0);
1153
ffc46952
FR		 1154 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1155 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1156}
1157
e6de30d6 1158#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1159
1160static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1161{
1162 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1163}
1164
1165static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1166{
1167 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1168}
1169
24192210 1170static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1171{
24192210
FR		 1172 void __iomem *ioaddr = tp->mmio_addr;
1173
e6de30d6 1174 r8168dp_2_mdio_start(ioaddr);
1175
24192210 1176 r8169_mdio_write(tp, reg, value);
e6de30d6 1177
1178 r8168dp_2_mdio_stop(ioaddr);
1179}
1180
24192210 1181static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1182{
24192210 1183 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1184 int value;
1185
1186 r8168dp_2_mdio_start(ioaddr);
1187
24192210 1188 value = r8169_mdio_read(tp, reg);
e6de30d6 1189
1190 r8168dp_2_mdio_stop(ioaddr);
1191
1192 return value;
1193}
1194
4da19633 1195static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1196{
24192210 1197 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1198}
1199
4da19633 1200static int rtl_readphy(struct rtl8169_private *tp, int location)
1201{
24192210 1202 return tp->mdio_ops.read(tp, location);
4da19633 1203}
1204
1205static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1206{
1207 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1208}
1209
1210static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1211{
1212 int val;
1213
4da19633 1214 val = rtl_readphy(tp, reg_addr);
1215 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1216}
1217
ccdffb9a
FR		 1218static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1219 int val)
1220{
1221 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1222
4da19633 1223 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1224}
1225
1226static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1227{
1228 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1229
4da19633 1230 return rtl_readphy(tp, location);
ccdffb9a
FR		 1231}
1232
ffc46952
FR		 1233DECLARE_RTL_COND(rtl_ephyar_cond)
1234{
1235 void __iomem *ioaddr = tp->mmio_addr;
1236
1237 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1238}
1239
fdf6fc06 1240static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1241{
fdf6fc06 1242 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1243
1244 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1245 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1246
ffc46952
FR		 1247 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1248
1249 udelay(10);
dacf8154
FR		 1250}
1251
fdf6fc06 1252static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1253{
fdf6fc06 1254 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1255
1256 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1257
ffc46952
FR		 1258 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1259 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1260}
1261
fdf6fc06
FR		 1262static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1263 u32 val, int type)
133ac40a 1264{
fdf6fc06 1265 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1266
1267 BUG_ON((addr & 3) || (mask == 0));
1268 RTL_W32(ERIDR, val);
1269 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1270
ffc46952 1271 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1272}
1273
fdf6fc06 1274static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1275{
fdf6fc06 1276 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1277
1278 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1279
ffc46952
FR		 1280 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1281 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1282}
1283
fdf6fc06
FR		 1284static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1285 u32 m, int type)
133ac40a
HW		 1286{
1287 u32 val;
1288
fdf6fc06
FR		 1289 val = rtl_eri_read(tp, addr, type);
1290 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1291}
1292
c28aa385 1293struct exgmac_reg {
1294 u16 addr;
1295 u16 mask;
1296 u32 val;
1297};
1298
fdf6fc06 1299static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1300 const struct exgmac_reg *r, int len)
1301{
1302 while (len-- > 0) {
fdf6fc06 1303 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1304 r++;
1305 }
1306}
1307
ffc46952
FR		 1308DECLARE_RTL_COND(rtl_efusear_cond)
1309{
1310 void __iomem *ioaddr = tp->mmio_addr;
1311
1312 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1313}
1314
fdf6fc06 1315static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1316{
fdf6fc06 1317 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1318
1319 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1320
ffc46952
FR		 1321 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1322 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1323}
1324
9085cdfa
FR		 1325static u16 rtl_get_events(struct rtl8169_private *tp)
1326{
1327 void __iomem *ioaddr = tp->mmio_addr;
1328
1329 return RTL_R16(IntrStatus);
1330}
1331
1332static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1333{
1334 void __iomem *ioaddr = tp->mmio_addr;
1335
1336 RTL_W16(IntrStatus, bits);
1337 mmiowb();
1338}
1339
1340static void rtl_irq_disable(struct rtl8169_private *tp)
1341{
1342 void __iomem *ioaddr = tp->mmio_addr;
1343
1344 RTL_W16(IntrMask, 0);
1345 mmiowb();
1346}
1347
3e990ff5
FR		 1348static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1349{
1350 void __iomem *ioaddr = tp->mmio_addr;
1351
1352 RTL_W16(IntrMask, bits);
1353}
1354
da78dbff
FR		 1355#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1356#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1357#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1358
1359static void rtl_irq_enable_all(struct rtl8169_private *tp)
1360{
1361 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1362}
1363
811fd301 1364static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1365{
811fd301 1366 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1367
9085cdfa 1368 rtl_irq_disable(tp);
da78dbff 1369 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1370 RTL_R8(ChipCmd);
1da177e4
LT		 1371}
1372
4da19633 1373static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1374{
4da19633 1375 void __iomem *ioaddr = tp->mmio_addr;
1376
1da177e4
LT		 1377 return RTL_R32(TBICSR) & TBIReset;
1378}
1379
4da19633 1380static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1381{
4da19633 1382 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1383}
1384
1385static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1386{
1387 return RTL_R32(TBICSR) & TBILinkOk;
1388}
1389
1390static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1391{
1392 return RTL_R8(PHYstatus) & LinkStatus;
1393}
1394
4da19633 1395static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1396{
4da19633 1397 void __iomem *ioaddr = tp->mmio_addr;
1398
1da177e4
LT		 1399 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1400}
1401
4da19633 1402static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1403{
1404 unsigned int val;
1405
4da19633 1406 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1407 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1408}
1409
70090424
HW		 1410static void rtl_link_chg_patch(struct rtl8169_private *tp)
1411{
1412 void __iomem *ioaddr = tp->mmio_addr;
1413 struct net_device *dev = tp->dev;
1414
1415 if (!netif_running(dev))
1416 return;
1417
b3d7b2f2
HW		 1418 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1419 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1420 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1421 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1422 ERIAR_EXGMAC);
1423 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1424 ERIAR_EXGMAC);
70090424 1425 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1426 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1427 ERIAR_EXGMAC);
1428 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1429 ERIAR_EXGMAC);
70090424 1430 } else {
fdf6fc06
FR		 1431 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1432 ERIAR_EXGMAC);
1433 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1434 ERIAR_EXGMAC);
70090424
HW		 1435 }
1436 /* Reset packet filter */
fdf6fc06 1437 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1438 ERIAR_EXGMAC);
fdf6fc06 1439 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1440 ERIAR_EXGMAC);
c2218925
HW		 1441 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1442 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1443 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1444 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1445 ERIAR_EXGMAC);
1446 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1447 ERIAR_EXGMAC);
c2218925 1448 } else {
fdf6fc06
FR		 1449 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1450 ERIAR_EXGMAC);
1451 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1452 ERIAR_EXGMAC);
c2218925 1453 }
7e18dca1
HW		 1454 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1455 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1456 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1457 ERIAR_EXGMAC);
1458 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1459 ERIAR_EXGMAC);
7e18dca1 1460 } else {
fdf6fc06
FR		 1461 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1462 ERIAR_EXGMAC);
7e18dca1 1463 }
70090424
HW		 1464 }
1465}
1466
e4fbce74 1467static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1468 struct rtl8169_private *tp,
1469 void __iomem *ioaddr, bool pm)
1da177e4 1470{
1da177e4 1471 if (tp->link_ok(ioaddr)) {
70090424 1472 rtl_link_chg_patch(tp);
e1759441 1473 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1474 if (pm)
1475 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1476 netif_carrier_on(dev);
1519e57f
FR		 1477 if (net_ratelimit())
1478 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1479 } else {
1da177e4 1480 netif_carrier_off(dev);
bf82c189 1481 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1482 if (pm)
10953db8 1483 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1484 }
1da177e4
LT		 1485}
1486
e4fbce74
RW		 1487static void rtl8169_check_link_status(struct net_device *dev,
1488 struct rtl8169_private *tp,
1489 void __iomem *ioaddr)
1490{
1491 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1492}
1493
e1759441
RW		 1494#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1495
1496static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1497{
61a4dcc2
FR		 1498 void __iomem *ioaddr = tp->mmio_addr;
1499 u8 options;
e1759441 1500 u32 wolopts = 0;
61a4dcc2
FR		 1501
1502 options = RTL_R8(Config1);
1503 if (!(options & PMEnable))
e1759441 1504 return 0;
61a4dcc2
FR		 1505
1506 options = RTL_R8(Config3);
1507 if (options & LinkUp)
e1759441 1508 wolopts |= WAKE_PHY;
61a4dcc2 1509 if (options & MagicPacket)
e1759441 1510 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1511
1512 options = RTL_R8(Config5);
1513 if (options & UWF)
e1759441 1514 wolopts |= WAKE_UCAST;
61a4dcc2 1515 if (options & BWF)
e1759441 1516 wolopts |= WAKE_BCAST;
61a4dcc2 1517 if (options & MWF)
e1759441 1518 wolopts |= WAKE_MCAST;
61a4dcc2 1519
e1759441 1520 return wolopts;
61a4dcc2
FR		 1521}
1522
e1759441 1523static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1524{
1525 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1526
da78dbff 1527 rtl_lock_work(tp);
e1759441
RW		 1528
1529 wol->supported = WAKE_ANY;
1530 wol->wolopts = __rtl8169_get_wol(tp);
1531
da78dbff 1532 rtl_unlock_work(tp);
e1759441
RW		 1533}
1534
1535static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1536{
61a4dcc2 1537 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1538 unsigned int i;
350f7596 1539 static const struct {
61a4dcc2
FR		 1540 u32 opt;
1541 u16 reg;
1542 u8 mask;
1543 } cfg[] = {
61a4dcc2
FR		 1544 { WAKE_PHY, Config3, LinkUp },
1545 { WAKE_MAGIC, Config3, MagicPacket },
1546 { WAKE_UCAST, Config5, UWF },
1547 { WAKE_BCAST, Config5, BWF },
1548 { WAKE_MCAST, Config5, MWF },
1549 { WAKE_ANY, Config5, LanWake }
1550 };
851e6022 1551 u8 options;
61a4dcc2 1552
61a4dcc2
FR		 1553 RTL_W8(Cfg9346, Cfg9346_Unlock);
1554
1555 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1556 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1557 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1558 options |= cfg[i].mask;
1559 RTL_W8(cfg[i].reg, options);
1560 }
1561
851e6022
FR		 1562 switch (tp->mac_version) {
1563 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1564 options = RTL_R8(Config1) & ~PMEnable;
1565 if (wolopts)
1566 options |= PMEnable;
1567 RTL_W8(Config1, options);
1568 break;
1569 default:
d387b427
FR		 1570 options = RTL_R8(Config2) & ~PME_SIGNAL;
1571 if (wolopts)
1572 options |= PME_SIGNAL;
1573 RTL_W8(Config2, options);
851e6022
FR		 1574 break;
1575 }
1576
61a4dcc2 1577 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1578}
1579
1580static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1581{
1582 struct rtl8169_private *tp = netdev_priv(dev);
1583
da78dbff 1584 rtl_lock_work(tp);
61a4dcc2 1585
f23e7fda
FR		 1586 if (wol->wolopts)
1587 tp->features |= RTL_FEATURE_WOL;
1588 else
1589 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1590 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1591
1592 rtl_unlock_work(tp);
61a4dcc2 1593
ea80907f 1594 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1595
61a4dcc2
FR		 1596 return 0;
1597}
1598
31bd204f
FR		 1599static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1600{
85bffe6c 1601 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1602}
1603
1da177e4
LT		 1604static void rtl8169_get_drvinfo(struct net_device *dev,
1605 struct ethtool_drvinfo *info)
1606{
1607 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1608 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1609
68aad78c
RJ		 1610 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1611 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1612 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1613 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1614 if (!IS_ERR_OR_NULL(rtl_fw))
1615 strlcpy(info->fw_version, rtl_fw->version,
1616 sizeof(info->fw_version));
1da177e4
LT		 1617}
1618
1619static int rtl8169_get_regs_len(struct net_device *dev)
1620{
1621 return R8169_REGS_SIZE;
1622}
1623
1624static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1625 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1626{
1627 struct rtl8169_private *tp = netdev_priv(dev);
1628 void __iomem *ioaddr = tp->mmio_addr;
1629 int ret = 0;
1630 u32 reg;
1631
1632 reg = RTL_R32(TBICSR);
1633 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1634 (duplex == DUPLEX_FULL)) {
1635 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1636 } else if (autoneg == AUTONEG_ENABLE)
1637 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1638 else {
bf82c189
JP		 1639 netif_warn(tp, link, dev,
1640 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1641 ret = -EOPNOTSUPP;
1642 }
1643
1644 return ret;
1645}
1646
1647static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1648 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1649{
1650 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1651 int giga_ctrl, bmcr;
54405cde 1652 int rc = -EINVAL;
1da177e4 1653
716b50a3 1654 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1655
1656 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1657 int auto_nego;
1658
4da19633 1659 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1660 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1661 ADVERTISE_100HALF | ADVERTISE_100FULL);
1662
1663 if (adv & ADVERTISED_10baseT_Half)
1664 auto_nego |= ADVERTISE_10HALF;
1665 if (adv & ADVERTISED_10baseT_Full)
1666 auto_nego |= ADVERTISE_10FULL;
1667 if (adv & ADVERTISED_100baseT_Half)
1668 auto_nego |= ADVERTISE_100HALF;
1669 if (adv & ADVERTISED_100baseT_Full)
1670 auto_nego |= ADVERTISE_100FULL;
1671
3577aa1b 1672 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1673
4da19633 1674 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1675 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1676
3577aa1b 1677 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1678 if (tp->mii.supports_gmii) {
54405cde
ON		 1679 if (adv & ADVERTISED_1000baseT_Half)
1680 giga_ctrl |= ADVERTISE_1000HALF;
1681 if (adv & ADVERTISED_1000baseT_Full)
1682 giga_ctrl |= ADVERTISE_1000FULL;
1683 } else if (adv & (ADVERTISED_1000baseT_Half |
1684 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1685 netif_info(tp, link, dev,
1686 "PHY does not support 1000Mbps\n");
54405cde 1687 goto out;
bcf0bf90 1688 }
1da177e4 1689
3577aa1b 1690 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1691
4da19633 1692 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1693 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1694 } else {
1695 giga_ctrl = 0;
1696
1697 if (speed == SPEED_10)
1698 bmcr = 0;
1699 else if (speed == SPEED_100)
1700 bmcr = BMCR_SPEED100;
1701 else
54405cde 1702 goto out;
3577aa1b 1703
1704 if (duplex == DUPLEX_FULL)
1705 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1706 }
1707
4da19633 1708 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1709
cecb5fd7
FR		 1710 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1711 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1712 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1713 rtl_writephy(tp, 0x17, 0x2138);
1714 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1715 } else {
4da19633 1716 rtl_writephy(tp, 0x17, 0x2108);
1717 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1718 }
1719 }
1720
54405cde
ON		 1721 rc = 0;
1722out:
1723 return rc;
1da177e4
LT		 1724}
1725
1726static int rtl8169_set_speed(struct net_device *dev,
54405cde 1727 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1728{
1729 struct rtl8169_private *tp = netdev_priv(dev);
1730 int ret;
1731
54405cde 1732 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1733 if (ret < 0)
1734 goto out;
1da177e4 1735
4876cc1e
FR		 1736 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1737 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1738 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1739 }
1740out:
1da177e4
LT		 1741 return ret;
1742}
1743
1744static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1745{
1746 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1747 int ret;
1748
4876cc1e
FR		 1749 del_timer_sync(&tp->timer);
1750
da78dbff 1751 rtl_lock_work(tp);
cecb5fd7 1752 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1753 cmd->duplex, cmd->advertising);
da78dbff 1754 rtl_unlock_work(tp);
5b0384f4 1755
1da177e4
LT		 1756 return ret;
1757}
1758
c8f44aff
MM		 1759static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1760 netdev_features_t features)
1da177e4 1761{
d58d46b5
FR		 1762 struct rtl8169_private *tp = netdev_priv(dev);
1763
2b7b4318 1764 if (dev->mtu > TD_MSS_MAX)
350fb32a 1765 features &= ~NETIF_F_ALL_TSO;
1da177e4 1766
d58d46b5
FR		 1767 if (dev->mtu > JUMBO_1K &&
1768 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1769 features &= ~NETIF_F_IP_CSUM;
1770
350fb32a 1771 return features;
1da177e4
LT		 1772}
1773
da78dbff
FR		 1774static void __rtl8169_set_features(struct net_device *dev,
1775 netdev_features_t features)
1da177e4
LT		 1776{
1777 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1778 netdev_features_t changed = features ^ dev->features;
da78dbff 1779 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1780
6bbe021d
BG		 1781 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1782 return;
1da177e4 1783
6bbe021d
BG		 1784 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1785 if (features & NETIF_F_RXCSUM)
1786 tp->cp_cmd |= RxChkSum;
1787 else
1788 tp->cp_cmd &= ~RxChkSum;
350fb32a 1789
6bbe021d
BG		 1790 if (dev->features & NETIF_F_HW_VLAN_RX)
1791 tp->cp_cmd |= RxVlan;
1792 else
1793 tp->cp_cmd &= ~RxVlan;
1794
1795 RTL_W16(CPlusCmd, tp->cp_cmd);
1796 RTL_R16(CPlusCmd);
1797 }
1798 if (changed & NETIF_F_RXALL) {
1799 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1800 if (features & NETIF_F_RXALL)
1801 tmp |= (AcceptErr | AcceptRunt);
1802 RTL_W32(RxConfig, tmp);
1803 }
da78dbff 1804}
1da177e4 1805
da78dbff
FR		 1806static int rtl8169_set_features(struct net_device *dev,
1807 netdev_features_t features)
1808{
1809 struct rtl8169_private *tp = netdev_priv(dev);
1810
1811 rtl_lock_work(tp);
1812 __rtl8169_set_features(dev, features);
1813 rtl_unlock_work(tp);
1da177e4
LT		 1814
1815 return 0;
1816}
1817
da78dbff 1818
810f4893 1819static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1820{
eab6d18d 1821 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1822 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1823}
1824
7a8fc77b 1825static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1826{
1827 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1828
7a8fc77b
FR		 1829 if (opts2 & RxVlanTag)
1830 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1da177e4
LT		 1831}
1832
ccdffb9a 1833static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1834{
1835 struct rtl8169_private *tp = netdev_priv(dev);
1836 void __iomem *ioaddr = tp->mmio_addr;
1837 u32 status;
1838
1839 cmd->supported =
1840 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1841 cmd->port = PORT_FIBRE;
1842 cmd->transceiver = XCVR_INTERNAL;
1843
1844 status = RTL_R32(TBICSR);
1845 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1846 cmd->autoneg = !!(status & TBINwEnable);
1847
70739497 1848 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1849 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1850
1851 return 0;
1da177e4
LT		 1852}
1853
ccdffb9a 1854static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1855{
1856 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1857
1858 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1859}
1860
1861static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1862{
1863 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1864 int rc;
1da177e4 1865
da78dbff 1866 rtl_lock_work(tp);
ccdffb9a 1867 rc = tp->get_settings(dev, cmd);
da78dbff 1868 rtl_unlock_work(tp);
1da177e4 1869
ccdffb9a 1870 return rc;
1da177e4
LT		 1871}
1872
1873static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1874 void *p)
1875{
5b0384f4 1876 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1877
5b0384f4
FR		 1878 if (regs->len > R8169_REGS_SIZE)
1879 regs->len = R8169_REGS_SIZE;
1da177e4 1880
da78dbff 1881 rtl_lock_work(tp);
5b0384f4 1882 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1883 rtl_unlock_work(tp);
1da177e4
LT		 1884}
1885
b57b7e5a
SH		 1886static u32 rtl8169_get_msglevel(struct net_device *dev)
1887{
1888 struct rtl8169_private *tp = netdev_priv(dev);
1889
1890 return tp->msg_enable;
1891}
1892
1893static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1894{
1895 struct rtl8169_private *tp = netdev_priv(dev);
1896
1897 tp->msg_enable = value;
1898}
1899
d4a3a0fc
SH		 1900static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1901 "tx_packets",
1902 "rx_packets",
1903 "tx_errors",
1904 "rx_errors",
1905 "rx_missed",
1906 "align_errors",
1907 "tx_single_collisions",
1908 "tx_multi_collisions",
1909 "unicast",
1910 "broadcast",
1911 "multicast",
1912 "tx_aborted",
1913 "tx_underrun",
1914};
1915
b9f2c044 1916static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1917{
b9f2c044
JG		 1918 switch (sset) {
1919 case ETH_SS_STATS:
1920 return ARRAY_SIZE(rtl8169_gstrings);
1921 default:
1922 return -EOPNOTSUPP;
1923 }
d4a3a0fc
SH		 1924}
1925
ffc46952
FR		 1926DECLARE_RTL_COND(rtl_counters_cond)
1927{
1928 void __iomem *ioaddr = tp->mmio_addr;
1929
1930 return RTL_R32(CounterAddrLow) & CounterDump;
1931}
1932
355423d0 1933static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1934{
1935 struct rtl8169_private *tp = netdev_priv(dev);
1936 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1937 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1938 struct rtl8169_counters *counters;
1939 dma_addr_t paddr;
1940 u32 cmd;
1941
355423d0
IV		 1942 /*
1943 * Some chips are unable to dump tally counters when the receiver
1944 * is disabled.
1945 */
1946 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1947 return;
d4a3a0fc 1948
48addcc9 1949 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1950 if (!counters)
1951 return;
1952
1953 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1954 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1955 RTL_W32(CounterAddrLow, cmd);
1956 RTL_W32(CounterAddrLow, cmd | CounterDump);
1957
ffc46952
FR		 1958 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1959 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1960
1961 RTL_W32(CounterAddrLow, 0);
1962 RTL_W32(CounterAddrHigh, 0);
1963
48addcc9 1964 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1965}
1966
355423d0
IV		 1967static void rtl8169_get_ethtool_stats(struct net_device *dev,
1968 struct ethtool_stats *stats, u64 *data)
1969{
1970 struct rtl8169_private *tp = netdev_priv(dev);
1971
1972 ASSERT_RTNL();
1973
1974 rtl8169_update_counters(dev);
1975
1976 data[0] = le64_to_cpu(tp->counters.tx_packets);
1977 data[1] = le64_to_cpu(tp->counters.rx_packets);
1978 data[2] = le64_to_cpu(tp->counters.tx_errors);
1979 data[3] = le32_to_cpu(tp->counters.rx_errors);
1980 data[4] = le16_to_cpu(tp->counters.rx_missed);
1981 data[5] = le16_to_cpu(tp->counters.align_errors);
1982 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1983 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1984 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1985 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1986 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1987 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1988 data[12] = le16_to_cpu(tp->counters.tx_underun);
1989}
1990
d4a3a0fc
SH		 1991static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1992{
1993 switch(stringset) {
1994 case ETH_SS_STATS:
1995 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1996 break;
1997 }
1998}
1999
7282d491 2000static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2001 .get_drvinfo = rtl8169_get_drvinfo,
2002 .get_regs_len = rtl8169_get_regs_len,
2003 .get_link = ethtool_op_get_link,
2004 .get_settings = rtl8169_get_settings,
2005 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2006 .get_msglevel = rtl8169_get_msglevel,
2007 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2008 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2009 .get_wol = rtl8169_get_wol,
2010 .set_wol = rtl8169_set_wol,
d4a3a0fc 2011 .get_strings = rtl8169_get_strings,
b9f2c044 2012 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2013 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2014 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2015};
2016
07d3f51f 2017static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2018 struct net_device *dev, u8 default_version)
1da177e4 2019{
5d320a20 2020 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2021 /*
2022 * The driver currently handles the 8168Bf and the 8168Be identically
2023 * but they can be identified more specifically through the test below
2024 * if needed:
2025 *
2026 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2027 *
2028 * Same thing for the 8101Eb and the 8101Ec:
2029 *
2030 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2031 */
3744100e 2032 static const struct rtl_mac_info {
1da177e4 2033 u32 mask;
e3cf0cc0 2034 u32 val;
1da177e4
LT		 2035 int mac_version;
2036 } mac_info[] = {
c558386b
HW		 2037 /* 8168G family. */
2038 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2039 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2040
c2218925 2041 /* 8168F family. */
b3d7b2f2 2042 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2043 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2044 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2045
01dc7fec 2046 /* 8168E family. */
70090424 2047 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2048 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2049 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2050 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2051
5b538df9 2052 /* 8168D family. */
daf9df6d 2053 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2054 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2055 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2056
e6de30d6 2057 /* 8168DP family. */
2058 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2059 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2060 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2061
ef808d50 2062 /* 8168C family. */
17c99297 2063 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2064 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2065 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2066 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2067 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2068 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2069 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2070 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2071 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2072
2073 /* 8168B family. */
2074 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2075 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2076 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2077 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2078
2079 /* 8101 family. */
5598bfe5
HW		 2080 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2081 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2082 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2083 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2084 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2085 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2086 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2087 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2088 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2089 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2090 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2091 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2092 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2093 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2094 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2095 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2096 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2097 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2098 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2099 /* FIXME: where did these entries come from ? -- FR */
2100 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2101 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2102
2103 /* 8110 family. */
2104 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2105 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2106 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2107 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2108 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2109 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2110
f21b75e9
JD		 2111 /* Catch-all */
2112 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2113 };
2114 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2115 u32 reg;
2116
e3cf0cc0
FR		 2117 reg = RTL_R32(TxConfig);
2118 while ((reg & p->mask) != p->val)
1da177e4
LT		 2119 p++;
2120 tp->mac_version = p->mac_version;
5d320a20
FR		 2121
2122 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2123 netif_notice(tp, probe, dev,
2124 "unknown MAC, using family default\n");
2125 tp->mac_version = default_version;
2126 }
1da177e4
LT		 2127}
2128
2129static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2130{
bcf0bf90 2131 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2132}
2133
867763c1
FR		 2134struct phy_reg {
2135 u16 reg;
2136 u16 val;
2137};
2138
4da19633 2139static void rtl_writephy_batch(struct rtl8169_private *tp,
2140 const struct phy_reg *regs, int len)
867763c1
FR		 2141{
2142 while (len-- > 0) {
4da19633 2143 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2144 regs++;
2145 }
2146}
2147
bca03d5f 2148#define PHY_READ 0x00000000
2149#define PHY_DATA_OR 0x10000000
2150#define PHY_DATA_AND 0x20000000
2151#define PHY_BJMPN 0x30000000
eee3786f 2152#define PHY_MDIO_CHG 0x40000000
bca03d5f 2153#define PHY_CLEAR_READCOUNT 0x70000000
2154#define PHY_WRITE 0x80000000
2155#define PHY_READCOUNT_EQ_SKIP 0x90000000
2156#define PHY_COMP_EQ_SKIPN 0xa0000000
2157#define PHY_COMP_NEQ_SKIPN 0xb0000000
2158#define PHY_WRITE_PREVIOUS 0xc0000000
2159#define PHY_SKIPN 0xd0000000
2160#define PHY_DELAY_MS 0xe0000000
bca03d5f 2161
960aee6c
HW		 2162struct fw_info {
2163 u32 magic;
2164 char version[RTL_VER_SIZE];
2165 __le32 fw_start;
2166 __le32 fw_len;
2167 u8 chksum;
2168} __packed;
2169
1c361efb
FR		 2170#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2171
2172static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2173{
b6ffd97f 2174 const struct firmware *fw = rtl_fw->fw;
960aee6c 2175 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2176 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2177 char *version = rtl_fw->version;
2178 bool rc = false;
2179
2180 if (fw->size < FW_OPCODE_SIZE)
2181 goto out;
960aee6c
HW		 2182
2183 if (!fw_info->magic) {
2184 size_t i, size, start;
2185 u8 checksum = 0;
2186
2187 if (fw->size < sizeof(*fw_info))
2188 goto out;
2189
2190 for (i = 0; i < fw->size; i++)
2191 checksum += fw->data[i];
2192 if (checksum != 0)
2193 goto out;
2194
2195 start = le32_to_cpu(fw_info->fw_start);
2196 if (start > fw->size)
2197 goto out;
2198
2199 size = le32_to_cpu(fw_info->fw_len);
2200 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2201 goto out;
2202
2203 memcpy(version, fw_info->version, RTL_VER_SIZE);
2204
2205 pa->code = (__le32 *)(fw->data + start);
2206 pa->size = size;
2207 } else {
1c361efb
FR		 2208 if (fw->size % FW_OPCODE_SIZE)
2209 goto out;
2210
2211 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2212
2213 pa->code = (__le32 *)fw->data;
2214 pa->size = fw->size / FW_OPCODE_SIZE;
2215 }
2216 version[RTL_VER_SIZE - 1] = 0;
2217
2218 rc = true;
2219out:
2220 return rc;
2221}
2222
fd112f2e
FR		 2223static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2224 struct rtl_fw_phy_action *pa)
1c361efb 2225{
fd112f2e 2226 bool rc = false;
1c361efb 2227 size_t index;
bca03d5f 2228
1c361efb
FR		 2229 for (index = 0; index < pa->size; index++) {
2230 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2231 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2232
42b82dc1 2233 switch(action & 0xf0000000) {
2234 case PHY_READ:
2235 case PHY_DATA_OR:
2236 case PHY_DATA_AND:
eee3786f 2237 case PHY_MDIO_CHG:
42b82dc1 2238 case PHY_CLEAR_READCOUNT:
2239 case PHY_WRITE:
2240 case PHY_WRITE_PREVIOUS:
2241 case PHY_DELAY_MS:
2242 break;
2243
2244 case PHY_BJMPN:
2245 if (regno > index) {
fd112f2e 2246 netif_err(tp, ifup, tp->dev,
cecb5fd7 2247 "Out of range of firmware\n");
fd112f2e 2248 goto out;
42b82dc1 2249 }
2250 break;
2251 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2252 if (index + 2 >= pa->size) {
fd112f2e 2253 netif_err(tp, ifup, tp->dev,
cecb5fd7 2254 "Out of range of firmware\n");
fd112f2e 2255 goto out;
42b82dc1 2256 }
2257 break;
2258 case PHY_COMP_EQ_SKIPN:
2259 case PHY_COMP_NEQ_SKIPN:
2260 case PHY_SKIPN:
1c361efb 2261 if (index + 1 + regno >= pa->size) {
fd112f2e 2262 netif_err(tp, ifup, tp->dev,
cecb5fd7 2263 "Out of range of firmware\n");
fd112f2e 2264 goto out;
42b82dc1 2265 }
bca03d5f 2266 break;
2267
42b82dc1 2268 default:
fd112f2e 2269 netif_err(tp, ifup, tp->dev,
42b82dc1 2270 "Invalid action 0x%08x\n", action);
fd112f2e 2271 goto out;
bca03d5f 2272 }
2273 }
fd112f2e
FR		 2274 rc = true;
2275out:
2276 return rc;
2277}
bca03d5f 2278
fd112f2e
FR		 2279static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2280{
2281 struct net_device *dev = tp->dev;
2282 int rc = -EINVAL;
2283
2284 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2285 netif_err(tp, ifup, dev, "invalid firwmare\n");
2286 goto out;
2287 }
2288
2289 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2290 rc = 0;
2291out:
2292 return rc;
2293}
2294
2295static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2296{
2297 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2298 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2299 u32 predata, count;
2300 size_t index;
2301
2302 predata = count = 0;
eee3786f 2303 org.write = ops->write;
2304 org.read = ops->read;
42b82dc1 2305
1c361efb
FR		 2306 for (index = 0; index < pa->size; ) {
2307 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2308 u32 data = action & 0x0000ffff;
42b82dc1 2309 u32 regno = (action & 0x0fff0000) >> 16;
2310
2311 if (!action)
2312 break;
bca03d5f 2313
2314 switch(action & 0xf0000000) {
42b82dc1 2315 case PHY_READ:
2316 predata = rtl_readphy(tp, regno);
2317 count++;
2318 index++;
2319 break;
2320 case PHY_DATA_OR:
2321 predata |= data;
2322 index++;
2323 break;
2324 case PHY_DATA_AND:
2325 predata &= data;
2326 index++;
2327 break;
2328 case PHY_BJMPN:
2329 index -= regno;
2330 break;
eee3786f 2331 case PHY_MDIO_CHG:
2332 if (data == 0) {
2333 ops->write = org.write;
2334 ops->read = org.read;
2335 } else if (data == 1) {
2336 ops->write = mac_mcu_write;
2337 ops->read = mac_mcu_read;
2338 }
2339
42b82dc1 2340 index++;
2341 break;
2342 case PHY_CLEAR_READCOUNT:
2343 count = 0;
2344 index++;
2345 break;
bca03d5f 2346 case PHY_WRITE:
42b82dc1 2347 rtl_writephy(tp, regno, data);
2348 index++;
2349 break;
2350 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2351 index += (count == data) ? 2 : 1;
bca03d5f 2352 break;
42b82dc1 2353 case PHY_COMP_EQ_SKIPN:
2354 if (predata == data)
2355 index += regno;
2356 index++;
2357 break;
2358 case PHY_COMP_NEQ_SKIPN:
2359 if (predata != data)
2360 index += regno;
2361 index++;
2362 break;
2363 case PHY_WRITE_PREVIOUS:
2364 rtl_writephy(tp, regno, predata);
2365 index++;
2366 break;
2367 case PHY_SKIPN:
2368 index += regno + 1;
2369 break;
2370 case PHY_DELAY_MS:
2371 mdelay(data);
2372 index++;
2373 break;
2374
bca03d5f 2375 default:
2376 BUG();
2377 }
2378 }
eee3786f 2379
2380 ops->write = org.write;
2381 ops->read = org.read;
bca03d5f 2382}
2383
f1e02ed1 2384static void rtl_release_firmware(struct rtl8169_private *tp)
2385{
b6ffd97f
FR		 2386 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2387 release_firmware(tp->rtl_fw->fw);
2388 kfree(tp->rtl_fw);
2389 }
2390 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2391}
2392
953a12cc 2393static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2394{
b6ffd97f 2395 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2396
2397 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2398 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2399 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2400}
2401
2402static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2403{
2404 if (rtl_readphy(tp, reg) != val)
2405 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2406 else
2407 rtl_apply_firmware(tp);
f1e02ed1 2408}
2409
4da19633 2410static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2411{
350f7596 2412 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2413 { 0x1f, 0x0001 },
2414 { 0x06, 0x006e },
2415 { 0x08, 0x0708 },
2416 { 0x15, 0x4000 },
2417 { 0x18, 0x65c7 },
1da177e4 2418
0b9b571d 2419 { 0x1f, 0x0001 },
2420 { 0x03, 0x00a1 },
2421 { 0x02, 0x0008 },
2422 { 0x01, 0x0120 },
2423 { 0x00, 0x1000 },
2424 { 0x04, 0x0800 },
2425 { 0x04, 0x0000 },
1da177e4 2426
0b9b571d 2427 { 0x03, 0xff41 },
2428 { 0x02, 0xdf60 },
2429 { 0x01, 0x0140 },
2430 { 0x00, 0x0077 },
2431 { 0x04, 0x7800 },
2432 { 0x04, 0x7000 },
2433
2434 { 0x03, 0x802f },
2435 { 0x02, 0x4f02 },
2436 { 0x01, 0x0409 },
2437 { 0x00, 0xf0f9 },
2438 { 0x04, 0x9800 },
2439 { 0x04, 0x9000 },
2440
2441 { 0x03, 0xdf01 },
2442 { 0x02, 0xdf20 },
2443 { 0x01, 0xff95 },
2444 { 0x00, 0xba00 },
2445 { 0x04, 0xa800 },
2446 { 0x04, 0xa000 },
2447
2448 { 0x03, 0xff41 },
2449 { 0x02, 0xdf20 },
2450 { 0x01, 0x0140 },
2451 { 0x00, 0x00bb },
2452 { 0x04, 0xb800 },
2453 { 0x04, 0xb000 },
2454
2455 { 0x03, 0xdf41 },
2456 { 0x02, 0xdc60 },
2457 { 0x01, 0x6340 },
2458 { 0x00, 0x007d },
2459 { 0x04, 0xd800 },
2460 { 0x04, 0xd000 },
2461
2462 { 0x03, 0xdf01 },
2463 { 0x02, 0xdf20 },
2464 { 0x01, 0x100a },
2465 { 0x00, 0xa0ff },
2466 { 0x04, 0xf800 },
2467 { 0x04, 0xf000 },
2468
2469 { 0x1f, 0x0000 },
2470 { 0x0b, 0x0000 },
2471 { 0x00, 0x9200 }
2472 };
1da177e4 2473
4da19633 2474 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2475}
2476
4da19633 2477static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2478{
350f7596 2479 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2480 { 0x1f, 0x0002 },
2481 { 0x01, 0x90d0 },
2482 { 0x1f, 0x0000 }
2483 };
2484
4da19633 2485 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2486}
2487
4da19633 2488static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2489{
2490 struct pci_dev *pdev = tp->pci_dev;
2e955856 2491
ccbae55e
SS		 2492 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2493 (pdev->subsystem_device != 0xe000))
2e955856 2494 return;
2495
4da19633 2496 rtl_writephy(tp, 0x1f, 0x0001);
2497 rtl_writephy(tp, 0x10, 0xf01b);
2498 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2499}
2500
4da19633 2501static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2502{
350f7596 2503 static const struct phy_reg phy_reg_init[] = {
2e955856 2504 { 0x1f, 0x0001 },
2505 { 0x04, 0x0000 },
2506 { 0x03, 0x00a1 },
2507 { 0x02, 0x0008 },
2508 { 0x01, 0x0120 },
2509 { 0x00, 0x1000 },
2510 { 0x04, 0x0800 },
2511 { 0x04, 0x9000 },
2512 { 0x03, 0x802f },
2513 { 0x02, 0x4f02 },
2514 { 0x01, 0x0409 },
2515 { 0x00, 0xf099 },
2516 { 0x04, 0x9800 },
2517 { 0x04, 0xa000 },
2518 { 0x03, 0xdf01 },
2519 { 0x02, 0xdf20 },
2520 { 0x01, 0xff95 },
2521 { 0x00, 0xba00 },
2522 { 0x04, 0xa800 },
2523 { 0x04, 0xf000 },
2524 { 0x03, 0xdf01 },
2525 { 0x02, 0xdf20 },
2526 { 0x01, 0x101a },
2527 { 0x00, 0xa0ff },
2528 { 0x04, 0xf800 },
2529 { 0x04, 0x0000 },
2530 { 0x1f, 0x0000 },
2531
2532 { 0x1f, 0x0001 },
2533 { 0x10, 0xf41b },
2534 { 0x14, 0xfb54 },
2535 { 0x18, 0xf5c7 },
2536 { 0x1f, 0x0000 },
2537
2538 { 0x1f, 0x0001 },
2539 { 0x17, 0x0cc0 },
2540 { 0x1f, 0x0000 }
2541 };
2542
4da19633 2543 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2544
4da19633 2545 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2546}
2547
4da19633 2548static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2549{
350f7596 2550 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2551 { 0x1f, 0x0001 },
2552 { 0x04, 0x0000 },
2553 { 0x03, 0x00a1 },
2554 { 0x02, 0x0008 },
2555 { 0x01, 0x0120 },
2556 { 0x00, 0x1000 },
2557 { 0x04, 0x0800 },
2558 { 0x04, 0x9000 },
2559 { 0x03, 0x802f },
2560 { 0x02, 0x4f02 },
2561 { 0x01, 0x0409 },
2562 { 0x00, 0xf099 },
2563 { 0x04, 0x9800 },
2564 { 0x04, 0xa000 },
2565 { 0x03, 0xdf01 },
2566 { 0x02, 0xdf20 },
2567 { 0x01, 0xff95 },
2568 { 0x00, 0xba00 },
2569 { 0x04, 0xa800 },
2570 { 0x04, 0xf000 },
2571 { 0x03, 0xdf01 },
2572 { 0x02, 0xdf20 },
2573 { 0x01, 0x101a },
2574 { 0x00, 0xa0ff },
2575 { 0x04, 0xf800 },
2576 { 0x04, 0x0000 },
2577 { 0x1f, 0x0000 },
2578
2579 { 0x1f, 0x0001 },
2580 { 0x0b, 0x8480 },
2581 { 0x1f, 0x0000 },
2582
2583 { 0x1f, 0x0001 },
2584 { 0x18, 0x67c7 },
2585 { 0x04, 0x2000 },
2586 { 0x03, 0x002f },
2587 { 0x02, 0x4360 },
2588 { 0x01, 0x0109 },
2589 { 0x00, 0x3022 },
2590 { 0x04, 0x2800 },
2591 { 0x1f, 0x0000 },
2592
2593 { 0x1f, 0x0001 },
2594 { 0x17, 0x0cc0 },
2595 { 0x1f, 0x0000 }
2596 };
2597
4da19633 2598 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2599}
2600
4da19633 2601static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2602{
350f7596 2603 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2604 { 0x10, 0xf41b },
2605 { 0x1f, 0x0000 }
2606 };
2607
4da19633 2608 rtl_writephy(tp, 0x1f, 0x0001);
2609 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2610
4da19633 2611 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2612}
2613
4da19633 2614static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2615{
350f7596 2616 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2617 { 0x1f, 0x0001 },
2618 { 0x10, 0xf41b },
2619 { 0x1f, 0x0000 }
2620 };
2621
4da19633 2622 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2623}
2624
4da19633 2625static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2626{
350f7596 2627 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2628 { 0x1f, 0x0000 },
2629 { 0x1d, 0x0f00 },
2630 { 0x1f, 0x0002 },
2631 { 0x0c, 0x1ec8 },
2632 { 0x1f, 0x0000 }
2633 };
2634
4da19633 2635 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2636}
2637
4da19633 2638static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2639{
350f7596 2640 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2641 { 0x1f, 0x0001 },
2642 { 0x1d, 0x3d98 },
2643 { 0x1f, 0x0000 }
2644 };
2645
4da19633 2646 rtl_writephy(tp, 0x1f, 0x0000);
2647 rtl_patchphy(tp, 0x14, 1 << 5);
2648 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2649
4da19633 2650 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2651}
2652
4da19633 2653static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2654{
350f7596 2655 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2656 { 0x1f, 0x0001 },
2657 { 0x12, 0x2300 },
867763c1
FR		 2658 { 0x1f, 0x0002 },
2659 { 0x00, 0x88d4 },
2660 { 0x01, 0x82b1 },
2661 { 0x03, 0x7002 },
2662 { 0x08, 0x9e30 },
2663 { 0x09, 0x01f0 },
2664 { 0x0a, 0x5500 },
2665 { 0x0c, 0x00c8 },
2666 { 0x1f, 0x0003 },
2667 { 0x12, 0xc096 },
2668 { 0x16, 0x000a },
f50d4275
FR		 2669 { 0x1f, 0x0000 },
2670 { 0x1f, 0x0000 },
2671 { 0x09, 0x2000 },
2672 { 0x09, 0x0000 }
867763c1
FR		 2673 };
2674
4da19633 2675 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2676
4da19633 2677 rtl_patchphy(tp, 0x14, 1 << 5);
2678 rtl_patchphy(tp, 0x0d, 1 << 5);
2679 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2680}
2681
4da19633 2682static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2683{
350f7596 2684 static const struct phy_reg phy_reg_init[] = {
f50d4275 2685 { 0x1f, 0x0001 },
7da97ec9 2686 { 0x12, 0x2300 },
f50d4275
FR		 2687 { 0x03, 0x802f },
2688 { 0x02, 0x4f02 },
2689 { 0x01, 0x0409 },
2690 { 0x00, 0xf099 },
2691 { 0x04, 0x9800 },
2692 { 0x04, 0x9000 },
2693 { 0x1d, 0x3d98 },
7da97ec9
FR		 2694 { 0x1f, 0x0002 },
2695 { 0x0c, 0x7eb8 },
f50d4275
FR		 2696 { 0x06, 0x0761 },
2697 { 0x1f, 0x0003 },
2698 { 0x16, 0x0f0a },
7da97ec9
FR		 2699 { 0x1f, 0x0000 }
2700 };
2701
4da19633 2702 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2703
4da19633 2704 rtl_patchphy(tp, 0x16, 1 << 0);
2705 rtl_patchphy(tp, 0x14, 1 << 5);
2706 rtl_patchphy(tp, 0x0d, 1 << 5);
2707 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2708}
2709
4da19633 2710static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2711{
350f7596 2712 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2713 { 0x1f, 0x0001 },
2714 { 0x12, 0x2300 },
2715 { 0x1d, 0x3d98 },
2716 { 0x1f, 0x0002 },
2717 { 0x0c, 0x7eb8 },
2718 { 0x06, 0x5461 },
2719 { 0x1f, 0x0003 },
2720 { 0x16, 0x0f0a },
2721 { 0x1f, 0x0000 }
2722 };
2723
4da19633 2724 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2725
4da19633 2726 rtl_patchphy(tp, 0x16, 1 << 0);
2727 rtl_patchphy(tp, 0x14, 1 << 5);
2728 rtl_patchphy(tp, 0x0d, 1 << 5);
2729 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2730}
2731
4da19633 2732static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2733{
4da19633 2734 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2735}
2736
bca03d5f 2737static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2738{
350f7596 2739 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2740 /* Channel Estimation */
5b538df9 2741 { 0x1f, 0x0001 },
daf9df6d 2742 { 0x06, 0x4064 },
2743 { 0x07, 0x2863 },
2744 { 0x08, 0x059c },
2745 { 0x09, 0x26b4 },
2746 { 0x0a, 0x6a19 },
2747 { 0x0b, 0xdcc8 },
2748 { 0x10, 0xf06d },
2749 { 0x14, 0x7f68 },
2750 { 0x18, 0x7fd9 },
2751 { 0x1c, 0xf0ff },
2752 { 0x1d, 0x3d9c },
5b538df9 2753 { 0x1f, 0x0003 },
daf9df6d 2754 { 0x12, 0xf49f },
2755 { 0x13, 0x070b },
2756 { 0x1a, 0x05ad },
bca03d5f 2757 { 0x14, 0x94c0 },
2758
2759 /*
2760 * Tx Error Issue
cecb5fd7 2761 * Enhance line driver power
bca03d5f 2762 */
5b538df9 2763 { 0x1f, 0x0002 },
daf9df6d 2764 { 0x06, 0x5561 },
2765 { 0x1f, 0x0005 },
2766 { 0x05, 0x8332 },
bca03d5f 2767 { 0x06, 0x5561 },
2768
2769 /*
2770 * Can not link to 1Gbps with bad cable
2771 * Decrease SNR threshold form 21.07dB to 19.04dB
2772 */
2773 { 0x1f, 0x0001 },
2774 { 0x17, 0x0cc0 },
daf9df6d 2775
5b538df9 2776 { 0x1f, 0x0000 },
bca03d5f 2777 { 0x0d, 0xf880 }
daf9df6d 2778 };
2779
4da19633 2780 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2781
bca03d5f 2782 /*
2783 * Rx Error Issue
2784 * Fine Tune Switching regulator parameter
2785 */
4da19633 2786 rtl_writephy(tp, 0x1f, 0x0002);
2787 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2788 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2789
fdf6fc06 2790 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2791 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2792 { 0x1f, 0x0002 },
2793 { 0x05, 0x669a },
2794 { 0x1f, 0x0005 },
2795 { 0x05, 0x8330 },
2796 { 0x06, 0x669a },
2797 { 0x1f, 0x0002 }
2798 };
2799 int val;
2800
4da19633 2801 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2802
4da19633 2803 val = rtl_readphy(tp, 0x0d);
daf9df6d 2804
2805 if ((val & 0x00ff) != 0x006c) {
350f7596 2806 static const u32 set[] = {
daf9df6d 2807 0x0065, 0x0066, 0x0067, 0x0068,
2808 0x0069, 0x006a, 0x006b, 0x006c
2809 };
2810 int i;
2811
4da19633 2812 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2813
2814 val &= 0xff00;
2815 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2816 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2817 }
2818 } else {
350f7596 2819 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2820 { 0x1f, 0x0002 },
2821 { 0x05, 0x6662 },
2822 { 0x1f, 0x0005 },
2823 { 0x05, 0x8330 },
2824 { 0x06, 0x6662 }
2825 };
2826
4da19633 2827 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2828 }
2829
bca03d5f 2830 /* RSET couple improve */
4da19633 2831 rtl_writephy(tp, 0x1f, 0x0002);
2832 rtl_patchphy(tp, 0x0d, 0x0300);
2833 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2834
bca03d5f 2835 /* Fine tune PLL performance */
4da19633 2836 rtl_writephy(tp, 0x1f, 0x0002);
2837 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2838 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2839
4da19633 2840 rtl_writephy(tp, 0x1f, 0x0005);
2841 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2842
2843 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2844
4da19633 2845 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2846}
2847
bca03d5f 2848static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2849{
350f7596 2850 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2851 /* Channel Estimation */
daf9df6d 2852 { 0x1f, 0x0001 },
2853 { 0x06, 0x4064 },
2854 { 0x07, 0x2863 },
2855 { 0x08, 0x059c },
2856 { 0x09, 0x26b4 },
2857 { 0x0a, 0x6a19 },
2858 { 0x0b, 0xdcc8 },
2859 { 0x10, 0xf06d },
2860 { 0x14, 0x7f68 },
2861 { 0x18, 0x7fd9 },
2862 { 0x1c, 0xf0ff },
2863 { 0x1d, 0x3d9c },
2864 { 0x1f, 0x0003 },
2865 { 0x12, 0xf49f },
2866 { 0x13, 0x070b },
2867 { 0x1a, 0x05ad },
2868 { 0x14, 0x94c0 },
2869
bca03d5f 2870 /*
2871 * Tx Error Issue
cecb5fd7 2872 * Enhance line driver power
bca03d5f 2873 */
daf9df6d 2874 { 0x1f, 0x0002 },
2875 { 0x06, 0x5561 },
2876 { 0x1f, 0x0005 },
2877 { 0x05, 0x8332 },
bca03d5f 2878 { 0x06, 0x5561 },
2879
2880 /*
2881 * Can not link to 1Gbps with bad cable
2882 * Decrease SNR threshold form 21.07dB to 19.04dB
2883 */
2884 { 0x1f, 0x0001 },
2885 { 0x17, 0x0cc0 },
daf9df6d 2886
2887 { 0x1f, 0x0000 },
bca03d5f 2888 { 0x0d, 0xf880 }
5b538df9
FR		 2889 };
2890
4da19633 2891 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2892
fdf6fc06 2893 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2894 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2895 { 0x1f, 0x0002 },
2896 { 0x05, 0x669a },
5b538df9 2897 { 0x1f, 0x0005 },
daf9df6d 2898 { 0x05, 0x8330 },
2899 { 0x06, 0x669a },
2900
2901 { 0x1f, 0x0002 }
2902 };
2903 int val;
2904
4da19633 2905 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2906
4da19633 2907 val = rtl_readphy(tp, 0x0d);
daf9df6d 2908 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2909 static const u32 set[] = {
daf9df6d 2910 0x0065, 0x0066, 0x0067, 0x0068,
2911 0x0069, 0x006a, 0x006b, 0x006c
2912 };
2913 int i;
2914
4da19633 2915 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2916
2917 val &= 0xff00;
2918 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2919 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2920 }
2921 } else {
350f7596 2922 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2923 { 0x1f, 0x0002 },
2924 { 0x05, 0x2642 },
5b538df9 2925 { 0x1f, 0x0005 },
daf9df6d 2926 { 0x05, 0x8330 },
2927 { 0x06, 0x2642 }
5b538df9
FR		 2928 };
2929
4da19633 2930 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2931 }
2932
bca03d5f 2933 /* Fine tune PLL performance */
4da19633 2934 rtl_writephy(tp, 0x1f, 0x0002);
2935 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2936 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2937
bca03d5f 2938 /* Switching regulator Slew rate */
4da19633 2939 rtl_writephy(tp, 0x1f, 0x0002);
2940 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2941
4da19633 2942 rtl_writephy(tp, 0x1f, 0x0005);
2943 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2944
2945 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2946
4da19633 2947 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2948}
2949
4da19633 2950static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2951{
350f7596 2952 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2953 { 0x1f, 0x0002 },
2954 { 0x10, 0x0008 },
2955 { 0x0d, 0x006c },
2956
2957 { 0x1f, 0x0000 },
2958 { 0x0d, 0xf880 },
2959
2960 { 0x1f, 0x0001 },
2961 { 0x17, 0x0cc0 },
2962
2963 { 0x1f, 0x0001 },
2964 { 0x0b, 0xa4d8 },
2965 { 0x09, 0x281c },
2966 { 0x07, 0x2883 },
2967 { 0x0a, 0x6b35 },
2968 { 0x1d, 0x3da4 },
2969 { 0x1c, 0xeffd },
2970 { 0x14, 0x7f52 },
2971 { 0x18, 0x7fc6 },
2972 { 0x08, 0x0601 },
2973 { 0x06, 0x4063 },
2974 { 0x10, 0xf074 },
2975 { 0x1f, 0x0003 },
2976 { 0x13, 0x0789 },
2977 { 0x12, 0xf4bd },
2978 { 0x1a, 0x04fd },
2979 { 0x14, 0x84b0 },
2980 { 0x1f, 0x0000 },
2981 { 0x00, 0x9200 },
2982
2983 { 0x1f, 0x0005 },
2984 { 0x01, 0x0340 },
2985 { 0x1f, 0x0001 },
2986 { 0x04, 0x4000 },
2987 { 0x03, 0x1d21 },
2988 { 0x02, 0x0c32 },
2989 { 0x01, 0x0200 },
2990 { 0x00, 0x5554 },
2991 { 0x04, 0x4800 },
2992 { 0x04, 0x4000 },
2993 { 0x04, 0xf000 },
2994 { 0x03, 0xdf01 },
2995 { 0x02, 0xdf20 },
2996 { 0x01, 0x101a },
2997 { 0x00, 0xa0ff },
2998 { 0x04, 0xf800 },
2999 { 0x04, 0xf000 },
3000 { 0x1f, 0x0000 },
3001
3002 { 0x1f, 0x0007 },
3003 { 0x1e, 0x0023 },
3004 { 0x16, 0x0000 },
3005 { 0x1f, 0x0000 }
3006 };
3007
4da19633 3008 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3009}
3010
e6de30d6 3011static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3012{
3013 static const struct phy_reg phy_reg_init[] = {
3014 { 0x1f, 0x0001 },
3015 { 0x17, 0x0cc0 },
3016
3017 { 0x1f, 0x0007 },
3018 { 0x1e, 0x002d },
3019 { 0x18, 0x0040 },
3020 { 0x1f, 0x0000 }
3021 };
3022
3023 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3024 rtl_patchphy(tp, 0x0d, 1 << 5);
3025}
3026
70090424 3027static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3028{
3029 static const struct phy_reg phy_reg_init[] = {
3030 /* Enable Delay cap */
3031 { 0x1f, 0x0005 },
3032 { 0x05, 0x8b80 },
3033 { 0x06, 0xc896 },
3034 { 0x1f, 0x0000 },
3035
3036 /* Channel estimation fine tune */
3037 { 0x1f, 0x0001 },
3038 { 0x0b, 0x6c20 },
3039 { 0x07, 0x2872 },
3040 { 0x1c, 0xefff },
3041 { 0x1f, 0x0003 },
3042 { 0x14, 0x6420 },
3043 { 0x1f, 0x0000 },
3044
3045 /* Update PFM & 10M TX idle timer */
3046 { 0x1f, 0x0007 },
3047 { 0x1e, 0x002f },
3048 { 0x15, 0x1919 },
3049 { 0x1f, 0x0000 },
3050
3051 { 0x1f, 0x0007 },
3052 { 0x1e, 0x00ac },
3053 { 0x18, 0x0006 },
3054 { 0x1f, 0x0000 }
3055 };
3056
15ecd039
FR		 3057 rtl_apply_firmware(tp);
3058
01dc7fec 3059 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3060
3061 /* DCO enable for 10M IDLE Power */
3062 rtl_writephy(tp, 0x1f, 0x0007);
3063 rtl_writephy(tp, 0x1e, 0x0023);
3064 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3065 rtl_writephy(tp, 0x1f, 0x0000);
3066
3067 /* For impedance matching */
3068 rtl_writephy(tp, 0x1f, 0x0002);
3069 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3070 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3071
3072 /* PHY auto speed down */
3073 rtl_writephy(tp, 0x1f, 0x0007);
3074 rtl_writephy(tp, 0x1e, 0x002d);
3075 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3076 rtl_writephy(tp, 0x1f, 0x0000);
3077 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3078
3079 rtl_writephy(tp, 0x1f, 0x0005);
3080 rtl_writephy(tp, 0x05, 0x8b86);
3081 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3082 rtl_writephy(tp, 0x1f, 0x0000);
3083
3084 rtl_writephy(tp, 0x1f, 0x0005);
3085 rtl_writephy(tp, 0x05, 0x8b85);
3086 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3087 rtl_writephy(tp, 0x1f, 0x0007);
3088 rtl_writephy(tp, 0x1e, 0x0020);
3089 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3090 rtl_writephy(tp, 0x1f, 0x0006);
3091 rtl_writephy(tp, 0x00, 0x5a00);
3092 rtl_writephy(tp, 0x1f, 0x0000);
3093 rtl_writephy(tp, 0x0d, 0x0007);
3094 rtl_writephy(tp, 0x0e, 0x003c);
3095 rtl_writephy(tp, 0x0d, 0x4007);
3096 rtl_writephy(tp, 0x0e, 0x0000);
3097 rtl_writephy(tp, 0x0d, 0x0000);
3098}
3099
9ecb9aab 3100static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3101{
3102 const u16 w[] = {
3103 addr[0] | (addr[1] << 8),
3104 addr[2] | (addr[3] << 8),
3105 addr[4] | (addr[5] << 8)
3106 };
3107 const struct exgmac_reg e[] = {
3108 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3109 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3110 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3111 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3112 };
3113
3114 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3115}
3116
70090424
HW		 3117static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3118{
3119 static const struct phy_reg phy_reg_init[] = {
3120 /* Enable Delay cap */
3121 { 0x1f, 0x0004 },
3122 { 0x1f, 0x0007 },
3123 { 0x1e, 0x00ac },
3124 { 0x18, 0x0006 },
3125 { 0x1f, 0x0002 },
3126 { 0x1f, 0x0000 },
3127 { 0x1f, 0x0000 },
3128
3129 /* Channel estimation fine tune */
3130 { 0x1f, 0x0003 },
3131 { 0x09, 0xa20f },
3132 { 0x1f, 0x0000 },
3133 { 0x1f, 0x0000 },
3134
3135 /* Green Setting */
3136 { 0x1f, 0x0005 },
3137 { 0x05, 0x8b5b },
3138 { 0x06, 0x9222 },
3139 { 0x05, 0x8b6d },
3140 { 0x06, 0x8000 },
3141 { 0x05, 0x8b76 },
3142 { 0x06, 0x8000 },
3143 { 0x1f, 0x0000 }
3144 };
3145
3146 rtl_apply_firmware(tp);
3147
3148 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3149
3150 /* For 4-corner performance improve */
3151 rtl_writephy(tp, 0x1f, 0x0005);
3152 rtl_writephy(tp, 0x05, 0x8b80);
3153 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3154 rtl_writephy(tp, 0x1f, 0x0000);
3155
3156 /* PHY auto speed down */
3157 rtl_writephy(tp, 0x1f, 0x0004);
3158 rtl_writephy(tp, 0x1f, 0x0007);
3159 rtl_writephy(tp, 0x1e, 0x002d);
3160 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3161 rtl_writephy(tp, 0x1f, 0x0002);
3162 rtl_writephy(tp, 0x1f, 0x0000);
3163 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3164
3165 /* improve 10M EEE waveform */
3166 rtl_writephy(tp, 0x1f, 0x0005);
3167 rtl_writephy(tp, 0x05, 0x8b86);
3168 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3169 rtl_writephy(tp, 0x1f, 0x0000);
3170
3171 /* Improve 2-pair detection performance */
3172 rtl_writephy(tp, 0x1f, 0x0005);
3173 rtl_writephy(tp, 0x05, 0x8b85);
3174 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3175 rtl_writephy(tp, 0x1f, 0x0000);
3176
3177 /* EEE setting */
fdf6fc06 3178 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3179 rtl_writephy(tp, 0x1f, 0x0005);
3180 rtl_writephy(tp, 0x05, 0x8b85);
3181 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3182 rtl_writephy(tp, 0x1f, 0x0004);
3183 rtl_writephy(tp, 0x1f, 0x0007);
3184 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3185 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3186 rtl_writephy(tp, 0x1f, 0x0002);
3187 rtl_writephy(tp, 0x1f, 0x0000);
3188 rtl_writephy(tp, 0x0d, 0x0007);
3189 rtl_writephy(tp, 0x0e, 0x003c);
3190 rtl_writephy(tp, 0x0d, 0x4007);
3191 rtl_writephy(tp, 0x0e, 0x0000);
3192 rtl_writephy(tp, 0x0d, 0x0000);
3193
3194 /* Green feature */
3195 rtl_writephy(tp, 0x1f, 0x0003);
3196 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3197 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3198 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3199
9ecb9aab 3200 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3201 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3202}
3203
5f886e08
HW		 3204static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3205{
3206 /* For 4-corner performance improve */
3207 rtl_writephy(tp, 0x1f, 0x0005);
3208 rtl_writephy(tp, 0x05, 0x8b80);
3209 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3210 rtl_writephy(tp, 0x1f, 0x0000);
3211
3212 /* PHY auto speed down */
3213 rtl_writephy(tp, 0x1f, 0x0007);
3214 rtl_writephy(tp, 0x1e, 0x002d);
3215 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3216 rtl_writephy(tp, 0x1f, 0x0000);
3217 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3218
3219 /* Improve 10M EEE waveform */
3220 rtl_writephy(tp, 0x1f, 0x0005);
3221 rtl_writephy(tp, 0x05, 0x8b86);
3222 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3223 rtl_writephy(tp, 0x1f, 0x0000);
3224}
3225
c2218925
HW		 3226static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3227{
3228 static const struct phy_reg phy_reg_init[] = {
3229 /* Channel estimation fine tune */
3230 { 0x1f, 0x0003 },
3231 { 0x09, 0xa20f },
3232 { 0x1f, 0x0000 },
3233
3234 /* Modify green table for giga & fnet */
3235 { 0x1f, 0x0005 },
3236 { 0x05, 0x8b55 },
3237 { 0x06, 0x0000 },
3238 { 0x05, 0x8b5e },
3239 { 0x06, 0x0000 },
3240 { 0x05, 0x8b67 },
3241 { 0x06, 0x0000 },
3242 { 0x05, 0x8b70 },
3243 { 0x06, 0x0000 },
3244 { 0x1f, 0x0000 },
3245 { 0x1f, 0x0007 },
3246 { 0x1e, 0x0078 },
3247 { 0x17, 0x0000 },
3248 { 0x19, 0x00fb },
3249 { 0x1f, 0x0000 },
3250
3251 /* Modify green table for 10M */
3252 { 0x1f, 0x0005 },
3253 { 0x05, 0x8b79 },
3254 { 0x06, 0xaa00 },
3255 { 0x1f, 0x0000 },
3256
3257 /* Disable hiimpedance detection (RTCT) */
3258 { 0x1f, 0x0003 },
3259 { 0x01, 0x328a },
3260 { 0x1f, 0x0000 }
3261 };
3262
3263 rtl_apply_firmware(tp);
3264
3265 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3266
5f886e08 3267 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3268
3269 /* Improve 2-pair detection performance */
3270 rtl_writephy(tp, 0x1f, 0x0005);
3271 rtl_writephy(tp, 0x05, 0x8b85);
3272 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3273 rtl_writephy(tp, 0x1f, 0x0000);
3274}
3275
3276static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3277{
3278 rtl_apply_firmware(tp);
3279
5f886e08 3280 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3281}
3282
b3d7b2f2
HW		 3283static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3284{
b3d7b2f2
HW		 3285 static const struct phy_reg phy_reg_init[] = {
3286 /* Channel estimation fine tune */
3287 { 0x1f, 0x0003 },
3288 { 0x09, 0xa20f },
3289 { 0x1f, 0x0000 },
3290
3291 /* Modify green table for giga & fnet */
3292 { 0x1f, 0x0005 },
3293 { 0x05, 0x8b55 },
3294 { 0x06, 0x0000 },
3295 { 0x05, 0x8b5e },
3296 { 0x06, 0x0000 },
3297 { 0x05, 0x8b67 },
3298 { 0x06, 0x0000 },
3299 { 0x05, 0x8b70 },
3300 { 0x06, 0x0000 },
3301 { 0x1f, 0x0000 },
3302 { 0x1f, 0x0007 },
3303 { 0x1e, 0x0078 },
3304 { 0x17, 0x0000 },
3305 { 0x19, 0x00aa },
3306 { 0x1f, 0x0000 },
3307
3308 /* Modify green table for 10M */
3309 { 0x1f, 0x0005 },
3310 { 0x05, 0x8b79 },
3311 { 0x06, 0xaa00 },
3312 { 0x1f, 0x0000 },
3313
3314 /* Disable hiimpedance detection (RTCT) */
3315 { 0x1f, 0x0003 },
3316 { 0x01, 0x328a },
3317 { 0x1f, 0x0000 }
3318 };
3319
3320
3321 rtl_apply_firmware(tp);
3322
3323 rtl8168f_hw_phy_config(tp);
3324
3325 /* Improve 2-pair detection performance */
3326 rtl_writephy(tp, 0x1f, 0x0005);
3327 rtl_writephy(tp, 0x05, 0x8b85);
3328 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3329 rtl_writephy(tp, 0x1f, 0x0000);
3330
3331 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3332
3333 /* Modify green table for giga */
3334 rtl_writephy(tp, 0x1f, 0x0005);
3335 rtl_writephy(tp, 0x05, 0x8b54);
3336 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3337 rtl_writephy(tp, 0x05, 0x8b5d);
3338 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3339 rtl_writephy(tp, 0x05, 0x8a7c);
3340 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3341 rtl_writephy(tp, 0x05, 0x8a7f);
3342 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3343 rtl_writephy(tp, 0x05, 0x8a82);
3344 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3345 rtl_writephy(tp, 0x05, 0x8a85);
3346 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3347 rtl_writephy(tp, 0x05, 0x8a88);
3348 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3349 rtl_writephy(tp, 0x1f, 0x0000);
3350
3351 /* uc same-seed solution */
3352 rtl_writephy(tp, 0x1f, 0x0005);
3353 rtl_writephy(tp, 0x05, 0x8b85);
3354 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3355 rtl_writephy(tp, 0x1f, 0x0000);
3356
3357 /* eee setting */
fdf6fc06 3358 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3359 rtl_writephy(tp, 0x1f, 0x0005);
3360 rtl_writephy(tp, 0x05, 0x8b85);
3361 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3362 rtl_writephy(tp, 0x1f, 0x0004);
3363 rtl_writephy(tp, 0x1f, 0x0007);
3364 rtl_writephy(tp, 0x1e, 0x0020);
3365 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3366 rtl_writephy(tp, 0x1f, 0x0000);
3367 rtl_writephy(tp, 0x0d, 0x0007);
3368 rtl_writephy(tp, 0x0e, 0x003c);
3369 rtl_writephy(tp, 0x0d, 0x4007);
3370 rtl_writephy(tp, 0x0e, 0x0000);
3371 rtl_writephy(tp, 0x0d, 0x0000);
3372
3373 /* Green feature */
3374 rtl_writephy(tp, 0x1f, 0x0003);
3375 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3376 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3377 rtl_writephy(tp, 0x1f, 0x0000);
3378}
3379
c558386b
HW		 3380static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3381{
c558386b
HW		 3382 rtl_apply_firmware(tp);
3383
41f44d13 3384 rtl_writephy(tp, 0x1f, 0x0a46);
3385 if (rtl_readphy(tp, 0x10) & 0x0100) {
3386 rtl_writephy(tp, 0x1f, 0x0bcc);
3387 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3388 } else {
3389 rtl_writephy(tp, 0x1f, 0x0bcc);
3390 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3391 }
c558386b 3392
41f44d13 3393 rtl_writephy(tp, 0x1f, 0x0a46);
3394 if (rtl_readphy(tp, 0x13) & 0x0100) {
3395 rtl_writephy(tp, 0x1f, 0x0c41);
3396 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3397 } else {
fe7524c0 3398 rtl_writephy(tp, 0x1f, 0x0c41);
3399 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3400 }
c558386b 3401
41f44d13 3402 /* Enable PHY auto speed down */
3403 rtl_writephy(tp, 0x1f, 0x0a44);
3404 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3405
fe7524c0 3406 rtl_writephy(tp, 0x1f, 0x0bcc);
3407 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3408 rtl_writephy(tp, 0x1f, 0x0a44);
3409 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3410 rtl_writephy(tp, 0x1f, 0x0a43);
3411 rtl_writephy(tp, 0x13, 0x8084);
3412 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3413 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3414
41f44d13 3415 /* EEE auto-fallback function */
3416 rtl_writephy(tp, 0x1f, 0x0a4b);
3417 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3418
41f44d13 3419 /* Enable UC LPF tune function */
3420 rtl_writephy(tp, 0x1f, 0x0a43);
3421 rtl_writephy(tp, 0x13, 0x8012);
3422 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3423
3424 rtl_writephy(tp, 0x1f, 0x0c42);
3425 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3426
fe7524c0 3427 /* Improve SWR Efficiency */
3428 rtl_writephy(tp, 0x1f, 0x0bcd);
3429 rtl_writephy(tp, 0x14, 0x5065);
3430 rtl_writephy(tp, 0x14, 0xd065);
3431 rtl_writephy(tp, 0x1f, 0x0bc8);
3432 rtl_writephy(tp, 0x11, 0x5655);
3433 rtl_writephy(tp, 0x1f, 0x0bcd);
3434 rtl_writephy(tp, 0x14, 0x1065);
3435 rtl_writephy(tp, 0x14, 0x9065);
3436 rtl_writephy(tp, 0x14, 0x1065);
3437
41f44d13 3438 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3439}
3440
4da19633 3441static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3442{
350f7596 3443 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3444 { 0x1f, 0x0003 },
3445 { 0x08, 0x441d },
3446 { 0x01, 0x9100 },
3447 { 0x1f, 0x0000 }
3448 };
3449
4da19633 3450 rtl_writephy(tp, 0x1f, 0x0000);
3451 rtl_patchphy(tp, 0x11, 1 << 12);
3452 rtl_patchphy(tp, 0x19, 1 << 13);
3453 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3454
4da19633 3455 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3456}
3457
5a5e4443
HW		 3458static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3459{
3460 static const struct phy_reg phy_reg_init[] = {
3461 { 0x1f, 0x0005 },
3462 { 0x1a, 0x0000 },
3463 { 0x1f, 0x0000 },
3464
3465 { 0x1f, 0x0004 },
3466 { 0x1c, 0x0000 },
3467 { 0x1f, 0x0000 },
3468
3469 { 0x1f, 0x0001 },
3470 { 0x15, 0x7701 },
3471 { 0x1f, 0x0000 }
3472 };
3473
3474 /* Disable ALDPS before ram code */
eef63cc1
FR		 3475 rtl_writephy(tp, 0x1f, 0x0000);
3476 rtl_writephy(tp, 0x18, 0x0310);
3477 msleep(100);
5a5e4443 3478
953a12cc 3479 rtl_apply_firmware(tp);
5a5e4443
HW		 3480
3481 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3482}
3483
7e18dca1
HW		 3484static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3485{
7e18dca1 3486 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3487 rtl_writephy(tp, 0x1f, 0x0000);
3488 rtl_writephy(tp, 0x18, 0x0310);
3489 msleep(20);
7e18dca1
HW		 3490
3491 rtl_apply_firmware(tp);
3492
3493 /* EEE setting */
fdf6fc06 3494 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3495 rtl_writephy(tp, 0x1f, 0x0004);
3496 rtl_writephy(tp, 0x10, 0x401f);
3497 rtl_writephy(tp, 0x19, 0x7030);
3498 rtl_writephy(tp, 0x1f, 0x0000);
3499}
3500
5598bfe5
HW		 3501static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3502{
5598bfe5
HW		 3503 static const struct phy_reg phy_reg_init[] = {
3504 { 0x1f, 0x0004 },
3505 { 0x10, 0xc07f },
3506 { 0x19, 0x7030 },
3507 { 0x1f, 0x0000 }
3508 };
3509
3510 /* Disable ALDPS before ram code */
eef63cc1
FR		 3511 rtl_writephy(tp, 0x1f, 0x0000);
3512 rtl_writephy(tp, 0x18, 0x0310);
3513 msleep(100);
5598bfe5
HW		 3514
3515 rtl_apply_firmware(tp);
3516
fdf6fc06 3517 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3518 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3519
fdf6fc06 3520 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3521}
3522
5615d9f1
FR		 3523static void rtl_hw_phy_config(struct net_device *dev)
3524{
3525 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3526
3527 rtl8169_print_mac_version(tp);
3528
3529 switch (tp->mac_version) {
3530 case RTL_GIGA_MAC_VER_01:
3531 break;
3532 case RTL_GIGA_MAC_VER_02:
3533 case RTL_GIGA_MAC_VER_03:
4da19633 3534 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3535 break;
3536 case RTL_GIGA_MAC_VER_04:
4da19633 3537 rtl8169sb_hw_phy_config(tp);
5615d9f1 3538 break;
2e955856 3539 case RTL_GIGA_MAC_VER_05:
4da19633 3540 rtl8169scd_hw_phy_config(tp);
2e955856 3541 break;
8c7006aa 3542 case RTL_GIGA_MAC_VER_06:
4da19633 3543 rtl8169sce_hw_phy_config(tp);
8c7006aa 3544 break;
2857ffb7
FR		 3545 case RTL_GIGA_MAC_VER_07:
3546 case RTL_GIGA_MAC_VER_08:
3547 case RTL_GIGA_MAC_VER_09:
4da19633 3548 rtl8102e_hw_phy_config(tp);
2857ffb7 3549 break;
236b8082 3550 case RTL_GIGA_MAC_VER_11:
4da19633 3551 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3552 break;
3553 case RTL_GIGA_MAC_VER_12:
4da19633 3554 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3555 break;
3556 case RTL_GIGA_MAC_VER_17:
4da19633 3557 rtl8168bef_hw_phy_config(tp);
236b8082 3558 break;
867763c1 3559 case RTL_GIGA_MAC_VER_18:
4da19633 3560 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3561 break;
3562 case RTL_GIGA_MAC_VER_19:
4da19633 3563 rtl8168c_1_hw_phy_config(tp);
867763c1 3564 break;
7da97ec9 3565 case RTL_GIGA_MAC_VER_20:
4da19633 3566 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3567 break;
197ff761 3568 case RTL_GIGA_MAC_VER_21:
4da19633 3569 rtl8168c_3_hw_phy_config(tp);
197ff761 3570 break;
6fb07058 3571 case RTL_GIGA_MAC_VER_22:
4da19633 3572 rtl8168c_4_hw_phy_config(tp);
6fb07058 3573 break;
ef3386f0 3574 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3575 case RTL_GIGA_MAC_VER_24:
4da19633 3576 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3577 break;
5b538df9 3578 case RTL_GIGA_MAC_VER_25:
bca03d5f 3579 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3580 break;
3581 case RTL_GIGA_MAC_VER_26:
bca03d5f 3582 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3583 break;
3584 case RTL_GIGA_MAC_VER_27:
4da19633 3585 rtl8168d_3_hw_phy_config(tp);
5b538df9 3586 break;
e6de30d6 3587 case RTL_GIGA_MAC_VER_28:
3588 rtl8168d_4_hw_phy_config(tp);
3589 break;
5a5e4443
HW		 3590 case RTL_GIGA_MAC_VER_29:
3591 case RTL_GIGA_MAC_VER_30:
3592 rtl8105e_hw_phy_config(tp);
3593 break;
cecb5fd7
FR		 3594 case RTL_GIGA_MAC_VER_31:
3595 /* None. */
3596 break;
01dc7fec 3597 case RTL_GIGA_MAC_VER_32:
01dc7fec 3598 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3599 rtl8168e_1_hw_phy_config(tp);
3600 break;
3601 case RTL_GIGA_MAC_VER_34:
3602 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3603 break;
c2218925
HW		 3604 case RTL_GIGA_MAC_VER_35:
3605 rtl8168f_1_hw_phy_config(tp);
3606 break;
3607 case RTL_GIGA_MAC_VER_36:
3608 rtl8168f_2_hw_phy_config(tp);
3609 break;
ef3386f0 3610
7e18dca1
HW		 3611 case RTL_GIGA_MAC_VER_37:
3612 rtl8402_hw_phy_config(tp);
3613 break;
3614
b3d7b2f2
HW		 3615 case RTL_GIGA_MAC_VER_38:
3616 rtl8411_hw_phy_config(tp);
3617 break;
3618
5598bfe5
HW		 3619 case RTL_GIGA_MAC_VER_39:
3620 rtl8106e_hw_phy_config(tp);
3621 break;
3622
c558386b
HW		 3623 case RTL_GIGA_MAC_VER_40:
3624 rtl8168g_1_hw_phy_config(tp);
3625 break;
3626
3627 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3628 default:
3629 break;
3630 }
3631}
3632
da78dbff 3633static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3634{
1da177e4
LT		 3635 struct timer_list *timer = &tp->timer;
3636 void __iomem *ioaddr = tp->mmio_addr;
3637 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3638
bcf0bf90 3639 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3640
4da19633 3641 if (tp->phy_reset_pending(tp)) {
5b0384f4 3642 /*
1da177e4
LT		 3643 * A busy loop could burn quite a few cycles on nowadays CPU.
3644 * Let's delay the execution of the timer for a few ticks.
3645 */
3646 timeout = HZ/10;
3647 goto out_mod_timer;
3648 }
3649
3650 if (tp->link_ok(ioaddr))
da78dbff 3651 return;
1da177e4 3652
da78dbff 3653 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3654
4da19633 3655 tp->phy_reset_enable(tp);
1da177e4
LT		 3656
3657out_mod_timer:
3658 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3659}
3660
3661static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3662{
da78dbff
FR		 3663 if (!test_and_set_bit(flag, tp->wk.flags))
3664 schedule_work(&tp->wk.work);
da78dbff
FR		 3665}
3666
3667static void rtl8169_phy_timer(unsigned long __opaque)
3668{
3669 struct net_device *dev = (struct net_device *)__opaque;
3670 struct rtl8169_private *tp = netdev_priv(dev);
3671
98ddf986 3672 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3673}
3674
1da177e4
LT		 3675static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3676 void __iomem *ioaddr)
3677{
3678 iounmap(ioaddr);
3679 pci_release_regions(pdev);
87aeec76 3680 pci_clear_mwi(pdev);
1da177e4
LT		 3681 pci_disable_device(pdev);
3682 free_netdev(dev);
3683}
3684
ffc46952
FR		 3685DECLARE_RTL_COND(rtl_phy_reset_cond)
3686{
3687 return tp->phy_reset_pending(tp);
3688}
3689
bf793295
FR		 3690static void rtl8169_phy_reset(struct net_device *dev,
3691 struct rtl8169_private *tp)
3692{
4da19633 3693 tp->phy_reset_enable(tp);
ffc46952 3694 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3695}
3696
2544bfc0
FR		 3697static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3698{
3699 void __iomem *ioaddr = tp->mmio_addr;
3700
3701 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3702 (RTL_R8(PHYstatus) & TBI_Enable);
3703}
3704
4ff96fa6
FR		 3705static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3706{
3707 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3708
5615d9f1 3709 rtl_hw_phy_config(dev);
4ff96fa6 3710
77332894
MS		 3711 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3712 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3713 RTL_W8(0x82, 0x01);
3714 }
4ff96fa6 3715
6dccd16b
FR		 3716 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3717
3718 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3719 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3720
bcf0bf90 3721 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3722 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3723 RTL_W8(0x82, 0x01);
3724 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3725 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3726 }
3727
bf793295
FR		 3728 rtl8169_phy_reset(dev, tp);
3729
54405cde 3730 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3731 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3732 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3733 (tp->mii.supports_gmii ?
3734 ADVERTISED_1000baseT_Half |
3735 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3736
2544bfc0 3737 if (rtl_tbi_enabled(tp))
bf82c189 3738 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3739}
3740
773d2021
FR		 3741static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3742{
3743 void __iomem *ioaddr = tp->mmio_addr;
773d2021 3744
da78dbff 3745 rtl_lock_work(tp);
773d2021
FR		 3746
3747 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3748
9ecb9aab 3749 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 3750 RTL_R32(MAC4);
3751
9ecb9aab 3752 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 3753 RTL_R32(MAC0);
3754
9ecb9aab 3755 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3756 rtl_rar_exgmac_set(tp, addr);
c28aa385 3757
773d2021
FR		 3758 RTL_W8(Cfg9346, Cfg9346_Lock);
3759
da78dbff 3760 rtl_unlock_work(tp);
773d2021
FR		 3761}
3762
3763static int rtl_set_mac_address(struct net_device *dev, void *p)
3764{
3765 struct rtl8169_private *tp = netdev_priv(dev);
3766 struct sockaddr *addr = p;
3767
3768 if (!is_valid_ether_addr(addr->sa_data))
3769 return -EADDRNOTAVAIL;
3770
3771 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3772
3773 rtl_rar_set(tp, dev->dev_addr);
3774
3775 return 0;
3776}
3777
5f787a1a
FR		 3778static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3779{
3780 struct rtl8169_private *tp = netdev_priv(dev);
3781 struct mii_ioctl_data *data = if_mii(ifr);
3782
8b4ab28d
FR		 3783 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3784}
5f787a1a 3785
cecb5fd7
FR		 3786static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3787 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3788{
5f787a1a
FR		 3789 switch (cmd) {
3790 case SIOCGMIIPHY:
3791 data->phy_id = 32; /* Internal PHY */
3792 return 0;
3793
3794 case SIOCGMIIREG:
4da19633 3795 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3796 return 0;
3797
3798 case SIOCSMIIREG:
4da19633 3799 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3800 return 0;
3801 }
3802 return -EOPNOTSUPP;
3803}
3804
8b4ab28d
FR		 3805static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3806{
3807 return -EOPNOTSUPP;
3808}
3809
fbac58fc
FR		 3810static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3811{
3812 if (tp->features & RTL_FEATURE_MSI) {
3813 pci_disable_msi(pdev);
3814 tp->features &= ~RTL_FEATURE_MSI;
3815 }
3816}
3817
baf63293 3818static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 3819{
3820 struct mdio_ops *ops = &tp->mdio_ops;
3821
3822 switch (tp->mac_version) {
3823 case RTL_GIGA_MAC_VER_27:
3824 ops->write = r8168dp_1_mdio_write;
3825 ops->read = r8168dp_1_mdio_read;
3826 break;
e6de30d6 3827 case RTL_GIGA_MAC_VER_28:
4804b3b3 3828 case RTL_GIGA_MAC_VER_31:
e6de30d6 3829 ops->write = r8168dp_2_mdio_write;
3830 ops->read = r8168dp_2_mdio_read;
3831 break;
c558386b
HW		 3832 case RTL_GIGA_MAC_VER_40:
3833 case RTL_GIGA_MAC_VER_41:
3834 ops->write = r8168g_mdio_write;
3835 ops->read = r8168g_mdio_read;
3836 break;
c0e45c1c 3837 default:
3838 ops->write = r8169_mdio_write;
3839 ops->read = r8169_mdio_read;
3840 break;
3841 }
3842}
3843
649b3b8c 3844static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3845{
3846 void __iomem *ioaddr = tp->mmio_addr;
3847
3848 switch (tp->mac_version) {
b00e69de
CB		 3849 case RTL_GIGA_MAC_VER_25:
3850 case RTL_GIGA_MAC_VER_26:
649b3b8c 3851 case RTL_GIGA_MAC_VER_29:
3852 case RTL_GIGA_MAC_VER_30:
3853 case RTL_GIGA_MAC_VER_32:
3854 case RTL_GIGA_MAC_VER_33:
3855 case RTL_GIGA_MAC_VER_34:
7e18dca1 3856 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3857 case RTL_GIGA_MAC_VER_38:
5598bfe5 3858 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3859 case RTL_GIGA_MAC_VER_40:
3860 case RTL_GIGA_MAC_VER_41:
649b3b8c 3861 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3862 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3863 break;
3864 default:
3865 break;
3866 }
3867}
3868
3869static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3870{
3871 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3872 return false;
3873
3874 rtl_writephy(tp, 0x1f, 0x0000);
3875 rtl_writephy(tp, MII_BMCR, 0x0000);
3876
3877 rtl_wol_suspend_quirk(tp);
3878
3879 return true;
3880}
3881
065c27c1 3882static void r810x_phy_power_down(struct rtl8169_private *tp)
3883{
3884 rtl_writephy(tp, 0x1f, 0x0000);
3885 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3886}
3887
3888static void r810x_phy_power_up(struct rtl8169_private *tp)
3889{
3890 rtl_writephy(tp, 0x1f, 0x0000);
3891 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3892}
3893
3894static void r810x_pll_power_down(struct rtl8169_private *tp)
3895{
0004299a
HW		 3896 void __iomem *ioaddr = tp->mmio_addr;
3897
649b3b8c 3898 if (rtl_wol_pll_power_down(tp))
065c27c1 3899 return;
065c27c1 3900
3901 r810x_phy_power_down(tp);
0004299a
HW		 3902
3903 switch (tp->mac_version) {
3904 case RTL_GIGA_MAC_VER_07:
3905 case RTL_GIGA_MAC_VER_08:
3906 case RTL_GIGA_MAC_VER_09:
3907 case RTL_GIGA_MAC_VER_10:
3908 case RTL_GIGA_MAC_VER_13:
3909 case RTL_GIGA_MAC_VER_16:
3910 break;
3911 default:
3912 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3913 break;
3914 }
065c27c1 3915}
3916
3917static void r810x_pll_power_up(struct rtl8169_private *tp)
3918{
0004299a
HW		 3919 void __iomem *ioaddr = tp->mmio_addr;
3920
065c27c1 3921 r810x_phy_power_up(tp);
0004299a
HW		 3922
3923 switch (tp->mac_version) {
3924 case RTL_GIGA_MAC_VER_07:
3925 case RTL_GIGA_MAC_VER_08:
3926 case RTL_GIGA_MAC_VER_09:
3927 case RTL_GIGA_MAC_VER_10:
3928 case RTL_GIGA_MAC_VER_13:
3929 case RTL_GIGA_MAC_VER_16:
3930 break;
3931 default:
3932 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3933 break;
3934 }
065c27c1 3935}
3936
3937static void r8168_phy_power_up(struct rtl8169_private *tp)
3938{
3939 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3940 switch (tp->mac_version) {
3941 case RTL_GIGA_MAC_VER_11:
3942 case RTL_GIGA_MAC_VER_12:
3943 case RTL_GIGA_MAC_VER_17:
3944 case RTL_GIGA_MAC_VER_18:
3945 case RTL_GIGA_MAC_VER_19:
3946 case RTL_GIGA_MAC_VER_20:
3947 case RTL_GIGA_MAC_VER_21:
3948 case RTL_GIGA_MAC_VER_22:
3949 case RTL_GIGA_MAC_VER_23:
3950 case RTL_GIGA_MAC_VER_24:
3951 case RTL_GIGA_MAC_VER_25:
3952 case RTL_GIGA_MAC_VER_26:
3953 case RTL_GIGA_MAC_VER_27:
3954 case RTL_GIGA_MAC_VER_28:
3955 case RTL_GIGA_MAC_VER_31:
3956 rtl_writephy(tp, 0x0e, 0x0000);
3957 break;
3958 default:
3959 break;
3960 }
065c27c1 3961 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3962}
3963
3964static void r8168_phy_power_down(struct rtl8169_private *tp)
3965{
3966 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3967 switch (tp->mac_version) {
3968 case RTL_GIGA_MAC_VER_32:
3969 case RTL_GIGA_MAC_VER_33:
3970 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3971 break;
3972
3973 case RTL_GIGA_MAC_VER_11:
3974 case RTL_GIGA_MAC_VER_12:
3975 case RTL_GIGA_MAC_VER_17:
3976 case RTL_GIGA_MAC_VER_18:
3977 case RTL_GIGA_MAC_VER_19:
3978 case RTL_GIGA_MAC_VER_20:
3979 case RTL_GIGA_MAC_VER_21:
3980 case RTL_GIGA_MAC_VER_22:
3981 case RTL_GIGA_MAC_VER_23:
3982 case RTL_GIGA_MAC_VER_24:
3983 case RTL_GIGA_MAC_VER_25:
3984 case RTL_GIGA_MAC_VER_26:
3985 case RTL_GIGA_MAC_VER_27:
3986 case RTL_GIGA_MAC_VER_28:
3987 case RTL_GIGA_MAC_VER_31:
3988 rtl_writephy(tp, 0x0e, 0x0200);
3989 default:
3990 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3991 break;
3992 }
065c27c1 3993}
3994
3995static void r8168_pll_power_down(struct rtl8169_private *tp)
3996{
3997 void __iomem *ioaddr = tp->mmio_addr;
3998
cecb5fd7
FR		 3999 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4000 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4001 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4002 r8168dp_check_dash(tp)) {
065c27c1 4003 return;
5d2e1957 4004 }
065c27c1 4005
cecb5fd7
FR		 4006 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4007 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4008 (RTL_R16(CPlusCmd) & ASF)) {
4009 return;
4010 }
4011
01dc7fec 4012 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4013 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4014 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4015
649b3b8c 4016 if (rtl_wol_pll_power_down(tp))
065c27c1 4017 return;
065c27c1 4018
4019 r8168_phy_power_down(tp);
4020
4021 switch (tp->mac_version) {
4022 case RTL_GIGA_MAC_VER_25:
4023 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4024 case RTL_GIGA_MAC_VER_27:
4025 case RTL_GIGA_MAC_VER_28:
4804b3b3 4026 case RTL_GIGA_MAC_VER_31:
01dc7fec 4027 case RTL_GIGA_MAC_VER_32:
4028 case RTL_GIGA_MAC_VER_33:
065c27c1 4029 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4030 break;
4031 }
4032}
4033
4034static void r8168_pll_power_up(struct rtl8169_private *tp)
4035{
4036 void __iomem *ioaddr = tp->mmio_addr;
4037
065c27c1 4038 switch (tp->mac_version) {
4039 case RTL_GIGA_MAC_VER_25:
4040 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4041 case RTL_GIGA_MAC_VER_27:
4042 case RTL_GIGA_MAC_VER_28:
4804b3b3 4043 case RTL_GIGA_MAC_VER_31:
01dc7fec 4044 case RTL_GIGA_MAC_VER_32:
4045 case RTL_GIGA_MAC_VER_33:
065c27c1 4046 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4047 break;
4048 }
4049
4050 r8168_phy_power_up(tp);
4051}
4052
d58d46b5
FR		 4053static void rtl_generic_op(struct rtl8169_private *tp,
4054 void (*op)(struct rtl8169_private *))
065c27c1 4055{
4056 if (op)
4057 op(tp);
4058}
4059
4060static void rtl_pll_power_down(struct rtl8169_private *tp)
4061{
d58d46b5 4062 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4063}
4064
4065static void rtl_pll_power_up(struct rtl8169_private *tp)
4066{
d58d46b5 4067 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4068}
4069
baf63293 4070static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4071{
4072 struct pll_power_ops *ops = &tp->pll_power_ops;
4073
4074 switch (tp->mac_version) {
4075 case RTL_GIGA_MAC_VER_07:
4076 case RTL_GIGA_MAC_VER_08:
4077 case RTL_GIGA_MAC_VER_09:
4078 case RTL_GIGA_MAC_VER_10:
4079 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4080 case RTL_GIGA_MAC_VER_29:
4081 case RTL_GIGA_MAC_VER_30:
7e18dca1 4082 case RTL_GIGA_MAC_VER_37:
5598bfe5 4083 case RTL_GIGA_MAC_VER_39:
065c27c1 4084 ops->down = r810x_pll_power_down;
4085 ops->up = r810x_pll_power_up;
4086 break;
4087
4088 case RTL_GIGA_MAC_VER_11:
4089 case RTL_GIGA_MAC_VER_12:
4090 case RTL_GIGA_MAC_VER_17:
4091 case RTL_GIGA_MAC_VER_18:
4092 case RTL_GIGA_MAC_VER_19:
4093 case RTL_GIGA_MAC_VER_20:
4094 case RTL_GIGA_MAC_VER_21:
4095 case RTL_GIGA_MAC_VER_22:
4096 case RTL_GIGA_MAC_VER_23:
4097 case RTL_GIGA_MAC_VER_24:
4098 case RTL_GIGA_MAC_VER_25:
4099 case RTL_GIGA_MAC_VER_26:
4100 case RTL_GIGA_MAC_VER_27:
e6de30d6 4101 case RTL_GIGA_MAC_VER_28:
4804b3b3 4102 case RTL_GIGA_MAC_VER_31:
01dc7fec 4103 case RTL_GIGA_MAC_VER_32:
4104 case RTL_GIGA_MAC_VER_33:
70090424 4105 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4106 case RTL_GIGA_MAC_VER_35:
4107 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4108 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4109 case RTL_GIGA_MAC_VER_40:
4110 case RTL_GIGA_MAC_VER_41:
065c27c1 4111 ops->down = r8168_pll_power_down;
4112 ops->up = r8168_pll_power_up;
4113 break;
4114
4115 default:
4116 ops->down = NULL;
4117 ops->up = NULL;
4118 break;
4119 }
4120}
4121
e542a226
HW		 4122static void rtl_init_rxcfg(struct rtl8169_private *tp)
4123{
4124 void __iomem *ioaddr = tp->mmio_addr;
4125
4126 switch (tp->mac_version) {
4127 case RTL_GIGA_MAC_VER_01:
4128 case RTL_GIGA_MAC_VER_02:
4129 case RTL_GIGA_MAC_VER_03:
4130 case RTL_GIGA_MAC_VER_04:
4131 case RTL_GIGA_MAC_VER_05:
4132 case RTL_GIGA_MAC_VER_06:
4133 case RTL_GIGA_MAC_VER_10:
4134 case RTL_GIGA_MAC_VER_11:
4135 case RTL_GIGA_MAC_VER_12:
4136 case RTL_GIGA_MAC_VER_13:
4137 case RTL_GIGA_MAC_VER_14:
4138 case RTL_GIGA_MAC_VER_15:
4139 case RTL_GIGA_MAC_VER_16:
4140 case RTL_GIGA_MAC_VER_17:
4141 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4142 break;
4143 case RTL_GIGA_MAC_VER_18:
4144 case RTL_GIGA_MAC_VER_19:
4145 case RTL_GIGA_MAC_VER_20:
4146 case RTL_GIGA_MAC_VER_21:
4147 case RTL_GIGA_MAC_VER_22:
4148 case RTL_GIGA_MAC_VER_23:
4149 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4150 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4151 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4152 break;
4153 default:
4154 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4155 break;
4156 }
4157}
4158
92fc43b4
HW		 4159static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4160{
9fba0812 4161 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4162}
4163
d58d46b5
FR		 4164static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4165{
9c5028e9 4166 void __iomem *ioaddr = tp->mmio_addr;
4167
4168 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4169 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4170 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4171}
4172
4173static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4174{
9c5028e9 4175 void __iomem *ioaddr = tp->mmio_addr;
4176
4177 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4178 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4179 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4180}
4181
4182static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4183{
4184 void __iomem *ioaddr = tp->mmio_addr;
4185
4186 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4187 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4188 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4189}
4190
4191static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4192{
4193 void __iomem *ioaddr = tp->mmio_addr;
4194
4195 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4196 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4197 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4198}
4199
4200static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4201{
4202 void __iomem *ioaddr = tp->mmio_addr;
4203
4204 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4205}
4206
4207static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4208{
4209 void __iomem *ioaddr = tp->mmio_addr;
4210
4211 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4212}
4213
4214static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4215{
4216 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4217
4218 RTL_W8(MaxTxPacketSize, 0x3f);
4219 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4220 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4221 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4222}
4223
4224static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4225{
4226 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4227
4228 RTL_W8(MaxTxPacketSize, 0x0c);
4229 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4230 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4231 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4232}
4233
4234static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4235{
4236 rtl_tx_performance_tweak(tp->pci_dev,
4237 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4238}
4239
4240static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4241{
4242 rtl_tx_performance_tweak(tp->pci_dev,
4243 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4244}
4245
4246static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4247{
4248 void __iomem *ioaddr = tp->mmio_addr;
4249
4250 r8168b_0_hw_jumbo_enable(tp);
4251
4252 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4253}
4254
4255static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4256{
4257 void __iomem *ioaddr = tp->mmio_addr;
4258
4259 r8168b_0_hw_jumbo_disable(tp);
4260
4261 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4262}
4263
baf63293 4264static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4265{
4266 struct jumbo_ops *ops = &tp->jumbo_ops;
4267
4268 switch (tp->mac_version) {
4269 case RTL_GIGA_MAC_VER_11:
4270 ops->disable = r8168b_0_hw_jumbo_disable;
4271 ops->enable = r8168b_0_hw_jumbo_enable;
4272 break;
4273 case RTL_GIGA_MAC_VER_12:
4274 case RTL_GIGA_MAC_VER_17:
4275 ops->disable = r8168b_1_hw_jumbo_disable;
4276 ops->enable = r8168b_1_hw_jumbo_enable;
4277 break;
4278 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4279 case RTL_GIGA_MAC_VER_19:
4280 case RTL_GIGA_MAC_VER_20:
4281 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4282 case RTL_GIGA_MAC_VER_22:
4283 case RTL_GIGA_MAC_VER_23:
4284 case RTL_GIGA_MAC_VER_24:
4285 case RTL_GIGA_MAC_VER_25:
4286 case RTL_GIGA_MAC_VER_26:
4287 ops->disable = r8168c_hw_jumbo_disable;
4288 ops->enable = r8168c_hw_jumbo_enable;
4289 break;
4290 case RTL_GIGA_MAC_VER_27:
4291 case RTL_GIGA_MAC_VER_28:
4292 ops->disable = r8168dp_hw_jumbo_disable;
4293 ops->enable = r8168dp_hw_jumbo_enable;
4294 break;
4295 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4296 case RTL_GIGA_MAC_VER_32:
4297 case RTL_GIGA_MAC_VER_33:
4298 case RTL_GIGA_MAC_VER_34:
4299 ops->disable = r8168e_hw_jumbo_disable;
4300 ops->enable = r8168e_hw_jumbo_enable;
4301 break;
4302
4303 /*
4304 * No action needed for jumbo frames with 8169.
4305 * No jumbo for 810x at all.
4306 */
c558386b
HW		 4307 case RTL_GIGA_MAC_VER_40:
4308 case RTL_GIGA_MAC_VER_41:
d58d46b5
FR		 4309 default:
4310 ops->disable = NULL;
4311 ops->enable = NULL;
4312 break;
4313 }
4314}
4315
ffc46952
FR		 4316DECLARE_RTL_COND(rtl_chipcmd_cond)
4317{
4318 void __iomem *ioaddr = tp->mmio_addr;
4319
4320 return RTL_R8(ChipCmd) & CmdReset;
4321}
4322
6f43adc8
FR		 4323static void rtl_hw_reset(struct rtl8169_private *tp)
4324{
4325 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4326
6f43adc8
FR		 4327 RTL_W8(ChipCmd, CmdReset);
4328
ffc46952 4329 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4330}
4331
b6ffd97f 4332static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4333{
b6ffd97f
FR		 4334 struct rtl_fw *rtl_fw;
4335 const char *name;
4336 int rc = -ENOMEM;
953a12cc 4337
b6ffd97f
FR		 4338 name = rtl_lookup_firmware_name(tp);
4339 if (!name)
4340 goto out_no_firmware;
953a12cc 4341
b6ffd97f
FR		 4342 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4343 if (!rtl_fw)
4344 goto err_warn;
31bd204f 4345
b6ffd97f
FR		 4346 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4347 if (rc < 0)
4348 goto err_free;
4349
fd112f2e
FR		 4350 rc = rtl_check_firmware(tp, rtl_fw);
4351 if (rc < 0)
4352 goto err_release_firmware;
4353
b6ffd97f
FR		 4354 tp->rtl_fw = rtl_fw;
4355out:
4356 return;
4357
fd112f2e
FR		 4358err_release_firmware:
4359 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4360err_free:
4361 kfree(rtl_fw);
4362err_warn:
4363 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4364 name, rc);
4365out_no_firmware:
4366 tp->rtl_fw = NULL;
4367 goto out;
4368}
4369
4370static void rtl_request_firmware(struct rtl8169_private *tp)
4371{
4372 if (IS_ERR(tp->rtl_fw))
4373 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4374}
4375
92fc43b4
HW		 4376static void rtl_rx_close(struct rtl8169_private *tp)
4377{
4378 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4379
1687b566 4380 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4381}
4382
ffc46952
FR		 4383DECLARE_RTL_COND(rtl_npq_cond)
4384{
4385 void __iomem *ioaddr = tp->mmio_addr;
4386
4387 return RTL_R8(TxPoll) & NPQ;
4388}
4389
4390DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4391{
4392 void __iomem *ioaddr = tp->mmio_addr;
4393
4394 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4395}
4396
e6de30d6 4397static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4398{
e6de30d6 4399 void __iomem *ioaddr = tp->mmio_addr;
4400
1da177e4 4401 /* Disable interrupts */
811fd301 4402 rtl8169_irq_mask_and_ack(tp);
1da177e4 4403
92fc43b4
HW		 4404 rtl_rx_close(tp);
4405
5d2e1957 4406 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4407 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4408 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4409 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4410 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4411 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4412 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4413 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4414 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4415 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
b3d7b2f2 4416 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4417 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4418 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4419 } else {
4420 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4421 udelay(100);
e6de30d6 4422 }
4423
92fc43b4 4424 rtl_hw_reset(tp);
1da177e4
LT		 4425}
4426
7f796d83 4427static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4428{
4429 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4430
4431 /* Set DMA burst size and Interframe Gap Time */
4432 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4433 (InterFrameGap << TxInterFrameGapShift));
4434}
4435
07ce4064 4436static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4437{
4438 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4439
07ce4064
FR		 4440 tp->hw_start(dev);
4441
da78dbff 4442 rtl_irq_enable_all(tp);
07ce4064
FR		 4443}
4444
7f796d83
FR		 4445static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4446 void __iomem *ioaddr)
4447{
4448 /*
4449 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4450 * register to be written before TxDescAddrLow to work.
4451 * Switching from MMIO to I/O access fixes the issue as well.
4452 */
4453 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4454 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4455 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4456 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4457}
4458
4459static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4460{
4461 u16 cmd;
4462
4463 cmd = RTL_R16(CPlusCmd);
4464 RTL_W16(CPlusCmd, cmd);
4465 return cmd;
4466}
4467
fdd7b4c3 4468static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4469{
4470 /* Low hurts. Let's disable the filtering. */
207d6e87 4471 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4472}
4473
6dccd16b
FR		 4474static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4475{
3744100e 4476 static const struct rtl_cfg2_info {
6dccd16b
FR		 4477 u32 mac_version;
4478 u32 clk;
4479 u32 val;
4480 } cfg2_info [] = {
4481 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4482 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4483 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4484 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4485 };
4486 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4487 unsigned int i;
4488 u32 clk;
4489
4490 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4491 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4492 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4493 RTL_W32(0x7c, p->val);
4494 break;
4495 }
4496 }
4497}
4498
e6b763ea
FR		 4499static void rtl_set_rx_mode(struct net_device *dev)
4500{
4501 struct rtl8169_private *tp = netdev_priv(dev);
4502 void __iomem *ioaddr = tp->mmio_addr;
4503 u32 mc_filter[2]; /* Multicast hash filter */
4504 int rx_mode;
4505 u32 tmp = 0;
4506
4507 if (dev->flags & IFF_PROMISC) {
4508 /* Unconditionally log net taps. */
4509 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4510 rx_mode =
4511 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4512 AcceptAllPhys;
4513 mc_filter[1] = mc_filter[0] = 0xffffffff;
4514 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4515 (dev->flags & IFF_ALLMULTI)) {
4516 /* Too many to filter perfectly -- accept all multicasts. */
4517 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4518 mc_filter[1] = mc_filter[0] = 0xffffffff;
4519 } else {
4520 struct netdev_hw_addr *ha;
4521
4522 rx_mode = AcceptBroadcast | AcceptMyPhys;
4523 mc_filter[1] = mc_filter[0] = 0;
4524 netdev_for_each_mc_addr(ha, dev) {
4525 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4526 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4527 rx_mode |= AcceptMulticast;
4528 }
4529 }
4530
4531 if (dev->features & NETIF_F_RXALL)
4532 rx_mode |= (AcceptErr | AcceptRunt);
4533
4534 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4535
4536 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4537 u32 data = mc_filter[0];
4538
4539 mc_filter[0] = swab32(mc_filter[1]);
4540 mc_filter[1] = swab32(data);
4541 }
4542
0481776b
NW		 4543 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4544 mc_filter[1] = mc_filter[0] = 0xffffffff;
4545
e6b763ea
FR		 4546 RTL_W32(MAR0 + 4, mc_filter[1]);
4547 RTL_W32(MAR0 + 0, mc_filter[0]);
4548
4549 RTL_W32(RxConfig, tmp);
4550}
4551
07ce4064
FR		 4552static void rtl_hw_start_8169(struct net_device *dev)
4553{
4554 struct rtl8169_private *tp = netdev_priv(dev);
4555 void __iomem *ioaddr = tp->mmio_addr;
4556 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4557
9cb427b6
FR		 4558 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4559 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4560 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4561 }
4562
1da177e4 4563 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4564 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4565 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4566 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4567 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4568 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4569
e542a226
HW		 4570 rtl_init_rxcfg(tp);
4571
f0298f81 4572 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4573
6f0333b8 4574 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4575
cecb5fd7
FR		 4576 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4577 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4578 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4579 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4580 rtl_set_rx_tx_config_registers(tp);
1da177e4 4581
7f796d83 4582 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4583
cecb5fd7
FR		 4584 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4585 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4586 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4587 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4588 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4589 }
4590
bcf0bf90
FR		 4591 RTL_W16(CPlusCmd, tp->cp_cmd);
4592
6dccd16b
FR		 4593 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4594
1da177e4
LT		 4595 /*
4596 * Undocumented corner. Supposedly:
4597 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4598 */
4599 RTL_W16(IntrMitigate, 0x0000);
4600
7f796d83 4601 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4602
cecb5fd7
FR		 4603 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4604 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4605 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4606 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4607 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4608 rtl_set_rx_tx_config_registers(tp);
4609 }
4610
1da177e4 4611 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4612
4613 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4614 RTL_R8(IntrMask);
1da177e4
LT		 4615
4616 RTL_W32(RxMissed, 0);
4617
07ce4064 4618 rtl_set_rx_mode(dev);
1da177e4
LT		 4619
4620 /* no early-rx interrupts */
4621 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4622}
1da177e4 4623
beb1fe18
HW		 4624static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4625{
4626 if (tp->csi_ops.write)
52989f0e 4627 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4628}
4629
4630static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4631{
52989f0e 4632 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4633}
4634
4635static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4636{
4637 u32 csi;
4638
beb1fe18
HW		 4639 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4640 rtl_csi_write(tp, 0x070c, csi | bits);
4641}
4642
4643static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4644{
4645 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4646}
4647
beb1fe18 4648static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4649{
beb1fe18 4650 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4651}
4652
ffc46952
FR		 4653DECLARE_RTL_COND(rtl_csiar_cond)
4654{
4655 void __iomem *ioaddr = tp->mmio_addr;
4656
4657 return RTL_R32(CSIAR) & CSIAR_FLAG;
4658}
4659
52989f0e 4660static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4661{
52989f0e 4662 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4663
4664 RTL_W32(CSIDR, value);
4665 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4666 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4667
ffc46952 4668 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4669}
4670
52989f0e 4671static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4672{
52989f0e 4673 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4674
4675 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4676 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4677
ffc46952
FR		 4678 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4679 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4680}
4681
52989f0e 4682static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4683{
52989f0e 4684 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4685
4686 RTL_W32(CSIDR, value);
4687 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4688 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4689 CSIAR_FUNC_NIC);
4690
ffc46952 4691 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4692}
4693
52989f0e 4694static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4695{
52989f0e 4696 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4697
4698 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4699 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4700
ffc46952
FR		 4701 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4702 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4703}
4704
baf63293 4705static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 4706{
4707 struct csi_ops *ops = &tp->csi_ops;
4708
4709 switch (tp->mac_version) {
4710 case RTL_GIGA_MAC_VER_01:
4711 case RTL_GIGA_MAC_VER_02:
4712 case RTL_GIGA_MAC_VER_03:
4713 case RTL_GIGA_MAC_VER_04:
4714 case RTL_GIGA_MAC_VER_05:
4715 case RTL_GIGA_MAC_VER_06:
4716 case RTL_GIGA_MAC_VER_10:
4717 case RTL_GIGA_MAC_VER_11:
4718 case RTL_GIGA_MAC_VER_12:
4719 case RTL_GIGA_MAC_VER_13:
4720 case RTL_GIGA_MAC_VER_14:
4721 case RTL_GIGA_MAC_VER_15:
4722 case RTL_GIGA_MAC_VER_16:
4723 case RTL_GIGA_MAC_VER_17:
4724 ops->write = NULL;
4725 ops->read = NULL;
4726 break;
4727
7e18dca1 4728 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4729 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4730 ops->write = r8402_csi_write;
4731 ops->read = r8402_csi_read;
4732 break;
4733
beb1fe18
HW		 4734 default:
4735 ops->write = r8169_csi_write;
4736 ops->read = r8169_csi_read;
4737 break;
4738 }
dacf8154
FR		 4739}
4740
4741struct ephy_info {
4742 unsigned int offset;
4743 u16 mask;
4744 u16 bits;
4745};
4746
fdf6fc06
FR		 4747static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4748 int len)
dacf8154
FR		 4749{
4750 u16 w;
4751
4752 while (len-- > 0) {
fdf6fc06
FR		 4753 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4754 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4755 e++;
4756 }
4757}
4758
b726e493
FR		 4759static void rtl_disable_clock_request(struct pci_dev *pdev)
4760{
7d7903b2
JL		 4761 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4762 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4763}
4764
e6de30d6 4765static void rtl_enable_clock_request(struct pci_dev *pdev)
4766{
7d7903b2
JL		 4767 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4768 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4769}
4770
b726e493
FR		 4771#define R8168_CPCMD_QUIRK_MASK (\
4772 EnableBist | \
4773 Mac_dbgo_oe | \
4774 Force_half_dup | \
4775 Force_rxflow_en | \
4776 Force_txflow_en | \
4777 Cxpl_dbg_sel | \
4778 ASF | \
4779 PktCntrDisable | \
4780 Mac_dbgo_sel)
4781
beb1fe18 4782static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4783{
beb1fe18
HW		 4784 void __iomem *ioaddr = tp->mmio_addr;
4785 struct pci_dev *pdev = tp->pci_dev;
4786
b726e493
FR		 4787 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4788
4789 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4790
faf1e785 4791 if (tp->dev->mtu <= ETH_DATA_LEN) {
4792 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4793 PCI_EXP_DEVCTL_NOSNOOP_EN);
4794 }
219a1e9d
FR		 4795}
4796
beb1fe18 4797static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4798{
beb1fe18
HW		 4799 void __iomem *ioaddr = tp->mmio_addr;
4800
4801 rtl_hw_start_8168bb(tp);
b726e493 4802
f0298f81 4803 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4804
4805 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4806}
4807
beb1fe18 4808static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4809{
beb1fe18
HW		 4810 void __iomem *ioaddr = tp->mmio_addr;
4811 struct pci_dev *pdev = tp->pci_dev;
4812
b726e493
FR		 4813 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4814
4815 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4816
faf1e785 4817 if (tp->dev->mtu <= ETH_DATA_LEN)
4818 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4819
4820 rtl_disable_clock_request(pdev);
4821
4822 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4823}
4824
beb1fe18 4825static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4826{
350f7596 4827 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4828 { 0x01, 0, 0x0001 },
4829 { 0x02, 0x0800, 0x1000 },
4830 { 0x03, 0, 0x0042 },
4831 { 0x06, 0x0080, 0x0000 },
4832 { 0x07, 0, 0x2000 }
4833 };
4834
beb1fe18 4835 rtl_csi_access_enable_2(tp);
b726e493 4836
fdf6fc06 4837 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4838
beb1fe18 4839 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4840}
4841
beb1fe18 4842static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4843{
beb1fe18
HW		 4844 void __iomem *ioaddr = tp->mmio_addr;
4845 struct pci_dev *pdev = tp->pci_dev;
4846
4847 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4848
4849 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4850
faf1e785 4851 if (tp->dev->mtu <= ETH_DATA_LEN)
4852 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 4853
4854 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4855}
4856
beb1fe18 4857static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4858{
beb1fe18
HW		 4859 void __iomem *ioaddr = tp->mmio_addr;
4860 struct pci_dev *pdev = tp->pci_dev;
4861
4862 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4863
4864 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4865
4866 /* Magic. */
4867 RTL_W8(DBG_REG, 0x20);
4868
f0298f81 4869 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4870
faf1e785 4871 if (tp->dev->mtu <= ETH_DATA_LEN)
4872 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 4873
4874 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4875}
4876
beb1fe18 4877static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4878{
beb1fe18 4879 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4880 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4881 { 0x02, 0x0800, 0x1000 },
4882 { 0x03, 0, 0x0002 },
4883 { 0x06, 0x0080, 0x0000 }
4884 };
4885
beb1fe18 4886 rtl_csi_access_enable_2(tp);
b726e493
FR		 4887
4888 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4889
fdf6fc06 4890 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4891
beb1fe18 4892 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4893}
4894
beb1fe18 4895static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4896{
350f7596 4897 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4898 { 0x01, 0, 0x0001 },
4899 { 0x03, 0x0400, 0x0220 }
4900 };
4901
beb1fe18 4902 rtl_csi_access_enable_2(tp);
b726e493 4903
fdf6fc06 4904 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4905
beb1fe18 4906 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4907}
4908
beb1fe18 4909static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4910{
beb1fe18 4911 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4912}
4913
beb1fe18 4914static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4915{
beb1fe18 4916 rtl_csi_access_enable_2(tp);
6fb07058 4917
beb1fe18 4918 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4919}
4920
beb1fe18 4921static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4922{
beb1fe18
HW		 4923 void __iomem *ioaddr = tp->mmio_addr;
4924 struct pci_dev *pdev = tp->pci_dev;
4925
4926 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4927
4928 rtl_disable_clock_request(pdev);
4929
f0298f81 4930 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 4931
faf1e785 4932 if (tp->dev->mtu <= ETH_DATA_LEN)
4933 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 4934
4935 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4936}
4937
beb1fe18 4938static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4939{
beb1fe18
HW		 4940 void __iomem *ioaddr = tp->mmio_addr;
4941 struct pci_dev *pdev = tp->pci_dev;
4942
4943 rtl_csi_access_enable_1(tp);
4804b3b3 4944
faf1e785 4945 if (tp->dev->mtu <= ETH_DATA_LEN)
4946 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 4947
4948 RTL_W8(MaxTxPacketSize, TxPacketMax);
4949
4950 rtl_disable_clock_request(pdev);
4951}
4952
beb1fe18 4953static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4954{
beb1fe18
HW		 4955 void __iomem *ioaddr = tp->mmio_addr;
4956 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4957 static const struct ephy_info e_info_8168d_4[] = {
4958 { 0x0b, ~0, 0x48 },
4959 { 0x19, 0x20, 0x50 },
4960 { 0x0c, ~0, 0x20 }
4961 };
4962 int i;
4963
beb1fe18 4964 rtl_csi_access_enable_1(tp);
e6de30d6 4965
4966 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4967
4968 RTL_W8(MaxTxPacketSize, TxPacketMax);
4969
4970 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4971 const struct ephy_info *e = e_info_8168d_4 + i;
4972 u16 w;
4973
fdf6fc06
FR		 4974 w = rtl_ephy_read(tp, e->offset);
4975 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 4976 }
4977
4978 rtl_enable_clock_request(pdev);
4979}
4980
beb1fe18 4981static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4982{
beb1fe18
HW		 4983 void __iomem *ioaddr = tp->mmio_addr;
4984 struct pci_dev *pdev = tp->pci_dev;
70090424 4985 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4986 { 0x00, 0x0200, 0x0100 },
4987 { 0x00, 0x0000, 0x0004 },
4988 { 0x06, 0x0002, 0x0001 },
4989 { 0x06, 0x0000, 0x0030 },
4990 { 0x07, 0x0000, 0x2000 },
4991 { 0x00, 0x0000, 0x0020 },
4992 { 0x03, 0x5800, 0x2000 },
4993 { 0x03, 0x0000, 0x0001 },
4994 { 0x01, 0x0800, 0x1000 },
4995 { 0x07, 0x0000, 0x4000 },
4996 { 0x1e, 0x0000, 0x2000 },
4997 { 0x19, 0xffff, 0xfe6c },
4998 { 0x0a, 0x0000, 0x0040 }
4999 };
5000
beb1fe18 5001 rtl_csi_access_enable_2(tp);
01dc7fec 5002
fdf6fc06 5003 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5004
faf1e785 5005 if (tp->dev->mtu <= ETH_DATA_LEN)
5006 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5007
5008 RTL_W8(MaxTxPacketSize, TxPacketMax);
5009
5010 rtl_disable_clock_request(pdev);
5011
5012 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5013 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5014 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5015
cecb5fd7 5016 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5017}
5018
beb1fe18 5019static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5020{
beb1fe18
HW		 5021 void __iomem *ioaddr = tp->mmio_addr;
5022 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5023 static const struct ephy_info e_info_8168e_2[] = {
5024 { 0x09, 0x0000, 0x0080 },
5025 { 0x19, 0x0000, 0x0224 }
5026 };
5027
beb1fe18 5028 rtl_csi_access_enable_1(tp);
70090424 5029
fdf6fc06 5030 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5031
faf1e785 5032 if (tp->dev->mtu <= ETH_DATA_LEN)
5033 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5034
fdf6fc06
FR		 5035 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5036 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5037 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5038 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5039 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5040 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5041 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5042 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5043
3090bd9a 5044 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5045
4521e1a9
FR		 5046 rtl_disable_clock_request(pdev);
5047
70090424
HW		 5048 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5049 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5050
5051 /* Adjust EEE LED frequency */
5052 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5053
5054 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5055 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5056 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5057}
5058
5f886e08 5059static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5060{
beb1fe18
HW		 5061 void __iomem *ioaddr = tp->mmio_addr;
5062 struct pci_dev *pdev = tp->pci_dev;
c2218925 5063
5f886e08 5064 rtl_csi_access_enable_2(tp);
c2218925
HW		 5065
5066 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5067
fdf6fc06
FR		 5068 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5069 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5070 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5071 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5072 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5073 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5074 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5075 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5076 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5077 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5078
5079 RTL_W8(MaxTxPacketSize, EarlySize);
5080
4521e1a9
FR		 5081 rtl_disable_clock_request(pdev);
5082
c2218925
HW		 5083 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5084 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5085 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5086 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5087 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5088}
5089
5f886e08
HW		 5090static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5091{
5092 void __iomem *ioaddr = tp->mmio_addr;
5093 static const struct ephy_info e_info_8168f_1[] = {
5094 { 0x06, 0x00c0, 0x0020 },
5095 { 0x08, 0x0001, 0x0002 },
5096 { 0x09, 0x0000, 0x0080 },
5097 { 0x19, 0x0000, 0x0224 }
5098 };
5099
5100 rtl_hw_start_8168f(tp);
5101
fdf6fc06 5102 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5103
fdf6fc06 5104 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5105
5106 /* Adjust EEE LED frequency */
5107 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5108}
5109
b3d7b2f2
HW		 5110static void rtl_hw_start_8411(struct rtl8169_private *tp)
5111{
b3d7b2f2
HW		 5112 static const struct ephy_info e_info_8168f_1[] = {
5113 { 0x06, 0x00c0, 0x0020 },
5114 { 0x0f, 0xffff, 0x5200 },
5115 { 0x1e, 0x0000, 0x4000 },
5116 { 0x19, 0x0000, 0x0224 }
5117 };
5118
5119 rtl_hw_start_8168f(tp);
5120
fdf6fc06 5121 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5122
fdf6fc06 5123 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5124}
5125
c558386b
HW		 5126static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5127{
5128 void __iomem *ioaddr = tp->mmio_addr;
5129 struct pci_dev *pdev = tp->pci_dev;
5130
5131 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5132 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5133 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5134 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5135
5136 rtl_csi_access_enable_1(tp);
5137
5138 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5139
5140 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5141 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5142
5143 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4521e1a9 5144 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 5145 RTL_W8(MaxTxPacketSize, EarlySize);
5146
5147 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5148 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5149
5150 /* Adjust EEE LED frequency */
5151 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5152
5153 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5154}
5155
07ce4064
FR		 5156static void rtl_hw_start_8168(struct net_device *dev)
5157{
2dd99530
FR		 5158 struct rtl8169_private *tp = netdev_priv(dev);
5159 void __iomem *ioaddr = tp->mmio_addr;
5160
5161 RTL_W8(Cfg9346, Cfg9346_Unlock);
5162
f0298f81 5163 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5164
6f0333b8 5165 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5166
0e485150 5167 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5168
5169 RTL_W16(CPlusCmd, tp->cp_cmd);
5170
0e485150 5171 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5172
0e485150 5173 /* Work around for RxFIFO overflow. */
811fd301 5174 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5175 tp->event_slow |= RxFIFOOver | PCSTimeout;
5176 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5177 }
5178
5179 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5180
b8363901
FR		 5181 rtl_set_rx_mode(dev);
5182
5183 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5184 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 5185
5186 RTL_R8(IntrMask);
5187
219a1e9d
FR		 5188 switch (tp->mac_version) {
5189 case RTL_GIGA_MAC_VER_11:
beb1fe18 5190 rtl_hw_start_8168bb(tp);
4804b3b3 5191 break;
219a1e9d
FR		 5192
5193 case RTL_GIGA_MAC_VER_12:
5194 case RTL_GIGA_MAC_VER_17:
beb1fe18 5195 rtl_hw_start_8168bef(tp);
4804b3b3 5196 break;
219a1e9d
FR		 5197
5198 case RTL_GIGA_MAC_VER_18:
beb1fe18 5199 rtl_hw_start_8168cp_1(tp);
4804b3b3 5200 break;
219a1e9d
FR		 5201
5202 case RTL_GIGA_MAC_VER_19:
beb1fe18 5203 rtl_hw_start_8168c_1(tp);
4804b3b3 5204 break;
219a1e9d
FR		 5205
5206 case RTL_GIGA_MAC_VER_20:
beb1fe18 5207 rtl_hw_start_8168c_2(tp);
4804b3b3 5208 break;
219a1e9d 5209
197ff761 5210 case RTL_GIGA_MAC_VER_21:
beb1fe18 5211 rtl_hw_start_8168c_3(tp);
4804b3b3 5212 break;
197ff761 5213
6fb07058 5214 case RTL_GIGA_MAC_VER_22:
beb1fe18 5215 rtl_hw_start_8168c_4(tp);
4804b3b3 5216 break;
6fb07058 5217
ef3386f0 5218 case RTL_GIGA_MAC_VER_23:
beb1fe18 5219 rtl_hw_start_8168cp_2(tp);
4804b3b3 5220 break;
ef3386f0 5221
7f3e3d3a 5222 case RTL_GIGA_MAC_VER_24:
beb1fe18 5223 rtl_hw_start_8168cp_3(tp);
4804b3b3 5224 break;
7f3e3d3a 5225
5b538df9 5226 case RTL_GIGA_MAC_VER_25:
daf9df6d 5227 case RTL_GIGA_MAC_VER_26:
5228 case RTL_GIGA_MAC_VER_27:
beb1fe18 5229 rtl_hw_start_8168d(tp);
4804b3b3 5230 break;
5b538df9 5231
e6de30d6 5232 case RTL_GIGA_MAC_VER_28:
beb1fe18 5233 rtl_hw_start_8168d_4(tp);
4804b3b3 5234 break;
cecb5fd7 5235
4804b3b3 5236 case RTL_GIGA_MAC_VER_31:
beb1fe18 5237 rtl_hw_start_8168dp(tp);
4804b3b3 5238 break;
5239
01dc7fec 5240 case RTL_GIGA_MAC_VER_32:
5241 case RTL_GIGA_MAC_VER_33:
beb1fe18 5242 rtl_hw_start_8168e_1(tp);
70090424
HW		 5243 break;
5244 case RTL_GIGA_MAC_VER_34:
beb1fe18 5245 rtl_hw_start_8168e_2(tp);
01dc7fec 5246 break;
e6de30d6 5247
c2218925
HW		 5248 case RTL_GIGA_MAC_VER_35:
5249 case RTL_GIGA_MAC_VER_36:
beb1fe18 5250 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5251 break;
5252
b3d7b2f2
HW		 5253 case RTL_GIGA_MAC_VER_38:
5254 rtl_hw_start_8411(tp);
5255 break;
5256
c558386b
HW		 5257 case RTL_GIGA_MAC_VER_40:
5258 case RTL_GIGA_MAC_VER_41:
5259 rtl_hw_start_8168g_1(tp);
5260 break;
5261
219a1e9d
FR		 5262 default:
5263 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5264 dev->name, tp->mac_version);
4804b3b3 5265 break;
219a1e9d 5266 }
2dd99530 5267
0e485150
FR		 5268 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5269
b8363901
FR		 5270 RTL_W8(Cfg9346, Cfg9346_Lock);
5271
2dd99530 5272 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5273}
1da177e4 5274
2857ffb7
FR		 5275#define R810X_CPCMD_QUIRK_MASK (\
5276 EnableBist | \
5277 Mac_dbgo_oe | \
5278 Force_half_dup | \
5edcc537 5279 Force_rxflow_en | \
2857ffb7
FR		 5280 Force_txflow_en | \
5281 Cxpl_dbg_sel | \
5282 ASF | \
5283 PktCntrDisable | \
d24e9aaf 5284 Mac_dbgo_sel)
2857ffb7 5285
beb1fe18 5286static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5287{
beb1fe18
HW		 5288 void __iomem *ioaddr = tp->mmio_addr;
5289 struct pci_dev *pdev = tp->pci_dev;
350f7596 5290 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5291 { 0x01, 0, 0x6e65 },
5292 { 0x02, 0, 0x091f },
5293 { 0x03, 0, 0xc2f9 },
5294 { 0x06, 0, 0xafb5 },
5295 { 0x07, 0, 0x0e00 },
5296 { 0x19, 0, 0xec80 },
5297 { 0x01, 0, 0x2e65 },
5298 { 0x01, 0, 0x6e65 }
5299 };
5300 u8 cfg1;
5301
beb1fe18 5302 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5303
5304 RTL_W8(DBG_REG, FIX_NAK_1);
5305
5306 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5307
5308 RTL_W8(Config1,
5309 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5310 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5311
5312 cfg1 = RTL_R8(Config1);
5313 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5314 RTL_W8(Config1, cfg1 & ~LEDS0);
5315
fdf6fc06 5316 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5317}
5318
beb1fe18 5319static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5320{
beb1fe18
HW		 5321 void __iomem *ioaddr = tp->mmio_addr;
5322 struct pci_dev *pdev = tp->pci_dev;
5323
5324 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5325
5326 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5327
5328 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5329 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5330}
5331
beb1fe18 5332static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5333{
beb1fe18 5334 rtl_hw_start_8102e_2(tp);
2857ffb7 5335
fdf6fc06 5336 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5337}
5338
beb1fe18 5339static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5340{
beb1fe18 5341 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5342 static const struct ephy_info e_info_8105e_1[] = {
5343 { 0x07, 0, 0x4000 },
5344 { 0x19, 0, 0x0200 },
5345 { 0x19, 0, 0x0020 },
5346 { 0x1e, 0, 0x2000 },
5347 { 0x03, 0, 0x0001 },
5348 { 0x19, 0, 0x0100 },
5349 { 0x19, 0, 0x0004 },
5350 { 0x0a, 0, 0x0020 }
5351 };
5352
cecb5fd7 5353 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5354 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5355
cecb5fd7 5356 /* Disable Early Tally Counter */
5a5e4443
HW		 5357 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5358
5359 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5360 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5361
fdf6fc06 5362 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5363}
5364
beb1fe18 5365static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5366{
beb1fe18 5367 rtl_hw_start_8105e_1(tp);
fdf6fc06 5368 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5369}
5370
7e18dca1
HW		 5371static void rtl_hw_start_8402(struct rtl8169_private *tp)
5372{
5373 void __iomem *ioaddr = tp->mmio_addr;
5374 static const struct ephy_info e_info_8402[] = {
5375 { 0x19, 0xffff, 0xff64 },
5376 { 0x1e, 0, 0x4000 }
5377 };
5378
5379 rtl_csi_access_enable_2(tp);
5380
5381 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5382 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5383
5384 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5385 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5386
fdf6fc06 5387 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5388
5389 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5390
fdf6fc06
FR		 5391 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5392 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5393 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5394 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5395 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5396 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5397 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5398}
5399
5598bfe5
HW		 5400static void rtl_hw_start_8106(struct rtl8169_private *tp)
5401{
5402 void __iomem *ioaddr = tp->mmio_addr;
5403
5404 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5405 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5406
4521e1a9 5407 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 5408 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5409 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5410}
5411
07ce4064
FR		 5412static void rtl_hw_start_8101(struct net_device *dev)
5413{
cdf1a608
FR		 5414 struct rtl8169_private *tp = netdev_priv(dev);
5415 void __iomem *ioaddr = tp->mmio_addr;
5416 struct pci_dev *pdev = tp->pci_dev;
5417
da78dbff
FR		 5418 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5419 tp->event_slow &= ~RxFIFOOver;
811fd301 5420
cecb5fd7 5421 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5422 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 5423 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5424 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5425
d24e9aaf
HW		 5426 RTL_W8(Cfg9346, Cfg9346_Unlock);
5427
2857ffb7
FR		 5428 switch (tp->mac_version) {
5429 case RTL_GIGA_MAC_VER_07:
beb1fe18 5430 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5431 break;
5432
5433 case RTL_GIGA_MAC_VER_08:
beb1fe18 5434 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5435 break;
5436
5437 case RTL_GIGA_MAC_VER_09:
beb1fe18 5438 rtl_hw_start_8102e_2(tp);
2857ffb7 5439 break;
5a5e4443
HW		 5440
5441 case RTL_GIGA_MAC_VER_29:
beb1fe18 5442 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5443 break;
5444 case RTL_GIGA_MAC_VER_30:
beb1fe18 5445 rtl_hw_start_8105e_2(tp);
5a5e4443 5446 break;
7e18dca1
HW		 5447
5448 case RTL_GIGA_MAC_VER_37:
5449 rtl_hw_start_8402(tp);
5450 break;
5598bfe5
HW		 5451
5452 case RTL_GIGA_MAC_VER_39:
5453 rtl_hw_start_8106(tp);
5454 break;
cdf1a608
FR		 5455 }
5456
d24e9aaf 5457 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5458
f0298f81 5459 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5460
6f0333b8 5461 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5462
d24e9aaf 5463 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5464 RTL_W16(CPlusCmd, tp->cp_cmd);
5465
5466 RTL_W16(IntrMitigate, 0x0000);
5467
5468 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5469
5470 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5471 rtl_set_rx_tx_config_registers(tp);
5472
cdf1a608
FR		 5473 RTL_R8(IntrMask);
5474
cdf1a608
FR		 5475 rtl_set_rx_mode(dev);
5476
5477 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5478}
5479
5480static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5481{
d58d46b5
FR		 5482 struct rtl8169_private *tp = netdev_priv(dev);
5483
5484 if (new_mtu < ETH_ZLEN ||
5485 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5486 return -EINVAL;
5487
d58d46b5
FR		 5488 if (new_mtu > ETH_DATA_LEN)
5489 rtl_hw_jumbo_enable(tp);
5490 else
5491 rtl_hw_jumbo_disable(tp);
5492
1da177e4 5493 dev->mtu = new_mtu;
350fb32a
MM		 5494 netdev_update_features(dev);
5495
323bb685 5496 return 0;
1da177e4
LT		 5497}
5498
5499static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5500{
95e0918d 5501 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5502 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5503}
5504
6f0333b8
ED		 5505static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5506 void **data_buff, struct RxDesc *desc)
1da177e4 5507{
48addcc9 5508 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5509 DMA_FROM_DEVICE);
48addcc9 5510
6f0333b8
ED		 5511 kfree(*data_buff);
5512 *data_buff = NULL;
1da177e4
LT		 5513 rtl8169_make_unusable_by_asic(desc);
5514}
5515
5516static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5517{
5518 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5519
5520 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5521}
5522
5523static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5524 u32 rx_buf_sz)
5525{
5526 desc->addr = cpu_to_le64(mapping);
5527 wmb();
5528 rtl8169_mark_to_asic(desc, rx_buf_sz);
5529}
5530
6f0333b8
ED		 5531static inline void *rtl8169_align(void *data)
5532{
5533 return (void *)ALIGN((long)data, 16);
5534}
5535
0ecbe1ca
SG		 5536static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5537 struct RxDesc *desc)
1da177e4 5538{
6f0333b8 5539 void *data;
1da177e4 5540 dma_addr_t mapping;
48addcc9 5541 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5542 struct net_device *dev = tp->dev;
6f0333b8 5543 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5544
6f0333b8
ED		 5545 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5546 if (!data)
5547 return NULL;
e9f63f30 5548
6f0333b8
ED		 5549 if (rtl8169_align(data) != data) {
5550 kfree(data);
5551 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5552 if (!data)
5553 return NULL;
5554 }
3eafe507 5555
48addcc9 5556 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5557 DMA_FROM_DEVICE);
d827d86b
SG		 5558 if (unlikely(dma_mapping_error(d, mapping))) {
5559 if (net_ratelimit())
5560 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5561 goto err_out;
d827d86b 5562 }
1da177e4
LT		 5563
5564 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5565 return data;
3eafe507
SG		 5566
5567err_out:
5568 kfree(data);
5569 return NULL;
1da177e4
LT		 5570}
5571
5572static void rtl8169_rx_clear(struct rtl8169_private *tp)
5573{
07d3f51f 5574 unsigned int i;
1da177e4
LT		 5575
5576 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5577 if (tp->Rx_databuff[i]) {
5578 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5579 tp->RxDescArray + i);
5580 }
5581 }
5582}
5583
0ecbe1ca 5584static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5585{
0ecbe1ca
SG		 5586 desc->opts1 |= cpu_to_le32(RingEnd);
5587}
5b0384f4 5588
0ecbe1ca
SG		 5589static int rtl8169_rx_fill(struct rtl8169_private *tp)
5590{
5591 unsigned int i;
1da177e4 5592
0ecbe1ca
SG		 5593 for (i = 0; i < NUM_RX_DESC; i++) {
5594 void *data;
4ae47c2d 5595
6f0333b8 5596 if (tp->Rx_databuff[i])
1da177e4 5597 continue;
bcf0bf90 5598
0ecbe1ca 5599 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5600 if (!data) {
5601 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5602 goto err_out;
6f0333b8
ED		 5603 }
5604 tp->Rx_databuff[i] = data;
1da177e4 5605 }
1da177e4 5606
0ecbe1ca
SG		 5607 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5608 return 0;
5609
5610err_out:
5611 rtl8169_rx_clear(tp);
5612 return -ENOMEM;
1da177e4
LT		 5613}
5614
1da177e4
LT		 5615static int rtl8169_init_ring(struct net_device *dev)
5616{
5617 struct rtl8169_private *tp = netdev_priv(dev);
5618
5619 rtl8169_init_ring_indexes(tp);
5620
5621 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5622 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5623
0ecbe1ca 5624 return rtl8169_rx_fill(tp);
1da177e4
LT		 5625}
5626
48addcc9 5627static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5628 struct TxDesc *desc)
5629{
5630 unsigned int len = tx_skb->len;
5631
48addcc9
SG		 5632 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5633
1da177e4
LT		 5634 desc->opts1 = 0x00;
5635 desc->opts2 = 0x00;
5636 desc->addr = 0x00;
5637 tx_skb->len = 0;
5638}
5639
3eafe507
SG		 5640static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5641 unsigned int n)
1da177e4
LT		 5642{
5643 unsigned int i;
5644
3eafe507
SG		 5645 for (i = 0; i < n; i++) {
5646 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5647 struct ring_info *tx_skb = tp->tx_skb + entry;
5648 unsigned int len = tx_skb->len;
5649
5650 if (len) {
5651 struct sk_buff *skb = tx_skb->skb;
5652
48addcc9 5653 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5654 tp->TxDescArray + entry);
5655 if (skb) {
cac4b22f 5656 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5657 dev_kfree_skb(skb);
5658 tx_skb->skb = NULL;
5659 }
1da177e4
LT		 5660 }
5661 }
3eafe507
SG		 5662}
5663
5664static void rtl8169_tx_clear(struct rtl8169_private *tp)
5665{
5666 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5667 tp->cur_tx = tp->dirty_tx = 0;
5668}
5669
4422bcd4 5670static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5671{
c4028958 5672 struct net_device *dev = tp->dev;
56de414c 5673 int i;
1da177e4 5674
da78dbff
FR		 5675 napi_disable(&tp->napi);
5676 netif_stop_queue(dev);
5677 synchronize_sched();
1da177e4 5678
c7c2c39b 5679 rtl8169_hw_reset(tp);
5680
56de414c
FR		 5681 for (i = 0; i < NUM_RX_DESC; i++)
5682 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5683
1da177e4 5684 rtl8169_tx_clear(tp);
c7c2c39b 5685 rtl8169_init_ring_indexes(tp);
1da177e4 5686
da78dbff 5687 napi_enable(&tp->napi);
56de414c
FR		 5688 rtl_hw_start(dev);
5689 netif_wake_queue(dev);
5690 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5691}
5692
5693static void rtl8169_tx_timeout(struct net_device *dev)
5694{
da78dbff
FR		 5695 struct rtl8169_private *tp = netdev_priv(dev);
5696
5697 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5698}
5699
5700static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5701 u32 *opts)
1da177e4
LT		 5702{
5703 struct skb_shared_info *info = skb_shinfo(skb);
5704 unsigned int cur_frag, entry;
a6343afb 5705 struct TxDesc * uninitialized_var(txd);
48addcc9 5706 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5707
5708 entry = tp->cur_tx;
5709 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5710 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5711 dma_addr_t mapping;
5712 u32 status, len;
5713 void *addr;
5714
5715 entry = (entry + 1) % NUM_TX_DESC;
5716
5717 txd = tp->TxDescArray + entry;
9e903e08 5718 len = skb_frag_size(frag);
929f6189 5719 addr = skb_frag_address(frag);
48addcc9 5720 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5721 if (unlikely(dma_mapping_error(d, mapping))) {
5722 if (net_ratelimit())
5723 netif_err(tp, drv, tp->dev,
5724 "Failed to map TX fragments DMA!\n");
3eafe507 5725 goto err_out;
d827d86b 5726 }
1da177e4 5727
cecb5fd7 5728 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5729 status = opts[0] | len |
5730 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5731
5732 txd->opts1 = cpu_to_le32(status);
2b7b4318 5733 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5734 txd->addr = cpu_to_le64(mapping);
5735
5736 tp->tx_skb[entry].len = len;
5737 }
5738
5739 if (cur_frag) {
5740 tp->tx_skb[entry].skb = skb;
5741 txd->opts1 |= cpu_to_le32(LastFrag);
5742 }
5743
5744 return cur_frag;
3eafe507
SG		 5745
5746err_out:
5747 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5748 return -EIO;
1da177e4
LT		 5749}
5750
2b7b4318
FR		 5751static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5752 struct sk_buff *skb, u32 *opts)
1da177e4 5753{
2b7b4318 5754 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5755 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5756 int offset = info->opts_offset;
350fb32a 5757
2b7b4318
FR		 5758 if (mss) {
5759 opts[0] |= TD_LSO;
5760 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5761 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5762 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5763
5764 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5765 opts[offset] |= info->checksum.tcp;
1da177e4 5766 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5767 opts[offset] |= info->checksum.udp;
5768 else
5769 WARN_ON_ONCE(1);
1da177e4 5770 }
1da177e4
LT		 5771}
5772
61357325
SH		 5773static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5774 struct net_device *dev)
1da177e4
LT		 5775{
5776 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5777 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5778 struct TxDesc *txd = tp->TxDescArray + entry;
5779 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5780 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5781 dma_addr_t mapping;
5782 u32 status, len;
2b7b4318 5783 u32 opts[2];
3eafe507 5784 int frags;
5b0384f4 5785
477206a0 5786 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5787 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5788 goto err_stop_0;
1da177e4
LT		 5789 }
5790
5791 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5792 goto err_stop_0;
5793
5794 len = skb_headlen(skb);
48addcc9 5795 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5796 if (unlikely(dma_mapping_error(d, mapping))) {
5797 if (net_ratelimit())
5798 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5799 goto err_dma_0;
d827d86b 5800 }
3eafe507
SG		 5801
5802 tp->tx_skb[entry].len = len;
5803 txd->addr = cpu_to_le64(mapping);
1da177e4 5804
810f4893 5805 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
2b7b4318 5806 opts[0] = DescOwn;
1da177e4 5807
2b7b4318
FR		 5808 rtl8169_tso_csum(tp, skb, opts);
5809
5810 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5811 if (frags < 0)
5812 goto err_dma_1;
5813 else if (frags)
2b7b4318 5814 opts[0] |= FirstFrag;
3eafe507 5815 else {
2b7b4318 5816 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5817 tp->tx_skb[entry].skb = skb;
5818 }
5819
2b7b4318
FR		 5820 txd->opts2 = cpu_to_le32(opts[1]);
5821
5047fb5d
RC		 5822 skb_tx_timestamp(skb);
5823
1da177e4
LT		 5824 wmb();
5825
cecb5fd7 5826 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5827 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5828 txd->opts1 = cpu_to_le32(status);
5829
1da177e4
LT		 5830 tp->cur_tx += frags + 1;
5831
4c020a96 5832 wmb();
1da177e4 5833
cecb5fd7 5834 RTL_W8(TxPoll, NPQ);
1da177e4 5835
da78dbff
FR		 5836 mmiowb();
5837
477206a0 5838 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5839 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5840 * not miss a ring update when it notices a stopped queue.
5841 */
5842 smp_wmb();
1da177e4 5843 netif_stop_queue(dev);
ae1f23fb
FR		 5844 /* Sync with rtl_tx:
5845 * - publish queue status and cur_tx ring index (write barrier)
5846 * - refresh dirty_tx ring index (read barrier).
5847 * May the current thread have a pessimistic view of the ring
5848 * status and forget to wake up queue, a racing rtl_tx thread
5849 * can't.
5850 */
1e874e04 5851 smp_mb();
477206a0 5852 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5853 netif_wake_queue(dev);
5854 }
5855
61357325 5856 return NETDEV_TX_OK;
1da177e4 5857
3eafe507 5858err_dma_1:
48addcc9 5859 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5860err_dma_0:
5861 dev_kfree_skb(skb);
5862 dev->stats.tx_dropped++;
5863 return NETDEV_TX_OK;
5864
5865err_stop_0:
1da177e4 5866 netif_stop_queue(dev);
cebf8cc7 5867 dev->stats.tx_dropped++;
61357325 5868 return NETDEV_TX_BUSY;
1da177e4
LT		 5869}
5870
5871static void rtl8169_pcierr_interrupt(struct net_device *dev)
5872{
5873 struct rtl8169_private *tp = netdev_priv(dev);
5874 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5875 u16 pci_status, pci_cmd;
5876
5877 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5878 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5879
bf82c189
JP		 5880 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5881 pci_cmd, pci_status);
1da177e4
LT		 5882
5883 /*
5884 * The recovery sequence below admits a very elaborated explanation:
5885 * - it seems to work;
d03902b8
FR		 5886 * - I did not see what else could be done;
5887 * - it makes iop3xx happy.
1da177e4
LT		 5888 *
5889 * Feel free to adjust to your needs.
5890 */
a27993f3 5891 if (pdev->broken_parity_status)
d03902b8
FR		 5892 pci_cmd &= ~PCI_COMMAND_PARITY;
5893 else
5894 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5895
5896 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5897
5898 pci_write_config_word(pdev, PCI_STATUS,
5899 pci_status & (PCI_STATUS_DETECTED_PARITY |
5900 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5901 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5902
5903 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 5904 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 5905 void __iomem *ioaddr = tp->mmio_addr;
5906
bf82c189 5907 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5908 tp->cp_cmd &= ~PCIDAC;
5909 RTL_W16(CPlusCmd, tp->cp_cmd);
5910 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5911 }
5912
e6de30d6 5913 rtl8169_hw_reset(tp);
d03902b8 5914
98ddf986 5915 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5916}
5917
da78dbff 5918static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5919{
5920 unsigned int dirty_tx, tx_left;
5921
1da177e4
LT		 5922 dirty_tx = tp->dirty_tx;
5923 smp_rmb();
5924 tx_left = tp->cur_tx - dirty_tx;
5925
5926 while (tx_left > 0) {
5927 unsigned int entry = dirty_tx % NUM_TX_DESC;
5928 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5929 u32 status;
5930
5931 rmb();
5932 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5933 if (status & DescOwn)
5934 break;
5935
48addcc9
SG		 5936 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5937 tp->TxDescArray + entry);
1da177e4 5938 if (status & LastFrag) {
17bcb684
FR		 5939 u64_stats_update_begin(&tp->tx_stats.syncp);
5940 tp->tx_stats.packets++;
5941 tp->tx_stats.bytes += tx_skb->skb->len;
5942 u64_stats_update_end(&tp->tx_stats.syncp);
5943 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5944 tx_skb->skb = NULL;
5945 }
5946 dirty_tx++;
5947 tx_left--;
5948 }
5949
5950 if (tp->dirty_tx != dirty_tx) {
5951 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5952 /* Sync with rtl8169_start_xmit:
5953 * - publish dirty_tx ring index (write barrier)
5954 * - refresh cur_tx ring index and queue status (read barrier)
5955 * May the current thread miss the stopped queue condition,
5956 * a racing xmit thread can only have a right view of the
5957 * ring status.
5958 */
1e874e04 5959 smp_mb();
1da177e4 5960 if (netif_queue_stopped(dev) &&
477206a0 5961 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5962 netif_wake_queue(dev);
5963 }
d78ae2dc
FR		 5964 /*
5965 * 8168 hack: TxPoll requests are lost when the Tx packets are
5966 * too close. Let's kick an extra TxPoll request when a burst
5967 * of start_xmit activity is detected (if it is not detected,
5968 * it is slow enough). -- FR
5969 */
da78dbff
FR		 5970 if (tp->cur_tx != dirty_tx) {
5971 void __iomem *ioaddr = tp->mmio_addr;
5972
d78ae2dc 5973 RTL_W8(TxPoll, NPQ);
da78dbff 5974 }
1da177e4
LT		 5975 }
5976}
5977
126fa4b9
FR		 5978static inline int rtl8169_fragmented_frame(u32 status)
5979{
5980 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5981}
5982
adea1ac7 5983static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5984{
1da177e4
LT		 5985 u32 status = opts1 & RxProtoMask;
5986
5987 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5988 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5989 skb->ip_summed = CHECKSUM_UNNECESSARY;
5990 else
bc8acf2c 5991 skb_checksum_none_assert(skb);
1da177e4
LT		 5992}
5993
6f0333b8
ED		 5994static struct sk_buff *rtl8169_try_rx_copy(void *data,
5995 struct rtl8169_private *tp,
5996 int pkt_size,
5997 dma_addr_t addr)
1da177e4 5998{
b449655f 5999 struct sk_buff *skb;
48addcc9 6000 struct device *d = &tp->pci_dev->dev;
b449655f 6001
6f0333b8 6002 data = rtl8169_align(data);
48addcc9 6003 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6004 prefetch(data);
6005 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6006 if (skb)
6007 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6008 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6009
6f0333b8 6010 return skb;
1da177e4
LT		 6011}
6012
da78dbff 6013static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6014{
6015 unsigned int cur_rx, rx_left;
6f0333b8 6016 unsigned int count;
1da177e4 6017
1da177e4 6018 cur_rx = tp->cur_rx;
1da177e4 6019
9fba0812 6020 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6021 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6022 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6023 u32 status;
6024
6025 rmb();
e03f33af 6026 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6027
6028 if (status & DescOwn)
6029 break;
4dcb7d33 6030 if (unlikely(status & RxRES)) {
bf82c189
JP		 6031 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6032 status);
cebf8cc7 6033 dev->stats.rx_errors++;
1da177e4 6034 if (status & (RxRWT | RxRUNT))
cebf8cc7 6035 dev->stats.rx_length_errors++;
1da177e4 6036 if (status & RxCRC)
cebf8cc7 6037 dev->stats.rx_crc_errors++;
9dccf611 6038 if (status & RxFOVF) {
da78dbff 6039 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6040 dev->stats.rx_fifo_errors++;
9dccf611 6041 }
6bbe021d
BG		 6042 if ((status & (RxRUNT | RxCRC)) &&
6043 !(status & (RxRWT | RxFOVF)) &&
6044 (dev->features & NETIF_F_RXALL))
6045 goto process_pkt;
1da177e4 6046 } else {
6f0333b8 6047 struct sk_buff *skb;
6bbe021d
BG		 6048 dma_addr_t addr;
6049 int pkt_size;
6050
6051process_pkt:
6052 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6053 if (likely(!(dev->features & NETIF_F_RXFCS)))
6054 pkt_size = (status & 0x00003fff) - 4;
6055 else
6056 pkt_size = status & 0x00003fff;
1da177e4 6057
126fa4b9
FR		 6058 /*
6059 * The driver does not support incoming fragmented
6060 * frames. They are seen as a symptom of over-mtu
6061 * sized frames.
6062 */
6063 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6064 dev->stats.rx_dropped++;
6065 dev->stats.rx_length_errors++;
ce11ff5e 6066 goto release_descriptor;
126fa4b9
FR		 6067 }
6068
6f0333b8
ED		 6069 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6070 tp, pkt_size, addr);
6f0333b8
ED		 6071 if (!skb) {
6072 dev->stats.rx_dropped++;
ce11ff5e 6073 goto release_descriptor;
1da177e4
LT		 6074 }
6075
adea1ac7 6076 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6077 skb_put(skb, pkt_size);
6078 skb->protocol = eth_type_trans(skb, dev);
6079
7a8fc77b
FR		 6080 rtl8169_rx_vlan_tag(desc, skb);
6081
56de414c 6082 napi_gro_receive(&tp->napi, skb);
1da177e4 6083
8027aa24
JW		 6084 u64_stats_update_begin(&tp->rx_stats.syncp);
6085 tp->rx_stats.packets++;
6086 tp->rx_stats.bytes += pkt_size;
6087 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6088 }
ce11ff5e 6089release_descriptor:
6090 desc->opts2 = 0;
6091 wmb();
6092 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 6093 }
6094
6095 count = cur_rx - tp->cur_rx;
6096 tp->cur_rx = cur_rx;
6097
1da177e4
LT		 6098 return count;
6099}
6100
07d3f51f 6101static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6102{
07d3f51f 6103 struct net_device *dev = dev_instance;
1da177e4 6104 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6105 int handled = 0;
9085cdfa 6106 u16 status;
1da177e4 6107
9085cdfa 6108 status = rtl_get_events(tp);
da78dbff
FR		 6109 if (status && status != 0xffff) {
6110 status &= RTL_EVENT_NAPI | tp->event_slow;
6111 if (status) {
6112 handled = 1;
1da177e4 6113
da78dbff
FR		 6114 rtl_irq_disable(tp);
6115 napi_schedule(&tp->napi);
f11a377b 6116 }
da78dbff
FR		 6117 }
6118 return IRQ_RETVAL(handled);
6119}
1da177e4 6120
da78dbff
FR		 6121/*
6122 * Workqueue context.
6123 */
6124static void rtl_slow_event_work(struct rtl8169_private *tp)
6125{
6126 struct net_device *dev = tp->dev;
6127 u16 status;
6128
6129 status = rtl_get_events(tp) & tp->event_slow;
6130 rtl_ack_events(tp, status);
1da177e4 6131
da78dbff
FR		 6132 if (unlikely(status & RxFIFOOver)) {
6133 switch (tp->mac_version) {
6134 /* Work around for rx fifo overflow */
6135 case RTL_GIGA_MAC_VER_11:
6136 netif_stop_queue(dev);
934714d0
FR		 6137 /* XXX - Hack alert. See rtl_task(). */
6138 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6139 default:
f11a377b
DD		 6140 break;
6141 }
da78dbff 6142 }
1da177e4 6143
da78dbff
FR		 6144 if (unlikely(status & SYSErr))
6145 rtl8169_pcierr_interrupt(dev);
0e485150 6146
da78dbff
FR		 6147 if (status & LinkChg)
6148 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6149
7dbb4918 6150 rtl_irq_enable_all(tp);
1da177e4
LT		 6151}
6152
4422bcd4
FR		 6153static void rtl_task(struct work_struct *work)
6154{
da78dbff
FR		 6155 static const struct {
6156 int bitnr;
6157 void (*action)(struct rtl8169_private *);
6158 } rtl_work[] = {
934714d0 6159 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6160 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6161 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6162 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6163 };
4422bcd4
FR		 6164 struct rtl8169_private *tp =
6165 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6166 struct net_device *dev = tp->dev;
6167 int i;
6168
6169 rtl_lock_work(tp);
6170
6c4a70c5
FR		 6171 if (!netif_running(dev) ||
6172 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6173 goto out_unlock;
6174
6175 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6176 bool pending;
6177
da78dbff 6178 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6179 if (pending)
6180 rtl_work[i].action(tp);
6181 }
4422bcd4 6182
da78dbff
FR		 6183out_unlock:
6184 rtl_unlock_work(tp);
4422bcd4
FR		 6185}
6186
bea3348e 6187static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6188{
bea3348e
SH		 6189 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6190 struct net_device *dev = tp->dev;
da78dbff
FR		 6191 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6192 int work_done= 0;
6193 u16 status;
6194
6195 status = rtl_get_events(tp);
6196 rtl_ack_events(tp, status & ~tp->event_slow);
6197
6198 if (status & RTL_EVENT_NAPI_RX)
6199 work_done = rtl_rx(dev, tp, (u32) budget);
6200
6201 if (status & RTL_EVENT_NAPI_TX)
6202 rtl_tx(dev, tp);
1da177e4 6203
da78dbff
FR		 6204 if (status & tp->event_slow) {
6205 enable_mask &= ~tp->event_slow;
6206
6207 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6208 }
1da177e4 6209
bea3348e 6210 if (work_done < budget) {
288379f0 6211 napi_complete(napi);
f11a377b 6212
da78dbff
FR		 6213 rtl_irq_enable(tp, enable_mask);
6214 mmiowb();
1da177e4
LT		 6215 }
6216
bea3348e 6217 return work_done;
1da177e4 6218}
1da177e4 6219
523a6094
FR		 6220static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6221{
6222 struct rtl8169_private *tp = netdev_priv(dev);
6223
6224 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6225 return;
6226
6227 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6228 RTL_W32(RxMissed, 0);
6229}
6230
1da177e4
LT		 6231static void rtl8169_down(struct net_device *dev)
6232{
6233 struct rtl8169_private *tp = netdev_priv(dev);
6234 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6235
4876cc1e 6236 del_timer_sync(&tp->timer);
1da177e4 6237
93dd79e8 6238 napi_disable(&tp->napi);
da78dbff 6239 netif_stop_queue(dev);
1da177e4 6240
92fc43b4 6241 rtl8169_hw_reset(tp);
323bb685
SG		 6242 /*
6243 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6244 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6245 * and napi is disabled (rtl8169_poll).
323bb685 6246 */
523a6094 6247 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6248
1da177e4 6249 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6250 synchronize_sched();
1da177e4 6251
1da177e4
LT		 6252 rtl8169_tx_clear(tp);
6253
6254 rtl8169_rx_clear(tp);
065c27c1 6255
6256 rtl_pll_power_down(tp);
1da177e4
LT		 6257}
6258
6259static int rtl8169_close(struct net_device *dev)
6260{
6261 struct rtl8169_private *tp = netdev_priv(dev);
6262 struct pci_dev *pdev = tp->pci_dev;
6263
e1759441
RW		 6264 pm_runtime_get_sync(&pdev->dev);
6265
cecb5fd7 6266 /* Update counters before going down */
355423d0
IV		 6267 rtl8169_update_counters(dev);
6268
da78dbff 6269 rtl_lock_work(tp);
6c4a70c5 6270 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6271
1da177e4 6272 rtl8169_down(dev);
da78dbff 6273 rtl_unlock_work(tp);
1da177e4 6274
92a7c4e7 6275 free_irq(pdev->irq, dev);
1da177e4 6276
82553bb6
SG		 6277 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6278 tp->RxPhyAddr);
6279 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6280 tp->TxPhyAddr);
1da177e4
LT		 6281 tp->TxDescArray = NULL;
6282 tp->RxDescArray = NULL;
6283
e1759441
RW		 6284 pm_runtime_put_sync(&pdev->dev);
6285
1da177e4
LT		 6286 return 0;
6287}
6288
dc1c00ce
FR		 6289#ifdef CONFIG_NET_POLL_CONTROLLER
6290static void rtl8169_netpoll(struct net_device *dev)
6291{
6292 struct rtl8169_private *tp = netdev_priv(dev);
6293
6294 rtl8169_interrupt(tp->pci_dev->irq, dev);
6295}
6296#endif
6297
df43ac78
FR		 6298static int rtl_open(struct net_device *dev)
6299{
6300 struct rtl8169_private *tp = netdev_priv(dev);
6301 void __iomem *ioaddr = tp->mmio_addr;
6302 struct pci_dev *pdev = tp->pci_dev;
6303 int retval = -ENOMEM;
6304
6305 pm_runtime_get_sync(&pdev->dev);
6306
6307 /*
e75d6606 6308 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6309 * dma_alloc_coherent provides more.
6310 */
6311 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6312 &tp->TxPhyAddr, GFP_KERNEL);
6313 if (!tp->TxDescArray)
6314 goto err_pm_runtime_put;
6315
6316 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6317 &tp->RxPhyAddr, GFP_KERNEL);
6318 if (!tp->RxDescArray)
6319 goto err_free_tx_0;
6320
6321 retval = rtl8169_init_ring(dev);
6322 if (retval < 0)
6323 goto err_free_rx_1;
6324
6325 INIT_WORK(&tp->wk.work, rtl_task);
6326
6327 smp_mb();
6328
6329 rtl_request_firmware(tp);
6330
92a7c4e7 6331 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6332 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6333 dev->name, dev);
6334 if (retval < 0)
6335 goto err_release_fw_2;
6336
6337 rtl_lock_work(tp);
6338
6339 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6340
6341 napi_enable(&tp->napi);
6342
6343 rtl8169_init_phy(dev, tp);
6344
6345 __rtl8169_set_features(dev, dev->features);
6346
6347 rtl_pll_power_up(tp);
6348
6349 rtl_hw_start(dev);
6350
6351 netif_start_queue(dev);
6352
6353 rtl_unlock_work(tp);
6354
6355 tp->saved_wolopts = 0;
6356 pm_runtime_put_noidle(&pdev->dev);
6357
6358 rtl8169_check_link_status(dev, tp, ioaddr);
6359out:
6360 return retval;
6361
6362err_release_fw_2:
6363 rtl_release_firmware(tp);
6364 rtl8169_rx_clear(tp);
6365err_free_rx_1:
6366 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6367 tp->RxPhyAddr);
6368 tp->RxDescArray = NULL;
6369err_free_tx_0:
6370 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6371 tp->TxPhyAddr);
6372 tp->TxDescArray = NULL;
6373err_pm_runtime_put:
6374 pm_runtime_put_noidle(&pdev->dev);
6375 goto out;
6376}
6377
8027aa24
JW		 6378static struct rtnl_link_stats64 *
6379rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6380{
6381 struct rtl8169_private *tp = netdev_priv(dev);
6382 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6383 unsigned int start;
1da177e4 6384
da78dbff 6385 if (netif_running(dev))
523a6094 6386 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6387
8027aa24
JW		 6388 do {
6389 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6390 stats->rx_packets = tp->rx_stats.packets;
6391 stats->rx_bytes = tp->rx_stats.bytes;
6392 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6393
6394
6395 do {
6396 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6397 stats->tx_packets = tp->tx_stats.packets;
6398 stats->tx_bytes = tp->tx_stats.bytes;
6399 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6400
6401 stats->rx_dropped = dev->stats.rx_dropped;
6402 stats->tx_dropped = dev->stats.tx_dropped;
6403 stats->rx_length_errors = dev->stats.rx_length_errors;
6404 stats->rx_errors = dev->stats.rx_errors;
6405 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6406 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6407 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6408
6409 return stats;
1da177e4
LT		 6410}
6411
861ab440 6412static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6413{
065c27c1 6414 struct rtl8169_private *tp = netdev_priv(dev);
6415
5d06a99f 6416 if (!netif_running(dev))
861ab440 6417 return;
5d06a99f
FR		 6418
6419 netif_device_detach(dev);
6420 netif_stop_queue(dev);
da78dbff
FR		 6421
6422 rtl_lock_work(tp);
6423 napi_disable(&tp->napi);
6c4a70c5 6424 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6425 rtl_unlock_work(tp);
6426
6427 rtl_pll_power_down(tp);
861ab440
RW		 6428}
6429
6430#ifdef CONFIG_PM
6431
6432static int rtl8169_suspend(struct device *device)
6433{
6434 struct pci_dev *pdev = to_pci_dev(device);
6435 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6436
861ab440 6437 rtl8169_net_suspend(dev);
1371fa6d 6438
5d06a99f
FR		 6439 return 0;
6440}
6441
e1759441
RW		 6442static void __rtl8169_resume(struct net_device *dev)
6443{
065c27c1 6444 struct rtl8169_private *tp = netdev_priv(dev);
6445
e1759441 6446 netif_device_attach(dev);
065c27c1 6447
6448 rtl_pll_power_up(tp);
6449
cff4c162
AS		 6450 rtl_lock_work(tp);
6451 napi_enable(&tp->napi);
6c4a70c5 6452 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6453 rtl_unlock_work(tp);
da78dbff 6454
98ddf986 6455 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6456}
6457
861ab440 6458static int rtl8169_resume(struct device *device)
5d06a99f 6459{
861ab440 6460 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6461 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6462 struct rtl8169_private *tp = netdev_priv(dev);
6463
6464 rtl8169_init_phy(dev, tp);
5d06a99f 6465
e1759441
RW		 6466 if (netif_running(dev))
6467 __rtl8169_resume(dev);
5d06a99f 6468
e1759441
RW		 6469 return 0;
6470}
6471
6472static int rtl8169_runtime_suspend(struct device *device)
6473{
6474 struct pci_dev *pdev = to_pci_dev(device);
6475 struct net_device *dev = pci_get_drvdata(pdev);
6476 struct rtl8169_private *tp = netdev_priv(dev);
6477
6478 if (!tp->TxDescArray)
6479 return 0;
6480
da78dbff 6481 rtl_lock_work(tp);
e1759441
RW		 6482 tp->saved_wolopts = __rtl8169_get_wol(tp);
6483 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6484 rtl_unlock_work(tp);
e1759441
RW		 6485
6486 rtl8169_net_suspend(dev);
6487
6488 return 0;
6489}
6490
6491static int rtl8169_runtime_resume(struct device *device)
6492{
6493 struct pci_dev *pdev = to_pci_dev(device);
6494 struct net_device *dev = pci_get_drvdata(pdev);
6495 struct rtl8169_private *tp = netdev_priv(dev);
6496
6497 if (!tp->TxDescArray)
6498 return 0;
6499
da78dbff 6500 rtl_lock_work(tp);
e1759441
RW		 6501 __rtl8169_set_wol(tp, tp->saved_wolopts);
6502 tp->saved_wolopts = 0;
da78dbff 6503 rtl_unlock_work(tp);
e1759441 6504
fccec10b
SG		 6505 rtl8169_init_phy(dev, tp);
6506
e1759441 6507 __rtl8169_resume(dev);
5d06a99f 6508
5d06a99f
FR		 6509 return 0;
6510}
6511
e1759441
RW		 6512static int rtl8169_runtime_idle(struct device *device)
6513{
6514 struct pci_dev *pdev = to_pci_dev(device);
6515 struct net_device *dev = pci_get_drvdata(pdev);
6516 struct rtl8169_private *tp = netdev_priv(dev);
6517
e4fbce74 6518 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6519}
6520
47145210 6521static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6522 .suspend = rtl8169_suspend,
6523 .resume = rtl8169_resume,
6524 .freeze = rtl8169_suspend,
6525 .thaw = rtl8169_resume,
6526 .poweroff = rtl8169_suspend,
6527 .restore = rtl8169_resume,
6528 .runtime_suspend = rtl8169_runtime_suspend,
6529 .runtime_resume = rtl8169_runtime_resume,
6530 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6531};
6532
6533#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6534
6535#else /* !CONFIG_PM */
6536
6537#define RTL8169_PM_OPS NULL
6538
6539#endif /* !CONFIG_PM */
6540
649b3b8c 6541static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6542{
6543 void __iomem *ioaddr = tp->mmio_addr;
6544
6545 /* WoL fails with 8168b when the receiver is disabled. */
6546 switch (tp->mac_version) {
6547 case RTL_GIGA_MAC_VER_11:
6548 case RTL_GIGA_MAC_VER_12:
6549 case RTL_GIGA_MAC_VER_17:
6550 pci_clear_master(tp->pci_dev);
6551
6552 RTL_W8(ChipCmd, CmdRxEnb);
6553 /* PCI commit */
6554 RTL_R8(ChipCmd);
6555 break;
6556 default:
6557 break;
6558 }
6559}
6560
1765f95d
FR		 6561static void rtl_shutdown(struct pci_dev *pdev)
6562{
861ab440 6563 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6564 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6565 struct device *d = &pdev->dev;
6566
6567 pm_runtime_get_sync(d);
861ab440
RW		 6568
6569 rtl8169_net_suspend(dev);
1765f95d 6570
cecb5fd7 6571 /* Restore original MAC address */
cc098dc7
IV		 6572 rtl_rar_set(tp, dev->perm_addr);
6573
92fc43b4 6574 rtl8169_hw_reset(tp);
4bb3f522 6575
861ab440 6576 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6577 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6578 rtl_wol_suspend_quirk(tp);
6579 rtl_wol_shutdown_quirk(tp);
ca52efd5 6580 }
6581
861ab440
RW		 6582 pci_wake_from_d3(pdev, true);
6583 pci_set_power_state(pdev, PCI_D3hot);
6584 }
2a15cd2f 6585
6586 pm_runtime_put_noidle(d);
861ab440 6587}
5d06a99f 6588
baf63293 6589static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6590{
6591 struct net_device *dev = pci_get_drvdata(pdev);
6592 struct rtl8169_private *tp = netdev_priv(dev);
6593
6594 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6595 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6596 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6597 rtl8168_driver_stop(tp);
6598 }
6599
6600 cancel_work_sync(&tp->wk.work);
6601
ad1be8d3
DN		 6602 netif_napi_del(&tp->napi);
6603
e27566ed
FR		 6604 unregister_netdev(dev);
6605
6606 rtl_release_firmware(tp);
6607
6608 if (pci_dev_run_wake(pdev))
6609 pm_runtime_get_noresume(&pdev->dev);
6610
6611 /* restore original MAC address */
6612 rtl_rar_set(tp, dev->perm_addr);
6613
6614 rtl_disable_msi(pdev, tp);
6615 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6616 pci_set_drvdata(pdev, NULL);
6617}
6618
fa9c385e 6619static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6620 .ndo_open = rtl_open,
fa9c385e
FR		 6621 .ndo_stop = rtl8169_close,
6622 .ndo_get_stats64 = rtl8169_get_stats64,
6623 .ndo_start_xmit = rtl8169_start_xmit,
6624 .ndo_tx_timeout = rtl8169_tx_timeout,
6625 .ndo_validate_addr = eth_validate_addr,
6626 .ndo_change_mtu = rtl8169_change_mtu,
6627 .ndo_fix_features = rtl8169_fix_features,
6628 .ndo_set_features = rtl8169_set_features,
6629 .ndo_set_mac_address = rtl_set_mac_address,
6630 .ndo_do_ioctl = rtl8169_ioctl,
6631 .ndo_set_rx_mode = rtl_set_rx_mode,
6632#ifdef CONFIG_NET_POLL_CONTROLLER
6633 .ndo_poll_controller = rtl8169_netpoll,
6634#endif
6635
6636};
6637
31fa8b18
FR		 6638static const struct rtl_cfg_info {
6639 void (*hw_start)(struct net_device *);
6640 unsigned int region;
6641 unsigned int align;
6642 u16 event_slow;
6643 unsigned features;
6644 u8 default_ver;
6645} rtl_cfg_infos [] = {
6646 [RTL_CFG_0] = {
6647 .hw_start = rtl_hw_start_8169,
6648 .region = 1,
6649 .align = 0,
6650 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6651 .features = RTL_FEATURE_GMII,
6652 .default_ver = RTL_GIGA_MAC_VER_01,
6653 },
6654 [RTL_CFG_1] = {
6655 .hw_start = rtl_hw_start_8168,
6656 .region = 2,
6657 .align = 8,
6658 .event_slow = SYSErr | LinkChg | RxOverflow,
6659 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6660 .default_ver = RTL_GIGA_MAC_VER_11,
6661 },
6662 [RTL_CFG_2] = {
6663 .hw_start = rtl_hw_start_8101,
6664 .region = 2,
6665 .align = 8,
6666 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6667 PCSTimeout,
6668 .features = RTL_FEATURE_MSI,
6669 .default_ver = RTL_GIGA_MAC_VER_13,
6670 }
6671};
6672
6673/* Cfg9346_Unlock assumed. */
6674static unsigned rtl_try_msi(struct rtl8169_private *tp,
6675 const struct rtl_cfg_info *cfg)
6676{
6677 void __iomem *ioaddr = tp->mmio_addr;
6678 unsigned msi = 0;
6679 u8 cfg2;
6680
6681 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6682 if (cfg->features & RTL_FEATURE_MSI) {
6683 if (pci_enable_msi(tp->pci_dev)) {
6684 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6685 } else {
6686 cfg2 |= MSIEnable;
6687 msi = RTL_FEATURE_MSI;
6688 }
6689 }
6690 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6691 RTL_W8(Config2, cfg2);
6692 return msi;
6693}
6694
c558386b
HW		 6695DECLARE_RTL_COND(rtl_link_list_ready_cond)
6696{
6697 void __iomem *ioaddr = tp->mmio_addr;
6698
6699 return RTL_R8(MCU) & LINK_LIST_RDY;
6700}
6701
6702DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6703{
6704 void __iomem *ioaddr = tp->mmio_addr;
6705
6706 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6707}
6708
baf63293 6709static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 6710{
6711 void __iomem *ioaddr = tp->mmio_addr;
6712 u32 data;
6713
6714 tp->ocp_base = OCP_STD_PHY_BASE;
6715
6716 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6717
6718 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6719 return;
6720
6721 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6722 return;
6723
6724 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6725 msleep(1);
6726 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6727
5f8bcce9 6728 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6729 data &= ~(1 << 14);
6730 r8168_mac_ocp_write(tp, 0xe8de, data);
6731
6732 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6733 return;
6734
5f8bcce9 6735 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6736 data |= (1 << 15);
6737 r8168_mac_ocp_write(tp, 0xe8de, data);
6738
6739 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6740 return;
6741}
6742
baf63293 6743static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 6744{
6745 switch (tp->mac_version) {
6746 case RTL_GIGA_MAC_VER_40:
6747 case RTL_GIGA_MAC_VER_41:
6748 rtl_hw_init_8168g(tp);
6749 break;
6750
6751 default:
6752 break;
6753 }
6754}
6755
baf63293 6756static int
3b6cf25d
FR		 6757rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6758{
6759 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6760 const unsigned int region = cfg->region;
6761 struct rtl8169_private *tp;
6762 struct mii_if_info *mii;
6763 struct net_device *dev;
6764 void __iomem *ioaddr;
6765 int chipset, i;
6766 int rc;
6767
6768 if (netif_msg_drv(&debug)) {
6769 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6770 MODULENAME, RTL8169_VERSION);
6771 }
6772
6773 dev = alloc_etherdev(sizeof (*tp));
6774 if (!dev) {
6775 rc = -ENOMEM;
6776 goto out;
6777 }
6778
6779 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6780 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6781 tp = netdev_priv(dev);
6782 tp->dev = dev;
6783 tp->pci_dev = pdev;
6784 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6785
6786 mii = &tp->mii;
6787 mii->dev = dev;
6788 mii->mdio_read = rtl_mdio_read;
6789 mii->mdio_write = rtl_mdio_write;
6790 mii->phy_id_mask = 0x1f;
6791 mii->reg_num_mask = 0x1f;
6792 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6793
6794 /* disable ASPM completely as that cause random device stop working
6795 * problems as well as full system hangs for some PCIe devices users */
6796 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6797 PCIE_LINK_STATE_CLKPM);
6798
6799 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6800 rc = pci_enable_device(pdev);
6801 if (rc < 0) {
6802 netif_err(tp, probe, dev, "enable failure\n");
6803 goto err_out_free_dev_1;
6804 }
6805
6806 if (pci_set_mwi(pdev) < 0)
6807 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6808
6809 /* make sure PCI base addr 1 is MMIO */
6810 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6811 netif_err(tp, probe, dev,
6812 "region #%d not an MMIO resource, aborting\n",
6813 region);
6814 rc = -ENODEV;
6815 goto err_out_mwi_2;
6816 }
6817
6818 /* check for weird/broken PCI region reporting */
6819 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6820 netif_err(tp, probe, dev,
6821 "Invalid PCI region size(s), aborting\n");
6822 rc = -ENODEV;
6823 goto err_out_mwi_2;
6824 }
6825
6826 rc = pci_request_regions(pdev, MODULENAME);
6827 if (rc < 0) {
6828 netif_err(tp, probe, dev, "could not request regions\n");
6829 goto err_out_mwi_2;
6830 }
6831
6832 tp->cp_cmd = RxChkSum;
6833
6834 if ((sizeof(dma_addr_t) > 4) &&
6835 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6836 tp->cp_cmd |= PCIDAC;
6837 dev->features |= NETIF_F_HIGHDMA;
6838 } else {
6839 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6840 if (rc < 0) {
6841 netif_err(tp, probe, dev, "DMA configuration failed\n");
6842 goto err_out_free_res_3;
6843 }
6844 }
6845
6846 /* ioremap MMIO region */
6847 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6848 if (!ioaddr) {
6849 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6850 rc = -EIO;
6851 goto err_out_free_res_3;
6852 }
6853 tp->mmio_addr = ioaddr;
6854
6855 if (!pci_is_pcie(pdev))
6856 netif_info(tp, probe, dev, "not PCI Express\n");
6857
6858 /* Identify chip attached to board */
6859 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6860
6861 rtl_init_rxcfg(tp);
6862
6863 rtl_irq_disable(tp);
6864
c558386b
HW		 6865 rtl_hw_initialize(tp);
6866
3b6cf25d
FR		 6867 rtl_hw_reset(tp);
6868
6869 rtl_ack_events(tp, 0xffff);
6870
6871 pci_set_master(pdev);
6872
6873 /*
6874 * Pretend we are using VLANs; This bypasses a nasty bug where
6875 * Interrupts stop flowing on high load on 8110SCd controllers.
6876 */
6877 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6878 tp->cp_cmd |= RxVlan;
6879
6880 rtl_init_mdio_ops(tp);
6881 rtl_init_pll_power_ops(tp);
6882 rtl_init_jumbo_ops(tp);
beb1fe18 6883 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6884
6885 rtl8169_print_mac_version(tp);
6886
6887 chipset = tp->mac_version;
6888 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6889
6890 RTL_W8(Cfg9346, Cfg9346_Unlock);
6891 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6892 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6893 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6894 tp->features |= RTL_FEATURE_WOL;
6895 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6896 tp->features |= RTL_FEATURE_WOL;
6897 tp->features |= rtl_try_msi(tp, cfg);
6898 RTL_W8(Cfg9346, Cfg9346_Lock);
6899
6900 if (rtl_tbi_enabled(tp)) {
6901 tp->set_speed = rtl8169_set_speed_tbi;
6902 tp->get_settings = rtl8169_gset_tbi;
6903 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6904 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6905 tp->link_ok = rtl8169_tbi_link_ok;
6906 tp->do_ioctl = rtl_tbi_ioctl;
6907 } else {
6908 tp->set_speed = rtl8169_set_speed_xmii;
6909 tp->get_settings = rtl8169_gset_xmii;
6910 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6911 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6912 tp->link_ok = rtl8169_xmii_link_ok;
6913 tp->do_ioctl = rtl_xmii_ioctl;
6914 }
6915
6916 mutex_init(&tp->wk.mutex);
6917
6918 /* Get MAC address */
6919 for (i = 0; i < ETH_ALEN; i++)
6920 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d
FR		 6921
6922 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6923 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6924
6925 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6926
6927 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6928 * properly for all devices */
6929 dev->features |= NETIF_F_RXCSUM |
6930 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6931
6932 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6933 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6934 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6935 NETIF_F_HIGHDMA;
6936
6937 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6938 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6939 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6940
6941 dev->hw_features |= NETIF_F_RXALL;
6942 dev->hw_features |= NETIF_F_RXFCS;
6943
6944 tp->hw_start = cfg->hw_start;
6945 tp->event_slow = cfg->event_slow;
6946
6947 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6948 ~(RxBOVF | RxFOVF) : ~0;
6949
6950 init_timer(&tp->timer);
6951 tp->timer.data = (unsigned long) dev;
6952 tp->timer.function = rtl8169_phy_timer;
6953
6954 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6955
6956 rc = register_netdev(dev);
6957 if (rc < 0)
6958 goto err_out_msi_4;
6959
6960 pci_set_drvdata(pdev, dev);
6961
92a7c4e7
FR		 6962 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6963 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6964 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6965 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6966 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6967 "tx checksumming: %s]\n",
6968 rtl_chip_infos[chipset].jumbo_max,
6969 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6970 }
6971
6972 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6973 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6974 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6975 rtl8168_driver_start(tp);
6976 }
6977
6978 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6979
6980 if (pci_dev_run_wake(pdev))
6981 pm_runtime_put_noidle(&pdev->dev);
6982
6983 netif_carrier_off(dev);
6984
6985out:
6986 return rc;
6987
6988err_out_msi_4:
ad1be8d3 6989 netif_napi_del(&tp->napi);
3b6cf25d
FR		 6990 rtl_disable_msi(pdev, tp);
6991 iounmap(ioaddr);
6992err_out_free_res_3:
6993 pci_release_regions(pdev);
6994err_out_mwi_2:
6995 pci_clear_mwi(pdev);
6996 pci_disable_device(pdev);
6997err_out_free_dev_1:
6998 free_netdev(dev);
6999 goto out;
7000}
7001
1da177e4
LT		 7002static struct pci_driver rtl8169_pci_driver = {
7003 .name = MODULENAME,
7004 .id_table = rtl8169_pci_tbl,
3b6cf25d 7005 .probe = rtl_init_one,
baf63293 7006 .remove = rtl_remove_one,
1765f95d 7007 .shutdown = rtl_shutdown,
861ab440 7008 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7009};
7010
3eeb7da9 7011module_pci_driver(rtl8169_pci_driver);
Linux kernel - Deliverables
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