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c156633f SS |
1 | /* Renesas Ethernet AVB device driver |
2 | * | |
3 | * Copyright (C) 2014-2015 Renesas Electronics Corporation | |
4 | * Copyright (C) 2015 Renesas Solutions Corp. | |
568b3ce7 | 5 | * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> |
c156633f SS |
6 | * |
7 | * Based on the SuperH Ethernet driver | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License version 2, | |
11 | * as published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #ifndef __RAVB_H__ | |
15 | #define __RAVB_H__ | |
16 | ||
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mdio-bitbang.h> | |
21 | #include <linux/netdevice.h> | |
22 | #include <linux/phy.h> | |
a0d2f206 SS |
23 | #include <linux/platform_device.h> |
24 | #include <linux/ptp_clock_kernel.h> | |
c156633f SS |
25 | |
26 | #define BE_TX_RING_SIZE 64 /* TX ring size for Best Effort */ | |
27 | #define BE_RX_RING_SIZE 1024 /* RX ring size for Best Effort */ | |
28 | #define NC_TX_RING_SIZE 64 /* TX ring size for Network Control */ | |
29 | #define NC_RX_RING_SIZE 64 /* RX ring size for Network Control */ | |
30 | #define BE_TX_RING_MIN 64 | |
31 | #define BE_RX_RING_MIN 64 | |
32 | #define BE_TX_RING_MAX 1024 | |
33 | #define BE_RX_RING_MAX 2048 | |
34 | ||
35 | #define PKT_BUF_SZ 1538 | |
36 | ||
37 | /* Driver's parameters */ | |
38 | #define RAVB_ALIGN 128 | |
39 | ||
40 | /* Hardware time stamp */ | |
41 | #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */ | |
42 | #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */ | |
43 | ||
44 | #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */ | |
45 | #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */ | |
46 | #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002 | |
47 | #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006 | |
48 | #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */ | |
49 | ||
50 | enum ravb_reg { | |
51 | /* AVB-DMAC registers */ | |
52 | CCC = 0x0000, | |
53 | DBAT = 0x0004, | |
54 | DLR = 0x0008, | |
55 | CSR = 0x000C, | |
56 | CDAR0 = 0x0010, | |
57 | CDAR1 = 0x0014, | |
58 | CDAR2 = 0x0018, | |
59 | CDAR3 = 0x001C, | |
60 | CDAR4 = 0x0020, | |
61 | CDAR5 = 0x0024, | |
62 | CDAR6 = 0x0028, | |
63 | CDAR7 = 0x002C, | |
64 | CDAR8 = 0x0030, | |
65 | CDAR9 = 0x0034, | |
66 | CDAR10 = 0x0038, | |
67 | CDAR11 = 0x003C, | |
68 | CDAR12 = 0x0040, | |
69 | CDAR13 = 0x0044, | |
70 | CDAR14 = 0x0048, | |
71 | CDAR15 = 0x004C, | |
72 | CDAR16 = 0x0050, | |
73 | CDAR17 = 0x0054, | |
74 | CDAR18 = 0x0058, | |
75 | CDAR19 = 0x005C, | |
76 | CDAR20 = 0x0060, | |
77 | CDAR21 = 0x0064, | |
78 | ESR = 0x0088, | |
79 | RCR = 0x0090, | |
80 | RQC0 = 0x0094, | |
81 | RQC1 = 0x0098, | |
82 | RQC2 = 0x009C, | |
83 | RQC3 = 0x00A0, | |
84 | RQC4 = 0x00A4, | |
85 | RPC = 0x00B0, | |
86 | UFCW = 0x00BC, | |
87 | UFCS = 0x00C0, | |
88 | UFCV0 = 0x00C4, | |
89 | UFCV1 = 0x00C8, | |
90 | UFCV2 = 0x00CC, | |
91 | UFCV3 = 0x00D0, | |
92 | UFCV4 = 0x00D4, | |
93 | UFCD0 = 0x00E0, | |
94 | UFCD1 = 0x00E4, | |
95 | UFCD2 = 0x00E8, | |
96 | UFCD3 = 0x00EC, | |
97 | UFCD4 = 0x00F0, | |
98 | SFO = 0x00FC, | |
99 | SFP0 = 0x0100, | |
100 | SFP1 = 0x0104, | |
101 | SFP2 = 0x0108, | |
102 | SFP3 = 0x010C, | |
103 | SFP4 = 0x0110, | |
104 | SFP5 = 0x0114, | |
105 | SFP6 = 0x0118, | |
106 | SFP7 = 0x011C, | |
107 | SFP8 = 0x0120, | |
108 | SFP9 = 0x0124, | |
109 | SFP10 = 0x0128, | |
110 | SFP11 = 0x012C, | |
111 | SFP12 = 0x0130, | |
112 | SFP13 = 0x0134, | |
113 | SFP14 = 0x0138, | |
114 | SFP15 = 0x013C, | |
115 | SFP16 = 0x0140, | |
116 | SFP17 = 0x0144, | |
117 | SFP18 = 0x0148, | |
118 | SFP19 = 0x014C, | |
119 | SFP20 = 0x0150, | |
120 | SFP21 = 0x0154, | |
121 | SFP22 = 0x0158, | |
122 | SFP23 = 0x015C, | |
123 | SFP24 = 0x0160, | |
124 | SFP25 = 0x0164, | |
125 | SFP26 = 0x0168, | |
126 | SFP27 = 0x016C, | |
127 | SFP28 = 0x0170, | |
128 | SFP29 = 0x0174, | |
129 | SFP30 = 0x0178, | |
130 | SFP31 = 0x017C, | |
131 | SFM0 = 0x01C0, | |
132 | SFM1 = 0x01C4, | |
133 | TGC = 0x0300, | |
134 | TCCR = 0x0304, | |
135 | TSR = 0x0308, | |
136 | TFA0 = 0x0310, | |
137 | TFA1 = 0x0314, | |
138 | TFA2 = 0x0318, | |
139 | CIVR0 = 0x0320, | |
140 | CIVR1 = 0x0324, | |
141 | CDVR0 = 0x0328, | |
142 | CDVR1 = 0x032C, | |
143 | CUL0 = 0x0330, | |
144 | CUL1 = 0x0334, | |
145 | CLL0 = 0x0338, | |
146 | CLL1 = 0x033C, | |
147 | DIC = 0x0350, | |
148 | DIS = 0x0354, | |
149 | EIC = 0x0358, | |
150 | EIS = 0x035C, | |
151 | RIC0 = 0x0360, | |
152 | RIS0 = 0x0364, | |
153 | RIC1 = 0x0368, | |
154 | RIS1 = 0x036C, | |
155 | RIC2 = 0x0370, | |
156 | RIS2 = 0x0374, | |
157 | TIC = 0x0378, | |
158 | TIS = 0x037C, | |
159 | ISS = 0x0380, | |
160 | GCCR = 0x0390, | |
161 | GMTT = 0x0394, | |
162 | GPTC = 0x0398, | |
163 | GTI = 0x039C, | |
164 | GTO0 = 0x03A0, | |
165 | GTO1 = 0x03A4, | |
166 | GTO2 = 0x03A8, | |
167 | GIC = 0x03AC, | |
168 | GIS = 0x03B0, | |
169 | GCPT = 0x03B4, /* Undocumented? */ | |
170 | GCT0 = 0x03B8, | |
171 | GCT1 = 0x03BC, | |
172 | GCT2 = 0x03C0, | |
173 | ||
174 | /* E-MAC registers */ | |
175 | ECMR = 0x0500, | |
176 | RFLR = 0x0508, | |
177 | ECSR = 0x0510, | |
178 | ECSIPR = 0x0518, | |
179 | PIR = 0x0520, | |
180 | PSR = 0x0528, | |
181 | PIPR = 0x052c, | |
182 | MPR = 0x0558, | |
183 | PFTCR = 0x055c, | |
184 | PFRCR = 0x0560, | |
185 | GECMR = 0x05b0, | |
186 | MAHR = 0x05c0, | |
187 | MALR = 0x05c8, | |
188 | TROCR = 0x0700, /* Undocumented? */ | |
189 | CDCR = 0x0708, /* Undocumented? */ | |
190 | LCCR = 0x0710, /* Undocumented? */ | |
191 | CEFCR = 0x0740, | |
192 | FRECR = 0x0748, | |
193 | TSFRCR = 0x0750, | |
194 | TLFRCR = 0x0758, | |
195 | RFCR = 0x0760, | |
196 | CERCR = 0x0768, /* Undocumented? */ | |
197 | CEECR = 0x0770, /* Undocumented? */ | |
198 | MAFCR = 0x0778, | |
199 | }; | |
200 | ||
201 | ||
202 | /* Register bits of the Ethernet AVB */ | |
203 | /* CCC */ | |
204 | enum CCC_BIT { | |
205 | CCC_OPC = 0x00000003, | |
206 | CCC_OPC_RESET = 0x00000000, | |
207 | CCC_OPC_CONFIG = 0x00000001, | |
208 | CCC_OPC_OPERATION = 0x00000002, | |
f5d7837f | 209 | CCC_GAC = 0x00000080, |
c156633f SS |
210 | CCC_DTSR = 0x00000100, |
211 | CCC_CSEL = 0x00030000, | |
212 | CCC_CSEL_HPB = 0x00010000, | |
213 | CCC_CSEL_ETH_TX = 0x00020000, | |
214 | CCC_CSEL_GMII_REF = 0x00030000, | |
215 | CCC_BOC = 0x00100000, /* Undocumented? */ | |
216 | CCC_LBME = 0x01000000, | |
217 | }; | |
218 | ||
219 | /* CSR */ | |
220 | enum CSR_BIT { | |
221 | CSR_OPS = 0x0000000F, | |
222 | CSR_OPS_RESET = 0x00000001, | |
223 | CSR_OPS_CONFIG = 0x00000002, | |
224 | CSR_OPS_OPERATION = 0x00000004, | |
225 | CSR_OPS_STANDBY = 0x00000008, /* Undocumented? */ | |
226 | CSR_DTS = 0x00000100, | |
227 | CSR_TPO0 = 0x00010000, | |
228 | CSR_TPO1 = 0x00020000, | |
229 | CSR_TPO2 = 0x00040000, | |
230 | CSR_TPO3 = 0x00080000, | |
231 | CSR_RPO = 0x00100000, | |
232 | }; | |
233 | ||
234 | /* ESR */ | |
235 | enum ESR_BIT { | |
236 | ESR_EQN = 0x0000001F, | |
237 | ESR_ET = 0x00000F00, | |
238 | ESR_EIL = 0x00001000, | |
239 | }; | |
240 | ||
241 | /* RCR */ | |
242 | enum RCR_BIT { | |
243 | RCR_EFFS = 0x00000001, | |
244 | RCR_ENCF = 0x00000002, | |
245 | RCR_ESF = 0x0000000C, | |
246 | RCR_ETS0 = 0x00000010, | |
247 | RCR_ETS2 = 0x00000020, | |
248 | RCR_RFCL = 0x1FFF0000, | |
249 | }; | |
250 | ||
251 | /* RQC0/1/2/3/4 */ | |
252 | enum RQC_BIT { | |
253 | RQC_RSM0 = 0x00000003, | |
254 | RQC_UFCC0 = 0x00000030, | |
255 | RQC_RSM1 = 0x00000300, | |
256 | RQC_UFCC1 = 0x00003000, | |
257 | RQC_RSM2 = 0x00030000, | |
258 | RQC_UFCC2 = 0x00300000, | |
259 | RQC_RSM3 = 0x03000000, | |
260 | RQC_UFCC3 = 0x30000000, | |
261 | }; | |
262 | ||
263 | /* RPC */ | |
264 | enum RPC_BIT { | |
265 | RPC_PCNT = 0x00000700, | |
266 | RPC_DCNT = 0x00FF0000, | |
267 | }; | |
268 | ||
269 | /* UFCW */ | |
270 | enum UFCW_BIT { | |
271 | UFCW_WL0 = 0x0000003F, | |
272 | UFCW_WL1 = 0x00003F00, | |
273 | UFCW_WL2 = 0x003F0000, | |
274 | UFCW_WL3 = 0x3F000000, | |
275 | }; | |
276 | ||
277 | /* UFCS */ | |
278 | enum UFCS_BIT { | |
279 | UFCS_SL0 = 0x0000003F, | |
280 | UFCS_SL1 = 0x00003F00, | |
281 | UFCS_SL2 = 0x003F0000, | |
282 | UFCS_SL3 = 0x3F000000, | |
283 | }; | |
284 | ||
285 | /* UFCV0/1/2/3/4 */ | |
286 | enum UFCV_BIT { | |
287 | UFCV_CV0 = 0x0000003F, | |
288 | UFCV_CV1 = 0x00003F00, | |
289 | UFCV_CV2 = 0x003F0000, | |
290 | UFCV_CV3 = 0x3F000000, | |
291 | }; | |
292 | ||
293 | /* UFCD0/1/2/3/4 */ | |
294 | enum UFCD_BIT { | |
295 | UFCD_DV0 = 0x0000003F, | |
296 | UFCD_DV1 = 0x00003F00, | |
297 | UFCD_DV2 = 0x003F0000, | |
298 | UFCD_DV3 = 0x3F000000, | |
299 | }; | |
300 | ||
301 | /* SFO */ | |
302 | enum SFO_BIT { | |
303 | SFO_FPB = 0x0000003F, | |
304 | }; | |
305 | ||
306 | /* RTC */ | |
307 | enum RTC_BIT { | |
308 | RTC_MFL0 = 0x00000FFF, | |
309 | RTC_MFL1 = 0x0FFF0000, | |
310 | }; | |
311 | ||
312 | /* TGC */ | |
313 | enum TGC_BIT { | |
314 | TGC_TSM0 = 0x00000001, | |
315 | TGC_TSM1 = 0x00000002, | |
316 | TGC_TSM2 = 0x00000004, | |
317 | TGC_TSM3 = 0x00000008, | |
318 | TGC_TQP = 0x00000030, | |
319 | TGC_TQP_NONAVB = 0x00000000, | |
320 | TGC_TQP_AVBMODE1 = 0x00000010, | |
321 | TGC_TQP_AVBMODE2 = 0x00000030, | |
322 | TGC_TBD0 = 0x00000300, | |
323 | TGC_TBD1 = 0x00003000, | |
324 | TGC_TBD2 = 0x00030000, | |
325 | TGC_TBD3 = 0x00300000, | |
326 | }; | |
327 | ||
328 | /* TCCR */ | |
329 | enum TCCR_BIT { | |
330 | TCCR_TSRQ0 = 0x00000001, | |
331 | TCCR_TSRQ1 = 0x00000002, | |
332 | TCCR_TSRQ2 = 0x00000004, | |
333 | TCCR_TSRQ3 = 0x00000008, | |
334 | TCCR_TFEN = 0x00000100, | |
335 | TCCR_TFR = 0x00000200, | |
336 | }; | |
337 | ||
338 | /* TSR */ | |
339 | enum TSR_BIT { | |
340 | TSR_CCS0 = 0x00000003, | |
341 | TSR_CCS1 = 0x0000000C, | |
342 | TSR_TFFL = 0x00000700, | |
343 | }; | |
344 | ||
345 | /* TFA2 */ | |
346 | enum TFA2_BIT { | |
347 | TFA2_TSV = 0x0000FFFF, | |
348 | TFA2_TST = 0x03FF0000, | |
349 | }; | |
350 | ||
351 | /* DIC */ | |
352 | enum DIC_BIT { | |
353 | DIC_DPE1 = 0x00000002, | |
354 | DIC_DPE2 = 0x00000004, | |
355 | DIC_DPE3 = 0x00000008, | |
356 | DIC_DPE4 = 0x00000010, | |
357 | DIC_DPE5 = 0x00000020, | |
358 | DIC_DPE6 = 0x00000040, | |
359 | DIC_DPE7 = 0x00000080, | |
360 | DIC_DPE8 = 0x00000100, | |
361 | DIC_DPE9 = 0x00000200, | |
362 | DIC_DPE10 = 0x00000400, | |
363 | DIC_DPE11 = 0x00000800, | |
364 | DIC_DPE12 = 0x00001000, | |
365 | DIC_DPE13 = 0x00002000, | |
366 | DIC_DPE14 = 0x00004000, | |
367 | DIC_DPE15 = 0x00008000, | |
368 | }; | |
369 | ||
370 | /* DIS */ | |
371 | enum DIS_BIT { | |
372 | DIS_DPF1 = 0x00000002, | |
373 | DIS_DPF2 = 0x00000004, | |
374 | DIS_DPF3 = 0x00000008, | |
375 | DIS_DPF4 = 0x00000010, | |
376 | DIS_DPF5 = 0x00000020, | |
377 | DIS_DPF6 = 0x00000040, | |
378 | DIS_DPF7 = 0x00000080, | |
379 | DIS_DPF8 = 0x00000100, | |
380 | DIS_DPF9 = 0x00000200, | |
381 | DIS_DPF10 = 0x00000400, | |
382 | DIS_DPF11 = 0x00000800, | |
383 | DIS_DPF12 = 0x00001000, | |
384 | DIS_DPF13 = 0x00002000, | |
385 | DIS_DPF14 = 0x00004000, | |
386 | DIS_DPF15 = 0x00008000, | |
387 | }; | |
388 | ||
389 | /* EIC */ | |
390 | enum EIC_BIT { | |
391 | EIC_MREE = 0x00000001, | |
392 | EIC_MTEE = 0x00000002, | |
393 | EIC_QEE = 0x00000004, | |
394 | EIC_SEE = 0x00000008, | |
395 | EIC_CLLE0 = 0x00000010, | |
396 | EIC_CLLE1 = 0x00000020, | |
397 | EIC_CULE0 = 0x00000040, | |
398 | EIC_CULE1 = 0x00000080, | |
399 | EIC_TFFE = 0x00000100, | |
400 | }; | |
401 | ||
402 | /* EIS */ | |
403 | enum EIS_BIT { | |
404 | EIS_MREF = 0x00000001, | |
405 | EIS_MTEF = 0x00000002, | |
406 | EIS_QEF = 0x00000004, | |
407 | EIS_SEF = 0x00000008, | |
408 | EIS_CLLF0 = 0x00000010, | |
409 | EIS_CLLF1 = 0x00000020, | |
410 | EIS_CULF0 = 0x00000040, | |
411 | EIS_CULF1 = 0x00000080, | |
412 | EIS_TFFF = 0x00000100, | |
413 | EIS_QFS = 0x00010000, | |
414 | }; | |
415 | ||
416 | /* RIC0 */ | |
417 | enum RIC0_BIT { | |
418 | RIC0_FRE0 = 0x00000001, | |
419 | RIC0_FRE1 = 0x00000002, | |
420 | RIC0_FRE2 = 0x00000004, | |
421 | RIC0_FRE3 = 0x00000008, | |
422 | RIC0_FRE4 = 0x00000010, | |
423 | RIC0_FRE5 = 0x00000020, | |
424 | RIC0_FRE6 = 0x00000040, | |
425 | RIC0_FRE7 = 0x00000080, | |
426 | RIC0_FRE8 = 0x00000100, | |
427 | RIC0_FRE9 = 0x00000200, | |
428 | RIC0_FRE10 = 0x00000400, | |
429 | RIC0_FRE11 = 0x00000800, | |
430 | RIC0_FRE12 = 0x00001000, | |
431 | RIC0_FRE13 = 0x00002000, | |
432 | RIC0_FRE14 = 0x00004000, | |
433 | RIC0_FRE15 = 0x00008000, | |
434 | RIC0_FRE16 = 0x00010000, | |
435 | RIC0_FRE17 = 0x00020000, | |
436 | }; | |
437 | ||
438 | /* RIC0 */ | |
439 | enum RIS0_BIT { | |
440 | RIS0_FRF0 = 0x00000001, | |
441 | RIS0_FRF1 = 0x00000002, | |
442 | RIS0_FRF2 = 0x00000004, | |
443 | RIS0_FRF3 = 0x00000008, | |
444 | RIS0_FRF4 = 0x00000010, | |
445 | RIS0_FRF5 = 0x00000020, | |
446 | RIS0_FRF6 = 0x00000040, | |
447 | RIS0_FRF7 = 0x00000080, | |
448 | RIS0_FRF8 = 0x00000100, | |
449 | RIS0_FRF9 = 0x00000200, | |
450 | RIS0_FRF10 = 0x00000400, | |
451 | RIS0_FRF11 = 0x00000800, | |
452 | RIS0_FRF12 = 0x00001000, | |
453 | RIS0_FRF13 = 0x00002000, | |
454 | RIS0_FRF14 = 0x00004000, | |
455 | RIS0_FRF15 = 0x00008000, | |
456 | RIS0_FRF16 = 0x00010000, | |
457 | RIS0_FRF17 = 0x00020000, | |
458 | }; | |
459 | ||
460 | /* RIC1 */ | |
461 | enum RIC1_BIT { | |
462 | RIC1_RFWE = 0x80000000, | |
463 | }; | |
464 | ||
465 | /* RIS1 */ | |
466 | enum RIS1_BIT { | |
467 | RIS1_RFWF = 0x80000000, | |
468 | }; | |
469 | ||
470 | /* RIC2 */ | |
471 | enum RIC2_BIT { | |
472 | RIC2_QFE0 = 0x00000001, | |
473 | RIC2_QFE1 = 0x00000002, | |
474 | RIC2_QFE2 = 0x00000004, | |
475 | RIC2_QFE3 = 0x00000008, | |
476 | RIC2_QFE4 = 0x00000010, | |
477 | RIC2_QFE5 = 0x00000020, | |
478 | RIC2_QFE6 = 0x00000040, | |
479 | RIC2_QFE7 = 0x00000080, | |
480 | RIC2_QFE8 = 0x00000100, | |
481 | RIC2_QFE9 = 0x00000200, | |
482 | RIC2_QFE10 = 0x00000400, | |
483 | RIC2_QFE11 = 0x00000800, | |
484 | RIC2_QFE12 = 0x00001000, | |
485 | RIC2_QFE13 = 0x00002000, | |
486 | RIC2_QFE14 = 0x00004000, | |
487 | RIC2_QFE15 = 0x00008000, | |
488 | RIC2_QFE16 = 0x00010000, | |
489 | RIC2_QFE17 = 0x00020000, | |
490 | RIC2_RFFE = 0x80000000, | |
491 | }; | |
492 | ||
493 | /* RIS2 */ | |
494 | enum RIS2_BIT { | |
495 | RIS2_QFF0 = 0x00000001, | |
496 | RIS2_QFF1 = 0x00000002, | |
497 | RIS2_QFF2 = 0x00000004, | |
498 | RIS2_QFF3 = 0x00000008, | |
499 | RIS2_QFF4 = 0x00000010, | |
500 | RIS2_QFF5 = 0x00000020, | |
501 | RIS2_QFF6 = 0x00000040, | |
502 | RIS2_QFF7 = 0x00000080, | |
503 | RIS2_QFF8 = 0x00000100, | |
504 | RIS2_QFF9 = 0x00000200, | |
505 | RIS2_QFF10 = 0x00000400, | |
506 | RIS2_QFF11 = 0x00000800, | |
507 | RIS2_QFF12 = 0x00001000, | |
508 | RIS2_QFF13 = 0x00002000, | |
509 | RIS2_QFF14 = 0x00004000, | |
510 | RIS2_QFF15 = 0x00008000, | |
511 | RIS2_QFF16 = 0x00010000, | |
512 | RIS2_QFF17 = 0x00020000, | |
513 | RIS2_RFFF = 0x80000000, | |
514 | }; | |
515 | ||
516 | /* TIC */ | |
517 | enum TIC_BIT { | |
518 | TIC_FTE0 = 0x00000001, /* Undocumented? */ | |
519 | TIC_FTE1 = 0x00000002, /* Undocumented? */ | |
520 | TIC_TFUE = 0x00000100, | |
521 | TIC_TFWE = 0x00000200, | |
522 | }; | |
523 | ||
524 | /* TIS */ | |
525 | enum TIS_BIT { | |
526 | TIS_FTF0 = 0x00000001, /* Undocumented? */ | |
527 | TIS_FTF1 = 0x00000002, /* Undocumented? */ | |
528 | TIS_TFUF = 0x00000100, | |
529 | TIS_TFWF = 0x00000200, | |
530 | }; | |
531 | ||
532 | /* ISS */ | |
533 | enum ISS_BIT { | |
534 | ISS_FRS = 0x00000001, /* Undocumented? */ | |
535 | ISS_FTS = 0x00000004, /* Undocumented? */ | |
536 | ISS_ES = 0x00000040, | |
537 | ISS_MS = 0x00000080, | |
538 | ISS_TFUS = 0x00000100, | |
539 | ISS_TFWS = 0x00000200, | |
540 | ISS_RFWS = 0x00001000, | |
541 | ISS_CGIS = 0x00002000, | |
542 | ISS_DPS1 = 0x00020000, | |
543 | ISS_DPS2 = 0x00040000, | |
544 | ISS_DPS3 = 0x00080000, | |
545 | ISS_DPS4 = 0x00100000, | |
546 | ISS_DPS5 = 0x00200000, | |
547 | ISS_DPS6 = 0x00400000, | |
548 | ISS_DPS7 = 0x00800000, | |
549 | ISS_DPS8 = 0x01000000, | |
550 | ISS_DPS9 = 0x02000000, | |
551 | ISS_DPS10 = 0x04000000, | |
552 | ISS_DPS11 = 0x08000000, | |
553 | ISS_DPS12 = 0x10000000, | |
554 | ISS_DPS13 = 0x20000000, | |
555 | ISS_DPS14 = 0x40000000, | |
556 | ISS_DPS15 = 0x80000000, | |
557 | }; | |
558 | ||
559 | /* GCCR */ | |
560 | enum GCCR_BIT { | |
561 | GCCR_TCR = 0x00000003, | |
562 | GCCR_TCR_NOREQ = 0x00000000, /* No request */ | |
563 | GCCR_TCR_RESET = 0x00000001, /* gPTP/AVTP presentation timer reset */ | |
564 | GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */ | |
565 | GCCR_LTO = 0x00000004, | |
566 | GCCR_LTI = 0x00000008, | |
567 | GCCR_LPTC = 0x00000010, | |
568 | GCCR_LMTT = 0x00000020, | |
569 | GCCR_TCSS = 0x00000300, | |
570 | GCCR_TCSS_GPTP = 0x00000000, /* gPTP timer value */ | |
571 | GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */ | |
572 | GCCR_TCSS_AVTP = 0x00000200, /* AVTP presentation time value */ | |
573 | }; | |
574 | ||
575 | /* GTI */ | |
576 | enum GTI_BIT { | |
577 | GTI_TIV = 0x0FFFFFFF, | |
578 | }; | |
579 | ||
b3d39a88 SH |
580 | #define GTI_TIV_MAX GTI_TIV |
581 | #define GTI_TIV_MIN 0x20 | |
582 | ||
c156633f SS |
583 | /* GIC */ |
584 | enum GIC_BIT { | |
585 | GIC_PTCE = 0x00000001, /* Undocumented? */ | |
586 | GIC_PTME = 0x00000004, | |
587 | }; | |
588 | ||
589 | /* GIS */ | |
590 | enum GIS_BIT { | |
591 | GIS_PTCF = 0x00000001, /* Undocumented? */ | |
592 | GIS_PTMF = 0x00000004, | |
593 | }; | |
594 | ||
595 | /* ECMR */ | |
596 | enum ECMR_BIT { | |
597 | ECMR_PRM = 0x00000001, | |
598 | ECMR_DM = 0x00000002, | |
599 | ECMR_TE = 0x00000020, | |
600 | ECMR_RE = 0x00000040, | |
601 | ECMR_MPDE = 0x00000200, | |
602 | ECMR_TXF = 0x00010000, /* Undocumented? */ | |
603 | ECMR_RXF = 0x00020000, | |
604 | ECMR_PFR = 0x00040000, | |
605 | ECMR_ZPF = 0x00080000, /* Undocumented? */ | |
606 | ECMR_RZPF = 0x00100000, | |
607 | ECMR_DPAD = 0x00200000, | |
608 | ECMR_RCSC = 0x00800000, | |
609 | ECMR_TRCCM = 0x04000000, | |
610 | }; | |
611 | ||
612 | /* ECSR */ | |
613 | enum ECSR_BIT { | |
614 | ECSR_ICD = 0x00000001, | |
615 | ECSR_MPD = 0x00000002, | |
616 | ECSR_LCHNG = 0x00000004, | |
617 | ECSR_PHYI = 0x00000008, | |
618 | }; | |
619 | ||
620 | /* ECSIPR */ | |
621 | enum ECSIPR_BIT { | |
622 | ECSIPR_ICDIP = 0x00000001, | |
623 | ECSIPR_MPDIP = 0x00000002, | |
624 | ECSIPR_LCHNGIP = 0x00000004, /* Undocumented? */ | |
625 | }; | |
626 | ||
627 | /* PIR */ | |
628 | enum PIR_BIT { | |
629 | PIR_MDC = 0x00000001, | |
630 | PIR_MMD = 0x00000002, | |
631 | PIR_MDO = 0x00000004, | |
632 | PIR_MDI = 0x00000008, | |
633 | }; | |
634 | ||
635 | /* PSR */ | |
636 | enum PSR_BIT { | |
637 | PSR_LMON = 0x00000001, | |
638 | }; | |
639 | ||
640 | /* PIPR */ | |
641 | enum PIPR_BIT { | |
642 | PIPR_PHYIP = 0x00000001, | |
643 | }; | |
644 | ||
645 | /* MPR */ | |
646 | enum MPR_BIT { | |
647 | MPR_MP = 0x0000ffff, | |
648 | }; | |
649 | ||
650 | /* GECMR */ | |
651 | enum GECMR_BIT { | |
652 | GECMR_SPEED = 0x00000001, | |
653 | GECMR_SPEED_100 = 0x00000000, | |
654 | GECMR_SPEED_1000 = 0x00000001, | |
655 | }; | |
656 | ||
657 | /* The Ethernet AVB descriptor definitions. */ | |
658 | struct ravb_desc { | |
659 | __le16 ds; /* Descriptor size */ | |
660 | u8 cc; /* Content control MSBs (reserved) */ | |
661 | u8 die_dt; /* Descriptor interrupt enable and type */ | |
662 | __le32 dptr; /* Descriptor pointer */ | |
663 | }; | |
664 | ||
2f45d190 SS |
665 | #define DPTR_ALIGN 4 /* Required descriptor pointer alignment */ |
666 | ||
c156633f SS |
667 | enum DIE_DT { |
668 | /* Frame data */ | |
669 | DT_FMID = 0x40, | |
670 | DT_FSTART = 0x50, | |
671 | DT_FEND = 0x60, | |
672 | DT_FSINGLE = 0x70, | |
673 | /* Chain control */ | |
674 | DT_LINK = 0x80, | |
675 | DT_LINKFIX = 0x90, | |
676 | DT_EOS = 0xa0, | |
677 | /* HW/SW arbitration */ | |
678 | DT_FEMPTY = 0xc0, | |
679 | DT_FEMPTY_IS = 0xd0, | |
680 | DT_FEMPTY_IC = 0xe0, | |
681 | DT_FEMPTY_ND = 0xf0, | |
682 | DT_LEMPTY = 0x20, | |
683 | DT_EEMPTY = 0x30, | |
684 | }; | |
685 | ||
686 | struct ravb_rx_desc { | |
687 | __le16 ds_cc; /* Descriptor size and content control LSBs */ | |
688 | u8 msc; /* MAC status code */ | |
689 | u8 die_dt; /* Descriptor interrupt enable and type */ | |
690 | __le32 dptr; /* Descpriptor pointer */ | |
691 | }; | |
692 | ||
693 | struct ravb_ex_rx_desc { | |
694 | __le16 ds_cc; /* Descriptor size and content control lower bits */ | |
695 | u8 msc; /* MAC status code */ | |
696 | u8 die_dt; /* Descriptor interrupt enable and type */ | |
697 | __le32 dptr; /* Descpriptor pointer */ | |
698 | __le32 ts_n; /* Timestampe nsec */ | |
699 | __le32 ts_sl; /* Timestamp low */ | |
700 | __le16 ts_sh; /* Timestamp high */ | |
701 | __le16 res; /* Reserved bits */ | |
702 | }; | |
703 | ||
704 | enum RX_DS_CC_BIT { | |
705 | RX_DS = 0x0fff, /* Data size */ | |
706 | RX_TR = 0x1000, /* Truncation indication */ | |
707 | RX_EI = 0x2000, /* Error indication */ | |
708 | RX_PS = 0xc000, /* Padding selection */ | |
709 | }; | |
710 | ||
711 | /* E-MAC status code */ | |
712 | enum MSC_BIT { | |
713 | MSC_CRC = 0x01, /* Frame CRC error */ | |
714 | MSC_RFE = 0x02, /* Frame reception error (flagged by PHY) */ | |
715 | MSC_RTSF = 0x04, /* Frame length error (frame too short) */ | |
716 | MSC_RTLF = 0x08, /* Frame length error (frame too long) */ | |
717 | MSC_FRE = 0x10, /* Fraction error (not a multiple of 8 bits) */ | |
718 | MSC_CRL = 0x20, /* Carrier lost */ | |
719 | MSC_CEEF = 0x40, /* Carrier extension error */ | |
720 | MSC_MC = 0x80, /* Multicast frame reception */ | |
721 | }; | |
722 | ||
723 | struct ravb_tx_desc { | |
724 | __le16 ds_tagl; /* Descriptor size and frame tag LSBs */ | |
725 | u8 tagh_tsr; /* Frame tag MSBs and timestamp storage request bit */ | |
726 | u8 die_dt; /* Descriptor interrupt enable and type */ | |
727 | __le32 dptr; /* Descpriptor pointer */ | |
728 | }; | |
729 | ||
730 | enum TX_DS_TAGL_BIT { | |
731 | TX_DS = 0x0fff, /* Data size */ | |
732 | TX_TAGL = 0xf000, /* Frame tag LSBs */ | |
733 | }; | |
734 | ||
735 | enum TX_TAGH_TSR_BIT { | |
736 | TX_TAGH = 0x3f, /* Frame tag MSBs */ | |
737 | TX_TSR = 0x40, /* Timestamp storage request */ | |
738 | }; | |
739 | enum RAVB_QUEUE { | |
740 | RAVB_BE = 0, /* Best Effort Queue */ | |
741 | RAVB_NC, /* Network Control Queue */ | |
742 | }; | |
743 | ||
744 | #define DBAT_ENTRY_NUM 22 | |
745 | #define RX_QUEUE_OFFSET 4 | |
746 | #define NUM_RX_QUEUE 2 | |
747 | #define NUM_TX_QUEUE 2 | |
2f45d190 | 748 | #define NUM_TX_DESC 2 /* TX descriptors per packet */ |
c156633f SS |
749 | |
750 | struct ravb_tstamp_skb { | |
751 | struct list_head list; | |
752 | struct sk_buff *skb; | |
753 | u16 tag; | |
754 | }; | |
755 | ||
a0d2f206 SS |
756 | struct ravb_ptp_perout { |
757 | u32 target; | |
758 | u32 period; | |
759 | }; | |
760 | ||
761 | #define N_EXT_TS 1 | |
762 | #define N_PER_OUT 1 | |
763 | ||
764 | struct ravb_ptp { | |
765 | struct ptp_clock *clock; | |
766 | struct ptp_clock_info info; | |
767 | u32 default_addend; | |
768 | u32 current_addend; | |
769 | int extts[N_EXT_TS]; | |
770 | struct ravb_ptp_perout perout[N_PER_OUT]; | |
771 | }; | |
772 | ||
22d4df8f KM |
773 | enum ravb_chip_id { |
774 | RCAR_GEN2, | |
775 | RCAR_GEN3, | |
776 | }; | |
777 | ||
c156633f SS |
778 | struct ravb_private { |
779 | struct net_device *ndev; | |
780 | struct platform_device *pdev; | |
781 | void __iomem *addr; | |
782 | struct mdiobb_ctrl mdiobb; | |
783 | u32 num_rx_ring[NUM_RX_QUEUE]; | |
784 | u32 num_tx_ring[NUM_TX_QUEUE]; | |
785 | u32 desc_bat_size; | |
786 | dma_addr_t desc_bat_dma; | |
787 | struct ravb_desc *desc_bat; | |
788 | dma_addr_t rx_desc_dma[NUM_RX_QUEUE]; | |
789 | dma_addr_t tx_desc_dma[NUM_TX_QUEUE]; | |
790 | struct ravb_ex_rx_desc *rx_ring[NUM_RX_QUEUE]; | |
791 | struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE]; | |
2f45d190 | 792 | void *tx_align[NUM_TX_QUEUE]; |
c156633f SS |
793 | struct sk_buff **rx_skb[NUM_RX_QUEUE]; |
794 | struct sk_buff **tx_skb[NUM_TX_QUEUE]; | |
c156633f SS |
795 | u32 rx_over_errors; |
796 | u32 rx_fifo_errors; | |
797 | struct net_device_stats stats[NUM_RX_QUEUE]; | |
798 | u32 tstamp_tx_ctrl; | |
799 | u32 tstamp_rx_ctrl; | |
800 | struct list_head ts_skb_list; | |
801 | u32 ts_skb_tag; | |
a0d2f206 | 802 | struct ravb_ptp ptp; |
c156633f SS |
803 | spinlock_t lock; /* Register access lock */ |
804 | u32 cur_rx[NUM_RX_QUEUE]; /* Consumer ring indices */ | |
805 | u32 dirty_rx[NUM_RX_QUEUE]; /* Producer ring indices */ | |
806 | u32 cur_tx[NUM_TX_QUEUE]; | |
807 | u32 dirty_tx[NUM_TX_QUEUE]; | |
808 | struct napi_struct napi[NUM_RX_QUEUE]; | |
809 | struct work_struct work; | |
810 | /* MII transceiver section. */ | |
811 | struct mii_bus *mii_bus; /* MDIO bus control */ | |
812 | struct phy_device *phydev; /* PHY device control */ | |
813 | int link; | |
814 | phy_interface_t phy_interface; | |
815 | int msg_enable; | |
816 | int speed; | |
817 | int duplex; | |
22d4df8f KM |
818 | int emac_irq; |
819 | enum ravb_chip_id chip_id; | |
c156633f SS |
820 | |
821 | unsigned no_avb_link:1; | |
822 | unsigned avb_link_active_low:1; | |
823 | }; | |
824 | ||
825 | static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg) | |
826 | { | |
827 | struct ravb_private *priv = netdev_priv(ndev); | |
828 | ||
829 | return ioread32(priv->addr + reg); | |
830 | } | |
831 | ||
832 | static inline void ravb_write(struct net_device *ndev, u32 data, | |
833 | enum ravb_reg reg) | |
834 | { | |
835 | struct ravb_private *priv = netdev_priv(ndev); | |
836 | ||
837 | iowrite32(data, priv->addr + reg); | |
838 | } | |
839 | ||
568b3ce7 SS |
840 | void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, |
841 | u32 set); | |
a0d2f206 SS |
842 | int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value); |
843 | ||
844 | irqreturn_t ravb_ptp_interrupt(struct net_device *ndev); | |
845 | void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev); | |
846 | void ravb_ptp_stop(struct net_device *ndev); | |
847 | ||
c156633f | 848 | #endif /* #ifndef __RAVB_H__ */ |