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c156633f SS |
1 | /* Renesas Ethernet AVB device driver |
2 | * | |
3 | * Copyright (C) 2014-2015 Renesas Electronics Corporation | |
4 | * Copyright (C) 2015 Renesas Solutions Corp. | |
568b3ce7 | 5 | * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> |
c156633f SS |
6 | * |
7 | * Based on the SuperH Ethernet driver | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License version 2, | |
11 | * as published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/cache.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/etherdevice.h> | |
20 | #include <linux/ethtool.h> | |
21 | #include <linux/if_vlan.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/net_tstamp.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_device.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/of_mdio.h> | |
30 | #include <linux/of_net.h> | |
c156633f SS |
31 | #include <linux/pm_runtime.h> |
32 | #include <linux/slab.h> | |
33 | #include <linux/spinlock.h> | |
34 | ||
b3d39a88 SH |
35 | #include <asm/div64.h> |
36 | ||
c156633f SS |
37 | #include "ravb.h" |
38 | ||
39 | #define RAVB_DEF_MSG_ENABLE \ | |
40 | (NETIF_MSG_LINK | \ | |
41 | NETIF_MSG_TIMER | \ | |
42 | NETIF_MSG_RX_ERR | \ | |
43 | NETIF_MSG_TX_ERR) | |
44 | ||
568b3ce7 SS |
45 | void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, |
46 | u32 set) | |
47 | { | |
48 | ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); | |
49 | } | |
50 | ||
a0d2f206 | 51 | int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) |
c156633f SS |
52 | { |
53 | int i; | |
54 | ||
55 | for (i = 0; i < 10000; i++) { | |
56 | if ((ravb_read(ndev, reg) & mask) == value) | |
57 | return 0; | |
58 | udelay(10); | |
59 | } | |
60 | return -ETIMEDOUT; | |
61 | } | |
62 | ||
63 | static int ravb_config(struct net_device *ndev) | |
64 | { | |
65 | int error; | |
66 | ||
67 | /* Set config mode */ | |
568b3ce7 | 68 | ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); |
c156633f SS |
69 | /* Check if the operating mode is changed to the config mode */ |
70 | error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); | |
71 | if (error) | |
72 | netdev_err(ndev, "failed to switch device to config mode\n"); | |
73 | ||
74 | return error; | |
75 | } | |
76 | ||
77 | static void ravb_set_duplex(struct net_device *ndev) | |
78 | { | |
79 | struct ravb_private *priv = netdev_priv(ndev); | |
c156633f | 80 | |
568b3ce7 | 81 | ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); |
c156633f SS |
82 | } |
83 | ||
84 | static void ravb_set_rate(struct net_device *ndev) | |
85 | { | |
86 | struct ravb_private *priv = netdev_priv(ndev); | |
87 | ||
88 | switch (priv->speed) { | |
89 | case 100: /* 100BASE */ | |
90 | ravb_write(ndev, GECMR_SPEED_100, GECMR); | |
91 | break; | |
92 | case 1000: /* 1000BASE */ | |
93 | ravb_write(ndev, GECMR_SPEED_1000, GECMR); | |
94 | break; | |
c156633f SS |
95 | } |
96 | } | |
97 | ||
98 | static void ravb_set_buffer_align(struct sk_buff *skb) | |
99 | { | |
100 | u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); | |
101 | ||
102 | if (reserve) | |
103 | skb_reserve(skb, RAVB_ALIGN - reserve); | |
104 | } | |
105 | ||
106 | /* Get MAC address from the MAC address registers | |
107 | * | |
108 | * Ethernet AVB device doesn't have ROM for MAC address. | |
109 | * This function gets the MAC address that was used by a bootloader. | |
110 | */ | |
111 | static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) | |
112 | { | |
113 | if (mac) { | |
114 | ether_addr_copy(ndev->dev_addr, mac); | |
115 | } else { | |
d9660638 SS |
116 | u32 mahr = ravb_read(ndev, MAHR); |
117 | u32 malr = ravb_read(ndev, MALR); | |
118 | ||
119 | ndev->dev_addr[0] = (mahr >> 24) & 0xFF; | |
120 | ndev->dev_addr[1] = (mahr >> 16) & 0xFF; | |
121 | ndev->dev_addr[2] = (mahr >> 8) & 0xFF; | |
122 | ndev->dev_addr[3] = (mahr >> 0) & 0xFF; | |
123 | ndev->dev_addr[4] = (malr >> 8) & 0xFF; | |
124 | ndev->dev_addr[5] = (malr >> 0) & 0xFF; | |
c156633f SS |
125 | } |
126 | } | |
127 | ||
128 | static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) | |
129 | { | |
130 | struct ravb_private *priv = container_of(ctrl, struct ravb_private, | |
131 | mdiobb); | |
c156633f | 132 | |
568b3ce7 | 133 | ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); |
c156633f SS |
134 | } |
135 | ||
136 | /* MDC pin control */ | |
137 | static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) | |
138 | { | |
139 | ravb_mdio_ctrl(ctrl, PIR_MDC, level); | |
140 | } | |
141 | ||
142 | /* Data I/O pin control */ | |
143 | static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) | |
144 | { | |
145 | ravb_mdio_ctrl(ctrl, PIR_MMD, output); | |
146 | } | |
147 | ||
148 | /* Set data bit */ | |
149 | static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) | |
150 | { | |
151 | ravb_mdio_ctrl(ctrl, PIR_MDO, value); | |
152 | } | |
153 | ||
154 | /* Get data bit */ | |
155 | static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) | |
156 | { | |
157 | struct ravb_private *priv = container_of(ctrl, struct ravb_private, | |
158 | mdiobb); | |
159 | ||
160 | return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; | |
161 | } | |
162 | ||
163 | /* MDIO bus control struct */ | |
164 | static struct mdiobb_ops bb_ops = { | |
165 | .owner = THIS_MODULE, | |
166 | .set_mdc = ravb_set_mdc, | |
167 | .set_mdio_dir = ravb_set_mdio_dir, | |
168 | .set_mdio_data = ravb_set_mdio_data, | |
169 | .get_mdio_data = ravb_get_mdio_data, | |
170 | }; | |
171 | ||
172 | /* Free skb's and DMA buffers for Ethernet AVB */ | |
173 | static void ravb_ring_free(struct net_device *ndev, int q) | |
174 | { | |
175 | struct ravb_private *priv = netdev_priv(ndev); | |
176 | int ring_size; | |
177 | int i; | |
178 | ||
179 | /* Free RX skb ringbuffer */ | |
180 | if (priv->rx_skb[q]) { | |
181 | for (i = 0; i < priv->num_rx_ring[q]; i++) | |
182 | dev_kfree_skb(priv->rx_skb[q][i]); | |
183 | } | |
184 | kfree(priv->rx_skb[q]); | |
185 | priv->rx_skb[q] = NULL; | |
186 | ||
187 | /* Free TX skb ringbuffer */ | |
188 | if (priv->tx_skb[q]) { | |
189 | for (i = 0; i < priv->num_tx_ring[q]; i++) | |
190 | dev_kfree_skb(priv->tx_skb[q][i]); | |
191 | } | |
192 | kfree(priv->tx_skb[q]); | |
193 | priv->tx_skb[q] = NULL; | |
194 | ||
195 | /* Free aligned TX buffers */ | |
2f45d190 SS |
196 | kfree(priv->tx_align[q]); |
197 | priv->tx_align[q] = NULL; | |
c156633f SS |
198 | |
199 | if (priv->rx_ring[q]) { | |
200 | ring_size = sizeof(struct ravb_ex_rx_desc) * | |
201 | (priv->num_rx_ring[q] + 1); | |
e2dbb33a | 202 | dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], |
c156633f SS |
203 | priv->rx_desc_dma[q]); |
204 | priv->rx_ring[q] = NULL; | |
205 | } | |
206 | ||
207 | if (priv->tx_ring[q]) { | |
208 | ring_size = sizeof(struct ravb_tx_desc) * | |
2f45d190 | 209 | (priv->num_tx_ring[q] * NUM_TX_DESC + 1); |
e2dbb33a | 210 | dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], |
c156633f SS |
211 | priv->tx_desc_dma[q]); |
212 | priv->tx_ring[q] = NULL; | |
213 | } | |
214 | } | |
215 | ||
216 | /* Format skb and descriptor buffer for Ethernet AVB */ | |
217 | static void ravb_ring_format(struct net_device *ndev, int q) | |
218 | { | |
219 | struct ravb_private *priv = netdev_priv(ndev); | |
aad0d51e SS |
220 | struct ravb_ex_rx_desc *rx_desc; |
221 | struct ravb_tx_desc *tx_desc; | |
222 | struct ravb_desc *desc; | |
c156633f | 223 | int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; |
2f45d190 SS |
224 | int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * |
225 | NUM_TX_DESC; | |
c156633f | 226 | dma_addr_t dma_addr; |
c156633f SS |
227 | int i; |
228 | ||
229 | priv->cur_rx[q] = 0; | |
230 | priv->cur_tx[q] = 0; | |
231 | priv->dirty_rx[q] = 0; | |
232 | priv->dirty_tx[q] = 0; | |
233 | ||
234 | memset(priv->rx_ring[q], 0, rx_ring_size); | |
235 | /* Build RX ring buffer */ | |
236 | for (i = 0; i < priv->num_rx_ring[q]; i++) { | |
c156633f SS |
237 | /* RX descriptor */ |
238 | rx_desc = &priv->rx_ring[q][i]; | |
239 | /* The size of the buffer should be on 16-byte boundary. */ | |
240 | rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16)); | |
e2dbb33a | 241 | dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, |
c156633f SS |
242 | ALIGN(PKT_BUF_SZ, 16), |
243 | DMA_FROM_DEVICE); | |
d8b48911 SS |
244 | /* We just set the data size to 0 for a failed mapping which |
245 | * should prevent DMA from happening... | |
246 | */ | |
e2dbb33a | 247 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) |
d8b48911 | 248 | rx_desc->ds_cc = cpu_to_le16(0); |
c156633f SS |
249 | rx_desc->dptr = cpu_to_le32(dma_addr); |
250 | rx_desc->die_dt = DT_FEMPTY; | |
251 | } | |
252 | rx_desc = &priv->rx_ring[q][i]; | |
253 | rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); | |
254 | rx_desc->die_dt = DT_LINKFIX; /* type */ | |
c156633f SS |
255 | |
256 | memset(priv->tx_ring[q], 0, tx_ring_size); | |
257 | /* Build TX ring buffer */ | |
2f45d190 SS |
258 | for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; |
259 | i++, tx_desc++) { | |
260 | tx_desc->die_dt = DT_EEMPTY; | |
261 | tx_desc++; | |
c156633f SS |
262 | tx_desc->die_dt = DT_EEMPTY; |
263 | } | |
c156633f SS |
264 | tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); |
265 | tx_desc->die_dt = DT_LINKFIX; /* type */ | |
266 | ||
267 | /* RX descriptor base address for best effort */ | |
268 | desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; | |
269 | desc->die_dt = DT_LINKFIX; /* type */ | |
270 | desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); | |
271 | ||
272 | /* TX descriptor base address for best effort */ | |
273 | desc = &priv->desc_bat[q]; | |
274 | desc->die_dt = DT_LINKFIX; /* type */ | |
275 | desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); | |
276 | } | |
277 | ||
278 | /* Init skb and descriptor buffer for Ethernet AVB */ | |
279 | static int ravb_ring_init(struct net_device *ndev, int q) | |
280 | { | |
281 | struct ravb_private *priv = netdev_priv(ndev); | |
d8b48911 | 282 | struct sk_buff *skb; |
c156633f | 283 | int ring_size; |
d8b48911 | 284 | int i; |
c156633f SS |
285 | |
286 | /* Allocate RX and TX skb rings */ | |
287 | priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], | |
288 | sizeof(*priv->rx_skb[q]), GFP_KERNEL); | |
289 | priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], | |
290 | sizeof(*priv->tx_skb[q]), GFP_KERNEL); | |
291 | if (!priv->rx_skb[q] || !priv->tx_skb[q]) | |
292 | goto error; | |
293 | ||
d8b48911 SS |
294 | for (i = 0; i < priv->num_rx_ring[q]; i++) { |
295 | skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1); | |
296 | if (!skb) | |
297 | goto error; | |
298 | ravb_set_buffer_align(skb); | |
299 | priv->rx_skb[q][i] = skb; | |
300 | } | |
301 | ||
c156633f | 302 | /* Allocate rings for the aligned buffers */ |
2f45d190 SS |
303 | priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + |
304 | DPTR_ALIGN - 1, GFP_KERNEL); | |
305 | if (!priv->tx_align[q]) | |
c156633f SS |
306 | goto error; |
307 | ||
308 | /* Allocate all RX descriptors. */ | |
309 | ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); | |
e2dbb33a | 310 | priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, |
c156633f SS |
311 | &priv->rx_desc_dma[q], |
312 | GFP_KERNEL); | |
313 | if (!priv->rx_ring[q]) | |
314 | goto error; | |
315 | ||
316 | priv->dirty_rx[q] = 0; | |
317 | ||
318 | /* Allocate all TX descriptors. */ | |
2f45d190 SS |
319 | ring_size = sizeof(struct ravb_tx_desc) * |
320 | (priv->num_tx_ring[q] * NUM_TX_DESC + 1); | |
e2dbb33a | 321 | priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, |
c156633f SS |
322 | &priv->tx_desc_dma[q], |
323 | GFP_KERNEL); | |
324 | if (!priv->tx_ring[q]) | |
325 | goto error; | |
326 | ||
327 | return 0; | |
328 | ||
329 | error: | |
330 | ravb_ring_free(ndev, q); | |
331 | ||
332 | return -ENOMEM; | |
333 | } | |
334 | ||
335 | /* E-MAC init function */ | |
336 | static void ravb_emac_init(struct net_device *ndev) | |
337 | { | |
338 | struct ravb_private *priv = netdev_priv(ndev); | |
c156633f SS |
339 | |
340 | /* Receive frame limit set register */ | |
341 | ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); | |
342 | ||
343 | /* PAUSE prohibition */ | |
1c1fa821 SS |
344 | ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | |
345 | ECMR_TE | ECMR_RE, ECMR); | |
c156633f SS |
346 | |
347 | ravb_set_rate(ndev); | |
348 | ||
349 | /* Set MAC address */ | |
350 | ravb_write(ndev, | |
351 | (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | | |
352 | (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); | |
353 | ravb_write(ndev, | |
354 | (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); | |
355 | ||
356 | ravb_write(ndev, 1, MPR); | |
357 | ||
358 | /* E-MAC status register clear */ | |
359 | ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); | |
360 | ||
361 | /* E-MAC interrupt enable register */ | |
362 | ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); | |
363 | } | |
364 | ||
365 | /* Device init function for Ethernet AVB */ | |
366 | static int ravb_dmac_init(struct net_device *ndev) | |
367 | { | |
368 | int error; | |
369 | ||
370 | /* Set CONFIG mode */ | |
371 | error = ravb_config(ndev); | |
372 | if (error) | |
373 | return error; | |
374 | ||
375 | error = ravb_ring_init(ndev, RAVB_BE); | |
376 | if (error) | |
377 | return error; | |
378 | error = ravb_ring_init(ndev, RAVB_NC); | |
379 | if (error) { | |
380 | ravb_ring_free(ndev, RAVB_BE); | |
381 | return error; | |
382 | } | |
383 | ||
384 | /* Descriptor format */ | |
385 | ravb_ring_format(ndev, RAVB_BE); | |
386 | ravb_ring_format(ndev, RAVB_NC); | |
387 | ||
388 | #if defined(__LITTLE_ENDIAN) | |
568b3ce7 | 389 | ravb_modify(ndev, CCC, CCC_BOC, 0); |
c156633f | 390 | #else |
568b3ce7 | 391 | ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); |
c156633f SS |
392 | #endif |
393 | ||
394 | /* Set AVB RX */ | |
395 | ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR); | |
396 | ||
397 | /* Set FIFO size */ | |
398 | ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); | |
399 | ||
400 | /* Timestamp enable */ | |
401 | ravb_write(ndev, TCCR_TFEN, TCCR); | |
402 | ||
6474de5f | 403 | /* Interrupt init: */ |
c156633f SS |
404 | /* Frame receive */ |
405 | ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); | |
6474de5f KM |
406 | /* Disable FIFO full warning */ |
407 | ravb_write(ndev, 0, RIC1); | |
c156633f SS |
408 | /* Receive FIFO full error, descriptor empty */ |
409 | ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); | |
410 | /* Frame transmitted, timestamp FIFO updated */ | |
411 | ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); | |
412 | ||
413 | /* Setting the control will start the AVB-DMAC process. */ | |
568b3ce7 | 414 | ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); |
c156633f SS |
415 | |
416 | return 0; | |
417 | } | |
418 | ||
419 | /* Free TX skb function for AVB-IP */ | |
420 | static int ravb_tx_free(struct net_device *ndev, int q) | |
421 | { | |
422 | struct ravb_private *priv = netdev_priv(ndev); | |
423 | struct net_device_stats *stats = &priv->stats[q]; | |
424 | struct ravb_tx_desc *desc; | |
425 | int free_num = 0; | |
aad0d51e | 426 | int entry; |
c156633f SS |
427 | u32 size; |
428 | ||
429 | for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { | |
2f45d190 SS |
430 | entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * |
431 | NUM_TX_DESC); | |
c156633f SS |
432 | desc = &priv->tx_ring[q][entry]; |
433 | if (desc->die_dt != DT_FEMPTY) | |
434 | break; | |
435 | /* Descriptor type must be checked before all other reads */ | |
436 | dma_rmb(); | |
437 | size = le16_to_cpu(desc->ds_tagl) & TX_DS; | |
438 | /* Free the original skb. */ | |
2f45d190 | 439 | if (priv->tx_skb[q][entry / NUM_TX_DESC]) { |
e2dbb33a | 440 | dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), |
c156633f | 441 | size, DMA_TO_DEVICE); |
2f45d190 SS |
442 | /* Last packet descriptor? */ |
443 | if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { | |
444 | entry /= NUM_TX_DESC; | |
445 | dev_kfree_skb_any(priv->tx_skb[q][entry]); | |
446 | priv->tx_skb[q][entry] = NULL; | |
447 | stats->tx_packets++; | |
448 | } | |
c156633f SS |
449 | free_num++; |
450 | } | |
c156633f SS |
451 | stats->tx_bytes += size; |
452 | desc->die_dt = DT_EEMPTY; | |
453 | } | |
454 | return free_num; | |
455 | } | |
456 | ||
457 | static void ravb_get_tx_tstamp(struct net_device *ndev) | |
458 | { | |
459 | struct ravb_private *priv = netdev_priv(ndev); | |
460 | struct ravb_tstamp_skb *ts_skb, *ts_skb2; | |
461 | struct skb_shared_hwtstamps shhwtstamps; | |
462 | struct sk_buff *skb; | |
463 | struct timespec64 ts; | |
464 | u16 tag, tfa_tag; | |
465 | int count; | |
466 | u32 tfa2; | |
467 | ||
468 | count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; | |
469 | while (count--) { | |
470 | tfa2 = ravb_read(ndev, TFA2); | |
471 | tfa_tag = (tfa2 & TFA2_TST) >> 16; | |
472 | ts.tv_nsec = (u64)ravb_read(ndev, TFA0); | |
473 | ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | | |
474 | ravb_read(ndev, TFA1); | |
475 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
476 | shhwtstamps.hwtstamp = timespec64_to_ktime(ts); | |
477 | list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, | |
478 | list) { | |
479 | skb = ts_skb->skb; | |
480 | tag = ts_skb->tag; | |
481 | list_del(&ts_skb->list); | |
482 | kfree(ts_skb); | |
483 | if (tag == tfa_tag) { | |
484 | skb_tstamp_tx(skb, &shhwtstamps); | |
485 | break; | |
486 | } | |
487 | } | |
568b3ce7 | 488 | ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); |
c156633f SS |
489 | } |
490 | } | |
491 | ||
492 | /* Packet receive function for Ethernet AVB */ | |
493 | static bool ravb_rx(struct net_device *ndev, int *quota, int q) | |
494 | { | |
495 | struct ravb_private *priv = netdev_priv(ndev); | |
496 | int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; | |
497 | int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - | |
498 | priv->cur_rx[q]; | |
499 | struct net_device_stats *stats = &priv->stats[q]; | |
500 | struct ravb_ex_rx_desc *desc; | |
501 | struct sk_buff *skb; | |
502 | dma_addr_t dma_addr; | |
503 | struct timespec64 ts; | |
c156633f | 504 | u8 desc_status; |
aad0d51e | 505 | u16 pkt_len; |
c156633f SS |
506 | int limit; |
507 | ||
508 | boguscnt = min(boguscnt, *quota); | |
509 | limit = boguscnt; | |
510 | desc = &priv->rx_ring[q][entry]; | |
511 | while (desc->die_dt != DT_FEMPTY) { | |
512 | /* Descriptor type must be checked before all other reads */ | |
513 | dma_rmb(); | |
514 | desc_status = desc->msc; | |
515 | pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; | |
516 | ||
517 | if (--boguscnt < 0) | |
518 | break; | |
519 | ||
d8b48911 SS |
520 | /* We use 0-byte descriptors to mark the DMA mapping errors */ |
521 | if (!pkt_len) | |
522 | continue; | |
523 | ||
c156633f SS |
524 | if (desc_status & MSC_MC) |
525 | stats->multicast++; | |
526 | ||
527 | if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | | |
528 | MSC_CEEF)) { | |
529 | stats->rx_errors++; | |
530 | if (desc_status & MSC_CRC) | |
531 | stats->rx_crc_errors++; | |
532 | if (desc_status & MSC_RFE) | |
533 | stats->rx_frame_errors++; | |
534 | if (desc_status & (MSC_RTLF | MSC_RTSF)) | |
535 | stats->rx_length_errors++; | |
536 | if (desc_status & MSC_CEEF) | |
537 | stats->rx_missed_errors++; | |
538 | } else { | |
539 | u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; | |
540 | ||
541 | skb = priv->rx_skb[q][entry]; | |
542 | priv->rx_skb[q][entry] = NULL; | |
e2dbb33a | 543 | dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), |
e2370f07 SS |
544 | ALIGN(PKT_BUF_SZ, 16), |
545 | DMA_FROM_DEVICE); | |
c156633f SS |
546 | get_ts &= (q == RAVB_NC) ? |
547 | RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : | |
548 | ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; | |
549 | if (get_ts) { | |
550 | struct skb_shared_hwtstamps *shhwtstamps; | |
551 | ||
552 | shhwtstamps = skb_hwtstamps(skb); | |
553 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
554 | ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << | |
555 | 32) | le32_to_cpu(desc->ts_sl); | |
556 | ts.tv_nsec = le32_to_cpu(desc->ts_n); | |
557 | shhwtstamps->hwtstamp = timespec64_to_ktime(ts); | |
558 | } | |
559 | skb_put(skb, pkt_len); | |
560 | skb->protocol = eth_type_trans(skb, ndev); | |
561 | napi_gro_receive(&priv->napi[q], skb); | |
562 | stats->rx_packets++; | |
563 | stats->rx_bytes += pkt_len; | |
564 | } | |
565 | ||
566 | entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; | |
567 | desc = &priv->rx_ring[q][entry]; | |
568 | } | |
569 | ||
570 | /* Refill the RX ring buffers. */ | |
571 | for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { | |
572 | entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; | |
573 | desc = &priv->rx_ring[q][entry]; | |
574 | /* The size of the buffer should be on 16-byte boundary. */ | |
575 | desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16)); | |
576 | ||
577 | if (!priv->rx_skb[q][entry]) { | |
578 | skb = netdev_alloc_skb(ndev, | |
579 | PKT_BUF_SZ + RAVB_ALIGN - 1); | |
580 | if (!skb) | |
581 | break; /* Better luck next round. */ | |
582 | ravb_set_buffer_align(skb); | |
e2dbb33a | 583 | dma_addr = dma_map_single(ndev->dev.parent, skb->data, |
c156633f SS |
584 | le16_to_cpu(desc->ds_cc), |
585 | DMA_FROM_DEVICE); | |
586 | skb_checksum_none_assert(skb); | |
d8b48911 SS |
587 | /* We just set the data size to 0 for a failed mapping |
588 | * which should prevent DMA from happening... | |
589 | */ | |
e2dbb33a | 590 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) |
d8b48911 | 591 | desc->ds_cc = cpu_to_le16(0); |
c156633f SS |
592 | desc->dptr = cpu_to_le32(dma_addr); |
593 | priv->rx_skb[q][entry] = skb; | |
594 | } | |
595 | /* Descriptor type must be set after all the above writes */ | |
596 | dma_wmb(); | |
597 | desc->die_dt = DT_FEMPTY; | |
598 | } | |
599 | ||
600 | *quota -= limit - (++boguscnt); | |
601 | ||
602 | return boguscnt <= 0; | |
603 | } | |
604 | ||
605 | static void ravb_rcv_snd_disable(struct net_device *ndev) | |
606 | { | |
607 | /* Disable TX and RX */ | |
568b3ce7 | 608 | ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); |
c156633f SS |
609 | } |
610 | ||
611 | static void ravb_rcv_snd_enable(struct net_device *ndev) | |
612 | { | |
613 | /* Enable TX and RX */ | |
568b3ce7 | 614 | ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); |
c156633f SS |
615 | } |
616 | ||
617 | /* function for waiting dma process finished */ | |
618 | static int ravb_stop_dma(struct net_device *ndev) | |
619 | { | |
620 | int error; | |
621 | ||
622 | /* Wait for stopping the hardware TX process */ | |
623 | error = ravb_wait(ndev, TCCR, | |
624 | TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); | |
625 | if (error) | |
626 | return error; | |
627 | ||
628 | error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, | |
629 | 0); | |
630 | if (error) | |
631 | return error; | |
632 | ||
633 | /* Stop the E-MAC's RX/TX processes. */ | |
634 | ravb_rcv_snd_disable(ndev); | |
635 | ||
636 | /* Wait for stopping the RX DMA process */ | |
637 | error = ravb_wait(ndev, CSR, CSR_RPO, 0); | |
638 | if (error) | |
639 | return error; | |
640 | ||
641 | /* Stop AVB-DMAC process */ | |
642 | return ravb_config(ndev); | |
643 | } | |
644 | ||
645 | /* E-MAC interrupt handler */ | |
646 | static void ravb_emac_interrupt(struct net_device *ndev) | |
647 | { | |
648 | struct ravb_private *priv = netdev_priv(ndev); | |
649 | u32 ecsr, psr; | |
650 | ||
651 | ecsr = ravb_read(ndev, ECSR); | |
652 | ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ | |
653 | if (ecsr & ECSR_ICD) | |
654 | ndev->stats.tx_carrier_errors++; | |
655 | if (ecsr & ECSR_LCHNG) { | |
656 | /* Link changed */ | |
657 | if (priv->no_avb_link) | |
658 | return; | |
659 | psr = ravb_read(ndev, PSR); | |
660 | if (priv->avb_link_active_low) | |
661 | psr ^= PSR_LMON; | |
662 | if (!(psr & PSR_LMON)) { | |
663 | /* DIsable RX and TX */ | |
664 | ravb_rcv_snd_disable(ndev); | |
665 | } else { | |
666 | /* Enable RX and TX */ | |
667 | ravb_rcv_snd_enable(ndev); | |
668 | } | |
669 | } | |
670 | } | |
671 | ||
672 | /* Error interrupt handler */ | |
673 | static void ravb_error_interrupt(struct net_device *ndev) | |
674 | { | |
675 | struct ravb_private *priv = netdev_priv(ndev); | |
676 | u32 eis, ris2; | |
677 | ||
678 | eis = ravb_read(ndev, EIS); | |
679 | ravb_write(ndev, ~EIS_QFS, EIS); | |
680 | if (eis & EIS_QFS) { | |
681 | ris2 = ravb_read(ndev, RIS2); | |
682 | ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); | |
683 | ||
684 | /* Receive Descriptor Empty int */ | |
685 | if (ris2 & RIS2_QFF0) | |
686 | priv->stats[RAVB_BE].rx_over_errors++; | |
687 | ||
688 | /* Receive Descriptor Empty int */ | |
689 | if (ris2 & RIS2_QFF1) | |
690 | priv->stats[RAVB_NC].rx_over_errors++; | |
691 | ||
692 | /* Receive FIFO Overflow int */ | |
693 | if (ris2 & RIS2_RFFF) | |
694 | priv->rx_fifo_errors++; | |
695 | } | |
696 | } | |
697 | ||
698 | static irqreturn_t ravb_interrupt(int irq, void *dev_id) | |
699 | { | |
700 | struct net_device *ndev = dev_id; | |
701 | struct ravb_private *priv = netdev_priv(ndev); | |
702 | irqreturn_t result = IRQ_NONE; | |
703 | u32 iss; | |
704 | ||
705 | spin_lock(&priv->lock); | |
706 | /* Get interrupt status */ | |
707 | iss = ravb_read(ndev, ISS); | |
708 | ||
709 | /* Received and transmitted interrupts */ | |
710 | if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { | |
711 | u32 ris0 = ravb_read(ndev, RIS0); | |
712 | u32 ric0 = ravb_read(ndev, RIC0); | |
713 | u32 tis = ravb_read(ndev, TIS); | |
714 | u32 tic = ravb_read(ndev, TIC); | |
715 | int q; | |
716 | ||
717 | /* Timestamp updated */ | |
718 | if (tis & TIS_TFUF) { | |
719 | ravb_write(ndev, ~TIS_TFUF, TIS); | |
720 | ravb_get_tx_tstamp(ndev); | |
721 | result = IRQ_HANDLED; | |
722 | } | |
723 | ||
724 | /* Network control and best effort queue RX/TX */ | |
725 | for (q = RAVB_NC; q >= RAVB_BE; q--) { | |
726 | if (((ris0 & ric0) & BIT(q)) || | |
727 | ((tis & tic) & BIT(q))) { | |
728 | if (napi_schedule_prep(&priv->napi[q])) { | |
729 | /* Mask RX and TX interrupts */ | |
2452cb0c MN |
730 | ric0 &= ~BIT(q); |
731 | tic &= ~BIT(q); | |
732 | ravb_write(ndev, ric0, RIC0); | |
733 | ravb_write(ndev, tic, TIC); | |
c156633f SS |
734 | __napi_schedule(&priv->napi[q]); |
735 | } else { | |
736 | netdev_warn(ndev, | |
737 | "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", | |
738 | ris0, ric0); | |
739 | netdev_warn(ndev, | |
740 | " tx status 0x%08x, tx mask 0x%08x.\n", | |
741 | tis, tic); | |
742 | } | |
743 | result = IRQ_HANDLED; | |
744 | } | |
745 | } | |
746 | } | |
747 | ||
748 | /* E-MAC status summary */ | |
749 | if (iss & ISS_MS) { | |
750 | ravb_emac_interrupt(ndev); | |
751 | result = IRQ_HANDLED; | |
752 | } | |
753 | ||
754 | /* Error status summary */ | |
755 | if (iss & ISS_ES) { | |
756 | ravb_error_interrupt(ndev); | |
757 | result = IRQ_HANDLED; | |
758 | } | |
759 | ||
38c848c7 YK |
760 | if ((iss & ISS_CGIS) && ravb_ptp_interrupt(ndev) == IRQ_HANDLED) |
761 | result = IRQ_HANDLED; | |
a0d2f206 | 762 | |
c156633f SS |
763 | mmiowb(); |
764 | spin_unlock(&priv->lock); | |
765 | return result; | |
766 | } | |
767 | ||
768 | static int ravb_poll(struct napi_struct *napi, int budget) | |
769 | { | |
770 | struct net_device *ndev = napi->dev; | |
771 | struct ravb_private *priv = netdev_priv(ndev); | |
772 | unsigned long flags; | |
773 | int q = napi - priv->napi; | |
774 | int mask = BIT(q); | |
775 | int quota = budget; | |
776 | u32 ris0, tis; | |
777 | ||
778 | for (;;) { | |
779 | tis = ravb_read(ndev, TIS); | |
780 | ris0 = ravb_read(ndev, RIS0); | |
781 | if (!((ris0 & mask) || (tis & mask))) | |
782 | break; | |
783 | ||
784 | /* Processing RX Descriptor Ring */ | |
785 | if (ris0 & mask) { | |
786 | /* Clear RX interrupt */ | |
787 | ravb_write(ndev, ~mask, RIS0); | |
788 | if (ravb_rx(ndev, "a, q)) | |
789 | goto out; | |
790 | } | |
791 | /* Processing TX Descriptor Ring */ | |
792 | if (tis & mask) { | |
793 | spin_lock_irqsave(&priv->lock, flags); | |
794 | /* Clear TX interrupt */ | |
795 | ravb_write(ndev, ~mask, TIS); | |
796 | ravb_tx_free(ndev, q); | |
797 | netif_wake_subqueue(ndev, q); | |
798 | mmiowb(); | |
799 | spin_unlock_irqrestore(&priv->lock, flags); | |
800 | } | |
801 | } | |
802 | ||
803 | napi_complete(napi); | |
804 | ||
805 | /* Re-enable RX/TX interrupts */ | |
806 | spin_lock_irqsave(&priv->lock, flags); | |
568b3ce7 SS |
807 | ravb_modify(ndev, RIC0, mask, mask); |
808 | ravb_modify(ndev, TIC, mask, mask); | |
c156633f SS |
809 | mmiowb(); |
810 | spin_unlock_irqrestore(&priv->lock, flags); | |
811 | ||
812 | /* Receive error message handling */ | |
813 | priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; | |
814 | priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; | |
815 | if (priv->rx_over_errors != ndev->stats.rx_over_errors) { | |
816 | ndev->stats.rx_over_errors = priv->rx_over_errors; | |
817 | netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n"); | |
818 | } | |
819 | if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) { | |
820 | ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; | |
821 | netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n"); | |
822 | } | |
823 | out: | |
824 | return budget - quota; | |
825 | } | |
826 | ||
827 | /* PHY state control function */ | |
828 | static void ravb_adjust_link(struct net_device *ndev) | |
829 | { | |
830 | struct ravb_private *priv = netdev_priv(ndev); | |
831 | struct phy_device *phydev = priv->phydev; | |
832 | bool new_state = false; | |
833 | ||
834 | if (phydev->link) { | |
835 | if (phydev->duplex != priv->duplex) { | |
836 | new_state = true; | |
837 | priv->duplex = phydev->duplex; | |
838 | ravb_set_duplex(ndev); | |
839 | } | |
840 | ||
841 | if (phydev->speed != priv->speed) { | |
842 | new_state = true; | |
843 | priv->speed = phydev->speed; | |
844 | ravb_set_rate(ndev); | |
845 | } | |
846 | if (!priv->link) { | |
568b3ce7 | 847 | ravb_modify(ndev, ECMR, ECMR_TXF, 0); |
c156633f SS |
848 | new_state = true; |
849 | priv->link = phydev->link; | |
850 | if (priv->no_avb_link) | |
851 | ravb_rcv_snd_enable(ndev); | |
852 | } | |
853 | } else if (priv->link) { | |
854 | new_state = true; | |
855 | priv->link = 0; | |
856 | priv->speed = 0; | |
857 | priv->duplex = -1; | |
858 | if (priv->no_avb_link) | |
859 | ravb_rcv_snd_disable(ndev); | |
860 | } | |
861 | ||
862 | if (new_state && netif_msg_link(priv)) | |
863 | phy_print_status(phydev); | |
864 | } | |
865 | ||
866 | /* PHY init function */ | |
867 | static int ravb_phy_init(struct net_device *ndev) | |
868 | { | |
869 | struct device_node *np = ndev->dev.parent->of_node; | |
870 | struct ravb_private *priv = netdev_priv(ndev); | |
871 | struct phy_device *phydev; | |
872 | struct device_node *pn; | |
b4bc88a8 | 873 | int err; |
c156633f SS |
874 | |
875 | priv->link = 0; | |
876 | priv->speed = 0; | |
877 | priv->duplex = -1; | |
878 | ||
879 | /* Try connecting to PHY */ | |
880 | pn = of_parse_phandle(np, "phy-handle", 0); | |
b4bc88a8 KM |
881 | if (!pn) { |
882 | /* In the case of a fixed PHY, the DT node associated | |
883 | * to the PHY is the Ethernet MAC DT node. | |
884 | */ | |
885 | if (of_phy_is_fixed_link(np)) { | |
886 | err = of_phy_register_fixed_link(np); | |
887 | if (err) | |
888 | return err; | |
889 | } | |
890 | pn = of_node_get(np); | |
891 | } | |
c156633f SS |
892 | phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, |
893 | priv->phy_interface); | |
894 | if (!phydev) { | |
895 | netdev_err(ndev, "failed to connect PHY\n"); | |
896 | return -ENOENT; | |
897 | } | |
898 | ||
22d4df8f KM |
899 | /* This driver only support 10/100Mbit speeds on Gen3 |
900 | * at this time. | |
901 | */ | |
902 | if (priv->chip_id == RCAR_GEN3) { | |
903 | int err; | |
904 | ||
905 | err = phy_set_max_speed(phydev, SPEED_100); | |
906 | if (err) { | |
907 | netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); | |
908 | phy_disconnect(phydev); | |
909 | return err; | |
910 | } | |
911 | ||
912 | netdev_info(ndev, "limited PHY to 100Mbit/s\n"); | |
913 | } | |
914 | ||
54499969 KM |
915 | /* 10BASE is not supported */ |
916 | phydev->supported &= ~PHY_10BT_FEATURES; | |
917 | ||
2220943a | 918 | phy_attached_info(phydev); |
c156633f SS |
919 | |
920 | priv->phydev = phydev; | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
925 | /* PHY control start function */ | |
926 | static int ravb_phy_start(struct net_device *ndev) | |
927 | { | |
928 | struct ravb_private *priv = netdev_priv(ndev); | |
929 | int error; | |
930 | ||
931 | error = ravb_phy_init(ndev); | |
932 | if (error) | |
933 | return error; | |
934 | ||
935 | phy_start(priv->phydev); | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) | |
941 | { | |
942 | struct ravb_private *priv = netdev_priv(ndev); | |
943 | int error = -ENODEV; | |
944 | unsigned long flags; | |
945 | ||
946 | if (priv->phydev) { | |
947 | spin_lock_irqsave(&priv->lock, flags); | |
948 | error = phy_ethtool_gset(priv->phydev, ecmd); | |
949 | spin_unlock_irqrestore(&priv->lock, flags); | |
950 | } | |
951 | ||
952 | return error; | |
953 | } | |
954 | ||
955 | static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) | |
956 | { | |
957 | struct ravb_private *priv = netdev_priv(ndev); | |
958 | unsigned long flags; | |
959 | int error; | |
960 | ||
961 | if (!priv->phydev) | |
962 | return -ENODEV; | |
963 | ||
964 | spin_lock_irqsave(&priv->lock, flags); | |
965 | ||
966 | /* Disable TX and RX */ | |
967 | ravb_rcv_snd_disable(ndev); | |
968 | ||
969 | error = phy_ethtool_sset(priv->phydev, ecmd); | |
970 | if (error) | |
971 | goto error_exit; | |
972 | ||
973 | if (ecmd->duplex == DUPLEX_FULL) | |
974 | priv->duplex = 1; | |
975 | else | |
976 | priv->duplex = 0; | |
977 | ||
978 | ravb_set_duplex(ndev); | |
979 | ||
980 | error_exit: | |
981 | mdelay(1); | |
982 | ||
983 | /* Enable TX and RX */ | |
984 | ravb_rcv_snd_enable(ndev); | |
985 | ||
986 | mmiowb(); | |
987 | spin_unlock_irqrestore(&priv->lock, flags); | |
988 | ||
989 | return error; | |
990 | } | |
991 | ||
992 | static int ravb_nway_reset(struct net_device *ndev) | |
993 | { | |
994 | struct ravb_private *priv = netdev_priv(ndev); | |
995 | int error = -ENODEV; | |
996 | unsigned long flags; | |
997 | ||
998 | if (priv->phydev) { | |
999 | spin_lock_irqsave(&priv->lock, flags); | |
1000 | error = phy_start_aneg(priv->phydev); | |
1001 | spin_unlock_irqrestore(&priv->lock, flags); | |
1002 | } | |
1003 | ||
1004 | return error; | |
1005 | } | |
1006 | ||
1007 | static u32 ravb_get_msglevel(struct net_device *ndev) | |
1008 | { | |
1009 | struct ravb_private *priv = netdev_priv(ndev); | |
1010 | ||
1011 | return priv->msg_enable; | |
1012 | } | |
1013 | ||
1014 | static void ravb_set_msglevel(struct net_device *ndev, u32 value) | |
1015 | { | |
1016 | struct ravb_private *priv = netdev_priv(ndev); | |
1017 | ||
1018 | priv->msg_enable = value; | |
1019 | } | |
1020 | ||
1021 | static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { | |
1022 | "rx_queue_0_current", | |
1023 | "tx_queue_0_current", | |
1024 | "rx_queue_0_dirty", | |
1025 | "tx_queue_0_dirty", | |
1026 | "rx_queue_0_packets", | |
1027 | "tx_queue_0_packets", | |
1028 | "rx_queue_0_bytes", | |
1029 | "tx_queue_0_bytes", | |
1030 | "rx_queue_0_mcast_packets", | |
1031 | "rx_queue_0_errors", | |
1032 | "rx_queue_0_crc_errors", | |
1033 | "rx_queue_0_frame_errors", | |
1034 | "rx_queue_0_length_errors", | |
1035 | "rx_queue_0_missed_errors", | |
1036 | "rx_queue_0_over_errors", | |
1037 | ||
1038 | "rx_queue_1_current", | |
1039 | "tx_queue_1_current", | |
1040 | "rx_queue_1_dirty", | |
1041 | "tx_queue_1_dirty", | |
1042 | "rx_queue_1_packets", | |
1043 | "tx_queue_1_packets", | |
1044 | "rx_queue_1_bytes", | |
1045 | "tx_queue_1_bytes", | |
1046 | "rx_queue_1_mcast_packets", | |
1047 | "rx_queue_1_errors", | |
1048 | "rx_queue_1_crc_errors", | |
b17c1d9a | 1049 | "rx_queue_1_frame_errors", |
c156633f SS |
1050 | "rx_queue_1_length_errors", |
1051 | "rx_queue_1_missed_errors", | |
1052 | "rx_queue_1_over_errors", | |
1053 | }; | |
1054 | ||
1055 | #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) | |
1056 | ||
1057 | static int ravb_get_sset_count(struct net_device *netdev, int sset) | |
1058 | { | |
1059 | switch (sset) { | |
1060 | case ETH_SS_STATS: | |
1061 | return RAVB_STATS_LEN; | |
1062 | default: | |
1063 | return -EOPNOTSUPP; | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | static void ravb_get_ethtool_stats(struct net_device *ndev, | |
1068 | struct ethtool_stats *stats, u64 *data) | |
1069 | { | |
1070 | struct ravb_private *priv = netdev_priv(ndev); | |
1071 | int i = 0; | |
1072 | int q; | |
1073 | ||
1074 | /* Device-specific stats */ | |
1075 | for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { | |
1076 | struct net_device_stats *stats = &priv->stats[q]; | |
1077 | ||
1078 | data[i++] = priv->cur_rx[q]; | |
1079 | data[i++] = priv->cur_tx[q]; | |
1080 | data[i++] = priv->dirty_rx[q]; | |
1081 | data[i++] = priv->dirty_tx[q]; | |
1082 | data[i++] = stats->rx_packets; | |
1083 | data[i++] = stats->tx_packets; | |
1084 | data[i++] = stats->rx_bytes; | |
1085 | data[i++] = stats->tx_bytes; | |
1086 | data[i++] = stats->multicast; | |
1087 | data[i++] = stats->rx_errors; | |
1088 | data[i++] = stats->rx_crc_errors; | |
1089 | data[i++] = stats->rx_frame_errors; | |
1090 | data[i++] = stats->rx_length_errors; | |
1091 | data[i++] = stats->rx_missed_errors; | |
1092 | data[i++] = stats->rx_over_errors; | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) | |
1097 | { | |
1098 | switch (stringset) { | |
1099 | case ETH_SS_STATS: | |
1100 | memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); | |
1101 | break; | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | static void ravb_get_ringparam(struct net_device *ndev, | |
1106 | struct ethtool_ringparam *ring) | |
1107 | { | |
1108 | struct ravb_private *priv = netdev_priv(ndev); | |
1109 | ||
1110 | ring->rx_max_pending = BE_RX_RING_MAX; | |
1111 | ring->tx_max_pending = BE_TX_RING_MAX; | |
1112 | ring->rx_pending = priv->num_rx_ring[RAVB_BE]; | |
1113 | ring->tx_pending = priv->num_tx_ring[RAVB_BE]; | |
1114 | } | |
1115 | ||
1116 | static int ravb_set_ringparam(struct net_device *ndev, | |
1117 | struct ethtool_ringparam *ring) | |
1118 | { | |
1119 | struct ravb_private *priv = netdev_priv(ndev); | |
1120 | int error; | |
1121 | ||
1122 | if (ring->tx_pending > BE_TX_RING_MAX || | |
1123 | ring->rx_pending > BE_RX_RING_MAX || | |
1124 | ring->tx_pending < BE_TX_RING_MIN || | |
1125 | ring->rx_pending < BE_RX_RING_MIN) | |
1126 | return -EINVAL; | |
1127 | if (ring->rx_mini_pending || ring->rx_jumbo_pending) | |
1128 | return -EINVAL; | |
1129 | ||
1130 | if (netif_running(ndev)) { | |
1131 | netif_device_detach(ndev); | |
a0d2f206 | 1132 | /* Stop PTP Clock driver */ |
50bfd838 SS |
1133 | if (priv->chip_id == RCAR_GEN2) |
1134 | ravb_ptp_stop(ndev); | |
c156633f SS |
1135 | /* Wait for DMA stopping */ |
1136 | error = ravb_stop_dma(ndev); | |
1137 | if (error) { | |
1138 | netdev_err(ndev, | |
1139 | "cannot set ringparam! Any AVB processes are still running?\n"); | |
1140 | return error; | |
1141 | } | |
1142 | synchronize_irq(ndev->irq); | |
1143 | ||
1144 | /* Free all the skb's in the RX queue and the DMA buffers. */ | |
1145 | ravb_ring_free(ndev, RAVB_BE); | |
1146 | ravb_ring_free(ndev, RAVB_NC); | |
1147 | } | |
1148 | ||
1149 | /* Set new parameters */ | |
1150 | priv->num_rx_ring[RAVB_BE] = ring->rx_pending; | |
1151 | priv->num_tx_ring[RAVB_BE] = ring->tx_pending; | |
1152 | ||
1153 | if (netif_running(ndev)) { | |
1154 | error = ravb_dmac_init(ndev); | |
1155 | if (error) { | |
1156 | netdev_err(ndev, | |
1157 | "%s: ravb_dmac_init() failed, error %d\n", | |
1158 | __func__, error); | |
1159 | return error; | |
1160 | } | |
1161 | ||
1162 | ravb_emac_init(ndev); | |
1163 | ||
a0d2f206 | 1164 | /* Initialise PTP Clock driver */ |
50bfd838 SS |
1165 | if (priv->chip_id == RCAR_GEN2) |
1166 | ravb_ptp_init(ndev, priv->pdev); | |
a0d2f206 | 1167 | |
c156633f SS |
1168 | netif_device_attach(ndev); |
1169 | } | |
1170 | ||
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | static int ravb_get_ts_info(struct net_device *ndev, | |
1175 | struct ethtool_ts_info *info) | |
1176 | { | |
a0d2f206 SS |
1177 | struct ravb_private *priv = netdev_priv(ndev); |
1178 | ||
c156633f SS |
1179 | info->so_timestamping = |
1180 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
1181 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1182 | SOF_TIMESTAMPING_SOFTWARE | | |
1183 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1184 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1185 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1186 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); | |
1187 | info->rx_filters = | |
1188 | (1 << HWTSTAMP_FILTER_NONE) | | |
1189 | (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | | |
1190 | (1 << HWTSTAMP_FILTER_ALL); | |
a0d2f206 | 1191 | info->phc_index = ptp_clock_index(priv->ptp.clock); |
c156633f SS |
1192 | |
1193 | return 0; | |
1194 | } | |
1195 | ||
1196 | static const struct ethtool_ops ravb_ethtool_ops = { | |
1197 | .get_settings = ravb_get_settings, | |
1198 | .set_settings = ravb_set_settings, | |
1199 | .nway_reset = ravb_nway_reset, | |
1200 | .get_msglevel = ravb_get_msglevel, | |
1201 | .set_msglevel = ravb_set_msglevel, | |
1202 | .get_link = ethtool_op_get_link, | |
1203 | .get_strings = ravb_get_strings, | |
1204 | .get_ethtool_stats = ravb_get_ethtool_stats, | |
1205 | .get_sset_count = ravb_get_sset_count, | |
1206 | .get_ringparam = ravb_get_ringparam, | |
1207 | .set_ringparam = ravb_set_ringparam, | |
1208 | .get_ts_info = ravb_get_ts_info, | |
1209 | }; | |
1210 | ||
1211 | /* Network device open function for Ethernet AVB */ | |
1212 | static int ravb_open(struct net_device *ndev) | |
1213 | { | |
1214 | struct ravb_private *priv = netdev_priv(ndev); | |
1215 | int error; | |
1216 | ||
1217 | napi_enable(&priv->napi[RAVB_BE]); | |
1218 | napi_enable(&priv->napi[RAVB_NC]); | |
1219 | ||
1220 | error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name, | |
1221 | ndev); | |
1222 | if (error) { | |
1223 | netdev_err(ndev, "cannot request IRQ\n"); | |
1224 | goto out_napi_off; | |
1225 | } | |
1226 | ||
22d4df8f KM |
1227 | if (priv->chip_id == RCAR_GEN3) { |
1228 | error = request_irq(priv->emac_irq, ravb_interrupt, | |
1229 | IRQF_SHARED, ndev->name, ndev); | |
1230 | if (error) { | |
1231 | netdev_err(ndev, "cannot request IRQ\n"); | |
1232 | goto out_free_irq; | |
1233 | } | |
1234 | } | |
1235 | ||
c156633f SS |
1236 | /* Device init */ |
1237 | error = ravb_dmac_init(ndev); | |
1238 | if (error) | |
508dc064 | 1239 | goto out_free_irq2; |
c156633f SS |
1240 | ravb_emac_init(ndev); |
1241 | ||
a0d2f206 | 1242 | /* Initialise PTP Clock driver */ |
f5d7837f KM |
1243 | if (priv->chip_id == RCAR_GEN2) |
1244 | ravb_ptp_init(ndev, priv->pdev); | |
a0d2f206 | 1245 | |
c156633f SS |
1246 | netif_tx_start_all_queues(ndev); |
1247 | ||
1248 | /* PHY control start */ | |
1249 | error = ravb_phy_start(ndev); | |
1250 | if (error) | |
a0d2f206 | 1251 | goto out_ptp_stop; |
c156633f SS |
1252 | |
1253 | return 0; | |
1254 | ||
a0d2f206 SS |
1255 | out_ptp_stop: |
1256 | /* Stop PTP Clock driver */ | |
f5d7837f KM |
1257 | if (priv->chip_id == RCAR_GEN2) |
1258 | ravb_ptp_stop(ndev); | |
508dc064 SS |
1259 | out_free_irq2: |
1260 | if (priv->chip_id == RCAR_GEN3) | |
1261 | free_irq(priv->emac_irq, ndev); | |
c156633f SS |
1262 | out_free_irq: |
1263 | free_irq(ndev->irq, ndev); | |
1264 | out_napi_off: | |
1265 | napi_disable(&priv->napi[RAVB_NC]); | |
1266 | napi_disable(&priv->napi[RAVB_BE]); | |
1267 | return error; | |
1268 | } | |
1269 | ||
1270 | /* Timeout function for Ethernet AVB */ | |
1271 | static void ravb_tx_timeout(struct net_device *ndev) | |
1272 | { | |
1273 | struct ravb_private *priv = netdev_priv(ndev); | |
1274 | ||
1275 | netif_err(priv, tx_err, ndev, | |
1276 | "transmit timed out, status %08x, resetting...\n", | |
1277 | ravb_read(ndev, ISS)); | |
1278 | ||
1279 | /* tx_errors count up */ | |
1280 | ndev->stats.tx_errors++; | |
1281 | ||
1282 | schedule_work(&priv->work); | |
1283 | } | |
1284 | ||
1285 | static void ravb_tx_timeout_work(struct work_struct *work) | |
1286 | { | |
1287 | struct ravb_private *priv = container_of(work, struct ravb_private, | |
1288 | work); | |
1289 | struct net_device *ndev = priv->ndev; | |
1290 | ||
1291 | netif_tx_stop_all_queues(ndev); | |
1292 | ||
a0d2f206 | 1293 | /* Stop PTP Clock driver */ |
50bfd838 SS |
1294 | if (priv->chip_id == RCAR_GEN2) |
1295 | ravb_ptp_stop(ndev); | |
a0d2f206 | 1296 | |
c156633f SS |
1297 | /* Wait for DMA stopping */ |
1298 | ravb_stop_dma(ndev); | |
1299 | ||
1300 | ravb_ring_free(ndev, RAVB_BE); | |
1301 | ravb_ring_free(ndev, RAVB_NC); | |
1302 | ||
1303 | /* Device init */ | |
1304 | ravb_dmac_init(ndev); | |
1305 | ravb_emac_init(ndev); | |
1306 | ||
a0d2f206 | 1307 | /* Initialise PTP Clock driver */ |
50bfd838 SS |
1308 | if (priv->chip_id == RCAR_GEN2) |
1309 | ravb_ptp_init(ndev, priv->pdev); | |
a0d2f206 | 1310 | |
c156633f SS |
1311 | netif_tx_start_all_queues(ndev); |
1312 | } | |
1313 | ||
1314 | /* Packet transmit function for Ethernet AVB */ | |
1315 | static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
1316 | { | |
1317 | struct ravb_private *priv = netdev_priv(ndev); | |
c156633f | 1318 | u16 q = skb_get_queue_mapping(skb); |
aad0d51e | 1319 | struct ravb_tstamp_skb *ts_skb; |
c156633f SS |
1320 | struct ravb_tx_desc *desc; |
1321 | unsigned long flags; | |
1322 | u32 dma_addr; | |
1323 | void *buffer; | |
1324 | u32 entry; | |
2f45d190 | 1325 | u32 len; |
c156633f SS |
1326 | |
1327 | spin_lock_irqsave(&priv->lock, flags); | |
2f45d190 SS |
1328 | if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * |
1329 | NUM_TX_DESC) { | |
c156633f SS |
1330 | netif_err(priv, tx_queued, ndev, |
1331 | "still transmitting with the full ring!\n"); | |
1332 | netif_stop_subqueue(ndev, q); | |
1333 | spin_unlock_irqrestore(&priv->lock, flags); | |
1334 | return NETDEV_TX_BUSY; | |
1335 | } | |
2f45d190 SS |
1336 | entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); |
1337 | priv->tx_skb[q][entry / NUM_TX_DESC] = skb; | |
c156633f SS |
1338 | |
1339 | if (skb_put_padto(skb, ETH_ZLEN)) | |
1340 | goto drop; | |
1341 | ||
2f45d190 SS |
1342 | buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + |
1343 | entry / NUM_TX_DESC * DPTR_ALIGN; | |
1344 | len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; | |
1345 | memcpy(buffer, skb->data, len); | |
e2dbb33a KM |
1346 | dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); |
1347 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) | |
c156633f | 1348 | goto drop; |
2f45d190 SS |
1349 | |
1350 | desc = &priv->tx_ring[q][entry]; | |
1351 | desc->ds_tagl = cpu_to_le16(len); | |
1352 | desc->dptr = cpu_to_le32(dma_addr); | |
1353 | ||
1354 | buffer = skb->data + len; | |
1355 | len = skb->len - len; | |
e2dbb33a KM |
1356 | dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); |
1357 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) | |
2f45d190 SS |
1358 | goto unmap; |
1359 | ||
1360 | desc++; | |
1361 | desc->ds_tagl = cpu_to_le16(len); | |
c156633f SS |
1362 | desc->dptr = cpu_to_le32(dma_addr); |
1363 | ||
1364 | /* TX timestamp required */ | |
1365 | if (q == RAVB_NC) { | |
1366 | ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); | |
1367 | if (!ts_skb) { | |
2f45d190 | 1368 | desc--; |
e2dbb33a | 1369 | dma_unmap_single(ndev->dev.parent, dma_addr, len, |
c156633f | 1370 | DMA_TO_DEVICE); |
2f45d190 | 1371 | goto unmap; |
c156633f SS |
1372 | } |
1373 | ts_skb->skb = skb; | |
1374 | ts_skb->tag = priv->ts_skb_tag++; | |
1375 | priv->ts_skb_tag &= 0x3ff; | |
1376 | list_add_tail(&ts_skb->list, &priv->ts_skb_list); | |
1377 | ||
1378 | /* TAG and timestamp required flag */ | |
1379 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
c156633f SS |
1380 | desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; |
1381 | desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12); | |
1382 | } | |
1383 | ||
d7be81a5 | 1384 | skb_tx_timestamp(skb); |
c156633f SS |
1385 | /* Descriptor type must be set after all the above writes */ |
1386 | dma_wmb(); | |
2f45d190 SS |
1387 | desc->die_dt = DT_FEND; |
1388 | desc--; | |
1389 | desc->die_dt = DT_FSTART; | |
c156633f | 1390 | |
568b3ce7 | 1391 | ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); |
c156633f | 1392 | |
2f45d190 SS |
1393 | priv->cur_tx[q] += NUM_TX_DESC; |
1394 | if (priv->cur_tx[q] - priv->dirty_tx[q] > | |
1395 | (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q)) | |
c156633f SS |
1396 | netif_stop_subqueue(ndev, q); |
1397 | ||
1398 | exit: | |
1399 | mmiowb(); | |
1400 | spin_unlock_irqrestore(&priv->lock, flags); | |
1401 | return NETDEV_TX_OK; | |
1402 | ||
2f45d190 | 1403 | unmap: |
e2dbb33a | 1404 | dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), |
2f45d190 | 1405 | le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); |
c156633f SS |
1406 | drop: |
1407 | dev_kfree_skb_any(skb); | |
2f45d190 | 1408 | priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; |
c156633f SS |
1409 | goto exit; |
1410 | } | |
1411 | ||
1412 | static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, | |
1413 | void *accel_priv, select_queue_fallback_t fallback) | |
1414 | { | |
1415 | /* If skb needs TX timestamp, it is handled in network control queue */ | |
1416 | return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : | |
1417 | RAVB_BE; | |
1418 | ||
1419 | } | |
1420 | ||
1421 | static struct net_device_stats *ravb_get_stats(struct net_device *ndev) | |
1422 | { | |
1423 | struct ravb_private *priv = netdev_priv(ndev); | |
1424 | struct net_device_stats *nstats, *stats0, *stats1; | |
1425 | ||
1426 | nstats = &ndev->stats; | |
1427 | stats0 = &priv->stats[RAVB_BE]; | |
1428 | stats1 = &priv->stats[RAVB_NC]; | |
1429 | ||
1430 | nstats->tx_dropped += ravb_read(ndev, TROCR); | |
1431 | ravb_write(ndev, 0, TROCR); /* (write clear) */ | |
1432 | nstats->collisions += ravb_read(ndev, CDCR); | |
1433 | ravb_write(ndev, 0, CDCR); /* (write clear) */ | |
1434 | nstats->tx_carrier_errors += ravb_read(ndev, LCCR); | |
1435 | ravb_write(ndev, 0, LCCR); /* (write clear) */ | |
1436 | ||
1437 | nstats->tx_carrier_errors += ravb_read(ndev, CERCR); | |
1438 | ravb_write(ndev, 0, CERCR); /* (write clear) */ | |
1439 | nstats->tx_carrier_errors += ravb_read(ndev, CEECR); | |
1440 | ravb_write(ndev, 0, CEECR); /* (write clear) */ | |
1441 | ||
1442 | nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; | |
1443 | nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; | |
1444 | nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; | |
1445 | nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; | |
1446 | nstats->multicast = stats0->multicast + stats1->multicast; | |
1447 | nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; | |
1448 | nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; | |
1449 | nstats->rx_frame_errors = | |
1450 | stats0->rx_frame_errors + stats1->rx_frame_errors; | |
1451 | nstats->rx_length_errors = | |
1452 | stats0->rx_length_errors + stats1->rx_length_errors; | |
1453 | nstats->rx_missed_errors = | |
1454 | stats0->rx_missed_errors + stats1->rx_missed_errors; | |
1455 | nstats->rx_over_errors = | |
1456 | stats0->rx_over_errors + stats1->rx_over_errors; | |
1457 | ||
1458 | return nstats; | |
1459 | } | |
1460 | ||
1461 | /* Update promiscuous bit */ | |
1462 | static void ravb_set_rx_mode(struct net_device *ndev) | |
1463 | { | |
1464 | struct ravb_private *priv = netdev_priv(ndev); | |
1465 | unsigned long flags; | |
c156633f SS |
1466 | |
1467 | spin_lock_irqsave(&priv->lock, flags); | |
568b3ce7 SS |
1468 | ravb_modify(ndev, ECMR, ECMR_PRM, |
1469 | ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); | |
c156633f SS |
1470 | mmiowb(); |
1471 | spin_unlock_irqrestore(&priv->lock, flags); | |
1472 | } | |
1473 | ||
1474 | /* Device close function for Ethernet AVB */ | |
1475 | static int ravb_close(struct net_device *ndev) | |
1476 | { | |
1477 | struct ravb_private *priv = netdev_priv(ndev); | |
1478 | struct ravb_tstamp_skb *ts_skb, *ts_skb2; | |
1479 | ||
1480 | netif_tx_stop_all_queues(ndev); | |
1481 | ||
1482 | /* Disable interrupts by clearing the interrupt masks. */ | |
1483 | ravb_write(ndev, 0, RIC0); | |
c156633f SS |
1484 | ravb_write(ndev, 0, RIC2); |
1485 | ravb_write(ndev, 0, TIC); | |
1486 | ||
a0d2f206 | 1487 | /* Stop PTP Clock driver */ |
f5d7837f KM |
1488 | if (priv->chip_id == RCAR_GEN2) |
1489 | ravb_ptp_stop(ndev); | |
a0d2f206 | 1490 | |
c156633f SS |
1491 | /* Set the config mode to stop the AVB-DMAC's processes */ |
1492 | if (ravb_stop_dma(ndev) < 0) | |
1493 | netdev_err(ndev, | |
1494 | "device will be stopped after h/w processes are done.\n"); | |
1495 | ||
1496 | /* Clear the timestamp list */ | |
1497 | list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { | |
1498 | list_del(&ts_skb->list); | |
1499 | kfree(ts_skb); | |
1500 | } | |
1501 | ||
1502 | /* PHY disconnect */ | |
1503 | if (priv->phydev) { | |
1504 | phy_stop(priv->phydev); | |
1505 | phy_disconnect(priv->phydev); | |
1506 | priv->phydev = NULL; | |
1507 | } | |
1508 | ||
1509 | free_irq(ndev->irq, ndev); | |
1510 | ||
1511 | napi_disable(&priv->napi[RAVB_NC]); | |
1512 | napi_disable(&priv->napi[RAVB_BE]); | |
1513 | ||
1514 | /* Free all the skb's in the RX queue and the DMA buffers. */ | |
1515 | ravb_ring_free(ndev, RAVB_BE); | |
1516 | ravb_ring_free(ndev, RAVB_NC); | |
1517 | ||
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) | |
1522 | { | |
1523 | struct ravb_private *priv = netdev_priv(ndev); | |
1524 | struct hwtstamp_config config; | |
1525 | ||
1526 | config.flags = 0; | |
1527 | config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : | |
1528 | HWTSTAMP_TX_OFF; | |
1529 | if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) | |
1530 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
1531 | else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) | |
1532 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
1533 | else | |
1534 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
1535 | ||
1536 | return copy_to_user(req->ifr_data, &config, sizeof(config)) ? | |
1537 | -EFAULT : 0; | |
1538 | } | |
1539 | ||
1540 | /* Control hardware time stamping */ | |
1541 | static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) | |
1542 | { | |
1543 | struct ravb_private *priv = netdev_priv(ndev); | |
1544 | struct hwtstamp_config config; | |
1545 | u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; | |
1546 | u32 tstamp_tx_ctrl; | |
1547 | ||
1548 | if (copy_from_user(&config, req->ifr_data, sizeof(config))) | |
1549 | return -EFAULT; | |
1550 | ||
1551 | /* Reserved for future extensions */ | |
1552 | if (config.flags) | |
1553 | return -EINVAL; | |
1554 | ||
1555 | switch (config.tx_type) { | |
1556 | case HWTSTAMP_TX_OFF: | |
1557 | tstamp_tx_ctrl = 0; | |
1558 | break; | |
1559 | case HWTSTAMP_TX_ON: | |
1560 | tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; | |
1561 | break; | |
1562 | default: | |
1563 | return -ERANGE; | |
1564 | } | |
1565 | ||
1566 | switch (config.rx_filter) { | |
1567 | case HWTSTAMP_FILTER_NONE: | |
1568 | tstamp_rx_ctrl = 0; | |
1569 | break; | |
1570 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1571 | tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; | |
1572 | break; | |
1573 | default: | |
1574 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
1575 | tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; | |
1576 | } | |
1577 | ||
1578 | priv->tstamp_tx_ctrl = tstamp_tx_ctrl; | |
1579 | priv->tstamp_rx_ctrl = tstamp_rx_ctrl; | |
1580 | ||
1581 | return copy_to_user(req->ifr_data, &config, sizeof(config)) ? | |
1582 | -EFAULT : 0; | |
1583 | } | |
1584 | ||
1585 | /* ioctl to device function */ | |
1586 | static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) | |
1587 | { | |
1588 | struct ravb_private *priv = netdev_priv(ndev); | |
1589 | struct phy_device *phydev = priv->phydev; | |
1590 | ||
1591 | if (!netif_running(ndev)) | |
1592 | return -EINVAL; | |
1593 | ||
1594 | if (!phydev) | |
1595 | return -ENODEV; | |
1596 | ||
1597 | switch (cmd) { | |
1598 | case SIOCGHWTSTAMP: | |
1599 | return ravb_hwtstamp_get(ndev, req); | |
1600 | case SIOCSHWTSTAMP: | |
1601 | return ravb_hwtstamp_set(ndev, req); | |
1602 | } | |
1603 | ||
1604 | return phy_mii_ioctl(phydev, req, cmd); | |
1605 | } | |
1606 | ||
1607 | static const struct net_device_ops ravb_netdev_ops = { | |
1608 | .ndo_open = ravb_open, | |
1609 | .ndo_stop = ravb_close, | |
1610 | .ndo_start_xmit = ravb_start_xmit, | |
1611 | .ndo_select_queue = ravb_select_queue, | |
1612 | .ndo_get_stats = ravb_get_stats, | |
1613 | .ndo_set_rx_mode = ravb_set_rx_mode, | |
1614 | .ndo_tx_timeout = ravb_tx_timeout, | |
1615 | .ndo_do_ioctl = ravb_do_ioctl, | |
1616 | .ndo_validate_addr = eth_validate_addr, | |
1617 | .ndo_set_mac_address = eth_mac_addr, | |
1618 | .ndo_change_mtu = eth_change_mtu, | |
1619 | }; | |
1620 | ||
1621 | /* MDIO bus init function */ | |
1622 | static int ravb_mdio_init(struct ravb_private *priv) | |
1623 | { | |
1624 | struct platform_device *pdev = priv->pdev; | |
1625 | struct device *dev = &pdev->dev; | |
1626 | int error; | |
1627 | ||
1628 | /* Bitbang init */ | |
1629 | priv->mdiobb.ops = &bb_ops; | |
1630 | ||
1631 | /* MII controller setting */ | |
1632 | priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); | |
1633 | if (!priv->mii_bus) | |
1634 | return -ENOMEM; | |
1635 | ||
1636 | /* Hook up MII support for ethtool */ | |
1637 | priv->mii_bus->name = "ravb_mii"; | |
1638 | priv->mii_bus->parent = dev; | |
1639 | snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", | |
1640 | pdev->name, pdev->id); | |
1641 | ||
1642 | /* Register MDIO bus */ | |
1643 | error = of_mdiobus_register(priv->mii_bus, dev->of_node); | |
1644 | if (error) | |
1645 | goto out_free_bus; | |
1646 | ||
1647 | return 0; | |
1648 | ||
1649 | out_free_bus: | |
1650 | free_mdio_bitbang(priv->mii_bus); | |
1651 | return error; | |
1652 | } | |
1653 | ||
1654 | /* MDIO bus release function */ | |
1655 | static int ravb_mdio_release(struct ravb_private *priv) | |
1656 | { | |
1657 | /* Unregister mdio bus */ | |
1658 | mdiobus_unregister(priv->mii_bus); | |
1659 | ||
1660 | /* Free bitbang info */ | |
1661 | free_mdio_bitbang(priv->mii_bus); | |
1662 | ||
1663 | return 0; | |
1664 | } | |
1665 | ||
22d4df8f KM |
1666 | static const struct of_device_id ravb_match_table[] = { |
1667 | { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, | |
1668 | { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, | |
0e874361 | 1669 | { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, |
22d4df8f | 1670 | { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, |
0e874361 | 1671 | { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, |
22d4df8f KM |
1672 | { } |
1673 | }; | |
1674 | MODULE_DEVICE_TABLE(of, ravb_match_table); | |
1675 | ||
b3d39a88 SH |
1676 | static int ravb_set_gti(struct net_device *ndev) |
1677 | { | |
1678 | ||
1679 | struct device *dev = ndev->dev.parent; | |
1680 | struct device_node *np = dev->of_node; | |
1681 | unsigned long rate; | |
1682 | struct clk *clk; | |
1683 | uint64_t inc; | |
1684 | ||
1685 | clk = of_clk_get(np, 0); | |
1686 | if (IS_ERR(clk)) { | |
1687 | dev_err(dev, "could not get clock\n"); | |
1688 | return PTR_ERR(clk); | |
1689 | } | |
1690 | ||
1691 | rate = clk_get_rate(clk); | |
1692 | clk_put(clk); | |
1693 | ||
1694 | inc = 1000000000ULL << 20; | |
1695 | do_div(inc, rate); | |
1696 | ||
1697 | if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { | |
1698 | dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", | |
1699 | inc, GTI_TIV_MIN, GTI_TIV_MAX); | |
1700 | return -EINVAL; | |
1701 | } | |
1702 | ||
1703 | ravb_write(ndev, inc, GTI); | |
1704 | ||
1705 | return 0; | |
1706 | } | |
1707 | ||
c156633f SS |
1708 | static int ravb_probe(struct platform_device *pdev) |
1709 | { | |
1710 | struct device_node *np = pdev->dev.of_node; | |
1711 | struct ravb_private *priv; | |
22d4df8f | 1712 | enum ravb_chip_id chip_id; |
c156633f SS |
1713 | struct net_device *ndev; |
1714 | int error, irq, q; | |
1715 | struct resource *res; | |
1716 | ||
1717 | if (!np) { | |
1718 | dev_err(&pdev->dev, | |
1719 | "this driver is required to be instantiated from device tree\n"); | |
1720 | return -EINVAL; | |
1721 | } | |
1722 | ||
1723 | /* Get base address */ | |
1724 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1725 | if (!res) { | |
1726 | dev_err(&pdev->dev, "invalid resource\n"); | |
1727 | return -EINVAL; | |
1728 | } | |
1729 | ||
1730 | ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), | |
1731 | NUM_TX_QUEUE, NUM_RX_QUEUE); | |
1732 | if (!ndev) | |
1733 | return -ENOMEM; | |
1734 | ||
1735 | pm_runtime_enable(&pdev->dev); | |
1736 | pm_runtime_get_sync(&pdev->dev); | |
1737 | ||
1738 | /* The Ether-specific entries in the device structure. */ | |
1739 | ndev->base_addr = res->start; | |
1740 | ndev->dma = -1; | |
22d4df8f | 1741 | |
e8668630 | 1742 | chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); |
22d4df8f KM |
1743 | |
1744 | if (chip_id == RCAR_GEN3) | |
1745 | irq = platform_get_irq_byname(pdev, "ch22"); | |
1746 | else | |
1747 | irq = platform_get_irq(pdev, 0); | |
c156633f | 1748 | if (irq < 0) { |
f375339e | 1749 | error = irq; |
c156633f SS |
1750 | goto out_release; |
1751 | } | |
1752 | ndev->irq = irq; | |
1753 | ||
1754 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1755 | ||
1756 | priv = netdev_priv(ndev); | |
1757 | priv->ndev = ndev; | |
1758 | priv->pdev = pdev; | |
1759 | priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; | |
1760 | priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; | |
1761 | priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; | |
1762 | priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; | |
1763 | priv->addr = devm_ioremap_resource(&pdev->dev, res); | |
1764 | if (IS_ERR(priv->addr)) { | |
1765 | error = PTR_ERR(priv->addr); | |
1766 | goto out_release; | |
1767 | } | |
1768 | ||
1769 | spin_lock_init(&priv->lock); | |
1770 | INIT_WORK(&priv->work, ravb_tx_timeout_work); | |
1771 | ||
1772 | priv->phy_interface = of_get_phy_mode(np); | |
1773 | ||
1774 | priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); | |
1775 | priv->avb_link_active_low = | |
1776 | of_property_read_bool(np, "renesas,ether-link-active-low"); | |
1777 | ||
22d4df8f KM |
1778 | if (chip_id == RCAR_GEN3) { |
1779 | irq = platform_get_irq_byname(pdev, "ch24"); | |
1780 | if (irq < 0) { | |
1781 | error = irq; | |
1782 | goto out_release; | |
1783 | } | |
1784 | priv->emac_irq = irq; | |
1785 | } | |
1786 | ||
1787 | priv->chip_id = chip_id; | |
1788 | ||
c156633f SS |
1789 | /* Set function */ |
1790 | ndev->netdev_ops = &ravb_netdev_ops; | |
1791 | ndev->ethtool_ops = &ravb_ethtool_ops; | |
1792 | ||
1793 | /* Set AVB config mode */ | |
f5d7837f | 1794 | if (chip_id == RCAR_GEN2) { |
568b3ce7 | 1795 | ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); |
f5d7837f | 1796 | /* Set CSEL value */ |
568b3ce7 | 1797 | ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); |
f5d7837f | 1798 | } else { |
568b3ce7 SS |
1799 | ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | |
1800 | CCC_GAC | CCC_CSEL_HPB); | |
f5d7837f | 1801 | } |
c156633f | 1802 | |
c156633f | 1803 | /* Set GTI value */ |
b3d39a88 SH |
1804 | error = ravb_set_gti(ndev); |
1805 | if (error) | |
1806 | goto out_release; | |
c156633f SS |
1807 | |
1808 | /* Request GTI loading */ | |
568b3ce7 | 1809 | ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); |
c156633f SS |
1810 | |
1811 | /* Allocate descriptor base address table */ | |
1812 | priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; | |
e2dbb33a | 1813 | priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, |
c156633f SS |
1814 | &priv->desc_bat_dma, GFP_KERNEL); |
1815 | if (!priv->desc_bat) { | |
c4511132 | 1816 | dev_err(&pdev->dev, |
c156633f SS |
1817 | "Cannot allocate desc base address table (size %d bytes)\n", |
1818 | priv->desc_bat_size); | |
1819 | error = -ENOMEM; | |
1820 | goto out_release; | |
1821 | } | |
1822 | for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) | |
1823 | priv->desc_bat[q].die_dt = DT_EOS; | |
1824 | ravb_write(ndev, priv->desc_bat_dma, DBAT); | |
1825 | ||
1826 | /* Initialise HW timestamp list */ | |
1827 | INIT_LIST_HEAD(&priv->ts_skb_list); | |
1828 | ||
f5d7837f KM |
1829 | /* Initialise PTP Clock driver */ |
1830 | if (chip_id != RCAR_GEN2) | |
1831 | ravb_ptp_init(ndev, pdev); | |
1832 | ||
c156633f SS |
1833 | /* Debug message level */ |
1834 | priv->msg_enable = RAVB_DEF_MSG_ENABLE; | |
1835 | ||
1836 | /* Read and set MAC address */ | |
1837 | ravb_read_mac_address(ndev, of_get_mac_address(np)); | |
1838 | if (!is_valid_ether_addr(ndev->dev_addr)) { | |
1839 | dev_warn(&pdev->dev, | |
1840 | "no valid MAC address supplied, using a random one\n"); | |
1841 | eth_hw_addr_random(ndev); | |
1842 | } | |
1843 | ||
1844 | /* MDIO bus init */ | |
1845 | error = ravb_mdio_init(priv); | |
1846 | if (error) { | |
c4511132 | 1847 | dev_err(&pdev->dev, "failed to initialize MDIO\n"); |
c156633f SS |
1848 | goto out_dma_free; |
1849 | } | |
1850 | ||
1851 | netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); | |
1852 | netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); | |
1853 | ||
1854 | /* Network device register */ | |
1855 | error = register_netdev(ndev); | |
1856 | if (error) | |
1857 | goto out_napi_del; | |
1858 | ||
1859 | /* Print device information */ | |
1860 | netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", | |
1861 | (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); | |
1862 | ||
1863 | platform_set_drvdata(pdev, ndev); | |
1864 | ||
1865 | return 0; | |
1866 | ||
1867 | out_napi_del: | |
1868 | netif_napi_del(&priv->napi[RAVB_NC]); | |
1869 | netif_napi_del(&priv->napi[RAVB_BE]); | |
1870 | ravb_mdio_release(priv); | |
1871 | out_dma_free: | |
e2dbb33a | 1872 | dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, |
c156633f | 1873 | priv->desc_bat_dma); |
f5d7837f KM |
1874 | |
1875 | /* Stop PTP Clock driver */ | |
1876 | if (chip_id != RCAR_GEN2) | |
1877 | ravb_ptp_stop(ndev); | |
c156633f SS |
1878 | out_release: |
1879 | if (ndev) | |
1880 | free_netdev(ndev); | |
1881 | ||
1882 | pm_runtime_put(&pdev->dev); | |
1883 | pm_runtime_disable(&pdev->dev); | |
1884 | return error; | |
1885 | } | |
1886 | ||
1887 | static int ravb_remove(struct platform_device *pdev) | |
1888 | { | |
1889 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1890 | struct ravb_private *priv = netdev_priv(ndev); | |
1891 | ||
f5d7837f KM |
1892 | /* Stop PTP Clock driver */ |
1893 | if (priv->chip_id != RCAR_GEN2) | |
1894 | ravb_ptp_stop(ndev); | |
1895 | ||
e2dbb33a | 1896 | dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, |
c156633f SS |
1897 | priv->desc_bat_dma); |
1898 | /* Set reset mode */ | |
1899 | ravb_write(ndev, CCC_OPC_RESET, CCC); | |
1900 | pm_runtime_put_sync(&pdev->dev); | |
1901 | unregister_netdev(ndev); | |
1902 | netif_napi_del(&priv->napi[RAVB_NC]); | |
1903 | netif_napi_del(&priv->napi[RAVB_BE]); | |
1904 | ravb_mdio_release(priv); | |
1905 | pm_runtime_disable(&pdev->dev); | |
1906 | free_netdev(ndev); | |
1907 | platform_set_drvdata(pdev, NULL); | |
1908 | ||
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | #ifdef CONFIG_PM | |
1913 | static int ravb_runtime_nop(struct device *dev) | |
1914 | { | |
1915 | /* Runtime PM callback shared between ->runtime_suspend() | |
1916 | * and ->runtime_resume(). Simply returns success. | |
1917 | * | |
1918 | * This driver re-initializes all registers after | |
1919 | * pm_runtime_get_sync() anyway so there is no need | |
1920 | * to save and restore registers here. | |
1921 | */ | |
1922 | return 0; | |
1923 | } | |
1924 | ||
1925 | static const struct dev_pm_ops ravb_dev_pm_ops = { | |
1926 | .runtime_suspend = ravb_runtime_nop, | |
1927 | .runtime_resume = ravb_runtime_nop, | |
1928 | }; | |
1929 | ||
1930 | #define RAVB_PM_OPS (&ravb_dev_pm_ops) | |
1931 | #else | |
1932 | #define RAVB_PM_OPS NULL | |
1933 | #endif | |
1934 | ||
c156633f SS |
1935 | static struct platform_driver ravb_driver = { |
1936 | .probe = ravb_probe, | |
1937 | .remove = ravb_remove, | |
1938 | .driver = { | |
1939 | .name = "ravb", | |
1940 | .pm = RAVB_PM_OPS, | |
1941 | .of_match_table = ravb_match_table, | |
1942 | }, | |
1943 | }; | |
1944 | ||
1945 | module_platform_driver(ravb_driver); | |
1946 | ||
1947 | MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); | |
1948 | MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); | |
1949 | MODULE_LICENSE("GPL v2"); |