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sh_eth: reuse sh_eth_chip_reset()
[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
b2b14d2f 6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
2274d375
SS		 55#define SH_ETH_OFFSET_INVALID ((u16)~0)
56
3365711d
BH		 57#define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
c0013f6f 60static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 61 SH_ETH_OFFSET_DEFAULTS,
62
c0013f6f
SS		 63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155};
156
db893473 157static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 158 SH_ETH_OFFSET_DEFAULTS,
159
db893473
SH		 160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
206 [TSU_TEN] = 0x0064,
207 [TSU_ADRH0] = 0x0100,
db893473
SH		 208
209 [TXNLCR0] = 0x0080,
210 [TXALCR0] = 0x0084,
211 [RXNLCR0] = 0x0088,
212 [RXALCR0] = 0x008C,
213};
214
a3f109bd 215static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 216 SH_ETH_OFFSET_DEFAULTS,
217
a3f109bd
SS		 218 [ECMR] = 0x0300,
219 [RFLR] = 0x0308,
220 [ECSR] = 0x0310,
221 [ECSIPR] = 0x0318,
222 [PIR] = 0x0320,
223 [PSR] = 0x0328,
224 [RDMLR] = 0x0340,
225 [IPGR] = 0x0350,
226 [APR] = 0x0354,
227 [MPR] = 0x0358,
228 [RFCF] = 0x0360,
229 [TPAUSER] = 0x0364,
230 [TPAUSECR] = 0x0368,
231 [MAHR] = 0x03c0,
232 [MALR] = 0x03c8,
233 [TROCR] = 0x03d0,
234 [CDCR] = 0x03d4,
235 [LCCR] = 0x03d8,
236 [CNDCR] = 0x03dc,
237 [CEFCR] = 0x03e4,
238 [FRECR] = 0x03e8,
239 [TSFRCR] = 0x03ec,
240 [TLFRCR] = 0x03f0,
241 [RFCR] = 0x03f4,
242 [MAFCR] = 0x03f8,
243
244 [EDMR] = 0x0200,
245 [EDTRR] = 0x0208,
246 [EDRRR] = 0x0210,
247 [TDLAR] = 0x0218,
248 [RDLAR] = 0x0220,
249 [EESR] = 0x0228,
250 [EESIPR] = 0x0230,
251 [TRSCER] = 0x0238,
252 [RMFCR] = 0x0240,
253 [TFTR] = 0x0248,
254 [FDR] = 0x0250,
255 [RMCR] = 0x0258,
256 [TFUCR] = 0x0264,
257 [RFOCR] = 0x0268,
55754f19 258 [RMIIMODE] = 0x026c,
a3f109bd
SS		 259 [FCFTR] = 0x0270,
260 [TRIMD] = 0x027c,
261};
262
c0013f6f 263static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 264 SH_ETH_OFFSET_DEFAULTS,
265
c0013f6f
SS		 266 [ECMR] = 0x0100,
267 [RFLR] = 0x0108,
268 [ECSR] = 0x0110,
269 [ECSIPR] = 0x0118,
270 [PIR] = 0x0120,
271 [PSR] = 0x0128,
272 [RDMLR] = 0x0140,
273 [IPGR] = 0x0150,
274 [APR] = 0x0154,
275 [MPR] = 0x0158,
276 [TPAUSER] = 0x0164,
277 [RFCF] = 0x0160,
278 [TPAUSECR] = 0x0168,
279 [BCFRR] = 0x016c,
280 [MAHR] = 0x01c0,
281 [MALR] = 0x01c8,
282 [TROCR] = 0x01d0,
283 [CDCR] = 0x01d4,
284 [LCCR] = 0x01d8,
285 [CNDCR] = 0x01dc,
286 [CEFCR] = 0x01e4,
287 [FRECR] = 0x01e8,
288 [TSFRCR] = 0x01ec,
289 [TLFRCR] = 0x01f0,
290 [RFCR] = 0x01f4,
291 [MAFCR] = 0x01f8,
292 [RTRATE] = 0x01fc,
293
294 [EDMR] = 0x0000,
295 [EDTRR] = 0x0008,
296 [EDRRR] = 0x0010,
297 [TDLAR] = 0x0018,
298 [RDLAR] = 0x0020,
299 [EESR] = 0x0028,
300 [EESIPR] = 0x0030,
301 [TRSCER] = 0x0038,
302 [RMFCR] = 0x0040,
303 [TFTR] = 0x0048,
304 [FDR] = 0x0050,
305 [RMCR] = 0x0058,
306 [TFUCR] = 0x0064,
307 [RFOCR] = 0x0068,
308 [FCFTR] = 0x0070,
309 [RPADIR] = 0x0078,
310 [TRIMD] = 0x007c,
311 [RBWAR] = 0x00c8,
312 [RDFAR] = 0x00cc,
313 [TBRAR] = 0x00d4,
314 [TDFAR] = 0x00d8,
315};
316
317static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 318 SH_ETH_OFFSET_DEFAULTS,
319
d8b0426a
SS		 320 [EDMR] = 0x0000,
321 [EDTRR] = 0x0004,
322 [EDRRR] = 0x0008,
323 [TDLAR] = 0x000c,
324 [RDLAR] = 0x0010,
325 [EESR] = 0x0014,
326 [EESIPR] = 0x0018,
327 [TRSCER] = 0x001c,
328 [RMFCR] = 0x0020,
329 [TFTR] = 0x0024,
330 [FDR] = 0x0028,
331 [RMCR] = 0x002c,
332 [EDOCR] = 0x0030,
333 [FCFTR] = 0x0034,
334 [RPADIR] = 0x0038,
335 [TRIMD] = 0x003c,
336 [RBWAR] = 0x0040,
337 [RDFAR] = 0x0044,
338 [TBRAR] = 0x004c,
339 [TDFAR] = 0x0050,
340
c0013f6f
SS		 341 [ECMR] = 0x0160,
342 [ECSR] = 0x0164,
343 [ECSIPR] = 0x0168,
344 [PIR] = 0x016c,
345 [MAHR] = 0x0170,
346 [MALR] = 0x0174,
347 [RFLR] = 0x0178,
348 [PSR] = 0x017c,
349 [TROCR] = 0x0180,
350 [CDCR] = 0x0184,
351 [LCCR] = 0x0188,
352 [CNDCR] = 0x018c,
353 [CEFCR] = 0x0194,
354 [FRECR] = 0x0198,
355 [TSFRCR] = 0x019c,
356 [TLFRCR] = 0x01a0,
357 [RFCR] = 0x01a4,
358 [MAFCR] = 0x01a8,
359 [IPGR] = 0x01b4,
360 [APR] = 0x01b8,
361 [MPR] = 0x01bc,
362 [TPAUSER] = 0x01c4,
363 [BCFR] = 0x01cc,
364
365 [ARSTR] = 0x0000,
366 [TSU_CTRST] = 0x0004,
367 [TSU_FWEN0] = 0x0010,
368 [TSU_FWEN1] = 0x0014,
369 [TSU_FCM] = 0x0018,
370 [TSU_BSYSL0] = 0x0020,
371 [TSU_BSYSL1] = 0x0024,
372 [TSU_PRISL0] = 0x0028,
373 [TSU_PRISL1] = 0x002c,
374 [TSU_FWSL0] = 0x0030,
375 [TSU_FWSL1] = 0x0034,
376 [TSU_FWSLC] = 0x0038,
377 [TSU_QTAGM0] = 0x0040,
378 [TSU_QTAGM1] = 0x0044,
379 [TSU_ADQT0] = 0x0048,
380 [TSU_ADQT1] = 0x004c,
381 [TSU_FWSR] = 0x0050,
382 [TSU_FWINMK] = 0x0054,
383 [TSU_ADSBSY] = 0x0060,
384 [TSU_TEN] = 0x0064,
385 [TSU_POST1] = 0x0070,
386 [TSU_POST2] = 0x0074,
387 [TSU_POST3] = 0x0078,
388 [TSU_POST4] = 0x007c,
389
390 [TXNLCR0] = 0x0080,
391 [TXALCR0] = 0x0084,
392 [RXNLCR0] = 0x0088,
393 [RXALCR0] = 0x008c,
394 [FWNLCR0] = 0x0090,
395 [FWALCR0] = 0x0094,
396 [TXNLCR1] = 0x00a0,
397 [TXALCR1] = 0x00a0,
398 [RXNLCR1] = 0x00a8,
399 [RXALCR1] = 0x00ac,
400 [FWNLCR1] = 0x00b0,
401 [FWALCR1] = 0x00b4,
402
403 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 404};
405
740c7f31
BH		 406static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
408
2274d375
SS		 409static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
410{
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412 u16 offset = mdp->reg_offset[enum_index];
413
414 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
415 return;
416
417 iowrite32(data, mdp->addr + offset);
418}
419
420static u32 sh_eth_read(struct net_device *ndev, int enum_index)
421{
422 struct sh_eth_private *mdp = netdev_priv(ndev);
423 u16 offset = mdp->reg_offset[enum_index];
424
425 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
426 return ~0U;
427
428 return ioread32(mdp->addr + offset);
429}
430
b2b14d2f
SS		 431static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
432 u32 set)
433{
434 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
435 enum_index);
436}
437
504c8ca5 438static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 439{
504c8ca5 440 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 441}
442
db893473
SH		 443static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
444{
445 return mdp->reg_offset == sh_eth_offset_fast_rz;
446}
447
8e994402 448static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be 449{
5e7a76be 450 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 451 u32 value;
5e7a76be
NI		 452
453 switch (mdp->phy_interface) {
454 case PHY_INTERFACE_MODE_GMII:
455 value = 0x2;
456 break;
457 case PHY_INTERFACE_MODE_MII:
458 value = 0x1;
459 break;
460 case PHY_INTERFACE_MODE_RMII:
461 value = 0x0;
462 break;
463 default:
f75f14ec
SS		 464 netdev_warn(ndev,
465 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 466 value = 0x1;
467 break;
468 }
469
470 sh_eth_write(ndev, value, RMII_MII);
471}
5e7a76be 472
8e994402 473static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 474{
475 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851 476
b2b14d2f 477 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
65ac8851
YS		 478}
479
99f84be6
GU		 480static void sh_eth_chip_reset(struct net_device *ndev)
481{
482 struct sh_eth_private *mdp = netdev_priv(ndev);
483
484 /* reset device */
ec65cfce 485 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
99f84be6
GU		 486 mdelay(1);
487}
488
a0f48be3
GU		 489static void sh_eth_set_rate_gether(struct net_device *ndev)
490{
491 struct sh_eth_private *mdp = netdev_priv(ndev);
492
493 switch (mdp->speed) {
494 case 10: /* 10BASE */
495 sh_eth_write(ndev, GECMR_10, GECMR);
496 break;
497 case 100:/* 100BASE */
498 sh_eth_write(ndev, GECMR_100, GECMR);
499 break;
500 case 1000: /* 1000BASE */
501 sh_eth_write(ndev, GECMR_1000, GECMR);
502 break;
a0f48be3
GU		 503 }
504}
505
99f84be6
GU		 506#ifdef CONFIG_OF
507/* R7S72100 */
508static struct sh_eth_cpu_data r7s72100_data = {
509 .chip_reset = sh_eth_chip_reset,
510 .set_duplex = sh_eth_set_duplex,
511
512 .register_type = SH_ETH_REG_FAST_RZ,
513
514 .ecsr_value = ECSR_ICD,
515 .ecsipr_value = ECSIPR_ICDIP,
516 .eesipr_value = 0xff7f009f,
517
518 .tx_check = EESR_TC1 | EESR_FTC,
519 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
520 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
521 EESR_TDE | EESR_ECI,
522 .fdr_value = 0x0000070f,
523
524 .no_psr = 1,
525 .apr = 1,
526 .mpr = 1,
527 .tpauser = 1,
528 .hw_swap = 1,
529 .rpadir = 1,
530 .rpadir_value = 2 << 16,
531 .no_trimd = 1,
532 .no_ade = 1,
533 .hw_crc = 1,
534 .tsu = 1,
535 .shift_rd0 = 1,
536};
a0f48be3
GU		 537
538static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
539{
c66b2581 540 sh_eth_chip_reset(ndev);
a0f48be3
GU		 541
542 sh_eth_select_mii(ndev);
543}
544
545/* R8A7740 */
546static struct sh_eth_cpu_data r8a7740_data = {
547 .chip_reset = sh_eth_chip_reset_r8a7740,
548 .set_duplex = sh_eth_set_duplex,
549 .set_rate = sh_eth_set_rate_gether,
550
551 .register_type = SH_ETH_REG_GIGABIT,
552
553 .ecsr_value = ECSR_ICD | ECSR_MPD,
554 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
555 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
556
557 .tx_check = EESR_TC1 | EESR_FTC,
558 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
559 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
560 EESR_TDE | EESR_ECI,
561 .fdr_value = 0x0000070f,
562
563 .apr = 1,
564 .mpr = 1,
565 .tpauser = 1,
566 .bculr = 1,
567 .hw_swap = 1,
568 .rpadir = 1,
569 .rpadir_value = 2 << 16,
570 .no_trimd = 1,
571 .no_ade = 1,
572 .tsu = 1,
573 .select_mii = 1,
574 .shift_rd0 = 1,
575};
99f84be6 576
04b0ed2a 577/* There is CPU dependent code */
589ebdef 578static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 579{
580 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 581
a3f109bd
SS		 582 switch (mdp->speed) {
583 case 10: /* 10BASE */
b2b14d2f 584 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
a3f109bd
SS		 585 break;
586 case 100:/* 100BASE */
b2b14d2f 587 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
a3f109bd 588 break;
a3f109bd
SS		 589 }
590}
591
674853b2 592/* R8A7778/9 */
589ebdef 593static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 594 .set_duplex = sh_eth_set_duplex,
589ebdef 595 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 596
a3153d8c
SS		 597 .register_type = SH_ETH_REG_FAST_RCAR,
598
a3f109bd
SS		 599 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
600 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
601 .eesipr_value = 0x01ff009f,
602
603 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 604 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
605 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
606 EESR_ECI,
d407bc02 607 .fdr_value = 0x00000f0f,
a3f109bd
SS		 608
609 .apr = 1,
610 .mpr = 1,
611 .tpauser = 1,
612 .hw_swap = 1,
613};
a3f109bd 614
94a12b15
SS		 615/* R8A7790/1 */
616static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 617 .set_duplex = sh_eth_set_duplex,
618 .set_rate = sh_eth_set_rate_r8a777x,
619
a3153d8c
SS		 620 .register_type = SH_ETH_REG_FAST_RCAR,
621
e18dbf7e
SH		 622 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
623 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
624 .eesipr_value = 0x01ff009f,
625
626 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 627 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
628 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
629 EESR_ECI,
d407bc02 630 .fdr_value = 0x00000f0f,
e18dbf7e 631
01fbd3f5
GU		 632 .trscer_err_mask = DESC_I_RINT8,
633
e18dbf7e
SH		 634 .apr = 1,
635 .mpr = 1,
636 .tpauser = 1,
637 .hw_swap = 1,
638 .rmiimode = 1,
639};
c74a2248 640#endif /* CONFIG_OF */
e18dbf7e 641
9c3beaab 642static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 643{
644 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 645
646 switch (mdp->speed) {
647 case 10: /* 10BASE */
b2b14d2f 648 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
65ac8851
YS		 649 break;
650 case 100:/* 100BASE */
b2b14d2f 651 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
65ac8851 652 break;
65ac8851
YS		 653 }
654}
655
656/* SH7724 */
9c3beaab 657static struct sh_eth_cpu_data sh7724_data = {
65ac8851 658 .set_duplex = sh_eth_set_duplex,
9c3beaab 659 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 660
a3153d8c
SS		 661 .register_type = SH_ETH_REG_FAST_SH4,
662
65ac8851
YS		 663 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
664 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 665 .eesipr_value = 0x01ff009f,
65ac8851
YS		 666
667 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 668 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
669 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
670 EESR_ECI,
65ac8851
YS		 671
672 .apr = 1,
673 .mpr = 1,
674 .tpauser = 1,
675 .hw_swap = 1,
503914cf
MD		 676 .rpadir = 1,
677 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 678};
5cee1d37 679
24549e2a 680static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 681{
682 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 683
684 switch (mdp->speed) {
685 case 10: /* 10BASE */
4a55530f 686 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 687 break;
688 case 100:/* 100BASE */
4a55530f 689 sh_eth_write(ndev, 1, RTRATE);
f29a3d04 690 break;
f29a3d04
YS		 691 }
692}
693
694/* SH7757 */
24549e2a
SS		 695static struct sh_eth_cpu_data sh7757_data = {
696 .set_duplex = sh_eth_set_duplex,
697 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 698
a3153d8c
SS		 699 .register_type = SH_ETH_REG_FAST_SH4,
700
f29a3d04 701 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 702
703 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 704 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
705 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
706 EESR_ECI,
f29a3d04 707
5b3dfd13 708 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 709 .apr = 1,
710 .mpr = 1,
711 .tpauser = 1,
712 .hw_swap = 1,
713 .no_ade = 1,
2e98e797
YS		 714 .rpadir = 1,
715 .rpadir_value = 2 << 16,
6b4b4fea 716 .rtrate = 1,
f29a3d04 717};
65ac8851 718
e403d295 719#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 720#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
721#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
722static void sh_eth_chip_reset_giga(struct net_device *ndev)
723{
0799c2d6 724 u32 mahr[2], malr[2];
79270922 725 int i;
8fcd4961
YS		 726
727 /* save MAHR and MALR */
728 for (i = 0; i < 2; i++) {
ae70644d
YS		 729 malr[i] = ioread32((void *)GIGA_MALR(i));
730 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 731 }
732
c66b2581 733 sh_eth_chip_reset(ndev);
8fcd4961
YS		 734
735 /* restore MAHR and MALR */
736 for (i = 0; i < 2; i++) {
ae70644d
YS		 737 iowrite32(malr[i], (void *)GIGA_MALR(i));
738 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 739 }
740}
741
8fcd4961
YS		 742static void sh_eth_set_rate_giga(struct net_device *ndev)
743{
744 struct sh_eth_private *mdp = netdev_priv(ndev);
745
746 switch (mdp->speed) {
747 case 10: /* 10BASE */
748 sh_eth_write(ndev, 0x00000000, GECMR);
749 break;
750 case 100:/* 100BASE */
751 sh_eth_write(ndev, 0x00000010, GECMR);
752 break;
753 case 1000: /* 1000BASE */
754 sh_eth_write(ndev, 0x00000020, GECMR);
755 break;
8fcd4961
YS		 756 }
757}
758
759/* SH7757(GETHERC) */
24549e2a 760static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 761 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 762 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 763 .set_rate = sh_eth_set_rate_giga,
764
a3153d8c
SS		 765 .register_type = SH_ETH_REG_GIGABIT,
766
8fcd4961
YS		 767 .ecsr_value = ECSR_ICD | ECSR_MPD,
768 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
769 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
770
771 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 772 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
773 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
774 EESR_TDE | EESR_ECI,
8fcd4961 775 .fdr_value = 0x0000072f,
8fcd4961 776
5b3dfd13 777 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 778 .apr = 1,
779 .mpr = 1,
780 .tpauser = 1,
781 .bculr = 1,
782 .hw_swap = 1,
783 .rpadir = 1,
784 .rpadir_value = 2 << 16,
785 .no_trimd = 1,
786 .no_ade = 1,
3acbc971 787 .tsu = 1,
8fcd4961
YS		 788};
789
f5d12767
SS		 790/* SH7734 */
791static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 792 .chip_reset = sh_eth_chip_reset,
793 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 794 .set_rate = sh_eth_set_rate_gether,
795
a3153d8c
SS		 796 .register_type = SH_ETH_REG_GIGABIT,
797
f5d12767
SS		 798 .ecsr_value = ECSR_ICD | ECSR_MPD,
799 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
800 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
801
802 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 803 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
804 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
805 EESR_TDE | EESR_ECI,
f5d12767
SS		 806
807 .apr = 1,
808 .mpr = 1,
809 .tpauser = 1,
810 .bculr = 1,
811 .hw_swap = 1,
812 .no_trimd = 1,
813 .no_ade = 1,
814 .tsu = 1,
815 .hw_crc = 1,
816 .select_mii = 1,
817};
818
819/* SH7763 */
820static struct sh_eth_cpu_data sh7763_data = {
821 .chip_reset = sh_eth_chip_reset,
822 .set_duplex = sh_eth_set_duplex,
823 .set_rate = sh_eth_set_rate_gether,
380af9e3 824
a3153d8c
SS		 825 .register_type = SH_ETH_REG_GIGABIT,
826
380af9e3
YS		 827 .ecsr_value = ECSR_ICD | ECSR_MPD,
828 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
829 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
830
831 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 832 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
833 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 834 EESR_ECI,
380af9e3
YS		 835
836 .apr = 1,
837 .mpr = 1,
838 .tpauser = 1,
839 .bculr = 1,
840 .hw_swap = 1,
380af9e3
YS		 841 .no_trimd = 1,
842 .no_ade = 1,
4986b996 843 .tsu = 1,
5b3dfd13 844 .irq_flags = IRQF_SHARED,
380af9e3
YS		 845};
846
c18a79ab 847static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 848 .register_type = SH_ETH_REG_FAST_SH3_SH2,
849
380af9e3
YS		 850 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
851
852 .apr = 1,
853 .mpr = 1,
854 .tpauser = 1,
855 .hw_swap = 1,
856};
7bbe150d
SS		 857
858static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 859 .register_type = SH_ETH_REG_FAST_SH3_SH2,
860
380af9e3 861 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 862 .tsu = 1,
380af9e3 863};
380af9e3
YS		 864
865static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
866{
867 if (!cd->ecsr_value)
868 cd->ecsr_value = DEFAULT_ECSR_INIT;
869
870 if (!cd->ecsipr_value)
871 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
872
873 if (!cd->fcftr_value)
128296fc 874 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 875 DEFAULT_FIFO_F_D_RFD;
876
877 if (!cd->fdr_value)
878 cd->fdr_value = DEFAULT_FDR_INIT;
879
380af9e3
YS		 880 if (!cd->tx_check)
881 cd->tx_check = DEFAULT_TX_CHECK;
882
883 if (!cd->eesr_err_check)
884 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 885
886 if (!cd->trscer_err_mask)
887 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 888}
889
5cee1d37
NI		 890static int sh_eth_check_reset(struct net_device *ndev)
891{
892 int ret = 0;
893 int cnt = 100;
894
895 while (cnt > 0) {
97717edc 896 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
5cee1d37
NI		 897 break;
898 mdelay(1);
899 cnt--;
900 }
9f8c4265 901 if (cnt <= 0) {
f75f14ec 902 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 903 ret = -ETIMEDOUT;
904 }
905 return ret;
380af9e3 906}
dabdde9e
NI		 907
908static int sh_eth_reset(struct net_device *ndev)
909{
910 struct sh_eth_private *mdp = netdev_priv(ndev);
911 int ret = 0;
912
db893473 913 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e 914 sh_eth_write(ndev, EDSR_ENALL, EDSR);
b2b14d2f 915 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
dabdde9e
NI		 916
917 ret = sh_eth_check_reset(ndev);
918 if (ret)
f738a13d 919 return ret;
dabdde9e
NI		 920
921 /* Table Init */
922 sh_eth_write(ndev, 0x0, TDLAR);
923 sh_eth_write(ndev, 0x0, TDFAR);
924 sh_eth_write(ndev, 0x0, TDFXR);
925 sh_eth_write(ndev, 0x0, TDFFR);
926 sh_eth_write(ndev, 0x0, RDLAR);
927 sh_eth_write(ndev, 0x0, RDFAR);
928 sh_eth_write(ndev, 0x0, RDFXR);
929 sh_eth_write(ndev, 0x0, RDFFR);
930
931 /* Reset HW CRC register */
932 if (mdp->cd->hw_crc)
933 sh_eth_write(ndev, 0x0, CSMR);
934
935 /* Select MII mode */
936 if (mdp->cd->select_mii)
937 sh_eth_select_mii(ndev);
938 } else {
b2b14d2f 939 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
dabdde9e 940 mdelay(3);
b2b14d2f 941 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
dabdde9e
NI		 942 }
943
dabdde9e
NI		 944 return ret;
945}
380af9e3 946
380af9e3
YS		 947static void sh_eth_set_receive_align(struct sk_buff *skb)
948{
4d6a949c 949 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 950
380af9e3 951 if (reserve)
4d6a949c 952 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 953}
380af9e3 954
128296fc 955/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 956static void update_mac_address(struct net_device *ndev)
957{
4a55530f 958 sh_eth_write(ndev,
128296fc
SS		 959 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
960 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 961 sh_eth_write(ndev,
128296fc 962 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 963}
964
128296fc 965/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 966 *
967 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
968 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
969 * When you want use this device, you must set MAC address in bootloader.
970 *
971 */
748031f9 972static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 973{
748031f9 974 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 975 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 976 } else {
37742f02
SS		 977 u32 mahr = sh_eth_read(ndev, MAHR);
978 u32 malr = sh_eth_read(ndev, MALR);
979
980 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
981 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
982 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
983 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
984 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
985 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 986 }
86a74ff2
NI		 987}
988
0799c2d6 989static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 990{
db893473 991 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 992 return EDTRR_TRNS_GETHER;
993 else
994 return EDTRR_TRNS_ETHER;
995}
996
86a74ff2 997struct bb_info {
ae70644d 998 void (*set_gate)(void *addr);
86a74ff2 999 struct mdiobb_ctrl ctrl;
ae70644d 1000 void *addr;
86a74ff2
NI		 1001};
1002
39b4b06b 1003static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
86a74ff2
NI		 1004{
1005 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
78fa3c5c 1006 u32 pir;
b3017e6a
YS		 1007
1008 if (bitbang->set_gate)
1009 bitbang->set_gate(bitbang->addr);
1010
78fa3c5c 1011 pir = ioread32(bitbang->addr);
39b4b06b 1012 if (set)
78fa3c5c 1013 pir |= mask;
86a74ff2 1014 else
78fa3c5c
SS		 1015 pir &= ~mask;
1016 iowrite32(pir, bitbang->addr);
39b4b06b
SS		 1017}
1018
1019/* Data I/O pin control */
1020static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1021{
1022 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
86a74ff2
NI		 1023}
1024
1025/* Set bit data*/
1026static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1027{
39b4b06b 1028 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
86a74ff2
NI		 1029}
1030
1031/* Get bit data*/
1032static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1033{
1034 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1035
1036 if (bitbang->set_gate)
1037 bitbang->set_gate(bitbang->addr);
1038
78fa3c5c 1039 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
86a74ff2
NI		 1040}
1041
1042/* MDC pin control */
1043static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1044{
39b4b06b 1045 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
86a74ff2
NI		 1046}
1047
1048/* mdio bus control struct */
1049static struct mdiobb_ops bb_ops = {
1050 .owner = THIS_MODULE,
1051 .set_mdc = sh_mdc_ctrl,
1052 .set_mdio_dir = sh_mmd_ctrl,
1053 .set_mdio_data = sh_set_mdio,
1054 .get_mdio_data = sh_get_mdio,
1055};
1056
86a74ff2
NI		 1057/* free skb and descriptor buffer */
1058static void sh_eth_ring_free(struct net_device *ndev)
1059{
1060 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1061 int ringsize, i;
86a74ff2
NI		 1062
1063 /* Free Rx skb ringbuffer */
1064 if (mdp->rx_skbuff) {
179d80af
SS		 1065 for (i = 0; i < mdp->num_rx_ring; i++)
1066 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1067 }
1068 kfree(mdp->rx_skbuff);
91c77550 1069 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1070
1071 /* Free Tx skb ringbuffer */
1072 if (mdp->tx_skbuff) {
179d80af
SS		 1073 for (i = 0; i < mdp->num_tx_ring; i++)
1074 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1075 }
1076 kfree(mdp->tx_skbuff);
91c77550 1077 mdp->tx_skbuff = NULL;
8e03a5e7
SS		 1078
1079 if (mdp->rx_ring) {
1080 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1081 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1082 mdp->rx_desc_dma);
1083 mdp->rx_ring = NULL;
1084 }
1085
1086 if (mdp->tx_ring) {
1087 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1088 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1089 mdp->tx_desc_dma);
1090 mdp->tx_ring = NULL;
1091 }
86a74ff2
NI		 1092}
1093
1094/* format skb and descriptor buffer */
1095static void sh_eth_ring_format(struct net_device *ndev)
1096{
1097 struct sh_eth_private *mdp = netdev_priv(ndev);
1098 int i;
1099 struct sk_buff *skb;
1100 struct sh_eth_rxdesc *rxdesc = NULL;
1101 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1102 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1103 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1104 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1105 dma_addr_t dma_addr;
5cbf20c7 1106 u32 buf_len;
86a74ff2 1107
128296fc
SS		 1108 mdp->cur_rx = 0;
1109 mdp->cur_tx = 0;
1110 mdp->dirty_rx = 0;
1111 mdp->dirty_tx = 0;
86a74ff2
NI		 1112
1113 memset(mdp->rx_ring, 0, rx_ringsize);
1114
1115 /* build Rx ring buffer */
525b8075 1116 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1117 /* skb */
1118 mdp->rx_skbuff[i] = NULL;
4d6a949c 1119 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1120 if (skb == NULL)
1121 break;
380af9e3
YS		 1122 sh_eth_set_receive_align(skb);
1123
ab857916 1124 /* The size of the buffer is a multiple of 32 bytes. */
5cbf20c7 1125 buf_len = ALIGN(mdp->rx_buf_sz, 32);
5cbf20c7 1126 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
52b9fa36
BH		 1127 DMA_FROM_DEVICE);
1128 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1129 kfree_skb(skb);
1130 break;
1131 }
1132 mdp->rx_skbuff[i] = skb;
d0ba9134
SS		 1133
1134 /* RX descriptor */
1135 rxdesc = &mdp->rx_ring[i];
1136 rxdesc->len = cpu_to_le32(buf_len << 16);
7cf72477
SS		 1137 rxdesc->addr = cpu_to_le32(dma_addr);
1138 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2 1139
b0ca2a21
NI		 1140 /* Rx descriptor address set */
1141 if (i == 0) {
4a55530f 1142 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1143 if (sh_eth_is_gether(mdp) ||
1144 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1145 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1146 }
86a74ff2
NI		 1147 }
1148
525b8075 1149 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1150
1151 /* Mark the last entry as wrapping the ring. */
c1b7fca6
SS		 1152 if (rxdesc)
1153 rxdesc->status |= cpu_to_le32(RD_RDLE);
86a74ff2
NI		 1154
1155 memset(mdp->tx_ring, 0, tx_ringsize);
1156
1157 /* build Tx ring buffer */
525b8075 1158 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1159 mdp->tx_skbuff[i] = NULL;
1160 txdesc = &mdp->tx_ring[i];
7cf72477
SS		 1161 txdesc->status = cpu_to_le32(TD_TFP);
1162 txdesc->len = cpu_to_le32(0);
b0ca2a21 1163 if (i == 0) {
71557a37 1164 /* Tx descriptor address set */
4a55530f 1165 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1166 if (sh_eth_is_gether(mdp) ||
1167 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1168 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1169 }
86a74ff2
NI		 1170 }
1171
7cf72477 1172 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2
NI		 1173}
1174
1175/* Get skb and descriptor buffer */
1176static int sh_eth_ring_init(struct net_device *ndev)
1177{
1178 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1179 int rx_ringsize, tx_ringsize;
86a74ff2 1180
128296fc 1181 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1182 * card needs room to do 8 byte alignment, +2 so we can reserve
1183 * the first 2 bytes, and +16 gets room for the status word from the
1184 * card.
1185 */
1186 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1187 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1188 if (mdp->cd->rpadir)
1189 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1190
1191 /* Allocate RX and TX skb rings */
2c94e856
SS		 1192 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1193 GFP_KERNEL);
91d80683
SS		 1194 if (!mdp->rx_skbuff)
1195 return -ENOMEM;
86a74ff2 1196
2c94e856
SS		 1197 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1198 GFP_KERNEL);
91d80683 1199 if (!mdp->tx_skbuff)
8e03a5e7 1200 goto ring_free;
86a74ff2
NI		 1201
1202 /* Allocate all Rx descriptors. */
525b8075 1203 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1204 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1205 GFP_KERNEL);
91d80683 1206 if (!mdp->rx_ring)
8e03a5e7 1207 goto ring_free;
86a74ff2
NI		 1208
1209 mdp->dirty_rx = 0;
1210
1211 /* Allocate all Tx descriptors. */
525b8075 1212 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1213 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1214 GFP_KERNEL);
91d80683 1215 if (!mdp->tx_ring)
8e03a5e7 1216 goto ring_free;
91d80683 1217 return 0;
86a74ff2 1218
8e03a5e7
SS		 1219ring_free:
1220 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1221 sh_eth_ring_free(ndev);
1222
91d80683 1223 return -ENOMEM;
86a74ff2
NI		 1224}
1225
f7967210 1226static int sh_eth_dev_init(struct net_device *ndev)
86a74ff2 1227{
86a74ff2 1228 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1229 int ret;
86a74ff2
NI		 1230
1231 /* Soft Reset */
5cee1d37
NI		 1232 ret = sh_eth_reset(ndev);
1233 if (ret)
f738a13d 1234 return ret;
86a74ff2 1235
55754f19
SH		 1236 if (mdp->cd->rmiimode)
1237 sh_eth_write(ndev, 0x1, RMIIMODE);
1238
b0ca2a21
NI		 1239 /* Descriptor format */
1240 sh_eth_ring_format(ndev);
380af9e3 1241 if (mdp->cd->rpadir)
4a55530f 1242 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1243
1244 /* all sh_eth int mask */
4a55530f 1245 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1246
10b9194f 1247#if defined(__LITTLE_ENDIAN)
380af9e3 1248 if (mdp->cd->hw_swap)
4a55530f 1249 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1250 else
b0ca2a21 1251#endif
4a55530f 1252 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1253
b0ca2a21 1254 /* FIFO size set */
4a55530f
YS		 1255 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1256 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1257
530aa2d0
BD		 1258 /* Frame recv control (enable multiple-packets per rx irq) */
1259 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1260
b284fbe3 1261 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1262
380af9e3 1263 if (mdp->cd->bculr)
4a55530f 1264 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1265
4a55530f 1266 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1267
380af9e3 1268 if (!mdp->cd->no_trimd)
4a55530f 1269 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1270
b0ca2a21 1271 /* Recv frame limit set register */
fdb37a7f
YS		 1272 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1273 RFLR);
86a74ff2 1274
b2b14d2f 1275 sh_eth_modify(ndev, EESR, 0, 0);
f7967210
SS		 1276 mdp->irq_enabled = true;
1277 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1278
1279 /* PAUSE Prohibition */
bffa731f
SS		 1280 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1281 ECMR_TE | ECMR_RE, ECMR);
b0ca2a21 1282
380af9e3
YS		 1283 if (mdp->cd->set_rate)
1284 mdp->cd->set_rate(ndev);
1285
b0ca2a21 1286 /* E-MAC Status Register clear */
4a55530f 1287 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1288
1289 /* E-MAC Interrupt Enable register */
f7967210 1290 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1291
1292 /* Set MAC address */
1293 update_mac_address(ndev);
1294
1295 /* mask reset */
380af9e3 1296 if (mdp->cd->apr)
4a55530f 1297 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1298 if (mdp->cd->mpr)
4a55530f 1299 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1300 if (mdp->cd->tpauser)
4a55530f 1301 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1302
f7967210
SS		 1303 /* Setting the Rx mode will start the Rx process. */
1304 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 1305
1306 return ret;
1307}
1308
740c7f31
BH		 1309static void sh_eth_dev_exit(struct net_device *ndev)
1310{
1311 struct sh_eth_private *mdp = netdev_priv(ndev);
1312 int i;
1313
1314 /* Deactivate all TX descriptors, so DMA should stop at next
1315 * packet boundary if it's currently running
1316 */
1317 for (i = 0; i < mdp->num_tx_ring; i++)
7cf72477 1318 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
740c7f31
BH		 1319
1320 /* Disable TX FIFO egress to MAC */
1321 sh_eth_rcv_snd_disable(ndev);
1322
1323 /* Stop RX DMA at next packet boundary */
1324 sh_eth_write(ndev, 0, EDRRR);
1325
1326 /* Aside from TX DMA, we can't tell when the hardware is
1327 * really stopped, so we need to reset to make sure.
1328 * Before doing that, wait for long enough to *probably*
1329 * finish transmitting the last packet and poll stats.
1330 */
1331 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1332 sh_eth_get_stats(ndev);
1333 sh_eth_reset(ndev);
a14c7d15
GU		 1334
1335 /* Set MAC address again */
1336 update_mac_address(ndev);
740c7f31
BH		 1337}
1338
86a74ff2
NI		 1339/* free Tx skb function */
1340static int sh_eth_txfree(struct net_device *ndev)
1341{
1342 struct sh_eth_private *mdp = netdev_priv(ndev);
1343 struct sh_eth_txdesc *txdesc;
128296fc 1344 int free_num = 0;
4fa8c3cc 1345 int entry;
86a74ff2
NI		 1346
1347 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1348 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1349 txdesc = &mdp->tx_ring[entry];
7cf72477 1350 if (txdesc->status & cpu_to_le32(TD_TACT))
86a74ff2 1351 break;
7d7355f5 1352 /* TACT bit must be checked before all the following reads */
f32bfb9a 1353 dma_rmb();
e5fd13f4
BH		 1354 netif_info(mdp, tx_done, ndev,
1355 "tx entry %d status 0x%08x\n",
7cf72477 1356 entry, le32_to_cpu(txdesc->status));
86a74ff2
NI		 1357 /* Free the original skb. */
1358 if (mdp->tx_skbuff[entry]) {
7cf72477
SS		 1359 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1360 le32_to_cpu(txdesc->len) >> 16,
5cbf20c7 1361 DMA_TO_DEVICE);
86a74ff2
NI		 1362 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1363 mdp->tx_skbuff[entry] = NULL;
128296fc 1364 free_num++;
86a74ff2 1365 }
7cf72477 1366 txdesc->status = cpu_to_le32(TD_TFP);
525b8075 1367 if (entry >= mdp->num_tx_ring - 1)
7cf72477 1368 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2 1369
bb7d92e3 1370 ndev->stats.tx_packets++;
7cf72477 1371 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
86a74ff2 1372 }
128296fc 1373 return free_num;
86a74ff2
NI		 1374}
1375
1376/* Packet receive function */
3719109d 1377static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1378{
1379 struct sh_eth_private *mdp = netdev_priv(ndev);
1380 struct sh_eth_rxdesc *rxdesc;
1381
525b8075
YS		 1382 int entry = mdp->cur_rx % mdp->num_rx_ring;
1383 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1384 int limit;
86a74ff2 1385 struct sk_buff *skb;
380af9e3 1386 u32 desc_status;
cb368595 1387 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1388 dma_addr_t dma_addr;
4fa8c3cc 1389 u16 pkt_len;
5cbf20c7 1390 u32 buf_len;
86a74ff2 1391
319cd520
MK		 1392 boguscnt = min(boguscnt, *quota);
1393 limit = boguscnt;
86a74ff2 1394 rxdesc = &mdp->rx_ring[entry];
7cf72477 1395 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
7d7355f5 1396 /* RACT bit must be checked before all the following reads */
f32bfb9a 1397 dma_rmb();
7cf72477
SS		 1398 desc_status = le32_to_cpu(rxdesc->status);
1399 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
86a74ff2
NI		 1400
1401 if (--boguscnt < 0)
1402 break;
1403
e5fd13f4
BH		 1404 netif_info(mdp, rx_status, ndev,
1405 "rx entry %d status 0x%08x len %d\n",
1406 entry, desc_status, pkt_len);
1407
86a74ff2 1408 if (!(desc_status & RDFEND))
bb7d92e3 1409 ndev->stats.rx_length_errors++;
86a74ff2 1410
128296fc 1411 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1412 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1413 * bit 0. However, in case of the R8A7740 and R7S72100
1414 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1415 * driver needs right shifting by 16.
dd019897 1416 */
ac8025a6
SS		 1417 if (mdp->cd->shift_rd0)
1418 desc_status >>= 16;
dd019897 1419
248be83d 1420 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1421 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1422 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1423 ndev->stats.rx_errors++;
86a74ff2 1424 if (desc_status & RD_RFS1)
bb7d92e3 1425 ndev->stats.rx_crc_errors++;
86a74ff2 1426 if (desc_status & RD_RFS2)
bb7d92e3 1427 ndev->stats.rx_frame_errors++;
86a74ff2 1428 if (desc_status & RD_RFS3)
bb7d92e3 1429 ndev->stats.rx_length_errors++;
86a74ff2 1430 if (desc_status & RD_RFS4)
bb7d92e3 1431 ndev->stats.rx_length_errors++;
86a74ff2 1432 if (desc_status & RD_RFS6)
bb7d92e3 1433 ndev->stats.rx_missed_errors++;
86a74ff2 1434 if (desc_status & RD_RFS10)
bb7d92e3 1435 ndev->stats.rx_over_errors++;
248be83d 1436 } else if (skb) {
7cf72477 1437 dma_addr = le32_to_cpu(rxdesc->addr);
380af9e3
YS		 1438 if (!mdp->cd->hw_swap)
1439 sh_eth_soft_swap(
1299653a 1440 phys_to_virt(ALIGN(dma_addr, 4)),
380af9e3 1441 pkt_len + 2);
86a74ff2 1442 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1443 if (mdp->cd->rpadir)
1444 skb_reserve(skb, NET_IP_ALIGN);
1299653a 1445 dma_unmap_single(&ndev->dev, dma_addr,
ab857916 1446 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1447 DMA_FROM_DEVICE);
86a74ff2
NI		 1448 skb_put(skb, pkt_len);
1449 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1450 netif_receive_skb(skb);
bb7d92e3
ED		 1451 ndev->stats.rx_packets++;
1452 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1453 if (desc_status & RD_RFS8)
1454 ndev->stats.multicast++;
86a74ff2 1455 }
525b8075 1456 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1457 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1458 }
1459
1460 /* Refill the Rx ring buffers. */
1461 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1462 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1463 rxdesc = &mdp->rx_ring[entry];
ab857916 1464 /* The size of the buffer is 32 byte boundary. */
5cbf20c7 1465 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1466 rxdesc->len = cpu_to_le32(buf_len << 16);
b0ca2a21 1467
86a74ff2 1468 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1469 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1470 if (skb == NULL)
1471 break; /* Better luck next round. */
380af9e3 1472 sh_eth_set_receive_align(skb);
52b9fa36 1473 dma_addr = dma_map_single(&ndev->dev, skb->data,
5cbf20c7 1474 buf_len, DMA_FROM_DEVICE);
52b9fa36
BH		 1475 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1476 kfree_skb(skb);
1477 break;
1478 }
1479 mdp->rx_skbuff[entry] = skb;
380af9e3 1480
bc8acf2c 1481 skb_checksum_none_assert(skb);
7cf72477 1482 rxdesc->addr = cpu_to_le32(dma_addr);
86a74ff2 1483 }
f32bfb9a 1484 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1485 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1486 rxdesc->status |=
7cf72477 1487 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
86a74ff2 1488 else
7cf72477 1489 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2
NI		 1490 }
1491
1492 /* Restart Rx engine if stopped. */
1493 /* If we don't need to check status, don't. -KDU */
79fba9f5 1494 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1495 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1496 if (intr_status & EESR_RDE &&
1497 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1498 u32 count = (sh_eth_read(ndev, RDFAR) -
1499 sh_eth_read(ndev, RDLAR)) >> 4;
1500
1501 mdp->cur_rx = count;
1502 mdp->dirty_rx = count;
1503 }
4a55530f 1504 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1505 }
86a74ff2 1506
319cd520
MK		 1507 *quota -= limit - boguscnt - 1;
1508
4f809cea 1509 return *quota <= 0;
86a74ff2
NI		 1510}
1511
4a55530f 1512static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1513{
1514 /* disable tx and rx */
b2b14d2f 1515 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
dc19e4e5
NI		 1516}
1517
4a55530f 1518static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1519{
1520 /* enable tx and rx */
b2b14d2f 1521 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
dc19e4e5
NI		 1522}
1523
86a74ff2 1524/* error control function */
0799c2d6 1525static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1526{
1527 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1528 u32 felic_stat;
380af9e3
YS		 1529 u32 link_stat;
1530 u32 mask;
86a74ff2
NI		 1531
1532 if (intr_status & EESR_ECI) {
4a55530f
YS		 1533 felic_stat = sh_eth_read(ndev, ECSR);
1534 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1535 if (felic_stat & ECSR_ICD)
bb7d92e3 1536 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1537 if (felic_stat & ECSR_LCHNG) {
1538 /* Link Changed */
4923576b 1539 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1540 goto ignore_link;
380af9e3 1541 } else {
4a55530f 1542 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1543 if (mdp->ether_link_active_low)
1544 link_stat = ~link_stat;
380af9e3 1545 }
128296fc 1546 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1547 sh_eth_rcv_snd_disable(ndev);
128296fc 1548 } else {
86a74ff2 1549 /* Link Up */
b2b14d2f 1550 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
128296fc 1551 /* clear int */
b2b14d2f
SS		 1552 sh_eth_modify(ndev, ECSR, 0, 0);
1553 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1554 DMAC_M_ECI);
86a74ff2 1555 /* enable tx and rx */
4a55530f 1556 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1557 }
1558 }
1559 }
1560
1e1b812b 1561ignore_link:
86a74ff2 1562 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1563 /* Unused write back interrupt */
1564 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1565 ndev->stats.tx_aborted_errors++;
8d5009f6 1566 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1567 }
86a74ff2
NI		 1568 }
1569
1570 if (intr_status & EESR_RABT) {
1571 /* Receive Abort int */
1572 if (intr_status & EESR_RFRMER) {
1573 /* Receive Frame Overflow int */
bb7d92e3 1574 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1575 }
1576 }
380af9e3 1577
dc19e4e5
NI		 1578 if (intr_status & EESR_TDE) {
1579 /* Transmit Descriptor Empty int */
bb7d92e3 1580 ndev->stats.tx_fifo_errors++;
8d5009f6 1581 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1582 }
1583
1584 if (intr_status & EESR_TFE) {
1585 /* FIFO under flow */
bb7d92e3 1586 ndev->stats.tx_fifo_errors++;
8d5009f6 1587 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1588 }
1589
1590 if (intr_status & EESR_RDE) {
1591 /* Receive Descriptor Empty int */
bb7d92e3 1592 ndev->stats.rx_over_errors++;
86a74ff2 1593 }
dc19e4e5 1594
86a74ff2
NI		 1595 if (intr_status & EESR_RFE) {
1596 /* Receive FIFO Overflow int */
bb7d92e3 1597 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1598 }
1599
1600 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1601 /* Address Error */
bb7d92e3 1602 ndev->stats.tx_fifo_errors++;
8d5009f6 1603 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1604 }
380af9e3
YS		 1605
1606 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1607 if (mdp->cd->no_ade)
1608 mask &= ~EESR_ADE;
1609 if (intr_status & mask) {
86a74ff2 1610 /* Tx error */
4a55530f 1611 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1612
86a74ff2 1613 /* dmesg */
da246855
SS		 1614 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1615 intr_status, mdp->cur_tx, mdp->dirty_tx,
1616 (u32)ndev->state, edtrr);
86a74ff2
NI		 1617 /* dirty buffer free */
1618 sh_eth_txfree(ndev);
1619
1620 /* SH7712 BUG */
c5ed5368 1621 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1622 /* tx dma start */
c5ed5368 1623 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1624 }
1625 /* wakeup */
1626 netif_wake_queue(ndev);
1627 }
1628}
1629
1630static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1631{
1632 struct net_device *ndev = netdev;
1633 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1634 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1635 irqreturn_t ret = IRQ_NONE;
0799c2d6 1636 u32 intr_status, intr_enable;
86a74ff2 1637
86a74ff2
NI		 1638 spin_lock(&mdp->lock);
1639
3893b273 1640 /* Get interrupt status */
4a55530f 1641 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1642 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1643 * enabled since it's the one that comes thru regardless of the mask,
1644 * and we need to fully handle it in sh_eth_error() in order to quench
1645 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1646 */
3719109d
SS		 1647 intr_enable = sh_eth_read(ndev, EESIPR);
1648 intr_status &= intr_enable | DMAC_M_ECI;
1649 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1650 ret = IRQ_HANDLED;
3719109d 1651 else
283e38db
BH		 1652 goto out;
1653
1654 if (!likely(mdp->irq_enabled)) {
1655 sh_eth_write(ndev, 0, EESIPR);
1656 goto out;
1657 }
86a74ff2 1658
3719109d
SS		 1659 if (intr_status & EESR_RX_CHECK) {
1660 if (napi_schedule_prep(&mdp->napi)) {
1661 /* Mask Rx interrupts */
1662 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1663 EESIPR);
1664 __napi_schedule(&mdp->napi);
1665 } else {
da246855 1666 netdev_warn(ndev,
0799c2d6 1667 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1668 intr_status, intr_enable);
3719109d
SS		 1669 }
1670 }
86a74ff2 1671
b0ca2a21 1672 /* Tx Check */
380af9e3 1673 if (intr_status & cd->tx_check) {
3719109d
SS		 1674 /* Clear Tx interrupts */
1675 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1676
86a74ff2
NI		 1677 sh_eth_txfree(ndev);
1678 netif_wake_queue(ndev);
1679 }
1680
3719109d
SS		 1681 if (intr_status & cd->eesr_err_check) {
1682 /* Clear error interrupts */
1683 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1684
86a74ff2 1685 sh_eth_error(ndev, intr_status);
3719109d 1686 }
86a74ff2 1687
283e38db 1688out:
86a74ff2
NI		 1689 spin_unlock(&mdp->lock);
1690
0e0fde3c 1691 return ret;
86a74ff2
NI		 1692}
1693
3719109d
SS		 1694static int sh_eth_poll(struct napi_struct *napi, int budget)
1695{
1696 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1697 napi);
1698 struct net_device *ndev = napi->dev;
1699 int quota = budget;
0799c2d6 1700 u32 intr_status;
3719109d
SS		 1701
1702 for (;;) {
1703 intr_status = sh_eth_read(ndev, EESR);
1704 if (!(intr_status & EESR_RX_CHECK))
1705 break;
1706 /* Clear Rx interrupts */
1707 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1708
1709 if (sh_eth_rx(ndev, intr_status, &quota))
1710 goto out;
1711 }
1712
1713 napi_complete(napi);
1714
1715 /* Reenable Rx interrupts */
283e38db
BH		 1716 if (mdp->irq_enabled)
1717 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1718out:
1719 return budget - quota;
1720}
1721
86a74ff2
NI		 1722/* PHY state control function */
1723static void sh_eth_adjust_link(struct net_device *ndev)
1724{
1725 struct sh_eth_private *mdp = netdev_priv(ndev);
1726 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1727 int new_state = 0;
1728
3340d2aa 1729 if (phydev->link) {
86a74ff2
NI		 1730 if (phydev->duplex != mdp->duplex) {
1731 new_state = 1;
1732 mdp->duplex = phydev->duplex;
380af9e3
YS		 1733 if (mdp->cd->set_duplex)
1734 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1735 }
1736
1737 if (phydev->speed != mdp->speed) {
1738 new_state = 1;
1739 mdp->speed = phydev->speed;
380af9e3
YS		 1740 if (mdp->cd->set_rate)
1741 mdp->cd->set_rate(ndev);
86a74ff2 1742 }
3340d2aa 1743 if (!mdp->link) {
b2b14d2f 1744 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
86a74ff2
NI		 1745 new_state = 1;
1746 mdp->link = phydev->link;
1e1b812b
SS		 1747 if (mdp->cd->no_psr || mdp->no_ether_link)
1748 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1749 }
1750 } else if (mdp->link) {
1751 new_state = 1;
3340d2aa 1752 mdp->link = 0;
86a74ff2
NI		 1753 mdp->speed = 0;
1754 mdp->duplex = -1;
1e1b812b
SS		 1755 if (mdp->cd->no_psr || mdp->no_ether_link)
1756 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1757 }
1758
dc19e4e5 1759 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1760 phy_print_status(phydev);
1761}
1762
1763/* PHY init function */
1764static int sh_eth_phy_init(struct net_device *ndev)
1765{
702eca02 1766 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1767 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1768 struct phy_device *phydev;
86a74ff2 1769
3340d2aa 1770 mdp->link = 0;
86a74ff2
NI		 1771 mdp->speed = 0;
1772 mdp->duplex = -1;
1773
1774 /* Try connect to PHY */
702eca02
BD		 1775 if (np) {
1776 struct device_node *pn;
1777
1778 pn = of_parse_phandle(np, "phy-handle", 0);
1779 phydev = of_phy_connect(ndev, pn,
1780 sh_eth_adjust_link, 0,
1781 mdp->phy_interface);
1782
1783 if (!phydev)
1784 phydev = ERR_PTR(-ENOENT);
1785 } else {
1786 char phy_id[MII_BUS_ID_SIZE + 3];
1787
1788 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1789 mdp->mii_bus->id, mdp->phy_id);
1790
1791 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1792 mdp->phy_interface);
1793 }
1794
86a74ff2 1795 if (IS_ERR(phydev)) {
da246855 1796 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1797 return PTR_ERR(phydev);
1798 }
380af9e3 1799
2220943a 1800 phy_attached_info(phydev);
86a74ff2
NI		 1801
1802 mdp->phydev = phydev;
1803
1804 return 0;
1805}
1806
1807/* PHY control start function */
1808static int sh_eth_phy_start(struct net_device *ndev)
1809{
1810 struct sh_eth_private *mdp = netdev_priv(ndev);
1811 int ret;
1812
1813 ret = sh_eth_phy_init(ndev);
1814 if (ret)
1815 return ret;
1816
86a74ff2
NI		 1817 phy_start(mdp->phydev);
1818
1819 return 0;
1820}
1821
dc19e4e5 1822static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1823 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1824{
1825 struct sh_eth_private *mdp = netdev_priv(ndev);
1826 unsigned long flags;
1827 int ret;
1828
4f9dce23
BH		 1829 if (!mdp->phydev)
1830 return -ENODEV;
1831
dc19e4e5
NI		 1832 spin_lock_irqsave(&mdp->lock, flags);
1833 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1834 spin_unlock_irqrestore(&mdp->lock, flags);
1835
1836 return ret;
1837}
1838
1839static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1840 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1841{
1842 struct sh_eth_private *mdp = netdev_priv(ndev);
1843 unsigned long flags;
1844 int ret;
dc19e4e5 1845
4f9dce23
BH		 1846 if (!mdp->phydev)
1847 return -ENODEV;
1848
dc19e4e5
NI		 1849 spin_lock_irqsave(&mdp->lock, flags);
1850
1851 /* disable tx and rx */
4a55530f 1852 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1853
1854 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1855 if (ret)
1856 goto error_exit;
1857
1858 if (ecmd->duplex == DUPLEX_FULL)
1859 mdp->duplex = 1;
1860 else
1861 mdp->duplex = 0;
1862
1863 if (mdp->cd->set_duplex)
1864 mdp->cd->set_duplex(ndev);
1865
1866error_exit:
1867 mdelay(1);
1868
1869 /* enable tx and rx */
4a55530f 1870 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1871
1872 spin_unlock_irqrestore(&mdp->lock, flags);
1873
1874 return ret;
1875}
1876
6b4b4fea
BH		 1877/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1878 * version must be bumped as well. Just adding registers up to that
1879 * limit is fine, as long as the existing register indices don't
1880 * change.
1881 */
1882#define SH_ETH_REG_DUMP_VERSION 1
1883#define SH_ETH_REG_DUMP_MAX_REGS 256
1884
1885static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1886{
1887 struct sh_eth_private *mdp = netdev_priv(ndev);
1888 struct sh_eth_cpu_data *cd = mdp->cd;
1889 u32 *valid_map;
1890 size_t len;
1891
1892 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1893
1894 /* Dump starts with a bitmap that tells ethtool which
1895 * registers are defined for this chip.
1896 */
1897 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1898 if (buf) {
1899 valid_map = buf;
1900 buf += len;
1901 } else {
1902 valid_map = NULL;
1903 }
1904
1905 /* Add a register to the dump, if it has a defined offset.
1906 * This automatically skips most undefined registers, but for
1907 * some it is also necessary to check a capability flag in
1908 * struct sh_eth_cpu_data.
1909 */
1910#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1911#define add_reg_from(reg, read_expr) do { \
1912 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1913 if (buf) { \
1914 mark_reg_valid(reg); \
1915 *buf++ = read_expr; \
1916 } \
1917 ++len; \
1918 } \
1919 } while (0)
1920#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1921#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1922
1923 add_reg(EDSR);
1924 add_reg(EDMR);
1925 add_reg(EDTRR);
1926 add_reg(EDRRR);
1927 add_reg(EESR);
1928 add_reg(EESIPR);
1929 add_reg(TDLAR);
1930 add_reg(TDFAR);
1931 add_reg(TDFXR);
1932 add_reg(TDFFR);
1933 add_reg(RDLAR);
1934 add_reg(RDFAR);
1935 add_reg(RDFXR);
1936 add_reg(RDFFR);
1937 add_reg(TRSCER);
1938 add_reg(RMFCR);
1939 add_reg(TFTR);
1940 add_reg(FDR);
1941 add_reg(RMCR);
1942 add_reg(TFUCR);
1943 add_reg(RFOCR);
1944 if (cd->rmiimode)
1945 add_reg(RMIIMODE);
1946 add_reg(FCFTR);
1947 if (cd->rpadir)
1948 add_reg(RPADIR);
1949 if (!cd->no_trimd)
1950 add_reg(TRIMD);
1951 add_reg(ECMR);
1952 add_reg(ECSR);
1953 add_reg(ECSIPR);
1954 add_reg(PIR);
1955 if (!cd->no_psr)
1956 add_reg(PSR);
1957 add_reg(RDMLR);
1958 add_reg(RFLR);
1959 add_reg(IPGR);
1960 if (cd->apr)
1961 add_reg(APR);
1962 if (cd->mpr)
1963 add_reg(MPR);
1964 add_reg(RFCR);
1965 add_reg(RFCF);
1966 if (cd->tpauser)
1967 add_reg(TPAUSER);
1968 add_reg(TPAUSECR);
1969 add_reg(GECMR);
1970 if (cd->bculr)
1971 add_reg(BCULR);
1972 add_reg(MAHR);
1973 add_reg(MALR);
1974 add_reg(TROCR);
1975 add_reg(CDCR);
1976 add_reg(LCCR);
1977 add_reg(CNDCR);
1978 add_reg(CEFCR);
1979 add_reg(FRECR);
1980 add_reg(TSFRCR);
1981 add_reg(TLFRCR);
1982 add_reg(CERCR);
1983 add_reg(CEECR);
1984 add_reg(MAFCR);
1985 if (cd->rtrate)
1986 add_reg(RTRATE);
1987 if (cd->hw_crc)
1988 add_reg(CSMR);
1989 if (cd->select_mii)
1990 add_reg(RMII_MII);
1991 add_reg(ARSTR);
1992 if (cd->tsu) {
1993 add_tsu_reg(TSU_CTRST);
1994 add_tsu_reg(TSU_FWEN0);
1995 add_tsu_reg(TSU_FWEN1);
1996 add_tsu_reg(TSU_FCM);
1997 add_tsu_reg(TSU_BSYSL0);
1998 add_tsu_reg(TSU_BSYSL1);
1999 add_tsu_reg(TSU_PRISL0);
2000 add_tsu_reg(TSU_PRISL1);
2001 add_tsu_reg(TSU_FWSL0);
2002 add_tsu_reg(TSU_FWSL1);
2003 add_tsu_reg(TSU_FWSLC);
2004 add_tsu_reg(TSU_QTAG0);
2005 add_tsu_reg(TSU_QTAG1);
2006 add_tsu_reg(TSU_QTAGM0);
2007 add_tsu_reg(TSU_QTAGM1);
2008 add_tsu_reg(TSU_FWSR);
2009 add_tsu_reg(TSU_FWINMK);
2010 add_tsu_reg(TSU_ADQT0);
2011 add_tsu_reg(TSU_ADQT1);
2012 add_tsu_reg(TSU_VTAG0);
2013 add_tsu_reg(TSU_VTAG1);
2014 add_tsu_reg(TSU_ADSBSY);
2015 add_tsu_reg(TSU_TEN);
2016 add_tsu_reg(TSU_POST1);
2017 add_tsu_reg(TSU_POST2);
2018 add_tsu_reg(TSU_POST3);
2019 add_tsu_reg(TSU_POST4);
2020 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2021 /* This is the start of a table, not just a single
2022 * register.
2023 */
2024 if (buf) {
2025 unsigned int i;
2026
2027 mark_reg_valid(TSU_ADRH0);
2028 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2029 *buf++ = ioread32(
2030 mdp->tsu_addr +
2031 mdp->reg_offset[TSU_ADRH0] +
2032 i * 4);
2033 }
2034 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2035 }
2036 }
2037
2038#undef mark_reg_valid
2039#undef add_reg_from
2040#undef add_reg
2041#undef add_tsu_reg
2042
2043 return len * 4;
2044}
2045
2046static int sh_eth_get_regs_len(struct net_device *ndev)
2047{
2048 return __sh_eth_get_regs(ndev, NULL);
2049}
2050
2051static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2052 void *buf)
2053{
2054 struct sh_eth_private *mdp = netdev_priv(ndev);
2055
2056 regs->version = SH_ETH_REG_DUMP_VERSION;
2057
2058 pm_runtime_get_sync(&mdp->pdev->dev);
2059 __sh_eth_get_regs(ndev, buf);
2060 pm_runtime_put_sync(&mdp->pdev->dev);
2061}
2062
dc19e4e5
NI		 2063static int sh_eth_nway_reset(struct net_device *ndev)
2064{
2065 struct sh_eth_private *mdp = netdev_priv(ndev);
2066 unsigned long flags;
2067 int ret;
2068
4f9dce23
BH		 2069 if (!mdp->phydev)
2070 return -ENODEV;
2071
dc19e4e5
NI		 2072 spin_lock_irqsave(&mdp->lock, flags);
2073 ret = phy_start_aneg(mdp->phydev);
2074 spin_unlock_irqrestore(&mdp->lock, flags);
2075
2076 return ret;
2077}
2078
2079static u32 sh_eth_get_msglevel(struct net_device *ndev)
2080{
2081 struct sh_eth_private *mdp = netdev_priv(ndev);
2082 return mdp->msg_enable;
2083}
2084
2085static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2086{
2087 struct sh_eth_private *mdp = netdev_priv(ndev);
2088 mdp->msg_enable = value;
2089}
2090
2091static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2092 "rx_current", "tx_current",
2093 "rx_dirty", "tx_dirty",
2094};
2095#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2096
2097static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2098{
2099 switch (sset) {
2100 case ETH_SS_STATS:
2101 return SH_ETH_STATS_LEN;
2102 default:
2103 return -EOPNOTSUPP;
2104 }
2105}
2106
2107static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2108 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2109{
2110 struct sh_eth_private *mdp = netdev_priv(ndev);
2111 int i = 0;
2112
2113 /* device-specific stats */
2114 data[i++] = mdp->cur_rx;
2115 data[i++] = mdp->cur_tx;
2116 data[i++] = mdp->dirty_rx;
2117 data[i++] = mdp->dirty_tx;
2118}
2119
2120static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2121{
2122 switch (stringset) {
2123 case ETH_SS_STATS:
2124 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2125 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2126 break;
2127 }
2128}
2129
525b8075
YS		 2130static void sh_eth_get_ringparam(struct net_device *ndev,
2131 struct ethtool_ringparam *ring)
2132{
2133 struct sh_eth_private *mdp = netdev_priv(ndev);
2134
2135 ring->rx_max_pending = RX_RING_MAX;
2136 ring->tx_max_pending = TX_RING_MAX;
2137 ring->rx_pending = mdp->num_rx_ring;
2138 ring->tx_pending = mdp->num_tx_ring;
2139}
2140
2141static int sh_eth_set_ringparam(struct net_device *ndev,
2142 struct ethtool_ringparam *ring)
2143{
2144 struct sh_eth_private *mdp = netdev_priv(ndev);
2145 int ret;
2146
2147 if (ring->tx_pending > TX_RING_MAX ||
2148 ring->rx_pending > RX_RING_MAX ||
2149 ring->tx_pending < TX_RING_MIN ||
2150 ring->rx_pending < RX_RING_MIN)
2151 return -EINVAL;
2152 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2153 return -EINVAL;
2154
2155 if (netif_running(ndev)) {
bd888916 2156 netif_device_detach(ndev);
525b8075 2157 netif_tx_disable(ndev);
283e38db
BH		 2158
2159 /* Serialise with the interrupt handler and NAPI, then
2160 * disable interrupts. We have to clear the
2161 * irq_enabled flag first to ensure that interrupts
2162 * won't be re-enabled.
2163 */
2164 mdp->irq_enabled = false;
525b8075 2165 synchronize_irq(ndev->irq);
283e38db 2166 napi_synchronize(&mdp->napi);
525b8075 2167 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2168
740c7f31 2169 sh_eth_dev_exit(ndev);
525b8075 2170
8e03a5e7 2171 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2172 sh_eth_ring_free(ndev);
084236d8 2173 }
525b8075
YS		 2174
2175 /* Set new parameters */
2176 mdp->num_rx_ring = ring->rx_pending;
2177 mdp->num_tx_ring = ring->tx_pending;
2178
525b8075 2179 if (netif_running(ndev)) {
084236d8
BH		 2180 ret = sh_eth_ring_init(ndev);
2181 if (ret < 0) {
2182 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2183 __func__);
2184 return ret;
2185 }
f7967210 2186 ret = sh_eth_dev_init(ndev);
084236d8
BH		 2187 if (ret < 0) {
2188 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2189 __func__);
2190 return ret;
2191 }
2192
bd888916 2193 netif_device_attach(ndev);
525b8075
YS		 2194 }
2195
2196 return 0;
2197}
2198
9b07be4b 2199static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2200 .get_settings = sh_eth_get_settings,
2201 .set_settings = sh_eth_set_settings,
6b4b4fea
BH		 2202 .get_regs_len = sh_eth_get_regs_len,
2203 .get_regs = sh_eth_get_regs,
9b07be4b 2204 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2205 .get_msglevel = sh_eth_get_msglevel,
2206 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2207 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2208 .get_strings = sh_eth_get_strings,
2209 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2210 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2211 .get_ringparam = sh_eth_get_ringparam,
2212 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2213};
2214
86a74ff2
NI		 2215/* network device open function */
2216static int sh_eth_open(struct net_device *ndev)
2217{
86a74ff2 2218 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 2219 int ret;
86a74ff2 2220
bcd5149d
MD		 2221 pm_runtime_get_sync(&mdp->pdev->dev);
2222
d2779e99
SS		 2223 napi_enable(&mdp->napi);
2224
a0607fd3 2225 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2226 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2227 if (ret) {
da246855 2228 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2229 goto out_napi_off;
86a74ff2
NI		 2230 }
2231
2232 /* Descriptor set */
2233 ret = sh_eth_ring_init(ndev);
2234 if (ret)
2235 goto out_free_irq;
2236
2237 /* device init */
f7967210 2238 ret = sh_eth_dev_init(ndev);
86a74ff2
NI		 2239 if (ret)
2240 goto out_free_irq;
2241
2242 /* PHY control start*/
2243 ret = sh_eth_phy_start(ndev);
2244 if (ret)
2245 goto out_free_irq;
2246
ad846aa5
SS		 2247 netif_start_queue(ndev);
2248
7fa2955f
MK		 2249 mdp->is_opened = 1;
2250
86a74ff2
NI		 2251 return ret;
2252
2253out_free_irq:
2254 free_irq(ndev->irq, ndev);
d2779e99
SS		 2255out_napi_off:
2256 napi_disable(&mdp->napi);
bcd5149d 2257 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2258 return ret;
2259}
2260
2261/* Timeout function */
2262static void sh_eth_tx_timeout(struct net_device *ndev)
2263{
2264 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2265 struct sh_eth_rxdesc *rxdesc;
2266 int i;
2267
2268 netif_stop_queue(ndev);
2269
8d5009f6
SS		 2270 netif_err(mdp, timer, ndev,
2271 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2272 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2273
2274 /* tx_errors count up */
bb7d92e3 2275 ndev->stats.tx_errors++;
86a74ff2 2276
86a74ff2 2277 /* Free all the skbuffs in the Rx queue. */
525b8075 2278 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2 2279 rxdesc = &mdp->rx_ring[i];
7cf72477
SS		 2280 rxdesc->status = cpu_to_le32(0);
2281 rxdesc->addr = cpu_to_le32(0xBADF00D0);
179d80af 2282 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2283 mdp->rx_skbuff[i] = NULL;
2284 }
525b8075 2285 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2286 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2287 mdp->tx_skbuff[i] = NULL;
2288 }
2289
2290 /* device init */
f7967210 2291 sh_eth_dev_init(ndev);
ad846aa5
SS		 2292
2293 netif_start_queue(ndev);
86a74ff2
NI		 2294}
2295
2296/* Packet transmit function */
2297static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2298{
2299 struct sh_eth_private *mdp = netdev_priv(ndev);
2300 struct sh_eth_txdesc *txdesc;
1299653a 2301 dma_addr_t dma_addr;
86a74ff2 2302 u32 entry;
fb5e2f9b 2303 unsigned long flags;
86a74ff2
NI		 2304
2305 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2306 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2307 if (!sh_eth_txfree(ndev)) {
8d5009f6 2308 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2309 netif_stop_queue(ndev);
2310 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2311 return NETDEV_TX_BUSY;
86a74ff2
NI		 2312 }
2313 }
2314 spin_unlock_irqrestore(&mdp->lock, flags);
2315
dacc73e0 2316 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2317 return NETDEV_TX_OK;
2318
525b8075 2319 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2320 mdp->tx_skbuff[entry] = skb;
2321 txdesc = &mdp->tx_ring[entry];
86a74ff2 2322 /* soft swap. */
380af9e3 2323 if (!mdp->cd->hw_swap)
3e230993 2324 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
1299653a
SS		 2325 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2326 DMA_TO_DEVICE);
2327 if (dma_mapping_error(&ndev->dev, dma_addr)) {
aa3933b8
BH		 2328 kfree_skb(skb);
2329 return NETDEV_TX_OK;
2330 }
7cf72477
SS		 2331 txdesc->addr = cpu_to_le32(dma_addr);
2332 txdesc->len = cpu_to_le32(skb->len << 16);
86a74ff2 2333
f32bfb9a 2334 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2335 if (entry >= mdp->num_tx_ring - 1)
7cf72477 2336 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
86a74ff2 2337 else
7cf72477 2338 txdesc->status |= cpu_to_le32(TD_TACT);
86a74ff2
NI		 2339
2340 mdp->cur_tx++;
2341
c5ed5368
YS		 2342 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2343 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2344
6ed10654 2345 return NETDEV_TX_OK;
86a74ff2
NI		 2346}
2347
4398f9c8
BH		 2348/* The statistics registers have write-clear behaviour, which means we
2349 * will lose any increment between the read and write. We mitigate
2350 * this by only clearing when we read a non-zero value, so we will
2351 * never falsely report a total of zero.
2352 */
2353static void
2354sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2355{
2356 u32 delta = sh_eth_read(ndev, reg);
2357
2358 if (delta) {
2359 *stat += delta;
2360 sh_eth_write(ndev, 0, reg);
2361 }
2362}
2363
7fa2955f
MK		 2364static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2365{
2366 struct sh_eth_private *mdp = netdev_priv(ndev);
2367
2368 if (sh_eth_is_rz_fast_ether(mdp))
2369 return &ndev->stats;
2370
2371 if (!mdp->is_opened)
2372 return &ndev->stats;
2373
4398f9c8
BH		 2374 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2375 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2376 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2377
2378 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2379 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2380 CERCR);
2381 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2382 CEECR);
7fa2955f 2383 } else {
4398f9c8
BH		 2384 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2385 CNDCR);
7fa2955f
MK		 2386 }
2387
2388 return &ndev->stats;
2389}
2390
86a74ff2
NI		 2391/* device close function */
2392static int sh_eth_close(struct net_device *ndev)
2393{
2394 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2395
2396 netif_stop_queue(ndev);
2397
283e38db
BH		 2398 /* Serialise with the interrupt handler and NAPI, then disable
2399 * interrupts. We have to clear the irq_enabled flag first to
2400 * ensure that interrupts won't be re-enabled.
2401 */
2402 mdp->irq_enabled = false;
2403 synchronize_irq(ndev->irq);
2404 napi_disable(&mdp->napi);
4a55530f 2405 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2406
740c7f31 2407 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2408
2409 /* PHY Disconnect */
2410 if (mdp->phydev) {
2411 phy_stop(mdp->phydev);
2412 phy_disconnect(mdp->phydev);
4f9dce23 2413 mdp->phydev = NULL;
86a74ff2
NI		 2414 }
2415
2416 free_irq(ndev->irq, ndev);
2417
8e03a5e7 2418 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2419 sh_eth_ring_free(ndev);
2420
bcd5149d
MD		 2421 pm_runtime_put_sync(&mdp->pdev->dev);
2422
7fa2955f 2423 mdp->is_opened = 0;
bcd5149d 2424
7fa2955f 2425 return 0;
86a74ff2
NI		 2426}
2427
bb7d92e3 2428/* ioctl to device function */
128296fc 2429static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2430{
2431 struct sh_eth_private *mdp = netdev_priv(ndev);
2432 struct phy_device *phydev = mdp->phydev;
2433
2434 if (!netif_running(ndev))
2435 return -EINVAL;
2436
2437 if (!phydev)
2438 return -ENODEV;
2439
28b04113 2440 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2441}
2442
6743fe6d
YS		 2443/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2444static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2445 int entry)
2446{
2447 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2448}
2449
2450static u32 sh_eth_tsu_get_post_mask(int entry)
2451{
2452 return 0x0f << (28 - ((entry % 8) * 4));
2453}
2454
2455static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2456{
2457 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2458}
2459
2460static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2461 int entry)
2462{
2463 struct sh_eth_private *mdp = netdev_priv(ndev);
2464 u32 tmp;
2465 void *reg_offset;
2466
2467 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2468 tmp = ioread32(reg_offset);
2469 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2470}
2471
2472static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2473 int entry)
2474{
2475 struct sh_eth_private *mdp = netdev_priv(ndev);
2476 u32 post_mask, ref_mask, tmp;
2477 void *reg_offset;
2478
2479 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2480 post_mask = sh_eth_tsu_get_post_mask(entry);
2481 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2482
2483 tmp = ioread32(reg_offset);
2484 iowrite32(tmp & ~post_mask, reg_offset);
2485
2486 /* If other port enables, the function returns "true" */
2487 return tmp & ref_mask;
2488}
2489
2490static int sh_eth_tsu_busy(struct net_device *ndev)
2491{
2492 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2493 struct sh_eth_private *mdp = netdev_priv(ndev);
2494
2495 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2496 udelay(10);
2497 timeout--;
2498 if (timeout <= 0) {
da246855 2499 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2500 return -ETIMEDOUT;
2501 }
2502 }
2503
2504 return 0;
2505}
2506
2507static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2508 const u8 *addr)
2509{
2510 u32 val;
2511
2512 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2513 iowrite32(val, reg);
2514 if (sh_eth_tsu_busy(ndev) < 0)
2515 return -EBUSY;
2516
2517 val = addr[4] << 8 | addr[5];
2518 iowrite32(val, reg + 4);
2519 if (sh_eth_tsu_busy(ndev) < 0)
2520 return -EBUSY;
2521
2522 return 0;
2523}
2524
2525static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2526{
2527 u32 val;
2528
2529 val = ioread32(reg);
2530 addr[0] = (val >> 24) & 0xff;
2531 addr[1] = (val >> 16) & 0xff;
2532 addr[2] = (val >> 8) & 0xff;
2533 addr[3] = val & 0xff;
2534 val = ioread32(reg + 4);
2535 addr[4] = (val >> 8) & 0xff;
2536 addr[5] = val & 0xff;
2537}
2538
2539
2540static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2541{
2542 struct sh_eth_private *mdp = netdev_priv(ndev);
2543 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2544 int i;
2545 u8 c_addr[ETH_ALEN];
2546
2547 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2548 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2549 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2550 return i;
2551 }
2552
2553 return -ENOENT;
2554}
2555
2556static int sh_eth_tsu_find_empty(struct net_device *ndev)
2557{
2558 u8 blank[ETH_ALEN];
2559 int entry;
2560
2561 memset(blank, 0, sizeof(blank));
2562 entry = sh_eth_tsu_find_entry(ndev, blank);
2563 return (entry < 0) ? -ENOMEM : entry;
2564}
2565
2566static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2567 int entry)
2568{
2569 struct sh_eth_private *mdp = netdev_priv(ndev);
2570 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2571 int ret;
2572 u8 blank[ETH_ALEN];
2573
2574 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2575 ~(1 << (31 - entry)), TSU_TEN);
2576
2577 memset(blank, 0, sizeof(blank));
2578 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2579 if (ret < 0)
2580 return ret;
2581 return 0;
2582}
2583
2584static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2585{
2586 struct sh_eth_private *mdp = netdev_priv(ndev);
2587 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2588 int i, ret;
2589
2590 if (!mdp->cd->tsu)
2591 return 0;
2592
2593 i = sh_eth_tsu_find_entry(ndev, addr);
2594 if (i < 0) {
2595 /* No entry found, create one */
2596 i = sh_eth_tsu_find_empty(ndev);
2597 if (i < 0)
2598 return -ENOMEM;
2599 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2600 if (ret < 0)
2601 return ret;
2602
2603 /* Enable the entry */
2604 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2605 (1 << (31 - i)), TSU_TEN);
2606 }
2607
2608 /* Entry found or created, enable POST */
2609 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2610
2611 return 0;
2612}
2613
2614static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2615{
2616 struct sh_eth_private *mdp = netdev_priv(ndev);
2617 int i, ret;
2618
2619 if (!mdp->cd->tsu)
2620 return 0;
2621
2622 i = sh_eth_tsu_find_entry(ndev, addr);
2623 if (i) {
2624 /* Entry found */
2625 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2626 goto done;
2627
2628 /* Disable the entry if both ports was disabled */
2629 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2630 if (ret < 0)
2631 return ret;
2632 }
2633done:
2634 return 0;
2635}
2636
2637static int sh_eth_tsu_purge_all(struct net_device *ndev)
2638{
2639 struct sh_eth_private *mdp = netdev_priv(ndev);
2640 int i, ret;
2641
b37feed7 2642 if (!mdp->cd->tsu)
6743fe6d
YS		 2643 return 0;
2644
2645 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2646 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2647 continue;
2648
2649 /* Disable the entry if both ports was disabled */
2650 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2651 if (ret < 0)
2652 return ret;
2653 }
2654
2655 return 0;
2656}
2657
2658static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2659{
2660 struct sh_eth_private *mdp = netdev_priv(ndev);
2661 u8 addr[ETH_ALEN];
2662 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2663 int i;
2664
b37feed7 2665 if (!mdp->cd->tsu)
6743fe6d
YS		 2666 return;
2667
2668 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2669 sh_eth_tsu_read_entry(reg_offset, addr);
2670 if (is_multicast_ether_addr(addr))
2671 sh_eth_tsu_del_entry(ndev, addr);
2672 }
2673}
2674
b37feed7
BH		 2675/* Update promiscuous flag and multicast filter */
2676static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2677{
6743fe6d
YS		 2678 struct sh_eth_private *mdp = netdev_priv(ndev);
2679 u32 ecmr_bits;
2680 int mcast_all = 0;
2681 unsigned long flags;
2682
2683 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2684 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2685 * Depending on ndev->flags, set PRM or clear MCT
2686 */
b37feed7
BH		 2687 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2688 if (mdp->cd->tsu)
2689 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2690
2691 if (!(ndev->flags & IFF_MULTICAST)) {
2692 sh_eth_tsu_purge_mcast(ndev);
2693 mcast_all = 1;
2694 }
2695 if (ndev->flags & IFF_ALLMULTI) {
2696 sh_eth_tsu_purge_mcast(ndev);
2697 ecmr_bits &= ~ECMR_MCT;
2698 mcast_all = 1;
2699 }
2700
86a74ff2 2701 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2702 sh_eth_tsu_purge_all(ndev);
2703 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2704 } else if (mdp->cd->tsu) {
2705 struct netdev_hw_addr *ha;
2706 netdev_for_each_mc_addr(ha, ndev) {
2707 if (mcast_all && is_multicast_ether_addr(ha->addr))
2708 continue;
2709
2710 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2711 if (!mcast_all) {
2712 sh_eth_tsu_purge_mcast(ndev);
2713 ecmr_bits &= ~ECMR_MCT;
2714 mcast_all = 1;
2715 }
2716 }
2717 }
86a74ff2 2718 }
6743fe6d
YS		 2719
2720 /* update the ethernet mode */
2721 sh_eth_write(ndev, ecmr_bits, ECMR);
2722
2723 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2724}
71cc7c37
YS		 2725
2726static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2727{
2728 if (!mdp->port)
2729 return TSU_VTAG0;
2730 else
2731 return TSU_VTAG1;
2732}
2733
80d5c368
PM		 2734static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2735 __be16 proto, u16 vid)
71cc7c37
YS		 2736{
2737 struct sh_eth_private *mdp = netdev_priv(ndev);
2738 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2739
2740 if (unlikely(!mdp->cd->tsu))
2741 return -EPERM;
2742
2743 /* No filtering if vid = 0 */
2744 if (!vid)
2745 return 0;
2746
2747 mdp->vlan_num_ids++;
2748
128296fc 2749 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2750 * already enabled, the driver disables it and the filte
2751 */
2752 if (mdp->vlan_num_ids > 1) {
2753 /* disable VLAN filter */
2754 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2755 return 0;
2756 }
2757
2758 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2759 vtag_reg_index);
2760
2761 return 0;
2762}
2763
80d5c368
PM		 2764static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2765 __be16 proto, u16 vid)
71cc7c37
YS		 2766{
2767 struct sh_eth_private *mdp = netdev_priv(ndev);
2768 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2769
2770 if (unlikely(!mdp->cd->tsu))
2771 return -EPERM;
2772
2773 /* No filtering if vid = 0 */
2774 if (!vid)
2775 return 0;
2776
2777 mdp->vlan_num_ids--;
2778 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2779
2780 return 0;
2781}
86a74ff2
NI		 2782
2783/* SuperH's TSU register init function */
4a55530f 2784static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2785{
db893473
SH		 2786 if (sh_eth_is_rz_fast_ether(mdp)) {
2787 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2788 return;
2789 }
2790
4a55530f
YS		 2791 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2792 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2793 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2794 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2795 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2796 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2797 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2798 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2799 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2800 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2801 if (sh_eth_is_gether(mdp)) {
2802 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2803 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2804 } else {
2805 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2806 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2807 }
4a55530f
YS		 2808 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2809 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2810 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2811 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2812 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2813 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2814 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2815}
2816
2817/* MDIO bus release function */
bd920ff5 2818static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2819{
86a74ff2 2820 /* unregister mdio bus */
bd920ff5 2821 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2822
2823 /* free bitbang info */
bd920ff5 2824 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2825
2826 return 0;
2827}
2828
2829/* MDIO bus init function */
bd920ff5 2830static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2831 struct sh_eth_plat_data *pd)
86a74ff2 2832{
e7f4dc35 2833 int ret;
86a74ff2 2834 struct bb_info *bitbang;
bd920ff5 2835 struct platform_device *pdev = mdp->pdev;
aa8d4225 2836 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2837
2838 /* create bit control struct for PHY */
aa8d4225 2839 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2840 if (!bitbang)
2841 return -ENOMEM;
86a74ff2
NI		 2842
2843 /* bitbang init */
ae70644d 2844 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2845 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 2846 bitbang->ctrl.ops = &bb_ops;
2847
c2e07b3a 2848 /* MII controller setting */
86a74ff2 2849 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2850 if (!mdp->mii_bus)
2851 return -ENOMEM;
86a74ff2
NI		 2852
2853 /* Hook up MII support for ethtool */
2854 mdp->mii_bus->name = "sh_mii";
a5bd6060 2855 mdp->mii_bus->parent = dev;
5278fb54 2856 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2857 pdev->name, pdev->id);
86a74ff2 2858
bd920ff5
LP		 2859 /* register MDIO bus */
2860 if (dev->of_node) {
2861 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02 2862 } else {
702eca02
BD		 2863 if (pd->phy_irq > 0)
2864 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2865
2866 ret = mdiobus_register(mdp->mii_bus);
2867 }
2868
86a74ff2 2869 if (ret)
d5e07e69 2870 goto out_free_bus;
86a74ff2 2871
86a74ff2
NI		 2872 return 0;
2873
86a74ff2 2874out_free_bus:
298cf9be 2875 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2876 return ret;
2877}
2878
4a55530f
YS		 2879static const u16 *sh_eth_get_register_offset(int register_type)
2880{
2881 const u16 *reg_offset = NULL;
2882
2883 switch (register_type) {
2884 case SH_ETH_REG_GIGABIT:
2885 reg_offset = sh_eth_offset_gigabit;
2886 break;
db893473
SH		 2887 case SH_ETH_REG_FAST_RZ:
2888 reg_offset = sh_eth_offset_fast_rz;
2889 break;
a3f109bd
SS		 2890 case SH_ETH_REG_FAST_RCAR:
2891 reg_offset = sh_eth_offset_fast_rcar;
2892 break;
4a55530f
YS		 2893 case SH_ETH_REG_FAST_SH4:
2894 reg_offset = sh_eth_offset_fast_sh4;
2895 break;
2896 case SH_ETH_REG_FAST_SH3_SH2:
2897 reg_offset = sh_eth_offset_fast_sh3_sh2;
2898 break;
4a55530f
YS		 2899 }
2900
2901 return reg_offset;
2902}
2903
8f728d79 2904static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2905 .ndo_open = sh_eth_open,
2906 .ndo_stop = sh_eth_close,
2907 .ndo_start_xmit = sh_eth_start_xmit,
2908 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2909 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2910 .ndo_tx_timeout = sh_eth_tx_timeout,
2911 .ndo_do_ioctl = sh_eth_do_ioctl,
2912 .ndo_validate_addr = eth_validate_addr,
2913 .ndo_set_mac_address = eth_mac_addr,
2914 .ndo_change_mtu = eth_change_mtu,
2915};
2916
8f728d79
SS		 2917static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2918 .ndo_open = sh_eth_open,
2919 .ndo_stop = sh_eth_close,
2920 .ndo_start_xmit = sh_eth_start_xmit,
2921 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2922 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2923 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2924 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2925 .ndo_tx_timeout = sh_eth_tx_timeout,
2926 .ndo_do_ioctl = sh_eth_do_ioctl,
2927 .ndo_validate_addr = eth_validate_addr,
2928 .ndo_set_mac_address = eth_mac_addr,
2929 .ndo_change_mtu = eth_change_mtu,
2930};
2931
b356e978
SS		 2932#ifdef CONFIG_OF
2933static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2934{
2935 struct device_node *np = dev->of_node;
2936 struct sh_eth_plat_data *pdata;
b356e978
SS		 2937 const char *mac_addr;
2938
2939 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2940 if (!pdata)
2941 return NULL;
2942
2943 pdata->phy_interface = of_get_phy_mode(np);
2944
b356e978
SS		 2945 mac_addr = of_get_mac_address(np);
2946 if (mac_addr)
2947 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2948
2949 pdata->no_ether_link =
2950 of_property_read_bool(np, "renesas,no-ether-link");
2951 pdata->ether_link_active_low =
2952 of_property_read_bool(np, "renesas,ether-link-active-low");
2953
2954 return pdata;
2955}
2956
2957static const struct of_device_id sh_eth_match_table[] = {
2958 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2959 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2960 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2961 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2962 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 2963 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 2964 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 2965 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2966 { }
2967};
2968MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2969#else
2970static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2971{
2972 return NULL;
2973}
2974#endif
2975
86a74ff2
NI		 2976static int sh_eth_drv_probe(struct platform_device *pdev)
2977{
86a74ff2 2978 struct resource *res;
0b76b862 2979 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2980 const struct platform_device_id *id = platform_get_device_id(pdev);
4fa8c3cc
SS		 2981 struct sh_eth_private *mdp;
2982 struct net_device *ndev;
2983 int ret, devno;
86a74ff2
NI		 2984
2985 /* get base addr */
2986 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 2987
2988 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 2989 if (!ndev)
2990 return -ENOMEM;
86a74ff2 2991
b5893a08
BD		 2992 pm_runtime_enable(&pdev->dev);
2993 pm_runtime_get_sync(&pdev->dev);
2994
86a74ff2
NI		 2995 devno = pdev->id;
2996 if (devno < 0)
2997 devno = 0;
2998
2999 ndev->dma = -1;
cc3c080d 3000 ret = platform_get_irq(pdev, 0);
7a468ac6 3001 if (ret < 0)
86a74ff2 3002 goto out_release;
cc3c080d 3003 ndev->irq = ret;
86a74ff2
NI		 3004
3005 SET_NETDEV_DEV(ndev, &pdev->dev);
3006
86a74ff2 3007 mdp = netdev_priv(ndev);
525b8075
YS		 3008 mdp->num_tx_ring = TX_RING_SIZE;
3009 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3010 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3011 if (IS_ERR(mdp->addr)) {
3012 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3013 goto out_release;
3014 }
3015
c960804f
VB		 3016 ndev->base_addr = res->start;
3017
86a74ff2 3018 spin_lock_init(&mdp->lock);
bcd5149d 3019 mdp->pdev = pdev;
86a74ff2 3020
b356e978
SS		 3021 if (pdev->dev.of_node)
3022 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3023 if (!pd) {
3024 dev_err(&pdev->dev, "no platform data\n");
3025 ret = -EINVAL;
3026 goto out_release;
3027 }
3028
86a74ff2 3029 /* get PHY ID */
71557a37 3030 mdp->phy_id = pd->phy;
e47c9052 3031 mdp->phy_interface = pd->phy_interface;
4923576b
YS		 3032 mdp->no_ether_link = pd->no_ether_link;
3033 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3034
380af9e3 3035 /* set cpu data */
42a67c9b 3036 if (id)
b356e978 3037 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
42a67c9b
WS		 3038 else
3039 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
b356e978 3040
a3153d8c 3041 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3042 if (!mdp->reg_offset) {
3043 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3044 mdp->cd->register_type);
3045 ret = -EINVAL;
3046 goto out_release;
3047 }
380af9e3
YS		 3048 sh_eth_set_default_cpu_data(mdp->cd);
3049
86a74ff2 3050 /* set function */
8f728d79
SS		 3051 if (mdp->cd->tsu)
3052 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3053 else
3054 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3055 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3056 ndev->watchdog_timeo = TX_TIMEOUT;
3057
dc19e4e5
NI		 3058 /* debug message level */
3059 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3060
3061 /* read and set MAC address */
748031f9 3062 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3063 if (!is_valid_ether_addr(ndev->dev_addr)) {
3064 dev_warn(&pdev->dev,
3065 "no valid MAC address supplied, using a random one.\n");
3066 eth_hw_addr_random(ndev);
3067 }
86a74ff2 3068
6ba88021
YS		 3069 /* ioremap the TSU registers */
3070 if (mdp->cd->tsu) {
3071 struct resource *rtsu;
3072 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3073 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3074 if (IS_ERR(mdp->tsu_addr)) {
3075 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3076 goto out_release;
3077 }
6743fe6d 3078 mdp->port = devno % 2;
f646968f 3079 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3080 }
3081
150647fb
YS		 3082 /* initialize first or needed device */
3083 if (!devno || pd->needs_init) {
380af9e3
YS		 3084 if (mdp->cd->chip_reset)
3085 mdp->cd->chip_reset(ndev);
86a74ff2 3086
4986b996
YS		 3087 if (mdp->cd->tsu) {
3088 /* TSU init (Init only)*/
3089 sh_eth_tsu_init(mdp);
3090 }
86a74ff2
NI		 3091 }
3092
966d6dbb
HN		 3093 if (mdp->cd->rmiimode)
3094 sh_eth_write(ndev, 0x1, RMIIMODE);
3095
daacf03f
LP		 3096 /* MDIO bus init */
3097 ret = sh_mdio_init(mdp, pd);
3098 if (ret) {
3099 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3100 goto out_release;
3101 }
3102
3719109d
SS		 3103 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3104
86a74ff2
NI		 3105 /* network device register */
3106 ret = register_netdev(ndev);
3107 if (ret)
3719109d 3108 goto out_napi_del;
86a74ff2 3109
25985edc 3110 /* print device information */
f75f14ec
SS		 3111 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3112 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3113
b5893a08 3114 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3115 platform_set_drvdata(pdev, ndev);
3116
3117 return ret;
3118
3719109d
SS		 3119out_napi_del:
3120 netif_napi_del(&mdp->napi);
daacf03f 3121 sh_mdio_release(mdp);
3719109d 3122
86a74ff2
NI		 3123out_release:
3124 /* net_dev free */
3125 if (ndev)
3126 free_netdev(ndev);
3127
b5893a08
BD		 3128 pm_runtime_put(&pdev->dev);
3129 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3130 return ret;
3131}
3132
3133static int sh_eth_drv_remove(struct platform_device *pdev)
3134{
3135 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3136 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3137
86a74ff2 3138 unregister_netdev(ndev);
3719109d 3139 netif_napi_del(&mdp->napi);
daacf03f 3140 sh_mdio_release(mdp);
bcd5149d 3141 pm_runtime_disable(&pdev->dev);
86a74ff2 3142 free_netdev(ndev);
86a74ff2
NI		 3143
3144 return 0;
3145}
3146
540ad1b8 3147#ifdef CONFIG_PM
b71af046
MU		 3148#ifdef CONFIG_PM_SLEEP
3149static int sh_eth_suspend(struct device *dev)
3150{
3151 struct net_device *ndev = dev_get_drvdata(dev);
3152 int ret = 0;
3153
3154 if (netif_running(ndev)) {
3155 netif_device_detach(ndev);
3156 ret = sh_eth_close(ndev);
3157 }
3158
3159 return ret;
3160}
3161
3162static int sh_eth_resume(struct device *dev)
3163{
3164 struct net_device *ndev = dev_get_drvdata(dev);
3165 int ret = 0;
3166
3167 if (netif_running(ndev)) {
3168 ret = sh_eth_open(ndev);
3169 if (ret < 0)
3170 return ret;
3171 netif_device_attach(ndev);
3172 }
3173
3174 return ret;
3175}
3176#endif
3177
bcd5149d
MD		 3178static int sh_eth_runtime_nop(struct device *dev)
3179{
128296fc 3180 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3181 * and ->runtime_resume(). Simply returns success.
3182 *
3183 * This driver re-initializes all registers after
3184 * pm_runtime_get_sync() anyway so there is no need
3185 * to save and restore registers here.
3186 */
3187 return 0;
3188}
3189
540ad1b8 3190static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3191 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3192 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3193};
540ad1b8
NI		 3194#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3195#else
3196#define SH_ETH_PM_OPS NULL
3197#endif
bcd5149d 3198
afe391ad 3199static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3200 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3201 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3202 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3203 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3204 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3205 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3206 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3207 { }
3208};
3209MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3210
86a74ff2
NI		 3211static struct platform_driver sh_eth_driver = {
3212 .probe = sh_eth_drv_probe,
3213 .remove = sh_eth_drv_remove,
afe391ad 3214 .id_table = sh_eth_id_table,
86a74ff2
NI		 3215 .driver = {
3216 .name = CARDNAME,
540ad1b8 3217 .pm = SH_ETH_PM_OPS,
b356e978 3218 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3219 },
3220};
3221
db62f684 3222module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3223
3224MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3225MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3226MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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