[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.h

/*
 *  SuperH Ethernet device driver
 *
 *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
 *  Copyright (C) 2008-2012 Renesas Solutions Corp.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms and conditions of the GNU General Public License,
 *  version 2, as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *  You should have received a copy of the GNU General Public License along with
 *  this program; if not, write to the Free Software Foundation, Inc.,
 *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 *  The full GNU General Public License is included in this distribution in
 *  the file called "COPYING".
 */

#ifndef __SH_ETH_H__
#define __SH_ETH_H__

#define CARDNAME	"sh-eth"
#define TX_TIMEOUT	(5*HZ)
#define TX_RING_SIZE	64	/* Tx ring size */
#define RX_RING_SIZE	64	/* Rx ring size */
#define TX_RING_MIN	64
#define RX_RING_MIN	64
#define TX_RING_MAX	1024
#define RX_RING_MAX	1024
#define ETHERSMALL		60
#define PKT_BUF_SZ		1538
#define SH_ETH_TSU_TIMEOUT_MS	500
#define SH_ETH_TSU_CAM_ENTRIES	32

enum {
	/* E-DMAC registers */
	EDSR = 0,
	EDMR,
	EDTRR,
	EDRRR,
	EESR,
	EESIPR,
	TDLAR,
	TDFAR,
	TDFXR,
	TDFFR,
	RDLAR,
	RDFAR,
	RDFXR,
	RDFFR,
	TRSCER,
	RMFCR,
	TFTR,
	FDR,
	RMCR,
	EDOCR,
	TFUCR,
	RFOCR,
	FCFTR,
	RPADIR,
	TRIMD,
	RBWAR,
	TBRAR,

	/* Ether registers */
	ECMR,
	ECSR,
	ECSIPR,
	PIR,
	PSR,
	RDMLR,
	PIPR,
	RFLR,
	IPGR,
	APR,
	MPR,
	PFTCR,
	PFRCR,
	RFCR,
	RFCF,
	TPAUSER,
	TPAUSECR,
	BCFR,
	BCFRR,
	GECMR,
	BCULR,
	MAHR,
	MALR,
	TROCR,
	CDCR,
	LCCR,
	CNDCR,
	CEFCR,
	FRECR,
	TSFRCR,
	TLFRCR,
	CERCR,
	CEECR,
	MAFCR,
	RTRATE,
	CSMR,
	RMII_MII,

	/* TSU Absolute address */
	ARSTR,
	TSU_CTRST,
	TSU_FWEN0,
	TSU_FWEN1,
	TSU_FCM,
	TSU_BSYSL0,
	TSU_BSYSL1,
	TSU_PRISL0,
	TSU_PRISL1,
	TSU_FWSL0,
	TSU_FWSL1,
	TSU_FWSLC,
	TSU_QTAG0,
	TSU_QTAG1,
	TSU_QTAGM0,
	TSU_QTAGM1,
	TSU_FWSR,
	TSU_FWINMK,
	TSU_ADQT0,
	TSU_ADQT1,
	TSU_VTAG0,
	TSU_VTAG1,
	TSU_ADSBSY,
	TSU_TEN,
	TSU_POST1,
	TSU_POST2,
	TSU_POST3,
	TSU_POST4,
	TSU_ADRH0,
	TSU_ADRL0,
	TSU_ADRH31,
	TSU_ADRL31,

	TXNLCR0,
	TXALCR0,
	RXNLCR0,
	RXALCR0,
	FWNLCR0,
	FWALCR0,
	TXNLCR1,
	TXALCR1,
	RXNLCR1,
	RXALCR1,
	FWNLCR1,
	FWALCR1,

	/* This value must be written at last. */
	SH_ETH_MAX_REGISTER_OFFSET,
};

/* Driver's parameters */
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
#define SH4_SKB_RX_ALIGN	32
#else
#define SH2_SH3_SKB_RX_ALIGN	2
#endif

/*
 * Register's bits
 */
#if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\
    defined(CONFIG_ARCH_R8A7740)
/* EDSR */
enum EDSR_BIT {
	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
};
#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)

/* GECMR */
enum GECMR_BIT {
	GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
};
#endif

/* EDMR */
enum DMAC_M_BIT {
	EDMR_EL = 0x40, /* Litte endian */
	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
	EDMR_SRST_GETHER = 0x03,
	EDMR_SRST_ETHER = 0x01,
};

/* EDTRR */
enum DMAC_T_BIT {
	EDTRR_TRNS_GETHER = 0x03,
	EDTRR_TRNS_ETHER = 0x01,
};

/* EDRRR*/
enum EDRRR_R_BIT {
	EDRRR_R = 0x01,
};

/* TPAUSER */
enum TPAUSER_BIT {
	TPAUSER_TPAUSE = 0x0000ffff,
	TPAUSER_UNLIMITED = 0,
};

/* BCFR */
enum BCFR_BIT {
	BCFR_RPAUSE = 0x0000ffff,
	BCFR_UNLIMITED = 0,
};

/* PIR */
enum PIR_BIT {
	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
};

/* PSR */
enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };

/* EESR */
enum EESR_BIT {
	EESR_TWB1	= 0x80000000,
	EESR_TWB	= 0x40000000,	/* same as TWB0 */
	EESR_TC1	= 0x20000000,
	EESR_TUC	= 0x10000000,
	EESR_ROC	= 0x08000000,
	EESR_TABT	= 0x04000000,
	EESR_RABT	= 0x02000000,
	EESR_RFRMER	= 0x01000000,	/* same as RFCOF */
	EESR_ADE	= 0x00800000,
	EESR_ECI	= 0x00400000,
	EESR_FTC	= 0x00200000,	/* same as TC or TC0 */
	EESR_TDE	= 0x00100000,
	EESR_TFE	= 0x00080000,	/* same as TFUF */
	EESR_FRC	= 0x00040000,	/* same as FR */
	EESR_RDE	= 0x00020000,
	EESR_RFE	= 0x00010000,
	EESR_CND	= 0x00000800,
	EESR_DLC	= 0x00000400,
	EESR_CD		= 0x00000200,
	EESR_RTO	= 0x00000100,
	EESR_RMAF	= 0x00000080,
	EESR_CEEF	= 0x00000040,
	EESR_CELF	= 0x00000020,
	EESR_RRF	= 0x00000010,
	EESR_RTLF	= 0x00000008,
	EESR_RTSF	= 0x00000004,
	EESR_PRE	= 0x00000002,
	EESR_CERF	= 0x00000001,
};

#define DEFAULT_TX_CHECK	(EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
				 EESR_RTO)
#define DEFAULT_EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | \
				 EESR_RDE | EESR_RFRMER | EESR_ADE | \
				 EESR_TFE | EESR_TDE | EESR_ECI)
#define DEFAULT_TX_ERROR_CHECK	(EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
				 EESR_TFE)

/* EESIPR */
enum DMAC_IM_BIT {
	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
	DMAC_M_RABT = 0x02000000,
	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
	DMAC_M_RINT1 = 0x00000001,
};

/* Receive descriptor bit */
enum RD_STS_BIT {
	RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
	RD_RFS1 = 0x00000001,
};
#define RDF1ST	RD_RFP1
#define RDFEND	RD_RFP0
#define RD_RFP	(RD_RFP1|RD_RFP0)

/* FCFTR */
enum FCFTR_BIT {
	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
};
#define DEFAULT_FIFO_F_D_RFF	(FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
#define DEFAULT_FIFO_F_D_RFD	(FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)

/* Transfer descriptor bit */
enum TD_STS_BIT {
	TD_TACT = 0x80000000,
	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
	TD_TFP0 = 0x10000000,
};
#define TDF1ST	TD_TFP1
#define TDFEND	TD_TFP0
#define TD_TFP	(TD_TFP1|TD_TFP0)

/* RMCR */
#define DEFAULT_RMCR_VALUE	0x00000000

/* ECMR */
enum FELIC_MODE_BIT {
	ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
	ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
	ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
	ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
};

/* ECSR */
enum ECSR_STATUS_BIT {
	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
	ECSR_LCHNG = 0x04,
	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
};

#define DEFAULT_ECSR_INIT	(ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
				 ECSR_ICD | ECSIPR_MPDIP)

/* ECSIPR */
enum ECSIPR_STATUS_MASK_BIT {
	ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
	ECSIPR_LCHNGIP = 0x04,
	ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
};

#define DEFAULT_ECSIPR_INIT	(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
				 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)

/* APR */
enum APR_BIT {
	APR_AP = 0x00000001,
};

/* MPR */
enum MPR_BIT {
	MPR_MP = 0x00000001,
};

/* TRSCER */
enum DESC_I_BIT {
	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
	DESC_I_RINT1 = 0x0001,
};

/* RPADIR */
enum RPADIR_BIT {
	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
	RPADIR_PADR = 0x0003f,
};

/* FDR */
#define DEFAULT_FDR_INIT	0x00000707

/* ARSTR */
enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };

/* TSU_FWEN0 */
enum TSU_FWEN0_BIT {
	TSU_FWEN0_0 = 0x00000001,
};

/* TSU_ADSBSY */
enum TSU_ADSBSY_BIT {
	TSU_ADSBSY_0 = 0x00000001,
};

/* TSU_TEN */
enum TSU_TEN_BIT {
	TSU_TEN_0 = 0x80000000,
};

/* TSU_FWSL0 */
enum TSU_FWSL0_BIT {
	TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
	TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
	TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
};

/* TSU_FWSLC */
enum TSU_FWSLC_BIT {
	TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
	TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
	TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
	TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
	TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
};

/* TSU_VTAGn */
#define TSU_VTAG_ENABLE		0x80000000
#define TSU_VTAG_VID_MASK	0x00000fff

/*
 * The sh ether Tx buffer descriptors.
 * This structure should be 20 bytes.
 */
struct sh_eth_txdesc {
	u32 status;		/* TD0 */
#if defined(__LITTLE_ENDIAN)
	u16 pad0;		/* TD1 */
	u16 buffer_length;	/* TD1 */
#else
	u16 buffer_length;	/* TD1 */
	u16 pad0;		/* TD1 */
#endif
	u32 addr;		/* TD2 */
	u32 pad1;		/* padding data */
} __attribute__((aligned(2), packed));

/*
 * The sh ether Rx buffer descriptors.
 * This structure should be 20 bytes.
 */
struct sh_eth_rxdesc {
	u32 status;		/* RD0 */
#if defined(__LITTLE_ENDIAN)
	u16 frame_length;	/* RD1 */
	u16 buffer_length;	/* RD1 */
#else
	u16 buffer_length;	/* RD1 */
	u16 frame_length;	/* RD1 */
#endif
	u32 addr;		/* RD2 */
	u32 pad0;		/* padding data */
} __attribute__((aligned(2), packed));

/* This structure is used by each CPU dependency handling. */
struct sh_eth_cpu_data {
	/* optional functions */
	void (*chip_reset)(struct net_device *ndev);
	void (*set_duplex)(struct net_device *ndev);
	void (*set_rate)(struct net_device *ndev);

	/* mandatory initialize value */
	unsigned long eesipr_value;

	/* optional initialize value */
	unsigned long ecsr_value;
	unsigned long ecsipr_value;
	unsigned long fdr_value;
	unsigned long fcftr_value;
	unsigned long rpadir_value;
	unsigned long rmcr_value;

	/* interrupt checking mask */
	unsigned long tx_check;
	unsigned long eesr_err_check;
	unsigned long tx_error_check;

	/* hardware features */
	unsigned no_psr:1;		/* EtherC DO NOT have PSR */
	unsigned apr:1;			/* EtherC have APR */
	unsigned mpr:1;			/* EtherC have MPR */
	unsigned tpauser:1;		/* EtherC have TPAUSER */
	unsigned bculr:1;		/* EtherC have BCULR */
	unsigned tsu:1;			/* EtherC have TSU */
	unsigned hw_swap:1;		/* E-DMAC have DE bit in EDMR */
	unsigned rpadir:1;		/* E-DMAC have RPADIR */
	unsigned no_trimd:1;		/* E-DMAC DO NOT have TRIMD */
	unsigned no_ade:1;	/* E-DMAC DO NOT have ADE bit in EESR */
	unsigned hw_crc:1;	/* E-DMAC have CSMR */
	unsigned select_mii:1;	/* EtherC have RMII_MII (MII select register) */
};

struct sh_eth_private {
	struct platform_device *pdev;
	struct sh_eth_cpu_data *cd;
	const u16 *reg_offset;
	void __iomem *addr;
	void __iomem *tsu_addr;
	u32 num_rx_ring;
	u32 num_tx_ring;
	dma_addr_t rx_desc_dma;
	dma_addr_t tx_desc_dma;
	struct sh_eth_rxdesc *rx_ring;
	struct sh_eth_txdesc *tx_ring;
	struct sk_buff **rx_skbuff;
	struct sk_buff **tx_skbuff;
	spinlock_t lock;
	u32 cur_rx, dirty_rx;	/* Producer/consumer ring indices */
	u32 cur_tx, dirty_tx;
	u32 rx_buf_sz;		/* Based on MTU+slack. */
	int edmac_endian;
	/* MII transceiver section. */
	u32 phy_id;					/* PHY ID */
	struct mii_bus *mii_bus;	/* MDIO bus control */
	struct phy_device *phydev;	/* PHY device control */
	int link;
	phy_interface_t phy_interface;
	int msg_enable;
	int speed;
	int duplex;
	int port;		/* for TSU */
	int vlan_num_ids;	/* for VLAN tag filter */

	unsigned no_ether_link:1;
	unsigned ether_link_active_low:1;
};

static inline void sh_eth_soft_swap(char *src, int len)
{
#ifdef __LITTLE_ENDIAN__
	u32 *p = (u32 *)src;
	u32 *maxp;
	maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));

	for (; p < maxp; p++)
		*p = swab32(*p);
#endif
}

static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
				int enum_index)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
}

static inline unsigned long sh_eth_read(struct net_device *ndev,
					int enum_index)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
}

static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
					  int enum_index)
{
	return mdp->tsu_addr + mdp->reg_offset[enum_index];
}

static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
				unsigned long data, int enum_index)
{
	iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
}

static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
					int enum_index)
{
	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
}

#endif	/* #ifndef __SH_ETH_H__ */
Commit	Line	Data
86a74ff2 NI	1	/*
	2	* SuperH Ethernet device driver
	3	*
f0e81fec NI	4	* Copyright (C) 2006-2012 Nobuhiro Iwamatsu
f0e81fec NI	5	* Copyright (C) 2008-2012 Renesas Solutions Corp.
86a74ff2 NI	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program; if not, write to the Free Software Foundation, Inc.,
	17	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18	*
	19	* The full GNU General Public License is included in this distribution in
	20	* the file called "COPYING".
	21	*/
	22
	23	#ifndef __SH_ETH_H__
	24	#define __SH_ETH_H__
	25
86a74ff2 NI	26	#define CARDNAME "sh-eth"
86a74ff2 NI	27	#define TX_TIMEOUT (5*HZ)
b0ca2a21 NI	28	#define TX_RING_SIZE 64 /* Tx ring size */
b0ca2a21 NI	29	#define RX_RING_SIZE 64 /* Rx ring size */
525b8075 YS	30	#define TX_RING_MIN 64
	31	#define RX_RING_MIN 64
	32	#define TX_RING_MAX 1024
	33	#define RX_RING_MAX 1024
86a74ff2 NI	34	#define ETHERSMALL 60
86a74ff2 NI	35	#define PKT_BUF_SZ 1538
6743fe6d YS	36	#define SH_ETH_TSU_TIMEOUT_MS 500
6743fe6d YS	37	#define SH_ETH_TSU_CAM_ENTRIES 32
86a74ff2	38
4a55530f YS	39	enum {
	40	/* E-DMAC registers */
	41	EDSR = 0,
	42	EDMR,
	43	EDTRR,
	44	EDRRR,
	45	EESR,
	46	EESIPR,
	47	TDLAR,
	48	TDFAR,
	49	TDFXR,
	50	TDFFR,
	51	RDLAR,
	52	RDFAR,
	53	RDFXR,
	54	RDFFR,
	55	TRSCER,
	56	RMFCR,
	57	TFTR,
	58	FDR,
	59	RMCR,
	60	EDOCR,
	61	TFUCR,
	62	RFOCR,
	63	FCFTR,
	64	RPADIR,
	65	TRIMD,
	66	RBWAR,
	67	TBRAR,
	68
	69	/* Ether registers */
	70	ECMR,
	71	ECSR,
	72	ECSIPR,
	73	PIR,
	74	PSR,
	75	RDMLR,
	76	PIPR,
	77	RFLR,
	78	IPGR,
	79	APR,
	80	MPR,
	81	PFTCR,
	82	PFRCR,
	83	RFCR,
	84	RFCF,
	85	TPAUSER,
	86	TPAUSECR,
	87	BCFR,
	88	BCFRR,
	89	GECMR,
	90	BCULR,
	91	MAHR,
	92	MALR,
	93	TROCR,
	94	CDCR,
	95	LCCR,
	96	CNDCR,
	97	CEFCR,
	98	FRECR,
	99	TSFRCR,
	100	TLFRCR,
	101	CERCR,
	102	CEECR,
103	MAFCR,
104	RTRATE,
f0e81fec NI	105	CSMR,
f0e81fec NI	106	RMII_MII,
4a55530f YS	107
	108	/* TSU Absolute address */
	109	ARSTR,
	110	TSU_CTRST,
	111	TSU_FWEN0,
	112	TSU_FWEN1,
	113	TSU_FCM,
	114	TSU_BSYSL0,
	115	TSU_BSYSL1,
	116	TSU_PRISL0,
	117	TSU_PRISL1,
	118	TSU_FWSL0,
	119	TSU_FWSL1,
	120	TSU_FWSLC,
	121	TSU_QTAG0,
	122	TSU_QTAG1,
	123	TSU_QTAGM0,
	124	TSU_QTAGM1,
	125	TSU_FWSR,
	126	TSU_FWINMK,
	127	TSU_ADQT0,
	128	TSU_ADQT1,
	129	TSU_VTAG0,
	130	TSU_VTAG1,
	131	TSU_ADSBSY,
	132	TSU_TEN,
	133	TSU_POST1,
	134	TSU_POST2,
	135	TSU_POST3,
	136	TSU_POST4,
	137	TSU_ADRH0,
	138	TSU_ADRL0,
	139	TSU_ADRH31,
	140	TSU_ADRL31,
	141
	142	TXNLCR0,
	143	TXALCR0,
	144	RXNLCR0,
	145	RXALCR0,
	146	FWNLCR0,
	147	FWALCR0,
	148	TXNLCR1,
	149	TXALCR1,
	150	RXNLCR1,
	151	RXALCR1,
	152	FWNLCR1,
	153	FWALCR1,
	154
	155	/* This value must be written at last. */
	156	SH_ETH_MAX_REGISTER_OFFSET,
	157	};
	158
380af9e3	159	/* Driver's parameters */
73a0d907	160	#if defined(CONFIG_CPU_SH4) \|\| defined(CONFIG_ARCH_SHMOBILE)
380af9e3 YS	161	#define SH4_SKB_RX_ALIGN 32
	162	#else
	163	#define SH2_SH3_SKB_RX_ALIGN 2
	164	#endif
	165
b0ca2a21 NI	166	/*
	167	* Register's bits
	168	*/
73a0d907 YS	169	#if defined(CONFIG_CPU_SUBTYPE_SH7734) \|\| defined(CONFIG_CPU_SUBTYPE_SH7763) \|\|\
73a0d907 YS	170	defined(CONFIG_ARCH_R8A7740)
b0ca2a21 NI	171	/* EDSR */
	172	enum EDSR_BIT {
	173	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
	174	};
	175	#define EDSR_ENALL (EDSR_ENT\|EDSR_ENR)
	176
	177	/* GECMR */
	178	enum GECMR_BIT {
	179	GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
	180	};
	181	#endif
86a74ff2 NI	182
	183	/* EDMR */
	184	enum DMAC_M_BIT {
380af9e3	185	EDMR_EL = 0x40, /* Litte endian */
b0ca2a21	186	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
c5ed5368 YS	187	EDMR_SRST_GETHER = 0x03,
c5ed5368 YS	188	EDMR_SRST_ETHER = 0x01,
86a74ff2 NI	189	};
	190
	191	/* EDTRR */
	192	enum DMAC_T_BIT {
c5ed5368 YS	193	EDTRR_TRNS_GETHER = 0x03,
c5ed5368 YS	194	EDTRR_TRNS_ETHER = 0x01,
86a74ff2 NI	195	};
	196
	197	/* EDRRR*/
	198	enum EDRRR_R_BIT {
	199	EDRRR_R = 0x01,
	200	};
	201
	202	/* TPAUSER */
	203	enum TPAUSER_BIT {
	204	TPAUSER_TPAUSE = 0x0000ffff,
	205	TPAUSER_UNLIMITED = 0,
	206	};
	207
	208	/* BCFR */
	209	enum BCFR_BIT {
	210	BCFR_RPAUSE = 0x0000ffff,
	211	BCFR_UNLIMITED = 0,
	212	};
	213
	214	/* PIR */
	215	enum PIR_BIT {
	216	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
	217	};
	218
	219	/* PSR */
	220	enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
	221
	222	/* EESR */
	223	enum EESR_BIT {
380af9e3 YS	224	EESR_TWB1 = 0x80000000,
	225	EESR_TWB = 0x40000000, /* same as TWB0 */
	226	EESR_TC1 = 0x20000000,
	227	EESR_TUC = 0x10000000,
	228	EESR_ROC = 0x08000000,
	229	EESR_TABT = 0x04000000,
	230	EESR_RABT = 0x02000000,
	231	EESR_RFRMER = 0x01000000, /* same as RFCOF */
	232	EESR_ADE = 0x00800000,
	233	EESR_ECI = 0x00400000,
	234	EESR_FTC = 0x00200000, /* same as TC or TC0 */
	235	EESR_TDE = 0x00100000,
	236	EESR_TFE = 0x00080000, /* same as TFUF */
	237	EESR_FRC = 0x00040000, /* same as FR */
	238	EESR_RDE = 0x00020000,
	239	EESR_RFE = 0x00010000,
	240	EESR_CND = 0x00000800,
	241	EESR_DLC = 0x00000400,
	242	EESR_CD = 0x00000200,
	243	EESR_RTO = 0x00000100,
	244	EESR_RMAF = 0x00000080,
	245	EESR_CEEF = 0x00000040,
	246	EESR_CELF = 0x00000020,
	247	EESR_RRF = 0x00000010,
	248	EESR_RTLF = 0x00000008,
	249	EESR_RTSF = 0x00000004,
	250	EESR_PRE = 0x00000002,
	251	EESR_CERF = 0x00000001,
	252	};
	253
	254	#define DEFAULT_TX_CHECK (EESR_FTC \| EESR_CND \| EESR_DLC \| EESR_CD \| \
	255	EESR_RTO)
	256	#define DEFAULT_EESR_ERR_CHECK (EESR_TWB \| EESR_TABT \| EESR_RABT \| \
	257	EESR_RDE \| EESR_RFRMER \| EESR_ADE \| \
	258	EESR_TFE \| EESR_TDE \| EESR_ECI)
	259	#define DEFAULT_TX_ERROR_CHECK (EESR_TWB \| EESR_TABT \| EESR_ADE \| EESR_TDE \| \
	260	EESR_TFE)
86a74ff2 NI	261
	262	/* EESIPR */
	263	enum DMAC_IM_BIT {
	264	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
	265	DMAC_M_RABT = 0x02000000,
	266	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
	267	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
	268	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
	269	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
	270	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
	271	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
	272	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
	273	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
	274	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
	275	DMAC_M_RINT1 = 0x00000001,
	276	};
	277
	278	/* Receive descriptor bit */
	279	enum RD_STS_BIT {
b0ca2a21 NI	280	RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
b0ca2a21 NI	281	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
86a74ff2 NI	282	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
	283	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
	284	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
	285	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
	286	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
	287	RD_RFS1 = 0x00000001,
	288	};
b0ca2a21 NI	289	#define RDF1ST RD_RFP1
	290	#define RDFEND RD_RFP0
	291	#define RD_RFP (RD_RFP1\|RD_RFP0)
86a74ff2 NI	292
	293	/* FCFTR */
	294	enum FCFTR_BIT {
	295	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
	296	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
	297	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
	298	};
380af9e3 YS	299	#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 \| FCFTR_RFF1 \| FCFTR_RFF0)
380af9e3 YS	300	#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 \| FCFTR_RFD1 \| FCFTR_RFD0)
86a74ff2 NI	301
	302	/* Transfer descriptor bit */
	303	enum TD_STS_BIT {
b0ca2a21 NI	304	TD_TACT = 0x80000000,
b0ca2a21 NI	305	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
86a74ff2 NI	306	TD_TFP0 = 0x10000000,
	307	};
	308	#define TDF1ST TD_TFP1
	309	#define TDFEND TD_TFP0
	310	#define TD_TFP (TD_TFP1\|TD_TFP0)
	311
	312	/* RMCR */
380af9e3 YS	313	#define DEFAULT_RMCR_VALUE 0x00000000
380af9e3 YS	314
86a74ff2 NI	315	/* ECMR */
86a74ff2 NI	316	enum FELIC_MODE_BIT {
b0ca2a21 NI	317	ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
b0ca2a21 NI	318	ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
86a74ff2 NI	319	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
	320	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
	321	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
65ac8851	322	ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
380af9e3	323	ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
86a74ff2 NI	324	};
	325
	326	/* ECSR */
	327	enum ECSR_STATUS_BIT {
b0ca2a21	328	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
b0ca2a21	329	ECSR_LCHNG = 0x04,
86a74ff2 NI	330	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
	331	};
	332
380af9e3 YS	333	#define DEFAULT_ECSR_INIT (ECSR_BRCRX \| ECSR_PSRTO \| ECSR_LCHNG \| \
380af9e3 YS	334	ECSR_ICD \| ECSIPR_MPDIP)
b0ca2a21	335
86a74ff2 NI	336	/* ECSIPR */
86a74ff2 NI	337	enum ECSIPR_STATUS_MASK_BIT {
b0ca2a21	338	ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
b0ca2a21	339	ECSIPR_LCHNGIP = 0x04,
86a74ff2 NI	340	ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
	341	};
	342
380af9e3 YS	343	#define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP \| ECSIPR_PSRTOIP \| \
380af9e3 YS	344	ECSIPR_LCHNGIP \| ECSIPR_ICDIP \| ECSIPR_MPDIP)
b0ca2a21	345
86a74ff2 NI	346	/* APR */
	347	enum APR_BIT {
	348	APR_AP = 0x00000001,
	349	};
	350
	351	/* MPR */
	352	enum MPR_BIT {
	353	MPR_MP = 0x00000001,
	354	};
	355
	356	/* TRSCER */
	357	enum DESC_I_BIT {
	358	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
	359	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
	360	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
	361	DESC_I_RINT1 = 0x0001,
	362	};
	363
	364	/* RPADIR */
	365	enum RPADIR_BIT {
	366	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
	367	RPADIR_PADR = 0x0003f,
	368	};
	369
	370	/* FDR */
380af9e3 YS	371	#define DEFAULT_FDR_INIT 0x00000707
380af9e3 YS	372
86a74ff2 NI	373	/* ARSTR */
	374	enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
	375
	376	/* TSU_FWEN0 */
	377	enum TSU_FWEN0_BIT {
	378	TSU_FWEN0_0 = 0x00000001,
	379	};
	380
	381	/* TSU_ADSBSY */
	382	enum TSU_ADSBSY_BIT {
	383	TSU_ADSBSY_0 = 0x00000001,
	384	};
	385
	386	/* TSU_TEN */
	387	enum TSU_TEN_BIT {
	388	TSU_TEN_0 = 0x80000000,
	389	};
	390
	391	/* TSU_FWSL0 */
	392	enum TSU_FWSL0_BIT {
	393	TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
	394	TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
	395	TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
	396	};
	397
	398	/* TSU_FWSLC */
	399	enum TSU_FWSLC_BIT {
	400	TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
	401	TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
	402	TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
	403	TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
	404	TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
	405	};
	406
71cc7c37 YS	407	/* TSU_VTAGn */
	408	#define TSU_VTAG_ENABLE 0x80000000
	409	#define TSU_VTAG_VID_MASK 0x00000fff
	410
86a74ff2 NI	411	/*
	412	* The sh ether Tx buffer descriptors.
	413	* This structure should be 20 bytes.
	414	*/
	415	struct sh_eth_txdesc {
	416	u32 status; /* TD0 */
10b9194f	417	#if defined(__LITTLE_ENDIAN)
86a74ff2 NI	418	u16 pad0; /* TD1 */
	419	u16 buffer_length; /* TD1 */
	420	#else
	421	u16 buffer_length; /* TD1 */
	422	u16 pad0; /* TD1 */
	423	#endif
	424	u32 addr; /* TD2 */
	425	u32 pad1; /* padding data */
71557a37	426	} __attribute__((aligned(2), packed));
86a74ff2 NI	427
	428	/*
	429	* The sh ether Rx buffer descriptors.
	430	* This structure should be 20 bytes.
	431	*/
	432	struct sh_eth_rxdesc {
	433	u32 status; /* RD0 */
10b9194f	434	#if defined(__LITTLE_ENDIAN)
86a74ff2 NI	435	u16 frame_length; /* RD1 */
	436	u16 buffer_length; /* RD1 */
	437	#else
	438	u16 buffer_length; /* RD1 */
	439	u16 frame_length; /* RD1 */
	440	#endif
	441	u32 addr; /* RD2 */
	442	u32 pad0; /* padding data */
71557a37	443	} __attribute__((aligned(2), packed));
86a74ff2	444
380af9e3 YS	445	/* This structure is used by each CPU dependency handling. */
	446	struct sh_eth_cpu_data {
	447	/* optional functions */
	448	void (chip_reset)(struct net_device ndev);
	449	void (set_duplex)(struct net_device ndev);
	450	void (set_rate)(struct net_device ndev);
	451
	452	/* mandatory initialize value */
	453	unsigned long eesipr_value;
	454
	455	/* optional initialize value */
	456	unsigned long ecsr_value;
	457	unsigned long ecsipr_value;
	458	unsigned long fdr_value;
	459	unsigned long fcftr_value;
	460	unsigned long rpadir_value;
	461	unsigned long rmcr_value;
	462
	463	/* interrupt checking mask */
	464	unsigned long tx_check;
	465	unsigned long eesr_err_check;
	466	unsigned long tx_error_check;
	467
	468	/* hardware features */
	469	unsigned no_psr:1; /* EtherC DO NOT have PSR */
	470	unsigned apr:1; /* EtherC have APR */
	471	unsigned mpr:1; /* EtherC have MPR */
	472	unsigned tpauser:1; /* EtherC have TPAUSER */
	473	unsigned bculr:1; /* EtherC have BCULR */
4986b996	474	unsigned tsu:1; /* EtherC have TSU */
380af9e3 YS	475	unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
	476	unsigned rpadir:1; /* E-DMAC have RPADIR */
	477	unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
	478	unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
f0e81fec	479	unsigned hw_crc:1; /* E-DMAC have CSMR */
5e7a76be	480	unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */
380af9e3 YS	481	};
380af9e3 YS	482
86a74ff2	483	struct sh_eth_private {
bcd5149d	484	struct platform_device *pdev;
380af9e3	485	struct sh_eth_cpu_data *cd;
4a55530f	486	const u16 *reg_offset;
ae70644d	487	void __iomem *addr;
4a55530f	488	void __iomem *tsu_addr;
525b8075 YS	489	u32 num_rx_ring;
525b8075 YS	490	u32 num_tx_ring;
86a74ff2 NI	491	dma_addr_t rx_desc_dma;
	492	dma_addr_t tx_desc_dma;
	493	struct sh_eth_rxdesc *rx_ring;
	494	struct sh_eth_txdesc *tx_ring;
	495	struct sk_buff **rx_skbuff;
	496	struct sk_buff **tx_skbuff;
86a74ff2 NI	497	spinlock_t lock;
	498	u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
	499	u32 cur_tx, dirty_tx;
	500	u32 rx_buf_sz; /* Based on MTU+slack. */
71557a37	501	int edmac_endian;
86a74ff2 NI	502	/* MII transceiver section. */
	503	u32 phy_id; /* PHY ID */
	504	struct mii_bus mii_bus; / MDIO bus control */
	505	struct phy_device phydev; / PHY device control */
3340d2aa	506	int link;
e47c9052	507	phy_interface_t phy_interface;
86a74ff2 NI	508	int msg_enable;
	509	int speed;
	510	int duplex;
6743fe6d	511	int port; /* for TSU */
71cc7c37	512	int vlan_num_ids; /* for VLAN tag filter */
4923576b YS	513
	514	unsigned no_ether_link:1;
	515	unsigned ether_link_active_low:1;
86a74ff2 NI	516	};
86a74ff2 NI	517
380af9e3	518	static inline void sh_eth_soft_swap(char *src, int len)
86a74ff2 NI	519	{
	520	#ifdef __LITTLE_ENDIAN__
	521	u32 p = (u32 )src;
	522	u32 *maxp;
	523	maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
	524
	525	for (; p < maxp; p++)
	526	p = swab32(p);
	527	#endif
	528	}
380af9e3	529
4a55530f YS	530	static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
	531	int enum_index)
	532	{
	533	struct sh_eth_private *mdp = netdev_priv(ndev);
	534
ae70644d	535	iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
4a55530f YS	536	}
	537
	538	static inline unsigned long sh_eth_read(struct net_device *ndev,
	539	int enum_index)
	540	{
	541	struct sh_eth_private *mdp = netdev_priv(ndev);
	542
ae70644d	543	return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
4a55530f YS	544	}
4a55530f YS	545
6743fe6d YS	546	static inline void sh_eth_tsu_get_offset(struct sh_eth_private mdp,
	547	int enum_index)
	548	{
	549	return mdp->tsu_addr + mdp->reg_offset[enum_index];
	550	}
	551
4a55530f YS	552	static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
	553	unsigned long data, int enum_index)
	554	{
ae70644d	555	iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
4a55530f YS	556	}
	557
	558	static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
	559	int enum_index)
	560	{
ae70644d	561	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
4a55530f YS	562	}
4a55530f YS	563
380af9e3	564	#endif /* #ifndef __SH_ETH_H__ */