[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.h

/*
 *  SuperH Ethernet device driver
 *
 *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
 *  Copyright (C) 2008-2012 Renesas Solutions Corp.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms and conditions of the GNU General Public License,
 *  version 2, as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *  You should have received a copy of the GNU General Public License along with
 *  this program; if not, write to the Free Software Foundation, Inc.,
 *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 *  The full GNU General Public License is included in this distribution in
 *  the file called "COPYING".
 */

#ifndef __SH_ETH_H__
#define __SH_ETH_H__

#define CARDNAME	"sh-eth"
#define TX_TIMEOUT	(5*HZ)
#define TX_RING_SIZE	64	/* Tx ring size */
#define RX_RING_SIZE	64	/* Rx ring size */
#define ETHERSMALL		60
#define PKT_BUF_SZ		1538
#define SH_ETH_TSU_TIMEOUT_MS	500
#define SH_ETH_TSU_CAM_ENTRIES	32

enum {
	/* E-DMAC registers */
	EDSR = 0,
	EDMR,
	EDTRR,
	EDRRR,
	EESR,
	EESIPR,
	TDLAR,
	TDFAR,
	TDFXR,
	TDFFR,
	RDLAR,
	RDFAR,
	RDFXR,
	RDFFR,
	TRSCER,
	RMFCR,
	TFTR,
	FDR,
	RMCR,
	EDOCR,
	TFUCR,
	RFOCR,
	FCFTR,
	RPADIR,
	TRIMD,
	RBWAR,
	TBRAR,

	/* Ether registers */
	ECMR,
	ECSR,
	ECSIPR,
	PIR,
	PSR,
	RDMLR,
	PIPR,
	RFLR,
	IPGR,
	APR,
	MPR,
	PFTCR,
	PFRCR,
	RFCR,
	RFCF,
	TPAUSER,
	TPAUSECR,
	BCFR,
	BCFRR,
	GECMR,
	BCULR,
	MAHR,
	MALR,
	TROCR,
	CDCR,
	LCCR,
	CNDCR,
	CEFCR,
	FRECR,
	TSFRCR,
	TLFRCR,
	CERCR,
	CEECR,
	MAFCR,
	RTRATE,
	CSMR,
	RMII_MII,

	/* TSU Absolute address */
	ARSTR,
	TSU_CTRST,
	TSU_FWEN0,
	TSU_FWEN1,
	TSU_FCM,
	TSU_BSYSL0,
	TSU_BSYSL1,
	TSU_PRISL0,
	TSU_PRISL1,
	TSU_FWSL0,
	TSU_FWSL1,
	TSU_FWSLC,
	TSU_QTAG0,
	TSU_QTAG1,
	TSU_QTAGM0,
	TSU_QTAGM1,
	TSU_FWSR,
	TSU_FWINMK,
	TSU_ADQT0,
	TSU_ADQT1,
	TSU_VTAG0,
	TSU_VTAG1,
	TSU_ADSBSY,
	TSU_TEN,
	TSU_POST1,
	TSU_POST2,
	TSU_POST3,
	TSU_POST4,
	TSU_ADRH0,
	TSU_ADRL0,
	TSU_ADRH31,
	TSU_ADRL31,

	TXNLCR0,
	TXALCR0,
	RXNLCR0,
	RXALCR0,
	FWNLCR0,
	FWALCR0,
	TXNLCR1,
	TXALCR1,
	RXNLCR1,
	RXALCR1,
	FWNLCR1,
	FWALCR1,

	/* This value must be written at last. */
	SH_ETH_MAX_REGISTER_OFFSET,
};

static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
	[EDSR]	= 0x0000,
	[EDMR]	= 0x0400,
	[EDTRR]	= 0x0408,
	[EDRRR]	= 0x0410,
	[EESR]	= 0x0428,
	[EESIPR]	= 0x0430,
	[TDLAR]	= 0x0010,
	[TDFAR]	= 0x0014,
	[TDFXR]	= 0x0018,
	[TDFFR]	= 0x001c,
	[RDLAR]	= 0x0030,
	[RDFAR]	= 0x0034,
	[RDFXR]	= 0x0038,
	[RDFFR]	= 0x003c,
	[TRSCER]	= 0x0438,
	[RMFCR]	= 0x0440,
	[TFTR]	= 0x0448,
	[FDR]	= 0x0450,
	[RMCR]	= 0x0458,
	[RPADIR]	= 0x0460,
	[FCFTR]	= 0x0468,
	[CSMR] = 0x04E4,

	[ECMR]	= 0x0500,
	[ECSR]	= 0x0510,
	[ECSIPR]	= 0x0518,
	[PIR]	= 0x0520,
	[PSR]	= 0x0528,
	[PIPR]	= 0x052c,
	[RFLR]	= 0x0508,
	[APR]	= 0x0554,
	[MPR]	= 0x0558,
	[PFTCR]	= 0x055c,
	[PFRCR]	= 0x0560,
	[TPAUSER]	= 0x0564,
	[GECMR]	= 0x05b0,
	[BCULR]	= 0x05b4,
	[MAHR]	= 0x05c0,
	[MALR]	= 0x05c8,
	[TROCR]	= 0x0700,
	[CDCR]	= 0x0708,
	[LCCR]	= 0x0710,
	[CEFCR]	= 0x0740,
	[FRECR]	= 0x0748,
	[TSFRCR]	= 0x0750,
	[TLFRCR]	= 0x0758,
	[RFCR]	= 0x0760,
	[CERCR]	= 0x0768,
	[CEECR]	= 0x0770,
	[MAFCR]	= 0x0778,
	[RMII_MII] =  0x0790,

	[ARSTR]	= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_FWEN0]	= 0x0010,
	[TSU_FWEN1]	= 0x0014,
	[TSU_FCM]	= 0x0018,
	[TSU_BSYSL0]	= 0x0020,
	[TSU_BSYSL1]	= 0x0024,
	[TSU_PRISL0]	= 0x0028,
	[TSU_PRISL1]	= 0x002c,
	[TSU_FWSL0]	= 0x0030,
	[TSU_FWSL1]	= 0x0034,
	[TSU_FWSLC]	= 0x0038,
	[TSU_QTAG0]	= 0x0040,
	[TSU_QTAG1]	= 0x0044,
	[TSU_FWSR]	= 0x0050,
	[TSU_FWINMK]	= 0x0054,
	[TSU_ADQT0]	= 0x0048,
	[TSU_ADQT1]	= 0x004c,
	[TSU_VTAG0]	= 0x0058,
	[TSU_VTAG1]	= 0x005c,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,
	[TSU_ADRH0]	= 0x0100,
	[TSU_ADRL0]	= 0x0104,
	[TSU_ADRH31]	= 0x01f8,
	[TSU_ADRL31]	= 0x01fc,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008c,
	[FWNLCR0]	= 0x0090,
	[FWALCR0]	= 0x0094,
	[TXNLCR1]	= 0x00a0,
	[TXALCR1]	= 0x00a0,
	[RXNLCR1]	= 0x00a8,
	[RXALCR1]	= 0x00ac,
	[FWNLCR1]	= 0x00b0,
	[FWALCR1]	= 0x00b4,
};

static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]	= 0x0100,
	[RFLR]	= 0x0108,
	[ECSR]	= 0x0110,
	[ECSIPR]	= 0x0118,
	[PIR]	= 0x0120,
	[PSR]	= 0x0128,
	[RDMLR]	= 0x0140,
	[IPGR]	= 0x0150,
	[APR]	= 0x0154,
	[MPR]	= 0x0158,
	[TPAUSER]	= 0x0164,
	[RFCF]	= 0x0160,
	[TPAUSECR]	= 0x0168,
	[BCFRR]	= 0x016c,
	[MAHR]	= 0x01c0,
	[MALR]	= 0x01c8,
	[TROCR]	= 0x01d0,
	[CDCR]	= 0x01d4,
	[LCCR]	= 0x01d8,
	[CNDCR]	= 0x01dc,
	[CEFCR]	= 0x01e4,
	[FRECR]	= 0x01e8,
	[TSFRCR]	= 0x01ec,
	[TLFRCR]	= 0x01f0,
	[RFCR]	= 0x01f4,
	[MAFCR]	= 0x01f8,
	[RTRATE]	= 0x01fc,

	[EDMR]	= 0x0000,
	[EDTRR]	= 0x0008,
	[EDRRR]	= 0x0010,
	[TDLAR]	= 0x0018,
	[RDLAR]	= 0x0020,
	[EESR]	= 0x0028,
	[EESIPR]	= 0x0030,
	[TRSCER]	= 0x0038,
	[RMFCR]	= 0x0040,
	[TFTR]	= 0x0048,
	[FDR]	= 0x0050,
	[RMCR]	= 0x0058,
	[TFUCR]	= 0x0064,
	[RFOCR]	= 0x0068,
	[FCFTR]	= 0x0070,
	[RPADIR]	= 0x0078,
	[TRIMD]	= 0x007c,
	[RBWAR]	= 0x00c8,
	[RDFAR]	= 0x00cc,
	[TBRAR]	= 0x00d4,
	[TDFAR]	= 0x00d8,
};

static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]	= 0x0160,
	[ECSR]	= 0x0164,
	[ECSIPR]	= 0x0168,
	[PIR]	= 0x016c,
	[MAHR]	= 0x0170,
	[MALR]	= 0x0174,
	[RFLR]	= 0x0178,
	[PSR]	= 0x017c,
	[TROCR]	= 0x0180,
	[CDCR]	= 0x0184,
	[LCCR]	= 0x0188,
	[CNDCR]	= 0x018c,
	[CEFCR]	= 0x0194,
	[FRECR]	= 0x0198,
	[TSFRCR]	= 0x019c,
	[TLFRCR]	= 0x01a0,
	[RFCR]	= 0x01a4,
	[MAFCR]	= 0x01a8,
	[IPGR]	= 0x01b4,
	[APR]	= 0x01b8,
	[MPR]	= 0x01bc,
	[TPAUSER]	= 0x01c4,
	[BCFR]	= 0x01cc,

	[ARSTR]	= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_FWEN0]	= 0x0010,
	[TSU_FWEN1]	= 0x0014,
	[TSU_FCM]	= 0x0018,
	[TSU_BSYSL0]	= 0x0020,
	[TSU_BSYSL1]	= 0x0024,
	[TSU_PRISL0]	= 0x0028,
	[TSU_PRISL1]	= 0x002c,
	[TSU_FWSL0]	= 0x0030,
	[TSU_FWSL1]	= 0x0034,
	[TSU_FWSLC]	= 0x0038,
	[TSU_QTAGM0]	= 0x0040,
	[TSU_QTAGM1]	= 0x0044,
	[TSU_ADQT0]	= 0x0048,
	[TSU_ADQT1]	= 0x004c,
	[TSU_FWSR]	= 0x0050,
	[TSU_FWINMK]	= 0x0054,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008c,
	[FWNLCR0]	= 0x0090,
	[FWALCR0]	= 0x0094,
	[TXNLCR1]	= 0x00a0,
	[TXALCR1]	= 0x00a0,
	[RXNLCR1]	= 0x00a8,
	[RXALCR1]	= 0x00ac,
	[FWNLCR1]	= 0x00b0,
	[FWALCR1]	= 0x00b4,

	[TSU_ADRH0]	= 0x0100,
	[TSU_ADRL0]	= 0x0104,
	[TSU_ADRL31]	= 0x01fc,

};

/* Driver's parameters */
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
#define SH4_SKB_RX_ALIGN	32
#else
#define SH2_SH3_SKB_RX_ALIGN	2
#endif

/*
 * Register's bits
 */
#if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\
    defined(CONFIG_ARCH_R8A7740)
/* EDSR */
enum EDSR_BIT {
	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
};
#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)

/* GECMR */
enum GECMR_BIT {
	GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
};
#endif

/* EDMR */
enum DMAC_M_BIT {
	EDMR_EL = 0x40, /* Litte endian */
	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
	EDMR_SRST_GETHER = 0x03,
	EDMR_SRST_ETHER = 0x01,
};

/* EDTRR */
enum DMAC_T_BIT {
	EDTRR_TRNS_GETHER = 0x03,
	EDTRR_TRNS_ETHER = 0x01,
};

/* EDRRR*/
enum EDRRR_R_BIT {
	EDRRR_R = 0x01,
};

/* TPAUSER */
enum TPAUSER_BIT {
	TPAUSER_TPAUSE = 0x0000ffff,
	TPAUSER_UNLIMITED = 0,
};

/* BCFR */
enum BCFR_BIT {
	BCFR_RPAUSE = 0x0000ffff,
	BCFR_UNLIMITED = 0,
};

/* PIR */
enum PIR_BIT {
	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
};

/* PSR */
enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };

/* EESR */
enum EESR_BIT {
	EESR_TWB1	= 0x80000000,
	EESR_TWB	= 0x40000000,	/* same as TWB0 */
	EESR_TC1	= 0x20000000,
	EESR_TUC	= 0x10000000,
	EESR_ROC	= 0x08000000,
	EESR_TABT	= 0x04000000,
	EESR_RABT	= 0x02000000,
	EESR_RFRMER	= 0x01000000,	/* same as RFCOF */
	EESR_ADE	= 0x00800000,
	EESR_ECI	= 0x00400000,
	EESR_FTC	= 0x00200000,	/* same as TC or TC0 */
	EESR_TDE	= 0x00100000,
	EESR_TFE	= 0x00080000,	/* same as TFUF */
	EESR_FRC	= 0x00040000,	/* same as FR */
	EESR_RDE	= 0x00020000,
	EESR_RFE	= 0x00010000,
	EESR_CND	= 0x00000800,
	EESR_DLC	= 0x00000400,
	EESR_CD		= 0x00000200,
	EESR_RTO	= 0x00000100,
	EESR_RMAF	= 0x00000080,
	EESR_CEEF	= 0x00000040,
	EESR_CELF	= 0x00000020,
	EESR_RRF	= 0x00000010,
	EESR_RTLF	= 0x00000008,
	EESR_RTSF	= 0x00000004,
	EESR_PRE	= 0x00000002,
	EESR_CERF	= 0x00000001,
};

#define DEFAULT_TX_CHECK	(EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
				 EESR_RTO)
#define DEFAULT_EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | \
				 EESR_RDE | EESR_RFRMER | EESR_ADE | \
				 EESR_TFE | EESR_TDE | EESR_ECI)
#define DEFAULT_TX_ERROR_CHECK	(EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
				 EESR_TFE)

/* EESIPR */
enum DMAC_IM_BIT {
	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
	DMAC_M_RABT = 0x02000000,
	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
	DMAC_M_RINT1 = 0x00000001,
};

/* Receive descriptor bit */
enum RD_STS_BIT {
	RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
	RD_RFS1 = 0x00000001,
};
#define RDF1ST	RD_RFP1
#define RDFEND	RD_RFP0
#define RD_RFP	(RD_RFP1|RD_RFP0)

/* FCFTR */
enum FCFTR_BIT {
	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
};
#define DEFAULT_FIFO_F_D_RFF	(FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
#define DEFAULT_FIFO_F_D_RFD	(FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)

/* Transfer descriptor bit */
enum TD_STS_BIT {
	TD_TACT = 0x80000000,
	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
	TD_TFP0 = 0x10000000,
};
#define TDF1ST	TD_TFP1
#define TDFEND	TD_TFP0
#define TD_TFP	(TD_TFP1|TD_TFP0)

/* RMCR */
#define DEFAULT_RMCR_VALUE	0x00000000

/* ECMR */
enum FELIC_MODE_BIT {
	ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
	ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
	ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
	ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
};

/* ECSR */
enum ECSR_STATUS_BIT {
	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
	ECSR_LCHNG = 0x04,
	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
};

#define DEFAULT_ECSR_INIT	(ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
				 ECSR_ICD | ECSIPR_MPDIP)

/* ECSIPR */
enum ECSIPR_STATUS_MASK_BIT {
	ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
	ECSIPR_LCHNGIP = 0x04,
	ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
};

#define DEFAULT_ECSIPR_INIT	(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
				 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)

/* APR */
enum APR_BIT {
	APR_AP = 0x00000001,
};

/* MPR */
enum MPR_BIT {
	MPR_MP = 0x00000001,
};

/* TRSCER */
enum DESC_I_BIT {
	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
	DESC_I_RINT1 = 0x0001,
};

/* RPADIR */
enum RPADIR_BIT {
	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
	RPADIR_PADR = 0x0003f,
};

/* FDR */
#define DEFAULT_FDR_INIT	0x00000707

/* ARSTR */
enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };

/* TSU_FWEN0 */
enum TSU_FWEN0_BIT {
	TSU_FWEN0_0 = 0x00000001,
};

/* TSU_ADSBSY */
enum TSU_ADSBSY_BIT {
	TSU_ADSBSY_0 = 0x00000001,
};

/* TSU_TEN */
enum TSU_TEN_BIT {
	TSU_TEN_0 = 0x80000000,
};

/* TSU_FWSL0 */
enum TSU_FWSL0_BIT {
	TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
	TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
	TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
};

/* TSU_FWSLC */
enum TSU_FWSLC_BIT {
	TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
	TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
	TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
	TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
	TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
};

/* TSU_VTAGn */
#define TSU_VTAG_ENABLE		0x80000000
#define TSU_VTAG_VID_MASK	0x00000fff

/*
 * The sh ether Tx buffer descriptors.
 * This structure should be 20 bytes.
 */
struct sh_eth_txdesc {
	u32 status;		/* TD0 */
#if defined(__LITTLE_ENDIAN)
	u16 pad0;		/* TD1 */
	u16 buffer_length;	/* TD1 */
#else
	u16 buffer_length;	/* TD1 */
	u16 pad0;		/* TD1 */
#endif
	u32 addr;		/* TD2 */
	u32 pad1;		/* padding data */
} __attribute__((aligned(2), packed));

/*
 * The sh ether Rx buffer descriptors.
 * This structure should be 20 bytes.
 */
struct sh_eth_rxdesc {
	u32 status;		/* RD0 */
#if defined(__LITTLE_ENDIAN)
	u16 frame_length;	/* RD1 */
	u16 buffer_length;	/* RD1 */
#else
	u16 buffer_length;	/* RD1 */
	u16 frame_length;	/* RD1 */
#endif
	u32 addr;		/* RD2 */
	u32 pad0;		/* padding data */
} __attribute__((aligned(2), packed));

/* This structure is used by each CPU dependency handling. */
struct sh_eth_cpu_data {
	/* optional functions */
	void (*chip_reset)(struct net_device *ndev);
	void (*set_duplex)(struct net_device *ndev);
	void (*set_rate)(struct net_device *ndev);

	/* mandatory initialize value */
	unsigned long eesipr_value;

	/* optional initialize value */
	unsigned long ecsr_value;
	unsigned long ecsipr_value;
	unsigned long fdr_value;
	unsigned long fcftr_value;
	unsigned long rpadir_value;
	unsigned long rmcr_value;

	/* interrupt checking mask */
	unsigned long tx_check;
	unsigned long eesr_err_check;
	unsigned long tx_error_check;

	/* hardware features */
	unsigned no_psr:1;		/* EtherC DO NOT have PSR */
	unsigned apr:1;			/* EtherC have APR */
	unsigned mpr:1;			/* EtherC have MPR */
	unsigned tpauser:1;		/* EtherC have TPAUSER */
	unsigned bculr:1;		/* EtherC have BCULR */
	unsigned tsu:1;			/* EtherC have TSU */
	unsigned hw_swap:1;		/* E-DMAC have DE bit in EDMR */
	unsigned rpadir:1;		/* E-DMAC have RPADIR */
	unsigned no_trimd:1;		/* E-DMAC DO NOT have TRIMD */
	unsigned no_ade:1;	/* E-DMAC DO NOT have ADE bit in EESR */
	unsigned hw_crc:1;	/* E-DMAC have CSMR */
	unsigned select_mii:1;	/* EtherC have RMII_MII (MII select register) */
};

struct sh_eth_private {
	struct platform_device *pdev;
	struct sh_eth_cpu_data *cd;
	const u16 *reg_offset;
	void __iomem *addr;
	void __iomem *tsu_addr;
	dma_addr_t rx_desc_dma;
	dma_addr_t tx_desc_dma;
	struct sh_eth_rxdesc *rx_ring;
	struct sh_eth_txdesc *tx_ring;
	struct sk_buff **rx_skbuff;
	struct sk_buff **tx_skbuff;
	spinlock_t lock;
	u32 cur_rx, dirty_rx;	/* Producer/consumer ring indices */
	u32 cur_tx, dirty_tx;
	u32 rx_buf_sz;		/* Based on MTU+slack. */
	int edmac_endian;
	/* MII transceiver section. */
	u32 phy_id;					/* PHY ID */
	struct mii_bus *mii_bus;	/* MDIO bus control */
	struct phy_device *phydev;	/* PHY device control */
	enum phy_state link;
	phy_interface_t phy_interface;
	int msg_enable;
	int speed;
	int duplex;
	int port;		/* for TSU */
	int vlan_num_ids;	/* for VLAN tag filter */

	unsigned no_ether_link:1;
	unsigned ether_link_active_low:1;
};

static inline void sh_eth_soft_swap(char *src, int len)
{
#ifdef __LITTLE_ENDIAN__
	u32 *p = (u32 *)src;
	u32 *maxp;
	maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));

	for (; p < maxp; p++)
		*p = swab32(*p);
#endif
}

static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
				int enum_index)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
}

static inline unsigned long sh_eth_read(struct net_device *ndev,
					int enum_index)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
}

static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
					  int enum_index)
{
	return mdp->tsu_addr + mdp->reg_offset[enum_index];
}

static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
				unsigned long data, int enum_index)
{
	iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
}

static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
					int enum_index)
{
	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
}

#endif	/* #ifndef __SH_ETH_H__ */
Commit	Line	Data
86a74ff2 NI	1	/*
	2	* SuperH Ethernet device driver
	3	*
f0e81fec NI	4	* Copyright (C) 2006-2012 Nobuhiro Iwamatsu
f0e81fec NI	5	* Copyright (C) 2008-2012 Renesas Solutions Corp.
86a74ff2 NI	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program; if not, write to the Free Software Foundation, Inc.,
	17	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18	*
	19	* The full GNU General Public License is included in this distribution in
	20	* the file called "COPYING".
	21	*/
	22
	23	#ifndef __SH_ETH_H__
	24	#define __SH_ETH_H__
	25
86a74ff2 NI	26	#define CARDNAME "sh-eth"
86a74ff2 NI	27	#define TX_TIMEOUT (5*HZ)
b0ca2a21 NI	28	#define TX_RING_SIZE 64 /* Tx ring size */
b0ca2a21 NI	29	#define RX_RING_SIZE 64 /* Rx ring size */
86a74ff2 NI	30	#define ETHERSMALL 60
86a74ff2 NI	31	#define PKT_BUF_SZ 1538
6743fe6d YS	32	#define SH_ETH_TSU_TIMEOUT_MS 500
6743fe6d YS	33	#define SH_ETH_TSU_CAM_ENTRIES 32
86a74ff2	34
4a55530f YS	35	enum {
	36	/* E-DMAC registers */
	37	EDSR = 0,
	38	EDMR,
	39	EDTRR,
	40	EDRRR,
	41	EESR,
	42	EESIPR,
	43	TDLAR,
	44	TDFAR,
	45	TDFXR,
	46	TDFFR,
	47	RDLAR,
	48	RDFAR,
	49	RDFXR,
	50	RDFFR,
	51	TRSCER,
	52	RMFCR,
	53	TFTR,
	54	FDR,
	55	RMCR,
	56	EDOCR,
	57	TFUCR,
	58	RFOCR,
	59	FCFTR,
	60	RPADIR,
	61	TRIMD,
	62	RBWAR,
	63	TBRAR,
	64
	65	/* Ether registers */
	66	ECMR,
	67	ECSR,
	68	ECSIPR,
	69	PIR,
	70	PSR,
	71	RDMLR,
	72	PIPR,
	73	RFLR,
	74	IPGR,
	75	APR,
	76	MPR,
	77	PFTCR,
	78	PFRCR,
	79	RFCR,
	80	RFCF,
	81	TPAUSER,
	82	TPAUSECR,
	83	BCFR,
	84	BCFRR,
	85	GECMR,
	86	BCULR,
	87	MAHR,
	88	MALR,
	89	TROCR,
	90	CDCR,
	91	LCCR,
	92	CNDCR,
	93	CEFCR,
	94	FRECR,
	95	TSFRCR,
	96	TLFRCR,
	97	CERCR,
	98	CEECR,
99	MAFCR,
100	RTRATE,
f0e81fec NI	101	CSMR,
f0e81fec NI	102	RMII_MII,
4a55530f YS	103
	104	/* TSU Absolute address */
	105	ARSTR,
	106	TSU_CTRST,
	107	TSU_FWEN0,
	108	TSU_FWEN1,
	109	TSU_FCM,
	110	TSU_BSYSL0,
	111	TSU_BSYSL1,
	112	TSU_PRISL0,
	113	TSU_PRISL1,
	114	TSU_FWSL0,
	115	TSU_FWSL1,
	116	TSU_FWSLC,
	117	TSU_QTAG0,
	118	TSU_QTAG1,
	119	TSU_QTAGM0,
	120	TSU_QTAGM1,
	121	TSU_FWSR,
	122	TSU_FWINMK,
	123	TSU_ADQT0,
	124	TSU_ADQT1,
	125	TSU_VTAG0,
	126	TSU_VTAG1,
	127	TSU_ADSBSY,
	128	TSU_TEN,
	129	TSU_POST1,
	130	TSU_POST2,
	131	TSU_POST3,
	132	TSU_POST4,
	133	TSU_ADRH0,
	134	TSU_ADRL0,
	135	TSU_ADRH31,
	136	TSU_ADRL31,
	137
	138	TXNLCR0,
	139	TXALCR0,
	140	RXNLCR0,
	141	RXALCR0,
	142	FWNLCR0,
	143	FWALCR0,
	144	TXNLCR1,
	145	TXALCR1,
	146	RXNLCR1,
	147	RXALCR1,
	148	FWNLCR1,
	149	FWALCR1,
	150
	151	/* This value must be written at last. */
	152	SH_ETH_MAX_REGISTER_OFFSET,
	153	};
	154
	155	static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
	156	[EDSR] = 0x0000,
	157	[EDMR] = 0x0400,
	158	[EDTRR] = 0x0408,
	159	[EDRRR] = 0x0410,
	160	[EESR] = 0x0428,
	161	[EESIPR] = 0x0430,
	162	[TDLAR] = 0x0010,
	163	[TDFAR] = 0x0014,
	164	[TDFXR] = 0x0018,
	165	[TDFFR] = 0x001c,
	166	[RDLAR] = 0x0030,
167	[RDFAR] = 0x0034,
168	[RDFXR] = 0x0038,
169	[RDFFR] = 0x003c,
170	[TRSCER] = 0x0438,
171	[RMFCR] = 0x0440,
172	[TFTR] = 0x0448,
173	[FDR] = 0x0450,
174	[RMCR] = 0x0458,
175	[RPADIR] = 0x0460,
176	[FCFTR] = 0x0468,
f0e81fec	177	[CSMR] = 0x04E4,
4a55530f YS	178
	179	[ECMR] = 0x0500,
	180	[ECSR] = 0x0510,
	181	[ECSIPR] = 0x0518,
	182	[PIR] = 0x0520,
	183	[PSR] = 0x0528,
	184	[PIPR] = 0x052c,
	185	[RFLR] = 0x0508,
	186	[APR] = 0x0554,
	187	[MPR] = 0x0558,
	188	[PFTCR] = 0x055c,
	189	[PFRCR] = 0x0560,
	190	[TPAUSER] = 0x0564,
	191	[GECMR] = 0x05b0,
	192	[BCULR] = 0x05b4,
	193	[MAHR] = 0x05c0,
	194	[MALR] = 0x05c8,
	195	[TROCR] = 0x0700,
	196	[CDCR] = 0x0708,
	197	[LCCR] = 0x0710,
	198	[CEFCR] = 0x0740,
	199	[FRECR] = 0x0748,
	200	[TSFRCR] = 0x0750,
	201	[TLFRCR] = 0x0758,
	202	[RFCR] = 0x0760,
	203	[CERCR] = 0x0768,
	204	[CEECR] = 0x0770,
	205	[MAFCR] = 0x0778,
f0e81fec	206	[RMII_MII] = 0x0790,
4a55530f	207
4986b996	208	[ARSTR] = 0x0000,
4a55530f YS	209	[TSU_CTRST] = 0x0004,
	210	[TSU_FWEN0] = 0x0010,
	211	[TSU_FWEN1] = 0x0014,
	212	[TSU_FCM] = 0x0018,
	213	[TSU_BSYSL0] = 0x0020,
	214	[TSU_BSYSL1] = 0x0024,
	215	[TSU_PRISL0] = 0x0028,
	216	[TSU_PRISL1] = 0x002c,
	217	[TSU_FWSL0] = 0x0030,
	218	[TSU_FWSL1] = 0x0034,
	219	[TSU_FWSLC] = 0x0038,
	220	[TSU_QTAG0] = 0x0040,
	221	[TSU_QTAG1] = 0x0044,
	222	[TSU_FWSR] = 0x0050,
	223	[TSU_FWINMK] = 0x0054,
	224	[TSU_ADQT0] = 0x0048,
	225	[TSU_ADQT1] = 0x004c,
	226	[TSU_VTAG0] = 0x0058,
	227	[TSU_VTAG1] = 0x005c,
	228	[TSU_ADSBSY] = 0x0060,
	229	[TSU_TEN] = 0x0064,
	230	[TSU_POST1] = 0x0070,
	231	[TSU_POST2] = 0x0074,
	232	[TSU_POST3] = 0x0078,
	233	[TSU_POST4] = 0x007c,
	234	[TSU_ADRH0] = 0x0100,
	235	[TSU_ADRL0] = 0x0104,
	236	[TSU_ADRH31] = 0x01f8,
	237	[TSU_ADRL31] = 0x01fc,
	238
	239	[TXNLCR0] = 0x0080,
	240	[TXALCR0] = 0x0084,
	241	[RXNLCR0] = 0x0088,
	242	[RXALCR0] = 0x008c,
	243	[FWNLCR0] = 0x0090,
	244	[FWALCR0] = 0x0094,
	245	[TXNLCR1] = 0x00a0,
	246	[TXALCR1] = 0x00a0,
	247	[RXNLCR1] = 0x00a8,
	248	[RXALCR1] = 0x00ac,
	249	[FWNLCR1] = 0x00b0,
	250	[FWALCR1] = 0x00b4,
	251	};
	252
	253	static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
	254	[ECMR] = 0x0100,
	255	[RFLR] = 0x0108,
	256	[ECSR] = 0x0110,
	257	[ECSIPR] = 0x0118,
	258	[PIR] = 0x0120,
	259	[PSR] = 0x0128,
	260	[RDMLR] = 0x0140,
	261	[IPGR] = 0x0150,
	262	[APR] = 0x0154,
	263	[MPR] = 0x0158,
	264	[TPAUSER] = 0x0164,
	265	[RFCF] = 0x0160,
	266	[TPAUSECR] = 0x0168,
	267	[BCFRR] = 0x016c,
	268	[MAHR] = 0x01c0,
	269	[MALR] = 0x01c8,
	270	[TROCR] = 0x01d0,
	271	[CDCR] = 0x01d4,
	272	[LCCR] = 0x01d8,
273	[CNDCR] = 0x01dc,
274	[CEFCR] = 0x01e4,
275	[FRECR] = 0x01e8,
276	[TSFRCR] = 0x01ec,
277	[TLFRCR] = 0x01f0,
278	[RFCR] = 0x01f4,
279	[MAFCR] = 0x01f8,
280	[RTRATE] = 0x01fc,
281
282	[EDMR] = 0x0000,
283	[EDTRR] = 0x0008,
284	[EDRRR] = 0x0010,
285	[TDLAR] = 0x0018,
286	[RDLAR] = 0x0020,
287	[EESR] = 0x0028,
288	[EESIPR] = 0x0030,
289	[TRSCER] = 0x0038,
290	[RMFCR] = 0x0040,
291	[TFTR] = 0x0048,
292	[FDR] = 0x0050,
293	[RMCR] = 0x0058,
294	[TFUCR] = 0x0064,
295	[RFOCR] = 0x0068,
296	[FCFTR] = 0x0070,
297	[RPADIR] = 0x0078,
298	[TRIMD] = 0x007c,
299	[RBWAR] = 0x00c8,
300	[RDFAR] = 0x00cc,
301	[TBRAR] = 0x00d4,
302	[TDFAR] = 0x00d8,
303	};
304
305	static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
306	[ECMR] = 0x0160,
307	[ECSR] = 0x0164,
308	[ECSIPR] = 0x0168,
309	[PIR] = 0x016c,
310	[MAHR] = 0x0170,
311	[MALR] = 0x0174,
312	[RFLR] = 0x0178,
313	[PSR] = 0x017c,
314	[TROCR] = 0x0180,
315	[CDCR] = 0x0184,
316	[LCCR] = 0x0188,
317	[CNDCR] = 0x018c,
318	[CEFCR] = 0x0194,
319	[FRECR] = 0x0198,
320	[TSFRCR] = 0x019c,
321	[TLFRCR] = 0x01a0,
322	[RFCR] = 0x01a4,
323	[MAFCR] = 0x01a8,
324	[IPGR] = 0x01b4,
325	[APR] = 0x01b8,
326	[MPR] = 0x01bc,
327	[TPAUSER] = 0x01c4,
328	[BCFR] = 0x01cc,
329
4986b996	330	[ARSTR] = 0x0000,
4a55530f YS	331	[TSU_CTRST] = 0x0004,
	332	[TSU_FWEN0] = 0x0010,
	333	[TSU_FWEN1] = 0x0014,
	334	[TSU_FCM] = 0x0018,
	335	[TSU_BSYSL0] = 0x0020,
	336	[TSU_BSYSL1] = 0x0024,
	337	[TSU_PRISL0] = 0x0028,
	338	[TSU_PRISL1] = 0x002c,
	339	[TSU_FWSL0] = 0x0030,
	340	[TSU_FWSL1] = 0x0034,
	341	[TSU_FWSLC] = 0x0038,
	342	[TSU_QTAGM0] = 0x0040,
	343	[TSU_QTAGM1] = 0x0044,
	344	[TSU_ADQT0] = 0x0048,
	345	[TSU_ADQT1] = 0x004c,
	346	[TSU_FWSR] = 0x0050,
	347	[TSU_FWINMK] = 0x0054,
	348	[TSU_ADSBSY] = 0x0060,
	349	[TSU_TEN] = 0x0064,
	350	[TSU_POST1] = 0x0070,
	351	[TSU_POST2] = 0x0074,
	352	[TSU_POST3] = 0x0078,
	353	[TSU_POST4] = 0x007c,
	354
	355	[TXNLCR0] = 0x0080,
	356	[TXALCR0] = 0x0084,
	357	[RXNLCR0] = 0x0088,
	358	[RXALCR0] = 0x008c,
	359	[FWNLCR0] = 0x0090,
	360	[FWALCR0] = 0x0094,
	361	[TXNLCR1] = 0x00a0,
	362	[TXALCR1] = 0x00a0,
	363	[RXNLCR1] = 0x00a8,
	364	[RXALCR1] = 0x00ac,
	365	[FWNLCR1] = 0x00b0,
	366	[FWALCR1] = 0x00b4,
	367
	368	[TSU_ADRH0] = 0x0100,
	369	[TSU_ADRL0] = 0x0104,
	370	[TSU_ADRL31] = 0x01fc,
	371
	372	};
	373
380af9e3	374	/* Driver's parameters */
73a0d907	375	#if defined(CONFIG_CPU_SH4) \|\| defined(CONFIG_ARCH_SHMOBILE)
380af9e3 YS	376	#define SH4_SKB_RX_ALIGN 32
	377	#else
	378	#define SH2_SH3_SKB_RX_ALIGN 2
	379	#endif
	380
b0ca2a21 NI	381	/*
	382	* Register's bits
	383	*/
73a0d907 YS	384	#if defined(CONFIG_CPU_SUBTYPE_SH7734) \|\| defined(CONFIG_CPU_SUBTYPE_SH7763) \|\|\
73a0d907 YS	385	defined(CONFIG_ARCH_R8A7740)
b0ca2a21 NI	386	/* EDSR */
	387	enum EDSR_BIT {
	388	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
	389	};
	390	#define EDSR_ENALL (EDSR_ENT\|EDSR_ENR)
	391
	392	/* GECMR */
	393	enum GECMR_BIT {
	394	GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
	395	};
	396	#endif
86a74ff2 NI	397
	398	/* EDMR */
	399	enum DMAC_M_BIT {
380af9e3	400	EDMR_EL = 0x40, /* Litte endian */
b0ca2a21	401	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
c5ed5368 YS	402	EDMR_SRST_GETHER = 0x03,
c5ed5368 YS	403	EDMR_SRST_ETHER = 0x01,
86a74ff2 NI	404	};
	405
	406	/* EDTRR */
	407	enum DMAC_T_BIT {
c5ed5368 YS	408	EDTRR_TRNS_GETHER = 0x03,
c5ed5368 YS	409	EDTRR_TRNS_ETHER = 0x01,
86a74ff2 NI	410	};
	411
	412	/* EDRRR*/
	413	enum EDRRR_R_BIT {
	414	EDRRR_R = 0x01,
	415	};
	416
	417	/* TPAUSER */
	418	enum TPAUSER_BIT {
	419	TPAUSER_TPAUSE = 0x0000ffff,
	420	TPAUSER_UNLIMITED = 0,
	421	};
	422
	423	/* BCFR */
	424	enum BCFR_BIT {
	425	BCFR_RPAUSE = 0x0000ffff,
	426	BCFR_UNLIMITED = 0,
	427	};
	428
	429	/* PIR */
	430	enum PIR_BIT {
	431	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
	432	};
	433
	434	/* PSR */
	435	enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
	436
	437	/* EESR */
	438	enum EESR_BIT {
380af9e3 YS	439	EESR_TWB1 = 0x80000000,
	440	EESR_TWB = 0x40000000, /* same as TWB0 */
	441	EESR_TC1 = 0x20000000,
	442	EESR_TUC = 0x10000000,
	443	EESR_ROC = 0x08000000,
	444	EESR_TABT = 0x04000000,
	445	EESR_RABT = 0x02000000,
	446	EESR_RFRMER = 0x01000000, /* same as RFCOF */
	447	EESR_ADE = 0x00800000,
	448	EESR_ECI = 0x00400000,
	449	EESR_FTC = 0x00200000, /* same as TC or TC0 */
	450	EESR_TDE = 0x00100000,
	451	EESR_TFE = 0x00080000, /* same as TFUF */
	452	EESR_FRC = 0x00040000, /* same as FR */
	453	EESR_RDE = 0x00020000,
	454	EESR_RFE = 0x00010000,
	455	EESR_CND = 0x00000800,
	456	EESR_DLC = 0x00000400,
	457	EESR_CD = 0x00000200,
	458	EESR_RTO = 0x00000100,
	459	EESR_RMAF = 0x00000080,
	460	EESR_CEEF = 0x00000040,
	461	EESR_CELF = 0x00000020,
	462	EESR_RRF = 0x00000010,
	463	EESR_RTLF = 0x00000008,
	464	EESR_RTSF = 0x00000004,
	465	EESR_PRE = 0x00000002,
	466	EESR_CERF = 0x00000001,
	467	};
	468
	469	#define DEFAULT_TX_CHECK (EESR_FTC \| EESR_CND \| EESR_DLC \| EESR_CD \| \
	470	EESR_RTO)
	471	#define DEFAULT_EESR_ERR_CHECK (EESR_TWB \| EESR_TABT \| EESR_RABT \| \
	472	EESR_RDE \| EESR_RFRMER \| EESR_ADE \| \
	473	EESR_TFE \| EESR_TDE \| EESR_ECI)
	474	#define DEFAULT_TX_ERROR_CHECK (EESR_TWB \| EESR_TABT \| EESR_ADE \| EESR_TDE \| \
	475	EESR_TFE)
86a74ff2 NI	476
	477	/* EESIPR */
	478	enum DMAC_IM_BIT {
	479	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
	480	DMAC_M_RABT = 0x02000000,
	481	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
	482	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
	483	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
	484	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
	485	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
	486	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
	487	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
	488	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
	489	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
	490	DMAC_M_RINT1 = 0x00000001,
	491	};
	492
	493	/* Receive descriptor bit */
	494	enum RD_STS_BIT {
b0ca2a21 NI	495	RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
b0ca2a21 NI	496	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
86a74ff2 NI	497	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
	498	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
	499	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
	500	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
	501	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
	502	RD_RFS1 = 0x00000001,
	503	};
b0ca2a21 NI	504	#define RDF1ST RD_RFP1
	505	#define RDFEND RD_RFP0
	506	#define RD_RFP (RD_RFP1\|RD_RFP0)
86a74ff2 NI	507
	508	/* FCFTR */
	509	enum FCFTR_BIT {
	510	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
	511	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
	512	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
	513	};
380af9e3 YS	514	#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 \| FCFTR_RFF1 \| FCFTR_RFF0)
380af9e3 YS	515	#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 \| FCFTR_RFD1 \| FCFTR_RFD0)
86a74ff2 NI	516
	517	/* Transfer descriptor bit */
	518	enum TD_STS_BIT {
b0ca2a21 NI	519	TD_TACT = 0x80000000,
b0ca2a21 NI	520	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
86a74ff2 NI	521	TD_TFP0 = 0x10000000,
	522	};
	523	#define TDF1ST TD_TFP1
	524	#define TDFEND TD_TFP0
	525	#define TD_TFP (TD_TFP1\|TD_TFP0)
	526
	527	/* RMCR */
380af9e3 YS	528	#define DEFAULT_RMCR_VALUE 0x00000000
380af9e3 YS	529
86a74ff2 NI	530	/* ECMR */
86a74ff2 NI	531	enum FELIC_MODE_BIT {
b0ca2a21 NI	532	ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
b0ca2a21 NI	533	ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
86a74ff2 NI	534	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
	535	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
	536	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
65ac8851	537	ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
380af9e3	538	ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
86a74ff2 NI	539	};
	540
	541	/* ECSR */
	542	enum ECSR_STATUS_BIT {
b0ca2a21	543	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
b0ca2a21	544	ECSR_LCHNG = 0x04,
86a74ff2 NI	545	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
	546	};
	547
380af9e3 YS	548	#define DEFAULT_ECSR_INIT (ECSR_BRCRX \| ECSR_PSRTO \| ECSR_LCHNG \| \
380af9e3 YS	549	ECSR_ICD \| ECSIPR_MPDIP)
b0ca2a21	550
86a74ff2 NI	551	/* ECSIPR */
86a74ff2 NI	552	enum ECSIPR_STATUS_MASK_BIT {
b0ca2a21	553	ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
b0ca2a21	554	ECSIPR_LCHNGIP = 0x04,
86a74ff2 NI	555	ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
	556	};
	557
380af9e3 YS	558	#define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP \| ECSIPR_PSRTOIP \| \
380af9e3 YS	559	ECSIPR_LCHNGIP \| ECSIPR_ICDIP \| ECSIPR_MPDIP)
b0ca2a21	560
86a74ff2 NI	561	/* APR */
	562	enum APR_BIT {
	563	APR_AP = 0x00000001,
	564	};
	565
	566	/* MPR */
	567	enum MPR_BIT {
	568	MPR_MP = 0x00000001,
	569	};
	570
	571	/* TRSCER */
	572	enum DESC_I_BIT {
	573	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
	574	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
	575	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
	576	DESC_I_RINT1 = 0x0001,
	577	};
	578
	579	/* RPADIR */
	580	enum RPADIR_BIT {
	581	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
	582	RPADIR_PADR = 0x0003f,
	583	};
	584
	585	/* FDR */
380af9e3 YS	586	#define DEFAULT_FDR_INIT 0x00000707
380af9e3 YS	587
86a74ff2 NI	588	/* ARSTR */
	589	enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
	590
	591	/* TSU_FWEN0 */
	592	enum TSU_FWEN0_BIT {
	593	TSU_FWEN0_0 = 0x00000001,
	594	};
	595
	596	/* TSU_ADSBSY */
	597	enum TSU_ADSBSY_BIT {
	598	TSU_ADSBSY_0 = 0x00000001,
	599	};
	600
	601	/* TSU_TEN */
	602	enum TSU_TEN_BIT {
	603	TSU_TEN_0 = 0x80000000,
	604	};
	605
	606	/* TSU_FWSL0 */
	607	enum TSU_FWSL0_BIT {
	608	TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
	609	TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
	610	TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
	611	};
	612
	613	/* TSU_FWSLC */
	614	enum TSU_FWSLC_BIT {
	615	TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
	616	TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
	617	TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
	618	TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
	619	TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
	620	};
	621
71cc7c37 YS	622	/* TSU_VTAGn */
	623	#define TSU_VTAG_ENABLE 0x80000000
	624	#define TSU_VTAG_VID_MASK 0x00000fff
	625
86a74ff2 NI	626	/*
	627	* The sh ether Tx buffer descriptors.
	628	* This structure should be 20 bytes.
	629	*/
	630	struct sh_eth_txdesc {
	631	u32 status; /* TD0 */
10b9194f	632	#if defined(__LITTLE_ENDIAN)
86a74ff2 NI	633	u16 pad0; /* TD1 */
	634	u16 buffer_length; /* TD1 */
	635	#else
	636	u16 buffer_length; /* TD1 */
	637	u16 pad0; /* TD1 */
	638	#endif
	639	u32 addr; /* TD2 */
	640	u32 pad1; /* padding data */
71557a37	641	} __attribute__((aligned(2), packed));
86a74ff2 NI	642
	643	/*
	644	* The sh ether Rx buffer descriptors.
	645	* This structure should be 20 bytes.
	646	*/
	647	struct sh_eth_rxdesc {
	648	u32 status; /* RD0 */
10b9194f	649	#if defined(__LITTLE_ENDIAN)
86a74ff2 NI	650	u16 frame_length; /* RD1 */
	651	u16 buffer_length; /* RD1 */
	652	#else
	653	u16 buffer_length; /* RD1 */
	654	u16 frame_length; /* RD1 */
	655	#endif
	656	u32 addr; /* RD2 */
	657	u32 pad0; /* padding data */
71557a37	658	} __attribute__((aligned(2), packed));
86a74ff2	659
380af9e3 YS	660	/* This structure is used by each CPU dependency handling. */
	661	struct sh_eth_cpu_data {
	662	/* optional functions */
	663	void (chip_reset)(struct net_device ndev);
	664	void (set_duplex)(struct net_device ndev);
	665	void (set_rate)(struct net_device ndev);
	666
	667	/* mandatory initialize value */
	668	unsigned long eesipr_value;
	669
	670	/* optional initialize value */
	671	unsigned long ecsr_value;
	672	unsigned long ecsipr_value;
	673	unsigned long fdr_value;
	674	unsigned long fcftr_value;
	675	unsigned long rpadir_value;
	676	unsigned long rmcr_value;
	677
	678	/* interrupt checking mask */
	679	unsigned long tx_check;
	680	unsigned long eesr_err_check;
	681	unsigned long tx_error_check;
	682
	683	/* hardware features */
	684	unsigned no_psr:1; /* EtherC DO NOT have PSR */
	685	unsigned apr:1; /* EtherC have APR */
	686	unsigned mpr:1; /* EtherC have MPR */
	687	unsigned tpauser:1; /* EtherC have TPAUSER */
	688	unsigned bculr:1; /* EtherC have BCULR */
4986b996	689	unsigned tsu:1; /* EtherC have TSU */
380af9e3 YS	690	unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
	691	unsigned rpadir:1; /* E-DMAC have RPADIR */
	692	unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
	693	unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
f0e81fec	694	unsigned hw_crc:1; /* E-DMAC have CSMR */
5e7a76be	695	unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */
380af9e3 YS	696	};
380af9e3 YS	697
86a74ff2	698	struct sh_eth_private {
bcd5149d	699	struct platform_device *pdev;
380af9e3	700	struct sh_eth_cpu_data *cd;
4a55530f	701	const u16 *reg_offset;
ae70644d	702	void __iomem *addr;
4a55530f	703	void __iomem *tsu_addr;
86a74ff2 NI	704	dma_addr_t rx_desc_dma;
	705	dma_addr_t tx_desc_dma;
	706	struct sh_eth_rxdesc *rx_ring;
	707	struct sh_eth_txdesc *tx_ring;
	708	struct sk_buff **rx_skbuff;
	709	struct sk_buff **tx_skbuff;
86a74ff2 NI	710	spinlock_t lock;
	711	u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
	712	u32 cur_tx, dirty_tx;
	713	u32 rx_buf_sz; /* Based on MTU+slack. */
71557a37	714	int edmac_endian;
86a74ff2 NI	715	/* MII transceiver section. */
	716	u32 phy_id; /* PHY ID */
	717	struct mii_bus mii_bus; / MDIO bus control */
	718	struct phy_device phydev; / PHY device control */
	719	enum phy_state link;
e47c9052	720	phy_interface_t phy_interface;
86a74ff2 NI	721	int msg_enable;
	722	int speed;
	723	int duplex;
6743fe6d	724	int port; /* for TSU */
71cc7c37	725	int vlan_num_ids; /* for VLAN tag filter */
4923576b YS	726
	727	unsigned no_ether_link:1;
	728	unsigned ether_link_active_low:1;
86a74ff2 NI	729	};
86a74ff2 NI	730
380af9e3	731	static inline void sh_eth_soft_swap(char *src, int len)
86a74ff2 NI	732	{
	733	#ifdef __LITTLE_ENDIAN__
	734	u32 p = (u32 )src;
	735	u32 *maxp;
	736	maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
	737
	738	for (; p < maxp; p++)
	739	p = swab32(p);
	740	#endif
	741	}
380af9e3	742
4a55530f YS	743	static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
	744	int enum_index)
	745	{
	746	struct sh_eth_private *mdp = netdev_priv(ndev);
	747
ae70644d	748	iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
4a55530f YS	749	}
	750
	751	static inline unsigned long sh_eth_read(struct net_device *ndev,
	752	int enum_index)
	753	{
	754	struct sh_eth_private *mdp = netdev_priv(ndev);
	755
ae70644d	756	return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
4a55530f YS	757	}
4a55530f YS	758
6743fe6d YS	759	static inline void sh_eth_tsu_get_offset(struct sh_eth_private mdp,
	760	int enum_index)
	761	{
	762	return mdp->tsu_addr + mdp->reg_offset[enum_index];
	763	}
	764
4a55530f YS	765	static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
	766	unsigned long data, int enum_index)
	767	{
ae70644d	768	iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
4a55530f YS	769	}
	770
	771	static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
	772	int enum_index)
	773	{
ae70644d	774	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
4a55530f YS	775	}
4a55530f YS	776
380af9e3	777	#endif /* #ifndef __SH_ETH_H__ */