[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.h

/*
 *  SuperH Ethernet device driver
 *
 *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
 *  Copyright (C) 2008-2012 Renesas Solutions Corp.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms and conditions of the GNU General Public License,
 *  version 2, as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *  You should have received a copy of the GNU General Public License along with
 *  this program; if not, write to the Free Software Foundation, Inc.,
 *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 *  The full GNU General Public License is included in this distribution in
 *  the file called "COPYING".
 */

#ifndef __SH_ETH_H__
#define __SH_ETH_H__

#define CARDNAME	"sh-eth"
#define TX_TIMEOUT	(5*HZ)
#define TX_RING_SIZE	64	/* Tx ring size */
#define RX_RING_SIZE	64	/* Rx ring size */
#define TX_RING_MIN	64
#define RX_RING_MIN	64
#define TX_RING_MAX	1024
#define RX_RING_MAX	1024
#define ETHERSMALL		60
#define PKT_BUF_SZ		1538
#define SH_ETH_TSU_TIMEOUT_MS	500
#define SH_ETH_TSU_CAM_ENTRIES	32

enum {
	/* E-DMAC registers */
	EDSR = 0,
	EDMR,
	EDTRR,
	EDRRR,
	EESR,
	EESIPR,
	TDLAR,
	TDFAR,
	TDFXR,
	TDFFR,
	RDLAR,
	RDFAR,
	RDFXR,
	RDFFR,
	TRSCER,
	RMFCR,
	TFTR,
	FDR,
	RMCR,
	EDOCR,
	TFUCR,
	RFOCR,
	FCFTR,
	RPADIR,
	TRIMD,
	RBWAR,
	TBRAR,

	/* Ether registers */
	ECMR,
	ECSR,
	ECSIPR,
	PIR,
	PSR,
	RDMLR,
	PIPR,
	RFLR,
	IPGR,
	APR,
	MPR,
	PFTCR,
	PFRCR,
	RFCR,
	RFCF,
	TPAUSER,
	TPAUSECR,
	BCFR,
	BCFRR,
	GECMR,
	BCULR,
	MAHR,
	MALR,
	TROCR,
	CDCR,
	LCCR,
	CNDCR,
	CEFCR,
	FRECR,
	TSFRCR,
	TLFRCR,
	CERCR,
	CEECR,
	MAFCR,
	RTRATE,
	CSMR,
	RMII_MII,

	/* TSU Absolute address */
	ARSTR,
	TSU_CTRST,
	TSU_FWEN0,
	TSU_FWEN1,
	TSU_FCM,
	TSU_BSYSL0,
	TSU_BSYSL1,
	TSU_PRISL0,
	TSU_PRISL1,
	TSU_FWSL0,
	TSU_FWSL1,
	TSU_FWSLC,
	TSU_QTAG0,
	TSU_QTAG1,
	TSU_QTAGM0,
	TSU_QTAGM1,
	TSU_FWSR,
	TSU_FWINMK,
	TSU_ADQT0,
	TSU_ADQT1,
	TSU_VTAG0,
	TSU_VTAG1,
	TSU_ADSBSY,
	TSU_TEN,
	TSU_POST1,
	TSU_POST2,
	TSU_POST3,
	TSU_POST4,
	TSU_ADRH0,
	TSU_ADRL0,
	TSU_ADRH31,
	TSU_ADRL31,

	TXNLCR0,
	TXALCR0,
	RXNLCR0,
	RXALCR0,
	FWNLCR0,
	FWALCR0,
	TXNLCR1,
	TXALCR1,
	RXNLCR1,
	RXALCR1,
	FWNLCR1,
	FWALCR1,

	/* This value must be written at last. */
	SH_ETH_MAX_REGISTER_OFFSET,
};

static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
	[EDSR]	= 0x0000,
	[EDMR]	= 0x0400,
	[EDTRR]	= 0x0408,
	[EDRRR]	= 0x0410,
	[EESR]	= 0x0428,
	[EESIPR]	= 0x0430,
	[TDLAR]	= 0x0010,
	[TDFAR]	= 0x0014,
	[TDFXR]	= 0x0018,
	[TDFFR]	= 0x001c,
	[RDLAR]	= 0x0030,
	[RDFAR]	= 0x0034,
	[RDFXR]	= 0x0038,
	[RDFFR]	= 0x003c,
	[TRSCER]	= 0x0438,
	[RMFCR]	= 0x0440,
	[TFTR]	= 0x0448,
	[FDR]	= 0x0450,
	[RMCR]	= 0x0458,
	[RPADIR]	= 0x0460,
	[FCFTR]	= 0x0468,
	[CSMR] = 0x04E4,

	[ECMR]	= 0x0500,
	[ECSR]	= 0x0510,
	[ECSIPR]	= 0x0518,
	[PIR]	= 0x0520,
	[PSR]	= 0x0528,
	[PIPR]	= 0x052c,
	[RFLR]	= 0x0508,
	[APR]	= 0x0554,
	[MPR]	= 0x0558,
	[PFTCR]	= 0x055c,
	[PFRCR]	= 0x0560,
	[TPAUSER]	= 0x0564,
	[GECMR]	= 0x05b0,
	[BCULR]	= 0x05b4,
	[MAHR]	= 0x05c0,
	[MALR]	= 0x05c8,
	[TROCR]	= 0x0700,
	[CDCR]	= 0x0708,
	[LCCR]	= 0x0710,
	[CEFCR]	= 0x0740,
	[FRECR]	= 0x0748,
	[TSFRCR]	= 0x0750,
	[TLFRCR]	= 0x0758,
	[RFCR]	= 0x0760,
	[CERCR]	= 0x0768,
	[CEECR]	= 0x0770,
	[MAFCR]	= 0x0778,
	[RMII_MII] =  0x0790,

	[ARSTR]	= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_FWEN0]	= 0x0010,
	[TSU_FWEN1]	= 0x0014,
	[TSU_FCM]	= 0x0018,
	[TSU_BSYSL0]	= 0x0020,
	[TSU_BSYSL1]	= 0x0024,
	[TSU_PRISL0]	= 0x0028,
	[TSU_PRISL1]	= 0x002c,
	[TSU_FWSL0]	= 0x0030,
	[TSU_FWSL1]	= 0x0034,
	[TSU_FWSLC]	= 0x0038,
	[TSU_QTAG0]	= 0x0040,
	[TSU_QTAG1]	= 0x0044,
	[TSU_FWSR]	= 0x0050,
	[TSU_FWINMK]	= 0x0054,
	[TSU_ADQT0]	= 0x0048,
	[TSU_ADQT1]	= 0x004c,
	[TSU_VTAG0]	= 0x0058,
	[TSU_VTAG1]	= 0x005c,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,
	[TSU_ADRH0]	= 0x0100,
	[TSU_ADRL0]	= 0x0104,
	[TSU_ADRH31]	= 0x01f8,
	[TSU_ADRL31]	= 0x01fc,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008c,
	[FWNLCR0]	= 0x0090,
	[FWALCR0]	= 0x0094,
	[TXNLCR1]	= 0x00a0,
	[TXALCR1]	= 0x00a0,
	[RXNLCR1]	= 0x00a8,
	[RXALCR1]	= 0x00ac,
	[FWNLCR1]	= 0x00b0,
	[FWALCR1]	= 0x00b4,
};

static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]	= 0x0100,
	[RFLR]	= 0x0108,
	[ECSR]	= 0x0110,
	[ECSIPR]	= 0x0118,
	[PIR]	= 0x0120,
	[PSR]	= 0x0128,
	[RDMLR]	= 0x0140,
	[IPGR]	= 0x0150,
	[APR]	= 0x0154,
	[MPR]	= 0x0158,
	[TPAUSER]	= 0x0164,
	[RFCF]	= 0x0160,
	[TPAUSECR]	= 0x0168,
	[BCFRR]	= 0x016c,
	[MAHR]	= 0x01c0,
	[MALR]	= 0x01c8,
	[TROCR]	= 0x01d0,
	[CDCR]	= 0x01d4,
	[LCCR]	= 0x01d8,
	[CNDCR]	= 0x01dc,
	[CEFCR]	= 0x01e4,
	[FRECR]	= 0x01e8,
	[TSFRCR]	= 0x01ec,
	[TLFRCR]	= 0x01f0,
	[RFCR]	= 0x01f4,
	[MAFCR]	= 0x01f8,
	[RTRATE]	= 0x01fc,

	[EDMR]	= 0x0000,
	[EDTRR]	= 0x0008,
	[EDRRR]	= 0x0010,
	[TDLAR]	= 0x0018,
	[RDLAR]	= 0x0020,
	[EESR]	= 0x0028,
	[EESIPR]	= 0x0030,
	[TRSCER]	= 0x0038,
	[RMFCR]	= 0x0040,
	[TFTR]	= 0x0048,
	[FDR]	= 0x0050,
	[RMCR]	= 0x0058,
	[TFUCR]	= 0x0064,
	[RFOCR]	= 0x0068,
	[FCFTR]	= 0x0070,
	[RPADIR]	= 0x0078,
	[TRIMD]	= 0x007c,
	[RBWAR]	= 0x00c8,
	[RDFAR]	= 0x00cc,
	[TBRAR]	= 0x00d4,
	[TDFAR]	= 0x00d8,
};

static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]	= 0x0160,
	[ECSR]	= 0x0164,
	[ECSIPR]	= 0x0168,
	[PIR]	= 0x016c,
	[MAHR]	= 0x0170,
	[MALR]	= 0x0174,
	[RFLR]	= 0x0178,
	[PSR]	= 0x017c,
	[TROCR]	= 0x0180,
	[CDCR]	= 0x0184,
	[LCCR]	= 0x0188,
	[CNDCR]	= 0x018c,
	[CEFCR]	= 0x0194,
	[FRECR]	= 0x0198,
	[TSFRCR]	= 0x019c,
	[TLFRCR]	= 0x01a0,
	[RFCR]	= 0x01a4,
	[MAFCR]	= 0x01a8,
	[IPGR]	= 0x01b4,
	[APR]	= 0x01b8,
	[MPR]	= 0x01bc,
	[TPAUSER]	= 0x01c4,
	[BCFR]	= 0x01cc,

	[ARSTR]	= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_FWEN0]	= 0x0010,
	[TSU_FWEN1]	= 0x0014,
	[TSU_FCM]	= 0x0018,
	[TSU_BSYSL0]	= 0x0020,
	[TSU_BSYSL1]	= 0x0024,
	[TSU_PRISL0]	= 0x0028,
	[TSU_PRISL1]	= 0x002c,
	[TSU_FWSL0]	= 0x0030,
	[TSU_FWSL1]	= 0x0034,
	[TSU_FWSLC]	= 0x0038,
	[TSU_QTAGM0]	= 0x0040,
	[TSU_QTAGM1]	= 0x0044,
	[TSU_ADQT0]	= 0x0048,
	[TSU_ADQT1]	= 0x004c,
	[TSU_FWSR]	= 0x0050,
	[TSU_FWINMK]	= 0x0054,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008c,
	[FWNLCR0]	= 0x0090,
	[FWALCR0]	= 0x0094,
	[TXNLCR1]	= 0x00a0,
	[TXALCR1]	= 0x00a0,
	[RXNLCR1]	= 0x00a8,
	[RXALCR1]	= 0x00ac,
	[FWNLCR1]	= 0x00b0,
	[FWALCR1]	= 0x00b4,

	[TSU_ADRH0]	= 0x0100,
	[TSU_ADRL0]	= 0x0104,
	[TSU_ADRL31]	= 0x01fc,

};

/* Driver's parameters */
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
#define SH4_SKB_RX_ALIGN	32
#else
#define SH2_SH3_SKB_RX_ALIGN	2
#endif

/*
 * Register's bits
 */
#if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\
    defined(CONFIG_ARCH_R8A7740)
/* EDSR */
enum EDSR_BIT {
	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
};
#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)

/* GECMR */
enum GECMR_BIT {
	GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
};
#endif

/* EDMR */
enum DMAC_M_BIT {
	EDMR_EL = 0x40, /* Litte endian */
	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
	EDMR_SRST_GETHER = 0x03,
	EDMR_SRST_ETHER = 0x01,
};

/* EDTRR */
enum DMAC_T_BIT {
	EDTRR_TRNS_GETHER = 0x03,
	EDTRR_TRNS_ETHER = 0x01,
};

/* EDRRR*/
enum EDRRR_R_BIT {
	EDRRR_R = 0x01,
};

/* TPAUSER */
enum TPAUSER_BIT {
	TPAUSER_TPAUSE = 0x0000ffff,
	TPAUSER_UNLIMITED = 0,
};

/* BCFR */
enum BCFR_BIT {
	BCFR_RPAUSE = 0x0000ffff,
	BCFR_UNLIMITED = 0,
};

/* PIR */
enum PIR_BIT {
	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
};

/* PSR */
enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };

/* EESR */
enum EESR_BIT {
	EESR_TWB1	= 0x80000000,
	EESR_TWB	= 0x40000000,	/* same as TWB0 */
	EESR_TC1	= 0x20000000,
	EESR_TUC	= 0x10000000,
	EESR_ROC	= 0x08000000,
	EESR_TABT	= 0x04000000,
	EESR_RABT	= 0x02000000,
	EESR_RFRMER	= 0x01000000,	/* same as RFCOF */
	EESR_ADE	= 0x00800000,
	EESR_ECI	= 0x00400000,
	EESR_FTC	= 0x00200000,	/* same as TC or TC0 */
	EESR_TDE	= 0x00100000,
	EESR_TFE	= 0x00080000,	/* same as TFUF */
	EESR_FRC	= 0x00040000,	/* same as FR */
	EESR_RDE	= 0x00020000,
	EESR_RFE	= 0x00010000,
	EESR_CND	= 0x00000800,
	EESR_DLC	= 0x00000400,
	EESR_CD		= 0x00000200,
	EESR_RTO	= 0x00000100,
	EESR_RMAF	= 0x00000080,
	EESR_CEEF	= 0x00000040,
	EESR_CELF	= 0x00000020,
	EESR_RRF	= 0x00000010,
	EESR_RTLF	= 0x00000008,
	EESR_RTSF	= 0x00000004,
	EESR_PRE	= 0x00000002,
	EESR_CERF	= 0x00000001,
};

#define DEFAULT_TX_CHECK	(EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
				 EESR_RTO)
#define DEFAULT_EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | \
				 EESR_RDE | EESR_RFRMER | EESR_ADE | \
				 EESR_TFE | EESR_TDE | EESR_ECI)
#define DEFAULT_TX_ERROR_CHECK	(EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
				 EESR_TFE)

/* EESIPR */
enum DMAC_IM_BIT {
	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
	DMAC_M_RABT = 0x02000000,
	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
	DMAC_M_RINT1 = 0x00000001,
};

/* Receive descriptor bit */
enum RD_STS_BIT {
	RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
	RD_RFS1 = 0x00000001,
};
#define RDF1ST	RD_RFP1
#define RDFEND	RD_RFP0
#define RD_RFP	(RD_RFP1|RD_RFP0)

/* FCFTR */
enum FCFTR_BIT {
	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
};
#define DEFAULT_FIFO_F_D_RFF	(FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
#define DEFAULT_FIFO_F_D_RFD	(FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)

/* Transfer descriptor bit */
enum TD_STS_BIT {
	TD_TACT = 0x80000000,
	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
	TD_TFP0 = 0x10000000,
};
#define TDF1ST	TD_TFP1
#define TDFEND	TD_TFP0
#define TD_TFP	(TD_TFP1|TD_TFP0)

/* RMCR */
#define DEFAULT_RMCR_VALUE	0x00000000

/* ECMR */
enum FELIC_MODE_BIT {
	ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
	ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
	ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
	ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
};

/* ECSR */
enum ECSR_STATUS_BIT {
	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
	ECSR_LCHNG = 0x04,
	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
};

#define DEFAULT_ECSR_INIT	(ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
				 ECSR_ICD | ECSIPR_MPDIP)

/* ECSIPR */
enum ECSIPR_STATUS_MASK_BIT {
	ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
	ECSIPR_LCHNGIP = 0x04,
	ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
};

#define DEFAULT_ECSIPR_INIT	(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
				 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)

/* APR */
enum APR_BIT {
	APR_AP = 0x00000001,
};

/* MPR */
enum MPR_BIT {
	MPR_MP = 0x00000001,
};

/* TRSCER */
enum DESC_I_BIT {
	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
	DESC_I_RINT1 = 0x0001,
};

/* RPADIR */
enum RPADIR_BIT {
	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
	RPADIR_PADR = 0x0003f,
};

/* FDR */
#define DEFAULT_FDR_INIT	0x00000707

/* ARSTR */
enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };

/* TSU_FWEN0 */
enum TSU_FWEN0_BIT {
	TSU_FWEN0_0 = 0x00000001,
};

/* TSU_ADSBSY */
enum TSU_ADSBSY_BIT {
	TSU_ADSBSY_0 = 0x00000001,
};

/* TSU_TEN */
enum TSU_TEN_BIT {
	TSU_TEN_0 = 0x80000000,
};

/* TSU_FWSL0 */
enum TSU_FWSL0_BIT {
	TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
	TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
	TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
};

/* TSU_FWSLC */
enum TSU_FWSLC_BIT {
	TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
	TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
	TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
	TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
	TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
};

/* TSU_VTAGn */
#define TSU_VTAG_ENABLE		0x80000000
#define TSU_VTAG_VID_MASK	0x00000fff

/*
 * The sh ether Tx buffer descriptors.
 * This structure should be 20 bytes.
 */
struct sh_eth_txdesc {
	u32 status;		/* TD0 */
#if defined(__LITTLE_ENDIAN)
	u16 pad0;		/* TD1 */
	u16 buffer_length;	/* TD1 */
#else
	u16 buffer_length;	/* TD1 */
	u16 pad0;		/* TD1 */
#endif
	u32 addr;		/* TD2 */
	u32 pad1;		/* padding data */
} __attribute__((aligned(2), packed));

/*
 * The sh ether Rx buffer descriptors.
 * This structure should be 20 bytes.
 */
struct sh_eth_rxdesc {
	u32 status;		/* RD0 */
#if defined(__LITTLE_ENDIAN)
	u16 frame_length;	/* RD1 */
	u16 buffer_length;	/* RD1 */
#else
	u16 buffer_length;	/* RD1 */
	u16 frame_length;	/* RD1 */
#endif
	u32 addr;		/* RD2 */
	u32 pad0;		/* padding data */
} __attribute__((aligned(2), packed));

/* This structure is used by each CPU dependency handling. */
struct sh_eth_cpu_data {
	/* optional functions */
	void (*chip_reset)(struct net_device *ndev);
	void (*set_duplex)(struct net_device *ndev);
	void (*set_rate)(struct net_device *ndev);

	/* mandatory initialize value */
	unsigned long eesipr_value;

	/* optional initialize value */
	unsigned long ecsr_value;
	unsigned long ecsipr_value;
	unsigned long fdr_value;
	unsigned long fcftr_value;
	unsigned long rpadir_value;
	unsigned long rmcr_value;

	/* interrupt checking mask */
	unsigned long tx_check;
	unsigned long eesr_err_check;
	unsigned long tx_error_check;

	/* hardware features */
	unsigned no_psr:1;		/* EtherC DO NOT have PSR */
	unsigned apr:1;			/* EtherC have APR */
	unsigned mpr:1;			/* EtherC have MPR */
	unsigned tpauser:1;		/* EtherC have TPAUSER */
	unsigned bculr:1;		/* EtherC have BCULR */
	unsigned tsu:1;			/* EtherC have TSU */
	unsigned hw_swap:1;		/* E-DMAC have DE bit in EDMR */
	unsigned rpadir:1;		/* E-DMAC have RPADIR */
	unsigned no_trimd:1;		/* E-DMAC DO NOT have TRIMD */
	unsigned no_ade:1;	/* E-DMAC DO NOT have ADE bit in EESR */
	unsigned hw_crc:1;	/* E-DMAC have CSMR */
	unsigned select_mii:1;	/* EtherC have RMII_MII (MII select register) */
};

struct sh_eth_private {
	struct platform_device *pdev;
	struct sh_eth_cpu_data *cd;
	const u16 *reg_offset;
	void __iomem *addr;
	void __iomem *tsu_addr;
	struct bb_info *bitbang;
	u32 num_rx_ring;
	u32 num_tx_ring;
	dma_addr_t rx_desc_dma;
	dma_addr_t tx_desc_dma;
	struct sh_eth_rxdesc *rx_ring;
	struct sh_eth_txdesc *tx_ring;
	struct sk_buff **rx_skbuff;
	struct sk_buff **tx_skbuff;
	spinlock_t lock;
	u32 cur_rx, dirty_rx;	/* Producer/consumer ring indices */
	u32 cur_tx, dirty_tx;
	u32 rx_buf_sz;		/* Based on MTU+slack. */
	int edmac_endian;
	/* MII transceiver section. */
	u32 phy_id;					/* PHY ID */
	struct mii_bus *mii_bus;	/* MDIO bus control */
	struct phy_device *phydev;	/* PHY device control */
	enum phy_state link;
	phy_interface_t phy_interface;
	int msg_enable;
	int speed;
	int duplex;
	int port;		/* for TSU */
	int vlan_num_ids;	/* for VLAN tag filter */

	unsigned no_ether_link:1;
	unsigned ether_link_active_low:1;
};

static inline void sh_eth_soft_swap(char *src, int len)
{
#ifdef __LITTLE_ENDIAN__
	u32 *p = (u32 *)src;
	u32 *maxp;
	maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));

	for (; p < maxp; p++)
		*p = swab32(*p);
#endif
}

static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
				int enum_index)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
}

static inline unsigned long sh_eth_read(struct net_device *ndev,
					int enum_index)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
}

static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
					  int enum_index)
{
	return mdp->tsu_addr + mdp->reg_offset[enum_index];
}

static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
				unsigned long data, int enum_index)
{
	iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
}

static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
					int enum_index)
{
	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
}

#endif	/* #ifndef __SH_ETH_H__ */
Commit	Line	Data
86a74ff2 NI	1	/*
	2	* SuperH Ethernet device driver
	3	*
f0e81fec NI	4	* Copyright (C) 2006-2012 Nobuhiro Iwamatsu
f0e81fec NI	5	* Copyright (C) 2008-2012 Renesas Solutions Corp.
86a74ff2 NI	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program; if not, write to the Free Software Foundation, Inc.,
	17	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18	*
	19	* The full GNU General Public License is included in this distribution in
	20	* the file called "COPYING".
	21	*/
	22
	23	#ifndef __SH_ETH_H__
	24	#define __SH_ETH_H__
	25
86a74ff2 NI	26	#define CARDNAME "sh-eth"
86a74ff2 NI	27	#define TX_TIMEOUT (5*HZ)
b0ca2a21 NI	28	#define TX_RING_SIZE 64 /* Tx ring size */
b0ca2a21 NI	29	#define RX_RING_SIZE 64 /* Rx ring size */
525b8075 YS	30	#define TX_RING_MIN 64
	31	#define RX_RING_MIN 64
	32	#define TX_RING_MAX 1024
	33	#define RX_RING_MAX 1024
86a74ff2 NI	34	#define ETHERSMALL 60
86a74ff2 NI	35	#define PKT_BUF_SZ 1538
6743fe6d YS	36	#define SH_ETH_TSU_TIMEOUT_MS 500
6743fe6d YS	37	#define SH_ETH_TSU_CAM_ENTRIES 32
86a74ff2	38
4a55530f YS	39	enum {
	40	/* E-DMAC registers */
	41	EDSR = 0,
	42	EDMR,
	43	EDTRR,
	44	EDRRR,
	45	EESR,
	46	EESIPR,
	47	TDLAR,
	48	TDFAR,
	49	TDFXR,
	50	TDFFR,
	51	RDLAR,
	52	RDFAR,
	53	RDFXR,
	54	RDFFR,
	55	TRSCER,
	56	RMFCR,
	57	TFTR,
	58	FDR,
	59	RMCR,
	60	EDOCR,
	61	TFUCR,
	62	RFOCR,
	63	FCFTR,
	64	RPADIR,
	65	TRIMD,
	66	RBWAR,
	67	TBRAR,
	68
	69	/* Ether registers */
	70	ECMR,
	71	ECSR,
	72	ECSIPR,
	73	PIR,
	74	PSR,
	75	RDMLR,
	76	PIPR,
	77	RFLR,
	78	IPGR,
	79	APR,
	80	MPR,
	81	PFTCR,
	82	PFRCR,
	83	RFCR,
	84	RFCF,
	85	TPAUSER,
	86	TPAUSECR,
	87	BCFR,
	88	BCFRR,
	89	GECMR,
	90	BCULR,
	91	MAHR,
	92	MALR,
	93	TROCR,
	94	CDCR,
	95	LCCR,
	96	CNDCR,
	97	CEFCR,
	98	FRECR,
	99	TSFRCR,
	100	TLFRCR,
	101	CERCR,
	102	CEECR,
103	MAFCR,
104	RTRATE,
f0e81fec NI	105	CSMR,
f0e81fec NI	106	RMII_MII,
4a55530f YS	107
	108	/* TSU Absolute address */
	109	ARSTR,
	110	TSU_CTRST,
	111	TSU_FWEN0,
	112	TSU_FWEN1,
	113	TSU_FCM,
	114	TSU_BSYSL0,
	115	TSU_BSYSL1,
	116	TSU_PRISL0,
	117	TSU_PRISL1,
	118	TSU_FWSL0,
	119	TSU_FWSL1,
	120	TSU_FWSLC,
	121	TSU_QTAG0,
	122	TSU_QTAG1,
	123	TSU_QTAGM0,
	124	TSU_QTAGM1,
	125	TSU_FWSR,
	126	TSU_FWINMK,
	127	TSU_ADQT0,
	128	TSU_ADQT1,
	129	TSU_VTAG0,
	130	TSU_VTAG1,
	131	TSU_ADSBSY,
	132	TSU_TEN,
	133	TSU_POST1,
	134	TSU_POST2,
	135	TSU_POST3,
	136	TSU_POST4,
	137	TSU_ADRH0,
	138	TSU_ADRL0,
	139	TSU_ADRH31,
	140	TSU_ADRL31,
	141
	142	TXNLCR0,
	143	TXALCR0,
	144	RXNLCR0,
	145	RXALCR0,
	146	FWNLCR0,
	147	FWALCR0,
	148	TXNLCR1,
	149	TXALCR1,
	150	RXNLCR1,
	151	RXALCR1,
	152	FWNLCR1,
	153	FWALCR1,
	154
	155	/* This value must be written at last. */
	156	SH_ETH_MAX_REGISTER_OFFSET,
	157	};
	158
	159	static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
	160	[EDSR] = 0x0000,
	161	[EDMR] = 0x0400,
	162	[EDTRR] = 0x0408,
	163	[EDRRR] = 0x0410,
	164	[EESR] = 0x0428,
	165	[EESIPR] = 0x0430,
	166	[TDLAR] = 0x0010,
	167	[TDFAR] = 0x0014,
	168	[TDFXR] = 0x0018,
	169	[TDFFR] = 0x001c,
	170	[RDLAR] = 0x0030,
171	[RDFAR] = 0x0034,
172	[RDFXR] = 0x0038,
173	[RDFFR] = 0x003c,
174	[TRSCER] = 0x0438,
175	[RMFCR] = 0x0440,
176	[TFTR] = 0x0448,
177	[FDR] = 0x0450,
178	[RMCR] = 0x0458,
179	[RPADIR] = 0x0460,
180	[FCFTR] = 0x0468,
f0e81fec	181	[CSMR] = 0x04E4,
4a55530f YS	182
	183	[ECMR] = 0x0500,
	184	[ECSR] = 0x0510,
	185	[ECSIPR] = 0x0518,
	186	[PIR] = 0x0520,
	187	[PSR] = 0x0528,
	188	[PIPR] = 0x052c,
	189	[RFLR] = 0x0508,
	190	[APR] = 0x0554,
	191	[MPR] = 0x0558,
	192	[PFTCR] = 0x055c,
	193	[PFRCR] = 0x0560,
	194	[TPAUSER] = 0x0564,
	195	[GECMR] = 0x05b0,
	196	[BCULR] = 0x05b4,
	197	[MAHR] = 0x05c0,
	198	[MALR] = 0x05c8,
	199	[TROCR] = 0x0700,
	200	[CDCR] = 0x0708,
	201	[LCCR] = 0x0710,
	202	[CEFCR] = 0x0740,
	203	[FRECR] = 0x0748,
	204	[TSFRCR] = 0x0750,
	205	[TLFRCR] = 0x0758,
	206	[RFCR] = 0x0760,
	207	[CERCR] = 0x0768,
	208	[CEECR] = 0x0770,
	209	[MAFCR] = 0x0778,
f0e81fec	210	[RMII_MII] = 0x0790,
4a55530f	211
4986b996	212	[ARSTR] = 0x0000,
4a55530f YS	213	[TSU_CTRST] = 0x0004,
	214	[TSU_FWEN0] = 0x0010,
	215	[TSU_FWEN1] = 0x0014,
	216	[TSU_FCM] = 0x0018,
	217	[TSU_BSYSL0] = 0x0020,
	218	[TSU_BSYSL1] = 0x0024,
	219	[TSU_PRISL0] = 0x0028,
	220	[TSU_PRISL1] = 0x002c,
	221	[TSU_FWSL0] = 0x0030,
	222	[TSU_FWSL1] = 0x0034,
	223	[TSU_FWSLC] = 0x0038,
	224	[TSU_QTAG0] = 0x0040,
	225	[TSU_QTAG1] = 0x0044,
	226	[TSU_FWSR] = 0x0050,
	227	[TSU_FWINMK] = 0x0054,
	228	[TSU_ADQT0] = 0x0048,
	229	[TSU_ADQT1] = 0x004c,
	230	[TSU_VTAG0] = 0x0058,
	231	[TSU_VTAG1] = 0x005c,
	232	[TSU_ADSBSY] = 0x0060,
	233	[TSU_TEN] = 0x0064,
	234	[TSU_POST1] = 0x0070,
	235	[TSU_POST2] = 0x0074,
	236	[TSU_POST3] = 0x0078,
	237	[TSU_POST4] = 0x007c,
	238	[TSU_ADRH0] = 0x0100,
	239	[TSU_ADRL0] = 0x0104,
	240	[TSU_ADRH31] = 0x01f8,
	241	[TSU_ADRL31] = 0x01fc,
	242
	243	[TXNLCR0] = 0x0080,
	244	[TXALCR0] = 0x0084,
	245	[RXNLCR0] = 0x0088,
	246	[RXALCR0] = 0x008c,
	247	[FWNLCR0] = 0x0090,
	248	[FWALCR0] = 0x0094,
	249	[TXNLCR1] = 0x00a0,
	250	[TXALCR1] = 0x00a0,
	251	[RXNLCR1] = 0x00a8,
	252	[RXALCR1] = 0x00ac,
	253	[FWNLCR1] = 0x00b0,
	254	[FWALCR1] = 0x00b4,
	255	};
	256
	257	static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
	258	[ECMR] = 0x0100,
	259	[RFLR] = 0x0108,
	260	[ECSR] = 0x0110,
	261	[ECSIPR] = 0x0118,
	262	[PIR] = 0x0120,
	263	[PSR] = 0x0128,
	264	[RDMLR] = 0x0140,
	265	[IPGR] = 0x0150,
	266	[APR] = 0x0154,
	267	[MPR] = 0x0158,
	268	[TPAUSER] = 0x0164,
	269	[RFCF] = 0x0160,
	270	[TPAUSECR] = 0x0168,
	271	[BCFRR] = 0x016c,
	272	[MAHR] = 0x01c0,
	273	[MALR] = 0x01c8,
	274	[TROCR] = 0x01d0,
	275	[CDCR] = 0x01d4,
	276	[LCCR] = 0x01d8,
277	[CNDCR] = 0x01dc,
278	[CEFCR] = 0x01e4,
279	[FRECR] = 0x01e8,
280	[TSFRCR] = 0x01ec,
281	[TLFRCR] = 0x01f0,
282	[RFCR] = 0x01f4,
283	[MAFCR] = 0x01f8,
284	[RTRATE] = 0x01fc,
285
286	[EDMR] = 0x0000,
287	[EDTRR] = 0x0008,
288	[EDRRR] = 0x0010,
289	[TDLAR] = 0x0018,
290	[RDLAR] = 0x0020,
291	[EESR] = 0x0028,
292	[EESIPR] = 0x0030,
293	[TRSCER] = 0x0038,
294	[RMFCR] = 0x0040,
295	[TFTR] = 0x0048,
296	[FDR] = 0x0050,
297	[RMCR] = 0x0058,
298	[TFUCR] = 0x0064,
299	[RFOCR] = 0x0068,
300	[FCFTR] = 0x0070,
301	[RPADIR] = 0x0078,
302	[TRIMD] = 0x007c,
303	[RBWAR] = 0x00c8,
304	[RDFAR] = 0x00cc,
305	[TBRAR] = 0x00d4,
306	[TDFAR] = 0x00d8,
307	};
308
309	static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
310	[ECMR] = 0x0160,
311	[ECSR] = 0x0164,
312	[ECSIPR] = 0x0168,
313	[PIR] = 0x016c,
314	[MAHR] = 0x0170,
315	[MALR] = 0x0174,
316	[RFLR] = 0x0178,
317	[PSR] = 0x017c,
318	[TROCR] = 0x0180,
319	[CDCR] = 0x0184,
320	[LCCR] = 0x0188,
321	[CNDCR] = 0x018c,
322	[CEFCR] = 0x0194,
323	[FRECR] = 0x0198,
324	[TSFRCR] = 0x019c,
325	[TLFRCR] = 0x01a0,
326	[RFCR] = 0x01a4,
327	[MAFCR] = 0x01a8,
328	[IPGR] = 0x01b4,
329	[APR] = 0x01b8,
330	[MPR] = 0x01bc,
331	[TPAUSER] = 0x01c4,
332	[BCFR] = 0x01cc,
333
4986b996	334	[ARSTR] = 0x0000,
4a55530f YS	335	[TSU_CTRST] = 0x0004,
	336	[TSU_FWEN0] = 0x0010,
	337	[TSU_FWEN1] = 0x0014,
	338	[TSU_FCM] = 0x0018,
	339	[TSU_BSYSL0] = 0x0020,
	340	[TSU_BSYSL1] = 0x0024,
	341	[TSU_PRISL0] = 0x0028,
	342	[TSU_PRISL1] = 0x002c,
	343	[TSU_FWSL0] = 0x0030,
	344	[TSU_FWSL1] = 0x0034,
	345	[TSU_FWSLC] = 0x0038,
	346	[TSU_QTAGM0] = 0x0040,
	347	[TSU_QTAGM1] = 0x0044,
	348	[TSU_ADQT0] = 0x0048,
	349	[TSU_ADQT1] = 0x004c,
	350	[TSU_FWSR] = 0x0050,
	351	[TSU_FWINMK] = 0x0054,
	352	[TSU_ADSBSY] = 0x0060,
	353	[TSU_TEN] = 0x0064,
	354	[TSU_POST1] = 0x0070,
	355	[TSU_POST2] = 0x0074,
	356	[TSU_POST3] = 0x0078,
	357	[TSU_POST4] = 0x007c,
	358
	359	[TXNLCR0] = 0x0080,
	360	[TXALCR0] = 0x0084,
	361	[RXNLCR0] = 0x0088,
	362	[RXALCR0] = 0x008c,
	363	[FWNLCR0] = 0x0090,
	364	[FWALCR0] = 0x0094,
	365	[TXNLCR1] = 0x00a0,
	366	[TXALCR1] = 0x00a0,
	367	[RXNLCR1] = 0x00a8,
	368	[RXALCR1] = 0x00ac,
	369	[FWNLCR1] = 0x00b0,
	370	[FWALCR1] = 0x00b4,
	371
	372	[TSU_ADRH0] = 0x0100,
	373	[TSU_ADRL0] = 0x0104,
	374	[TSU_ADRL31] = 0x01fc,
	375
	376	};
	377
380af9e3	378	/* Driver's parameters */
73a0d907	379	#if defined(CONFIG_CPU_SH4) \|\| defined(CONFIG_ARCH_SHMOBILE)
380af9e3 YS	380	#define SH4_SKB_RX_ALIGN 32
	381	#else
	382	#define SH2_SH3_SKB_RX_ALIGN 2
	383	#endif
	384
b0ca2a21 NI	385	/*
	386	* Register's bits
	387	*/
73a0d907 YS	388	#if defined(CONFIG_CPU_SUBTYPE_SH7734) \|\| defined(CONFIG_CPU_SUBTYPE_SH7763) \|\|\
73a0d907 YS	389	defined(CONFIG_ARCH_R8A7740)
b0ca2a21 NI	390	/* EDSR */
	391	enum EDSR_BIT {
	392	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
	393	};
	394	#define EDSR_ENALL (EDSR_ENT\|EDSR_ENR)
	395
	396	/* GECMR */
	397	enum GECMR_BIT {
	398	GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
	399	};
	400	#endif
86a74ff2 NI	401
	402	/* EDMR */
	403	enum DMAC_M_BIT {
380af9e3	404	EDMR_EL = 0x40, /* Litte endian */
b0ca2a21	405	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
c5ed5368 YS	406	EDMR_SRST_GETHER = 0x03,
c5ed5368 YS	407	EDMR_SRST_ETHER = 0x01,
86a74ff2 NI	408	};
	409
	410	/* EDTRR */
	411	enum DMAC_T_BIT {
c5ed5368 YS	412	EDTRR_TRNS_GETHER = 0x03,
c5ed5368 YS	413	EDTRR_TRNS_ETHER = 0x01,
86a74ff2 NI	414	};
	415
	416	/* EDRRR*/
	417	enum EDRRR_R_BIT {
	418	EDRRR_R = 0x01,
	419	};
	420
	421	/* TPAUSER */
	422	enum TPAUSER_BIT {
	423	TPAUSER_TPAUSE = 0x0000ffff,
	424	TPAUSER_UNLIMITED = 0,
	425	};
	426
	427	/* BCFR */
	428	enum BCFR_BIT {
	429	BCFR_RPAUSE = 0x0000ffff,
	430	BCFR_UNLIMITED = 0,
	431	};
	432
	433	/* PIR */
	434	enum PIR_BIT {
	435	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
	436	};
	437
	438	/* PSR */
	439	enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
	440
	441	/* EESR */
	442	enum EESR_BIT {
380af9e3 YS	443	EESR_TWB1 = 0x80000000,
	444	EESR_TWB = 0x40000000, /* same as TWB0 */
	445	EESR_TC1 = 0x20000000,
	446	EESR_TUC = 0x10000000,
	447	EESR_ROC = 0x08000000,
	448	EESR_TABT = 0x04000000,
	449	EESR_RABT = 0x02000000,
	450	EESR_RFRMER = 0x01000000, /* same as RFCOF */
	451	EESR_ADE = 0x00800000,
	452	EESR_ECI = 0x00400000,
	453	EESR_FTC = 0x00200000, /* same as TC or TC0 */
	454	EESR_TDE = 0x00100000,
	455	EESR_TFE = 0x00080000, /* same as TFUF */
	456	EESR_FRC = 0x00040000, /* same as FR */
	457	EESR_RDE = 0x00020000,
	458	EESR_RFE = 0x00010000,
	459	EESR_CND = 0x00000800,
	460	EESR_DLC = 0x00000400,
	461	EESR_CD = 0x00000200,
	462	EESR_RTO = 0x00000100,
	463	EESR_RMAF = 0x00000080,
	464	EESR_CEEF = 0x00000040,
	465	EESR_CELF = 0x00000020,
	466	EESR_RRF = 0x00000010,
	467	EESR_RTLF = 0x00000008,
	468	EESR_RTSF = 0x00000004,
	469	EESR_PRE = 0x00000002,
	470	EESR_CERF = 0x00000001,
	471	};
	472
	473	#define DEFAULT_TX_CHECK (EESR_FTC \| EESR_CND \| EESR_DLC \| EESR_CD \| \
	474	EESR_RTO)
	475	#define DEFAULT_EESR_ERR_CHECK (EESR_TWB \| EESR_TABT \| EESR_RABT \| \
	476	EESR_RDE \| EESR_RFRMER \| EESR_ADE \| \
	477	EESR_TFE \| EESR_TDE \| EESR_ECI)
	478	#define DEFAULT_TX_ERROR_CHECK (EESR_TWB \| EESR_TABT \| EESR_ADE \| EESR_TDE \| \
	479	EESR_TFE)
86a74ff2 NI	480
	481	/* EESIPR */
	482	enum DMAC_IM_BIT {
	483	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
	484	DMAC_M_RABT = 0x02000000,
	485	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
	486	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
	487	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
	488	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
	489	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
	490	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
	491	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
	492	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
	493	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
	494	DMAC_M_RINT1 = 0x00000001,
	495	};
	496
	497	/* Receive descriptor bit */
	498	enum RD_STS_BIT {
b0ca2a21 NI	499	RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
b0ca2a21 NI	500	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
86a74ff2 NI	501	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
	502	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
	503	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
	504	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
	505	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
	506	RD_RFS1 = 0x00000001,
	507	};
b0ca2a21 NI	508	#define RDF1ST RD_RFP1
	509	#define RDFEND RD_RFP0
	510	#define RD_RFP (RD_RFP1\|RD_RFP0)
86a74ff2 NI	511
	512	/* FCFTR */
	513	enum FCFTR_BIT {
	514	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
	515	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
	516	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
	517	};
380af9e3 YS	518	#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 \| FCFTR_RFF1 \| FCFTR_RFF0)
380af9e3 YS	519	#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 \| FCFTR_RFD1 \| FCFTR_RFD0)
86a74ff2 NI	520
	521	/* Transfer descriptor bit */
	522	enum TD_STS_BIT {
b0ca2a21 NI	523	TD_TACT = 0x80000000,
b0ca2a21 NI	524	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
86a74ff2 NI	525	TD_TFP0 = 0x10000000,
	526	};
	527	#define TDF1ST TD_TFP1
	528	#define TDFEND TD_TFP0
	529	#define TD_TFP (TD_TFP1\|TD_TFP0)
	530
	531	/* RMCR */
380af9e3 YS	532	#define DEFAULT_RMCR_VALUE 0x00000000
380af9e3 YS	533
86a74ff2 NI	534	/* ECMR */
86a74ff2 NI	535	enum FELIC_MODE_BIT {
b0ca2a21 NI	536	ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
b0ca2a21 NI	537	ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
86a74ff2 NI	538	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
	539	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
	540	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
65ac8851	541	ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
380af9e3	542	ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
86a74ff2 NI	543	};
	544
	545	/* ECSR */
	546	enum ECSR_STATUS_BIT {
b0ca2a21	547	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
b0ca2a21	548	ECSR_LCHNG = 0x04,
86a74ff2 NI	549	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
	550	};
	551
380af9e3 YS	552	#define DEFAULT_ECSR_INIT (ECSR_BRCRX \| ECSR_PSRTO \| ECSR_LCHNG \| \
380af9e3 YS	553	ECSR_ICD \| ECSIPR_MPDIP)
b0ca2a21	554
86a74ff2 NI	555	/* ECSIPR */
86a74ff2 NI	556	enum ECSIPR_STATUS_MASK_BIT {
b0ca2a21	557	ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
b0ca2a21	558	ECSIPR_LCHNGIP = 0x04,
86a74ff2 NI	559	ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
	560	};
	561
380af9e3 YS	562	#define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP \| ECSIPR_PSRTOIP \| \
380af9e3 YS	563	ECSIPR_LCHNGIP \| ECSIPR_ICDIP \| ECSIPR_MPDIP)
b0ca2a21	564
86a74ff2 NI	565	/* APR */
	566	enum APR_BIT {
	567	APR_AP = 0x00000001,
	568	};
	569
	570	/* MPR */
	571	enum MPR_BIT {
	572	MPR_MP = 0x00000001,
	573	};
	574
	575	/* TRSCER */
	576	enum DESC_I_BIT {
	577	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
	578	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
	579	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
	580	DESC_I_RINT1 = 0x0001,
	581	};
	582
	583	/* RPADIR */
	584	enum RPADIR_BIT {
	585	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
	586	RPADIR_PADR = 0x0003f,
	587	};
	588
	589	/* FDR */
380af9e3 YS	590	#define DEFAULT_FDR_INIT 0x00000707
380af9e3 YS	591
86a74ff2 NI	592	/* ARSTR */
	593	enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
	594
	595	/* TSU_FWEN0 */
	596	enum TSU_FWEN0_BIT {
	597	TSU_FWEN0_0 = 0x00000001,
	598	};
	599
	600	/* TSU_ADSBSY */
	601	enum TSU_ADSBSY_BIT {
	602	TSU_ADSBSY_0 = 0x00000001,
	603	};
	604
	605	/* TSU_TEN */
	606	enum TSU_TEN_BIT {
	607	TSU_TEN_0 = 0x80000000,
	608	};
	609
	610	/* TSU_FWSL0 */
	611	enum TSU_FWSL0_BIT {
	612	TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
	613	TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
	614	TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
	615	};
	616
	617	/* TSU_FWSLC */
	618	enum TSU_FWSLC_BIT {
	619	TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
	620	TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
	621	TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
	622	TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
	623	TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
	624	};
	625
71cc7c37 YS	626	/* TSU_VTAGn */
	627	#define TSU_VTAG_ENABLE 0x80000000
	628	#define TSU_VTAG_VID_MASK 0x00000fff
	629
86a74ff2 NI	630	/*
	631	* The sh ether Tx buffer descriptors.
	632	* This structure should be 20 bytes.
	633	*/
	634	struct sh_eth_txdesc {
	635	u32 status; /* TD0 */
10b9194f	636	#if defined(__LITTLE_ENDIAN)
86a74ff2 NI	637	u16 pad0; /* TD1 */
	638	u16 buffer_length; /* TD1 */
	639	#else
	640	u16 buffer_length; /* TD1 */
	641	u16 pad0; /* TD1 */
	642	#endif
	643	u32 addr; /* TD2 */
	644	u32 pad1; /* padding data */
71557a37	645	} __attribute__((aligned(2), packed));
86a74ff2 NI	646
	647	/*
	648	* The sh ether Rx buffer descriptors.
	649	* This structure should be 20 bytes.
	650	*/
	651	struct sh_eth_rxdesc {
	652	u32 status; /* RD0 */
10b9194f	653	#if defined(__LITTLE_ENDIAN)
86a74ff2 NI	654	u16 frame_length; /* RD1 */
	655	u16 buffer_length; /* RD1 */
	656	#else
	657	u16 buffer_length; /* RD1 */
	658	u16 frame_length; /* RD1 */
	659	#endif
	660	u32 addr; /* RD2 */
	661	u32 pad0; /* padding data */
71557a37	662	} __attribute__((aligned(2), packed));
86a74ff2	663
380af9e3 YS	664	/* This structure is used by each CPU dependency handling. */
	665	struct sh_eth_cpu_data {
	666	/* optional functions */
	667	void (chip_reset)(struct net_device ndev);
	668	void (set_duplex)(struct net_device ndev);
	669	void (set_rate)(struct net_device ndev);
	670
	671	/* mandatory initialize value */
	672	unsigned long eesipr_value;
	673
	674	/* optional initialize value */
	675	unsigned long ecsr_value;
	676	unsigned long ecsipr_value;
	677	unsigned long fdr_value;
	678	unsigned long fcftr_value;
	679	unsigned long rpadir_value;
	680	unsigned long rmcr_value;
	681
	682	/* interrupt checking mask */
	683	unsigned long tx_check;
	684	unsigned long eesr_err_check;
	685	unsigned long tx_error_check;
	686
	687	/* hardware features */
	688	unsigned no_psr:1; /* EtherC DO NOT have PSR */
	689	unsigned apr:1; /* EtherC have APR */
	690	unsigned mpr:1; /* EtherC have MPR */
	691	unsigned tpauser:1; /* EtherC have TPAUSER */
	692	unsigned bculr:1; /* EtherC have BCULR */
4986b996	693	unsigned tsu:1; /* EtherC have TSU */
380af9e3 YS	694	unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
	695	unsigned rpadir:1; /* E-DMAC have RPADIR */
	696	unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
	697	unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
f0e81fec	698	unsigned hw_crc:1; /* E-DMAC have CSMR */
5e7a76be	699	unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */
380af9e3 YS	700	};
380af9e3 YS	701
86a74ff2	702	struct sh_eth_private {
bcd5149d	703	struct platform_device *pdev;
380af9e3	704	struct sh_eth_cpu_data *cd;
4a55530f	705	const u16 *reg_offset;
ae70644d	706	void __iomem *addr;
4a55530f	707	void __iomem *tsu_addr;
0582b7d1	708	struct bb_info *bitbang;
525b8075 YS	709	u32 num_rx_ring;
525b8075 YS	710	u32 num_tx_ring;
86a74ff2 NI	711	dma_addr_t rx_desc_dma;
	712	dma_addr_t tx_desc_dma;
	713	struct sh_eth_rxdesc *rx_ring;
	714	struct sh_eth_txdesc *tx_ring;
	715	struct sk_buff **rx_skbuff;
	716	struct sk_buff **tx_skbuff;
86a74ff2 NI	717	spinlock_t lock;
	718	u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
	719	u32 cur_tx, dirty_tx;
	720	u32 rx_buf_sz; /* Based on MTU+slack. */
71557a37	721	int edmac_endian;
86a74ff2 NI	722	/* MII transceiver section. */
	723	u32 phy_id; /* PHY ID */
	724	struct mii_bus mii_bus; / MDIO bus control */
	725	struct phy_device phydev; / PHY device control */
	726	enum phy_state link;
e47c9052	727	phy_interface_t phy_interface;
86a74ff2 NI	728	int msg_enable;
	729	int speed;
	730	int duplex;
6743fe6d	731	int port; /* for TSU */
71cc7c37	732	int vlan_num_ids; /* for VLAN tag filter */
4923576b YS	733
	734	unsigned no_ether_link:1;
	735	unsigned ether_link_active_low:1;
86a74ff2 NI	736	};
86a74ff2 NI	737
380af9e3	738	static inline void sh_eth_soft_swap(char *src, int len)
86a74ff2 NI	739	{
	740	#ifdef __LITTLE_ENDIAN__
	741	u32 p = (u32 )src;
	742	u32 *maxp;
	743	maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
	744
	745	for (; p < maxp; p++)
	746	p = swab32(p);
	747	#endif
	748	}
380af9e3	749
4a55530f YS	750	static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
	751	int enum_index)
	752	{
	753	struct sh_eth_private *mdp = netdev_priv(ndev);
	754
ae70644d	755	iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
4a55530f YS	756	}
	757
	758	static inline unsigned long sh_eth_read(struct net_device *ndev,
	759	int enum_index)
	760	{
	761	struct sh_eth_private *mdp = netdev_priv(ndev);
	762
ae70644d	763	return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
4a55530f YS	764	}
4a55530f YS	765
6743fe6d YS	766	static inline void sh_eth_tsu_get_offset(struct sh_eth_private mdp,
	767	int enum_index)
	768	{
	769	return mdp->tsu_addr + mdp->reg_offset[enum_index];
	770	}
	771
4a55530f YS	772	static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
	773	unsigned long data, int enum_index)
	774	{
ae70644d	775	iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
4a55530f YS	776	}
	777
	778	static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
	779	int enum_index)
	780	{
ae70644d	781	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
4a55530f YS	782	}
4a55530f YS	783
380af9e3	784	#endif /* #ifndef __SH_ETH_H__ */