projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: sh_eth: modify a condition of ioremap for TSU
[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.h
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
4a55530f 5 * Copyright (C) 2008-2011 Renesas Solutions Corp.
86a74ff2
NI		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23#ifndef __SH_ETH_H__
24#define __SH_ETH_H__
25
86a74ff2
NI		 26#define CARDNAME "sh-eth"
27#define TX_TIMEOUT (5*HZ)
b0ca2a21
NI		 28#define TX_RING_SIZE 64 /* Tx ring size */
29#define RX_RING_SIZE 64 /* Rx ring size */
86a74ff2
NI		 30#define ETHERSMALL 60
31#define PKT_BUF_SZ 1538
32
4a55530f
YS		 33enum {
34 /* E-DMAC registers */
35 EDSR = 0,
36 EDMR,
37 EDTRR,
38 EDRRR,
39 EESR,
40 EESIPR,
41 TDLAR,
42 TDFAR,
43 TDFXR,
44 TDFFR,
45 RDLAR,
46 RDFAR,
47 RDFXR,
48 RDFFR,
49 TRSCER,
50 RMFCR,
51 TFTR,
52 FDR,
53 RMCR,
54 EDOCR,
55 TFUCR,
56 RFOCR,
57 FCFTR,
58 RPADIR,
59 TRIMD,
60 RBWAR,
61 TBRAR,
62
63 /* Ether registers */
64 ECMR,
65 ECSR,
66 ECSIPR,
67 PIR,
68 PSR,
69 RDMLR,
70 PIPR,
71 RFLR,
72 IPGR,
73 APR,
74 MPR,
75 PFTCR,
76 PFRCR,
77 RFCR,
78 RFCF,
79 TPAUSER,
80 TPAUSECR,
81 BCFR,
82 BCFRR,
83 GECMR,
84 BCULR,
85 MAHR,
86 MALR,
87 TROCR,
88 CDCR,
89 LCCR,
90 CNDCR,
91 CEFCR,
92 FRECR,
93 TSFRCR,
94 TLFRCR,
95 CERCR,
96 CEECR,
97 MAFCR,
98 RTRATE,
99
100 /* TSU Absolute address */
101 ARSTR,
102 TSU_CTRST,
103 TSU_FWEN0,
104 TSU_FWEN1,
105 TSU_FCM,
106 TSU_BSYSL0,
107 TSU_BSYSL1,
108 TSU_PRISL0,
109 TSU_PRISL1,
110 TSU_FWSL0,
111 TSU_FWSL1,
112 TSU_FWSLC,
113 TSU_QTAG0,
114 TSU_QTAG1,
115 TSU_QTAGM0,
116 TSU_QTAGM1,
117 TSU_FWSR,
118 TSU_FWINMK,
119 TSU_ADQT0,
120 TSU_ADQT1,
121 TSU_VTAG0,
122 TSU_VTAG1,
123 TSU_ADSBSY,
124 TSU_TEN,
125 TSU_POST1,
126 TSU_POST2,
127 TSU_POST3,
128 TSU_POST4,
129 TSU_ADRH0,
130 TSU_ADRL0,
131 TSU_ADRH31,
132 TSU_ADRL31,
133
134 TXNLCR0,
135 TXALCR0,
136 RXNLCR0,
137 RXALCR0,
138 FWNLCR0,
139 FWALCR0,
140 TXNLCR1,
141 TXALCR1,
142 RXNLCR1,
143 RXALCR1,
144 FWNLCR1,
145 FWALCR1,
146
147 /* This value must be written at last. */
148 SH_ETH_MAX_REGISTER_OFFSET,
149};
150
151static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
152 [EDSR] = 0x0000,
153 [EDMR] = 0x0400,
154 [EDTRR] = 0x0408,
155 [EDRRR] = 0x0410,
156 [EESR] = 0x0428,
157 [EESIPR] = 0x0430,
158 [TDLAR] = 0x0010,
159 [TDFAR] = 0x0014,
160 [TDFXR] = 0x0018,
161 [TDFFR] = 0x001c,
162 [RDLAR] = 0x0030,
163 [RDFAR] = 0x0034,
164 [RDFXR] = 0x0038,
165 [RDFFR] = 0x003c,
166 [TRSCER] = 0x0438,
167 [RMFCR] = 0x0440,
168 [TFTR] = 0x0448,
169 [FDR] = 0x0450,
170 [RMCR] = 0x0458,
171 [RPADIR] = 0x0460,
172 [FCFTR] = 0x0468,
173
174 [ECMR] = 0x0500,
175 [ECSR] = 0x0510,
176 [ECSIPR] = 0x0518,
177 [PIR] = 0x0520,
178 [PSR] = 0x0528,
179 [PIPR] = 0x052c,
180 [RFLR] = 0x0508,
181 [APR] = 0x0554,
182 [MPR] = 0x0558,
183 [PFTCR] = 0x055c,
184 [PFRCR] = 0x0560,
185 [TPAUSER] = 0x0564,
186 [GECMR] = 0x05b0,
187 [BCULR] = 0x05b4,
188 [MAHR] = 0x05c0,
189 [MALR] = 0x05c8,
190 [TROCR] = 0x0700,
191 [CDCR] = 0x0708,
192 [LCCR] = 0x0710,
193 [CEFCR] = 0x0740,
194 [FRECR] = 0x0748,
195 [TSFRCR] = 0x0750,
196 [TLFRCR] = 0x0758,
197 [RFCR] = 0x0760,
198 [CERCR] = 0x0768,
199 [CEECR] = 0x0770,
200 [MAFCR] = 0x0778,
201
4986b996 202 [ARSTR] = 0x0000,
4a55530f
YS		 203 [TSU_CTRST] = 0x0004,
204 [TSU_FWEN0] = 0x0010,
205 [TSU_FWEN1] = 0x0014,
206 [TSU_FCM] = 0x0018,
207 [TSU_BSYSL0] = 0x0020,
208 [TSU_BSYSL1] = 0x0024,
209 [TSU_PRISL0] = 0x0028,
210 [TSU_PRISL1] = 0x002c,
211 [TSU_FWSL0] = 0x0030,
212 [TSU_FWSL1] = 0x0034,
213 [TSU_FWSLC] = 0x0038,
214 [TSU_QTAG0] = 0x0040,
215 [TSU_QTAG1] = 0x0044,
216 [TSU_FWSR] = 0x0050,
217 [TSU_FWINMK] = 0x0054,
218 [TSU_ADQT0] = 0x0048,
219 [TSU_ADQT1] = 0x004c,
220 [TSU_VTAG0] = 0x0058,
221 [TSU_VTAG1] = 0x005c,
222 [TSU_ADSBSY] = 0x0060,
223 [TSU_TEN] = 0x0064,
224 [TSU_POST1] = 0x0070,
225 [TSU_POST2] = 0x0074,
226 [TSU_POST3] = 0x0078,
227 [TSU_POST4] = 0x007c,
228 [TSU_ADRH0] = 0x0100,
229 [TSU_ADRL0] = 0x0104,
230 [TSU_ADRH31] = 0x01f8,
231 [TSU_ADRL31] = 0x01fc,
232
233 [TXNLCR0] = 0x0080,
234 [TXALCR0] = 0x0084,
235 [RXNLCR0] = 0x0088,
236 [RXALCR0] = 0x008c,
237 [FWNLCR0] = 0x0090,
238 [FWALCR0] = 0x0094,
239 [TXNLCR1] = 0x00a0,
240 [TXALCR1] = 0x00a0,
241 [RXNLCR1] = 0x00a8,
242 [RXALCR1] = 0x00ac,
243 [FWNLCR1] = 0x00b0,
244 [FWALCR1] = 0x00b4,
245};
246
247static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
248 [ECMR] = 0x0100,
249 [RFLR] = 0x0108,
250 [ECSR] = 0x0110,
251 [ECSIPR] = 0x0118,
252 [PIR] = 0x0120,
253 [PSR] = 0x0128,
254 [RDMLR] = 0x0140,
255 [IPGR] = 0x0150,
256 [APR] = 0x0154,
257 [MPR] = 0x0158,
258 [TPAUSER] = 0x0164,
259 [RFCF] = 0x0160,
260 [TPAUSECR] = 0x0168,
261 [BCFRR] = 0x016c,
262 [MAHR] = 0x01c0,
263 [MALR] = 0x01c8,
264 [TROCR] = 0x01d0,
265 [CDCR] = 0x01d4,
266 [LCCR] = 0x01d8,
267 [CNDCR] = 0x01dc,
268 [CEFCR] = 0x01e4,
269 [FRECR] = 0x01e8,
270 [TSFRCR] = 0x01ec,
271 [TLFRCR] = 0x01f0,
272 [RFCR] = 0x01f4,
273 [MAFCR] = 0x01f8,
274 [RTRATE] = 0x01fc,
275
276 [EDMR] = 0x0000,
277 [EDTRR] = 0x0008,
278 [EDRRR] = 0x0010,
279 [TDLAR] = 0x0018,
280 [RDLAR] = 0x0020,
281 [EESR] = 0x0028,
282 [EESIPR] = 0x0030,
283 [TRSCER] = 0x0038,
284 [RMFCR] = 0x0040,
285 [TFTR] = 0x0048,
286 [FDR] = 0x0050,
287 [RMCR] = 0x0058,
288 [TFUCR] = 0x0064,
289 [RFOCR] = 0x0068,
290 [FCFTR] = 0x0070,
291 [RPADIR] = 0x0078,
292 [TRIMD] = 0x007c,
293 [RBWAR] = 0x00c8,
294 [RDFAR] = 0x00cc,
295 [TBRAR] = 0x00d4,
296 [TDFAR] = 0x00d8,
297};
298
299static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
300 [ECMR] = 0x0160,
301 [ECSR] = 0x0164,
302 [ECSIPR] = 0x0168,
303 [PIR] = 0x016c,
304 [MAHR] = 0x0170,
305 [MALR] = 0x0174,
306 [RFLR] = 0x0178,
307 [PSR] = 0x017c,
308 [TROCR] = 0x0180,
309 [CDCR] = 0x0184,
310 [LCCR] = 0x0188,
311 [CNDCR] = 0x018c,
312 [CEFCR] = 0x0194,
313 [FRECR] = 0x0198,
314 [TSFRCR] = 0x019c,
315 [TLFRCR] = 0x01a0,
316 [RFCR] = 0x01a4,
317 [MAFCR] = 0x01a8,
318 [IPGR] = 0x01b4,
319 [APR] = 0x01b8,
320 [MPR] = 0x01bc,
321 [TPAUSER] = 0x01c4,
322 [BCFR] = 0x01cc,
323
4986b996 324 [ARSTR] = 0x0000,
4a55530f
YS		 325 [TSU_CTRST] = 0x0004,
326 [TSU_FWEN0] = 0x0010,
327 [TSU_FWEN1] = 0x0014,
328 [TSU_FCM] = 0x0018,
329 [TSU_BSYSL0] = 0x0020,
330 [TSU_BSYSL1] = 0x0024,
331 [TSU_PRISL0] = 0x0028,
332 [TSU_PRISL1] = 0x002c,
333 [TSU_FWSL0] = 0x0030,
334 [TSU_FWSL1] = 0x0034,
335 [TSU_FWSLC] = 0x0038,
336 [TSU_QTAGM0] = 0x0040,
337 [TSU_QTAGM1] = 0x0044,
338 [TSU_ADQT0] = 0x0048,
339 [TSU_ADQT1] = 0x004c,
340 [TSU_FWSR] = 0x0050,
341 [TSU_FWINMK] = 0x0054,
342 [TSU_ADSBSY] = 0x0060,
343 [TSU_TEN] = 0x0064,
344 [TSU_POST1] = 0x0070,
345 [TSU_POST2] = 0x0074,
346 [TSU_POST3] = 0x0078,
347 [TSU_POST4] = 0x007c,
348
349 [TXNLCR0] = 0x0080,
350 [TXALCR0] = 0x0084,
351 [RXNLCR0] = 0x0088,
352 [RXALCR0] = 0x008c,
353 [FWNLCR0] = 0x0090,
354 [FWALCR0] = 0x0094,
355 [TXNLCR1] = 0x00a0,
356 [TXALCR1] = 0x00a0,
357 [RXNLCR1] = 0x00a8,
358 [RXALCR1] = 0x00ac,
359 [FWNLCR1] = 0x00b0,
360 [FWALCR1] = 0x00b4,
361
362 [TSU_ADRH0] = 0x0100,
363 [TSU_ADRL0] = 0x0104,
364 [TSU_ADRL31] = 0x01fc,
365
366};
367
380af9e3
YS		 368/* Driver's parameters */
369#if defined(CONFIG_CPU_SH4)
370#define SH4_SKB_RX_ALIGN 32
371#else
372#define SH2_SH3_SKB_RX_ALIGN 2
373#endif
374
b0ca2a21
NI		 375/*
376 * Register's bits
377 */
378#ifdef CONFIG_CPU_SUBTYPE_SH7763
379/* EDSR */
380enum EDSR_BIT {
381 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
382};
383#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
384
385/* GECMR */
386enum GECMR_BIT {
387 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
388};
389#endif
86a74ff2
NI		 390
391/* EDMR */
392enum DMAC_M_BIT {
380af9e3 393 EDMR_EL = 0x40, /* Litte endian */
b0ca2a21 394 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
c5ed5368
YS		 395 EDMR_SRST_GETHER = 0x03,
396 EDMR_SRST_ETHER = 0x01,
86a74ff2
NI		 397};
398
399/* EDTRR */
400enum DMAC_T_BIT {
c5ed5368
YS		 401 EDTRR_TRNS_GETHER = 0x03,
402 EDTRR_TRNS_ETHER = 0x01,
86a74ff2
NI		 403};
404
405/* EDRRR*/
406enum EDRRR_R_BIT {
407 EDRRR_R = 0x01,
408};
409
410/* TPAUSER */
411enum TPAUSER_BIT {
412 TPAUSER_TPAUSE = 0x0000ffff,
413 TPAUSER_UNLIMITED = 0,
414};
415
416/* BCFR */
417enum BCFR_BIT {
418 BCFR_RPAUSE = 0x0000ffff,
419 BCFR_UNLIMITED = 0,
420};
421
422/* PIR */
423enum PIR_BIT {
424 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
425};
426
427/* PSR */
428enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
429
430/* EESR */
431enum EESR_BIT {
380af9e3
YS		 432 EESR_TWB1 = 0x80000000,
433 EESR_TWB = 0x40000000, /* same as TWB0 */
434 EESR_TC1 = 0x20000000,
435 EESR_TUC = 0x10000000,
436 EESR_ROC = 0x08000000,
437 EESR_TABT = 0x04000000,
438 EESR_RABT = 0x02000000,
439 EESR_RFRMER = 0x01000000, /* same as RFCOF */
440 EESR_ADE = 0x00800000,
441 EESR_ECI = 0x00400000,
442 EESR_FTC = 0x00200000, /* same as TC or TC0 */
443 EESR_TDE = 0x00100000,
444 EESR_TFE = 0x00080000, /* same as TFUF */
445 EESR_FRC = 0x00040000, /* same as FR */
446 EESR_RDE = 0x00020000,
447 EESR_RFE = 0x00010000,
448 EESR_CND = 0x00000800,
449 EESR_DLC = 0x00000400,
450 EESR_CD = 0x00000200,
451 EESR_RTO = 0x00000100,
452 EESR_RMAF = 0x00000080,
453 EESR_CEEF = 0x00000040,
454 EESR_CELF = 0x00000020,
455 EESR_RRF = 0x00000010,
456 EESR_RTLF = 0x00000008,
457 EESR_RTSF = 0x00000004,
458 EESR_PRE = 0x00000002,
459 EESR_CERF = 0x00000001,
460};
461
462#define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
463 EESR_RTO)
464#define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \
465 EESR_RDE | EESR_RFRMER | EESR_ADE | \
466 EESR_TFE | EESR_TDE | EESR_ECI)
467#define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
468 EESR_TFE)
86a74ff2
NI		 469
470/* EESIPR */
471enum DMAC_IM_BIT {
472 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
473 DMAC_M_RABT = 0x02000000,
474 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
475 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
476 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
477 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
478 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
479 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
480 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
481 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
482 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
483 DMAC_M_RINT1 = 0x00000001,
484};
485
486/* Receive descriptor bit */
487enum RD_STS_BIT {
b0ca2a21
NI		 488 RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
489 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
86a74ff2
NI		 490 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
491 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
492 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
493 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
494 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
495 RD_RFS1 = 0x00000001,
496};
b0ca2a21
NI		 497#define RDF1ST RD_RFP1
498#define RDFEND RD_RFP0
499#define RD_RFP (RD_RFP1|RD_RFP0)
86a74ff2
NI		 500
501/* FCFTR */
502enum FCFTR_BIT {
503 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
504 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
505 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
506};
380af9e3
YS		 507#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
508#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
86a74ff2
NI		 509
510/* Transfer descriptor bit */
511enum TD_STS_BIT {
b0ca2a21
NI		 512 TD_TACT = 0x80000000,
513 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
86a74ff2
NI		 514 TD_TFP0 = 0x10000000,
515};
516#define TDF1ST TD_TFP1
517#define TDFEND TD_TFP0
518#define TD_TFP (TD_TFP1|TD_TFP0)
519
520/* RMCR */
380af9e3
YS		 521#define DEFAULT_RMCR_VALUE 0x00000000
522
86a74ff2
NI		 523/* ECMR */
524enum FELIC_MODE_BIT {
b0ca2a21
NI		 525 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
526 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
86a74ff2
NI		 527 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
528 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
529 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
65ac8851 530 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
380af9e3 531 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
86a74ff2
NI		 532};
533
534/* ECSR */
535enum ECSR_STATUS_BIT {
b0ca2a21 536 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
b0ca2a21 537 ECSR_LCHNG = 0x04,
86a74ff2
NI		 538 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
539};
540
380af9e3
YS		 541#define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
542 ECSR_ICD | ECSIPR_MPDIP)
b0ca2a21 543
86a74ff2
NI		 544/* ECSIPR */
545enum ECSIPR_STATUS_MASK_BIT {
b0ca2a21 546 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
b0ca2a21 547 ECSIPR_LCHNGIP = 0x04,
86a74ff2
NI		 548 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
549};
550
380af9e3
YS		 551#define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
552 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
b0ca2a21 553
86a74ff2
NI		 554/* APR */
555enum APR_BIT {
556 APR_AP = 0x00000001,
557};
558
559/* MPR */
560enum MPR_BIT {
561 MPR_MP = 0x00000001,
562};
563
564/* TRSCER */
565enum DESC_I_BIT {
566 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
567 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
568 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
569 DESC_I_RINT1 = 0x0001,
570};
571
572/* RPADIR */
573enum RPADIR_BIT {
574 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
575 RPADIR_PADR = 0x0003f,
576};
577
578/* FDR */
380af9e3
YS		 579#define DEFAULT_FDR_INIT 0x00000707
580
86a74ff2
NI		 581enum phy_offsets {
582 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
583 PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
584 PHY_16 = 16,
585};
586
587/* PHY_CTRL */
588enum PHY_CTRL_BIT {
589 PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
590 PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
591 PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
592};
593#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
594
595/* PHY_STAT */
596enum PHY_STAT_BIT {
597 PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
598 PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
599 PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
600 PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
601};
602
603/* PHY_ANA */
604enum PHY_ANA_BIT {
605 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
606 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
607 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
b0ca2a21 608 PHY_A_SEL = 0x001e,
86a74ff2
NI		 609};
610/* PHY_ANL */
611enum PHY_ANL_BIT {
612 PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
613 PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
614 PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
615 PHY_L_SEL = 0x001f,
616};
617
618/* PHY_ANE */
619enum PHY_ANE_BIT {
620 PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
621 PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
622};
623
624/* DM9161 */
625enum PHY_16_BIT {
626 PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
627 PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
628 PHY_16_TXselect = 0x0400,
629 PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
630 PHY_16_Force100LNK = 0x0080,
631 PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
632 PHY_16_RPDCTR_EN = 0x0010,
633 PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
634 PHY_16_Sleepmode = 0x0002,
635 PHY_16_RemoteLoopOut = 0x0001,
636};
637
638#define POST_RX 0x08
639#define POST_FW 0x04
640#define POST0_RX (POST_RX)
641#define POST0_FW (POST_FW)
642#define POST1_RX (POST_RX >> 2)
643#define POST1_FW (POST_FW >> 2)
644#define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
645
646/* ARSTR */
647enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
648
649/* TSU_FWEN0 */
650enum TSU_FWEN0_BIT {
651 TSU_FWEN0_0 = 0x00000001,
652};
653
654/* TSU_ADSBSY */
655enum TSU_ADSBSY_BIT {
656 TSU_ADSBSY_0 = 0x00000001,
657};
658
659/* TSU_TEN */
660enum TSU_TEN_BIT {
661 TSU_TEN_0 = 0x80000000,
662};
663
664/* TSU_FWSL0 */
665enum TSU_FWSL0_BIT {
666 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
667 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
668 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
669};
670
671/* TSU_FWSLC */
672enum TSU_FWSLC_BIT {
673 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
674 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
675 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
676 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
677 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
678};
679
680/*
681 * The sh ether Tx buffer descriptors.
682 * This structure should be 20 bytes.
683 */
684struct sh_eth_txdesc {
685 u32 status; /* TD0 */
686#if defined(CONFIG_CPU_LITTLE_ENDIAN)
687 u16 pad0; /* TD1 */
688 u16 buffer_length; /* TD1 */
689#else
690 u16 buffer_length; /* TD1 */
691 u16 pad0; /* TD1 */
692#endif
693 u32 addr; /* TD2 */
694 u32 pad1; /* padding data */
71557a37 695} __attribute__((aligned(2), packed));
86a74ff2
NI		 696
697/*
698 * The sh ether Rx buffer descriptors.
699 * This structure should be 20 bytes.
700 */
701struct sh_eth_rxdesc {
702 u32 status; /* RD0 */
703#if defined(CONFIG_CPU_LITTLE_ENDIAN)
704 u16 frame_length; /* RD1 */
705 u16 buffer_length; /* RD1 */
706#else
707 u16 buffer_length; /* RD1 */
708 u16 frame_length; /* RD1 */
709#endif
710 u32 addr; /* RD2 */
711 u32 pad0; /* padding data */
71557a37 712} __attribute__((aligned(2), packed));
86a74ff2 713
380af9e3
YS		 714/* This structure is used by each CPU dependency handling. */
715struct sh_eth_cpu_data {
716 /* optional functions */
717 void (*chip_reset)(struct net_device *ndev);
718 void (*set_duplex)(struct net_device *ndev);
719 void (*set_rate)(struct net_device *ndev);
720
721 /* mandatory initialize value */
722 unsigned long eesipr_value;
723
724 /* optional initialize value */
725 unsigned long ecsr_value;
726 unsigned long ecsipr_value;
727 unsigned long fdr_value;
728 unsigned long fcftr_value;
729 unsigned long rpadir_value;
730 unsigned long rmcr_value;
731
732 /* interrupt checking mask */
733 unsigned long tx_check;
734 unsigned long eesr_err_check;
735 unsigned long tx_error_check;
736
737 /* hardware features */
738 unsigned no_psr:1; /* EtherC DO NOT have PSR */
739 unsigned apr:1; /* EtherC have APR */
740 unsigned mpr:1; /* EtherC have MPR */
741 unsigned tpauser:1; /* EtherC have TPAUSER */
742 unsigned bculr:1; /* EtherC have BCULR */
4986b996 743 unsigned tsu:1; /* EtherC have TSU */
380af9e3
YS		 744 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
745 unsigned rpadir:1; /* E-DMAC have RPADIR */
746 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
747 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
748};
749
86a74ff2 750struct sh_eth_private {
bcd5149d 751 struct platform_device *pdev;
380af9e3 752 struct sh_eth_cpu_data *cd;
4a55530f 753 const u16 *reg_offset;
ae70644d 754 void __iomem *addr;
4a55530f 755 void __iomem *tsu_addr;
86a74ff2
NI		 756 dma_addr_t rx_desc_dma;
757 dma_addr_t tx_desc_dma;
758 struct sh_eth_rxdesc *rx_ring;
759 struct sh_eth_txdesc *tx_ring;
760 struct sk_buff **rx_skbuff;
761 struct sk_buff **tx_skbuff;
86a74ff2
NI		 762 struct timer_list timer;
763 spinlock_t lock;
764 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
765 u32 cur_tx, dirty_tx;
766 u32 rx_buf_sz; /* Based on MTU+slack. */
71557a37 767 int edmac_endian;
86a74ff2
NI		 768 /* MII transceiver section. */
769 u32 phy_id; /* PHY ID */
770 struct mii_bus *mii_bus; /* MDIO bus control */
771 struct phy_device *phydev; /* PHY device control */
772 enum phy_state link;
e47c9052 773 phy_interface_t phy_interface;
86a74ff2
NI		 774 int msg_enable;
775 int speed;
776 int duplex;
777 u32 rx_int_var, tx_int_var; /* interrupt control variables */
778 char post_rx; /* POST receive */
779 char post_fw; /* POST forward */
780 struct net_device_stats tsu_stats; /* TSU forward status */
4923576b
YS		 781
782 unsigned no_ether_link:1;
783 unsigned ether_link_active_low:1;
86a74ff2
NI		 784};
785
380af9e3 786static inline void sh_eth_soft_swap(char *src, int len)
86a74ff2
NI		 787{
788#ifdef __LITTLE_ENDIAN__
789 u32 *p = (u32 *)src;
790 u32 *maxp;
791 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
792
793 for (; p < maxp; p++)
794 *p = swab32(*p);
795#endif
796}
380af9e3 797
4a55530f
YS		 798static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
799 int enum_index)
800{
801 struct sh_eth_private *mdp = netdev_priv(ndev);
802
ae70644d 803 iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
4a55530f
YS		 804}
805
806static inline unsigned long sh_eth_read(struct net_device *ndev,
807 int enum_index)
808{
809 struct sh_eth_private *mdp = netdev_priv(ndev);
810
ae70644d 811 return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
4a55530f
YS		 812}
813
814static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
815 unsigned long data, int enum_index)
816{
ae70644d 817 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
4a55530f
YS		 818}
819
820static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
821 int enum_index)
822{
ae70644d 823 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
4a55530f
YS		 824}
825
380af9e3 826#endif /* #ifndef __SH_ETH_H__ */
Linux kernel - Deliverables
This page took 0.72798 seconds and 5 git commands to generate.