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sfc: allow ethtool selftest and MC reboot to complete on an unprivileged function
[deliverable/linux.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
822b96f8
DP		 53struct efx_ef10_dev_addr {
54 u8 addr[ETH_ALEN];
55 u16 id;
56};
57
8127d661
BH		 58struct efx_ef10_filter_table {
59/* The RX match field masks supported by this fw & hw, in order of priority */
60 enum efx_filter_match_flags rx_match_flags[
61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
62 unsigned int rx_match_count;
63
64 struct {
65 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 66/* BUSY flag indicates that an update is in progress. AUTO_OLD is
67 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 68 */
69#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 70#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 71#define EFX_EF10_FILTER_FLAGS 3UL
72 u64 handle; /* firmware handle */
73 } *entry;
74 wait_queue_head_t waitq;
75/* Shadow of net_device address lists, guarded by mac_lock */
b59e6ef8
BH		 76#define EFX_EF10_FILTER_DEV_UC_MAX 32
77#define EFX_EF10_FILTER_DEV_MC_MAX 256
822b96f8
DP		 78 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
79 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 80 int dev_uc_count;
81 int dev_mc_count;
82/* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */
83 u16 ucdef_id;
84 u16 bcast_id;
85 u16 mcdef_id;
8127d661
BH		 86};
87
88/* An arbitrary search limit for the software hash table */
89#define EFX_EF10_FILTER_SEARCH_LIMIT 200
90
8127d661
BH		 91static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
92static void efx_ef10_filter_table_remove(struct efx_nic *efx);
93
94static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
95{
96 efx_dword_t reg;
97
98 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
99 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
100 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
101}
102
103static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
104{
02246a7f
SS		 105 int bar;
106
107 bar = efx->type->mem_bar;
108 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 109}
110
7a186f47
DP		 111static bool efx_ef10_is_vf(struct efx_nic *efx)
112{
113 return efx->type->is_vf;
114}
115
1cd9ecbb
DP		 116static int efx_ef10_get_pf_index(struct efx_nic *efx)
117{
118 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
119 struct efx_ef10_nic_data *nic_data = efx->nic_data;
120 size_t outlen;
121 int rc;
122
123 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
124 sizeof(outbuf), &outlen);
125 if (rc)
126 return rc;
127 if (outlen < sizeof(outbuf))
128 return -EIO;
129
130 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
131 return 0;
132}
133
88a37de6
SS		 134#ifdef CONFIG_SFC_SRIOV
135static int efx_ef10_get_vf_index(struct efx_nic *efx)
136{
137 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
138 struct efx_ef10_nic_data *nic_data = efx->nic_data;
139 size_t outlen;
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
143 sizeof(outbuf), &outlen);
144 if (rc)
145 return rc;
146 if (outlen < sizeof(outbuf))
147 return -EIO;
148
149 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
150 return 0;
151}
152#endif
153
e5a2538a 154static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661
BH		 155{
156 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
157 struct efx_ef10_nic_data *nic_data = efx->nic_data;
158 size_t outlen;
159 int rc;
160
161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
162
163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
164 outbuf, sizeof(outbuf), &outlen);
165 if (rc)
166 return rc;
e5a2538a
BH		 167 if (outlen < sizeof(outbuf)) {
168 netif_err(efx, drv, efx->net_dev,
169 "unable to read datapath firmware capabilities\n");
170 return -EIO;
171 }
172
173 nic_data->datapath_caps =
174 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 175
8d9f9dd4
DP		 176 /* record the DPCPU firmware IDs to determine VEB vswitching support.
177 */
178 nic_data->rx_dpcpu_fw_id =
179 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
180 nic_data->tx_dpcpu_fw_id =
181 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
182
e5a2538a
BH		 183 if (!(nic_data->datapath_caps &
184 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
185 netif_err(efx, drv, efx->net_dev,
186 "current firmware does not support TSO\n");
187 return -ENODEV;
188 }
189
190 if (!(nic_data->datapath_caps &
191 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
192 netif_err(efx, probe, efx->net_dev,
193 "current firmware does not support an RX prefix\n");
194 return -ENODEV;
8127d661
BH		 195 }
196
197 return 0;
198}
199
200static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
201{
202 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
203 int rc;
204
205 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
206 outbuf, sizeof(outbuf), NULL);
207 if (rc)
208 return rc;
209 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
210 return rc > 0 ? rc : -ERANGE;
211}
212
0d5e0fbb 213static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 214{
215 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
216 size_t outlen;
217 int rc;
218
219 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
220
221 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
222 outbuf, sizeof(outbuf), &outlen);
223 if (rc)
224 return rc;
225 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
226 return -EIO;
227
cd84ff4d
EC		 228 ether_addr_copy(mac_address,
229 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 230 return 0;
231}
232
0d5e0fbb
DP		 233static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
234{
235 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
236 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
237 size_t outlen;
238 int num_addrs, rc;
239
240 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
241 EVB_PORT_ID_ASSIGNED);
242 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
243 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
244
245 if (rc)
246 return rc;
247 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
248 return -EIO;
249
250 num_addrs = MCDI_DWORD(outbuf,
251 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
252
253 WARN_ON(num_addrs != 1);
254
255 ether_addr_copy(mac_address,
256 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
257
258 return 0;
259}
260
0f5c0845
SS		 261static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
262 struct device_attribute *attr,
263 char *buf)
264{
265 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
266
267 return sprintf(buf, "%d\n",
268 ((efx->mcdi->fn_flags) &
269 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
270 ? 1 : 0);
271}
272
273static ssize_t efx_ef10_show_primary_flag(struct device *dev,
274 struct device_attribute *attr,
275 char *buf)
276{
277 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
278
279 return sprintf(buf, "%d\n",
280 ((efx->mcdi->fn_flags) &
281 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
282 ? 1 : 0);
283}
284
285static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
286 NULL);
287static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
288
8127d661
BH		 289static int efx_ef10_probe(struct efx_nic *efx)
290{
291 struct efx_ef10_nic_data *nic_data;
8be41320 292 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 293 int i, rc;
294
aa3930ee
BH		 295 /* We can have one VI for each 8K region. However, until we
296 * use TX option descriptors we need two TX queues per channel.
8127d661
BH		 297 */
298 efx->max_channels =
299 min_t(unsigned int,
300 EFX_MAX_CHANNELS,
02246a7f 301 efx_ef10_mem_map_size(efx) /
8127d661 302 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
9fd3d3a4
EC		 303 if (WARN_ON(efx->max_channels == 0))
304 return -EIO;
8127d661
BH		 305
306 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
307 if (!nic_data)
308 return -ENOMEM;
309 efx->nic_data = nic_data;
310
75aba2a5
EC		 311 /* we assume later that we can copy from this buffer in dwords */
312 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
313
8127d661
BH		 314 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
315 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
316 if (rc)
317 goto fail1;
318
319 /* Get the MC's warm boot count. In case it's rebooting right
320 * now, be prepared to retry.
321 */
322 i = 0;
323 for (;;) {
324 rc = efx_ef10_get_warm_boot_count(efx);
325 if (rc >= 0)
326 break;
327 if (++i == 5)
328 goto fail2;
329 ssleep(1);
330 }
331 nic_data->warm_boot_count = rc;
332
333 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
334
45b2449e
DP		 335 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
336
8127d661
BH		 337 /* In case we're recovering from a crash (kexec), we want to
338 * cancel any outstanding request by the previous user of this
339 * function. We send a special message using the least
340 * significant bits of the 'high' (doorbell) register.
341 */
342 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
343
344 rc = efx_mcdi_init(efx);
345 if (rc)
346 goto fail2;
347
348 /* Reset (most) configuration for this function */
349 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
350 if (rc)
351 goto fail3;
352
353 /* Enable event logging */
354 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
355 if (rc)
356 goto fail3;
357
0f5c0845
SS		 358 rc = device_create_file(&efx->pci_dev->dev,
359 &dev_attr_link_control_flag);
1cd9ecbb
DP		 360 if (rc)
361 goto fail3;
362
0f5c0845
SS		 363 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
364 if (rc)
365 goto fail4;
366
367 rc = efx_ef10_get_pf_index(efx);
368 if (rc)
369 goto fail5;
370
e5a2538a 371 rc = efx_ef10_init_datapath_caps(efx);
8127d661 372 if (rc < 0)
0f5c0845 373 goto fail5;
8127d661
BH		 374
375 efx->rx_packet_len_offset =
376 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
377
8127d661
BH		 378 rc = efx_mcdi_port_get_number(efx);
379 if (rc < 0)
0f5c0845 380 goto fail5;
8127d661 381 efx->port_num = rc;
8be41320 382 net_dev->dev_port = rc;
8127d661 383
0d5e0fbb 384 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 385 if (rc)
0f5c0845 386 goto fail5;
8127d661
BH		 387
388 rc = efx_ef10_get_sysclk_freq(efx);
389 if (rc < 0)
0f5c0845 390 goto fail5;
8127d661
BH		 391 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
392
267d9d73
EC		 393 /* Check whether firmware supports bug 35388 workaround.
394 * First try to enable it, then if we get EPERM, just
395 * ask if it's already enabled
396 */
34ccfe6f 397 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
c9012e00 398 if (rc == 0) {
8127d661 399 nic_data->workaround_35388 = true;
c9012e00 400 } else if (rc == -EPERM) {
267d9d73
EC		 401 unsigned int enabled;
402
403 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
404 if (rc)
405 goto fail3;
406 nic_data->workaround_35388 = enabled &
407 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
c9012e00 408 } else if (rc != -ENOSYS && rc != -ENOENT) {
0f5c0845 409 goto fail5;
c9012e00 410 }
8127d661
BH		 411 netif_dbg(efx, probe, efx->net_dev,
412 "workaround for bug 35388 is %sabled\n",
413 nic_data->workaround_35388 ? "en" : "dis");
414
415 rc = efx_mcdi_mon_probe(efx);
267d9d73 416 if (rc && rc != -EPERM)
0f5c0845 417 goto fail5;
8127d661 418
9aecda95
BH		 419 efx_ptp_probe(efx, NULL);
420
1d051e00
SS		 421#ifdef CONFIG_SFC_SRIOV
422 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
423 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
424 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
425
426 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
427 } else
428#endif
429 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
430
8127d661
BH		 431 return 0;
432
0f5c0845
SS		 433fail5:
434 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
435fail4:
436 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661
BH		 437fail3:
438 efx_mcdi_fini(efx);
439fail2:
440 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
441fail1:
442 kfree(nic_data);
443 efx->nic_data = NULL;
444 return rc;
445}
446
447static int efx_ef10_free_vis(struct efx_nic *efx)
448{
aa09a3da 449 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 450 size_t outlen;
451 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
452 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 453
454 /* -EALREADY means nothing to free, so ignore */
455 if (rc == -EALREADY)
456 rc = 0;
1e0b8120
EC		 457 if (rc)
458 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
459 rc);
8127d661
BH		 460 return rc;
461}
462
183233be
BH		 463#ifdef EFX_USE_PIO
464
465static void efx_ef10_free_piobufs(struct efx_nic *efx)
466{
467 struct efx_ef10_nic_data *nic_data = efx->nic_data;
468 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
469 unsigned int i;
470 int rc;
471
472 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
473
474 for (i = 0; i < nic_data->n_piobufs; i++) {
475 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
476 nic_data->piobuf_handle[i]);
477 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
478 NULL, 0, NULL);
479 WARN_ON(rc);
480 }
481
482 nic_data->n_piobufs = 0;
483}
484
485static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
486{
487 struct efx_ef10_nic_data *nic_data = efx->nic_data;
488 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
489 unsigned int i;
490 size_t outlen;
491 int rc = 0;
492
493 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
494
495 for (i = 0; i < n; i++) {
496 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
497 outbuf, sizeof(outbuf), &outlen);
498 if (rc)
499 break;
500 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
501 rc = -EIO;
502 break;
503 }
504 nic_data->piobuf_handle[i] =
505 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
506 netif_dbg(efx, probe, efx->net_dev,
507 "allocated PIO buffer %u handle %x\n", i,
508 nic_data->piobuf_handle[i]);
509 }
510
511 nic_data->n_piobufs = i;
512 if (rc)
513 efx_ef10_free_piobufs(efx);
514 return rc;
515}
516
517static int efx_ef10_link_piobufs(struct efx_nic *efx)
518{
519 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 520 _MCDI_DECLARE_BUF(inbuf,
521 max(MC_CMD_LINK_PIOBUF_IN_LEN,
522 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 523 struct efx_channel *channel;
524 struct efx_tx_queue *tx_queue;
525 unsigned int offset, index;
526 int rc;
527
528 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
529 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
530
aa09a3da
JC		 531 memset(inbuf, 0, sizeof(inbuf));
532
183233be
BH		 533 /* Link a buffer to each VI in the write-combining mapping */
534 for (index = 0; index < nic_data->n_piobufs; ++index) {
535 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
536 nic_data->piobuf_handle[index]);
537 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
538 nic_data->pio_write_vi_base + index);
539 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
540 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
541 NULL, 0, NULL);
542 if (rc) {
543 netif_err(efx, drv, efx->net_dev,
544 "failed to link VI %u to PIO buffer %u (%d)\n",
545 nic_data->pio_write_vi_base + index, index,
546 rc);
547 goto fail;
548 }
549 netif_dbg(efx, probe, efx->net_dev,
550 "linked VI %u to PIO buffer %u\n",
551 nic_data->pio_write_vi_base + index, index);
552 }
553
554 /* Link a buffer to each TX queue */
555 efx_for_each_channel(channel, efx) {
556 efx_for_each_channel_tx_queue(tx_queue, channel) {
557 /* We assign the PIO buffers to queues in
558 * reverse order to allow for the following
559 * special case.
560 */
561 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
562 tx_queue->channel->channel - 1) *
563 efx_piobuf_size);
564 index = offset / ER_DZ_TX_PIOBUF_SIZE;
565 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
566
567 /* When the host page size is 4K, the first
568 * host page in the WC mapping may be within
569 * the same VI page as the last TX queue. We
570 * can only link one buffer to each VI.
571 */
572 if (tx_queue->queue == nic_data->pio_write_vi_base) {
573 BUG_ON(index != 0);
574 rc = 0;
575 } else {
576 MCDI_SET_DWORD(inbuf,
577 LINK_PIOBUF_IN_PIOBUF_HANDLE,
578 nic_data->piobuf_handle[index]);
579 MCDI_SET_DWORD(inbuf,
580 LINK_PIOBUF_IN_TXQ_INSTANCE,
581 tx_queue->queue);
582 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
583 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
584 NULL, 0, NULL);
585 }
586
587 if (rc) {
588 /* This is non-fatal; the TX path just
589 * won't use PIO for this queue
590 */
591 netif_err(efx, drv, efx->net_dev,
592 "failed to link VI %u to PIO buffer %u (%d)\n",
593 tx_queue->queue, index, rc);
594 tx_queue->piobuf = NULL;
595 } else {
596 tx_queue->piobuf =
597 nic_data->pio_write_base +
598 index * EFX_VI_PAGE_SIZE + offset;
599 tx_queue->piobuf_offset = offset;
600 netif_dbg(efx, probe, efx->net_dev,
601 "linked VI %u to PIO buffer %u offset %x addr %p\n",
602 tx_queue->queue, index,
603 tx_queue->piobuf_offset,
604 tx_queue->piobuf);
605 }
606 }
607 }
608
609 return 0;
610
611fail:
612 while (index--) {
613 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
614 nic_data->pio_write_vi_base + index);
615 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
616 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
617 NULL, 0, NULL);
618 }
619 return rc;
620}
621
622#else /* !EFX_USE_PIO */
623
624static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
625{
626 return n == 0 ? 0 : -ENOBUFS;
627}
628
629static int efx_ef10_link_piobufs(struct efx_nic *efx)
630{
631 return 0;
632}
633
634static void efx_ef10_free_piobufs(struct efx_nic *efx)
635{
636}
637
638#endif /* EFX_USE_PIO */
639
8127d661
BH		 640static void efx_ef10_remove(struct efx_nic *efx)
641{
642 struct efx_ef10_nic_data *nic_data = efx->nic_data;
643 int rc;
644
f1122a34
SS		 645#ifdef CONFIG_SFC_SRIOV
646 struct efx_ef10_nic_data *nic_data_pf;
647 struct pci_dev *pci_dev_pf;
648 struct efx_nic *efx_pf;
649 struct ef10_vf *vf;
650
651 if (efx->pci_dev->is_virtfn) {
652 pci_dev_pf = efx->pci_dev->physfn;
653 if (pci_dev_pf) {
654 efx_pf = pci_get_drvdata(pci_dev_pf);
655 nic_data_pf = efx_pf->nic_data;
656 vf = nic_data_pf->vf + nic_data->vf_index;
657 vf->efx = NULL;
658 } else
659 netif_info(efx, drv, efx->net_dev,
660 "Could not get the PF id from VF\n");
661 }
662#endif
663
9aecda95
BH		 664 efx_ptp_remove(efx);
665
8127d661
BH		 666 efx_mcdi_mon_remove(efx);
667
8127d661
BH		 668 efx_ef10_rx_free_indir_table(efx);
669
183233be
BH		 670 if (nic_data->wc_membase)
671 iounmap(nic_data->wc_membase);
672
8127d661
BH		 673 rc = efx_ef10_free_vis(efx);
674 WARN_ON(rc != 0);
675
183233be
BH		 676 if (!nic_data->must_restore_piobufs)
677 efx_ef10_free_piobufs(efx);
678
0f5c0845
SS		 679 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
680 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
681
8127d661
BH		 682 efx_mcdi_fini(efx);
683 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
684 kfree(nic_data);
685}
686
88a37de6
SS		 687static int efx_ef10_probe_pf(struct efx_nic *efx)
688{
689 return efx_ef10_probe(efx);
690}
691
7a186f47
DP		 692int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
693{
694 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
695
696 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
697 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
698 NULL, 0, NULL);
699}
700
701int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
702{
703 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
704
705 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
706 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
707 NULL, 0, NULL);
708}
709
710int efx_ef10_vport_add_mac(struct efx_nic *efx,
711 unsigned int port_id, u8 *mac)
712{
713 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
714
715 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
716 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
717
718 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
719 sizeof(inbuf), NULL, 0, NULL);
720}
721
722int efx_ef10_vport_del_mac(struct efx_nic *efx,
723 unsigned int port_id, u8 *mac)
724{
725 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
726
727 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
728 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
729
730 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
731 sizeof(inbuf), NULL, 0, NULL);
732}
733
88a37de6
SS		 734#ifdef CONFIG_SFC_SRIOV
735static int efx_ef10_probe_vf(struct efx_nic *efx)
736{
737 int rc;
6598dad2
DP		 738 struct pci_dev *pci_dev_pf;
739
740 /* If the parent PF has no VF data structure, it doesn't know about this
741 * VF so fail probe. The VF needs to be re-created. This can happen
742 * if the PF driver is unloaded while the VF is assigned to a guest.
743 */
744 pci_dev_pf = efx->pci_dev->physfn;
745 if (pci_dev_pf) {
746 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
747 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
748
749 if (!nic_data_pf->vf) {
750 netif_info(efx, drv, efx->net_dev,
751 "The VF cannot link to its parent PF; "
752 "please destroy and re-create the VF\n");
753 return -EBUSY;
754 }
755 }
88a37de6
SS		 756
757 rc = efx_ef10_probe(efx);
758 if (rc)
759 return rc;
760
761 rc = efx_ef10_get_vf_index(efx);
762 if (rc)
763 goto fail;
764
f1122a34
SS		 765 if (efx->pci_dev->is_virtfn) {
766 if (efx->pci_dev->physfn) {
767 struct efx_nic *efx_pf =
768 pci_get_drvdata(efx->pci_dev->physfn);
769 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
770 struct efx_ef10_nic_data *nic_data = efx->nic_data;
771
772 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 773 nic_data_p->vf[nic_data->vf_index].pci_dev =
774 efx->pci_dev;
f1122a34
SS		 775 } else
776 netif_info(efx, drv, efx->net_dev,
777 "Could not get the PF id from VF\n");
778 }
779
88a37de6
SS		 780 return 0;
781
782fail:
783 efx_ef10_remove(efx);
784 return rc;
785}
786#else
787static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
788{
789 return 0;
790}
791#endif
792
8127d661
BH		 793static int efx_ef10_alloc_vis(struct efx_nic *efx,
794 unsigned int min_vis, unsigned int max_vis)
795{
796 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
797 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
798 struct efx_ef10_nic_data *nic_data = efx->nic_data;
799 size_t outlen;
800 int rc;
801
802 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
803 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
804 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
805 outbuf, sizeof(outbuf), &outlen);
806 if (rc != 0)
807 return rc;
808
809 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
810 return -EIO;
811
812 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
813 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
814
815 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
816 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
817 return 0;
818}
819
183233be
BH		 820/* Note that the failure path of this function does not free
821 * resources, as this will be done by efx_ef10_remove().
822 */
8127d661
BH		 823static int efx_ef10_dimension_resources(struct efx_nic *efx)
824{
183233be
BH		 825 struct efx_ef10_nic_data *nic_data = efx->nic_data;
826 unsigned int uc_mem_map_size, wc_mem_map_size;
827 unsigned int min_vis, pio_write_vi_base, max_vis;
828 void __iomem *membase;
829 int rc;
830
831 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 832
183233be
BH		 833#ifdef EFX_USE_PIO
834 /* Try to allocate PIO buffers if wanted and if the full
835 * number of PIO buffers would be sufficient to allocate one
836 * copy-buffer per TX channel. Failure is non-fatal, as there
837 * are only a small number of PIO buffers shared between all
838 * functions of the controller.
839 */
840 if (efx_piobuf_size != 0 &&
841 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
842 efx->n_tx_channels) {
843 unsigned int n_piobufs =
844 DIV_ROUND_UP(efx->n_tx_channels,
845 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
846
847 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
848 if (rc)
849 netif_err(efx, probe, efx->net_dev,
850 "failed to allocate PIO buffers (%d)\n", rc);
851 else
852 netif_dbg(efx, probe, efx->net_dev,
853 "allocated %u PIO buffers\n", n_piobufs);
854 }
855#else
856 nic_data->n_piobufs = 0;
857#endif
858
859 /* PIO buffers should be mapped with write-combining enabled,
860 * and we want to make single UC and WC mappings rather than
861 * several of each (in fact that's the only option if host
862 * page size is >4K). So we may allocate some extra VIs just
863 * for writing PIO buffers through.
52ad762b
DP		 864 *
865 * The UC mapping contains (min_vis - 1) complete VIs and the
866 * first half of the next VI. Then the WC mapping begins with
867 * the second half of this last VI.
183233be
BH		 868 */
869 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
870 ER_DZ_TX_PIOBUF);
871 if (nic_data->n_piobufs) {
52ad762b
DP		 872 /* pio_write_vi_base rounds down to give the number of complete
873 * VIs inside the UC mapping.
874 */
183233be
BH		 875 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
876 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
877 nic_data->n_piobufs) *
878 EFX_VI_PAGE_SIZE) -
879 uc_mem_map_size);
880 max_vis = pio_write_vi_base + nic_data->n_piobufs;
881 } else {
882 pio_write_vi_base = 0;
883 wc_mem_map_size = 0;
884 max_vis = min_vis;
885 }
886
887 /* In case the last attached driver failed to free VIs, do it now */
888 rc = efx_ef10_free_vis(efx);
889 if (rc != 0)
890 return rc;
891
892 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
893 if (rc != 0)
894 return rc;
895
896 /* If we didn't get enough VIs to map all the PIO buffers, free the
897 * PIO buffers
898 */
899 if (nic_data->n_piobufs &&
900 nic_data->n_allocated_vis <
901 pio_write_vi_base + nic_data->n_piobufs) {
902 netif_dbg(efx, probe, efx->net_dev,
903 "%u VIs are not sufficient to map %u PIO buffers\n",
904 nic_data->n_allocated_vis, nic_data->n_piobufs);
905 efx_ef10_free_piobufs(efx);
906 }
907
908 /* Shrink the original UC mapping of the memory BAR */
909 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
910 if (!membase) {
911 netif_err(efx, probe, efx->net_dev,
912 "could not shrink memory BAR to %x\n",
913 uc_mem_map_size);
914 return -ENOMEM;
915 }
916 iounmap(efx->membase);
917 efx->membase = membase;
918
919 /* Set up the WC mapping if needed */
920 if (wc_mem_map_size) {
921 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
922 uc_mem_map_size,
923 wc_mem_map_size);
924 if (!nic_data->wc_membase) {
925 netif_err(efx, probe, efx->net_dev,
926 "could not allocate WC mapping of size %x\n",
927 wc_mem_map_size);
928 return -ENOMEM;
929 }
930 nic_data->pio_write_vi_base = pio_write_vi_base;
931 nic_data->pio_write_base =
932 nic_data->wc_membase +
933 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
934 uc_mem_map_size);
935
936 rc = efx_ef10_link_piobufs(efx);
937 if (rc)
938 efx_ef10_free_piobufs(efx);
939 }
940
941 netif_dbg(efx, probe, efx->net_dev,
942 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
943 &efx->membase_phys, efx->membase, uc_mem_map_size,
944 nic_data->wc_membase, wc_mem_map_size);
945
946 return 0;
8127d661
BH		 947}
948
949static int efx_ef10_init_nic(struct efx_nic *efx)
950{
951 struct efx_ef10_nic_data *nic_data = efx->nic_data;
952 int rc;
953
a915ccc9
BH		 954 if (nic_data->must_check_datapath_caps) {
955 rc = efx_ef10_init_datapath_caps(efx);
956 if (rc)
957 return rc;
958 nic_data->must_check_datapath_caps = false;
959 }
960
8127d661
BH		 961 if (nic_data->must_realloc_vis) {
962 /* We cannot let the number of VIs change now */
963 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
964 nic_data->n_allocated_vis);
965 if (rc)
966 return rc;
967 nic_data->must_realloc_vis = false;
968 }
969
183233be
BH		 970 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
971 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
972 if (rc == 0) {
973 rc = efx_ef10_link_piobufs(efx);
974 if (rc)
975 efx_ef10_free_piobufs(efx);
976 }
977
978 /* Log an error on failure, but this is non-fatal */
979 if (rc)
980 netif_err(efx, drv, efx->net_dev,
981 "failed to restore PIO buffers (%d)\n", rc);
982 nic_data->must_restore_piobufs = false;
983 }
984
267c0157
JC		 985 /* don't fail init if RSS setup doesn't work */
986 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
987
8127d661
BH		 988 return 0;
989}
990
3e336261
JC		 991static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
992{
993 struct efx_ef10_nic_data *nic_data = efx->nic_data;
994
995 /* All our allocations have been reset */
996 nic_data->must_realloc_vis = true;
997 nic_data->must_restore_filters = true;
998 nic_data->must_restore_piobufs = true;
999 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1000}
1001
087e9025
JC		 1002static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1003{
1004 if (reason == RESET_TYPE_MC_FAILURE)
1005 return RESET_TYPE_DATAPATH;
1006
1007 return efx_mcdi_map_reset_reason(reason);
1008}
1009
8127d661
BH		 1010static int efx_ef10_map_reset_flags(u32 *flags)
1011{
1012 enum {
1013 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1014 ETH_RESET_SHARED_SHIFT),
1015 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1016 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1017 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1018 ETH_RESET_SHARED_SHIFT)
1019 };
1020
1021 /* We assume for now that our PCI function is permitted to
1022 * reset everything.
1023 */
1024
1025 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1026 *flags &= ~EF10_RESET_MC;
1027 return RESET_TYPE_WORLD;
1028 }
1029
1030 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1031 *flags &= ~EF10_RESET_PORT;
1032 return RESET_TYPE_ALL;
1033 }
1034
1035 /* no invisible reset implemented */
1036
1037 return -EINVAL;
1038}
1039
3e336261
JC		 1040static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1041{
1042 int rc = efx_mcdi_reset(efx, reset_type);
1043
27324820
DP		 1044 /* Unprivileged functions return -EPERM, but need to return success
1045 * here so that the datapath is brought back up.
1046 */
1047 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1048 rc = 0;
1049
3e336261
JC		 1050 /* If it was a port reset, trigger reallocation of MC resources.
1051 * Note that on an MC reset nothing needs to be done now because we'll
1052 * detect the MC reset later and handle it then.
e283546c
EC		 1053 * For an FLR, we never get an MC reset event, but the MC has reset all
1054 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1055 */
e283546c
EC		 1056 if ((reset_type == RESET_TYPE_ALL ||
1057 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1058 efx_ef10_reset_mc_allocations(efx);
1059 return rc;
1060}
1061
8127d661
BH		 1062#define EF10_DMA_STAT(ext_name, mcdi_name) \
1063 [EF10_STAT_ ## ext_name] = \
1064 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1065#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1066 [EF10_STAT_ ## int_name] = \
1067 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1068#define EF10_OTHER_STAT(ext_name) \
1069 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1070#define GENERIC_SW_STAT(ext_name) \
1071 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1072
1073static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1074 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1075 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1076 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1077 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1078 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1079 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1080 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1081 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1082 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1083 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1084 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1085 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1086 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1087 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1088 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1089 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1090 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1091 EF10_OTHER_STAT(port_rx_good_bytes),
1092 EF10_OTHER_STAT(port_rx_bad_bytes),
1093 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1094 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1095 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1096 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1097 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1098 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1099 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1100 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1101 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1102 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1103 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1104 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1105 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1106 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1107 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1108 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1109 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1110 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1111 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1112 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1113 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1114 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1115 GENERIC_SW_STAT(rx_nodesc_trunc),
1116 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1117 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1118 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1119 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1120 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1121 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1122 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1123 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1124 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1125 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1126 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1127 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1128 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1129 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1130 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1131 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1132 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1133 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1134 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1135 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1136 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1137 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1138 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1139 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1140 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1141 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1142 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1143 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1144 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1145 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1146 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1147};
1148
e80ca013
DP		 1149#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1150 (1ULL << EF10_STAT_port_tx_packets) | \
1151 (1ULL << EF10_STAT_port_tx_pause) | \
1152 (1ULL << EF10_STAT_port_tx_unicast) | \
1153 (1ULL << EF10_STAT_port_tx_multicast) | \
1154 (1ULL << EF10_STAT_port_tx_broadcast) | \
1155 (1ULL << EF10_STAT_port_rx_bytes) | \
1156 (1ULL << \
1157 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1158 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1159 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1160 (1ULL << EF10_STAT_port_rx_packets) | \
1161 (1ULL << EF10_STAT_port_rx_good) | \
1162 (1ULL << EF10_STAT_port_rx_bad) | \
1163 (1ULL << EF10_STAT_port_rx_pause) | \
1164 (1ULL << EF10_STAT_port_rx_control) | \
1165 (1ULL << EF10_STAT_port_rx_unicast) | \
1166 (1ULL << EF10_STAT_port_rx_multicast) | \
1167 (1ULL << EF10_STAT_port_rx_broadcast) | \
1168 (1ULL << EF10_STAT_port_rx_lt64) | \
1169 (1ULL << EF10_STAT_port_rx_64) | \
1170 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1171 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1172 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1173 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1174 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1175 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1176 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1177 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1178 (1ULL << EF10_STAT_port_rx_overflow) | \
1179 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1180 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1181 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661
BH		 1182
1183/* These statistics are only provided by the 10G MAC. For a 10G/40G
1184 * switchable port we do not expose these because they might not
1185 * include all the packets they should.
1186 */
e80ca013
DP		 1187#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1188 (1ULL << EF10_STAT_port_tx_lt64) | \
1189 (1ULL << EF10_STAT_port_tx_64) | \
1190 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1191 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1192 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1193 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1194 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1195 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1196
1197/* These statistics are only provided by the 40G MAC. For a 10G/40G
1198 * switchable port we do expose these because the errors will otherwise
1199 * be silent.
1200 */
e80ca013
DP		 1201#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1202 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1203
568d7a00
EC		 1204/* These statistics are only provided if the firmware supports the
1205 * capability PM_AND_RXDP_COUNTERS.
1206 */
1207#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1208 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1209 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1210 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1211 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1212 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1213 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1214 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1215 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1216 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1217 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1218 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1219 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1220
4bae913b 1221static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1222{
4bae913b 1223 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1224 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1225 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1226
3c36a2ad
DP		 1227 if (!(efx->mcdi->fn_flags &
1228 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1229 return 0;
1230
8127d661 1231 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
4bae913b 1232 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
8127d661 1233 else
4bae913b 1234 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
568d7a00
EC		 1235
1236 if (nic_data->datapath_caps &
1237 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1238 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1239
4bae913b
EC		 1240 return raw_mask;
1241}
1242
1243static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1244{
d94619cd 1245 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1246 u64 raw_mask[2];
1247
1248 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1249
d94619cd
DP		 1250 /* Only show vadaptor stats when EVB capability is present */
1251 if (nic_data->datapath_caps &
1252 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1253 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1254 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1255 } else {
1256 raw_mask[1] = 0;
1257 }
4bae913b
EC		 1258
1259#if BITS_PER_LONG == 64
3c36a2ad
DP		 1260 mask[0] = raw_mask[0];
1261 mask[1] = raw_mask[1];
4bae913b 1262#else
3c36a2ad
DP		 1263 mask[0] = raw_mask[0] & 0xffffffff;
1264 mask[1] = raw_mask[0] >> 32;
1265 mask[2] = raw_mask[1] & 0xffffffff;
1266 mask[3] = raw_mask[1] >> 32;
4bae913b 1267#endif
8127d661
BH		 1268}
1269
1270static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1271{
4bae913b
EC		 1272 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1273
1274 efx_ef10_get_stat_mask(efx, mask);
8127d661 1275 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1276 mask, names);
8127d661
BH		 1277}
1278
d7788196
DP		 1279static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1280 struct rtnl_link_stats64 *core_stats)
1281{
1282 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1283 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1284 u64 *stats = nic_data->stats;
1285 size_t stats_count = 0, index;
1286
1287 efx_ef10_get_stat_mask(efx, mask);
1288
1289 if (full_stats) {
1290 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1291 if (efx_ef10_stat_desc[index].name) {
1292 *full_stats++ = stats[index];
1293 ++stats_count;
1294 }
1295 }
1296 }
1297
1298 if (core_stats) {
0fc95fca
DP		 1299 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1300 stats[EF10_STAT_rx_multicast] +
1301 stats[EF10_STAT_rx_broadcast];
1302 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1303 stats[EF10_STAT_tx_multicast] +
1304 stats[EF10_STAT_tx_broadcast];
1305 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1306 stats[EF10_STAT_rx_multicast_bytes] +
1307 stats[EF10_STAT_rx_broadcast_bytes];
1308 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1309 stats[EF10_STAT_tx_multicast_bytes] +
1310 stats[EF10_STAT_tx_broadcast_bytes];
1311 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1312 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1313 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1314 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1315 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1316 core_stats->rx_errors = core_stats->rx_crc_errors;
1317 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
d7788196
DP		 1318 }
1319
1320 return stats_count;
1321}
1322
1323static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1324{
1325 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1326 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1327 __le64 generation_start, generation_end;
1328 u64 *stats = nic_data->stats;
1329 __le64 *dma_stats;
1330
4bae913b
EC		 1331 efx_ef10_get_stat_mask(efx, mask);
1332
8127d661
BH		 1333 dma_stats = efx->stats_buffer.addr;
1334 nic_data = efx->nic_data;
1335
1336 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1337 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1338 return 0;
1339 rmb();
4bae913b 1340 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1341 stats, efx->stats_buffer.addr, false);
d546a893 1342 rmb();
8127d661
BH		 1343 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1344 if (generation_end != generation_start)
1345 return -EAGAIN;
1346
1347 /* Update derived statistics */
e80ca013
DP		 1348 efx_nic_fix_nodesc_drop_stat(efx,
1349 &stats[EF10_STAT_port_rx_nodesc_drops]);
1350 stats[EF10_STAT_port_rx_good_bytes] =
1351 stats[EF10_STAT_port_rx_bytes] -
1352 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1353 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1354 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1355 efx_update_sw_stats(efx, stats);
8127d661
BH		 1356 return 0;
1357}
1358
1359
d7788196
DP		 1360static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1361 struct rtnl_link_stats64 *core_stats)
8127d661 1362{
8127d661
BH		 1363 int retry;
1364
1365 /* If we're unlucky enough to read statistics during the DMA, wait
1366 * up to 10ms for it to finish (typically takes <500us)
1367 */
1368 for (retry = 0; retry < 100; ++retry) {
d7788196 1369 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1370 break;
1371 udelay(100);
1372 }
1373
d7788196
DP		 1374 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1375}
8127d661 1376
d7788196
DP		 1377static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1378{
1379 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1380 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1381 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1382 __le64 generation_start, generation_end;
1383 u64 *stats = nic_data->stats;
1384 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1385 struct efx_buffer stats_buf;
1386 __le64 *dma_stats;
1387 int rc;
1388
f00bf230
DP		 1389 spin_unlock_bh(&efx->stats_lock);
1390
1391 if (in_interrupt()) {
1392 /* If in atomic context, cannot update stats. Just update the
1393 * software stats and return so the caller can continue.
1394 */
1395 spin_lock_bh(&efx->stats_lock);
1396 efx_update_sw_stats(efx, stats);
1397 return 0;
1398 }
1399
d7788196
DP		 1400 efx_ef10_get_stat_mask(efx, mask);
1401
1402 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1403 if (rc) {
1404 spin_lock_bh(&efx->stats_lock);
d7788196 1405 return rc;
f00bf230 1406 }
d7788196
DP		 1407
1408 dma_stats = stats_buf.addr;
1409 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1410
1411 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1412 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1413 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1414 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1415 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1416
6dd4859b
DP		 1417 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1418 NULL, 0, NULL);
d7788196 1419 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1420 if (rc) {
1421 /* Expect ENOENT if DMA queues have not been set up */
1422 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1423 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1424 sizeof(inbuf), NULL, 0, rc);
d7788196 1425 goto out;
6dd4859b 1426 }
d7788196
DP		 1427
1428 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1429 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1430 WARN_ON_ONCE(1);
d7788196 1431 goto out;
0fc95fca 1432 }
d7788196
DP		 1433 rmb();
1434 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1435 stats, stats_buf.addr, false);
1436 rmb();
1437 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1438 if (generation_end != generation_start) {
1439 rc = -EAGAIN;
1440 goto out;
8127d661
BH		 1441 }
1442
d7788196
DP		 1443 efx_update_sw_stats(efx, stats);
1444out:
1445 efx_nic_free_buffer(efx, &stats_buf);
1446 return rc;
1447}
1448
1449static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1450 struct rtnl_link_stats64 *core_stats)
1451{
1452 if (efx_ef10_try_update_nic_stats_vf(efx))
1453 return 0;
1454
1455 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1456}
1457
1458static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1459{
1460 struct efx_nic *efx = channel->efx;
1461 unsigned int mode, value;
1462 efx_dword_t timer_cmd;
1463
1464 if (channel->irq_moderation) {
1465 mode = 3;
1466 value = channel->irq_moderation - 1;
1467 } else {
1468 mode = 0;
1469 value = 0;
1470 }
1471
1472 if (EFX_EF10_WORKAROUND_35388(efx)) {
1473 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1474 EFE_DD_EVQ_IND_TIMER_FLAGS,
1475 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1476 ERF_DD_EVQ_IND_TIMER_VAL, value);
1477 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1478 channel->channel);
1479 } else {
1480 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1481 ERF_DZ_TC_TIMER_VAL, value);
1482 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1483 channel->channel);
1484 }
1485}
1486
02246a7f
SS		 1487static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1488 struct ethtool_wolinfo *wol) {}
1489
1490static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1491{
1492 return -EOPNOTSUPP;
1493}
1494
8127d661
BH		 1495static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1496{
1497 wol->supported = 0;
1498 wol->wolopts = 0;
1499 memset(&wol->sopass, 0, sizeof(wol->sopass));
1500}
1501
1502static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1503{
1504 if (type != 0)
1505 return -EINVAL;
1506 return 0;
1507}
1508
1509static void efx_ef10_mcdi_request(struct efx_nic *efx,
1510 const efx_dword_t *hdr, size_t hdr_len,
1511 const efx_dword_t *sdu, size_t sdu_len)
1512{
1513 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1514 u8 *pdu = nic_data->mcdi_buf.addr;
1515
1516 memcpy(pdu, hdr, hdr_len);
1517 memcpy(pdu + hdr_len, sdu, sdu_len);
1518 wmb();
1519
1520 /* The hardware provides 'low' and 'high' (doorbell) registers
1521 * for passing the 64-bit address of an MCDI request to
1522 * firmware. However the dwords are swapped by firmware. The
1523 * least significant bits of the doorbell are then 0 for all
1524 * MCDI requests due to alignment.
1525 */
1526 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1527 ER_DZ_MC_DB_LWRD);
1528 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1529 ER_DZ_MC_DB_HWRD);
1530}
1531
1532static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1533{
1534 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1535 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1536
1537 rmb();
1538 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1539}
1540
1541static void
1542efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1543 size_t offset, size_t outlen)
1544{
1545 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1546 const u8 *pdu = nic_data->mcdi_buf.addr;
1547
1548 memcpy(outbuf, pdu + offset, outlen);
1549}
1550
1551static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1552{
1553 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1554 int rc;
1555
1556 rc = efx_ef10_get_warm_boot_count(efx);
1557 if (rc < 0) {
1558 /* The firmware is presumably in the process of
1559 * rebooting. However, we are supposed to report each
1560 * reboot just once, so we must only do that once we
1561 * can read and store the updated warm boot count.
1562 */
1563 return 0;
1564 }
1565
1566 if (rc == nic_data->warm_boot_count)
1567 return 0;
1568
1569 nic_data->warm_boot_count = rc;
1570
1571 /* All our allocations have been reset */
3e336261 1572 efx_ef10_reset_mc_allocations(efx);
8127d661 1573
6d8aaaf6
DP		 1574 /* Driver-created vswitches and vports must be re-created */
1575 nic_data->must_probe_vswitching = true;
1576 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1577
a915ccc9
BH		 1578 /* The datapath firmware might have been changed */
1579 nic_data->must_check_datapath_caps = true;
1580
869070c5
BH		 1581 /* MAC statistics have been cleared on the NIC; clear the local
1582 * statistic that we update with efx_update_diff_stat().
1583 */
e80ca013 1584 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
869070c5 1585
8127d661
BH		 1586 return -EIO;
1587}
1588
1589/* Handle an MSI interrupt
1590 *
1591 * Handle an MSI hardware interrupt. This routine schedules event
1592 * queue processing. No interrupt acknowledgement cycle is necessary.
1593 * Also, we never need to check that the interrupt is for us, since
1594 * MSI interrupts cannot be shared.
1595 */
1596static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1597{
1598 struct efx_msi_context *context = dev_id;
1599 struct efx_nic *efx = context->efx;
1600
1601 netif_vdbg(efx, intr, efx->net_dev,
1602 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1603
1604 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1605 /* Note test interrupts */
1606 if (context->index == efx->irq_level)
1607 efx->last_irq_cpu = raw_smp_processor_id();
1608
1609 /* Schedule processing of the channel */
1610 efx_schedule_channel_irq(efx->channel[context->index]);
1611 }
1612
1613 return IRQ_HANDLED;
1614}
1615
1616static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1617{
1618 struct efx_nic *efx = dev_id;
1619 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1620 struct efx_channel *channel;
1621 efx_dword_t reg;
1622 u32 queues;
1623
1624 /* Read the ISR which also ACKs the interrupts */
1625 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1626 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1627
1628 if (queues == 0)
1629 return IRQ_NONE;
1630
1631 if (likely(soft_enabled)) {
1632 /* Note test interrupts */
1633 if (queues & (1U << efx->irq_level))
1634 efx->last_irq_cpu = raw_smp_processor_id();
1635
1636 efx_for_each_channel(channel, efx) {
1637 if (queues & 1)
1638 efx_schedule_channel_irq(channel);
1639 queues >>= 1;
1640 }
1641 }
1642
1643 netif_vdbg(efx, intr, efx->net_dev,
1644 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1645 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1646
1647 return IRQ_HANDLED;
1648}
1649
1650static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1651{
1652 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1653
1654 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1655
1656 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1657 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1658 inbuf, sizeof(inbuf), NULL, 0, NULL);
1659}
1660
1661static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1662{
1663 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1664 (tx_queue->ptr_mask + 1) *
1665 sizeof(efx_qword_t),
1666 GFP_KERNEL);
1667}
1668
1669/* This writes to the TX_DESC_WPTR and also pushes data */
1670static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1671 const efx_qword_t *txd)
1672{
1673 unsigned int write_ptr;
1674 efx_oword_t reg;
1675
1676 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1677 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1678 reg.qword[0] = *txd;
1679 efx_writeo_page(tx_queue->efx, &reg,
1680 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1681}
1682
1683static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1684{
1685 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1686 EFX_BUF_SIZE));
8127d661
BH		 1687 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1688 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1689 struct efx_channel *channel = tx_queue->channel;
1690 struct efx_nic *efx = tx_queue->efx;
45b2449e 1691 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 1692 size_t inlen;
8127d661
BH		 1693 dma_addr_t dma_addr;
1694 efx_qword_t *txd;
1695 int rc;
1696 int i;
aa09a3da 1697 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661
BH		 1698
1699 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1700 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1701 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1702 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1703 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1704 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1705 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1706 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 1707 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 1708
1709 dma_addr = tx_queue->txd.buf.dma_addr;
1710
1711 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1712 tx_queue->queue, entries, (u64)dma_addr);
1713
1714 for (i = 0; i < entries; ++i) {
1715 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1716 dma_addr += EFX_BUF_SIZE;
1717 }
1718
1719 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1720
1721 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
aa09a3da 1722 NULL, 0, NULL);
8127d661
BH		 1723 if (rc)
1724 goto fail;
1725
1726 /* A previous user of this TX queue might have set us up the
1727 * bomb by writing a descriptor to the TX push collector but
1728 * not the doorbell. (Each collector belongs to a port, not a
1729 * queue or function, so cannot easily be reset.) We must
1730 * attempt to push a no-op descriptor in its place.
1731 */
1732 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1733 tx_queue->insert_count = 1;
1734 txd = efx_tx_desc(tx_queue, 0);
1735 EFX_POPULATE_QWORD_4(*txd,
1736 ESF_DZ_TX_DESC_IS_OPT, true,
1737 ESF_DZ_TX_OPTION_TYPE,
1738 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1739 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1740 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1741 tx_queue->write_count = 1;
1742 wmb();
1743 efx_ef10_push_tx_desc(tx_queue, txd);
1744
1745 return;
1746
1747fail:
48ce5634
BH		 1748 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1749 tx_queue->queue);
8127d661
BH		 1750}
1751
1752static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1753{
1754 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 1755 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 1756 struct efx_nic *efx = tx_queue->efx;
1757 size_t outlen;
1758 int rc;
1759
1760 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1761 tx_queue->queue);
1762
1e0b8120 1763 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1764 outbuf, sizeof(outbuf), &outlen);
1765
1766 if (rc && rc != -EALREADY)
1767 goto fail;
1768
1769 return;
1770
1771fail:
1e0b8120
EC		 1772 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1773 outbuf, outlen, rc);
8127d661
BH		 1774}
1775
1776static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1777{
1778 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1779}
1780
1781/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1782static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1783{
1784 unsigned int write_ptr;
1785 efx_dword_t reg;
1786
1787 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1788 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1789 efx_writed_page(tx_queue->efx, &reg,
1790 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1791}
1792
1793static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1794{
1795 unsigned int old_write_count = tx_queue->write_count;
1796 struct efx_tx_buffer *buffer;
1797 unsigned int write_ptr;
1798 efx_qword_t *txd;
1799
1800 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1801
1802 do {
1803 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1804 buffer = &tx_queue->buffer[write_ptr];
1805 txd = efx_tx_desc(tx_queue, write_ptr);
1806 ++tx_queue->write_count;
1807
1808 /* Create TX descriptor ring entry */
1809 if (buffer->flags & EFX_TX_BUF_OPTION) {
1810 *txd = buffer->option;
1811 } else {
1812 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1813 EFX_POPULATE_QWORD_3(
1814 *txd,
1815 ESF_DZ_TX_KER_CONT,
1816 buffer->flags & EFX_TX_BUF_CONT,
1817 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1818 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1819 }
1820 } while (tx_queue->write_count != tx_queue->insert_count);
1821
1822 wmb(); /* Ensure descriptors are written before they are fetched */
1823
1824 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1825 txd = efx_tx_desc(tx_queue,
1826 old_write_count & tx_queue->ptr_mask);
1827 efx_ef10_push_tx_desc(tx_queue, txd);
1828 ++tx_queue->pushes;
1829 } else {
1830 efx_ef10_notify_tx_desc(tx_queue);
1831 }
1832}
1833
267c0157
JC		 1834static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1835 bool exclusive, unsigned *context_size)
8127d661
BH		 1836{
1837 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1838 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 1839 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 1840 size_t outlen;
1841 int rc;
267c0157
JC		 1842 u32 alloc_type = exclusive ?
1843 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1844 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1845 unsigned rss_spread = exclusive ?
1846 efx->rss_spread :
1847 min(rounddown_pow_of_two(efx->rss_spread),
1848 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1849
1850 if (!exclusive && rss_spread == 1) {
1851 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1852 if (context_size)
1853 *context_size = 1;
1854 return 0;
1855 }
8127d661
BH		 1856
1857 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 1858 nic_data->vport_id);
267c0157
JC		 1859 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1860 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 1861
1862 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1863 outbuf, sizeof(outbuf), &outlen);
1864 if (rc != 0)
1865 return rc;
1866
1867 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1868 return -EIO;
1869
1870 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1871
267c0157
JC		 1872 if (context_size)
1873 *context_size = rss_spread;
1874
8127d661
BH		 1875 return 0;
1876}
1877
1878static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1879{
1880 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1881 int rc;
1882
1883 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1884 context);
1885
1886 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1887 NULL, 0, NULL);
1888 WARN_ON(rc != 0);
1889}
1890
267c0157
JC		 1891static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1892 const u32 *rx_indir_table)
8127d661
BH		 1893{
1894 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1895 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1896 int i, rc;
1897
1898 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1899 context);
1900 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1901 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1902
1903 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1904 MCDI_PTR(tablebuf,
1905 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 1906 (u8) rx_indir_table[i];
8127d661
BH		 1907
1908 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1909 sizeof(tablebuf), NULL, 0, NULL);
1910 if (rc != 0)
1911 return rc;
1912
1913 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1914 context);
1915 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1916 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1917 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1918 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1919 efx->rx_hash_key[i];
1920
1921 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1922 sizeof(keybuf), NULL, 0, NULL);
1923}
1924
1925static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1926{
1927 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1928
1929 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1930 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1931 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1932}
1933
267c0157
JC		 1934static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1935 unsigned *context_size)
8127d661 1936{
267c0157 1937 u32 new_rx_rss_context;
8127d661 1938 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 1939 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1940 false, context_size);
1941
1942 if (rc != 0)
1943 return rc;
8127d661 1944
267c0157
JC		 1945 nic_data->rx_rss_context = new_rx_rss_context;
1946 nic_data->rx_rss_context_exclusive = false;
1947 efx_set_default_rx_indir_table(efx);
1948 return 0;
1949}
8127d661 1950
267c0157
JC		 1951static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
1952 const u32 *rx_indir_table)
1953{
1954 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1955 int rc;
1956 u32 new_rx_rss_context;
1957
1958 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
1959 !nic_data->rx_rss_context_exclusive) {
1960 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1961 true, NULL);
1962 if (rc == -EOPNOTSUPP)
1963 return rc;
1964 else if (rc != 0)
1965 goto fail1;
1966 } else {
1967 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 1968 }
1969
267c0157
JC		 1970 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
1971 rx_indir_table);
8127d661 1972 if (rc != 0)
267c0157 1973 goto fail2;
8127d661 1974
267c0157
JC		 1975 if (nic_data->rx_rss_context != new_rx_rss_context)
1976 efx_ef10_rx_free_indir_table(efx);
1977 nic_data->rx_rss_context = new_rx_rss_context;
1978 nic_data->rx_rss_context_exclusive = true;
1979 if (rx_indir_table != efx->rx_indir_table)
1980 memcpy(efx->rx_indir_table, rx_indir_table,
1981 sizeof(efx->rx_indir_table));
1982 return 0;
8127d661 1983
267c0157
JC		 1984fail2:
1985 if (new_rx_rss_context != nic_data->rx_rss_context)
1986 efx_ef10_free_rss_context(efx, new_rx_rss_context);
1987fail1:
8127d661 1988 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 1989 return rc;
1990}
1991
1992static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
1993 const u32 *rx_indir_table)
1994{
1995 int rc;
1996
1997 if (efx->rss_spread == 1)
1998 return 0;
1999
2000 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2001
2002 if (rc == -ENOBUFS && !user) {
2003 unsigned context_size;
2004 bool mismatch = false;
2005 size_t i;
2006
2007 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2008 i++)
2009 mismatch = rx_indir_table[i] !=
2010 ethtool_rxfh_indir_default(i, efx->rss_spread);
2011
2012 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2013 if (rc == 0) {
2014 if (context_size != efx->rss_spread)
2015 netif_warn(efx, probe, efx->net_dev,
2016 "Could not allocate an exclusive RSS"
2017 " context; allocated a shared one of"
2018 " different size."
2019 " Wanted %u, got %u.\n",
2020 efx->rss_spread, context_size);
2021 else if (mismatch)
2022 netif_warn(efx, probe, efx->net_dev,
2023 "Could not allocate an exclusive RSS"
2024 " context; allocated a shared one but"
2025 " could not apply custom"
2026 " indirection.\n");
2027 else
2028 netif_info(efx, probe, efx->net_dev,
2029 "Could not allocate an exclusive RSS"
2030 " context; allocated a shared one.\n");
2031 }
2032 }
2033 return rc;
2034}
2035
2036static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2037 const u32 *rx_indir_table
2038 __attribute__ ((unused)))
2039{
2040 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2041
2042 if (user)
2043 return -EOPNOTSUPP;
2044 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2045 return 0;
2046 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2047}
2048
2049static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2050{
2051 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2052 (rx_queue->ptr_mask + 1) *
2053 sizeof(efx_qword_t),
2054 GFP_KERNEL);
2055}
2056
2057static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2058{
2059 MCDI_DECLARE_BUF(inbuf,
2060 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2061 EFX_BUF_SIZE));
8127d661
BH		 2062 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2063 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2064 struct efx_nic *efx = rx_queue->efx;
45b2449e 2065 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2066 size_t inlen;
8127d661
BH		 2067 dma_addr_t dma_addr;
2068 int rc;
2069 int i;
aa09a3da 2070 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2071
2072 rx_queue->scatter_n = 0;
2073 rx_queue->scatter_len = 0;
2074
2075 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2076 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2077 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2078 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2079 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2080 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2081 INIT_RXQ_IN_FLAG_PREFIX, 1,
2082 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2083 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2084 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2085
2086 dma_addr = rx_queue->rxd.buf.dma_addr;
2087
2088 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2089 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2090
2091 for (i = 0; i < entries; ++i) {
2092 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2093 dma_addr += EFX_BUF_SIZE;
2094 }
2095
2096 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2097
2098 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2099 NULL, 0, NULL);
48ce5634
BH		 2100 if (rc)
2101 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2102 efx_rx_queue_index(rx_queue));
8127d661
BH		 2103}
2104
2105static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2106{
2107 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2108 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2109 struct efx_nic *efx = rx_queue->efx;
2110 size_t outlen;
2111 int rc;
2112
2113 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2114 efx_rx_queue_index(rx_queue));
2115
1e0b8120 2116 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2117 outbuf, sizeof(outbuf), &outlen);
2118
2119 if (rc && rc != -EALREADY)
2120 goto fail;
2121
2122 return;
2123
2124fail:
1e0b8120
EC		 2125 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2126 outbuf, outlen, rc);
8127d661
BH		 2127}
2128
2129static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2130{
2131 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2132}
2133
2134/* This creates an entry in the RX descriptor queue */
2135static inline void
2136efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2137{
2138 struct efx_rx_buffer *rx_buf;
2139 efx_qword_t *rxd;
2140
2141 rxd = efx_rx_desc(rx_queue, index);
2142 rx_buf = efx_rx_buffer(rx_queue, index);
2143 EFX_POPULATE_QWORD_2(*rxd,
2144 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2145 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2146}
2147
2148static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2149{
2150 struct efx_nic *efx = rx_queue->efx;
2151 unsigned int write_count;
2152 efx_dword_t reg;
2153
2154 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2155 write_count = rx_queue->added_count & ~7;
2156 if (rx_queue->notified_count == write_count)
2157 return;
2158
2159 do
2160 efx_ef10_build_rx_desc(
2161 rx_queue,
2162 rx_queue->notified_count & rx_queue->ptr_mask);
2163 while (++rx_queue->notified_count != write_count);
2164
2165 wmb();
2166 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2167 write_count & rx_queue->ptr_mask);
2168 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2169 efx_rx_queue_index(rx_queue));
2170}
2171
2172static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2173
2174static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2175{
2176 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2177 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2178 efx_qword_t event;
2179
2180 EFX_POPULATE_QWORD_2(event,
2181 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2182 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2183
2184 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2185
2186 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2187 * already swapped the data to little-endian order.
2188 */
2189 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2190 sizeof(efx_qword_t));
2191
2192 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2193 inbuf, sizeof(inbuf), 0,
2194 efx_ef10_rx_defer_refill_complete, 0);
2195}
2196
2197static void
2198efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2199 int rc, efx_dword_t *outbuf,
2200 size_t outlen_actual)
2201{
2202 /* nothing to do */
2203}
2204
2205static int efx_ef10_ev_probe(struct efx_channel *channel)
2206{
2207 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2208 (channel->eventq_mask + 1) *
2209 sizeof(efx_qword_t),
2210 GFP_KERNEL);
2211}
2212
46e612b0
DP		 2213static void efx_ef10_ev_fini(struct efx_channel *channel)
2214{
2215 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2216 MCDI_DECLARE_BUF_ERR(outbuf);
2217 struct efx_nic *efx = channel->efx;
2218 size_t outlen;
2219 int rc;
2220
2221 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2222
2223 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2224 outbuf, sizeof(outbuf), &outlen);
2225
2226 if (rc && rc != -EALREADY)
2227 goto fail;
2228
2229 return;
2230
2231fail:
2232 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2233 outbuf, outlen, rc);
2234}
2235
8127d661
BH		 2236static int efx_ef10_ev_init(struct efx_channel *channel)
2237{
2238 MCDI_DECLARE_BUF(inbuf,
2239 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2240 EFX_BUF_SIZE));
2241 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2242 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2243 struct efx_nic *efx = channel->efx;
2244 struct efx_ef10_nic_data *nic_data;
2245 bool supports_rx_merge;
2246 size_t inlen, outlen;
46e612b0 2247 unsigned int enabled, implemented;
8127d661
BH		 2248 dma_addr_t dma_addr;
2249 int rc;
2250 int i;
2251
2252 nic_data = efx->nic_data;
2253 supports_rx_merge =
2254 !!(nic_data->datapath_caps &
2255 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2256
2257 /* Fill event queue with all ones (i.e. empty events) */
2258 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2259
2260 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2261 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2262 /* INIT_EVQ expects index in vector table, not absolute */
2263 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2264 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2265 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2266 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2267 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2268 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2269 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2270 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2271 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2272 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2273 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2274 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2275 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2276
2277 dma_addr = channel->eventq.buf.dma_addr;
2278 for (i = 0; i < entries; ++i) {
2279 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2280 dma_addr += EFX_BUF_SIZE;
2281 }
2282
2283 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2284
2285 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2286 outbuf, sizeof(outbuf), &outlen);
8127d661 2287 /* IRQ return is ignored */
46e612b0
DP		 2288 if (channel->channel || rc)
2289 return rc;
8127d661 2290
46e612b0
DP		 2291 /* Successfully created event queue on channel 0 */
2292 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed
EC		 2293 if (rc == -ENOSYS) {
2294 /* GET_WORKAROUNDS was implemented before the bug26807
2295 * workaround, thus the latter must be unavailable in this fw
2296 */
2297 nic_data->workaround_26807 = false;
2298 rc = 0;
2299 } else if (rc) {
8127d661 2300 goto fail;
832dc9ed
EC		 2301 } else {
2302 nic_data->workaround_26807 =
2303 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2304
2305 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2306 !nic_data->workaround_26807) {
5a55a72a
DP		 2307 unsigned int flags;
2308
34ccfe6f
DP		 2309 rc = efx_mcdi_set_workaround(efx,
2310 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 2311 true, &flags);
2312
2313 if (!rc) {
2314 if (flags &
2315 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2316 netif_info(efx, drv, efx->net_dev,
2317 "other functions on NIC have been reset\n");
2318 /* MC's boot count has incremented */
2319 ++nic_data->warm_boot_count;
2320 }
832dc9ed 2321 nic_data->workaround_26807 = true;
5a55a72a 2322 } else if (rc == -EPERM) {
832dc9ed 2323 rc = 0;
5a55a72a 2324 }
832dc9ed 2325 }
46e612b0
DP		 2326 }
2327
2328 if (!rc)
2329 return 0;
8127d661
BH		 2330
2331fail:
46e612b0
DP		 2332 efx_ef10_ev_fini(channel);
2333 return rc;
8127d661
BH		 2334}
2335
2336static void efx_ef10_ev_remove(struct efx_channel *channel)
2337{
2338 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2339}
2340
2341static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2342 unsigned int rx_queue_label)
2343{
2344 struct efx_nic *efx = rx_queue->efx;
2345
2346 netif_info(efx, hw, efx->net_dev,
2347 "rx event arrived on queue %d labeled as queue %u\n",
2348 efx_rx_queue_index(rx_queue), rx_queue_label);
2349
2350 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2351}
2352
2353static void
2354efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2355 unsigned int actual, unsigned int expected)
2356{
2357 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2358 struct efx_nic *efx = rx_queue->efx;
2359
2360 netif_info(efx, hw, efx->net_dev,
2361 "dropped %d events (index=%d expected=%d)\n",
2362 dropped, actual, expected);
2363
2364 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2365}
2366
2367/* partially received RX was aborted. clean up. */
2368static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2369{
2370 unsigned int rx_desc_ptr;
2371
8127d661
BH		 2372 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2373 "scattered RX aborted (dropping %u buffers)\n",
2374 rx_queue->scatter_n);
2375
2376 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2377
2378 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2379 0, EFX_RX_PKT_DISCARD);
2380
2381 rx_queue->removed_count += rx_queue->scatter_n;
2382 rx_queue->scatter_n = 0;
2383 rx_queue->scatter_len = 0;
2384 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2385}
2386
2387static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2388 const efx_qword_t *event)
2389{
2390 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2391 unsigned int n_descs, n_packets, i;
2392 struct efx_nic *efx = channel->efx;
2393 struct efx_rx_queue *rx_queue;
2394 bool rx_cont;
2395 u16 flags = 0;
2396
2397 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2398 return 0;
2399
2400 /* Basic packet information */
2401 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2402 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2403 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2404 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2405 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2406
48ce5634
BH		 2407 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2408 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2409 EFX_QWORD_FMT "\n",
2410 EFX_QWORD_VAL(*event));
8127d661
BH		 2411
2412 rx_queue = efx_channel_get_rx_queue(channel);
2413
2414 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2415 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2416
2417 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2418 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2419
2420 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 2421 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2422
8127d661
BH		 2423 /* detect rx abort */
2424 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 2425 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2426 netdev_WARN(efx->net_dev,
2427 "invalid RX abort: scatter_n=%u event="
2428 EFX_QWORD_FMT "\n",
2429 rx_queue->scatter_n,
2430 EFX_QWORD_VAL(*event));
8127d661
BH		 2431 efx_ef10_handle_rx_abort(rx_queue);
2432 return 0;
2433 }
2434
92a04168
BH		 2435 /* Check that RX completion merging is valid, i.e.
2436 * the current firmware supports it and this is a
2437 * non-scattered packet.
2438 */
2439 if (!(nic_data->datapath_caps &
2440 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2441 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 2442 efx_ef10_handle_rx_bad_lbits(
2443 rx_queue, next_ptr_lbits,
2444 (rx_queue->removed_count +
2445 rx_queue->scatter_n + 1) &
2446 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2447 return 0;
2448 }
2449
2450 /* Merged completion for multiple non-scattered packets */
2451 rx_queue->scatter_n = 1;
2452 rx_queue->scatter_len = 0;
2453 n_packets = n_descs;
2454 ++channel->n_rx_merge_events;
2455 channel->n_rx_merge_packets += n_packets;
2456 flags |= EFX_RX_PKT_PREFIX_LEN;
2457 } else {
2458 ++rx_queue->scatter_n;
2459 rx_queue->scatter_len += rx_bytes;
2460 if (rx_cont)
2461 return 0;
2462 n_packets = 1;
2463 }
2464
2465 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2466 flags |= EFX_RX_PKT_DISCARD;
2467
2468 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2469 channel->n_rx_ip_hdr_chksum_err += n_packets;
2470 } else if (unlikely(EFX_QWORD_FIELD(*event,
2471 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2472 channel->n_rx_tcp_udp_chksum_err += n_packets;
2473 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2474 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2475 flags |= EFX_RX_PKT_CSUMMED;
2476 }
2477
2478 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2479 flags |= EFX_RX_PKT_TCP;
2480
2481 channel->irq_mod_score += 2 * n_packets;
2482
2483 /* Handle received packet(s) */
2484 for (i = 0; i < n_packets; i++) {
2485 efx_rx_packet(rx_queue,
2486 rx_queue->removed_count & rx_queue->ptr_mask,
2487 rx_queue->scatter_n, rx_queue->scatter_len,
2488 flags);
2489 rx_queue->removed_count += rx_queue->scatter_n;
2490 }
2491
2492 rx_queue->scatter_n = 0;
2493 rx_queue->scatter_len = 0;
2494
2495 return n_packets;
2496}
2497
2498static int
2499efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2500{
2501 struct efx_nic *efx = channel->efx;
2502 struct efx_tx_queue *tx_queue;
2503 unsigned int tx_ev_desc_ptr;
2504 unsigned int tx_ev_q_label;
2505 int tx_descs = 0;
2506
2507 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2508 return 0;
2509
2510 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2511 return 0;
2512
2513 /* Transmit completion */
2514 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2515 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2516 tx_queue = efx_channel_get_tx_queue(channel,
2517 tx_ev_q_label % EFX_TXQ_TYPES);
2518 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2519 tx_queue->ptr_mask);
2520 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2521
2522 return tx_descs;
2523}
2524
2525static void
2526efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2527{
2528 struct efx_nic *efx = channel->efx;
2529 int subcode;
2530
2531 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2532
2533 switch (subcode) {
2534 case ESE_DZ_DRV_TIMER_EV:
2535 case ESE_DZ_DRV_WAKE_UP_EV:
2536 break;
2537 case ESE_DZ_DRV_START_UP_EV:
2538 /* event queue init complete. ok. */
2539 break;
2540 default:
2541 netif_err(efx, hw, efx->net_dev,
2542 "channel %d unknown driver event type %d"
2543 " (data " EFX_QWORD_FMT ")\n",
2544 channel->channel, subcode,
2545 EFX_QWORD_VAL(*event));
2546
2547 }
2548}
2549
2550static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2551 efx_qword_t *event)
2552{
2553 struct efx_nic *efx = channel->efx;
2554 u32 subcode;
2555
2556 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2557
2558 switch (subcode) {
2559 case EFX_EF10_TEST:
2560 channel->event_test_cpu = raw_smp_processor_id();
2561 break;
2562 case EFX_EF10_REFILL:
2563 /* The queue must be empty, so we won't receive any rx
2564 * events, so efx_process_channel() won't refill the
2565 * queue. Refill it here
2566 */
cce28794 2567 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 2568 break;
2569 default:
2570 netif_err(efx, hw, efx->net_dev,
2571 "channel %d unknown driver event type %u"
2572 " (data " EFX_QWORD_FMT ")\n",
2573 channel->channel, (unsigned) subcode,
2574 EFX_QWORD_VAL(*event));
2575 }
2576}
2577
2578static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2579{
2580 struct efx_nic *efx = channel->efx;
2581 efx_qword_t event, *p_event;
2582 unsigned int read_ptr;
2583 int ev_code;
2584 int tx_descs = 0;
2585 int spent = 0;
2586
75363a46
EB		 2587 if (quota <= 0)
2588 return spent;
2589
8127d661
BH		 2590 read_ptr = channel->eventq_read_ptr;
2591
2592 for (;;) {
2593 p_event = efx_event(channel, read_ptr);
2594 event = *p_event;
2595
2596 if (!efx_event_present(&event))
2597 break;
2598
2599 EFX_SET_QWORD(*p_event);
2600
2601 ++read_ptr;
2602
2603 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2604
2605 netif_vdbg(efx, drv, efx->net_dev,
2606 "processing event on %d " EFX_QWORD_FMT "\n",
2607 channel->channel, EFX_QWORD_VAL(event));
2608
2609 switch (ev_code) {
2610 case ESE_DZ_EV_CODE_MCDI_EV:
2611 efx_mcdi_process_event(channel, &event);
2612 break;
2613 case ESE_DZ_EV_CODE_RX_EV:
2614 spent += efx_ef10_handle_rx_event(channel, &event);
2615 if (spent >= quota) {
2616 /* XXX can we split a merged event to
2617 * avoid going over-quota?
2618 */
2619 spent = quota;
2620 goto out;
2621 }
2622 break;
2623 case ESE_DZ_EV_CODE_TX_EV:
2624 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2625 if (tx_descs > efx->txq_entries) {
2626 spent = quota;
2627 goto out;
2628 } else if (++spent == quota) {
2629 goto out;
2630 }
2631 break;
2632 case ESE_DZ_EV_CODE_DRIVER_EV:
2633 efx_ef10_handle_driver_event(channel, &event);
2634 if (++spent == quota)
2635 goto out;
2636 break;
2637 case EFX_EF10_DRVGEN_EV:
2638 efx_ef10_handle_driver_generated_event(channel, &event);
2639 break;
2640 default:
2641 netif_err(efx, hw, efx->net_dev,
2642 "channel %d unknown event type %d"
2643 " (data " EFX_QWORD_FMT ")\n",
2644 channel->channel, ev_code,
2645 EFX_QWORD_VAL(event));
2646 }
2647 }
2648
2649out:
2650 channel->eventq_read_ptr = read_ptr;
2651 return spent;
2652}
2653
2654static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2655{
2656 struct efx_nic *efx = channel->efx;
2657 efx_dword_t rptr;
2658
2659 if (EFX_EF10_WORKAROUND_35388(efx)) {
2660 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2661 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2662 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2663 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2664
2665 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2666 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2667 ERF_DD_EVQ_IND_RPTR,
2668 (channel->eventq_read_ptr &
2669 channel->eventq_mask) >>
2670 ERF_DD_EVQ_IND_RPTR_WIDTH);
2671 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2672 channel->channel);
2673 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2674 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2675 ERF_DD_EVQ_IND_RPTR,
2676 channel->eventq_read_ptr &
2677 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2678 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2679 channel->channel);
2680 } else {
2681 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2682 channel->eventq_read_ptr &
2683 channel->eventq_mask);
2684 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2685 }
2686}
2687
2688static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2689{
2690 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2691 struct efx_nic *efx = channel->efx;
2692 efx_qword_t event;
2693 int rc;
2694
2695 EFX_POPULATE_QWORD_2(event,
2696 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2697 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2698
2699 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2700
2701 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2702 * already swapped the data to little-endian order.
2703 */
2704 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2705 sizeof(efx_qword_t));
2706
2707 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2708 NULL, 0, NULL);
2709 if (rc != 0)
2710 goto fail;
2711
2712 return;
2713
2714fail:
2715 WARN_ON(true);
2716 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2717}
2718
2719void efx_ef10_handle_drain_event(struct efx_nic *efx)
2720{
2721 if (atomic_dec_and_test(&efx->active_queues))
2722 wake_up(&efx->flush_wq);
2723
2724 WARN_ON(atomic_read(&efx->active_queues) < 0);
2725}
2726
2727static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2728{
2729 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2730 struct efx_channel *channel;
2731 struct efx_tx_queue *tx_queue;
2732 struct efx_rx_queue *rx_queue;
2733 int pending;
2734
2735 /* If the MC has just rebooted, the TX/RX queues will have already been
2736 * torn down, but efx->active_queues needs to be set to zero.
2737 */
2738 if (nic_data->must_realloc_vis) {
2739 atomic_set(&efx->active_queues, 0);
2740 return 0;
2741 }
2742
2743 /* Do not attempt to write to the NIC during EEH recovery */
2744 if (efx->state != STATE_RECOVERY) {
2745 efx_for_each_channel(channel, efx) {
2746 efx_for_each_channel_rx_queue(rx_queue, channel)
2747 efx_ef10_rx_fini(rx_queue);
2748 efx_for_each_channel_tx_queue(tx_queue, channel)
2749 efx_ef10_tx_fini(tx_queue);
2750 }
2751
2752 wait_event_timeout(efx->flush_wq,
2753 atomic_read(&efx->active_queues) == 0,
2754 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2755 pending = atomic_read(&efx->active_queues);
2756 if (pending) {
2757 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2758 pending);
2759 return -ETIMEDOUT;
2760 }
2761 }
2762
2763 return 0;
2764}
2765
e283546c
EC		 2766static void efx_ef10_prepare_flr(struct efx_nic *efx)
2767{
2768 atomic_set(&efx->active_queues, 0);
2769}
2770
8127d661
BH		 2771static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2772 const struct efx_filter_spec *right)
2773{
2774 if ((left->match_flags ^ right->match_flags) |
2775 ((left->flags ^ right->flags) &
2776 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2777 return false;
2778
2779 return memcmp(&left->outer_vid, &right->outer_vid,
2780 sizeof(struct efx_filter_spec) -
2781 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2782}
2783
2784static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2785{
2786 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2787 return jhash2((const u32 *)&spec->outer_vid,
2788 (sizeof(struct efx_filter_spec) -
2789 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2790 0);
2791 /* XXX should we randomise the initval? */
2792}
2793
2794/* Decide whether a filter should be exclusive or else should allow
2795 * delivery to additional recipients. Currently we decide that
2796 * filters for specific local unicast MAC and IP addresses are
2797 * exclusive.
2798 */
2799static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2800{
2801 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2802 !is_multicast_ether_addr(spec->loc_mac))
2803 return true;
2804
2805 if ((spec->match_flags &
2806 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2807 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2808 if (spec->ether_type == htons(ETH_P_IP) &&
2809 !ipv4_is_multicast(spec->loc_host[0]))
2810 return true;
2811 if (spec->ether_type == htons(ETH_P_IPV6) &&
2812 ((const u8 *)spec->loc_host)[0] != 0xff)
2813 return true;
2814 }
2815
2816 return false;
2817}
2818
2819static struct efx_filter_spec *
2820efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2821 unsigned int filter_idx)
2822{
2823 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2824 ~EFX_EF10_FILTER_FLAGS);
2825}
2826
2827static unsigned int
2828efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2829 unsigned int filter_idx)
2830{
2831 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2832}
2833
2834static void
2835efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2836 unsigned int filter_idx,
2837 const struct efx_filter_spec *spec,
2838 unsigned int flags)
2839{
2840 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2841}
2842
2843static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2844 const struct efx_filter_spec *spec,
2845 efx_dword_t *inbuf, u64 handle,
2846 bool replacing)
2847{
2848 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2849
2850 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2851
2852 if (replacing) {
2853 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2854 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2855 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2856 } else {
2857 u32 match_fields = 0;
2858
2859 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2860 efx_ef10_filter_is_exclusive(spec) ?
2861 MC_CMD_FILTER_OP_IN_OP_INSERT :
2862 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2863
2864 /* Convert match flags and values. Unlike almost
2865 * everything else in MCDI, these fields are in
2866 * network byte order.
2867 */
2868 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2869 match_fields |=
2870 is_multicast_ether_addr(spec->loc_mac) ?
2871 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2872 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2873#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2874 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2875 match_fields |= \
2876 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2877 mcdi_field ## _LBN; \
2878 BUILD_BUG_ON( \
2879 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2880 sizeof(spec->gen_field)); \
2881 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2882 &spec->gen_field, sizeof(spec->gen_field)); \
2883 }
2884 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2885 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2886 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2887 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2888 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2889 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2890 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2891 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2892 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2893 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2894#undef COPY_FIELD
2895 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2896 match_fields);
2897 }
2898
45b2449e 2899 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2900 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2901 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2902 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2903 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 2904 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 2905 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2906 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 2907 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2908 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2909 0 : spec->dmaq_id);
8127d661
BH		 2910 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2911 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2912 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2913 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2914 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2915 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2916 spec->rss_context !=
2917 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2918 spec->rss_context : nic_data->rx_rss_context);
2919}
2920
2921static int efx_ef10_filter_push(struct efx_nic *efx,
2922 const struct efx_filter_spec *spec,
2923 u64 *handle, bool replacing)
2924{
2925 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2926 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2927 int rc;
2928
2929 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2930 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2931 outbuf, sizeof(outbuf), NULL);
2932 if (rc == 0)
2933 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 2934 if (rc == -ENOSPC)
2935 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 2936 return rc;
2937}
2938
2939static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2940 enum efx_filter_match_flags match_flags)
2941{
2942 unsigned int match_pri;
2943
2944 for (match_pri = 0;
2945 match_pri < table->rx_match_count;
2946 match_pri++)
2947 if (table->rx_match_flags[match_pri] == match_flags)
2948 return match_pri;
2949
2950 return -EPROTONOSUPPORT;
2951}
2952
2953static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2954 struct efx_filter_spec *spec,
2955 bool replace_equal)
2956{
2957 struct efx_ef10_filter_table *table = efx->filter_state;
2958 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2959 struct efx_filter_spec *saved_spec;
2960 unsigned int match_pri, hash;
2961 unsigned int priv_flags;
2962 bool replacing = false;
2963 int ins_index = -1;
2964 DEFINE_WAIT(wait);
2965 bool is_mc_recip;
2966 s32 rc;
2967
2968 /* For now, only support RX filters */
2969 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2970 EFX_FILTER_FLAG_RX)
2971 return -EINVAL;
2972
2973 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2974 if (rc < 0)
2975 return rc;
2976 match_pri = rc;
2977
2978 hash = efx_ef10_filter_hash(spec);
2979 is_mc_recip = efx_filter_is_mc_recipient(spec);
2980 if (is_mc_recip)
2981 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2982
2983 /* Find any existing filters with the same match tuple or
2984 * else a free slot to insert at. If any of them are busy,
2985 * we have to wait and retry.
2986 */
2987 for (;;) {
2988 unsigned int depth = 1;
2989 unsigned int i;
2990
2991 spin_lock_bh(&efx->filter_lock);
2992
2993 for (;;) {
2994 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2995 saved_spec = efx_ef10_filter_entry_spec(table, i);
2996
2997 if (!saved_spec) {
2998 if (ins_index < 0)
2999 ins_index = i;
3000 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3001 if (table->entry[i].spec &
3002 EFX_EF10_FILTER_FLAG_BUSY)
3003 break;
3004 if (spec->priority < saved_spec->priority &&
7665d1ab 3005 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 3006 rc = -EPERM;
3007 goto out_unlock;
3008 }
3009 if (!is_mc_recip) {
3010 /* This is the only one */
3011 if (spec->priority ==
3012 saved_spec->priority &&
3013 !replace_equal) {
3014 rc = -EEXIST;
3015 goto out_unlock;
3016 }
3017 ins_index = i;
3018 goto found;
3019 } else if (spec->priority >
3020 saved_spec->priority ||
3021 (spec->priority ==
3022 saved_spec->priority &&
3023 replace_equal)) {
3024 if (ins_index < 0)
3025 ins_index = i;
3026 else
3027 __set_bit(depth, mc_rem_map);
3028 }
3029 }
3030
3031 /* Once we reach the maximum search depth, use
3032 * the first suitable slot or return -EBUSY if
3033 * there was none
3034 */
3035 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3036 if (ins_index < 0) {
3037 rc = -EBUSY;
3038 goto out_unlock;
3039 }
3040 goto found;
3041 }
3042
3043 ++depth;
3044 }
3045
3046 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3047 spin_unlock_bh(&efx->filter_lock);
3048 schedule();
3049 }
3050
3051found:
3052 /* Create a software table entry if necessary, and mark it
3053 * busy. We might yet fail to insert, but any attempt to
3054 * insert a conflicting filter while we're waiting for the
3055 * firmware must find the busy entry.
3056 */
3057 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3058 if (saved_spec) {
7665d1ab
BH		 3059 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3060 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 3061 /* Just make sure it won't be removed */
7665d1ab
BH		 3062 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3063 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3064 table->entry[ins_index].spec &=
b59e6ef8 3065 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3066 rc = ins_index;
3067 goto out_unlock;
3068 }
3069 replacing = true;
3070 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3071 } else {
3072 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3073 if (!saved_spec) {
3074 rc = -ENOMEM;
3075 goto out_unlock;
3076 }
3077 *saved_spec = *spec;
3078 priv_flags = 0;
3079 }
3080 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3081 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3082
3083 /* Mark lower-priority multicast recipients busy prior to removal */
3084 if (is_mc_recip) {
3085 unsigned int depth, i;
3086
3087 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3088 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3089 if (test_bit(depth, mc_rem_map))
3090 table->entry[i].spec |=
3091 EFX_EF10_FILTER_FLAG_BUSY;
3092 }
3093 }
3094
3095 spin_unlock_bh(&efx->filter_lock);
3096
3097 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3098 replacing);
3099
3100 /* Finalise the software table entry */
3101 spin_lock_bh(&efx->filter_lock);
3102 if (rc == 0) {
3103 if (replacing) {
3104 /* Update the fields that may differ */
7665d1ab
BH		 3105 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3106 saved_spec->flags |=
3107 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3108 saved_spec->priority = spec->priority;
7665d1ab 3109 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 3110 saved_spec->flags |= spec->flags;
3111 saved_spec->rss_context = spec->rss_context;
3112 saved_spec->dmaq_id = spec->dmaq_id;
3113 }
3114 } else if (!replacing) {
3115 kfree(saved_spec);
3116 saved_spec = NULL;
3117 }
3118 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3119
3120 /* Remove and finalise entries for lower-priority multicast
3121 * recipients
3122 */
3123 if (is_mc_recip) {
3124 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3125 unsigned int depth, i;
3126
3127 memset(inbuf, 0, sizeof(inbuf));
3128
3129 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3130 if (!test_bit(depth, mc_rem_map))
3131 continue;
3132
3133 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3134 saved_spec = efx_ef10_filter_entry_spec(table, i);
3135 priv_flags = efx_ef10_filter_entry_flags(table, i);
3136
3137 if (rc == 0) {
3138 spin_unlock_bh(&efx->filter_lock);
3139 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3140 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3141 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3142 table->entry[i].handle);
3143 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3144 inbuf, sizeof(inbuf),
3145 NULL, 0, NULL);
3146 spin_lock_bh(&efx->filter_lock);
3147 }
3148
3149 if (rc == 0) {
3150 kfree(saved_spec);
3151 saved_spec = NULL;
3152 priv_flags = 0;
3153 } else {
3154 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3155 }
3156 efx_ef10_filter_set_entry(table, i, saved_spec,
3157 priv_flags);
3158 }
3159 }
3160
3161 /* If successful, return the inserted filter ID */
3162 if (rc == 0)
3163 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3164
3165 wake_up_all(&table->waitq);
3166out_unlock:
3167 spin_unlock_bh(&efx->filter_lock);
3168 finish_wait(&table->waitq, &wait);
3169 return rc;
3170}
3171
9fd8095d 3172static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 3173{
3174 /* no need to do anything here on EF10 */
3175}
3176
3177/* Remove a filter.
b59e6ef8
BH		 3178 * If !by_index, remove by ID
3179 * If by_index, remove by index
8127d661
BH		 3180 * Filter ID may come from userland and must be range-checked.
3181 */
3182static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 3183 unsigned int priority_mask,
b59e6ef8 3184 u32 filter_id, bool by_index)
8127d661
BH		 3185{
3186 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3187 struct efx_ef10_filter_table *table = efx->filter_state;
3188 MCDI_DECLARE_BUF(inbuf,
3189 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3190 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3191 struct efx_filter_spec *spec;
3192 DEFINE_WAIT(wait);
3193 int rc;
3194
3195 /* Find the software table entry and mark it busy. Don't
3196 * remove it yet; any attempt to update while we're waiting
3197 * for the firmware must find the busy entry.
3198 */
3199 for (;;) {
3200 spin_lock_bh(&efx->filter_lock);
3201 if (!(table->entry[filter_idx].spec &
3202 EFX_EF10_FILTER_FLAG_BUSY))
3203 break;
3204 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3205 spin_unlock_bh(&efx->filter_lock);
3206 schedule();
3207 }
7665d1ab 3208
8127d661 3209 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 3210 if (!spec ||
b59e6ef8 3211 (!by_index &&
8127d661
BH		 3212 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3213 filter_id / HUNT_FILTER_TBL_ROWS)) {
3214 rc = -ENOENT;
3215 goto out_unlock;
3216 }
7665d1ab
BH		 3217
3218 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 3219 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 3220 /* Just remove flags */
3221 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 3222 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 3223 rc = 0;
3224 goto out_unlock;
3225 }
3226
fbd79120 3227 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 3228 rc = -ENOENT;
3229 goto out_unlock;
3230 }
3231
8127d661
BH		 3232 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3233 spin_unlock_bh(&efx->filter_lock);
3234
7665d1ab 3235 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 3236 /* Reset to an automatic filter */
8127d661
BH		 3237
3238 struct efx_filter_spec new_spec = *spec;
3239
7665d1ab 3240 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 3241 new_spec.flags = (EFX_FILTER_FLAG_RX |
7665d1ab 3242 EFX_FILTER_FLAG_RX_RSS);
8127d661
BH		 3243 new_spec.dmaq_id = 0;
3244 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3245 rc = efx_ef10_filter_push(efx, &new_spec,
3246 &table->entry[filter_idx].handle,
3247 true);
3248
3249 spin_lock_bh(&efx->filter_lock);
3250 if (rc == 0)
3251 *spec = new_spec;
3252 } else {
3253 /* Really remove the filter */
3254
3255 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3256 efx_ef10_filter_is_exclusive(spec) ?
3257 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3258 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3259 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3260 table->entry[filter_idx].handle);
3261 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3262 inbuf, sizeof(inbuf), NULL, 0, NULL);
3263
3264 spin_lock_bh(&efx->filter_lock);
3265 if (rc == 0) {
3266 kfree(spec);
3267 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3268 }
3269 }
7665d1ab 3270
8127d661
BH		 3271 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3272 wake_up_all(&table->waitq);
3273out_unlock:
3274 spin_unlock_bh(&efx->filter_lock);
3275 finish_wait(&table->waitq, &wait);
3276 return rc;
3277}
3278
3279static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3280 enum efx_filter_priority priority,
3281 u32 filter_id)
3282{
fbd79120
BH		 3283 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3284 filter_id, false);
8127d661
BH		 3285}
3286
12fb0da4
EC		 3287static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3288{
3289 return filter_id % HUNT_FILTER_TBL_ROWS;
3290}
3291
3292static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3293 enum efx_filter_priority priority,
3294 u32 filter_id)
3295{
3296 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3297 filter_id, true);
3298}
3299
8127d661
BH		 3300static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3301 enum efx_filter_priority priority,
3302 u32 filter_id, struct efx_filter_spec *spec)
3303{
3304 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3305 struct efx_ef10_filter_table *table = efx->filter_state;
3306 const struct efx_filter_spec *saved_spec;
3307 int rc;
3308
3309 spin_lock_bh(&efx->filter_lock);
3310 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3311 if (saved_spec && saved_spec->priority == priority &&
3312 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3313 filter_id / HUNT_FILTER_TBL_ROWS) {
3314 *spec = *saved_spec;
3315 rc = 0;
3316 } else {
3317 rc = -ENOENT;
3318 }
3319 spin_unlock_bh(&efx->filter_lock);
3320 return rc;
3321}
3322
fbd79120 3323static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 3324 enum efx_filter_priority priority)
3325{
fbd79120
BH		 3326 unsigned int priority_mask;
3327 unsigned int i;
3328 int rc;
3329
3330 priority_mask = (((1U << (priority + 1)) - 1) &
3331 ~(1U << EFX_FILTER_PRI_AUTO));
3332
3333 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3334 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3335 i, true);
3336 if (rc && rc != -ENOENT)
3337 return rc;
3338 }
3339
3340 return 0;
8127d661
BH		 3341}
3342
3343static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3344 enum efx_filter_priority priority)
3345{
3346 struct efx_ef10_filter_table *table = efx->filter_state;
3347 unsigned int filter_idx;
3348 s32 count = 0;
3349
3350 spin_lock_bh(&efx->filter_lock);
3351 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3352 if (table->entry[filter_idx].spec &&
3353 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3354 priority)
3355 ++count;
3356 }
3357 spin_unlock_bh(&efx->filter_lock);
3358 return count;
3359}
3360
3361static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3362{
3363 struct efx_ef10_filter_table *table = efx->filter_state;
3364
3365 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3366}
3367
3368static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3369 enum efx_filter_priority priority,
3370 u32 *buf, u32 size)
3371{
3372 struct efx_ef10_filter_table *table = efx->filter_state;
3373 struct efx_filter_spec *spec;
3374 unsigned int filter_idx;
3375 s32 count = 0;
3376
3377 spin_lock_bh(&efx->filter_lock);
3378 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3379 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3380 if (spec && spec->priority == priority) {
3381 if (count == size) {
3382 count = -EMSGSIZE;
3383 break;
3384 }
3385 buf[count++] = (efx_ef10_filter_rx_match_pri(
3386 table, spec->match_flags) *
3387 HUNT_FILTER_TBL_ROWS +
3388 filter_idx);
3389 }
3390 }
3391 spin_unlock_bh(&efx->filter_lock);
3392 return count;
3393}
3394
3395#ifdef CONFIG_RFS_ACCEL
3396
3397static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3398
3399static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3400 struct efx_filter_spec *spec)
3401{
3402 struct efx_ef10_filter_table *table = efx->filter_state;
3403 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3404 struct efx_filter_spec *saved_spec;
3405 unsigned int hash, i, depth = 1;
3406 bool replacing = false;
3407 int ins_index = -1;
3408 u64 cookie;
3409 s32 rc;
3410
3411 /* Must be an RX filter without RSS and not for a multicast
3412 * destination address (RFS only works for connected sockets).
3413 * These restrictions allow us to pass only a tiny amount of
3414 * data through to the completion function.
3415 */
3416 EFX_WARN_ON_PARANOID(spec->flags !=
3417 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3418 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3419 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3420
3421 hash = efx_ef10_filter_hash(spec);
3422
3423 spin_lock_bh(&efx->filter_lock);
3424
3425 /* Find any existing filter with the same match tuple or else
3426 * a free slot to insert at. If an existing filter is busy,
3427 * we have to give up.
3428 */
3429 for (;;) {
3430 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3431 saved_spec = efx_ef10_filter_entry_spec(table, i);
3432
3433 if (!saved_spec) {
3434 if (ins_index < 0)
3435 ins_index = i;
3436 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3437 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3438 rc = -EBUSY;
3439 goto fail_unlock;
3440 }
8127d661
BH		 3441 if (spec->priority < saved_spec->priority) {
3442 rc = -EPERM;
3443 goto fail_unlock;
3444 }
3445 ins_index = i;
3446 break;
3447 }
3448
3449 /* Once we reach the maximum search depth, use the
3450 * first suitable slot or return -EBUSY if there was
3451 * none
3452 */
3453 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3454 if (ins_index < 0) {
3455 rc = -EBUSY;
3456 goto fail_unlock;
3457 }
3458 break;
3459 }
3460
3461 ++depth;
3462 }
3463
3464 /* Create a software table entry if necessary, and mark it
3465 * busy. We might yet fail to insert, but any attempt to
3466 * insert a conflicting filter while we're waiting for the
3467 * firmware must find the busy entry.
3468 */
3469 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3470 if (saved_spec) {
3471 replacing = true;
3472 } else {
3473 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3474 if (!saved_spec) {
3475 rc = -ENOMEM;
3476 goto fail_unlock;
3477 }
3478 *saved_spec = *spec;
3479 }
3480 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3481 EFX_EF10_FILTER_FLAG_BUSY);
3482
3483 spin_unlock_bh(&efx->filter_lock);
3484
3485 /* Pack up the variables needed on completion */
3486 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3487
3488 efx_ef10_filter_push_prep(efx, spec, inbuf,
3489 table->entry[ins_index].handle, replacing);
3490 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3491 MC_CMD_FILTER_OP_OUT_LEN,
3492 efx_ef10_filter_rfs_insert_complete, cookie);
3493
3494 return ins_index;
3495
3496fail_unlock:
3497 spin_unlock_bh(&efx->filter_lock);
3498 return rc;
3499}
3500
3501static void
3502efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3503 int rc, efx_dword_t *outbuf,
3504 size_t outlen_actual)
3505{
3506 struct efx_ef10_filter_table *table = efx->filter_state;
3507 unsigned int ins_index, dmaq_id;
3508 struct efx_filter_spec *spec;
3509 bool replacing;
3510
3511 /* Unpack the cookie */
3512 replacing = cookie >> 31;
3513 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3514 dmaq_id = cookie & 0xffff;
3515
3516 spin_lock_bh(&efx->filter_lock);
3517 spec = efx_ef10_filter_entry_spec(table, ins_index);
3518 if (rc == 0) {
3519 table->entry[ins_index].handle =
3520 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3521 if (replacing)
3522 spec->dmaq_id = dmaq_id;
3523 } else if (!replacing) {
3524 kfree(spec);
3525 spec = NULL;
3526 }
3527 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3528 spin_unlock_bh(&efx->filter_lock);
3529
3530 wake_up_all(&table->waitq);
3531}
3532
3533static void
3534efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3535 unsigned long filter_idx,
3536 int rc, efx_dword_t *outbuf,
3537 size_t outlen_actual);
3538
3539static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3540 unsigned int filter_idx)
3541{
3542 struct efx_ef10_filter_table *table = efx->filter_state;
3543 struct efx_filter_spec *spec =
3544 efx_ef10_filter_entry_spec(table, filter_idx);
3545 MCDI_DECLARE_BUF(inbuf,
3546 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3547 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3548
3549 if (!spec ||
3550 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3551 spec->priority != EFX_FILTER_PRI_HINT ||
3552 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3553 flow_id, filter_idx))
3554 return false;
3555
3556 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3557 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3558 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3559 table->entry[filter_idx].handle);
3560 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3561 efx_ef10_filter_rfs_expire_complete, filter_idx))
3562 return false;
3563
3564 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3565 return true;
3566}
3567
3568static void
3569efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3570 unsigned long filter_idx,
3571 int rc, efx_dword_t *outbuf,
3572 size_t outlen_actual)
3573{
3574 struct efx_ef10_filter_table *table = efx->filter_state;
3575 struct efx_filter_spec *spec =
3576 efx_ef10_filter_entry_spec(table, filter_idx);
3577
3578 spin_lock_bh(&efx->filter_lock);
3579 if (rc == 0) {
3580 kfree(spec);
3581 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3582 }
3583 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3584 wake_up_all(&table->waitq);
3585 spin_unlock_bh(&efx->filter_lock);
3586}
3587
3588#endif /* CONFIG_RFS_ACCEL */
3589
3590static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3591{
3592 int match_flags = 0;
3593
3594#define MAP_FLAG(gen_flag, mcdi_field) { \
3595 u32 old_mcdi_flags = mcdi_flags; \
3596 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3597 mcdi_field ## _LBN); \
3598 if (mcdi_flags != old_mcdi_flags) \
3599 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3600 }
3601 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3602 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3603 MAP_FLAG(REM_HOST, SRC_IP);
3604 MAP_FLAG(LOC_HOST, DST_IP);
3605 MAP_FLAG(REM_MAC, SRC_MAC);
3606 MAP_FLAG(REM_PORT, SRC_PORT);
3607 MAP_FLAG(LOC_MAC, DST_MAC);
3608 MAP_FLAG(LOC_PORT, DST_PORT);
3609 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3610 MAP_FLAG(INNER_VID, INNER_VLAN);
3611 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3612 MAP_FLAG(IP_PROTO, IP_PROTO);
3613#undef MAP_FLAG
3614
3615 /* Did we map them all? */
3616 if (mcdi_flags)
3617 return -EINVAL;
3618
3619 return match_flags;
3620}
3621
3622static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3623{
3624 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3625 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3626 unsigned int pd_match_pri, pd_match_count;
3627 struct efx_ef10_filter_table *table;
3628 size_t outlen;
3629 int rc;
3630
3631 table = kzalloc(sizeof(*table), GFP_KERNEL);
3632 if (!table)
3633 return -ENOMEM;
3634
3635 /* Find out which RX filter types are supported, and their priorities */
3636 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3637 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3638 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3639 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3640 &outlen);
3641 if (rc)
3642 goto fail;
3643 pd_match_count = MCDI_VAR_ARRAY_LEN(
3644 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3645 table->rx_match_count = 0;
3646
3647 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3648 u32 mcdi_flags =
3649 MCDI_ARRAY_DWORD(
3650 outbuf,
3651 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3652 pd_match_pri);
3653 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3654 if (rc < 0) {
3655 netif_dbg(efx, probe, efx->net_dev,
3656 "%s: fw flags %#x pri %u not supported in driver\n",
3657 __func__, mcdi_flags, pd_match_pri);
3658 } else {
3659 netif_dbg(efx, probe, efx->net_dev,
3660 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3661 __func__, mcdi_flags, pd_match_pri,
3662 rc, table->rx_match_count);
3663 table->rx_match_flags[table->rx_match_count++] = rc;
3664 }
3665 }
3666
3667 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3668 if (!table->entry) {
3669 rc = -ENOMEM;
3670 goto fail;
3671 }
3672
12fb0da4
EC		 3673 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3674 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3675 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3676
8127d661
BH		 3677 efx->filter_state = table;
3678 init_waitqueue_head(&table->waitq);
3679 return 0;
3680
3681fail:
3682 kfree(table);
3683 return rc;
3684}
3685
0d322413
EC		 3686/* Caller must hold efx->filter_sem for read if race against
3687 * efx_ef10_filter_table_remove() is possible
3688 */
8127d661
BH		 3689static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3690{
3691 struct efx_ef10_filter_table *table = efx->filter_state;
3692 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3693 struct efx_filter_spec *spec;
3694 unsigned int filter_idx;
3695 bool failed = false;
3696 int rc;
3697
0d322413
EC		 3698 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3699
8127d661
BH		 3700 if (!nic_data->must_restore_filters)
3701 return;
3702
0d322413
EC		 3703 if (!table)
3704 return;
3705
8127d661
BH		 3706 spin_lock_bh(&efx->filter_lock);
3707
3708 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3709 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3710 if (!spec)
3711 continue;
3712
3713 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3714 spin_unlock_bh(&efx->filter_lock);
3715
3716 rc = efx_ef10_filter_push(efx, spec,
3717 &table->entry[filter_idx].handle,
3718 false);
3719 if (rc)
3720 failed = true;
3721
3722 spin_lock_bh(&efx->filter_lock);
3723 if (rc) {
3724 kfree(spec);
3725 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3726 } else {
3727 table->entry[filter_idx].spec &=
3728 ~EFX_EF10_FILTER_FLAG_BUSY;
3729 }
3730 }
3731
3732 spin_unlock_bh(&efx->filter_lock);
3733
3734 if (failed)
3735 netif_err(efx, hw, efx->net_dev,
3736 "unable to restore all filters\n");
3737 else
3738 nic_data->must_restore_filters = false;
3739}
3740
0d322413 3741/* Caller must hold efx->filter_sem for write */
8127d661
BH		 3742static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3743{
3744 struct efx_ef10_filter_table *table = efx->filter_state;
3745 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3746 struct efx_filter_spec *spec;
3747 unsigned int filter_idx;
3748 int rc;
3749
0d322413
EC		 3750 efx->filter_state = NULL;
3751 if (!table)
3752 return;
3753
8127d661
BH		 3754 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3755 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3756 if (!spec)
3757 continue;
3758
3759 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3760 efx_ef10_filter_is_exclusive(spec) ?
3761 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3762 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3763 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3764 table->entry[filter_idx].handle);
3765 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3766 NULL, 0, NULL);
48ce5634
BH		 3767 if (rc)
3768 netdev_WARN(efx->net_dev,
3769 "filter_idx=%#x handle=%#llx\n",
3770 filter_idx,
3771 table->entry[filter_idx].handle);
8127d661
BH		 3772 kfree(spec);
3773 }
3774
3775 vfree(table->entry);
3776 kfree(table);
3777}
3778
12fb0da4
EC		 3779#define EFX_EF10_FILTER_DO_MARK_OLD(id) \
3780 if (id != EFX_EF10_FILTER_ID_INVALID) { \
3781 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \
3782 WARN_ON(!table->entry[filter_idx].spec); \
3783 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; \
3784 }
822b96f8 3785static void efx_ef10_filter_mark_old(struct efx_nic *efx)
8127d661
BH		 3786{
3787 struct efx_ef10_filter_table *table = efx->filter_state;
822b96f8 3788 unsigned int filter_idx, i;
8127d661 3789
0d322413
EC		 3790 if (!table)
3791 return;
3792
8127d661
BH		 3793 /* Mark old filters that may need to be removed */
3794 spin_lock_bh(&efx->filter_lock);
12fb0da4
EC		 3795 for (i = 0; i < table->dev_uc_count; i++)
3796 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id);
3797 for (i = 0; i < table->dev_mc_count; i++)
3798 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id);
3799 EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id);
3800 EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id);
3801 EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id);
8127d661 3802 spin_unlock_bh(&efx->filter_lock);
822b96f8 3803}
12fb0da4 3804#undef EFX_EF10_FILTER_DO_MARK_OLD
822b96f8
DP		 3805
3806static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc)
3807{
3808 struct efx_ef10_filter_table *table = efx->filter_state;
3809 struct net_device *net_dev = efx->net_dev;
3810 struct netdev_hw_addr *uc;
12fb0da4 3811 int addr_count;
822b96f8 3812 unsigned int i;
8127d661 3813
12fb0da4
EC		 3814 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3815 addr_count = netdev_uc_count(net_dev);
3816 if (net_dev->flags & IFF_PROMISC)
822b96f8 3817 *promisc = true;
12fb0da4 3818 table->dev_uc_count = 1 + addr_count;
822b96f8
DP		 3819 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3820 i = 1;
3821 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4
EC		 3822 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
3823 *promisc = true;
3824 break;
3825 }
822b96f8 3826 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
12fb0da4 3827 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
822b96f8
DP		 3828 i++;
3829 }
3830}
3831
3832static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc)
3833{
3834 struct efx_ef10_filter_table *table = efx->filter_state;
3835 struct net_device *net_dev = efx->net_dev;
3836 struct netdev_hw_addr *mc;
ab8b1f7c 3837 unsigned int i, addr_count;
822b96f8 3838
12fb0da4
EC		 3839 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3840 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
ab8b1f7c 3841 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
822b96f8 3842 *promisc = true;
ab8b1f7c 3843
12fb0da4
EC		 3844 addr_count = netdev_mc_count(net_dev);
3845 i = 0;
ab8b1f7c 3846 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4
EC		 3847 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
3848 *promisc = true;
3849 break;
3850 }
ab8b1f7c 3851 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
12fb0da4 3852 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
ab8b1f7c 3853 i++;
8127d661 3854 }
12fb0da4
EC		 3855
3856 table->dev_mc_count = i;
822b96f8 3857}
8127d661 3858
12fb0da4
EC		 3859static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
3860 bool multicast, bool rollback)
822b96f8
DP		 3861{
3862 struct efx_ef10_filter_table *table = efx->filter_state;
3863 struct efx_ef10_dev_addr *addr_list;
3864 struct efx_filter_spec spec;
12fb0da4
EC		 3865 u8 baddr[ETH_ALEN];
3866 unsigned int i, j;
3867 int addr_count;
822b96f8
DP		 3868 int rc;
3869
3870 if (multicast) {
3871 addr_list = table->dev_mc_list;
12fb0da4 3872 addr_count = table->dev_mc_count;
822b96f8
DP		 3873 } else {
3874 addr_list = table->dev_uc_list;
12fb0da4 3875 addr_count = table->dev_uc_count;
8127d661
BH		 3876 }
3877
822b96f8 3878 /* Insert/renew filters */
12fb0da4 3879 for (i = 0; i < addr_count; i++) {
b6f568e2
JC		 3880 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3881 EFX_FILTER_FLAG_RX_RSS,
3882 0);
3883 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
822b96f8 3884 addr_list[i].addr);
b6f568e2
JC		 3885 rc = efx_ef10_filter_insert(efx, &spec, true);
3886 if (rc < 0) {
12fb0da4
EC		 3887 if (rollback) {
3888 netif_info(efx, drv, efx->net_dev,
3889 "efx_ef10_filter_insert failed rc=%d\n",
3890 rc);
3891 /* Fall back to promiscuous */
3892 for (j = 0; j < i; j++) {
3893 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3894 continue;
3895 efx_ef10_filter_remove_unsafe(
3896 efx, EFX_FILTER_PRI_AUTO,
3897 addr_list[j].id);
3898 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3899 }
3900 return rc;
3901 } else {
3902 /* mark as not inserted, and carry on */
3903 rc = EFX_EF10_FILTER_ID_INVALID;
822b96f8 3904 }
8127d661 3905 }
12fb0da4 3906 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc);
8127d661 3907 }
822b96f8 3908
12fb0da4
EC		 3909 if (multicast && rollback) {
3910 /* Also need an Ethernet broadcast filter */
7665d1ab
BH		 3911 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3912 EFX_FILTER_FLAG_RX_RSS,
8127d661 3913 0);
12fb0da4
EC		 3914 eth_broadcast_addr(baddr);
3915 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr);
8127d661 3916 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 3917 if (rc < 0) {
822b96f8 3918 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 3919 "Broadcast filter insert failed rc=%d\n", rc);
3920 /* Fall back to promiscuous */
3921 for (j = 0; j < i; j++) {
3922 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3923 continue;
3924 efx_ef10_filter_remove_unsafe(
3925 efx, EFX_FILTER_PRI_AUTO,
3926 addr_list[j].id);
3927 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3928 }
3929 return rc;
3930 } else {
3931 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
3932 }
8127d661 3933 }
12fb0da4
EC		 3934
3935 return 0;
3936}
3937
3938static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast,
3939 bool rollback)
3940{
3941 struct efx_ef10_filter_table *table = efx->filter_state;
3942 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3943 struct efx_filter_spec spec;
3944 u8 baddr[ETH_ALEN];
3945 int rc;
3946
3947 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3948 EFX_FILTER_FLAG_RX_RSS,
3949 0);
3950
3951 if (multicast)
3952 efx_filter_set_mc_def(&spec);
3953 else
3954 efx_filter_set_uc_def(&spec);
3955
3956 rc = efx_ef10_filter_insert(efx, &spec, true);
3957 if (rc < 0) {
3958 netif_warn(efx, drv, efx->net_dev,
3959 "%scast mismatch filter insert failed rc=%d\n",
3960 multicast ? "Multi" : "Uni", rc);
3961 } else if (multicast) {
3962 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc);
3963 if (!nic_data->workaround_26807) {
3964 /* Also need an Ethernet broadcast filter */
3965 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3966 EFX_FILTER_FLAG_RX_RSS,
3967 0);
3968 eth_broadcast_addr(baddr);
3969 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3970 baddr);
3971 rc = efx_ef10_filter_insert(efx, &spec, true);
3972 if (rc < 0) {
3973 netif_warn(efx, drv, efx->net_dev,
3974 "Broadcast filter insert failed rc=%d\n",
3975 rc);
3976 if (rollback) {
3977 /* Roll back the mc_def filter */
3978 efx_ef10_filter_remove_unsafe(
3979 efx, EFX_FILTER_PRI_AUTO,
3980 table->mcdef_id);
3981 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3982 return rc;
3983 }
3984 } else {
3985 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
3986 }
3987 }
3988 rc = 0;
3989 } else {
3990 table->ucdef_id = rc;
3991 rc = 0;
3992 }
3993 return rc;
822b96f8
DP		 3994}
3995
3996/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
3997 * flag or removes these filters, we don't need to hold the filter_lock while
3998 * scanning for these filters.
3999 */
4000static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4001{
4002 struct efx_ef10_filter_table *table = efx->filter_state;
4003 bool remove_failed = false;
4004 int i;
8127d661 4005
8127d661
BH		 4006 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4007 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 4008 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
7665d1ab 4009 if (efx_ef10_filter_remove_internal(
fbd79120
BH		 4010 efx, 1U << EFX_FILTER_PRI_AUTO,
4011 i, true) < 0)
8127d661
BH		 4012 remove_failed = true;
4013 }
4014 }
4015 WARN_ON(remove_failed);
4016}
4017
7a186f47
DP		 4018static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4019{
4020 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4021 u8 mac_old[ETH_ALEN];
4022 int rc, rc2;
4023
4024 /* Only reconfigure a PF-created vport */
4025 if (is_zero_ether_addr(nic_data->vport_mac))
4026 return 0;
4027
4028 efx_device_detach_sync(efx);
4029 efx_net_stop(efx->net_dev);
4030 down_write(&efx->filter_sem);
4031 efx_ef10_filter_table_remove(efx);
4032 up_write(&efx->filter_sem);
4033
4034 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4035 if (rc)
4036 goto restore_filters;
4037
4038 ether_addr_copy(mac_old, nic_data->vport_mac);
4039 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4040 nic_data->vport_mac);
4041 if (rc)
4042 goto restore_vadaptor;
4043
4044 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4045 efx->net_dev->dev_addr);
4046 if (!rc) {
4047 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4048 } else {
4049 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4050 if (rc2) {
4051 /* Failed to add original MAC, so clear vport_mac */
4052 eth_zero_addr(nic_data->vport_mac);
4053 goto reset_nic;
4054 }
4055 }
4056
4057restore_vadaptor:
4058 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4059 if (rc2)
4060 goto reset_nic;
4061restore_filters:
4062 down_write(&efx->filter_sem);
4063 rc2 = efx_ef10_filter_table_probe(efx);
4064 up_write(&efx->filter_sem);
4065 if (rc2)
4066 goto reset_nic;
4067
4068 rc2 = efx_net_open(efx->net_dev);
4069 if (rc2)
4070 goto reset_nic;
4071
4072 netif_device_attach(efx->net_dev);
4073
4074 return rc;
4075
4076reset_nic:
4077 netif_err(efx, drv, efx->net_dev,
4078 "Failed to restore when changing MAC address - scheduling reset\n");
4079 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4080
4081 return rc ? rc : rc2;
4082}
4083
822b96f8
DP		 4084/* Caller must hold efx->filter_sem for read if race against
4085 * efx_ef10_filter_table_remove() is possible
4086 */
4087static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4088{
4089 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 4090 struct efx_ef10_nic_data *nic_data = efx->nic_data;
822b96f8
DP		 4091 struct net_device *net_dev = efx->net_dev;
4092 bool uc_promisc = false, mc_promisc = false;
4093
4094 if (!efx_dev_registered(efx))
4095 return;
4096
4097 if (!table)
4098 return;
4099
4100 efx_ef10_filter_mark_old(efx);
4101
4102 /* Copy/convert the address lists; add the primary station
4103 * address and broadcast address
4104 */
4105 netif_addr_lock_bh(net_dev);
4106 efx_ef10_filter_uc_addr_list(efx, &uc_promisc);
4107 efx_ef10_filter_mc_addr_list(efx, &mc_promisc);
4108 netif_addr_unlock_bh(net_dev);
4109
12fb0da4
EC		 4110 /* Insert/renew unicast filters */
4111 if (uc_promisc) {
4112 efx_ef10_filter_insert_def(efx, false, false);
4113 efx_ef10_filter_insert_addr_list(efx, false, false);
4114 } else {
4115 /* If any of the filters failed to insert, fall back to
4116 * promiscuous mode - add in the uc_def filter. But keep
4117 * our individual unicast filters.
4118 */
4119 if (efx_ef10_filter_insert_addr_list(efx, false, false))
4120 efx_ef10_filter_insert_def(efx, false, false);
4121 }
ab8b1f7c 4122
12fb0da4 4123 /* Insert/renew multicast filters */
ab8b1f7c
DP		 4124 /* If changing promiscuous state with cascaded multicast filters, remove
4125 * old filters first, so that packets are dropped rather than duplicated
4126 */
4127 if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc)
4128 efx_ef10_filter_remove_old(efx);
12fb0da4
EC		 4129 if (mc_promisc) {
4130 if (nic_data->workaround_26807) {
4131 /* If we failed to insert promiscuous filters, rollback
4132 * and fall back to individual multicast filters
4133 */
4134 if (efx_ef10_filter_insert_def(efx, true, true)) {
4135 /* Changing promisc state, so remove old filters */
4136 efx_ef10_filter_remove_old(efx);
4137 efx_ef10_filter_insert_addr_list(efx, true, false);
4138 }
4139 } else {
4140 /* If we failed to insert promiscuous filters, don't
4141 * rollback. Regardless, also insert the mc_list
4142 */
4143 efx_ef10_filter_insert_def(efx, true, false);
4144 efx_ef10_filter_insert_addr_list(efx, true, false);
4145 }
4146 } else {
4147 /* If any filters failed to insert, rollback and fall back to
4148 * promiscuous mode - mc_def filter and maybe broadcast. If
4149 * that fails, roll back again and insert as many of our
4150 * individual multicast filters as we can.
4151 */
4152 if (efx_ef10_filter_insert_addr_list(efx, true, true)) {
4153 /* Changing promisc state, so remove old filters */
4154 if (nic_data->workaround_26807)
4155 efx_ef10_filter_remove_old(efx);
4156 if (efx_ef10_filter_insert_def(efx, true, true))
4157 efx_ef10_filter_insert_addr_list(efx, true, false);
4158 }
4159 }
822b96f8
DP		 4160
4161 efx_ef10_filter_remove_old(efx);
ab8b1f7c 4162 efx->mc_promisc = mc_promisc;
822b96f8
DP		 4163}
4164
910c8789
SS		 4165static int efx_ef10_set_mac_address(struct efx_nic *efx)
4166{
4167 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4168 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4169 bool was_enabled = efx->port_enabled;
4170 int rc;
4171
4172 efx_device_detach_sync(efx);
4173 efx_net_stop(efx->net_dev);
4174 down_write(&efx->filter_sem);
4175 efx_ef10_filter_table_remove(efx);
4176
4177 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4178 efx->net_dev->dev_addr);
4179 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4180 nic_data->vport_id);
535a6177
DP		 4181 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4182 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 4183
4184 efx_ef10_filter_table_probe(efx);
4185 up_write(&efx->filter_sem);
4186 if (was_enabled)
4187 efx_net_open(efx->net_dev);
4188 netif_device_attach(efx->net_dev);
4189
9e9f665a
DP		 4190#ifdef CONFIG_SFC_SRIOV
4191 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 4192 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4193
9e9f665a
DP		 4194 if (rc == -EPERM) {
4195 struct efx_nic *efx_pf;
910c8789 4196
9e9f665a
DP		 4197 /* Switch to PF and change MAC address on vport */
4198 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 4199
9e9f665a
DP		 4200 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4201 nic_data->vf_index,
4202 efx->net_dev->dev_addr);
4203 } else if (!rc) {
910c8789
SS		 4204 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4205 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4206 unsigned int i;
4207
9e9f665a
DP		 4208 /* MAC address successfully changed by VF (with MAC
4209 * spoofing) so update the parent PF if possible.
4210 */
910c8789
SS		 4211 for (i = 0; i < efx_pf->vf_count; ++i) {
4212 struct ef10_vf *vf = nic_data->vf + i;
4213
4214 if (vf->efx == efx) {
4215 ether_addr_copy(vf->mac,
4216 efx->net_dev->dev_addr);
4217 return 0;
4218 }
4219 }
4220 }
9e9f665a 4221 } else
910c8789 4222#endif
9e9f665a
DP		 4223 if (rc == -EPERM) {
4224 netif_err(efx, drv, efx->net_dev,
4225 "Cannot change MAC address; use sfboot to enable"
4226 " mac-spoofing on this interface\n");
7a186f47
DP		 4227 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4228 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4229 * fall-back to the method of changing the MAC address on the
4230 * vport. This only applies to PFs because such versions of
4231 * MCFW do not support VFs.
4232 */
4233 rc = efx_ef10_vport_set_mac_address(efx);
535a6177
DP		 4234 } else {
4235 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4236 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 4237 }
4238
910c8789
SS		 4239 return rc;
4240}
4241
8127d661
BH		 4242static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4243{
4244 efx_ef10_filter_sync_rx_mode(efx);
4245
4246 return efx_mcdi_set_mac(efx);
4247}
4248
862f894c
SS		 4249static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4250{
4251 efx_ef10_filter_sync_rx_mode(efx);
4252
4253 return 0;
4254}
4255
74cd60a4
JC		 4256static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4257{
4258 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4259
4260 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4261 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4262 NULL, 0, NULL);
4263}
4264
4265/* MC BISTs follow a different poll mechanism to phy BISTs.
4266 * The BIST is done in the poll handler on the MC, and the MCDI command
4267 * will block until the BIST is done.
4268 */
4269static int efx_ef10_poll_bist(struct efx_nic *efx)
4270{
4271 int rc;
4272 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4273 size_t outlen;
4274 u32 result;
4275
4276 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4277 outbuf, sizeof(outbuf), &outlen);
4278 if (rc != 0)
4279 return rc;
4280
4281 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4282 return -EIO;
4283
4284 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4285 switch (result) {
4286 case MC_CMD_POLL_BIST_PASSED:
4287 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4288 return 0;
4289 case MC_CMD_POLL_BIST_TIMEOUT:
4290 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4291 return -EIO;
4292 case MC_CMD_POLL_BIST_FAILED:
4293 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4294 return -EIO;
4295 default:
4296 netif_err(efx, hw, efx->net_dev,
4297 "BIST returned unknown result %u", result);
4298 return -EIO;
4299 }
4300}
4301
4302static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4303{
4304 int rc;
4305
4306 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4307
4308 rc = efx_ef10_start_bist(efx, bist_type);
4309 if (rc != 0)
4310 return rc;
4311
4312 return efx_ef10_poll_bist(efx);
4313}
4314
4315static int
4316efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4317{
4318 int rc, rc2;
4319
4320 efx_reset_down(efx, RESET_TYPE_WORLD);
4321
4322 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4323 NULL, 0, NULL, 0, NULL);
4324 if (rc != 0)
4325 goto out;
4326
4327 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4328 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4329
4330 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4331
4332out:
27324820
DP		 4333 if (rc == -EPERM)
4334 rc = 0;
74cd60a4
JC		 4335 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4336 return rc ? rc : rc2;
4337}
4338
8127d661
BH		 4339#ifdef CONFIG_SFC_MTD
4340
4341struct efx_ef10_nvram_type_info {
4342 u16 type, type_mask;
4343 u8 port;
4344 const char *name;
4345};
4346
4347static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4348 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
4349 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
4350 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
4351 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
4352 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
4353 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
4354 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
4355 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
4356 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 4357 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 4358 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
4359};
4360
4361static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4362 struct efx_mcdi_mtd_partition *part,
4363 unsigned int type)
4364{
4365 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4366 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4367 const struct efx_ef10_nvram_type_info *info;
4368 size_t size, erase_size, outlen;
4369 bool protected;
4370 int rc;
4371
4372 for (info = efx_ef10_nvram_types; ; info++) {
4373 if (info ==
4374 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4375 return -ENODEV;
4376 if ((type & ~info->type_mask) == info->type)
4377 break;
4378 }
4379 if (info->port != efx_port_num(efx))
4380 return -ENODEV;
4381
4382 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4383 if (rc)
4384 return rc;
4385 if (protected)
4386 return -ENODEV; /* hide it */
4387
4388 part->nvram_type = type;
4389
4390 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4391 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4392 outbuf, sizeof(outbuf), &outlen);
4393 if (rc)
4394 return rc;
4395 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4396 return -EIO;
4397 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4398 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4399 part->fw_subtype = MCDI_DWORD(outbuf,
4400 NVRAM_METADATA_OUT_SUBTYPE);
4401
4402 part->common.dev_type_name = "EF10 NVRAM manager";
4403 part->common.type_name = info->name;
4404
4405 part->common.mtd.type = MTD_NORFLASH;
4406 part->common.mtd.flags = MTD_CAP_NORFLASH;
4407 part->common.mtd.size = size;
4408 part->common.mtd.erasesize = erase_size;
4409
4410 return 0;
4411}
4412
4413static int efx_ef10_mtd_probe(struct efx_nic *efx)
4414{
4415 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4416 struct efx_mcdi_mtd_partition *parts;
4417 size_t outlen, n_parts_total, i, n_parts;
4418 unsigned int type;
4419 int rc;
4420
4421 ASSERT_RTNL();
4422
4423 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4424 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4425 outbuf, sizeof(outbuf), &outlen);
4426 if (rc)
4427 return rc;
4428 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4429 return -EIO;
4430
4431 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4432 if (n_parts_total >
4433 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4434 return -EIO;
4435
4436 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4437 if (!parts)
4438 return -ENOMEM;
4439
4440 n_parts = 0;
4441 for (i = 0; i < n_parts_total; i++) {
4442 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4443 i);
4444 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4445 if (rc == 0)
4446 n_parts++;
4447 else if (rc != -ENODEV)
4448 goto fail;
4449 }
4450
4451 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4452fail:
4453 if (rc)
4454 kfree(parts);
4455 return rc;
4456}
4457
4458#endif /* CONFIG_SFC_MTD */
4459
4460static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4461{
4462 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4463}
4464
02246a7f
SS		 4465static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4466 u32 host_time) {}
4467
bd9a265d
JC		 4468static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4469 bool temp)
4470{
4471 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4472 int rc;
4473
4474 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4475 channel->sync_events_state == SYNC_EVENTS_VALID ||
4476 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4477 return 0;
4478 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4479
4480 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4481 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4482 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4483 channel->channel);
4484
4485 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4486 inbuf, sizeof(inbuf), NULL, 0, NULL);
4487
4488 if (rc != 0)
4489 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4490 SYNC_EVENTS_DISABLED;
4491
4492 return rc;
4493}
4494
4495static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4496 bool temp)
4497{
4498 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4499 int rc;
4500
4501 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4502 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4503 return 0;
4504 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
4505 channel->sync_events_state = SYNC_EVENTS_DISABLED;
4506 return 0;
4507 }
4508 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4509 SYNC_EVENTS_DISABLED;
4510
4511 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4512 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4513 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4514 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4515 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4516 channel->channel);
4517
4518 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4519 inbuf, sizeof(inbuf), NULL, 0, NULL);
4520
4521 return rc;
4522}
4523
4524static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4525 bool temp)
4526{
4527 int (*set)(struct efx_channel *channel, bool temp);
4528 struct efx_channel *channel;
4529
4530 set = en ?
4531 efx_ef10_rx_enable_timestamping :
4532 efx_ef10_rx_disable_timestamping;
4533
4534 efx_for_each_channel(channel, efx) {
4535 int rc = set(channel, temp);
4536 if (en && rc != 0) {
4537 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4538 return rc;
4539 }
4540 }
4541
4542 return 0;
4543}
4544
02246a7f
SS		 4545static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4546 struct hwtstamp_config *init)
4547{
4548 return -EOPNOTSUPP;
4549}
4550
bd9a265d
JC		 4551static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4552 struct hwtstamp_config *init)
4553{
4554 int rc;
4555
4556 switch (init->rx_filter) {
4557 case HWTSTAMP_FILTER_NONE:
4558 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4559 /* if TX timestamping is still requested then leave PTP on */
4560 return efx_ptp_change_mode(efx,
4561 init->tx_type != HWTSTAMP_TX_OFF, 0);
4562 case HWTSTAMP_FILTER_ALL:
4563 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4564 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4565 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4566 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4567 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4568 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4569 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4570 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4571 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4572 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4573 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4574 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4575 init->rx_filter = HWTSTAMP_FILTER_ALL;
4576 rc = efx_ptp_change_mode(efx, true, 0);
4577 if (!rc)
4578 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4579 if (rc)
4580 efx_ptp_change_mode(efx, false, 0);
4581 return rc;
4582 default:
4583 return -ERANGE;
4584 }
4585}
4586
02246a7f 4587const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 4588 .is_vf = true,
02246a7f
SS		 4589 .mem_bar = EFX_MEM_VF_BAR,
4590 .mem_map_size = efx_ef10_mem_map_size,
4591 .probe = efx_ef10_probe_vf,
4592 .remove = efx_ef10_remove,
4593 .dimension_resources = efx_ef10_dimension_resources,
4594 .init = efx_ef10_init_nic,
4595 .fini = efx_port_dummy_op_void,
087e9025 4596 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 4597 .map_reset_flags = efx_ef10_map_reset_flags,
4598 .reset = efx_ef10_reset,
4599 .probe_port = efx_mcdi_port_probe,
4600 .remove_port = efx_mcdi_port_remove,
4601 .fini_dmaq = efx_ef10_fini_dmaq,
4602 .prepare_flr = efx_ef10_prepare_flr,
4603 .finish_flr = efx_port_dummy_op_void,
4604 .describe_stats = efx_ef10_describe_stats,
d7788196 4605 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 4606 .start_stats = efx_port_dummy_op_void,
4607 .pull_stats = efx_port_dummy_op_void,
4608 .stop_stats = efx_port_dummy_op_void,
4609 .set_id_led = efx_mcdi_set_id_led,
4610 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 4611 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 4612 .check_mac_fault = efx_mcdi_mac_check_fault,
4613 .reconfigure_port = efx_mcdi_port_reconfigure,
4614 .get_wol = efx_ef10_get_wol_vf,
4615 .set_wol = efx_ef10_set_wol_vf,
4616 .resume_wol = efx_port_dummy_op_void,
4617 .mcdi_request = efx_ef10_mcdi_request,
4618 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4619 .mcdi_read_response = efx_ef10_mcdi_read_response,
4620 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4621 .irq_enable_master = efx_port_dummy_op_void,
4622 .irq_test_generate = efx_ef10_irq_test_generate,
4623 .irq_disable_non_ev = efx_port_dummy_op_void,
4624 .irq_handle_msi = efx_ef10_msi_interrupt,
4625 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4626 .tx_probe = efx_ef10_tx_probe,
4627 .tx_init = efx_ef10_tx_init,
4628 .tx_remove = efx_ef10_tx_remove,
4629 .tx_write = efx_ef10_tx_write,
267c0157 4630 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
02246a7f
SS		 4631 .rx_probe = efx_ef10_rx_probe,
4632 .rx_init = efx_ef10_rx_init,
4633 .rx_remove = efx_ef10_rx_remove,
4634 .rx_write = efx_ef10_rx_write,
4635 .rx_defer_refill = efx_ef10_rx_defer_refill,
4636 .ev_probe = efx_ef10_ev_probe,
4637 .ev_init = efx_ef10_ev_init,
4638 .ev_fini = efx_ef10_ev_fini,
4639 .ev_remove = efx_ef10_ev_remove,
4640 .ev_process = efx_ef10_ev_process,
4641 .ev_read_ack = efx_ef10_ev_read_ack,
4642 .ev_test_generate = efx_ef10_ev_test_generate,
4643 .filter_table_probe = efx_ef10_filter_table_probe,
4644 .filter_table_restore = efx_ef10_filter_table_restore,
4645 .filter_table_remove = efx_ef10_filter_table_remove,
4646 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4647 .filter_insert = efx_ef10_filter_insert,
4648 .filter_remove_safe = efx_ef10_filter_remove_safe,
4649 .filter_get_safe = efx_ef10_filter_get_safe,
4650 .filter_clear_rx = efx_ef10_filter_clear_rx,
4651 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4652 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4653 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4654#ifdef CONFIG_RFS_ACCEL
4655 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4656 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4657#endif
4658#ifdef CONFIG_SFC_MTD
4659 .mtd_probe = efx_port_dummy_op_int,
4660#endif
4661 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4662 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4663#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 4664 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4665 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4666 .vswitching_remove = efx_ef10_vswitching_remove_vf,
1d051e00 4667 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
02246a7f 4668#endif
0d5e0fbb 4669 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 4670 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 4671
02246a7f
SS		 4672 .revision = EFX_REV_HUNT_A0,
4673 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4674 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4675 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4676 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4677 .can_rx_scatter = true,
4678 .always_rx_scatter = true,
4679 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4680 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4681 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4682 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4683 .mcdi_max_ver = 2,
4684 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4685 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4686 1 << HWTSTAMP_FILTER_ALL,
4687};
4688
8127d661 4689const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 4690 .is_vf = false,
02246a7f 4691 .mem_bar = EFX_MEM_BAR,
8127d661 4692 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 4693 .probe = efx_ef10_probe_pf,
8127d661
BH		 4694 .remove = efx_ef10_remove,
4695 .dimension_resources = efx_ef10_dimension_resources,
4696 .init = efx_ef10_init_nic,
4697 .fini = efx_port_dummy_op_void,
087e9025 4698 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 4699 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 4700 .reset = efx_ef10_reset,
8127d661
BH		 4701 .probe_port = efx_mcdi_port_probe,
4702 .remove_port = efx_mcdi_port_remove,
4703 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 4704 .prepare_flr = efx_ef10_prepare_flr,
4705 .finish_flr = efx_port_dummy_op_void,
8127d661 4706 .describe_stats = efx_ef10_describe_stats,
d7788196 4707 .update_stats = efx_ef10_update_stats_pf,
8127d661 4708 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 4709 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 4710 .stop_stats = efx_mcdi_mac_stop_stats,
4711 .set_id_led = efx_mcdi_set_id_led,
4712 .push_irq_moderation = efx_ef10_push_irq_moderation,
4713 .reconfigure_mac = efx_ef10_mac_reconfigure,
4714 .check_mac_fault = efx_mcdi_mac_check_fault,
4715 .reconfigure_port = efx_mcdi_port_reconfigure,
4716 .get_wol = efx_ef10_get_wol,
4717 .set_wol = efx_ef10_set_wol,
4718 .resume_wol = efx_port_dummy_op_void,
74cd60a4 4719 .test_chip = efx_ef10_test_chip,
8127d661
BH		 4720 .test_nvram = efx_mcdi_nvram_test_all,
4721 .mcdi_request = efx_ef10_mcdi_request,
4722 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4723 .mcdi_read_response = efx_ef10_mcdi_read_response,
4724 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4725 .irq_enable_master = efx_port_dummy_op_void,
4726 .irq_test_generate = efx_ef10_irq_test_generate,
4727 .irq_disable_non_ev = efx_port_dummy_op_void,
4728 .irq_handle_msi = efx_ef10_msi_interrupt,
4729 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4730 .tx_probe = efx_ef10_tx_probe,
4731 .tx_init = efx_ef10_tx_init,
4732 .tx_remove = efx_ef10_tx_remove,
4733 .tx_write = efx_ef10_tx_write,
267c0157 4734 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
8127d661
BH		 4735 .rx_probe = efx_ef10_rx_probe,
4736 .rx_init = efx_ef10_rx_init,
4737 .rx_remove = efx_ef10_rx_remove,
4738 .rx_write = efx_ef10_rx_write,
4739 .rx_defer_refill = efx_ef10_rx_defer_refill,
4740 .ev_probe = efx_ef10_ev_probe,
4741 .ev_init = efx_ef10_ev_init,
4742 .ev_fini = efx_ef10_ev_fini,
4743 .ev_remove = efx_ef10_ev_remove,
4744 .ev_process = efx_ef10_ev_process,
4745 .ev_read_ack = efx_ef10_ev_read_ack,
4746 .ev_test_generate = efx_ef10_ev_test_generate,
4747 .filter_table_probe = efx_ef10_filter_table_probe,
4748 .filter_table_restore = efx_ef10_filter_table_restore,
4749 .filter_table_remove = efx_ef10_filter_table_remove,
4750 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4751 .filter_insert = efx_ef10_filter_insert,
4752 .filter_remove_safe = efx_ef10_filter_remove_safe,
4753 .filter_get_safe = efx_ef10_filter_get_safe,
4754 .filter_clear_rx = efx_ef10_filter_clear_rx,
4755 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4756 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4757 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4758#ifdef CONFIG_RFS_ACCEL
4759 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4760 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4761#endif
4762#ifdef CONFIG_SFC_MTD
4763 .mtd_probe = efx_ef10_mtd_probe,
4764 .mtd_rename = efx_mcdi_mtd_rename,
4765 .mtd_read = efx_mcdi_mtd_read,
4766 .mtd_erase = efx_mcdi_mtd_erase,
4767 .mtd_write = efx_mcdi_mtd_write,
4768 .mtd_sync = efx_mcdi_mtd_sync,
4769#endif
4770 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 4771 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4772 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
7fa8d547 4773#ifdef CONFIG_SFC_SRIOV
834e23dd 4774 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 4775 .sriov_init = efx_ef10_sriov_init,
4776 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 4777 .sriov_wanted = efx_ef10_sriov_wanted,
4778 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 4779 .sriov_flr = efx_ef10_sriov_flr,
4780 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4781 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4782 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4783 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 4784 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 4785 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4786 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4787 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 4788#endif
0d5e0fbb 4789 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 4790 .set_mac_address = efx_ef10_set_mac_address,
8127d661
BH		 4791
4792 .revision = EFX_REV_HUNT_A0,
4793 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4794 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4795 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 4796 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 4797 .can_rx_scatter = true,
4798 .always_rx_scatter = true,
4799 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4800 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4801 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4802 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4803 .mcdi_max_ver = 2,
4804 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 4805 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4806 1 << HWTSTAMP_FILTER_ALL,
8127d661 4807};
Linux kernel - Deliverables
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