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8127d661 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare network controllers and boards | |
3 | * Copyright 2012-2013 Solarflare Communications Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include "net_driver.h" | |
11 | #include "ef10_regs.h" | |
12 | #include "io.h" | |
13 | #include "mcdi.h" | |
14 | #include "mcdi_pcol.h" | |
15 | #include "nic.h" | |
16 | #include "workarounds.h" | |
74cd60a4 | 17 | #include "selftest.h" |
7fa8d547 | 18 | #include "ef10_sriov.h" |
8127d661 BH |
19 | #include <linux/in.h> |
20 | #include <linux/jhash.h> | |
21 | #include <linux/wait.h> | |
22 | #include <linux/workqueue.h> | |
23 | ||
24 | /* Hardware control for EF10 architecture including 'Huntington'. */ | |
25 | ||
26 | #define EFX_EF10_DRVGEN_EV 7 | |
27 | enum { | |
28 | EFX_EF10_TEST = 1, | |
29 | EFX_EF10_REFILL, | |
30 | }; | |
31 | ||
32 | /* The reserved RSS context value */ | |
33 | #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff | |
34 | ||
35 | /* The filter table(s) are managed by firmware and we have write-only | |
36 | * access. When removing filters we must identify them to the | |
37 | * firmware by a 64-bit handle, but this is too wide for Linux kernel | |
38 | * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to | |
39 | * be able to tell in advance whether a requested insertion will | |
40 | * replace an existing filter. Therefore we maintain a software hash | |
41 | * table, which should be at least as large as the hardware hash | |
42 | * table. | |
43 | * | |
44 | * Huntington has a single 8K filter table shared between all filter | |
45 | * types and both ports. | |
46 | */ | |
47 | #define HUNT_FILTER_TBL_ROWS 8192 | |
48 | ||
49 | struct efx_ef10_filter_table { | |
50 | /* The RX match field masks supported by this fw & hw, in order of priority */ | |
51 | enum efx_filter_match_flags rx_match_flags[ | |
52 | MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; | |
53 | unsigned int rx_match_count; | |
54 | ||
55 | struct { | |
56 | unsigned long spec; /* pointer to spec plus flag bits */ | |
b59e6ef8 BH |
57 | /* BUSY flag indicates that an update is in progress. AUTO_OLD is |
58 | * used to mark and sweep MAC filters for the device address lists. | |
8127d661 BH |
59 | */ |
60 | #define EFX_EF10_FILTER_FLAG_BUSY 1UL | |
b59e6ef8 | 61 | #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL |
8127d661 BH |
62 | #define EFX_EF10_FILTER_FLAGS 3UL |
63 | u64 handle; /* firmware handle */ | |
64 | } *entry; | |
65 | wait_queue_head_t waitq; | |
66 | /* Shadow of net_device address lists, guarded by mac_lock */ | |
b59e6ef8 BH |
67 | #define EFX_EF10_FILTER_DEV_UC_MAX 32 |
68 | #define EFX_EF10_FILTER_DEV_MC_MAX 256 | |
8127d661 BH |
69 | struct { |
70 | u8 addr[ETH_ALEN]; | |
71 | u16 id; | |
b59e6ef8 BH |
72 | } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX], |
73 | dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; | |
74 | int dev_uc_count; /* negative for PROMISC */ | |
75 | int dev_mc_count; /* negative for PROMISC/ALLMULTI */ | |
8127d661 BH |
76 | }; |
77 | ||
78 | /* An arbitrary search limit for the software hash table */ | |
79 | #define EFX_EF10_FILTER_SEARCH_LIMIT 200 | |
80 | ||
d43050c0 | 81 | static void efx_ef10_rx_push_rss_config(struct efx_nic *efx); |
8127d661 BH |
82 | static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); |
83 | static void efx_ef10_filter_table_remove(struct efx_nic *efx); | |
84 | ||
85 | static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) | |
86 | { | |
87 | efx_dword_t reg; | |
88 | ||
89 | efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); | |
90 | return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? | |
91 | EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; | |
92 | } | |
93 | ||
94 | static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) | |
95 | { | |
02246a7f SS |
96 | int bar; |
97 | ||
98 | bar = efx->type->mem_bar; | |
99 | return resource_size(&efx->pci_dev->resource[bar]); | |
8127d661 BH |
100 | } |
101 | ||
1cd9ecbb DP |
102 | static int efx_ef10_get_pf_index(struct efx_nic *efx) |
103 | { | |
104 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); | |
105 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
106 | size_t outlen; | |
107 | int rc; | |
108 | ||
109 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, | |
110 | sizeof(outbuf), &outlen); | |
111 | if (rc) | |
112 | return rc; | |
113 | if (outlen < sizeof(outbuf)) | |
114 | return -EIO; | |
115 | ||
116 | nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF); | |
117 | return 0; | |
118 | } | |
119 | ||
e5a2538a | 120 | static int efx_ef10_init_datapath_caps(struct efx_nic *efx) |
8127d661 BH |
121 | { |
122 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN); | |
123 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
124 | size_t outlen; | |
125 | int rc; | |
126 | ||
127 | BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); | |
128 | ||
129 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, | |
130 | outbuf, sizeof(outbuf), &outlen); | |
131 | if (rc) | |
132 | return rc; | |
e5a2538a BH |
133 | if (outlen < sizeof(outbuf)) { |
134 | netif_err(efx, drv, efx->net_dev, | |
135 | "unable to read datapath firmware capabilities\n"); | |
136 | return -EIO; | |
137 | } | |
138 | ||
139 | nic_data->datapath_caps = | |
140 | MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); | |
8127d661 | 141 | |
8d9f9dd4 DP |
142 | /* record the DPCPU firmware IDs to determine VEB vswitching support. |
143 | */ | |
144 | nic_data->rx_dpcpu_fw_id = | |
145 | MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); | |
146 | nic_data->tx_dpcpu_fw_id = | |
147 | MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); | |
148 | ||
e5a2538a BH |
149 | if (!(nic_data->datapath_caps & |
150 | (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) { | |
151 | netif_err(efx, drv, efx->net_dev, | |
152 | "current firmware does not support TSO\n"); | |
153 | return -ENODEV; | |
154 | } | |
155 | ||
156 | if (!(nic_data->datapath_caps & | |
157 | (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { | |
158 | netif_err(efx, probe, efx->net_dev, | |
159 | "current firmware does not support an RX prefix\n"); | |
160 | return -ENODEV; | |
8127d661 BH |
161 | } |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) | |
167 | { | |
168 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); | |
169 | int rc; | |
170 | ||
171 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, | |
172 | outbuf, sizeof(outbuf), NULL); | |
173 | if (rc) | |
174 | return rc; | |
175 | rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); | |
176 | return rc > 0 ? rc : -ERANGE; | |
177 | } | |
178 | ||
179 | static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address) | |
180 | { | |
181 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); | |
182 | size_t outlen; | |
183 | int rc; | |
184 | ||
185 | BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); | |
186 | ||
187 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, | |
188 | outbuf, sizeof(outbuf), &outlen); | |
189 | if (rc) | |
190 | return rc; | |
191 | if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) | |
192 | return -EIO; | |
193 | ||
cd84ff4d EC |
194 | ether_addr_copy(mac_address, |
195 | MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); | |
8127d661 BH |
196 | return 0; |
197 | } | |
198 | ||
199 | static int efx_ef10_probe(struct efx_nic *efx) | |
200 | { | |
201 | struct efx_ef10_nic_data *nic_data; | |
202 | int i, rc; | |
203 | ||
aa3930ee BH |
204 | /* We can have one VI for each 8K region. However, until we |
205 | * use TX option descriptors we need two TX queues per channel. | |
8127d661 BH |
206 | */ |
207 | efx->max_channels = | |
208 | min_t(unsigned int, | |
209 | EFX_MAX_CHANNELS, | |
02246a7f | 210 | efx_ef10_mem_map_size(efx) / |
8127d661 | 211 | (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); |
9fd3d3a4 EC |
212 | if (WARN_ON(efx->max_channels == 0)) |
213 | return -EIO; | |
8127d661 BH |
214 | |
215 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
216 | if (!nic_data) | |
217 | return -ENOMEM; | |
218 | efx->nic_data = nic_data; | |
219 | ||
220 | rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, | |
221 | 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); | |
222 | if (rc) | |
223 | goto fail1; | |
224 | ||
225 | /* Get the MC's warm boot count. In case it's rebooting right | |
226 | * now, be prepared to retry. | |
227 | */ | |
228 | i = 0; | |
229 | for (;;) { | |
230 | rc = efx_ef10_get_warm_boot_count(efx); | |
231 | if (rc >= 0) | |
232 | break; | |
233 | if (++i == 5) | |
234 | goto fail2; | |
235 | ssleep(1); | |
236 | } | |
237 | nic_data->warm_boot_count = rc; | |
238 | ||
239 | nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; | |
240 | ||
45b2449e DP |
241 | nic_data->vport_id = EVB_PORT_ID_ASSIGNED; |
242 | ||
8127d661 BH |
243 | /* In case we're recovering from a crash (kexec), we want to |
244 | * cancel any outstanding request by the previous user of this | |
245 | * function. We send a special message using the least | |
246 | * significant bits of the 'high' (doorbell) register. | |
247 | */ | |
248 | _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); | |
249 | ||
250 | rc = efx_mcdi_init(efx); | |
251 | if (rc) | |
252 | goto fail2; | |
253 | ||
254 | /* Reset (most) configuration for this function */ | |
255 | rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); | |
256 | if (rc) | |
257 | goto fail3; | |
258 | ||
259 | /* Enable event logging */ | |
260 | rc = efx_mcdi_log_ctrl(efx, true, false, 0); | |
261 | if (rc) | |
262 | goto fail3; | |
263 | ||
1cd9ecbb DP |
264 | rc = efx_ef10_get_pf_index(efx); |
265 | if (rc) | |
266 | goto fail3; | |
267 | ||
e5a2538a | 268 | rc = efx_ef10_init_datapath_caps(efx); |
8127d661 BH |
269 | if (rc < 0) |
270 | goto fail3; | |
271 | ||
272 | efx->rx_packet_len_offset = | |
273 | ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; | |
274 | ||
8127d661 BH |
275 | rc = efx_mcdi_port_get_number(efx); |
276 | if (rc < 0) | |
277 | goto fail3; | |
278 | efx->port_num = rc; | |
279 | ||
280 | rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr); | |
281 | if (rc) | |
282 | goto fail3; | |
283 | ||
284 | rc = efx_ef10_get_sysclk_freq(efx); | |
285 | if (rc < 0) | |
286 | goto fail3; | |
287 | efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */ | |
288 | ||
289 | /* Check whether firmware supports bug 35388 workaround */ | |
290 | rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true); | |
291 | if (rc == 0) | |
292 | nic_data->workaround_35388 = true; | |
293 | else if (rc != -ENOSYS && rc != -ENOENT) | |
294 | goto fail3; | |
295 | netif_dbg(efx, probe, efx->net_dev, | |
296 | "workaround for bug 35388 is %sabled\n", | |
297 | nic_data->workaround_35388 ? "en" : "dis"); | |
298 | ||
299 | rc = efx_mcdi_mon_probe(efx); | |
300 | if (rc) | |
301 | goto fail3; | |
302 | ||
9aecda95 BH |
303 | efx_ptp_probe(efx, NULL); |
304 | ||
8127d661 BH |
305 | return 0; |
306 | ||
307 | fail3: | |
308 | efx_mcdi_fini(efx); | |
309 | fail2: | |
310 | efx_nic_free_buffer(efx, &nic_data->mcdi_buf); | |
311 | fail1: | |
312 | kfree(nic_data); | |
313 | efx->nic_data = NULL; | |
314 | return rc; | |
315 | } | |
316 | ||
02246a7f SS |
317 | static int efx_ef10_probe_pf(struct efx_nic *efx) |
318 | { | |
319 | return efx_ef10_probe(efx); | |
320 | } | |
321 | ||
322 | #ifdef CONFIG_SFC_SRIOV | |
323 | static int efx_ef10_probe_vf(struct efx_nic *efx) | |
324 | { | |
325 | return efx_ef10_probe(efx); | |
326 | } | |
327 | #else | |
328 | static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) | |
329 | { | |
330 | return 0; | |
331 | } | |
332 | #endif | |
333 | ||
8127d661 BH |
334 | static int efx_ef10_free_vis(struct efx_nic *efx) |
335 | { | |
1e0b8120 EC |
336 | MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0); |
337 | size_t outlen; | |
338 | int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, | |
339 | outbuf, sizeof(outbuf), &outlen); | |
8127d661 BH |
340 | |
341 | /* -EALREADY means nothing to free, so ignore */ | |
342 | if (rc == -EALREADY) | |
343 | rc = 0; | |
1e0b8120 EC |
344 | if (rc) |
345 | efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, | |
346 | rc); | |
8127d661 BH |
347 | return rc; |
348 | } | |
349 | ||
183233be BH |
350 | #ifdef EFX_USE_PIO |
351 | ||
352 | static void efx_ef10_free_piobufs(struct efx_nic *efx) | |
353 | { | |
354 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
355 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); | |
356 | unsigned int i; | |
357 | int rc; | |
358 | ||
359 | BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); | |
360 | ||
361 | for (i = 0; i < nic_data->n_piobufs; i++) { | |
362 | MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, | |
363 | nic_data->piobuf_handle[i]); | |
364 | rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), | |
365 | NULL, 0, NULL); | |
366 | WARN_ON(rc); | |
367 | } | |
368 | ||
369 | nic_data->n_piobufs = 0; | |
370 | } | |
371 | ||
372 | static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) | |
373 | { | |
374 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
375 | MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); | |
376 | unsigned int i; | |
377 | size_t outlen; | |
378 | int rc = 0; | |
379 | ||
380 | BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); | |
381 | ||
382 | for (i = 0; i < n; i++) { | |
383 | rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, | |
384 | outbuf, sizeof(outbuf), &outlen); | |
385 | if (rc) | |
386 | break; | |
387 | if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { | |
388 | rc = -EIO; | |
389 | break; | |
390 | } | |
391 | nic_data->piobuf_handle[i] = | |
392 | MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); | |
393 | netif_dbg(efx, probe, efx->net_dev, | |
394 | "allocated PIO buffer %u handle %x\n", i, | |
395 | nic_data->piobuf_handle[i]); | |
396 | } | |
397 | ||
398 | nic_data->n_piobufs = i; | |
399 | if (rc) | |
400 | efx_ef10_free_piobufs(efx); | |
401 | return rc; | |
402 | } | |
403 | ||
404 | static int efx_ef10_link_piobufs(struct efx_nic *efx) | |
405 | { | |
406 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
407 | MCDI_DECLARE_BUF(inbuf, | |
408 | max(MC_CMD_LINK_PIOBUF_IN_LEN, | |
409 | MC_CMD_UNLINK_PIOBUF_IN_LEN)); | |
410 | struct efx_channel *channel; | |
411 | struct efx_tx_queue *tx_queue; | |
412 | unsigned int offset, index; | |
413 | int rc; | |
414 | ||
415 | BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); | |
416 | BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); | |
417 | ||
418 | /* Link a buffer to each VI in the write-combining mapping */ | |
419 | for (index = 0; index < nic_data->n_piobufs; ++index) { | |
420 | MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, | |
421 | nic_data->piobuf_handle[index]); | |
422 | MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, | |
423 | nic_data->pio_write_vi_base + index); | |
424 | rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, | |
425 | inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, | |
426 | NULL, 0, NULL); | |
427 | if (rc) { | |
428 | netif_err(efx, drv, efx->net_dev, | |
429 | "failed to link VI %u to PIO buffer %u (%d)\n", | |
430 | nic_data->pio_write_vi_base + index, index, | |
431 | rc); | |
432 | goto fail; | |
433 | } | |
434 | netif_dbg(efx, probe, efx->net_dev, | |
435 | "linked VI %u to PIO buffer %u\n", | |
436 | nic_data->pio_write_vi_base + index, index); | |
437 | } | |
438 | ||
439 | /* Link a buffer to each TX queue */ | |
440 | efx_for_each_channel(channel, efx) { | |
441 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
442 | /* We assign the PIO buffers to queues in | |
443 | * reverse order to allow for the following | |
444 | * special case. | |
445 | */ | |
446 | offset = ((efx->tx_channel_offset + efx->n_tx_channels - | |
447 | tx_queue->channel->channel - 1) * | |
448 | efx_piobuf_size); | |
449 | index = offset / ER_DZ_TX_PIOBUF_SIZE; | |
450 | offset = offset % ER_DZ_TX_PIOBUF_SIZE; | |
451 | ||
452 | /* When the host page size is 4K, the first | |
453 | * host page in the WC mapping may be within | |
454 | * the same VI page as the last TX queue. We | |
455 | * can only link one buffer to each VI. | |
456 | */ | |
457 | if (tx_queue->queue == nic_data->pio_write_vi_base) { | |
458 | BUG_ON(index != 0); | |
459 | rc = 0; | |
460 | } else { | |
461 | MCDI_SET_DWORD(inbuf, | |
462 | LINK_PIOBUF_IN_PIOBUF_HANDLE, | |
463 | nic_data->piobuf_handle[index]); | |
464 | MCDI_SET_DWORD(inbuf, | |
465 | LINK_PIOBUF_IN_TXQ_INSTANCE, | |
466 | tx_queue->queue); | |
467 | rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, | |
468 | inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, | |
469 | NULL, 0, NULL); | |
470 | } | |
471 | ||
472 | if (rc) { | |
473 | /* This is non-fatal; the TX path just | |
474 | * won't use PIO for this queue | |
475 | */ | |
476 | netif_err(efx, drv, efx->net_dev, | |
477 | "failed to link VI %u to PIO buffer %u (%d)\n", | |
478 | tx_queue->queue, index, rc); | |
479 | tx_queue->piobuf = NULL; | |
480 | } else { | |
481 | tx_queue->piobuf = | |
482 | nic_data->pio_write_base + | |
483 | index * EFX_VI_PAGE_SIZE + offset; | |
484 | tx_queue->piobuf_offset = offset; | |
485 | netif_dbg(efx, probe, efx->net_dev, | |
486 | "linked VI %u to PIO buffer %u offset %x addr %p\n", | |
487 | tx_queue->queue, index, | |
488 | tx_queue->piobuf_offset, | |
489 | tx_queue->piobuf); | |
490 | } | |
491 | } | |
492 | } | |
493 | ||
494 | return 0; | |
495 | ||
496 | fail: | |
497 | while (index--) { | |
498 | MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, | |
499 | nic_data->pio_write_vi_base + index); | |
500 | efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, | |
501 | inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, | |
502 | NULL, 0, NULL); | |
503 | } | |
504 | return rc; | |
505 | } | |
506 | ||
507 | #else /* !EFX_USE_PIO */ | |
508 | ||
509 | static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) | |
510 | { | |
511 | return n == 0 ? 0 : -ENOBUFS; | |
512 | } | |
513 | ||
514 | static int efx_ef10_link_piobufs(struct efx_nic *efx) | |
515 | { | |
516 | return 0; | |
517 | } | |
518 | ||
519 | static void efx_ef10_free_piobufs(struct efx_nic *efx) | |
520 | { | |
521 | } | |
522 | ||
523 | #endif /* EFX_USE_PIO */ | |
524 | ||
8127d661 BH |
525 | static void efx_ef10_remove(struct efx_nic *efx) |
526 | { | |
527 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
528 | int rc; | |
529 | ||
9aecda95 BH |
530 | efx_ptp_remove(efx); |
531 | ||
8127d661 BH |
532 | efx_mcdi_mon_remove(efx); |
533 | ||
8127d661 BH |
534 | efx_ef10_rx_free_indir_table(efx); |
535 | ||
183233be BH |
536 | if (nic_data->wc_membase) |
537 | iounmap(nic_data->wc_membase); | |
538 | ||
8127d661 BH |
539 | rc = efx_ef10_free_vis(efx); |
540 | WARN_ON(rc != 0); | |
541 | ||
183233be BH |
542 | if (!nic_data->must_restore_piobufs) |
543 | efx_ef10_free_piobufs(efx); | |
544 | ||
8127d661 BH |
545 | efx_mcdi_fini(efx); |
546 | efx_nic_free_buffer(efx, &nic_data->mcdi_buf); | |
547 | kfree(nic_data); | |
548 | } | |
549 | ||
550 | static int efx_ef10_alloc_vis(struct efx_nic *efx, | |
551 | unsigned int min_vis, unsigned int max_vis) | |
552 | { | |
553 | MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); | |
554 | MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); | |
555 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
556 | size_t outlen; | |
557 | int rc; | |
558 | ||
559 | MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); | |
560 | MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); | |
561 | rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), | |
562 | outbuf, sizeof(outbuf), &outlen); | |
563 | if (rc != 0) | |
564 | return rc; | |
565 | ||
566 | if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) | |
567 | return -EIO; | |
568 | ||
569 | netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", | |
570 | MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); | |
571 | ||
572 | nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); | |
573 | nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); | |
574 | return 0; | |
575 | } | |
576 | ||
183233be BH |
577 | /* Note that the failure path of this function does not free |
578 | * resources, as this will be done by efx_ef10_remove(). | |
579 | */ | |
8127d661 BH |
580 | static int efx_ef10_dimension_resources(struct efx_nic *efx) |
581 | { | |
183233be BH |
582 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
583 | unsigned int uc_mem_map_size, wc_mem_map_size; | |
584 | unsigned int min_vis, pio_write_vi_base, max_vis; | |
585 | void __iomem *membase; | |
586 | int rc; | |
587 | ||
588 | min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); | |
8127d661 | 589 | |
183233be BH |
590 | #ifdef EFX_USE_PIO |
591 | /* Try to allocate PIO buffers if wanted and if the full | |
592 | * number of PIO buffers would be sufficient to allocate one | |
593 | * copy-buffer per TX channel. Failure is non-fatal, as there | |
594 | * are only a small number of PIO buffers shared between all | |
595 | * functions of the controller. | |
596 | */ | |
597 | if (efx_piobuf_size != 0 && | |
598 | ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= | |
599 | efx->n_tx_channels) { | |
600 | unsigned int n_piobufs = | |
601 | DIV_ROUND_UP(efx->n_tx_channels, | |
602 | ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); | |
603 | ||
604 | rc = efx_ef10_alloc_piobufs(efx, n_piobufs); | |
605 | if (rc) | |
606 | netif_err(efx, probe, efx->net_dev, | |
607 | "failed to allocate PIO buffers (%d)\n", rc); | |
608 | else | |
609 | netif_dbg(efx, probe, efx->net_dev, | |
610 | "allocated %u PIO buffers\n", n_piobufs); | |
611 | } | |
612 | #else | |
613 | nic_data->n_piobufs = 0; | |
614 | #endif | |
615 | ||
616 | /* PIO buffers should be mapped with write-combining enabled, | |
617 | * and we want to make single UC and WC mappings rather than | |
618 | * several of each (in fact that's the only option if host | |
619 | * page size is >4K). So we may allocate some extra VIs just | |
620 | * for writing PIO buffers through. | |
52ad762b DP |
621 | * |
622 | * The UC mapping contains (min_vis - 1) complete VIs and the | |
623 | * first half of the next VI. Then the WC mapping begins with | |
624 | * the second half of this last VI. | |
183233be BH |
625 | */ |
626 | uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE + | |
627 | ER_DZ_TX_PIOBUF); | |
628 | if (nic_data->n_piobufs) { | |
52ad762b DP |
629 | /* pio_write_vi_base rounds down to give the number of complete |
630 | * VIs inside the UC mapping. | |
631 | */ | |
183233be BH |
632 | pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; |
633 | wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + | |
634 | nic_data->n_piobufs) * | |
635 | EFX_VI_PAGE_SIZE) - | |
636 | uc_mem_map_size); | |
637 | max_vis = pio_write_vi_base + nic_data->n_piobufs; | |
638 | } else { | |
639 | pio_write_vi_base = 0; | |
640 | wc_mem_map_size = 0; | |
641 | max_vis = min_vis; | |
642 | } | |
643 | ||
644 | /* In case the last attached driver failed to free VIs, do it now */ | |
645 | rc = efx_ef10_free_vis(efx); | |
646 | if (rc != 0) | |
647 | return rc; | |
648 | ||
649 | rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); | |
650 | if (rc != 0) | |
651 | return rc; | |
652 | ||
653 | /* If we didn't get enough VIs to map all the PIO buffers, free the | |
654 | * PIO buffers | |
655 | */ | |
656 | if (nic_data->n_piobufs && | |
657 | nic_data->n_allocated_vis < | |
658 | pio_write_vi_base + nic_data->n_piobufs) { | |
659 | netif_dbg(efx, probe, efx->net_dev, | |
660 | "%u VIs are not sufficient to map %u PIO buffers\n", | |
661 | nic_data->n_allocated_vis, nic_data->n_piobufs); | |
662 | efx_ef10_free_piobufs(efx); | |
663 | } | |
664 | ||
665 | /* Shrink the original UC mapping of the memory BAR */ | |
666 | membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); | |
667 | if (!membase) { | |
668 | netif_err(efx, probe, efx->net_dev, | |
669 | "could not shrink memory BAR to %x\n", | |
670 | uc_mem_map_size); | |
671 | return -ENOMEM; | |
672 | } | |
673 | iounmap(efx->membase); | |
674 | efx->membase = membase; | |
675 | ||
676 | /* Set up the WC mapping if needed */ | |
677 | if (wc_mem_map_size) { | |
678 | nic_data->wc_membase = ioremap_wc(efx->membase_phys + | |
679 | uc_mem_map_size, | |
680 | wc_mem_map_size); | |
681 | if (!nic_data->wc_membase) { | |
682 | netif_err(efx, probe, efx->net_dev, | |
683 | "could not allocate WC mapping of size %x\n", | |
684 | wc_mem_map_size); | |
685 | return -ENOMEM; | |
686 | } | |
687 | nic_data->pio_write_vi_base = pio_write_vi_base; | |
688 | nic_data->pio_write_base = | |
689 | nic_data->wc_membase + | |
690 | (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - | |
691 | uc_mem_map_size); | |
692 | ||
693 | rc = efx_ef10_link_piobufs(efx); | |
694 | if (rc) | |
695 | efx_ef10_free_piobufs(efx); | |
696 | } | |
697 | ||
698 | netif_dbg(efx, probe, efx->net_dev, | |
699 | "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", | |
700 | &efx->membase_phys, efx->membase, uc_mem_map_size, | |
701 | nic_data->wc_membase, wc_mem_map_size); | |
702 | ||
703 | return 0; | |
8127d661 BH |
704 | } |
705 | ||
706 | static int efx_ef10_init_nic(struct efx_nic *efx) | |
707 | { | |
708 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
709 | int rc; | |
710 | ||
a915ccc9 BH |
711 | if (nic_data->must_check_datapath_caps) { |
712 | rc = efx_ef10_init_datapath_caps(efx); | |
713 | if (rc) | |
714 | return rc; | |
715 | nic_data->must_check_datapath_caps = false; | |
716 | } | |
717 | ||
8127d661 BH |
718 | if (nic_data->must_realloc_vis) { |
719 | /* We cannot let the number of VIs change now */ | |
720 | rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, | |
721 | nic_data->n_allocated_vis); | |
722 | if (rc) | |
723 | return rc; | |
724 | nic_data->must_realloc_vis = false; | |
725 | } | |
726 | ||
183233be BH |
727 | if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { |
728 | rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); | |
729 | if (rc == 0) { | |
730 | rc = efx_ef10_link_piobufs(efx); | |
731 | if (rc) | |
732 | efx_ef10_free_piobufs(efx); | |
733 | } | |
734 | ||
735 | /* Log an error on failure, but this is non-fatal */ | |
736 | if (rc) | |
737 | netif_err(efx, drv, efx->net_dev, | |
738 | "failed to restore PIO buffers (%d)\n", rc); | |
739 | nic_data->must_restore_piobufs = false; | |
740 | } | |
741 | ||
d43050c0 | 742 | efx_ef10_rx_push_rss_config(efx); |
8127d661 BH |
743 | return 0; |
744 | } | |
745 | ||
3e336261 JC |
746 | static void efx_ef10_reset_mc_allocations(struct efx_nic *efx) |
747 | { | |
748 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
749 | ||
750 | /* All our allocations have been reset */ | |
751 | nic_data->must_realloc_vis = true; | |
752 | nic_data->must_restore_filters = true; | |
753 | nic_data->must_restore_piobufs = true; | |
754 | nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; | |
755 | } | |
756 | ||
8127d661 BH |
757 | static int efx_ef10_map_reset_flags(u32 *flags) |
758 | { | |
759 | enum { | |
760 | EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << | |
761 | ETH_RESET_SHARED_SHIFT), | |
762 | EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | | |
763 | ETH_RESET_OFFLOAD | ETH_RESET_MAC | | |
764 | ETH_RESET_PHY | ETH_RESET_MGMT) << | |
765 | ETH_RESET_SHARED_SHIFT) | |
766 | }; | |
767 | ||
768 | /* We assume for now that our PCI function is permitted to | |
769 | * reset everything. | |
770 | */ | |
771 | ||
772 | if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { | |
773 | *flags &= ~EF10_RESET_MC; | |
774 | return RESET_TYPE_WORLD; | |
775 | } | |
776 | ||
777 | if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { | |
778 | *flags &= ~EF10_RESET_PORT; | |
779 | return RESET_TYPE_ALL; | |
780 | } | |
781 | ||
782 | /* no invisible reset implemented */ | |
783 | ||
784 | return -EINVAL; | |
785 | } | |
786 | ||
3e336261 JC |
787 | static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) |
788 | { | |
789 | int rc = efx_mcdi_reset(efx, reset_type); | |
790 | ||
791 | /* If it was a port reset, trigger reallocation of MC resources. | |
792 | * Note that on an MC reset nothing needs to be done now because we'll | |
793 | * detect the MC reset later and handle it then. | |
e283546c EC |
794 | * For an FLR, we never get an MC reset event, but the MC has reset all |
795 | * resources assigned to us, so we have to trigger reallocation now. | |
3e336261 | 796 | */ |
e283546c EC |
797 | if ((reset_type == RESET_TYPE_ALL || |
798 | reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) | |
3e336261 JC |
799 | efx_ef10_reset_mc_allocations(efx); |
800 | return rc; | |
801 | } | |
802 | ||
8127d661 BH |
803 | #define EF10_DMA_STAT(ext_name, mcdi_name) \ |
804 | [EF10_STAT_ ## ext_name] = \ | |
805 | { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } | |
806 | #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ | |
807 | [EF10_STAT_ ## int_name] = \ | |
808 | { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } | |
809 | #define EF10_OTHER_STAT(ext_name) \ | |
810 | [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } | |
e4d112e4 EC |
811 | #define GENERIC_SW_STAT(ext_name) \ |
812 | [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } | |
8127d661 BH |
813 | |
814 | static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { | |
815 | EF10_DMA_STAT(tx_bytes, TX_BYTES), | |
816 | EF10_DMA_STAT(tx_packets, TX_PKTS), | |
817 | EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS), | |
818 | EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS), | |
819 | EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS), | |
820 | EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS), | |
821 | EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS), | |
822 | EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS), | |
823 | EF10_DMA_STAT(tx_64, TX_64_PKTS), | |
824 | EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS), | |
825 | EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS), | |
826 | EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS), | |
827 | EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS), | |
828 | EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), | |
829 | EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), | |
830 | EF10_DMA_STAT(rx_bytes, RX_BYTES), | |
831 | EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES), | |
832 | EF10_OTHER_STAT(rx_good_bytes), | |
833 | EF10_OTHER_STAT(rx_bad_bytes), | |
834 | EF10_DMA_STAT(rx_packets, RX_PKTS), | |
835 | EF10_DMA_STAT(rx_good, RX_GOOD_PKTS), | |
836 | EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS), | |
837 | EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS), | |
838 | EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS), | |
839 | EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS), | |
840 | EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS), | |
841 | EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS), | |
842 | EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS), | |
843 | EF10_DMA_STAT(rx_64, RX_64_PKTS), | |
844 | EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS), | |
845 | EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS), | |
846 | EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS), | |
847 | EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS), | |
848 | EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), | |
849 | EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), | |
850 | EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS), | |
851 | EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS), | |
852 | EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS), | |
853 | EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS), | |
854 | EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS), | |
855 | EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS), | |
e4d112e4 EC |
856 | GENERIC_SW_STAT(rx_nodesc_trunc), |
857 | GENERIC_SW_STAT(rx_noskb_drops), | |
568d7a00 EC |
858 | EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), |
859 | EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), | |
860 | EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), | |
861 | EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), | |
862 | EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB), | |
863 | EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB), | |
864 | EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING), | |
865 | EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), | |
866 | EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), | |
867 | EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS), | |
79ac47ae SS |
868 | EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS), |
869 | EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS), | |
8127d661 BH |
870 | }; |
871 | ||
872 | #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \ | |
873 | (1ULL << EF10_STAT_tx_packets) | \ | |
874 | (1ULL << EF10_STAT_tx_pause) | \ | |
875 | (1ULL << EF10_STAT_tx_unicast) | \ | |
876 | (1ULL << EF10_STAT_tx_multicast) | \ | |
877 | (1ULL << EF10_STAT_tx_broadcast) | \ | |
878 | (1ULL << EF10_STAT_rx_bytes) | \ | |
879 | (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \ | |
880 | (1ULL << EF10_STAT_rx_good_bytes) | \ | |
881 | (1ULL << EF10_STAT_rx_bad_bytes) | \ | |
882 | (1ULL << EF10_STAT_rx_packets) | \ | |
883 | (1ULL << EF10_STAT_rx_good) | \ | |
884 | (1ULL << EF10_STAT_rx_bad) | \ | |
885 | (1ULL << EF10_STAT_rx_pause) | \ | |
886 | (1ULL << EF10_STAT_rx_control) | \ | |
887 | (1ULL << EF10_STAT_rx_unicast) | \ | |
888 | (1ULL << EF10_STAT_rx_multicast) | \ | |
889 | (1ULL << EF10_STAT_rx_broadcast) | \ | |
890 | (1ULL << EF10_STAT_rx_lt64) | \ | |
891 | (1ULL << EF10_STAT_rx_64) | \ | |
892 | (1ULL << EF10_STAT_rx_65_to_127) | \ | |
893 | (1ULL << EF10_STAT_rx_128_to_255) | \ | |
894 | (1ULL << EF10_STAT_rx_256_to_511) | \ | |
895 | (1ULL << EF10_STAT_rx_512_to_1023) | \ | |
896 | (1ULL << EF10_STAT_rx_1024_to_15xx) | \ | |
897 | (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \ | |
898 | (1ULL << EF10_STAT_rx_gtjumbo) | \ | |
899 | (1ULL << EF10_STAT_rx_bad_gtjumbo) | \ | |
900 | (1ULL << EF10_STAT_rx_overflow) | \ | |
e4d112e4 EC |
901 | (1ULL << EF10_STAT_rx_nodesc_drops) | \ |
902 | (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ | |
903 | (1ULL << GENERIC_STAT_rx_noskb_drops)) | |
8127d661 BH |
904 | |
905 | /* These statistics are only provided by the 10G MAC. For a 10G/40G | |
906 | * switchable port we do not expose these because they might not | |
907 | * include all the packets they should. | |
908 | */ | |
909 | #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \ | |
910 | (1ULL << EF10_STAT_tx_lt64) | \ | |
911 | (1ULL << EF10_STAT_tx_64) | \ | |
912 | (1ULL << EF10_STAT_tx_65_to_127) | \ | |
913 | (1ULL << EF10_STAT_tx_128_to_255) | \ | |
914 | (1ULL << EF10_STAT_tx_256_to_511) | \ | |
915 | (1ULL << EF10_STAT_tx_512_to_1023) | \ | |
916 | (1ULL << EF10_STAT_tx_1024_to_15xx) | \ | |
917 | (1ULL << EF10_STAT_tx_15xx_to_jumbo)) | |
918 | ||
919 | /* These statistics are only provided by the 40G MAC. For a 10G/40G | |
920 | * switchable port we do expose these because the errors will otherwise | |
921 | * be silent. | |
922 | */ | |
923 | #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \ | |
924 | (1ULL << EF10_STAT_rx_length_error)) | |
925 | ||
568d7a00 EC |
926 | /* These statistics are only provided if the firmware supports the |
927 | * capability PM_AND_RXDP_COUNTERS. | |
928 | */ | |
929 | #define HUNT_PM_AND_RXDP_STAT_MASK ( \ | |
930 | (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \ | |
931 | (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \ | |
932 | (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \ | |
933 | (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \ | |
934 | (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \ | |
935 | (1ULL << EF10_STAT_rx_pm_discard_qbb) | \ | |
936 | (1ULL << EF10_STAT_rx_pm_discard_mapping) | \ | |
937 | (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \ | |
938 | (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \ | |
939 | (1ULL << EF10_STAT_rx_dp_streaming_packets) | \ | |
79ac47ae SS |
940 | (1ULL << EF10_STAT_rx_dp_hlb_fetch) | \ |
941 | (1ULL << EF10_STAT_rx_dp_hlb_wait)) | |
568d7a00 | 942 | |
4bae913b | 943 | static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) |
8127d661 | 944 | { |
4bae913b | 945 | u64 raw_mask = HUNT_COMMON_STAT_MASK; |
8127d661 | 946 | u32 port_caps = efx_mcdi_phy_get_caps(efx); |
568d7a00 | 947 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
8127d661 BH |
948 | |
949 | if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) | |
4bae913b | 950 | raw_mask |= HUNT_40G_EXTRA_STAT_MASK; |
8127d661 | 951 | else |
4bae913b | 952 | raw_mask |= HUNT_10G_ONLY_STAT_MASK; |
568d7a00 EC |
953 | |
954 | if (nic_data->datapath_caps & | |
955 | (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) | |
956 | raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; | |
957 | ||
4bae913b EC |
958 | return raw_mask; |
959 | } | |
960 | ||
961 | static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) | |
962 | { | |
963 | u64 raw_mask = efx_ef10_raw_stat_mask(efx); | |
964 | ||
965 | #if BITS_PER_LONG == 64 | |
966 | mask[0] = raw_mask; | |
967 | #else | |
968 | mask[0] = raw_mask & 0xffffffff; | |
969 | mask[1] = raw_mask >> 32; | |
970 | #endif | |
8127d661 BH |
971 | } |
972 | ||
973 | static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) | |
974 | { | |
4bae913b EC |
975 | DECLARE_BITMAP(mask, EF10_STAT_COUNT); |
976 | ||
977 | efx_ef10_get_stat_mask(efx, mask); | |
8127d661 | 978 | return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, |
4bae913b | 979 | mask, names); |
8127d661 BH |
980 | } |
981 | ||
982 | static int efx_ef10_try_update_nic_stats(struct efx_nic *efx) | |
983 | { | |
984 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
4bae913b | 985 | DECLARE_BITMAP(mask, EF10_STAT_COUNT); |
8127d661 BH |
986 | __le64 generation_start, generation_end; |
987 | u64 *stats = nic_data->stats; | |
988 | __le64 *dma_stats; | |
989 | ||
4bae913b EC |
990 | efx_ef10_get_stat_mask(efx, mask); |
991 | ||
8127d661 BH |
992 | dma_stats = efx->stats_buffer.addr; |
993 | nic_data = efx->nic_data; | |
994 | ||
995 | generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; | |
996 | if (generation_end == EFX_MC_STATS_GENERATION_INVALID) | |
997 | return 0; | |
998 | rmb(); | |
4bae913b | 999 | efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, |
8127d661 | 1000 | stats, efx->stats_buffer.addr, false); |
d546a893 | 1001 | rmb(); |
8127d661 BH |
1002 | generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; |
1003 | if (generation_end != generation_start) | |
1004 | return -EAGAIN; | |
1005 | ||
1006 | /* Update derived statistics */ | |
f8f3b5ae | 1007 | efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]); |
8127d661 BH |
1008 | stats[EF10_STAT_rx_good_bytes] = |
1009 | stats[EF10_STAT_rx_bytes] - | |
1010 | stats[EF10_STAT_rx_bytes_minus_good_bytes]; | |
1011 | efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes], | |
1012 | stats[EF10_STAT_rx_bytes_minus_good_bytes]); | |
e4d112e4 | 1013 | efx_update_sw_stats(efx, stats); |
8127d661 BH |
1014 | return 0; |
1015 | } | |
1016 | ||
1017 | ||
1018 | static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats, | |
1019 | struct rtnl_link_stats64 *core_stats) | |
1020 | { | |
4bae913b | 1021 | DECLARE_BITMAP(mask, EF10_STAT_COUNT); |
8127d661 BH |
1022 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
1023 | u64 *stats = nic_data->stats; | |
1024 | size_t stats_count = 0, index; | |
1025 | int retry; | |
1026 | ||
4bae913b EC |
1027 | efx_ef10_get_stat_mask(efx, mask); |
1028 | ||
8127d661 BH |
1029 | /* If we're unlucky enough to read statistics during the DMA, wait |
1030 | * up to 10ms for it to finish (typically takes <500us) | |
1031 | */ | |
1032 | for (retry = 0; retry < 100; ++retry) { | |
1033 | if (efx_ef10_try_update_nic_stats(efx) == 0) | |
1034 | break; | |
1035 | udelay(100); | |
1036 | } | |
1037 | ||
1038 | if (full_stats) { | |
1039 | for_each_set_bit(index, mask, EF10_STAT_COUNT) { | |
1040 | if (efx_ef10_stat_desc[index].name) { | |
1041 | *full_stats++ = stats[index]; | |
1042 | ++stats_count; | |
1043 | } | |
1044 | } | |
1045 | } | |
1046 | ||
1047 | if (core_stats) { | |
1048 | core_stats->rx_packets = stats[EF10_STAT_rx_packets]; | |
1049 | core_stats->tx_packets = stats[EF10_STAT_tx_packets]; | |
1050 | core_stats->rx_bytes = stats[EF10_STAT_rx_bytes]; | |
1051 | core_stats->tx_bytes = stats[EF10_STAT_tx_bytes]; | |
e4d112e4 EC |
1052 | core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops] + |
1053 | stats[GENERIC_STAT_rx_nodesc_trunc] + | |
1054 | stats[GENERIC_STAT_rx_noskb_drops]; | |
8127d661 BH |
1055 | core_stats->multicast = stats[EF10_STAT_rx_multicast]; |
1056 | core_stats->rx_length_errors = | |
1057 | stats[EF10_STAT_rx_gtjumbo] + | |
1058 | stats[EF10_STAT_rx_length_error]; | |
1059 | core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; | |
1060 | core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error]; | |
1061 | core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; | |
1062 | core_stats->rx_errors = (core_stats->rx_length_errors + | |
1063 | core_stats->rx_crc_errors + | |
1064 | core_stats->rx_frame_errors); | |
1065 | } | |
1066 | ||
1067 | return stats_count; | |
1068 | } | |
1069 | ||
1070 | static void efx_ef10_push_irq_moderation(struct efx_channel *channel) | |
1071 | { | |
1072 | struct efx_nic *efx = channel->efx; | |
1073 | unsigned int mode, value; | |
1074 | efx_dword_t timer_cmd; | |
1075 | ||
1076 | if (channel->irq_moderation) { | |
1077 | mode = 3; | |
1078 | value = channel->irq_moderation - 1; | |
1079 | } else { | |
1080 | mode = 0; | |
1081 | value = 0; | |
1082 | } | |
1083 | ||
1084 | if (EFX_EF10_WORKAROUND_35388(efx)) { | |
1085 | EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, | |
1086 | EFE_DD_EVQ_IND_TIMER_FLAGS, | |
1087 | ERF_DD_EVQ_IND_TIMER_MODE, mode, | |
1088 | ERF_DD_EVQ_IND_TIMER_VAL, value); | |
1089 | efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, | |
1090 | channel->channel); | |
1091 | } else { | |
1092 | EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, | |
1093 | ERF_DZ_TC_TIMER_VAL, value); | |
1094 | efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, | |
1095 | channel->channel); | |
1096 | } | |
1097 | } | |
1098 | ||
02246a7f SS |
1099 | static void efx_ef10_get_wol_vf(struct efx_nic *efx, |
1100 | struct ethtool_wolinfo *wol) {} | |
1101 | ||
1102 | static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) | |
1103 | { | |
1104 | return -EOPNOTSUPP; | |
1105 | } | |
1106 | ||
8127d661 BH |
1107 | static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) |
1108 | { | |
1109 | wol->supported = 0; | |
1110 | wol->wolopts = 0; | |
1111 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
1112 | } | |
1113 | ||
1114 | static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) | |
1115 | { | |
1116 | if (type != 0) | |
1117 | return -EINVAL; | |
1118 | return 0; | |
1119 | } | |
1120 | ||
1121 | static void efx_ef10_mcdi_request(struct efx_nic *efx, | |
1122 | const efx_dword_t *hdr, size_t hdr_len, | |
1123 | const efx_dword_t *sdu, size_t sdu_len) | |
1124 | { | |
1125 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1126 | u8 *pdu = nic_data->mcdi_buf.addr; | |
1127 | ||
1128 | memcpy(pdu, hdr, hdr_len); | |
1129 | memcpy(pdu + hdr_len, sdu, sdu_len); | |
1130 | wmb(); | |
1131 | ||
1132 | /* The hardware provides 'low' and 'high' (doorbell) registers | |
1133 | * for passing the 64-bit address of an MCDI request to | |
1134 | * firmware. However the dwords are swapped by firmware. The | |
1135 | * least significant bits of the doorbell are then 0 for all | |
1136 | * MCDI requests due to alignment. | |
1137 | */ | |
1138 | _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), | |
1139 | ER_DZ_MC_DB_LWRD); | |
1140 | _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), | |
1141 | ER_DZ_MC_DB_HWRD); | |
1142 | } | |
1143 | ||
1144 | static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) | |
1145 | { | |
1146 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1147 | const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; | |
1148 | ||
1149 | rmb(); | |
1150 | return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); | |
1151 | } | |
1152 | ||
1153 | static void | |
1154 | efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, | |
1155 | size_t offset, size_t outlen) | |
1156 | { | |
1157 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1158 | const u8 *pdu = nic_data->mcdi_buf.addr; | |
1159 | ||
1160 | memcpy(outbuf, pdu + offset, outlen); | |
1161 | } | |
1162 | ||
1163 | static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) | |
1164 | { | |
1165 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1166 | int rc; | |
1167 | ||
1168 | rc = efx_ef10_get_warm_boot_count(efx); | |
1169 | if (rc < 0) { | |
1170 | /* The firmware is presumably in the process of | |
1171 | * rebooting. However, we are supposed to report each | |
1172 | * reboot just once, so we must only do that once we | |
1173 | * can read and store the updated warm boot count. | |
1174 | */ | |
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | if (rc == nic_data->warm_boot_count) | |
1179 | return 0; | |
1180 | ||
1181 | nic_data->warm_boot_count = rc; | |
1182 | ||
1183 | /* All our allocations have been reset */ | |
3e336261 | 1184 | efx_ef10_reset_mc_allocations(efx); |
8127d661 | 1185 | |
6d8aaaf6 DP |
1186 | /* Driver-created vswitches and vports must be re-created */ |
1187 | nic_data->must_probe_vswitching = true; | |
1188 | nic_data->vport_id = EVB_PORT_ID_ASSIGNED; | |
1189 | ||
a915ccc9 BH |
1190 | /* The datapath firmware might have been changed */ |
1191 | nic_data->must_check_datapath_caps = true; | |
1192 | ||
869070c5 BH |
1193 | /* MAC statistics have been cleared on the NIC; clear the local |
1194 | * statistic that we update with efx_update_diff_stat(). | |
1195 | */ | |
1196 | nic_data->stats[EF10_STAT_rx_bad_bytes] = 0; | |
1197 | ||
8127d661 BH |
1198 | return -EIO; |
1199 | } | |
1200 | ||
1201 | /* Handle an MSI interrupt | |
1202 | * | |
1203 | * Handle an MSI hardware interrupt. This routine schedules event | |
1204 | * queue processing. No interrupt acknowledgement cycle is necessary. | |
1205 | * Also, we never need to check that the interrupt is for us, since | |
1206 | * MSI interrupts cannot be shared. | |
1207 | */ | |
1208 | static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) | |
1209 | { | |
1210 | struct efx_msi_context *context = dev_id; | |
1211 | struct efx_nic *efx = context->efx; | |
1212 | ||
1213 | netif_vdbg(efx, intr, efx->net_dev, | |
1214 | "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); | |
1215 | ||
1216 | if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { | |
1217 | /* Note test interrupts */ | |
1218 | if (context->index == efx->irq_level) | |
1219 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1220 | ||
1221 | /* Schedule processing of the channel */ | |
1222 | efx_schedule_channel_irq(efx->channel[context->index]); | |
1223 | } | |
1224 | ||
1225 | return IRQ_HANDLED; | |
1226 | } | |
1227 | ||
1228 | static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) | |
1229 | { | |
1230 | struct efx_nic *efx = dev_id; | |
1231 | bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); | |
1232 | struct efx_channel *channel; | |
1233 | efx_dword_t reg; | |
1234 | u32 queues; | |
1235 | ||
1236 | /* Read the ISR which also ACKs the interrupts */ | |
1237 | efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); | |
1238 | queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); | |
1239 | ||
1240 | if (queues == 0) | |
1241 | return IRQ_NONE; | |
1242 | ||
1243 | if (likely(soft_enabled)) { | |
1244 | /* Note test interrupts */ | |
1245 | if (queues & (1U << efx->irq_level)) | |
1246 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1247 | ||
1248 | efx_for_each_channel(channel, efx) { | |
1249 | if (queues & 1) | |
1250 | efx_schedule_channel_irq(channel); | |
1251 | queues >>= 1; | |
1252 | } | |
1253 | } | |
1254 | ||
1255 | netif_vdbg(efx, intr, efx->net_dev, | |
1256 | "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", | |
1257 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); | |
1258 | ||
1259 | return IRQ_HANDLED; | |
1260 | } | |
1261 | ||
1262 | static void efx_ef10_irq_test_generate(struct efx_nic *efx) | |
1263 | { | |
1264 | MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); | |
1265 | ||
1266 | BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); | |
1267 | ||
1268 | MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); | |
1269 | (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, | |
1270 | inbuf, sizeof(inbuf), NULL, 0, NULL); | |
1271 | } | |
1272 | ||
1273 | static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) | |
1274 | { | |
1275 | return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, | |
1276 | (tx_queue->ptr_mask + 1) * | |
1277 | sizeof(efx_qword_t), | |
1278 | GFP_KERNEL); | |
1279 | } | |
1280 | ||
1281 | /* This writes to the TX_DESC_WPTR and also pushes data */ | |
1282 | static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, | |
1283 | const efx_qword_t *txd) | |
1284 | { | |
1285 | unsigned int write_ptr; | |
1286 | efx_oword_t reg; | |
1287 | ||
1288 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; | |
1289 | EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); | |
1290 | reg.qword[0] = *txd; | |
1291 | efx_writeo_page(tx_queue->efx, ®, | |
1292 | ER_DZ_TX_DESC_UPD, tx_queue->queue); | |
1293 | } | |
1294 | ||
1295 | static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) | |
1296 | { | |
1297 | MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / | |
1298 | EFX_BUF_SIZE)); | |
1299 | MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN); | |
1300 | bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; | |
1301 | size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; | |
1302 | struct efx_channel *channel = tx_queue->channel; | |
1303 | struct efx_nic *efx = tx_queue->efx; | |
45b2449e | 1304 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
8127d661 BH |
1305 | size_t inlen, outlen; |
1306 | dma_addr_t dma_addr; | |
1307 | efx_qword_t *txd; | |
1308 | int rc; | |
1309 | int i; | |
1310 | ||
1311 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); | |
1312 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); | |
1313 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); | |
1314 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); | |
1315 | MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS, | |
1316 | INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, | |
1317 | INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); | |
1318 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); | |
45b2449e | 1319 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id); |
8127d661 BH |
1320 | |
1321 | dma_addr = tx_queue->txd.buf.dma_addr; | |
1322 | ||
1323 | netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", | |
1324 | tx_queue->queue, entries, (u64)dma_addr); | |
1325 | ||
1326 | for (i = 0; i < entries; ++i) { | |
1327 | MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); | |
1328 | dma_addr += EFX_BUF_SIZE; | |
1329 | } | |
1330 | ||
1331 | inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); | |
1332 | ||
1333 | rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen, | |
1334 | outbuf, sizeof(outbuf), &outlen); | |
1335 | if (rc) | |
1336 | goto fail; | |
1337 | ||
1338 | /* A previous user of this TX queue might have set us up the | |
1339 | * bomb by writing a descriptor to the TX push collector but | |
1340 | * not the doorbell. (Each collector belongs to a port, not a | |
1341 | * queue or function, so cannot easily be reset.) We must | |
1342 | * attempt to push a no-op descriptor in its place. | |
1343 | */ | |
1344 | tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; | |
1345 | tx_queue->insert_count = 1; | |
1346 | txd = efx_tx_desc(tx_queue, 0); | |
1347 | EFX_POPULATE_QWORD_4(*txd, | |
1348 | ESF_DZ_TX_DESC_IS_OPT, true, | |
1349 | ESF_DZ_TX_OPTION_TYPE, | |
1350 | ESE_DZ_TX_OPTION_DESC_CRC_CSUM, | |
1351 | ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, | |
1352 | ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); | |
1353 | tx_queue->write_count = 1; | |
1354 | wmb(); | |
1355 | efx_ef10_push_tx_desc(tx_queue, txd); | |
1356 | ||
1357 | return; | |
1358 | ||
1359 | fail: | |
48ce5634 BH |
1360 | netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", |
1361 | tx_queue->queue); | |
8127d661 BH |
1362 | } |
1363 | ||
1364 | static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) | |
1365 | { | |
1366 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); | |
1367 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN); | |
1368 | struct efx_nic *efx = tx_queue->efx; | |
1369 | size_t outlen; | |
1370 | int rc; | |
1371 | ||
1372 | MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, | |
1373 | tx_queue->queue); | |
1374 | ||
1e0b8120 | 1375 | rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), |
8127d661 BH |
1376 | outbuf, sizeof(outbuf), &outlen); |
1377 | ||
1378 | if (rc && rc != -EALREADY) | |
1379 | goto fail; | |
1380 | ||
1381 | return; | |
1382 | ||
1383 | fail: | |
1e0b8120 EC |
1384 | efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, |
1385 | outbuf, outlen, rc); | |
8127d661 BH |
1386 | } |
1387 | ||
1388 | static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) | |
1389 | { | |
1390 | efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); | |
1391 | } | |
1392 | ||
1393 | /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ | |
1394 | static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) | |
1395 | { | |
1396 | unsigned int write_ptr; | |
1397 | efx_dword_t reg; | |
1398 | ||
1399 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; | |
1400 | EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); | |
1401 | efx_writed_page(tx_queue->efx, ®, | |
1402 | ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); | |
1403 | } | |
1404 | ||
1405 | static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) | |
1406 | { | |
1407 | unsigned int old_write_count = tx_queue->write_count; | |
1408 | struct efx_tx_buffer *buffer; | |
1409 | unsigned int write_ptr; | |
1410 | efx_qword_t *txd; | |
1411 | ||
1412 | BUG_ON(tx_queue->write_count == tx_queue->insert_count); | |
1413 | ||
1414 | do { | |
1415 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; | |
1416 | buffer = &tx_queue->buffer[write_ptr]; | |
1417 | txd = efx_tx_desc(tx_queue, write_ptr); | |
1418 | ++tx_queue->write_count; | |
1419 | ||
1420 | /* Create TX descriptor ring entry */ | |
1421 | if (buffer->flags & EFX_TX_BUF_OPTION) { | |
1422 | *txd = buffer->option; | |
1423 | } else { | |
1424 | BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); | |
1425 | EFX_POPULATE_QWORD_3( | |
1426 | *txd, | |
1427 | ESF_DZ_TX_KER_CONT, | |
1428 | buffer->flags & EFX_TX_BUF_CONT, | |
1429 | ESF_DZ_TX_KER_BYTE_CNT, buffer->len, | |
1430 | ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); | |
1431 | } | |
1432 | } while (tx_queue->write_count != tx_queue->insert_count); | |
1433 | ||
1434 | wmb(); /* Ensure descriptors are written before they are fetched */ | |
1435 | ||
1436 | if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { | |
1437 | txd = efx_tx_desc(tx_queue, | |
1438 | old_write_count & tx_queue->ptr_mask); | |
1439 | efx_ef10_push_tx_desc(tx_queue, txd); | |
1440 | ++tx_queue->pushes; | |
1441 | } else { | |
1442 | efx_ef10_notify_tx_desc(tx_queue); | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context) | |
1447 | { | |
1448 | MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); | |
1449 | MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); | |
45b2449e | 1450 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
8127d661 BH |
1451 | size_t outlen; |
1452 | int rc; | |
1453 | ||
1454 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, | |
45b2449e | 1455 | nic_data->vport_id); |
8127d661 BH |
1456 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, |
1457 | MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE); | |
1458 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, | |
1459 | EFX_MAX_CHANNELS); | |
1460 | ||
1461 | rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), | |
1462 | outbuf, sizeof(outbuf), &outlen); | |
1463 | if (rc != 0) | |
1464 | return rc; | |
1465 | ||
1466 | if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) | |
1467 | return -EIO; | |
1468 | ||
1469 | *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) | |
1475 | { | |
1476 | MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); | |
1477 | int rc; | |
1478 | ||
1479 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, | |
1480 | context); | |
1481 | ||
1482 | rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), | |
1483 | NULL, 0, NULL); | |
1484 | WARN_ON(rc != 0); | |
1485 | } | |
1486 | ||
1487 | static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context) | |
1488 | { | |
1489 | MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); | |
1490 | MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); | |
1491 | int i, rc; | |
1492 | ||
1493 | MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, | |
1494 | context); | |
1495 | BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != | |
1496 | MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); | |
1497 | ||
1498 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) | |
1499 | MCDI_PTR(tablebuf, | |
1500 | RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = | |
1501 | (u8) efx->rx_indir_table[i]; | |
1502 | ||
1503 | rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, | |
1504 | sizeof(tablebuf), NULL, 0, NULL); | |
1505 | if (rc != 0) | |
1506 | return rc; | |
1507 | ||
1508 | MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, | |
1509 | context); | |
1510 | BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != | |
1511 | MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); | |
1512 | for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) | |
1513 | MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = | |
1514 | efx->rx_hash_key[i]; | |
1515 | ||
1516 | return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, | |
1517 | sizeof(keybuf), NULL, 0, NULL); | |
1518 | } | |
1519 | ||
1520 | static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) | |
1521 | { | |
1522 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1523 | ||
1524 | if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) | |
1525 | efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); | |
1526 | nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; | |
1527 | } | |
1528 | ||
d43050c0 | 1529 | static void efx_ef10_rx_push_rss_config(struct efx_nic *efx) |
8127d661 BH |
1530 | { |
1531 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1532 | int rc; | |
1533 | ||
d43050c0 | 1534 | netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n"); |
8127d661 BH |
1535 | |
1536 | if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) { | |
1537 | rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context); | |
1538 | if (rc != 0) | |
1539 | goto fail; | |
1540 | } | |
1541 | ||
1542 | rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context); | |
1543 | if (rc != 0) | |
1544 | goto fail; | |
1545 | ||
1546 | return; | |
1547 | ||
1548 | fail: | |
1549 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); | |
1550 | } | |
1551 | ||
1552 | static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) | |
1553 | { | |
1554 | return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, | |
1555 | (rx_queue->ptr_mask + 1) * | |
1556 | sizeof(efx_qword_t), | |
1557 | GFP_KERNEL); | |
1558 | } | |
1559 | ||
1560 | static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) | |
1561 | { | |
1562 | MCDI_DECLARE_BUF(inbuf, | |
1563 | MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / | |
1564 | EFX_BUF_SIZE)); | |
1565 | MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN); | |
1566 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); | |
1567 | size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; | |
1568 | struct efx_nic *efx = rx_queue->efx; | |
45b2449e | 1569 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
8127d661 BH |
1570 | size_t inlen, outlen; |
1571 | dma_addr_t dma_addr; | |
1572 | int rc; | |
1573 | int i; | |
1574 | ||
1575 | rx_queue->scatter_n = 0; | |
1576 | rx_queue->scatter_len = 0; | |
1577 | ||
1578 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); | |
1579 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); | |
1580 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); | |
1581 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, | |
1582 | efx_rx_queue_index(rx_queue)); | |
bd9a265d JC |
1583 | MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, |
1584 | INIT_RXQ_IN_FLAG_PREFIX, 1, | |
1585 | INIT_RXQ_IN_FLAG_TIMESTAMP, 1); | |
8127d661 | 1586 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); |
45b2449e | 1587 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id); |
8127d661 BH |
1588 | |
1589 | dma_addr = rx_queue->rxd.buf.dma_addr; | |
1590 | ||
1591 | netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", | |
1592 | efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); | |
1593 | ||
1594 | for (i = 0; i < entries; ++i) { | |
1595 | MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); | |
1596 | dma_addr += EFX_BUF_SIZE; | |
1597 | } | |
1598 | ||
1599 | inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); | |
1600 | ||
1601 | rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, | |
1602 | outbuf, sizeof(outbuf), &outlen); | |
48ce5634 BH |
1603 | if (rc) |
1604 | netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", | |
1605 | efx_rx_queue_index(rx_queue)); | |
8127d661 BH |
1606 | } |
1607 | ||
1608 | static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) | |
1609 | { | |
1610 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); | |
1611 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN); | |
1612 | struct efx_nic *efx = rx_queue->efx; | |
1613 | size_t outlen; | |
1614 | int rc; | |
1615 | ||
1616 | MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, | |
1617 | efx_rx_queue_index(rx_queue)); | |
1618 | ||
1e0b8120 | 1619 | rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), |
8127d661 BH |
1620 | outbuf, sizeof(outbuf), &outlen); |
1621 | ||
1622 | if (rc && rc != -EALREADY) | |
1623 | goto fail; | |
1624 | ||
1625 | return; | |
1626 | ||
1627 | fail: | |
1e0b8120 EC |
1628 | efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, |
1629 | outbuf, outlen, rc); | |
8127d661 BH |
1630 | } |
1631 | ||
1632 | static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) | |
1633 | { | |
1634 | efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); | |
1635 | } | |
1636 | ||
1637 | /* This creates an entry in the RX descriptor queue */ | |
1638 | static inline void | |
1639 | efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) | |
1640 | { | |
1641 | struct efx_rx_buffer *rx_buf; | |
1642 | efx_qword_t *rxd; | |
1643 | ||
1644 | rxd = efx_rx_desc(rx_queue, index); | |
1645 | rx_buf = efx_rx_buffer(rx_queue, index); | |
1646 | EFX_POPULATE_QWORD_2(*rxd, | |
1647 | ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, | |
1648 | ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); | |
1649 | } | |
1650 | ||
1651 | static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) | |
1652 | { | |
1653 | struct efx_nic *efx = rx_queue->efx; | |
1654 | unsigned int write_count; | |
1655 | efx_dword_t reg; | |
1656 | ||
1657 | /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ | |
1658 | write_count = rx_queue->added_count & ~7; | |
1659 | if (rx_queue->notified_count == write_count) | |
1660 | return; | |
1661 | ||
1662 | do | |
1663 | efx_ef10_build_rx_desc( | |
1664 | rx_queue, | |
1665 | rx_queue->notified_count & rx_queue->ptr_mask); | |
1666 | while (++rx_queue->notified_count != write_count); | |
1667 | ||
1668 | wmb(); | |
1669 | EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, | |
1670 | write_count & rx_queue->ptr_mask); | |
1671 | efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, | |
1672 | efx_rx_queue_index(rx_queue)); | |
1673 | } | |
1674 | ||
1675 | static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; | |
1676 | ||
1677 | static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) | |
1678 | { | |
1679 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); | |
1680 | MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); | |
1681 | efx_qword_t event; | |
1682 | ||
1683 | EFX_POPULATE_QWORD_2(event, | |
1684 | ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, | |
1685 | ESF_DZ_EV_DATA, EFX_EF10_REFILL); | |
1686 | ||
1687 | MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); | |
1688 | ||
1689 | /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has | |
1690 | * already swapped the data to little-endian order. | |
1691 | */ | |
1692 | memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], | |
1693 | sizeof(efx_qword_t)); | |
1694 | ||
1695 | efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, | |
1696 | inbuf, sizeof(inbuf), 0, | |
1697 | efx_ef10_rx_defer_refill_complete, 0); | |
1698 | } | |
1699 | ||
1700 | static void | |
1701 | efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, | |
1702 | int rc, efx_dword_t *outbuf, | |
1703 | size_t outlen_actual) | |
1704 | { | |
1705 | /* nothing to do */ | |
1706 | } | |
1707 | ||
1708 | static int efx_ef10_ev_probe(struct efx_channel *channel) | |
1709 | { | |
1710 | return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, | |
1711 | (channel->eventq_mask + 1) * | |
1712 | sizeof(efx_qword_t), | |
1713 | GFP_KERNEL); | |
1714 | } | |
1715 | ||
1716 | static int efx_ef10_ev_init(struct efx_channel *channel) | |
1717 | { | |
1718 | MCDI_DECLARE_BUF(inbuf, | |
1719 | MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / | |
1720 | EFX_BUF_SIZE)); | |
1721 | MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN); | |
1722 | size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; | |
1723 | struct efx_nic *efx = channel->efx; | |
1724 | struct efx_ef10_nic_data *nic_data; | |
1725 | bool supports_rx_merge; | |
1726 | size_t inlen, outlen; | |
1727 | dma_addr_t dma_addr; | |
1728 | int rc; | |
1729 | int i; | |
1730 | ||
1731 | nic_data = efx->nic_data; | |
1732 | supports_rx_merge = | |
1733 | !!(nic_data->datapath_caps & | |
1734 | 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); | |
1735 | ||
1736 | /* Fill event queue with all ones (i.e. empty events) */ | |
1737 | memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); | |
1738 | ||
1739 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); | |
1740 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); | |
1741 | /* INIT_EVQ expects index in vector table, not absolute */ | |
1742 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); | |
1743 | MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, | |
1744 | INIT_EVQ_IN_FLAG_INTERRUPTING, 1, | |
1745 | INIT_EVQ_IN_FLAG_RX_MERGE, 1, | |
1746 | INIT_EVQ_IN_FLAG_TX_MERGE, 1, | |
1747 | INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge); | |
1748 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, | |
1749 | MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); | |
1750 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); | |
1751 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); | |
1752 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, | |
1753 | MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); | |
1754 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); | |
1755 | ||
1756 | dma_addr = channel->eventq.buf.dma_addr; | |
1757 | for (i = 0; i < entries; ++i) { | |
1758 | MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); | |
1759 | dma_addr += EFX_BUF_SIZE; | |
1760 | } | |
1761 | ||
1762 | inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); | |
1763 | ||
1764 | rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, | |
1765 | outbuf, sizeof(outbuf), &outlen); | |
8127d661 | 1766 | /* IRQ return is ignored */ |
8127d661 BH |
1767 | return rc; |
1768 | } | |
1769 | ||
1770 | static void efx_ef10_ev_fini(struct efx_channel *channel) | |
1771 | { | |
1772 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); | |
1773 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN); | |
1774 | struct efx_nic *efx = channel->efx; | |
1775 | size_t outlen; | |
1776 | int rc; | |
1777 | ||
1778 | MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); | |
1779 | ||
1e0b8120 | 1780 | rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), |
8127d661 BH |
1781 | outbuf, sizeof(outbuf), &outlen); |
1782 | ||
1783 | if (rc && rc != -EALREADY) | |
1784 | goto fail; | |
1785 | ||
1786 | return; | |
1787 | ||
1788 | fail: | |
1e0b8120 EC |
1789 | efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, |
1790 | outbuf, outlen, rc); | |
8127d661 BH |
1791 | } |
1792 | ||
1793 | static void efx_ef10_ev_remove(struct efx_channel *channel) | |
1794 | { | |
1795 | efx_nic_free_buffer(channel->efx, &channel->eventq.buf); | |
1796 | } | |
1797 | ||
1798 | static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, | |
1799 | unsigned int rx_queue_label) | |
1800 | { | |
1801 | struct efx_nic *efx = rx_queue->efx; | |
1802 | ||
1803 | netif_info(efx, hw, efx->net_dev, | |
1804 | "rx event arrived on queue %d labeled as queue %u\n", | |
1805 | efx_rx_queue_index(rx_queue), rx_queue_label); | |
1806 | ||
1807 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1808 | } | |
1809 | ||
1810 | static void | |
1811 | efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, | |
1812 | unsigned int actual, unsigned int expected) | |
1813 | { | |
1814 | unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; | |
1815 | struct efx_nic *efx = rx_queue->efx; | |
1816 | ||
1817 | netif_info(efx, hw, efx->net_dev, | |
1818 | "dropped %d events (index=%d expected=%d)\n", | |
1819 | dropped, actual, expected); | |
1820 | ||
1821 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1822 | } | |
1823 | ||
1824 | /* partially received RX was aborted. clean up. */ | |
1825 | static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) | |
1826 | { | |
1827 | unsigned int rx_desc_ptr; | |
1828 | ||
8127d661 BH |
1829 | netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, |
1830 | "scattered RX aborted (dropping %u buffers)\n", | |
1831 | rx_queue->scatter_n); | |
1832 | ||
1833 | rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; | |
1834 | ||
1835 | efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, | |
1836 | 0, EFX_RX_PKT_DISCARD); | |
1837 | ||
1838 | rx_queue->removed_count += rx_queue->scatter_n; | |
1839 | rx_queue->scatter_n = 0; | |
1840 | rx_queue->scatter_len = 0; | |
1841 | ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; | |
1842 | } | |
1843 | ||
1844 | static int efx_ef10_handle_rx_event(struct efx_channel *channel, | |
1845 | const efx_qword_t *event) | |
1846 | { | |
1847 | unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; | |
1848 | unsigned int n_descs, n_packets, i; | |
1849 | struct efx_nic *efx = channel->efx; | |
1850 | struct efx_rx_queue *rx_queue; | |
1851 | bool rx_cont; | |
1852 | u16 flags = 0; | |
1853 | ||
1854 | if (unlikely(ACCESS_ONCE(efx->reset_pending))) | |
1855 | return 0; | |
1856 | ||
1857 | /* Basic packet information */ | |
1858 | rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); | |
1859 | next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); | |
1860 | rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); | |
1861 | rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); | |
1862 | rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); | |
1863 | ||
48ce5634 BH |
1864 | if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) |
1865 | netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" | |
1866 | EFX_QWORD_FMT "\n", | |
1867 | EFX_QWORD_VAL(*event)); | |
8127d661 BH |
1868 | |
1869 | rx_queue = efx_channel_get_rx_queue(channel); | |
1870 | ||
1871 | if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) | |
1872 | efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); | |
1873 | ||
1874 | n_descs = ((next_ptr_lbits - rx_queue->removed_count) & | |
1875 | ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); | |
1876 | ||
1877 | if (n_descs != rx_queue->scatter_n + 1) { | |
92a04168 BH |
1878 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
1879 | ||
8127d661 BH |
1880 | /* detect rx abort */ |
1881 | if (unlikely(n_descs == rx_queue->scatter_n)) { | |
48ce5634 BH |
1882 | if (rx_queue->scatter_n == 0 || rx_bytes != 0) |
1883 | netdev_WARN(efx->net_dev, | |
1884 | "invalid RX abort: scatter_n=%u event=" | |
1885 | EFX_QWORD_FMT "\n", | |
1886 | rx_queue->scatter_n, | |
1887 | EFX_QWORD_VAL(*event)); | |
8127d661 BH |
1888 | efx_ef10_handle_rx_abort(rx_queue); |
1889 | return 0; | |
1890 | } | |
1891 | ||
92a04168 BH |
1892 | /* Check that RX completion merging is valid, i.e. |
1893 | * the current firmware supports it and this is a | |
1894 | * non-scattered packet. | |
1895 | */ | |
1896 | if (!(nic_data->datapath_caps & | |
1897 | (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || | |
1898 | rx_queue->scatter_n != 0 || rx_cont) { | |
8127d661 BH |
1899 | efx_ef10_handle_rx_bad_lbits( |
1900 | rx_queue, next_ptr_lbits, | |
1901 | (rx_queue->removed_count + | |
1902 | rx_queue->scatter_n + 1) & | |
1903 | ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); | |
1904 | return 0; | |
1905 | } | |
1906 | ||
1907 | /* Merged completion for multiple non-scattered packets */ | |
1908 | rx_queue->scatter_n = 1; | |
1909 | rx_queue->scatter_len = 0; | |
1910 | n_packets = n_descs; | |
1911 | ++channel->n_rx_merge_events; | |
1912 | channel->n_rx_merge_packets += n_packets; | |
1913 | flags |= EFX_RX_PKT_PREFIX_LEN; | |
1914 | } else { | |
1915 | ++rx_queue->scatter_n; | |
1916 | rx_queue->scatter_len += rx_bytes; | |
1917 | if (rx_cont) | |
1918 | return 0; | |
1919 | n_packets = 1; | |
1920 | } | |
1921 | ||
1922 | if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) | |
1923 | flags |= EFX_RX_PKT_DISCARD; | |
1924 | ||
1925 | if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { | |
1926 | channel->n_rx_ip_hdr_chksum_err += n_packets; | |
1927 | } else if (unlikely(EFX_QWORD_FIELD(*event, | |
1928 | ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { | |
1929 | channel->n_rx_tcp_udp_chksum_err += n_packets; | |
1930 | } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || | |
1931 | rx_l4_class == ESE_DZ_L4_CLASS_UDP) { | |
1932 | flags |= EFX_RX_PKT_CSUMMED; | |
1933 | } | |
1934 | ||
1935 | if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) | |
1936 | flags |= EFX_RX_PKT_TCP; | |
1937 | ||
1938 | channel->irq_mod_score += 2 * n_packets; | |
1939 | ||
1940 | /* Handle received packet(s) */ | |
1941 | for (i = 0; i < n_packets; i++) { | |
1942 | efx_rx_packet(rx_queue, | |
1943 | rx_queue->removed_count & rx_queue->ptr_mask, | |
1944 | rx_queue->scatter_n, rx_queue->scatter_len, | |
1945 | flags); | |
1946 | rx_queue->removed_count += rx_queue->scatter_n; | |
1947 | } | |
1948 | ||
1949 | rx_queue->scatter_n = 0; | |
1950 | rx_queue->scatter_len = 0; | |
1951 | ||
1952 | return n_packets; | |
1953 | } | |
1954 | ||
1955 | static int | |
1956 | efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) | |
1957 | { | |
1958 | struct efx_nic *efx = channel->efx; | |
1959 | struct efx_tx_queue *tx_queue; | |
1960 | unsigned int tx_ev_desc_ptr; | |
1961 | unsigned int tx_ev_q_label; | |
1962 | int tx_descs = 0; | |
1963 | ||
1964 | if (unlikely(ACCESS_ONCE(efx->reset_pending))) | |
1965 | return 0; | |
1966 | ||
1967 | if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) | |
1968 | return 0; | |
1969 | ||
1970 | /* Transmit completion */ | |
1971 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); | |
1972 | tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); | |
1973 | tx_queue = efx_channel_get_tx_queue(channel, | |
1974 | tx_ev_q_label % EFX_TXQ_TYPES); | |
1975 | tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & | |
1976 | tx_queue->ptr_mask); | |
1977 | efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); | |
1978 | ||
1979 | return tx_descs; | |
1980 | } | |
1981 | ||
1982 | static void | |
1983 | efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) | |
1984 | { | |
1985 | struct efx_nic *efx = channel->efx; | |
1986 | int subcode; | |
1987 | ||
1988 | subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); | |
1989 | ||
1990 | switch (subcode) { | |
1991 | case ESE_DZ_DRV_TIMER_EV: | |
1992 | case ESE_DZ_DRV_WAKE_UP_EV: | |
1993 | break; | |
1994 | case ESE_DZ_DRV_START_UP_EV: | |
1995 | /* event queue init complete. ok. */ | |
1996 | break; | |
1997 | default: | |
1998 | netif_err(efx, hw, efx->net_dev, | |
1999 | "channel %d unknown driver event type %d" | |
2000 | " (data " EFX_QWORD_FMT ")\n", | |
2001 | channel->channel, subcode, | |
2002 | EFX_QWORD_VAL(*event)); | |
2003 | ||
2004 | } | |
2005 | } | |
2006 | ||
2007 | static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, | |
2008 | efx_qword_t *event) | |
2009 | { | |
2010 | struct efx_nic *efx = channel->efx; | |
2011 | u32 subcode; | |
2012 | ||
2013 | subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); | |
2014 | ||
2015 | switch (subcode) { | |
2016 | case EFX_EF10_TEST: | |
2017 | channel->event_test_cpu = raw_smp_processor_id(); | |
2018 | break; | |
2019 | case EFX_EF10_REFILL: | |
2020 | /* The queue must be empty, so we won't receive any rx | |
2021 | * events, so efx_process_channel() won't refill the | |
2022 | * queue. Refill it here | |
2023 | */ | |
cce28794 | 2024 | efx_fast_push_rx_descriptors(&channel->rx_queue, true); |
8127d661 BH |
2025 | break; |
2026 | default: | |
2027 | netif_err(efx, hw, efx->net_dev, | |
2028 | "channel %d unknown driver event type %u" | |
2029 | " (data " EFX_QWORD_FMT ")\n", | |
2030 | channel->channel, (unsigned) subcode, | |
2031 | EFX_QWORD_VAL(*event)); | |
2032 | } | |
2033 | } | |
2034 | ||
2035 | static int efx_ef10_ev_process(struct efx_channel *channel, int quota) | |
2036 | { | |
2037 | struct efx_nic *efx = channel->efx; | |
2038 | efx_qword_t event, *p_event; | |
2039 | unsigned int read_ptr; | |
2040 | int ev_code; | |
2041 | int tx_descs = 0; | |
2042 | int spent = 0; | |
2043 | ||
75363a46 EB |
2044 | if (quota <= 0) |
2045 | return spent; | |
2046 | ||
8127d661 BH |
2047 | read_ptr = channel->eventq_read_ptr; |
2048 | ||
2049 | for (;;) { | |
2050 | p_event = efx_event(channel, read_ptr); | |
2051 | event = *p_event; | |
2052 | ||
2053 | if (!efx_event_present(&event)) | |
2054 | break; | |
2055 | ||
2056 | EFX_SET_QWORD(*p_event); | |
2057 | ||
2058 | ++read_ptr; | |
2059 | ||
2060 | ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); | |
2061 | ||
2062 | netif_vdbg(efx, drv, efx->net_dev, | |
2063 | "processing event on %d " EFX_QWORD_FMT "\n", | |
2064 | channel->channel, EFX_QWORD_VAL(event)); | |
2065 | ||
2066 | switch (ev_code) { | |
2067 | case ESE_DZ_EV_CODE_MCDI_EV: | |
2068 | efx_mcdi_process_event(channel, &event); | |
2069 | break; | |
2070 | case ESE_DZ_EV_CODE_RX_EV: | |
2071 | spent += efx_ef10_handle_rx_event(channel, &event); | |
2072 | if (spent >= quota) { | |
2073 | /* XXX can we split a merged event to | |
2074 | * avoid going over-quota? | |
2075 | */ | |
2076 | spent = quota; | |
2077 | goto out; | |
2078 | } | |
2079 | break; | |
2080 | case ESE_DZ_EV_CODE_TX_EV: | |
2081 | tx_descs += efx_ef10_handle_tx_event(channel, &event); | |
2082 | if (tx_descs > efx->txq_entries) { | |
2083 | spent = quota; | |
2084 | goto out; | |
2085 | } else if (++spent == quota) { | |
2086 | goto out; | |
2087 | } | |
2088 | break; | |
2089 | case ESE_DZ_EV_CODE_DRIVER_EV: | |
2090 | efx_ef10_handle_driver_event(channel, &event); | |
2091 | if (++spent == quota) | |
2092 | goto out; | |
2093 | break; | |
2094 | case EFX_EF10_DRVGEN_EV: | |
2095 | efx_ef10_handle_driver_generated_event(channel, &event); | |
2096 | break; | |
2097 | default: | |
2098 | netif_err(efx, hw, efx->net_dev, | |
2099 | "channel %d unknown event type %d" | |
2100 | " (data " EFX_QWORD_FMT ")\n", | |
2101 | channel->channel, ev_code, | |
2102 | EFX_QWORD_VAL(event)); | |
2103 | } | |
2104 | } | |
2105 | ||
2106 | out: | |
2107 | channel->eventq_read_ptr = read_ptr; | |
2108 | return spent; | |
2109 | } | |
2110 | ||
2111 | static void efx_ef10_ev_read_ack(struct efx_channel *channel) | |
2112 | { | |
2113 | struct efx_nic *efx = channel->efx; | |
2114 | efx_dword_t rptr; | |
2115 | ||
2116 | if (EFX_EF10_WORKAROUND_35388(efx)) { | |
2117 | BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < | |
2118 | (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); | |
2119 | BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > | |
2120 | (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); | |
2121 | ||
2122 | EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, | |
2123 | EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, | |
2124 | ERF_DD_EVQ_IND_RPTR, | |
2125 | (channel->eventq_read_ptr & | |
2126 | channel->eventq_mask) >> | |
2127 | ERF_DD_EVQ_IND_RPTR_WIDTH); | |
2128 | efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, | |
2129 | channel->channel); | |
2130 | EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, | |
2131 | EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, | |
2132 | ERF_DD_EVQ_IND_RPTR, | |
2133 | channel->eventq_read_ptr & | |
2134 | ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); | |
2135 | efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, | |
2136 | channel->channel); | |
2137 | } else { | |
2138 | EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, | |
2139 | channel->eventq_read_ptr & | |
2140 | channel->eventq_mask); | |
2141 | efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); | |
2142 | } | |
2143 | } | |
2144 | ||
2145 | static void efx_ef10_ev_test_generate(struct efx_channel *channel) | |
2146 | { | |
2147 | MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); | |
2148 | struct efx_nic *efx = channel->efx; | |
2149 | efx_qword_t event; | |
2150 | int rc; | |
2151 | ||
2152 | EFX_POPULATE_QWORD_2(event, | |
2153 | ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, | |
2154 | ESF_DZ_EV_DATA, EFX_EF10_TEST); | |
2155 | ||
2156 | MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); | |
2157 | ||
2158 | /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has | |
2159 | * already swapped the data to little-endian order. | |
2160 | */ | |
2161 | memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], | |
2162 | sizeof(efx_qword_t)); | |
2163 | ||
2164 | rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), | |
2165 | NULL, 0, NULL); | |
2166 | if (rc != 0) | |
2167 | goto fail; | |
2168 | ||
2169 | return; | |
2170 | ||
2171 | fail: | |
2172 | WARN_ON(true); | |
2173 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); | |
2174 | } | |
2175 | ||
2176 | void efx_ef10_handle_drain_event(struct efx_nic *efx) | |
2177 | { | |
2178 | if (atomic_dec_and_test(&efx->active_queues)) | |
2179 | wake_up(&efx->flush_wq); | |
2180 | ||
2181 | WARN_ON(atomic_read(&efx->active_queues) < 0); | |
2182 | } | |
2183 | ||
2184 | static int efx_ef10_fini_dmaq(struct efx_nic *efx) | |
2185 | { | |
2186 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
2187 | struct efx_channel *channel; | |
2188 | struct efx_tx_queue *tx_queue; | |
2189 | struct efx_rx_queue *rx_queue; | |
2190 | int pending; | |
2191 | ||
2192 | /* If the MC has just rebooted, the TX/RX queues will have already been | |
2193 | * torn down, but efx->active_queues needs to be set to zero. | |
2194 | */ | |
2195 | if (nic_data->must_realloc_vis) { | |
2196 | atomic_set(&efx->active_queues, 0); | |
2197 | return 0; | |
2198 | } | |
2199 | ||
2200 | /* Do not attempt to write to the NIC during EEH recovery */ | |
2201 | if (efx->state != STATE_RECOVERY) { | |
2202 | efx_for_each_channel(channel, efx) { | |
2203 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
2204 | efx_ef10_rx_fini(rx_queue); | |
2205 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
2206 | efx_ef10_tx_fini(tx_queue); | |
2207 | } | |
2208 | ||
2209 | wait_event_timeout(efx->flush_wq, | |
2210 | atomic_read(&efx->active_queues) == 0, | |
2211 | msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); | |
2212 | pending = atomic_read(&efx->active_queues); | |
2213 | if (pending) { | |
2214 | netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", | |
2215 | pending); | |
2216 | return -ETIMEDOUT; | |
2217 | } | |
2218 | } | |
2219 | ||
2220 | return 0; | |
2221 | } | |
2222 | ||
e283546c EC |
2223 | static void efx_ef10_prepare_flr(struct efx_nic *efx) |
2224 | { | |
2225 | atomic_set(&efx->active_queues, 0); | |
2226 | } | |
2227 | ||
8127d661 BH |
2228 | static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, |
2229 | const struct efx_filter_spec *right) | |
2230 | { | |
2231 | if ((left->match_flags ^ right->match_flags) | | |
2232 | ((left->flags ^ right->flags) & | |
2233 | (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) | |
2234 | return false; | |
2235 | ||
2236 | return memcmp(&left->outer_vid, &right->outer_vid, | |
2237 | sizeof(struct efx_filter_spec) - | |
2238 | offsetof(struct efx_filter_spec, outer_vid)) == 0; | |
2239 | } | |
2240 | ||
2241 | static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) | |
2242 | { | |
2243 | BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); | |
2244 | return jhash2((const u32 *)&spec->outer_vid, | |
2245 | (sizeof(struct efx_filter_spec) - | |
2246 | offsetof(struct efx_filter_spec, outer_vid)) / 4, | |
2247 | 0); | |
2248 | /* XXX should we randomise the initval? */ | |
2249 | } | |
2250 | ||
2251 | /* Decide whether a filter should be exclusive or else should allow | |
2252 | * delivery to additional recipients. Currently we decide that | |
2253 | * filters for specific local unicast MAC and IP addresses are | |
2254 | * exclusive. | |
2255 | */ | |
2256 | static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) | |
2257 | { | |
2258 | if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && | |
2259 | !is_multicast_ether_addr(spec->loc_mac)) | |
2260 | return true; | |
2261 | ||
2262 | if ((spec->match_flags & | |
2263 | (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == | |
2264 | (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { | |
2265 | if (spec->ether_type == htons(ETH_P_IP) && | |
2266 | !ipv4_is_multicast(spec->loc_host[0])) | |
2267 | return true; | |
2268 | if (spec->ether_type == htons(ETH_P_IPV6) && | |
2269 | ((const u8 *)spec->loc_host)[0] != 0xff) | |
2270 | return true; | |
2271 | } | |
2272 | ||
2273 | return false; | |
2274 | } | |
2275 | ||
2276 | static struct efx_filter_spec * | |
2277 | efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, | |
2278 | unsigned int filter_idx) | |
2279 | { | |
2280 | return (struct efx_filter_spec *)(table->entry[filter_idx].spec & | |
2281 | ~EFX_EF10_FILTER_FLAGS); | |
2282 | } | |
2283 | ||
2284 | static unsigned int | |
2285 | efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, | |
2286 | unsigned int filter_idx) | |
2287 | { | |
2288 | return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; | |
2289 | } | |
2290 | ||
2291 | static void | |
2292 | efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, | |
2293 | unsigned int filter_idx, | |
2294 | const struct efx_filter_spec *spec, | |
2295 | unsigned int flags) | |
2296 | { | |
2297 | table->entry[filter_idx].spec = (unsigned long)spec | flags; | |
2298 | } | |
2299 | ||
2300 | static void efx_ef10_filter_push_prep(struct efx_nic *efx, | |
2301 | const struct efx_filter_spec *spec, | |
2302 | efx_dword_t *inbuf, u64 handle, | |
2303 | bool replacing) | |
2304 | { | |
2305 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
2306 | ||
2307 | memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); | |
2308 | ||
2309 | if (replacing) { | |
2310 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
2311 | MC_CMD_FILTER_OP_IN_OP_REPLACE); | |
2312 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); | |
2313 | } else { | |
2314 | u32 match_fields = 0; | |
2315 | ||
2316 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
2317 | efx_ef10_filter_is_exclusive(spec) ? | |
2318 | MC_CMD_FILTER_OP_IN_OP_INSERT : | |
2319 | MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); | |
2320 | ||
2321 | /* Convert match flags and values. Unlike almost | |
2322 | * everything else in MCDI, these fields are in | |
2323 | * network byte order. | |
2324 | */ | |
2325 | if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) | |
2326 | match_fields |= | |
2327 | is_multicast_ether_addr(spec->loc_mac) ? | |
2328 | 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : | |
2329 | 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; | |
2330 | #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ | |
2331 | if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ | |
2332 | match_fields |= \ | |
2333 | 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ | |
2334 | mcdi_field ## _LBN; \ | |
2335 | BUILD_BUG_ON( \ | |
2336 | MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ | |
2337 | sizeof(spec->gen_field)); \ | |
2338 | memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ | |
2339 | &spec->gen_field, sizeof(spec->gen_field)); \ | |
2340 | } | |
2341 | COPY_FIELD(REM_HOST, rem_host, SRC_IP); | |
2342 | COPY_FIELD(LOC_HOST, loc_host, DST_IP); | |
2343 | COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); | |
2344 | COPY_FIELD(REM_PORT, rem_port, SRC_PORT); | |
2345 | COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); | |
2346 | COPY_FIELD(LOC_PORT, loc_port, DST_PORT); | |
2347 | COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); | |
2348 | COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); | |
2349 | COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); | |
2350 | COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); | |
2351 | #undef COPY_FIELD | |
2352 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, | |
2353 | match_fields); | |
2354 | } | |
2355 | ||
45b2449e | 2356 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id); |
8127d661 BH |
2357 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, |
2358 | spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? | |
2359 | MC_CMD_FILTER_OP_IN_RX_DEST_DROP : | |
2360 | MC_CMD_FILTER_OP_IN_RX_DEST_HOST); | |
e3d36293 | 2361 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0); |
8127d661 BH |
2362 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, |
2363 | MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); | |
a0bc3487 BH |
2364 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, |
2365 | spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? | |
2366 | 0 : spec->dmaq_id); | |
8127d661 BH |
2367 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, |
2368 | (spec->flags & EFX_FILTER_FLAG_RX_RSS) ? | |
2369 | MC_CMD_FILTER_OP_IN_RX_MODE_RSS : | |
2370 | MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); | |
2371 | if (spec->flags & EFX_FILTER_FLAG_RX_RSS) | |
2372 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, | |
2373 | spec->rss_context != | |
2374 | EFX_FILTER_RSS_CONTEXT_DEFAULT ? | |
2375 | spec->rss_context : nic_data->rx_rss_context); | |
2376 | } | |
2377 | ||
2378 | static int efx_ef10_filter_push(struct efx_nic *efx, | |
2379 | const struct efx_filter_spec *spec, | |
2380 | u64 *handle, bool replacing) | |
2381 | { | |
2382 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); | |
2383 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); | |
2384 | int rc; | |
2385 | ||
2386 | efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); | |
2387 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), | |
2388 | outbuf, sizeof(outbuf), NULL); | |
2389 | if (rc == 0) | |
2390 | *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); | |
065e64c4 BH |
2391 | if (rc == -ENOSPC) |
2392 | rc = -EBUSY; /* to match efx_farch_filter_insert() */ | |
8127d661 BH |
2393 | return rc; |
2394 | } | |
2395 | ||
2396 | static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table, | |
2397 | enum efx_filter_match_flags match_flags) | |
2398 | { | |
2399 | unsigned int match_pri; | |
2400 | ||
2401 | for (match_pri = 0; | |
2402 | match_pri < table->rx_match_count; | |
2403 | match_pri++) | |
2404 | if (table->rx_match_flags[match_pri] == match_flags) | |
2405 | return match_pri; | |
2406 | ||
2407 | return -EPROTONOSUPPORT; | |
2408 | } | |
2409 | ||
2410 | static s32 efx_ef10_filter_insert(struct efx_nic *efx, | |
2411 | struct efx_filter_spec *spec, | |
2412 | bool replace_equal) | |
2413 | { | |
2414 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2415 | DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); | |
2416 | struct efx_filter_spec *saved_spec; | |
2417 | unsigned int match_pri, hash; | |
2418 | unsigned int priv_flags; | |
2419 | bool replacing = false; | |
2420 | int ins_index = -1; | |
2421 | DEFINE_WAIT(wait); | |
2422 | bool is_mc_recip; | |
2423 | s32 rc; | |
2424 | ||
2425 | /* For now, only support RX filters */ | |
2426 | if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != | |
2427 | EFX_FILTER_FLAG_RX) | |
2428 | return -EINVAL; | |
2429 | ||
2430 | rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags); | |
2431 | if (rc < 0) | |
2432 | return rc; | |
2433 | match_pri = rc; | |
2434 | ||
2435 | hash = efx_ef10_filter_hash(spec); | |
2436 | is_mc_recip = efx_filter_is_mc_recipient(spec); | |
2437 | if (is_mc_recip) | |
2438 | bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); | |
2439 | ||
2440 | /* Find any existing filters with the same match tuple or | |
2441 | * else a free slot to insert at. If any of them are busy, | |
2442 | * we have to wait and retry. | |
2443 | */ | |
2444 | for (;;) { | |
2445 | unsigned int depth = 1; | |
2446 | unsigned int i; | |
2447 | ||
2448 | spin_lock_bh(&efx->filter_lock); | |
2449 | ||
2450 | for (;;) { | |
2451 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); | |
2452 | saved_spec = efx_ef10_filter_entry_spec(table, i); | |
2453 | ||
2454 | if (!saved_spec) { | |
2455 | if (ins_index < 0) | |
2456 | ins_index = i; | |
2457 | } else if (efx_ef10_filter_equal(spec, saved_spec)) { | |
2458 | if (table->entry[i].spec & | |
2459 | EFX_EF10_FILTER_FLAG_BUSY) | |
2460 | break; | |
2461 | if (spec->priority < saved_spec->priority && | |
7665d1ab | 2462 | spec->priority != EFX_FILTER_PRI_AUTO) { |
8127d661 BH |
2463 | rc = -EPERM; |
2464 | goto out_unlock; | |
2465 | } | |
2466 | if (!is_mc_recip) { | |
2467 | /* This is the only one */ | |
2468 | if (spec->priority == | |
2469 | saved_spec->priority && | |
2470 | !replace_equal) { | |
2471 | rc = -EEXIST; | |
2472 | goto out_unlock; | |
2473 | } | |
2474 | ins_index = i; | |
2475 | goto found; | |
2476 | } else if (spec->priority > | |
2477 | saved_spec->priority || | |
2478 | (spec->priority == | |
2479 | saved_spec->priority && | |
2480 | replace_equal)) { | |
2481 | if (ins_index < 0) | |
2482 | ins_index = i; | |
2483 | else | |
2484 | __set_bit(depth, mc_rem_map); | |
2485 | } | |
2486 | } | |
2487 | ||
2488 | /* Once we reach the maximum search depth, use | |
2489 | * the first suitable slot or return -EBUSY if | |
2490 | * there was none | |
2491 | */ | |
2492 | if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { | |
2493 | if (ins_index < 0) { | |
2494 | rc = -EBUSY; | |
2495 | goto out_unlock; | |
2496 | } | |
2497 | goto found; | |
2498 | } | |
2499 | ||
2500 | ++depth; | |
2501 | } | |
2502 | ||
2503 | prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); | |
2504 | spin_unlock_bh(&efx->filter_lock); | |
2505 | schedule(); | |
2506 | } | |
2507 | ||
2508 | found: | |
2509 | /* Create a software table entry if necessary, and mark it | |
2510 | * busy. We might yet fail to insert, but any attempt to | |
2511 | * insert a conflicting filter while we're waiting for the | |
2512 | * firmware must find the busy entry. | |
2513 | */ | |
2514 | saved_spec = efx_ef10_filter_entry_spec(table, ins_index); | |
2515 | if (saved_spec) { | |
7665d1ab BH |
2516 | if (spec->priority == EFX_FILTER_PRI_AUTO && |
2517 | saved_spec->priority >= EFX_FILTER_PRI_AUTO) { | |
8127d661 | 2518 | /* Just make sure it won't be removed */ |
7665d1ab BH |
2519 | if (saved_spec->priority > EFX_FILTER_PRI_AUTO) |
2520 | saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; | |
8127d661 | 2521 | table->entry[ins_index].spec &= |
b59e6ef8 | 2522 | ~EFX_EF10_FILTER_FLAG_AUTO_OLD; |
8127d661 BH |
2523 | rc = ins_index; |
2524 | goto out_unlock; | |
2525 | } | |
2526 | replacing = true; | |
2527 | priv_flags = efx_ef10_filter_entry_flags(table, ins_index); | |
2528 | } else { | |
2529 | saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); | |
2530 | if (!saved_spec) { | |
2531 | rc = -ENOMEM; | |
2532 | goto out_unlock; | |
2533 | } | |
2534 | *saved_spec = *spec; | |
2535 | priv_flags = 0; | |
2536 | } | |
2537 | efx_ef10_filter_set_entry(table, ins_index, saved_spec, | |
2538 | priv_flags | EFX_EF10_FILTER_FLAG_BUSY); | |
2539 | ||
2540 | /* Mark lower-priority multicast recipients busy prior to removal */ | |
2541 | if (is_mc_recip) { | |
2542 | unsigned int depth, i; | |
2543 | ||
2544 | for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { | |
2545 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); | |
2546 | if (test_bit(depth, mc_rem_map)) | |
2547 | table->entry[i].spec |= | |
2548 | EFX_EF10_FILTER_FLAG_BUSY; | |
2549 | } | |
2550 | } | |
2551 | ||
2552 | spin_unlock_bh(&efx->filter_lock); | |
2553 | ||
2554 | rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, | |
2555 | replacing); | |
2556 | ||
2557 | /* Finalise the software table entry */ | |
2558 | spin_lock_bh(&efx->filter_lock); | |
2559 | if (rc == 0) { | |
2560 | if (replacing) { | |
2561 | /* Update the fields that may differ */ | |
7665d1ab BH |
2562 | if (saved_spec->priority == EFX_FILTER_PRI_AUTO) |
2563 | saved_spec->flags |= | |
2564 | EFX_FILTER_FLAG_RX_OVER_AUTO; | |
8127d661 | 2565 | saved_spec->priority = spec->priority; |
7665d1ab | 2566 | saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; |
8127d661 BH |
2567 | saved_spec->flags |= spec->flags; |
2568 | saved_spec->rss_context = spec->rss_context; | |
2569 | saved_spec->dmaq_id = spec->dmaq_id; | |
2570 | } | |
2571 | } else if (!replacing) { | |
2572 | kfree(saved_spec); | |
2573 | saved_spec = NULL; | |
2574 | } | |
2575 | efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); | |
2576 | ||
2577 | /* Remove and finalise entries for lower-priority multicast | |
2578 | * recipients | |
2579 | */ | |
2580 | if (is_mc_recip) { | |
2581 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); | |
2582 | unsigned int depth, i; | |
2583 | ||
2584 | memset(inbuf, 0, sizeof(inbuf)); | |
2585 | ||
2586 | for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { | |
2587 | if (!test_bit(depth, mc_rem_map)) | |
2588 | continue; | |
2589 | ||
2590 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); | |
2591 | saved_spec = efx_ef10_filter_entry_spec(table, i); | |
2592 | priv_flags = efx_ef10_filter_entry_flags(table, i); | |
2593 | ||
2594 | if (rc == 0) { | |
2595 | spin_unlock_bh(&efx->filter_lock); | |
2596 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
2597 | MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); | |
2598 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, | |
2599 | table->entry[i].handle); | |
2600 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, | |
2601 | inbuf, sizeof(inbuf), | |
2602 | NULL, 0, NULL); | |
2603 | spin_lock_bh(&efx->filter_lock); | |
2604 | } | |
2605 | ||
2606 | if (rc == 0) { | |
2607 | kfree(saved_spec); | |
2608 | saved_spec = NULL; | |
2609 | priv_flags = 0; | |
2610 | } else { | |
2611 | priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; | |
2612 | } | |
2613 | efx_ef10_filter_set_entry(table, i, saved_spec, | |
2614 | priv_flags); | |
2615 | } | |
2616 | } | |
2617 | ||
2618 | /* If successful, return the inserted filter ID */ | |
2619 | if (rc == 0) | |
2620 | rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; | |
2621 | ||
2622 | wake_up_all(&table->waitq); | |
2623 | out_unlock: | |
2624 | spin_unlock_bh(&efx->filter_lock); | |
2625 | finish_wait(&table->waitq, &wait); | |
2626 | return rc; | |
2627 | } | |
2628 | ||
9fd8095d | 2629 | static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) |
8127d661 BH |
2630 | { |
2631 | /* no need to do anything here on EF10 */ | |
2632 | } | |
2633 | ||
2634 | /* Remove a filter. | |
b59e6ef8 BH |
2635 | * If !by_index, remove by ID |
2636 | * If by_index, remove by index | |
8127d661 BH |
2637 | * Filter ID may come from userland and must be range-checked. |
2638 | */ | |
2639 | static int efx_ef10_filter_remove_internal(struct efx_nic *efx, | |
fbd79120 | 2640 | unsigned int priority_mask, |
b59e6ef8 | 2641 | u32 filter_id, bool by_index) |
8127d661 BH |
2642 | { |
2643 | unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; | |
2644 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2645 | MCDI_DECLARE_BUF(inbuf, | |
2646 | MC_CMD_FILTER_OP_IN_HANDLE_OFST + | |
2647 | MC_CMD_FILTER_OP_IN_HANDLE_LEN); | |
2648 | struct efx_filter_spec *spec; | |
2649 | DEFINE_WAIT(wait); | |
2650 | int rc; | |
2651 | ||
2652 | /* Find the software table entry and mark it busy. Don't | |
2653 | * remove it yet; any attempt to update while we're waiting | |
2654 | * for the firmware must find the busy entry. | |
2655 | */ | |
2656 | for (;;) { | |
2657 | spin_lock_bh(&efx->filter_lock); | |
2658 | if (!(table->entry[filter_idx].spec & | |
2659 | EFX_EF10_FILTER_FLAG_BUSY)) | |
2660 | break; | |
2661 | prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); | |
2662 | spin_unlock_bh(&efx->filter_lock); | |
2663 | schedule(); | |
2664 | } | |
7665d1ab | 2665 | |
8127d661 | 2666 | spec = efx_ef10_filter_entry_spec(table, filter_idx); |
7665d1ab | 2667 | if (!spec || |
b59e6ef8 | 2668 | (!by_index && |
8127d661 BH |
2669 | efx_ef10_filter_rx_match_pri(table, spec->match_flags) != |
2670 | filter_id / HUNT_FILTER_TBL_ROWS)) { | |
2671 | rc = -ENOENT; | |
2672 | goto out_unlock; | |
2673 | } | |
7665d1ab BH |
2674 | |
2675 | if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && | |
fbd79120 | 2676 | priority_mask == (1U << EFX_FILTER_PRI_AUTO)) { |
7665d1ab BH |
2677 | /* Just remove flags */ |
2678 | spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; | |
b59e6ef8 | 2679 | table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; |
7665d1ab BH |
2680 | rc = 0; |
2681 | goto out_unlock; | |
2682 | } | |
2683 | ||
fbd79120 | 2684 | if (!(priority_mask & (1U << spec->priority))) { |
7665d1ab BH |
2685 | rc = -ENOENT; |
2686 | goto out_unlock; | |
2687 | } | |
2688 | ||
8127d661 BH |
2689 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; |
2690 | spin_unlock_bh(&efx->filter_lock); | |
2691 | ||
7665d1ab | 2692 | if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { |
b59e6ef8 | 2693 | /* Reset to an automatic filter */ |
8127d661 BH |
2694 | |
2695 | struct efx_filter_spec new_spec = *spec; | |
2696 | ||
7665d1ab | 2697 | new_spec.priority = EFX_FILTER_PRI_AUTO; |
8127d661 | 2698 | new_spec.flags = (EFX_FILTER_FLAG_RX | |
7665d1ab | 2699 | EFX_FILTER_FLAG_RX_RSS); |
8127d661 BH |
2700 | new_spec.dmaq_id = 0; |
2701 | new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; | |
2702 | rc = efx_ef10_filter_push(efx, &new_spec, | |
2703 | &table->entry[filter_idx].handle, | |
2704 | true); | |
2705 | ||
2706 | spin_lock_bh(&efx->filter_lock); | |
2707 | if (rc == 0) | |
2708 | *spec = new_spec; | |
2709 | } else { | |
2710 | /* Really remove the filter */ | |
2711 | ||
2712 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
2713 | efx_ef10_filter_is_exclusive(spec) ? | |
2714 | MC_CMD_FILTER_OP_IN_OP_REMOVE : | |
2715 | MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); | |
2716 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, | |
2717 | table->entry[filter_idx].handle); | |
2718 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, | |
2719 | inbuf, sizeof(inbuf), NULL, 0, NULL); | |
2720 | ||
2721 | spin_lock_bh(&efx->filter_lock); | |
2722 | if (rc == 0) { | |
2723 | kfree(spec); | |
2724 | efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); | |
2725 | } | |
2726 | } | |
7665d1ab | 2727 | |
8127d661 BH |
2728 | table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; |
2729 | wake_up_all(&table->waitq); | |
2730 | out_unlock: | |
2731 | spin_unlock_bh(&efx->filter_lock); | |
2732 | finish_wait(&table->waitq, &wait); | |
2733 | return rc; | |
2734 | } | |
2735 | ||
2736 | static int efx_ef10_filter_remove_safe(struct efx_nic *efx, | |
2737 | enum efx_filter_priority priority, | |
2738 | u32 filter_id) | |
2739 | { | |
fbd79120 BH |
2740 | return efx_ef10_filter_remove_internal(efx, 1U << priority, |
2741 | filter_id, false); | |
8127d661 BH |
2742 | } |
2743 | ||
2744 | static int efx_ef10_filter_get_safe(struct efx_nic *efx, | |
2745 | enum efx_filter_priority priority, | |
2746 | u32 filter_id, struct efx_filter_spec *spec) | |
2747 | { | |
2748 | unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; | |
2749 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2750 | const struct efx_filter_spec *saved_spec; | |
2751 | int rc; | |
2752 | ||
2753 | spin_lock_bh(&efx->filter_lock); | |
2754 | saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); | |
2755 | if (saved_spec && saved_spec->priority == priority && | |
2756 | efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) == | |
2757 | filter_id / HUNT_FILTER_TBL_ROWS) { | |
2758 | *spec = *saved_spec; | |
2759 | rc = 0; | |
2760 | } else { | |
2761 | rc = -ENOENT; | |
2762 | } | |
2763 | spin_unlock_bh(&efx->filter_lock); | |
2764 | return rc; | |
2765 | } | |
2766 | ||
fbd79120 | 2767 | static int efx_ef10_filter_clear_rx(struct efx_nic *efx, |
8127d661 BH |
2768 | enum efx_filter_priority priority) |
2769 | { | |
fbd79120 BH |
2770 | unsigned int priority_mask; |
2771 | unsigned int i; | |
2772 | int rc; | |
2773 | ||
2774 | priority_mask = (((1U << (priority + 1)) - 1) & | |
2775 | ~(1U << EFX_FILTER_PRI_AUTO)); | |
2776 | ||
2777 | for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { | |
2778 | rc = efx_ef10_filter_remove_internal(efx, priority_mask, | |
2779 | i, true); | |
2780 | if (rc && rc != -ENOENT) | |
2781 | return rc; | |
2782 | } | |
2783 | ||
2784 | return 0; | |
8127d661 BH |
2785 | } |
2786 | ||
2787 | static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, | |
2788 | enum efx_filter_priority priority) | |
2789 | { | |
2790 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2791 | unsigned int filter_idx; | |
2792 | s32 count = 0; | |
2793 | ||
2794 | spin_lock_bh(&efx->filter_lock); | |
2795 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { | |
2796 | if (table->entry[filter_idx].spec && | |
2797 | efx_ef10_filter_entry_spec(table, filter_idx)->priority == | |
2798 | priority) | |
2799 | ++count; | |
2800 | } | |
2801 | spin_unlock_bh(&efx->filter_lock); | |
2802 | return count; | |
2803 | } | |
2804 | ||
2805 | static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) | |
2806 | { | |
2807 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2808 | ||
2809 | return table->rx_match_count * HUNT_FILTER_TBL_ROWS; | |
2810 | } | |
2811 | ||
2812 | static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, | |
2813 | enum efx_filter_priority priority, | |
2814 | u32 *buf, u32 size) | |
2815 | { | |
2816 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2817 | struct efx_filter_spec *spec; | |
2818 | unsigned int filter_idx; | |
2819 | s32 count = 0; | |
2820 | ||
2821 | spin_lock_bh(&efx->filter_lock); | |
2822 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { | |
2823 | spec = efx_ef10_filter_entry_spec(table, filter_idx); | |
2824 | if (spec && spec->priority == priority) { | |
2825 | if (count == size) { | |
2826 | count = -EMSGSIZE; | |
2827 | break; | |
2828 | } | |
2829 | buf[count++] = (efx_ef10_filter_rx_match_pri( | |
2830 | table, spec->match_flags) * | |
2831 | HUNT_FILTER_TBL_ROWS + | |
2832 | filter_idx); | |
2833 | } | |
2834 | } | |
2835 | spin_unlock_bh(&efx->filter_lock); | |
2836 | return count; | |
2837 | } | |
2838 | ||
2839 | #ifdef CONFIG_RFS_ACCEL | |
2840 | ||
2841 | static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; | |
2842 | ||
2843 | static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, | |
2844 | struct efx_filter_spec *spec) | |
2845 | { | |
2846 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2847 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); | |
2848 | struct efx_filter_spec *saved_spec; | |
2849 | unsigned int hash, i, depth = 1; | |
2850 | bool replacing = false; | |
2851 | int ins_index = -1; | |
2852 | u64 cookie; | |
2853 | s32 rc; | |
2854 | ||
2855 | /* Must be an RX filter without RSS and not for a multicast | |
2856 | * destination address (RFS only works for connected sockets). | |
2857 | * These restrictions allow us to pass only a tiny amount of | |
2858 | * data through to the completion function. | |
2859 | */ | |
2860 | EFX_WARN_ON_PARANOID(spec->flags != | |
2861 | (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); | |
2862 | EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); | |
2863 | EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); | |
2864 | ||
2865 | hash = efx_ef10_filter_hash(spec); | |
2866 | ||
2867 | spin_lock_bh(&efx->filter_lock); | |
2868 | ||
2869 | /* Find any existing filter with the same match tuple or else | |
2870 | * a free slot to insert at. If an existing filter is busy, | |
2871 | * we have to give up. | |
2872 | */ | |
2873 | for (;;) { | |
2874 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); | |
2875 | saved_spec = efx_ef10_filter_entry_spec(table, i); | |
2876 | ||
2877 | if (!saved_spec) { | |
2878 | if (ins_index < 0) | |
2879 | ins_index = i; | |
2880 | } else if (efx_ef10_filter_equal(spec, saved_spec)) { | |
2881 | if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { | |
2882 | rc = -EBUSY; | |
2883 | goto fail_unlock; | |
2884 | } | |
8127d661 BH |
2885 | if (spec->priority < saved_spec->priority) { |
2886 | rc = -EPERM; | |
2887 | goto fail_unlock; | |
2888 | } | |
2889 | ins_index = i; | |
2890 | break; | |
2891 | } | |
2892 | ||
2893 | /* Once we reach the maximum search depth, use the | |
2894 | * first suitable slot or return -EBUSY if there was | |
2895 | * none | |
2896 | */ | |
2897 | if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { | |
2898 | if (ins_index < 0) { | |
2899 | rc = -EBUSY; | |
2900 | goto fail_unlock; | |
2901 | } | |
2902 | break; | |
2903 | } | |
2904 | ||
2905 | ++depth; | |
2906 | } | |
2907 | ||
2908 | /* Create a software table entry if necessary, and mark it | |
2909 | * busy. We might yet fail to insert, but any attempt to | |
2910 | * insert a conflicting filter while we're waiting for the | |
2911 | * firmware must find the busy entry. | |
2912 | */ | |
2913 | saved_spec = efx_ef10_filter_entry_spec(table, ins_index); | |
2914 | if (saved_spec) { | |
2915 | replacing = true; | |
2916 | } else { | |
2917 | saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); | |
2918 | if (!saved_spec) { | |
2919 | rc = -ENOMEM; | |
2920 | goto fail_unlock; | |
2921 | } | |
2922 | *saved_spec = *spec; | |
2923 | } | |
2924 | efx_ef10_filter_set_entry(table, ins_index, saved_spec, | |
2925 | EFX_EF10_FILTER_FLAG_BUSY); | |
2926 | ||
2927 | spin_unlock_bh(&efx->filter_lock); | |
2928 | ||
2929 | /* Pack up the variables needed on completion */ | |
2930 | cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; | |
2931 | ||
2932 | efx_ef10_filter_push_prep(efx, spec, inbuf, | |
2933 | table->entry[ins_index].handle, replacing); | |
2934 | efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), | |
2935 | MC_CMD_FILTER_OP_OUT_LEN, | |
2936 | efx_ef10_filter_rfs_insert_complete, cookie); | |
2937 | ||
2938 | return ins_index; | |
2939 | ||
2940 | fail_unlock: | |
2941 | spin_unlock_bh(&efx->filter_lock); | |
2942 | return rc; | |
2943 | } | |
2944 | ||
2945 | static void | |
2946 | efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, | |
2947 | int rc, efx_dword_t *outbuf, | |
2948 | size_t outlen_actual) | |
2949 | { | |
2950 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2951 | unsigned int ins_index, dmaq_id; | |
2952 | struct efx_filter_spec *spec; | |
2953 | bool replacing; | |
2954 | ||
2955 | /* Unpack the cookie */ | |
2956 | replacing = cookie >> 31; | |
2957 | ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); | |
2958 | dmaq_id = cookie & 0xffff; | |
2959 | ||
2960 | spin_lock_bh(&efx->filter_lock); | |
2961 | spec = efx_ef10_filter_entry_spec(table, ins_index); | |
2962 | if (rc == 0) { | |
2963 | table->entry[ins_index].handle = | |
2964 | MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); | |
2965 | if (replacing) | |
2966 | spec->dmaq_id = dmaq_id; | |
2967 | } else if (!replacing) { | |
2968 | kfree(spec); | |
2969 | spec = NULL; | |
2970 | } | |
2971 | efx_ef10_filter_set_entry(table, ins_index, spec, 0); | |
2972 | spin_unlock_bh(&efx->filter_lock); | |
2973 | ||
2974 | wake_up_all(&table->waitq); | |
2975 | } | |
2976 | ||
2977 | static void | |
2978 | efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, | |
2979 | unsigned long filter_idx, | |
2980 | int rc, efx_dword_t *outbuf, | |
2981 | size_t outlen_actual); | |
2982 | ||
2983 | static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, | |
2984 | unsigned int filter_idx) | |
2985 | { | |
2986 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2987 | struct efx_filter_spec *spec = | |
2988 | efx_ef10_filter_entry_spec(table, filter_idx); | |
2989 | MCDI_DECLARE_BUF(inbuf, | |
2990 | MC_CMD_FILTER_OP_IN_HANDLE_OFST + | |
2991 | MC_CMD_FILTER_OP_IN_HANDLE_LEN); | |
2992 | ||
2993 | if (!spec || | |
2994 | (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || | |
2995 | spec->priority != EFX_FILTER_PRI_HINT || | |
2996 | !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, | |
2997 | flow_id, filter_idx)) | |
2998 | return false; | |
2999 | ||
3000 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
3001 | MC_CMD_FILTER_OP_IN_OP_REMOVE); | |
3002 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, | |
3003 | table->entry[filter_idx].handle); | |
3004 | if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, | |
3005 | efx_ef10_filter_rfs_expire_complete, filter_idx)) | |
3006 | return false; | |
3007 | ||
3008 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; | |
3009 | return true; | |
3010 | } | |
3011 | ||
3012 | static void | |
3013 | efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, | |
3014 | unsigned long filter_idx, | |
3015 | int rc, efx_dword_t *outbuf, | |
3016 | size_t outlen_actual) | |
3017 | { | |
3018 | struct efx_ef10_filter_table *table = efx->filter_state; | |
3019 | struct efx_filter_spec *spec = | |
3020 | efx_ef10_filter_entry_spec(table, filter_idx); | |
3021 | ||
3022 | spin_lock_bh(&efx->filter_lock); | |
3023 | if (rc == 0) { | |
3024 | kfree(spec); | |
3025 | efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); | |
3026 | } | |
3027 | table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; | |
3028 | wake_up_all(&table->waitq); | |
3029 | spin_unlock_bh(&efx->filter_lock); | |
3030 | } | |
3031 | ||
3032 | #endif /* CONFIG_RFS_ACCEL */ | |
3033 | ||
3034 | static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) | |
3035 | { | |
3036 | int match_flags = 0; | |
3037 | ||
3038 | #define MAP_FLAG(gen_flag, mcdi_field) { \ | |
3039 | u32 old_mcdi_flags = mcdi_flags; \ | |
3040 | mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ | |
3041 | mcdi_field ## _LBN); \ | |
3042 | if (mcdi_flags != old_mcdi_flags) \ | |
3043 | match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ | |
3044 | } | |
3045 | MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); | |
3046 | MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); | |
3047 | MAP_FLAG(REM_HOST, SRC_IP); | |
3048 | MAP_FLAG(LOC_HOST, DST_IP); | |
3049 | MAP_FLAG(REM_MAC, SRC_MAC); | |
3050 | MAP_FLAG(REM_PORT, SRC_PORT); | |
3051 | MAP_FLAG(LOC_MAC, DST_MAC); | |
3052 | MAP_FLAG(LOC_PORT, DST_PORT); | |
3053 | MAP_FLAG(ETHER_TYPE, ETHER_TYPE); | |
3054 | MAP_FLAG(INNER_VID, INNER_VLAN); | |
3055 | MAP_FLAG(OUTER_VID, OUTER_VLAN); | |
3056 | MAP_FLAG(IP_PROTO, IP_PROTO); | |
3057 | #undef MAP_FLAG | |
3058 | ||
3059 | /* Did we map them all? */ | |
3060 | if (mcdi_flags) | |
3061 | return -EINVAL; | |
3062 | ||
3063 | return match_flags; | |
3064 | } | |
3065 | ||
3066 | static int efx_ef10_filter_table_probe(struct efx_nic *efx) | |
3067 | { | |
3068 | MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); | |
3069 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); | |
3070 | unsigned int pd_match_pri, pd_match_count; | |
3071 | struct efx_ef10_filter_table *table; | |
3072 | size_t outlen; | |
3073 | int rc; | |
3074 | ||
3075 | table = kzalloc(sizeof(*table), GFP_KERNEL); | |
3076 | if (!table) | |
3077 | return -ENOMEM; | |
3078 | ||
3079 | /* Find out which RX filter types are supported, and their priorities */ | |
3080 | MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, | |
3081 | MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); | |
3082 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, | |
3083 | inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), | |
3084 | &outlen); | |
3085 | if (rc) | |
3086 | goto fail; | |
3087 | pd_match_count = MCDI_VAR_ARRAY_LEN( | |
3088 | outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); | |
3089 | table->rx_match_count = 0; | |
3090 | ||
3091 | for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { | |
3092 | u32 mcdi_flags = | |
3093 | MCDI_ARRAY_DWORD( | |
3094 | outbuf, | |
3095 | GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, | |
3096 | pd_match_pri); | |
3097 | rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); | |
3098 | if (rc < 0) { | |
3099 | netif_dbg(efx, probe, efx->net_dev, | |
3100 | "%s: fw flags %#x pri %u not supported in driver\n", | |
3101 | __func__, mcdi_flags, pd_match_pri); | |
3102 | } else { | |
3103 | netif_dbg(efx, probe, efx->net_dev, | |
3104 | "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", | |
3105 | __func__, mcdi_flags, pd_match_pri, | |
3106 | rc, table->rx_match_count); | |
3107 | table->rx_match_flags[table->rx_match_count++] = rc; | |
3108 | } | |
3109 | } | |
3110 | ||
3111 | table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); | |
3112 | if (!table->entry) { | |
3113 | rc = -ENOMEM; | |
3114 | goto fail; | |
3115 | } | |
3116 | ||
3117 | efx->filter_state = table; | |
3118 | init_waitqueue_head(&table->waitq); | |
3119 | return 0; | |
3120 | ||
3121 | fail: | |
3122 | kfree(table); | |
3123 | return rc; | |
3124 | } | |
3125 | ||
3126 | static void efx_ef10_filter_table_restore(struct efx_nic *efx) | |
3127 | { | |
3128 | struct efx_ef10_filter_table *table = efx->filter_state; | |
3129 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
3130 | struct efx_filter_spec *spec; | |
3131 | unsigned int filter_idx; | |
3132 | bool failed = false; | |
3133 | int rc; | |
3134 | ||
3135 | if (!nic_data->must_restore_filters) | |
3136 | return; | |
3137 | ||
3138 | spin_lock_bh(&efx->filter_lock); | |
3139 | ||
3140 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { | |
3141 | spec = efx_ef10_filter_entry_spec(table, filter_idx); | |
3142 | if (!spec) | |
3143 | continue; | |
3144 | ||
3145 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; | |
3146 | spin_unlock_bh(&efx->filter_lock); | |
3147 | ||
3148 | rc = efx_ef10_filter_push(efx, spec, | |
3149 | &table->entry[filter_idx].handle, | |
3150 | false); | |
3151 | if (rc) | |
3152 | failed = true; | |
3153 | ||
3154 | spin_lock_bh(&efx->filter_lock); | |
3155 | if (rc) { | |
3156 | kfree(spec); | |
3157 | efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); | |
3158 | } else { | |
3159 | table->entry[filter_idx].spec &= | |
3160 | ~EFX_EF10_FILTER_FLAG_BUSY; | |
3161 | } | |
3162 | } | |
3163 | ||
3164 | spin_unlock_bh(&efx->filter_lock); | |
3165 | ||
3166 | if (failed) | |
3167 | netif_err(efx, hw, efx->net_dev, | |
3168 | "unable to restore all filters\n"); | |
3169 | else | |
3170 | nic_data->must_restore_filters = false; | |
3171 | } | |
3172 | ||
3173 | static void efx_ef10_filter_table_remove(struct efx_nic *efx) | |
3174 | { | |
3175 | struct efx_ef10_filter_table *table = efx->filter_state; | |
3176 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); | |
3177 | struct efx_filter_spec *spec; | |
3178 | unsigned int filter_idx; | |
3179 | int rc; | |
3180 | ||
3181 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { | |
3182 | spec = efx_ef10_filter_entry_spec(table, filter_idx); | |
3183 | if (!spec) | |
3184 | continue; | |
3185 | ||
3186 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
3187 | efx_ef10_filter_is_exclusive(spec) ? | |
3188 | MC_CMD_FILTER_OP_IN_OP_REMOVE : | |
3189 | MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); | |
3190 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, | |
3191 | table->entry[filter_idx].handle); | |
3192 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), | |
3193 | NULL, 0, NULL); | |
48ce5634 BH |
3194 | if (rc) |
3195 | netdev_WARN(efx->net_dev, | |
3196 | "filter_idx=%#x handle=%#llx\n", | |
3197 | filter_idx, | |
3198 | table->entry[filter_idx].handle); | |
8127d661 BH |
3199 | kfree(spec); |
3200 | } | |
3201 | ||
3202 | vfree(table->entry); | |
3203 | kfree(table); | |
3204 | } | |
3205 | ||
3206 | static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) | |
3207 | { | |
3208 | struct efx_ef10_filter_table *table = efx->filter_state; | |
3209 | struct net_device *net_dev = efx->net_dev; | |
3210 | struct efx_filter_spec spec; | |
3211 | bool remove_failed = false; | |
3212 | struct netdev_hw_addr *uc; | |
3213 | struct netdev_hw_addr *mc; | |
3214 | unsigned int filter_idx; | |
3215 | int i, n, rc; | |
3216 | ||
3217 | if (!efx_dev_registered(efx)) | |
3218 | return; | |
3219 | ||
3220 | /* Mark old filters that may need to be removed */ | |
3221 | spin_lock_bh(&efx->filter_lock); | |
b59e6ef8 | 3222 | n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count; |
8127d661 | 3223 | for (i = 0; i < n; i++) { |
b59e6ef8 BH |
3224 | filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS; |
3225 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; | |
8127d661 | 3226 | } |
b59e6ef8 | 3227 | n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count; |
8127d661 | 3228 | for (i = 0; i < n; i++) { |
b59e6ef8 BH |
3229 | filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS; |
3230 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; | |
8127d661 BH |
3231 | } |
3232 | spin_unlock_bh(&efx->filter_lock); | |
3233 | ||
3234 | /* Copy/convert the address lists; add the primary station | |
3235 | * address and broadcast address | |
3236 | */ | |
3237 | netif_addr_lock_bh(net_dev); | |
3238 | if (net_dev->flags & IFF_PROMISC || | |
b59e6ef8 BH |
3239 | netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) { |
3240 | table->dev_uc_count = -1; | |
8127d661 | 3241 | } else { |
b59e6ef8 | 3242 | table->dev_uc_count = 1 + netdev_uc_count(net_dev); |
cd84ff4d | 3243 | ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr); |
8127d661 BH |
3244 | i = 1; |
3245 | netdev_for_each_uc_addr(uc, net_dev) { | |
cd84ff4d | 3246 | ether_addr_copy(table->dev_uc_list[i].addr, uc->addr); |
8127d661 BH |
3247 | i++; |
3248 | } | |
3249 | } | |
3250 | if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) || | |
b59e6ef8 BH |
3251 | netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) { |
3252 | table->dev_mc_count = -1; | |
8127d661 | 3253 | } else { |
b59e6ef8 BH |
3254 | table->dev_mc_count = 1 + netdev_mc_count(net_dev); |
3255 | eth_broadcast_addr(table->dev_mc_list[0].addr); | |
8127d661 BH |
3256 | i = 1; |
3257 | netdev_for_each_mc_addr(mc, net_dev) { | |
cd84ff4d | 3258 | ether_addr_copy(table->dev_mc_list[i].addr, mc->addr); |
8127d661 BH |
3259 | i++; |
3260 | } | |
3261 | } | |
3262 | netif_addr_unlock_bh(net_dev); | |
3263 | ||
3264 | /* Insert/renew unicast filters */ | |
b59e6ef8 BH |
3265 | if (table->dev_uc_count >= 0) { |
3266 | for (i = 0; i < table->dev_uc_count; i++) { | |
7665d1ab BH |
3267 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
3268 | EFX_FILTER_FLAG_RX_RSS, | |
8127d661 BH |
3269 | 0); |
3270 | efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, | |
b59e6ef8 | 3271 | table->dev_uc_list[i].addr); |
8127d661 BH |
3272 | rc = efx_ef10_filter_insert(efx, &spec, true); |
3273 | if (rc < 0) { | |
3274 | /* Fall back to unicast-promisc */ | |
3275 | while (i--) | |
3276 | efx_ef10_filter_remove_safe( | |
7665d1ab | 3277 | efx, EFX_FILTER_PRI_AUTO, |
b59e6ef8 BH |
3278 | table->dev_uc_list[i].id); |
3279 | table->dev_uc_count = -1; | |
8127d661 BH |
3280 | break; |
3281 | } | |
b59e6ef8 | 3282 | table->dev_uc_list[i].id = rc; |
8127d661 BH |
3283 | } |
3284 | } | |
b59e6ef8 | 3285 | if (table->dev_uc_count < 0) { |
7665d1ab BH |
3286 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
3287 | EFX_FILTER_FLAG_RX_RSS, | |
8127d661 BH |
3288 | 0); |
3289 | efx_filter_set_uc_def(&spec); | |
3290 | rc = efx_ef10_filter_insert(efx, &spec, true); | |
3291 | if (rc < 0) { | |
3292 | WARN_ON(1); | |
b59e6ef8 | 3293 | table->dev_uc_count = 0; |
8127d661 | 3294 | } else { |
b59e6ef8 | 3295 | table->dev_uc_list[0].id = rc; |
8127d661 BH |
3296 | } |
3297 | } | |
3298 | ||
3299 | /* Insert/renew multicast filters */ | |
b59e6ef8 BH |
3300 | if (table->dev_mc_count >= 0) { |
3301 | for (i = 0; i < table->dev_mc_count; i++) { | |
7665d1ab BH |
3302 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
3303 | EFX_FILTER_FLAG_RX_RSS, | |
8127d661 BH |
3304 | 0); |
3305 | efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, | |
b59e6ef8 | 3306 | table->dev_mc_list[i].addr); |
8127d661 BH |
3307 | rc = efx_ef10_filter_insert(efx, &spec, true); |
3308 | if (rc < 0) { | |
3309 | /* Fall back to multicast-promisc */ | |
3310 | while (i--) | |
3311 | efx_ef10_filter_remove_safe( | |
7665d1ab | 3312 | efx, EFX_FILTER_PRI_AUTO, |
b59e6ef8 BH |
3313 | table->dev_mc_list[i].id); |
3314 | table->dev_mc_count = -1; | |
8127d661 BH |
3315 | break; |
3316 | } | |
b59e6ef8 | 3317 | table->dev_mc_list[i].id = rc; |
8127d661 BH |
3318 | } |
3319 | } | |
b59e6ef8 | 3320 | if (table->dev_mc_count < 0) { |
7665d1ab BH |
3321 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
3322 | EFX_FILTER_FLAG_RX_RSS, | |
8127d661 BH |
3323 | 0); |
3324 | efx_filter_set_mc_def(&spec); | |
3325 | rc = efx_ef10_filter_insert(efx, &spec, true); | |
3326 | if (rc < 0) { | |
3327 | WARN_ON(1); | |
b59e6ef8 | 3328 | table->dev_mc_count = 0; |
8127d661 | 3329 | } else { |
b59e6ef8 | 3330 | table->dev_mc_list[0].id = rc; |
8127d661 BH |
3331 | } |
3332 | } | |
3333 | ||
3334 | /* Remove filters that weren't renewed. Since nothing else | |
b59e6ef8 | 3335 | * changes the AUTO_OLD flag or removes these filters, we |
8127d661 BH |
3336 | * don't need to hold the filter_lock while scanning for |
3337 | * these filters. | |
3338 | */ | |
3339 | for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { | |
3340 | if (ACCESS_ONCE(table->entry[i].spec) & | |
b59e6ef8 | 3341 | EFX_EF10_FILTER_FLAG_AUTO_OLD) { |
7665d1ab | 3342 | if (efx_ef10_filter_remove_internal( |
fbd79120 BH |
3343 | efx, 1U << EFX_FILTER_PRI_AUTO, |
3344 | i, true) < 0) | |
8127d661 BH |
3345 | remove_failed = true; |
3346 | } | |
3347 | } | |
3348 | WARN_ON(remove_failed); | |
3349 | } | |
3350 | ||
3351 | static int efx_ef10_mac_reconfigure(struct efx_nic *efx) | |
3352 | { | |
3353 | efx_ef10_filter_sync_rx_mode(efx); | |
3354 | ||
3355 | return efx_mcdi_set_mac(efx); | |
3356 | } | |
3357 | ||
74cd60a4 JC |
3358 | static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) |
3359 | { | |
3360 | MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); | |
3361 | ||
3362 | MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); | |
3363 | return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), | |
3364 | NULL, 0, NULL); | |
3365 | } | |
3366 | ||
3367 | /* MC BISTs follow a different poll mechanism to phy BISTs. | |
3368 | * The BIST is done in the poll handler on the MC, and the MCDI command | |
3369 | * will block until the BIST is done. | |
3370 | */ | |
3371 | static int efx_ef10_poll_bist(struct efx_nic *efx) | |
3372 | { | |
3373 | int rc; | |
3374 | MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); | |
3375 | size_t outlen; | |
3376 | u32 result; | |
3377 | ||
3378 | rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, | |
3379 | outbuf, sizeof(outbuf), &outlen); | |
3380 | if (rc != 0) | |
3381 | return rc; | |
3382 | ||
3383 | if (outlen < MC_CMD_POLL_BIST_OUT_LEN) | |
3384 | return -EIO; | |
3385 | ||
3386 | result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); | |
3387 | switch (result) { | |
3388 | case MC_CMD_POLL_BIST_PASSED: | |
3389 | netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); | |
3390 | return 0; | |
3391 | case MC_CMD_POLL_BIST_TIMEOUT: | |
3392 | netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); | |
3393 | return -EIO; | |
3394 | case MC_CMD_POLL_BIST_FAILED: | |
3395 | netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); | |
3396 | return -EIO; | |
3397 | default: | |
3398 | netif_err(efx, hw, efx->net_dev, | |
3399 | "BIST returned unknown result %u", result); | |
3400 | return -EIO; | |
3401 | } | |
3402 | } | |
3403 | ||
3404 | static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) | |
3405 | { | |
3406 | int rc; | |
3407 | ||
3408 | netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); | |
3409 | ||
3410 | rc = efx_ef10_start_bist(efx, bist_type); | |
3411 | if (rc != 0) | |
3412 | return rc; | |
3413 | ||
3414 | return efx_ef10_poll_bist(efx); | |
3415 | } | |
3416 | ||
3417 | static int | |
3418 | efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) | |
3419 | { | |
3420 | int rc, rc2; | |
3421 | ||
3422 | efx_reset_down(efx, RESET_TYPE_WORLD); | |
3423 | ||
3424 | rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, | |
3425 | NULL, 0, NULL, 0, NULL); | |
3426 | if (rc != 0) | |
3427 | goto out; | |
3428 | ||
3429 | tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; | |
3430 | tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; | |
3431 | ||
3432 | rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); | |
3433 | ||
3434 | out: | |
3435 | rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); | |
3436 | return rc ? rc : rc2; | |
3437 | } | |
3438 | ||
8127d661 BH |
3439 | #ifdef CONFIG_SFC_MTD |
3440 | ||
3441 | struct efx_ef10_nvram_type_info { | |
3442 | u16 type, type_mask; | |
3443 | u8 port; | |
3444 | const char *name; | |
3445 | }; | |
3446 | ||
3447 | static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { | |
3448 | { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, | |
3449 | { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, | |
3450 | { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, | |
3451 | { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, | |
3452 | { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, | |
3453 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, | |
3454 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, | |
3455 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, | |
3456 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, | |
a84f3bf9 | 3457 | { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, |
8127d661 BH |
3458 | { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, |
3459 | }; | |
3460 | ||
3461 | static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, | |
3462 | struct efx_mcdi_mtd_partition *part, | |
3463 | unsigned int type) | |
3464 | { | |
3465 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); | |
3466 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); | |
3467 | const struct efx_ef10_nvram_type_info *info; | |
3468 | size_t size, erase_size, outlen; | |
3469 | bool protected; | |
3470 | int rc; | |
3471 | ||
3472 | for (info = efx_ef10_nvram_types; ; info++) { | |
3473 | if (info == | |
3474 | efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) | |
3475 | return -ENODEV; | |
3476 | if ((type & ~info->type_mask) == info->type) | |
3477 | break; | |
3478 | } | |
3479 | if (info->port != efx_port_num(efx)) | |
3480 | return -ENODEV; | |
3481 | ||
3482 | rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); | |
3483 | if (rc) | |
3484 | return rc; | |
3485 | if (protected) | |
3486 | return -ENODEV; /* hide it */ | |
3487 | ||
3488 | part->nvram_type = type; | |
3489 | ||
3490 | MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); | |
3491 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), | |
3492 | outbuf, sizeof(outbuf), &outlen); | |
3493 | if (rc) | |
3494 | return rc; | |
3495 | if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) | |
3496 | return -EIO; | |
3497 | if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & | |
3498 | (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) | |
3499 | part->fw_subtype = MCDI_DWORD(outbuf, | |
3500 | NVRAM_METADATA_OUT_SUBTYPE); | |
3501 | ||
3502 | part->common.dev_type_name = "EF10 NVRAM manager"; | |
3503 | part->common.type_name = info->name; | |
3504 | ||
3505 | part->common.mtd.type = MTD_NORFLASH; | |
3506 | part->common.mtd.flags = MTD_CAP_NORFLASH; | |
3507 | part->common.mtd.size = size; | |
3508 | part->common.mtd.erasesize = erase_size; | |
3509 | ||
3510 | return 0; | |
3511 | } | |
3512 | ||
3513 | static int efx_ef10_mtd_probe(struct efx_nic *efx) | |
3514 | { | |
3515 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); | |
3516 | struct efx_mcdi_mtd_partition *parts; | |
3517 | size_t outlen, n_parts_total, i, n_parts; | |
3518 | unsigned int type; | |
3519 | int rc; | |
3520 | ||
3521 | ASSERT_RTNL(); | |
3522 | ||
3523 | BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); | |
3524 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, | |
3525 | outbuf, sizeof(outbuf), &outlen); | |
3526 | if (rc) | |
3527 | return rc; | |
3528 | if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) | |
3529 | return -EIO; | |
3530 | ||
3531 | n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); | |
3532 | if (n_parts_total > | |
3533 | MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) | |
3534 | return -EIO; | |
3535 | ||
3536 | parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); | |
3537 | if (!parts) | |
3538 | return -ENOMEM; | |
3539 | ||
3540 | n_parts = 0; | |
3541 | for (i = 0; i < n_parts_total; i++) { | |
3542 | type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, | |
3543 | i); | |
3544 | rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); | |
3545 | if (rc == 0) | |
3546 | n_parts++; | |
3547 | else if (rc != -ENODEV) | |
3548 | goto fail; | |
3549 | } | |
3550 | ||
3551 | rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); | |
3552 | fail: | |
3553 | if (rc) | |
3554 | kfree(parts); | |
3555 | return rc; | |
3556 | } | |
3557 | ||
3558 | #endif /* CONFIG_SFC_MTD */ | |
3559 | ||
3560 | static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) | |
3561 | { | |
3562 | _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); | |
3563 | } | |
3564 | ||
02246a7f SS |
3565 | static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, |
3566 | u32 host_time) {} | |
3567 | ||
bd9a265d JC |
3568 | static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, |
3569 | bool temp) | |
3570 | { | |
3571 | MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); | |
3572 | int rc; | |
3573 | ||
3574 | if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || | |
3575 | channel->sync_events_state == SYNC_EVENTS_VALID || | |
3576 | (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) | |
3577 | return 0; | |
3578 | channel->sync_events_state = SYNC_EVENTS_REQUESTED; | |
3579 | ||
3580 | MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); | |
3581 | MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); | |
3582 | MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, | |
3583 | channel->channel); | |
3584 | ||
3585 | rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, | |
3586 | inbuf, sizeof(inbuf), NULL, 0, NULL); | |
3587 | ||
3588 | if (rc != 0) | |
3589 | channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : | |
3590 | SYNC_EVENTS_DISABLED; | |
3591 | ||
3592 | return rc; | |
3593 | } | |
3594 | ||
3595 | static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, | |
3596 | bool temp) | |
3597 | { | |
3598 | MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); | |
3599 | int rc; | |
3600 | ||
3601 | if (channel->sync_events_state == SYNC_EVENTS_DISABLED || | |
3602 | (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) | |
3603 | return 0; | |
3604 | if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { | |
3605 | channel->sync_events_state = SYNC_EVENTS_DISABLED; | |
3606 | return 0; | |
3607 | } | |
3608 | channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : | |
3609 | SYNC_EVENTS_DISABLED; | |
3610 | ||
3611 | MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); | |
3612 | MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); | |
3613 | MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, | |
3614 | MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); | |
3615 | MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, | |
3616 | channel->channel); | |
3617 | ||
3618 | rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, | |
3619 | inbuf, sizeof(inbuf), NULL, 0, NULL); | |
3620 | ||
3621 | return rc; | |
3622 | } | |
3623 | ||
3624 | static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, | |
3625 | bool temp) | |
3626 | { | |
3627 | int (*set)(struct efx_channel *channel, bool temp); | |
3628 | struct efx_channel *channel; | |
3629 | ||
3630 | set = en ? | |
3631 | efx_ef10_rx_enable_timestamping : | |
3632 | efx_ef10_rx_disable_timestamping; | |
3633 | ||
3634 | efx_for_each_channel(channel, efx) { | |
3635 | int rc = set(channel, temp); | |
3636 | if (en && rc != 0) { | |
3637 | efx_ef10_ptp_set_ts_sync_events(efx, false, temp); | |
3638 | return rc; | |
3639 | } | |
3640 | } | |
3641 | ||
3642 | return 0; | |
3643 | } | |
3644 | ||
02246a7f SS |
3645 | static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, |
3646 | struct hwtstamp_config *init) | |
3647 | { | |
3648 | return -EOPNOTSUPP; | |
3649 | } | |
3650 | ||
bd9a265d JC |
3651 | static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, |
3652 | struct hwtstamp_config *init) | |
3653 | { | |
3654 | int rc; | |
3655 | ||
3656 | switch (init->rx_filter) { | |
3657 | case HWTSTAMP_FILTER_NONE: | |
3658 | efx_ef10_ptp_set_ts_sync_events(efx, false, false); | |
3659 | /* if TX timestamping is still requested then leave PTP on */ | |
3660 | return efx_ptp_change_mode(efx, | |
3661 | init->tx_type != HWTSTAMP_TX_OFF, 0); | |
3662 | case HWTSTAMP_FILTER_ALL: | |
3663 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
3664 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
3665 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
3666 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
3667 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3668 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
3669 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
3670 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
3671 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
3672 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
3673 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
3674 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
3675 | init->rx_filter = HWTSTAMP_FILTER_ALL; | |
3676 | rc = efx_ptp_change_mode(efx, true, 0); | |
3677 | if (!rc) | |
3678 | rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); | |
3679 | if (rc) | |
3680 | efx_ptp_change_mode(efx, false, 0); | |
3681 | return rc; | |
3682 | default: | |
3683 | return -ERANGE; | |
3684 | } | |
3685 | } | |
3686 | ||
02246a7f SS |
3687 | const struct efx_nic_type efx_hunt_a0_vf_nic_type = { |
3688 | .mem_bar = EFX_MEM_VF_BAR, | |
3689 | .mem_map_size = efx_ef10_mem_map_size, | |
3690 | .probe = efx_ef10_probe_vf, | |
3691 | .remove = efx_ef10_remove, | |
3692 | .dimension_resources = efx_ef10_dimension_resources, | |
3693 | .init = efx_ef10_init_nic, | |
3694 | .fini = efx_port_dummy_op_void, | |
3695 | .map_reset_reason = efx_mcdi_map_reset_reason, | |
3696 | .map_reset_flags = efx_ef10_map_reset_flags, | |
3697 | .reset = efx_ef10_reset, | |
3698 | .probe_port = efx_mcdi_port_probe, | |
3699 | .remove_port = efx_mcdi_port_remove, | |
3700 | .fini_dmaq = efx_ef10_fini_dmaq, | |
3701 | .prepare_flr = efx_ef10_prepare_flr, | |
3702 | .finish_flr = efx_port_dummy_op_void, | |
3703 | .describe_stats = efx_ef10_describe_stats, | |
3704 | .update_stats = efx_ef10_update_stats, | |
3705 | .start_stats = efx_port_dummy_op_void, | |
3706 | .pull_stats = efx_port_dummy_op_void, | |
3707 | .stop_stats = efx_port_dummy_op_void, | |
3708 | .set_id_led = efx_mcdi_set_id_led, | |
3709 | .push_irq_moderation = efx_ef10_push_irq_moderation, | |
3710 | .reconfigure_mac = efx_ef10_mac_reconfigure, | |
3711 | .check_mac_fault = efx_mcdi_mac_check_fault, | |
3712 | .reconfigure_port = efx_mcdi_port_reconfigure, | |
3713 | .get_wol = efx_ef10_get_wol_vf, | |
3714 | .set_wol = efx_ef10_set_wol_vf, | |
3715 | .resume_wol = efx_port_dummy_op_void, | |
3716 | .mcdi_request = efx_ef10_mcdi_request, | |
3717 | .mcdi_poll_response = efx_ef10_mcdi_poll_response, | |
3718 | .mcdi_read_response = efx_ef10_mcdi_read_response, | |
3719 | .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, | |
3720 | .irq_enable_master = efx_port_dummy_op_void, | |
3721 | .irq_test_generate = efx_ef10_irq_test_generate, | |
3722 | .irq_disable_non_ev = efx_port_dummy_op_void, | |
3723 | .irq_handle_msi = efx_ef10_msi_interrupt, | |
3724 | .irq_handle_legacy = efx_ef10_legacy_interrupt, | |
3725 | .tx_probe = efx_ef10_tx_probe, | |
3726 | .tx_init = efx_ef10_tx_init, | |
3727 | .tx_remove = efx_ef10_tx_remove, | |
3728 | .tx_write = efx_ef10_tx_write, | |
3729 | .rx_push_rss_config = efx_ef10_rx_push_rss_config, | |
3730 | .rx_probe = efx_ef10_rx_probe, | |
3731 | .rx_init = efx_ef10_rx_init, | |
3732 | .rx_remove = efx_ef10_rx_remove, | |
3733 | .rx_write = efx_ef10_rx_write, | |
3734 | .rx_defer_refill = efx_ef10_rx_defer_refill, | |
3735 | .ev_probe = efx_ef10_ev_probe, | |
3736 | .ev_init = efx_ef10_ev_init, | |
3737 | .ev_fini = efx_ef10_ev_fini, | |
3738 | .ev_remove = efx_ef10_ev_remove, | |
3739 | .ev_process = efx_ef10_ev_process, | |
3740 | .ev_read_ack = efx_ef10_ev_read_ack, | |
3741 | .ev_test_generate = efx_ef10_ev_test_generate, | |
3742 | .filter_table_probe = efx_ef10_filter_table_probe, | |
3743 | .filter_table_restore = efx_ef10_filter_table_restore, | |
3744 | .filter_table_remove = efx_ef10_filter_table_remove, | |
3745 | .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, | |
3746 | .filter_insert = efx_ef10_filter_insert, | |
3747 | .filter_remove_safe = efx_ef10_filter_remove_safe, | |
3748 | .filter_get_safe = efx_ef10_filter_get_safe, | |
3749 | .filter_clear_rx = efx_ef10_filter_clear_rx, | |
3750 | .filter_count_rx_used = efx_ef10_filter_count_rx_used, | |
3751 | .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, | |
3752 | .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, | |
3753 | #ifdef CONFIG_RFS_ACCEL | |
3754 | .filter_rfs_insert = efx_ef10_filter_rfs_insert, | |
3755 | .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, | |
3756 | #endif | |
3757 | #ifdef CONFIG_SFC_MTD | |
3758 | .mtd_probe = efx_port_dummy_op_int, | |
3759 | #endif | |
3760 | .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, | |
3761 | .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, | |
3762 | #ifdef CONFIG_SFC_SRIOV | |
7b8c7b54 SS |
3763 | .vswitching_probe = efx_ef10_vswitching_probe_vf, |
3764 | .vswitching_restore = efx_ef10_vswitching_restore_vf, | |
3765 | .vswitching_remove = efx_ef10_vswitching_remove_vf, | |
02246a7f SS |
3766 | #endif |
3767 | .revision = EFX_REV_HUNT_A0, | |
3768 | .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), | |
3769 | .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, | |
3770 | .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, | |
3771 | .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, | |
3772 | .can_rx_scatter = true, | |
3773 | .always_rx_scatter = true, | |
3774 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
3775 | .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, | |
3776 | .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
3777 | NETIF_F_RXHASH | NETIF_F_NTUPLE), | |
3778 | .mcdi_max_ver = 2, | |
3779 | .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, | |
3780 | .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | | |
3781 | 1 << HWTSTAMP_FILTER_ALL, | |
3782 | }; | |
3783 | ||
8127d661 | 3784 | const struct efx_nic_type efx_hunt_a0_nic_type = { |
02246a7f | 3785 | .mem_bar = EFX_MEM_BAR, |
8127d661 | 3786 | .mem_map_size = efx_ef10_mem_map_size, |
02246a7f | 3787 | .probe = efx_ef10_probe_pf, |
8127d661 BH |
3788 | .remove = efx_ef10_remove, |
3789 | .dimension_resources = efx_ef10_dimension_resources, | |
3790 | .init = efx_ef10_init_nic, | |
3791 | .fini = efx_port_dummy_op_void, | |
3792 | .map_reset_reason = efx_mcdi_map_reset_reason, | |
3793 | .map_reset_flags = efx_ef10_map_reset_flags, | |
3e336261 | 3794 | .reset = efx_ef10_reset, |
8127d661 BH |
3795 | .probe_port = efx_mcdi_port_probe, |
3796 | .remove_port = efx_mcdi_port_remove, | |
3797 | .fini_dmaq = efx_ef10_fini_dmaq, | |
e283546c EC |
3798 | .prepare_flr = efx_ef10_prepare_flr, |
3799 | .finish_flr = efx_port_dummy_op_void, | |
8127d661 BH |
3800 | .describe_stats = efx_ef10_describe_stats, |
3801 | .update_stats = efx_ef10_update_stats, | |
3802 | .start_stats = efx_mcdi_mac_start_stats, | |
f8f3b5ae | 3803 | .pull_stats = efx_mcdi_mac_pull_stats, |
8127d661 BH |
3804 | .stop_stats = efx_mcdi_mac_stop_stats, |
3805 | .set_id_led = efx_mcdi_set_id_led, | |
3806 | .push_irq_moderation = efx_ef10_push_irq_moderation, | |
3807 | .reconfigure_mac = efx_ef10_mac_reconfigure, | |
3808 | .check_mac_fault = efx_mcdi_mac_check_fault, | |
3809 | .reconfigure_port = efx_mcdi_port_reconfigure, | |
3810 | .get_wol = efx_ef10_get_wol, | |
3811 | .set_wol = efx_ef10_set_wol, | |
3812 | .resume_wol = efx_port_dummy_op_void, | |
74cd60a4 | 3813 | .test_chip = efx_ef10_test_chip, |
8127d661 BH |
3814 | .test_nvram = efx_mcdi_nvram_test_all, |
3815 | .mcdi_request = efx_ef10_mcdi_request, | |
3816 | .mcdi_poll_response = efx_ef10_mcdi_poll_response, | |
3817 | .mcdi_read_response = efx_ef10_mcdi_read_response, | |
3818 | .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, | |
3819 | .irq_enable_master = efx_port_dummy_op_void, | |
3820 | .irq_test_generate = efx_ef10_irq_test_generate, | |
3821 | .irq_disable_non_ev = efx_port_dummy_op_void, | |
3822 | .irq_handle_msi = efx_ef10_msi_interrupt, | |
3823 | .irq_handle_legacy = efx_ef10_legacy_interrupt, | |
3824 | .tx_probe = efx_ef10_tx_probe, | |
3825 | .tx_init = efx_ef10_tx_init, | |
3826 | .tx_remove = efx_ef10_tx_remove, | |
3827 | .tx_write = efx_ef10_tx_write, | |
d43050c0 | 3828 | .rx_push_rss_config = efx_ef10_rx_push_rss_config, |
8127d661 BH |
3829 | .rx_probe = efx_ef10_rx_probe, |
3830 | .rx_init = efx_ef10_rx_init, | |
3831 | .rx_remove = efx_ef10_rx_remove, | |
3832 | .rx_write = efx_ef10_rx_write, | |
3833 | .rx_defer_refill = efx_ef10_rx_defer_refill, | |
3834 | .ev_probe = efx_ef10_ev_probe, | |
3835 | .ev_init = efx_ef10_ev_init, | |
3836 | .ev_fini = efx_ef10_ev_fini, | |
3837 | .ev_remove = efx_ef10_ev_remove, | |
3838 | .ev_process = efx_ef10_ev_process, | |
3839 | .ev_read_ack = efx_ef10_ev_read_ack, | |
3840 | .ev_test_generate = efx_ef10_ev_test_generate, | |
3841 | .filter_table_probe = efx_ef10_filter_table_probe, | |
3842 | .filter_table_restore = efx_ef10_filter_table_restore, | |
3843 | .filter_table_remove = efx_ef10_filter_table_remove, | |
3844 | .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, | |
3845 | .filter_insert = efx_ef10_filter_insert, | |
3846 | .filter_remove_safe = efx_ef10_filter_remove_safe, | |
3847 | .filter_get_safe = efx_ef10_filter_get_safe, | |
3848 | .filter_clear_rx = efx_ef10_filter_clear_rx, | |
3849 | .filter_count_rx_used = efx_ef10_filter_count_rx_used, | |
3850 | .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, | |
3851 | .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, | |
3852 | #ifdef CONFIG_RFS_ACCEL | |
3853 | .filter_rfs_insert = efx_ef10_filter_rfs_insert, | |
3854 | .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, | |
3855 | #endif | |
3856 | #ifdef CONFIG_SFC_MTD | |
3857 | .mtd_probe = efx_ef10_mtd_probe, | |
3858 | .mtd_rename = efx_mcdi_mtd_rename, | |
3859 | .mtd_read = efx_mcdi_mtd_read, | |
3860 | .mtd_erase = efx_mcdi_mtd_erase, | |
3861 | .mtd_write = efx_mcdi_mtd_write, | |
3862 | .mtd_sync = efx_mcdi_mtd_sync, | |
3863 | #endif | |
3864 | .ptp_write_host_time = efx_ef10_ptp_write_host_time, | |
bd9a265d JC |
3865 | .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, |
3866 | .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, | |
7fa8d547 | 3867 | #ifdef CONFIG_SFC_SRIOV |
834e23dd | 3868 | .sriov_configure = efx_ef10_sriov_configure, |
d98a4ffe SS |
3869 | .sriov_init = efx_ef10_sriov_init, |
3870 | .sriov_fini = efx_ef10_sriov_fini, | |
3871 | .sriov_mac_address_changed = efx_ef10_sriov_mac_address_changed, | |
3872 | .sriov_wanted = efx_ef10_sriov_wanted, | |
3873 | .sriov_reset = efx_ef10_sriov_reset, | |
7fa8d547 SS |
3874 | .sriov_flr = efx_ef10_sriov_flr, |
3875 | .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, | |
3876 | .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, | |
3877 | .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, | |
3878 | .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, | |
7b8c7b54 SS |
3879 | .vswitching_probe = efx_ef10_vswitching_probe_pf, |
3880 | .vswitching_restore = efx_ef10_vswitching_restore_pf, | |
3881 | .vswitching_remove = efx_ef10_vswitching_remove_pf, | |
7fa8d547 | 3882 | #endif |
8127d661 BH |
3883 | |
3884 | .revision = EFX_REV_HUNT_A0, | |
3885 | .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), | |
3886 | .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, | |
3887 | .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, | |
bd9a265d | 3888 | .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, |
8127d661 BH |
3889 | .can_rx_scatter = true, |
3890 | .always_rx_scatter = true, | |
3891 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
3892 | .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, | |
3893 | .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
3894 | NETIF_F_RXHASH | NETIF_F_NTUPLE), | |
3895 | .mcdi_max_ver = 2, | |
3896 | .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, | |
bd9a265d JC |
3897 | .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | |
3898 | 1 << HWTSTAMP_FILTER_ALL, | |
8127d661 | 3899 | }; |