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sfc: Fix internal indices of ethtool stats for EF10
[deliverable/linux.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
17#include <linux/in.h>
18#include <linux/jhash.h>
19#include <linux/wait.h>
20#include <linux/workqueue.h>
21
22/* Hardware control for EF10 architecture including 'Huntington'. */
23
24#define EFX_EF10_DRVGEN_EV 7
25enum {
26 EFX_EF10_TEST = 1,
27 EFX_EF10_REFILL,
28};
29
30/* The reserved RSS context value */
31#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
32
33/* The filter table(s) are managed by firmware and we have write-only
34 * access. When removing filters we must identify them to the
35 * firmware by a 64-bit handle, but this is too wide for Linux kernel
36 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
37 * be able to tell in advance whether a requested insertion will
38 * replace an existing filter. Therefore we maintain a software hash
39 * table, which should be at least as large as the hardware hash
40 * table.
41 *
42 * Huntington has a single 8K filter table shared between all filter
43 * types and both ports.
44 */
45#define HUNT_FILTER_TBL_ROWS 8192
46
47struct efx_ef10_filter_table {
48/* The RX match field masks supported by this fw & hw, in order of priority */
49 enum efx_filter_match_flags rx_match_flags[
50 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
51 unsigned int rx_match_count;
52
53 struct {
54 unsigned long spec; /* pointer to spec plus flag bits */
55/* BUSY flag indicates that an update is in progress. STACK_OLD is
56 * used to mark and sweep stack-owned MAC filters.
57 */
58#define EFX_EF10_FILTER_FLAG_BUSY 1UL
59#define EFX_EF10_FILTER_FLAG_STACK_OLD 2UL
60#define EFX_EF10_FILTER_FLAGS 3UL
61 u64 handle; /* firmware handle */
62 } *entry;
63 wait_queue_head_t waitq;
64/* Shadow of net_device address lists, guarded by mac_lock */
65#define EFX_EF10_FILTER_STACK_UC_MAX 32
66#define EFX_EF10_FILTER_STACK_MC_MAX 256
67 struct {
68 u8 addr[ETH_ALEN];
69 u16 id;
70 } stack_uc_list[EFX_EF10_FILTER_STACK_UC_MAX],
71 stack_mc_list[EFX_EF10_FILTER_STACK_MC_MAX];
72 int stack_uc_count; /* negative for PROMISC */
73 int stack_mc_count; /* negative for PROMISC/ALLMULTI */
74};
75
76/* An arbitrary search limit for the software hash table */
77#define EFX_EF10_FILTER_SEARCH_LIMIT 200
78
79static void efx_ef10_rx_push_indir_table(struct efx_nic *efx);
80static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
81static void efx_ef10_filter_table_remove(struct efx_nic *efx);
82
83static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
84{
85 efx_dword_t reg;
86
87 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
88 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
89 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
90}
91
92static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
93{
94 return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
95}
96
e5a2538a 97static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661
BH		 98{
99 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
100 struct efx_ef10_nic_data *nic_data = efx->nic_data;
101 size_t outlen;
102 int rc;
103
104 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
105
106 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
107 outbuf, sizeof(outbuf), &outlen);
108 if (rc)
109 return rc;
e5a2538a
BH		 110 if (outlen < sizeof(outbuf)) {
111 netif_err(efx, drv, efx->net_dev,
112 "unable to read datapath firmware capabilities\n");
113 return -EIO;
114 }
115
116 nic_data->datapath_caps =
117 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 118
e5a2538a
BH		 119 if (!(nic_data->datapath_caps &
120 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
121 netif_err(efx, drv, efx->net_dev,
122 "current firmware does not support TSO\n");
123 return -ENODEV;
124 }
125
126 if (!(nic_data->datapath_caps &
127 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
128 netif_err(efx, probe, efx->net_dev,
129 "current firmware does not support an RX prefix\n");
130 return -ENODEV;
8127d661
BH		 131 }
132
133 return 0;
134}
135
136static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
137{
138 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
139 int rc;
140
141 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
142 outbuf, sizeof(outbuf), NULL);
143 if (rc)
144 return rc;
145 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
146 return rc > 0 ? rc : -ERANGE;
147}
148
149static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
150{
151 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
152 size_t outlen;
153 int rc;
154
155 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
156
157 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
158 outbuf, sizeof(outbuf), &outlen);
159 if (rc)
160 return rc;
161 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
162 return -EIO;
163
164 memcpy(mac_address,
165 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE), ETH_ALEN);
166 return 0;
167}
168
169static int efx_ef10_probe(struct efx_nic *efx)
170{
171 struct efx_ef10_nic_data *nic_data;
172 int i, rc;
173
174 /* We can have one VI for each 8K region. However we need
175 * multiple TX queues per channel.
176 */
177 efx->max_channels =
178 min_t(unsigned int,
179 EFX_MAX_CHANNELS,
180 resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
181 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
182 BUG_ON(efx->max_channels == 0);
183
184 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
185 if (!nic_data)
186 return -ENOMEM;
187 efx->nic_data = nic_data;
188
189 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
190 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
191 if (rc)
192 goto fail1;
193
194 /* Get the MC's warm boot count. In case it's rebooting right
195 * now, be prepared to retry.
196 */
197 i = 0;
198 for (;;) {
199 rc = efx_ef10_get_warm_boot_count(efx);
200 if (rc >= 0)
201 break;
202 if (++i == 5)
203 goto fail2;
204 ssleep(1);
205 }
206 nic_data->warm_boot_count = rc;
207
208 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
209
210 /* In case we're recovering from a crash (kexec), we want to
211 * cancel any outstanding request by the previous user of this
212 * function. We send a special message using the least
213 * significant bits of the 'high' (doorbell) register.
214 */
215 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
216
217 rc = efx_mcdi_init(efx);
218 if (rc)
219 goto fail2;
220
221 /* Reset (most) configuration for this function */
222 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
223 if (rc)
224 goto fail3;
225
226 /* Enable event logging */
227 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
228 if (rc)
229 goto fail3;
230
e5a2538a 231 rc = efx_ef10_init_datapath_caps(efx);
8127d661
BH		 232 if (rc < 0)
233 goto fail3;
234
235 efx->rx_packet_len_offset =
236 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
237
8127d661
BH		 238 rc = efx_mcdi_port_get_number(efx);
239 if (rc < 0)
240 goto fail3;
241 efx->port_num = rc;
242
243 rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
244 if (rc)
245 goto fail3;
246
247 rc = efx_ef10_get_sysclk_freq(efx);
248 if (rc < 0)
249 goto fail3;
250 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
251
252 /* Check whether firmware supports bug 35388 workaround */
253 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
254 if (rc == 0)
255 nic_data->workaround_35388 = true;
256 else if (rc != -ENOSYS && rc != -ENOENT)
257 goto fail3;
258 netif_dbg(efx, probe, efx->net_dev,
259 "workaround for bug 35388 is %sabled\n",
260 nic_data->workaround_35388 ? "en" : "dis");
261
262 rc = efx_mcdi_mon_probe(efx);
263 if (rc)
264 goto fail3;
265
8127d661
BH		 266 return 0;
267
268fail3:
269 efx_mcdi_fini(efx);
270fail2:
271 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
272fail1:
273 kfree(nic_data);
274 efx->nic_data = NULL;
275 return rc;
276}
277
278static int efx_ef10_free_vis(struct efx_nic *efx)
279{
280 int rc = efx_mcdi_rpc(efx, MC_CMD_FREE_VIS, NULL, 0, NULL, 0, NULL);
281
282 /* -EALREADY means nothing to free, so ignore */
283 if (rc == -EALREADY)
284 rc = 0;
285 return rc;
286}
287
288static void efx_ef10_remove(struct efx_nic *efx)
289{
290 struct efx_ef10_nic_data *nic_data = efx->nic_data;
291 int rc;
292
293 efx_mcdi_mon_remove(efx);
294
295 /* This needs to be after efx_ptp_remove_channel() with no filters */
296 efx_ef10_rx_free_indir_table(efx);
297
298 rc = efx_ef10_free_vis(efx);
299 WARN_ON(rc != 0);
300
301 efx_mcdi_fini(efx);
302 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
303 kfree(nic_data);
304}
305
306static int efx_ef10_alloc_vis(struct efx_nic *efx,
307 unsigned int min_vis, unsigned int max_vis)
308{
309 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
310 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
311 struct efx_ef10_nic_data *nic_data = efx->nic_data;
312 size_t outlen;
313 int rc;
314
315 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
316 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
317 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
318 outbuf, sizeof(outbuf), &outlen);
319 if (rc != 0)
320 return rc;
321
322 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
323 return -EIO;
324
325 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
326 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
327
328 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
329 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
330 return 0;
331}
332
333static int efx_ef10_dimension_resources(struct efx_nic *efx)
334{
335 unsigned int n_vis =
336 max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
337
338 return efx_ef10_alloc_vis(efx, n_vis, n_vis);
339}
340
341static int efx_ef10_init_nic(struct efx_nic *efx)
342{
343 struct efx_ef10_nic_data *nic_data = efx->nic_data;
344 int rc;
345
a915ccc9
BH		 346 if (nic_data->must_check_datapath_caps) {
347 rc = efx_ef10_init_datapath_caps(efx);
348 if (rc)
349 return rc;
350 nic_data->must_check_datapath_caps = false;
351 }
352
8127d661
BH		 353 if (nic_data->must_realloc_vis) {
354 /* We cannot let the number of VIs change now */
355 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
356 nic_data->n_allocated_vis);
357 if (rc)
358 return rc;
359 nic_data->must_realloc_vis = false;
360 }
361
362 efx_ef10_rx_push_indir_table(efx);
363 return 0;
364}
365
366static int efx_ef10_map_reset_flags(u32 *flags)
367{
368 enum {
369 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
370 ETH_RESET_SHARED_SHIFT),
371 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
372 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
373 ETH_RESET_PHY | ETH_RESET_MGMT) <<
374 ETH_RESET_SHARED_SHIFT)
375 };
376
377 /* We assume for now that our PCI function is permitted to
378 * reset everything.
379 */
380
381 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
382 *flags &= ~EF10_RESET_MC;
383 return RESET_TYPE_WORLD;
384 }
385
386 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
387 *flags &= ~EF10_RESET_PORT;
388 return RESET_TYPE_ALL;
389 }
390
391 /* no invisible reset implemented */
392
393 return -EINVAL;
394}
395
396#define EF10_DMA_STAT(ext_name, mcdi_name) \
397 [EF10_STAT_ ## ext_name] = \
398 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
399#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
400 [EF10_STAT_ ## int_name] = \
401 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
402#define EF10_OTHER_STAT(ext_name) \
403 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
404
405static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
406 EF10_DMA_STAT(tx_bytes, TX_BYTES),
407 EF10_DMA_STAT(tx_packets, TX_PKTS),
408 EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
409 EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
410 EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
411 EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
412 EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
413 EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
414 EF10_DMA_STAT(tx_64, TX_64_PKTS),
415 EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
416 EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
417 EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
418 EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
419 EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
420 EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
421 EF10_DMA_STAT(rx_bytes, RX_BYTES),
422 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
423 EF10_OTHER_STAT(rx_good_bytes),
424 EF10_OTHER_STAT(rx_bad_bytes),
425 EF10_DMA_STAT(rx_packets, RX_PKTS),
426 EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
427 EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
428 EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
429 EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
430 EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
431 EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
432 EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
433 EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
434 EF10_DMA_STAT(rx_64, RX_64_PKTS),
435 EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
436 EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
437 EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
438 EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
439 EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
440 EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
441 EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
442 EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
443 EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
444 EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
445 EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
446 EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
447};
448
449#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \
450 (1ULL << EF10_STAT_tx_packets) | \
451 (1ULL << EF10_STAT_tx_pause) | \
452 (1ULL << EF10_STAT_tx_unicast) | \
453 (1ULL << EF10_STAT_tx_multicast) | \
454 (1ULL << EF10_STAT_tx_broadcast) | \
455 (1ULL << EF10_STAT_rx_bytes) | \
456 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
457 (1ULL << EF10_STAT_rx_good_bytes) | \
458 (1ULL << EF10_STAT_rx_bad_bytes) | \
459 (1ULL << EF10_STAT_rx_packets) | \
460 (1ULL << EF10_STAT_rx_good) | \
461 (1ULL << EF10_STAT_rx_bad) | \
462 (1ULL << EF10_STAT_rx_pause) | \
463 (1ULL << EF10_STAT_rx_control) | \
464 (1ULL << EF10_STAT_rx_unicast) | \
465 (1ULL << EF10_STAT_rx_multicast) | \
466 (1ULL << EF10_STAT_rx_broadcast) | \
467 (1ULL << EF10_STAT_rx_lt64) | \
468 (1ULL << EF10_STAT_rx_64) | \
469 (1ULL << EF10_STAT_rx_65_to_127) | \
470 (1ULL << EF10_STAT_rx_128_to_255) | \
471 (1ULL << EF10_STAT_rx_256_to_511) | \
472 (1ULL << EF10_STAT_rx_512_to_1023) | \
473 (1ULL << EF10_STAT_rx_1024_to_15xx) | \
474 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \
475 (1ULL << EF10_STAT_rx_gtjumbo) | \
476 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \
477 (1ULL << EF10_STAT_rx_overflow) | \
478 (1ULL << EF10_STAT_rx_nodesc_drops))
479
480/* These statistics are only provided by the 10G MAC. For a 10G/40G
481 * switchable port we do not expose these because they might not
482 * include all the packets they should.
483 */
484#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \
485 (1ULL << EF10_STAT_tx_lt64) | \
486 (1ULL << EF10_STAT_tx_64) | \
487 (1ULL << EF10_STAT_tx_65_to_127) | \
488 (1ULL << EF10_STAT_tx_128_to_255) | \
489 (1ULL << EF10_STAT_tx_256_to_511) | \
490 (1ULL << EF10_STAT_tx_512_to_1023) | \
491 (1ULL << EF10_STAT_tx_1024_to_15xx) | \
492 (1ULL << EF10_STAT_tx_15xx_to_jumbo))
493
494/* These statistics are only provided by the 40G MAC. For a 10G/40G
495 * switchable port we do expose these because the errors will otherwise
496 * be silent.
497 */
498#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \
499 (1ULL << EF10_STAT_rx_length_error))
500
501#if BITS_PER_LONG == 64
502#define STAT_MASK_BITMAP(bits) (bits)
503#else
504#define STAT_MASK_BITMAP(bits) (bits) & 0xffffffff, (bits) >> 32
505#endif
506
507static const unsigned long *efx_ef10_stat_mask(struct efx_nic *efx)
508{
509 static const unsigned long hunt_40g_stat_mask[] = {
510 STAT_MASK_BITMAP(HUNT_COMMON_STAT_MASK |
511 HUNT_40G_EXTRA_STAT_MASK)
512 };
513 static const unsigned long hunt_10g_only_stat_mask[] = {
514 STAT_MASK_BITMAP(HUNT_COMMON_STAT_MASK |
515 HUNT_10G_ONLY_STAT_MASK)
516 };
517 u32 port_caps = efx_mcdi_phy_get_caps(efx);
518
519 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
520 return hunt_40g_stat_mask;
521 else
522 return hunt_10g_only_stat_mask;
523}
524
525static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
526{
527 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
528 efx_ef10_stat_mask(efx), names);
529}
530
531static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
532{
533 struct efx_ef10_nic_data *nic_data = efx->nic_data;
534 const unsigned long *stats_mask = efx_ef10_stat_mask(efx);
535 __le64 generation_start, generation_end;
536 u64 *stats = nic_data->stats;
537 __le64 *dma_stats;
538
539 dma_stats = efx->stats_buffer.addr;
540 nic_data = efx->nic_data;
541
542 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
543 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
544 return 0;
545 rmb();
546 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, stats_mask,
547 stats, efx->stats_buffer.addr, false);
d546a893 548 rmb();
8127d661
BH		 549 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
550 if (generation_end != generation_start)
551 return -EAGAIN;
552
553 /* Update derived statistics */
554 stats[EF10_STAT_rx_good_bytes] =
555 stats[EF10_STAT_rx_bytes] -
556 stats[EF10_STAT_rx_bytes_minus_good_bytes];
557 efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
558 stats[EF10_STAT_rx_bytes_minus_good_bytes]);
559
560 return 0;
561}
562
563
564static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
565 struct rtnl_link_stats64 *core_stats)
566{
567 const unsigned long *mask = efx_ef10_stat_mask(efx);
568 struct efx_ef10_nic_data *nic_data = efx->nic_data;
569 u64 *stats = nic_data->stats;
570 size_t stats_count = 0, index;
571 int retry;
572
573 /* If we're unlucky enough to read statistics during the DMA, wait
574 * up to 10ms for it to finish (typically takes <500us)
575 */
576 for (retry = 0; retry < 100; ++retry) {
577 if (efx_ef10_try_update_nic_stats(efx) == 0)
578 break;
579 udelay(100);
580 }
581
582 if (full_stats) {
583 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
584 if (efx_ef10_stat_desc[index].name) {
585 *full_stats++ = stats[index];
586 ++stats_count;
587 }
588 }
589 }
590
591 if (core_stats) {
592 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
593 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
594 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
595 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
596 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops];
597 core_stats->multicast = stats[EF10_STAT_rx_multicast];
598 core_stats->rx_length_errors =
599 stats[EF10_STAT_rx_gtjumbo] +
600 stats[EF10_STAT_rx_length_error];
601 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
602 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
603 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
604 core_stats->rx_errors = (core_stats->rx_length_errors +
605 core_stats->rx_crc_errors +
606 core_stats->rx_frame_errors);
607 }
608
609 return stats_count;
610}
611
612static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
613{
614 struct efx_nic *efx = channel->efx;
615 unsigned int mode, value;
616 efx_dword_t timer_cmd;
617
618 if (channel->irq_moderation) {
619 mode = 3;
620 value = channel->irq_moderation - 1;
621 } else {
622 mode = 0;
623 value = 0;
624 }
625
626 if (EFX_EF10_WORKAROUND_35388(efx)) {
627 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
628 EFE_DD_EVQ_IND_TIMER_FLAGS,
629 ERF_DD_EVQ_IND_TIMER_MODE, mode,
630 ERF_DD_EVQ_IND_TIMER_VAL, value);
631 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
632 channel->channel);
633 } else {
634 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
635 ERF_DZ_TC_TIMER_VAL, value);
636 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
637 channel->channel);
638 }
639}
640
641static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
642{
643 wol->supported = 0;
644 wol->wolopts = 0;
645 memset(&wol->sopass, 0, sizeof(wol->sopass));
646}
647
648static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
649{
650 if (type != 0)
651 return -EINVAL;
652 return 0;
653}
654
655static void efx_ef10_mcdi_request(struct efx_nic *efx,
656 const efx_dword_t *hdr, size_t hdr_len,
657 const efx_dword_t *sdu, size_t sdu_len)
658{
659 struct efx_ef10_nic_data *nic_data = efx->nic_data;
660 u8 *pdu = nic_data->mcdi_buf.addr;
661
662 memcpy(pdu, hdr, hdr_len);
663 memcpy(pdu + hdr_len, sdu, sdu_len);
664 wmb();
665
666 /* The hardware provides 'low' and 'high' (doorbell) registers
667 * for passing the 64-bit address of an MCDI request to
668 * firmware. However the dwords are swapped by firmware. The
669 * least significant bits of the doorbell are then 0 for all
670 * MCDI requests due to alignment.
671 */
672 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
673 ER_DZ_MC_DB_LWRD);
674 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
675 ER_DZ_MC_DB_HWRD);
676}
677
678static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
679{
680 struct efx_ef10_nic_data *nic_data = efx->nic_data;
681 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
682
683 rmb();
684 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
685}
686
687static void
688efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
689 size_t offset, size_t outlen)
690{
691 struct efx_ef10_nic_data *nic_data = efx->nic_data;
692 const u8 *pdu = nic_data->mcdi_buf.addr;
693
694 memcpy(outbuf, pdu + offset, outlen);
695}
696
697static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
698{
699 struct efx_ef10_nic_data *nic_data = efx->nic_data;
700 int rc;
701
702 rc = efx_ef10_get_warm_boot_count(efx);
703 if (rc < 0) {
704 /* The firmware is presumably in the process of
705 * rebooting. However, we are supposed to report each
706 * reboot just once, so we must only do that once we
707 * can read and store the updated warm boot count.
708 */
709 return 0;
710 }
711
712 if (rc == nic_data->warm_boot_count)
713 return 0;
714
715 nic_data->warm_boot_count = rc;
716
717 /* All our allocations have been reset */
718 nic_data->must_realloc_vis = true;
719 nic_data->must_restore_filters = true;
720 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
721
a915ccc9
BH		 722 /* The datapath firmware might have been changed */
723 nic_data->must_check_datapath_caps = true;
724
869070c5
BH		 725 /* MAC statistics have been cleared on the NIC; clear the local
726 * statistic that we update with efx_update_diff_stat().
727 */
728 nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
729
8127d661
BH		 730 return -EIO;
731}
732
733/* Handle an MSI interrupt
734 *
735 * Handle an MSI hardware interrupt. This routine schedules event
736 * queue processing. No interrupt acknowledgement cycle is necessary.
737 * Also, we never need to check that the interrupt is for us, since
738 * MSI interrupts cannot be shared.
739 */
740static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
741{
742 struct efx_msi_context *context = dev_id;
743 struct efx_nic *efx = context->efx;
744
745 netif_vdbg(efx, intr, efx->net_dev,
746 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
747
748 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
749 /* Note test interrupts */
750 if (context->index == efx->irq_level)
751 efx->last_irq_cpu = raw_smp_processor_id();
752
753 /* Schedule processing of the channel */
754 efx_schedule_channel_irq(efx->channel[context->index]);
755 }
756
757 return IRQ_HANDLED;
758}
759
760static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
761{
762 struct efx_nic *efx = dev_id;
763 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
764 struct efx_channel *channel;
765 efx_dword_t reg;
766 u32 queues;
767
768 /* Read the ISR which also ACKs the interrupts */
769 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
770 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
771
772 if (queues == 0)
773 return IRQ_NONE;
774
775 if (likely(soft_enabled)) {
776 /* Note test interrupts */
777 if (queues & (1U << efx->irq_level))
778 efx->last_irq_cpu = raw_smp_processor_id();
779
780 efx_for_each_channel(channel, efx) {
781 if (queues & 1)
782 efx_schedule_channel_irq(channel);
783 queues >>= 1;
784 }
785 }
786
787 netif_vdbg(efx, intr, efx->net_dev,
788 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
789 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
790
791 return IRQ_HANDLED;
792}
793
794static void efx_ef10_irq_test_generate(struct efx_nic *efx)
795{
796 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
797
798 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
799
800 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
801 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
802 inbuf, sizeof(inbuf), NULL, 0, NULL);
803}
804
805static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
806{
807 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
808 (tx_queue->ptr_mask + 1) *
809 sizeof(efx_qword_t),
810 GFP_KERNEL);
811}
812
813/* This writes to the TX_DESC_WPTR and also pushes data */
814static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
815 const efx_qword_t *txd)
816{
817 unsigned int write_ptr;
818 efx_oword_t reg;
819
820 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
821 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
822 reg.qword[0] = *txd;
823 efx_writeo_page(tx_queue->efx, &reg,
824 ER_DZ_TX_DESC_UPD, tx_queue->queue);
825}
826
827static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
828{
829 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
830 EFX_BUF_SIZE));
831 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
832 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
833 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
834 struct efx_channel *channel = tx_queue->channel;
835 struct efx_nic *efx = tx_queue->efx;
836 size_t inlen, outlen;
837 dma_addr_t dma_addr;
838 efx_qword_t *txd;
839 int rc;
840 int i;
841
842 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
843 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
844 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
845 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
846 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
847 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
848 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
849 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
850 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
851
852 dma_addr = tx_queue->txd.buf.dma_addr;
853
854 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
855 tx_queue->queue, entries, (u64)dma_addr);
856
857 for (i = 0; i < entries; ++i) {
858 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
859 dma_addr += EFX_BUF_SIZE;
860 }
861
862 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
863
864 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
865 outbuf, sizeof(outbuf), &outlen);
866 if (rc)
867 goto fail;
868
869 /* A previous user of this TX queue might have set us up the
870 * bomb by writing a descriptor to the TX push collector but
871 * not the doorbell. (Each collector belongs to a port, not a
872 * queue or function, so cannot easily be reset.) We must
873 * attempt to push a no-op descriptor in its place.
874 */
875 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
876 tx_queue->insert_count = 1;
877 txd = efx_tx_desc(tx_queue, 0);
878 EFX_POPULATE_QWORD_4(*txd,
879 ESF_DZ_TX_DESC_IS_OPT, true,
880 ESF_DZ_TX_OPTION_TYPE,
881 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
882 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
883 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
884 tx_queue->write_count = 1;
885 wmb();
886 efx_ef10_push_tx_desc(tx_queue, txd);
887
888 return;
889
890fail:
891 WARN_ON(true);
892 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
893}
894
895static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
896{
897 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
898 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
899 struct efx_nic *efx = tx_queue->efx;
900 size_t outlen;
901 int rc;
902
903 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
904 tx_queue->queue);
905
906 rc = efx_mcdi_rpc(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
907 outbuf, sizeof(outbuf), &outlen);
908
909 if (rc && rc != -EALREADY)
910 goto fail;
911
912 return;
913
914fail:
915 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
916}
917
918static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
919{
920 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
921}
922
923/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
924static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
925{
926 unsigned int write_ptr;
927 efx_dword_t reg;
928
929 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
930 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
931 efx_writed_page(tx_queue->efx, &reg,
932 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
933}
934
935static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
936{
937 unsigned int old_write_count = tx_queue->write_count;
938 struct efx_tx_buffer *buffer;
939 unsigned int write_ptr;
940 efx_qword_t *txd;
941
942 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
943
944 do {
945 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
946 buffer = &tx_queue->buffer[write_ptr];
947 txd = efx_tx_desc(tx_queue, write_ptr);
948 ++tx_queue->write_count;
949
950 /* Create TX descriptor ring entry */
951 if (buffer->flags & EFX_TX_BUF_OPTION) {
952 *txd = buffer->option;
953 } else {
954 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
955 EFX_POPULATE_QWORD_3(
956 *txd,
957 ESF_DZ_TX_KER_CONT,
958 buffer->flags & EFX_TX_BUF_CONT,
959 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
960 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
961 }
962 } while (tx_queue->write_count != tx_queue->insert_count);
963
964 wmb(); /* Ensure descriptors are written before they are fetched */
965
966 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
967 txd = efx_tx_desc(tx_queue,
968 old_write_count & tx_queue->ptr_mask);
969 efx_ef10_push_tx_desc(tx_queue, txd);
970 ++tx_queue->pushes;
971 } else {
972 efx_ef10_notify_tx_desc(tx_queue);
973 }
974}
975
976static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
977{
978 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
979 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
980 size_t outlen;
981 int rc;
982
983 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
984 EVB_PORT_ID_ASSIGNED);
985 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
986 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
987 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
988 EFX_MAX_CHANNELS);
989
990 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
991 outbuf, sizeof(outbuf), &outlen);
992 if (rc != 0)
993 return rc;
994
995 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
996 return -EIO;
997
998 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
999
1000 return 0;
1001}
1002
1003static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1004{
1005 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1006 int rc;
1007
1008 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1009 context);
1010
1011 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1012 NULL, 0, NULL);
1013 WARN_ON(rc != 0);
1014}
1015
1016static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1017{
1018 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1019 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1020 int i, rc;
1021
1022 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1023 context);
1024 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1025 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1026
1027 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1028 MCDI_PTR(tablebuf,
1029 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1030 (u8) efx->rx_indir_table[i];
1031
1032 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1033 sizeof(tablebuf), NULL, 0, NULL);
1034 if (rc != 0)
1035 return rc;
1036
1037 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1038 context);
1039 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1040 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1041 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1042 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1043 efx->rx_hash_key[i];
1044
1045 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1046 sizeof(keybuf), NULL, 0, NULL);
1047}
1048
1049static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1050{
1051 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1052
1053 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1054 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1055 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1056}
1057
1058static void efx_ef10_rx_push_indir_table(struct efx_nic *efx)
1059{
1060 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1061 int rc;
1062
1063 netif_dbg(efx, drv, efx->net_dev, "pushing RX indirection table\n");
1064
1065 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1066 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1067 if (rc != 0)
1068 goto fail;
1069 }
1070
1071 rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1072 if (rc != 0)
1073 goto fail;
1074
1075 return;
1076
1077fail:
1078 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1079}
1080
1081static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1082{
1083 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1084 (rx_queue->ptr_mask + 1) *
1085 sizeof(efx_qword_t),
1086 GFP_KERNEL);
1087}
1088
1089static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1090{
1091 MCDI_DECLARE_BUF(inbuf,
1092 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1093 EFX_BUF_SIZE));
1094 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1095 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1096 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1097 struct efx_nic *efx = rx_queue->efx;
1098 size_t inlen, outlen;
1099 dma_addr_t dma_addr;
1100 int rc;
1101 int i;
1102
1103 rx_queue->scatter_n = 0;
1104 rx_queue->scatter_len = 0;
1105
1106 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1107 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1108 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1109 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1110 efx_rx_queue_index(rx_queue));
1111 MCDI_POPULATE_DWORD_1(inbuf, INIT_RXQ_IN_FLAGS,
1112 INIT_RXQ_IN_FLAG_PREFIX, 1);
1113 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1114 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1115
1116 dma_addr = rx_queue->rxd.buf.dma_addr;
1117
1118 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1119 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1120
1121 for (i = 0; i < entries; ++i) {
1122 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1123 dma_addr += EFX_BUF_SIZE;
1124 }
1125
1126 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1127
1128 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1129 outbuf, sizeof(outbuf), &outlen);
1130 if (rc)
1131 goto fail;
1132
1133 return;
1134
1135fail:
1136 WARN_ON(true);
1137 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1138}
1139
1140static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1141{
1142 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1143 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1144 struct efx_nic *efx = rx_queue->efx;
1145 size_t outlen;
1146 int rc;
1147
1148 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1149 efx_rx_queue_index(rx_queue));
1150
1151 rc = efx_mcdi_rpc(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
1152 outbuf, sizeof(outbuf), &outlen);
1153
1154 if (rc && rc != -EALREADY)
1155 goto fail;
1156
1157 return;
1158
1159fail:
1160 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1161}
1162
1163static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1164{
1165 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1166}
1167
1168/* This creates an entry in the RX descriptor queue */
1169static inline void
1170efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1171{
1172 struct efx_rx_buffer *rx_buf;
1173 efx_qword_t *rxd;
1174
1175 rxd = efx_rx_desc(rx_queue, index);
1176 rx_buf = efx_rx_buffer(rx_queue, index);
1177 EFX_POPULATE_QWORD_2(*rxd,
1178 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1179 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1180}
1181
1182static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1183{
1184 struct efx_nic *efx = rx_queue->efx;
1185 unsigned int write_count;
1186 efx_dword_t reg;
1187
1188 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1189 write_count = rx_queue->added_count & ~7;
1190 if (rx_queue->notified_count == write_count)
1191 return;
1192
1193 do
1194 efx_ef10_build_rx_desc(
1195 rx_queue,
1196 rx_queue->notified_count & rx_queue->ptr_mask);
1197 while (++rx_queue->notified_count != write_count);
1198
1199 wmb();
1200 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1201 write_count & rx_queue->ptr_mask);
1202 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1203 efx_rx_queue_index(rx_queue));
1204}
1205
1206static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1207
1208static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1209{
1210 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1211 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1212 efx_qword_t event;
1213
1214 EFX_POPULATE_QWORD_2(event,
1215 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1216 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1217
1218 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1219
1220 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1221 * already swapped the data to little-endian order.
1222 */
1223 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1224 sizeof(efx_qword_t));
1225
1226 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1227 inbuf, sizeof(inbuf), 0,
1228 efx_ef10_rx_defer_refill_complete, 0);
1229}
1230
1231static void
1232efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1233 int rc, efx_dword_t *outbuf,
1234 size_t outlen_actual)
1235{
1236 /* nothing to do */
1237}
1238
1239static int efx_ef10_ev_probe(struct efx_channel *channel)
1240{
1241 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1242 (channel->eventq_mask + 1) *
1243 sizeof(efx_qword_t),
1244 GFP_KERNEL);
1245}
1246
1247static int efx_ef10_ev_init(struct efx_channel *channel)
1248{
1249 MCDI_DECLARE_BUF(inbuf,
1250 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1251 EFX_BUF_SIZE));
1252 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1253 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1254 struct efx_nic *efx = channel->efx;
1255 struct efx_ef10_nic_data *nic_data;
1256 bool supports_rx_merge;
1257 size_t inlen, outlen;
1258 dma_addr_t dma_addr;
1259 int rc;
1260 int i;
1261
1262 nic_data = efx->nic_data;
1263 supports_rx_merge =
1264 !!(nic_data->datapath_caps &
1265 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1266
1267 /* Fill event queue with all ones (i.e. empty events) */
1268 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1269
1270 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1271 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1272 /* INIT_EVQ expects index in vector table, not absolute */
1273 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1274 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1275 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1276 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1277 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1278 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1279 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1280 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1281 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1282 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1283 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1284 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1285 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1286
1287 dma_addr = channel->eventq.buf.dma_addr;
1288 for (i = 0; i < entries; ++i) {
1289 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1290 dma_addr += EFX_BUF_SIZE;
1291 }
1292
1293 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1294
1295 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1296 outbuf, sizeof(outbuf), &outlen);
1297 if (rc)
1298 goto fail;
1299
1300 /* IRQ return is ignored */
1301
1302 return 0;
1303
1304fail:
1305 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1306 return rc;
1307}
1308
1309static void efx_ef10_ev_fini(struct efx_channel *channel)
1310{
1311 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1312 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1313 struct efx_nic *efx = channel->efx;
1314 size_t outlen;
1315 int rc;
1316
1317 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1318
1319 rc = efx_mcdi_rpc(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
1320 outbuf, sizeof(outbuf), &outlen);
1321
1322 if (rc && rc != -EALREADY)
1323 goto fail;
1324
1325 return;
1326
1327fail:
1328 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1329}
1330
1331static void efx_ef10_ev_remove(struct efx_channel *channel)
1332{
1333 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1334}
1335
1336static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1337 unsigned int rx_queue_label)
1338{
1339 struct efx_nic *efx = rx_queue->efx;
1340
1341 netif_info(efx, hw, efx->net_dev,
1342 "rx event arrived on queue %d labeled as queue %u\n",
1343 efx_rx_queue_index(rx_queue), rx_queue_label);
1344
1345 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1346}
1347
1348static void
1349efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1350 unsigned int actual, unsigned int expected)
1351{
1352 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1353 struct efx_nic *efx = rx_queue->efx;
1354
1355 netif_info(efx, hw, efx->net_dev,
1356 "dropped %d events (index=%d expected=%d)\n",
1357 dropped, actual, expected);
1358
1359 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1360}
1361
1362/* partially received RX was aborted. clean up. */
1363static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1364{
1365 unsigned int rx_desc_ptr;
1366
1367 WARN_ON(rx_queue->scatter_n == 0);
1368
1369 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1370 "scattered RX aborted (dropping %u buffers)\n",
1371 rx_queue->scatter_n);
1372
1373 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1374
1375 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1376 0, EFX_RX_PKT_DISCARD);
1377
1378 rx_queue->removed_count += rx_queue->scatter_n;
1379 rx_queue->scatter_n = 0;
1380 rx_queue->scatter_len = 0;
1381 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1382}
1383
1384static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1385 const efx_qword_t *event)
1386{
1387 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1388 unsigned int n_descs, n_packets, i;
1389 struct efx_nic *efx = channel->efx;
1390 struct efx_rx_queue *rx_queue;
1391 bool rx_cont;
1392 u16 flags = 0;
1393
1394 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1395 return 0;
1396
1397 /* Basic packet information */
1398 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1399 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1400 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1401 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1402 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1403
1404 WARN_ON(EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT));
1405
1406 rx_queue = efx_channel_get_rx_queue(channel);
1407
1408 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1409 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1410
1411 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1412 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1413
1414 if (n_descs != rx_queue->scatter_n + 1) {
1415 /* detect rx abort */
1416 if (unlikely(n_descs == rx_queue->scatter_n)) {
1417 WARN_ON(rx_bytes != 0);
1418 efx_ef10_handle_rx_abort(rx_queue);
1419 return 0;
1420 }
1421
1422 if (unlikely(rx_queue->scatter_n != 0)) {
1423 /* Scattered packet completions cannot be
1424 * merged, so something has gone wrong.
1425 */
1426 efx_ef10_handle_rx_bad_lbits(
1427 rx_queue, next_ptr_lbits,
1428 (rx_queue->removed_count +
1429 rx_queue->scatter_n + 1) &
1430 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1431 return 0;
1432 }
1433
1434 /* Merged completion for multiple non-scattered packets */
1435 rx_queue->scatter_n = 1;
1436 rx_queue->scatter_len = 0;
1437 n_packets = n_descs;
1438 ++channel->n_rx_merge_events;
1439 channel->n_rx_merge_packets += n_packets;
1440 flags |= EFX_RX_PKT_PREFIX_LEN;
1441 } else {
1442 ++rx_queue->scatter_n;
1443 rx_queue->scatter_len += rx_bytes;
1444 if (rx_cont)
1445 return 0;
1446 n_packets = 1;
1447 }
1448
1449 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1450 flags |= EFX_RX_PKT_DISCARD;
1451
1452 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1453 channel->n_rx_ip_hdr_chksum_err += n_packets;
1454 } else if (unlikely(EFX_QWORD_FIELD(*event,
1455 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1456 channel->n_rx_tcp_udp_chksum_err += n_packets;
1457 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1458 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1459 flags |= EFX_RX_PKT_CSUMMED;
1460 }
1461
1462 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1463 flags |= EFX_RX_PKT_TCP;
1464
1465 channel->irq_mod_score += 2 * n_packets;
1466
1467 /* Handle received packet(s) */
1468 for (i = 0; i < n_packets; i++) {
1469 efx_rx_packet(rx_queue,
1470 rx_queue->removed_count & rx_queue->ptr_mask,
1471 rx_queue->scatter_n, rx_queue->scatter_len,
1472 flags);
1473 rx_queue->removed_count += rx_queue->scatter_n;
1474 }
1475
1476 rx_queue->scatter_n = 0;
1477 rx_queue->scatter_len = 0;
1478
1479 return n_packets;
1480}
1481
1482static int
1483efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1484{
1485 struct efx_nic *efx = channel->efx;
1486 struct efx_tx_queue *tx_queue;
1487 unsigned int tx_ev_desc_ptr;
1488 unsigned int tx_ev_q_label;
1489 int tx_descs = 0;
1490
1491 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1492 return 0;
1493
1494 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1495 return 0;
1496
1497 /* Transmit completion */
1498 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1499 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1500 tx_queue = efx_channel_get_tx_queue(channel,
1501 tx_ev_q_label % EFX_TXQ_TYPES);
1502 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1503 tx_queue->ptr_mask);
1504 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1505
1506 return tx_descs;
1507}
1508
1509static void
1510efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1511{
1512 struct efx_nic *efx = channel->efx;
1513 int subcode;
1514
1515 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1516
1517 switch (subcode) {
1518 case ESE_DZ_DRV_TIMER_EV:
1519 case ESE_DZ_DRV_WAKE_UP_EV:
1520 break;
1521 case ESE_DZ_DRV_START_UP_EV:
1522 /* event queue init complete. ok. */
1523 break;
1524 default:
1525 netif_err(efx, hw, efx->net_dev,
1526 "channel %d unknown driver event type %d"
1527 " (data " EFX_QWORD_FMT ")\n",
1528 channel->channel, subcode,
1529 EFX_QWORD_VAL(*event));
1530
1531 }
1532}
1533
1534static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1535 efx_qword_t *event)
1536{
1537 struct efx_nic *efx = channel->efx;
1538 u32 subcode;
1539
1540 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1541
1542 switch (subcode) {
1543 case EFX_EF10_TEST:
1544 channel->event_test_cpu = raw_smp_processor_id();
1545 break;
1546 case EFX_EF10_REFILL:
1547 /* The queue must be empty, so we won't receive any rx
1548 * events, so efx_process_channel() won't refill the
1549 * queue. Refill it here
1550 */
1551 efx_fast_push_rx_descriptors(&channel->rx_queue);
1552 break;
1553 default:
1554 netif_err(efx, hw, efx->net_dev,
1555 "channel %d unknown driver event type %u"
1556 " (data " EFX_QWORD_FMT ")\n",
1557 channel->channel, (unsigned) subcode,
1558 EFX_QWORD_VAL(*event));
1559 }
1560}
1561
1562static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1563{
1564 struct efx_nic *efx = channel->efx;
1565 efx_qword_t event, *p_event;
1566 unsigned int read_ptr;
1567 int ev_code;
1568 int tx_descs = 0;
1569 int spent = 0;
1570
1571 read_ptr = channel->eventq_read_ptr;
1572
1573 for (;;) {
1574 p_event = efx_event(channel, read_ptr);
1575 event = *p_event;
1576
1577 if (!efx_event_present(&event))
1578 break;
1579
1580 EFX_SET_QWORD(*p_event);
1581
1582 ++read_ptr;
1583
1584 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
1585
1586 netif_vdbg(efx, drv, efx->net_dev,
1587 "processing event on %d " EFX_QWORD_FMT "\n",
1588 channel->channel, EFX_QWORD_VAL(event));
1589
1590 switch (ev_code) {
1591 case ESE_DZ_EV_CODE_MCDI_EV:
1592 efx_mcdi_process_event(channel, &event);
1593 break;
1594 case ESE_DZ_EV_CODE_RX_EV:
1595 spent += efx_ef10_handle_rx_event(channel, &event);
1596 if (spent >= quota) {
1597 /* XXX can we split a merged event to
1598 * avoid going over-quota?
1599 */
1600 spent = quota;
1601 goto out;
1602 }
1603 break;
1604 case ESE_DZ_EV_CODE_TX_EV:
1605 tx_descs += efx_ef10_handle_tx_event(channel, &event);
1606 if (tx_descs > efx->txq_entries) {
1607 spent = quota;
1608 goto out;
1609 } else if (++spent == quota) {
1610 goto out;
1611 }
1612 break;
1613 case ESE_DZ_EV_CODE_DRIVER_EV:
1614 efx_ef10_handle_driver_event(channel, &event);
1615 if (++spent == quota)
1616 goto out;
1617 break;
1618 case EFX_EF10_DRVGEN_EV:
1619 efx_ef10_handle_driver_generated_event(channel, &event);
1620 break;
1621 default:
1622 netif_err(efx, hw, efx->net_dev,
1623 "channel %d unknown event type %d"
1624 " (data " EFX_QWORD_FMT ")\n",
1625 channel->channel, ev_code,
1626 EFX_QWORD_VAL(event));
1627 }
1628 }
1629
1630out:
1631 channel->eventq_read_ptr = read_ptr;
1632 return spent;
1633}
1634
1635static void efx_ef10_ev_read_ack(struct efx_channel *channel)
1636{
1637 struct efx_nic *efx = channel->efx;
1638 efx_dword_t rptr;
1639
1640 if (EFX_EF10_WORKAROUND_35388(efx)) {
1641 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
1642 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
1643 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
1644 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
1645
1646 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
1647 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
1648 ERF_DD_EVQ_IND_RPTR,
1649 (channel->eventq_read_ptr &
1650 channel->eventq_mask) >>
1651 ERF_DD_EVQ_IND_RPTR_WIDTH);
1652 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
1653 channel->channel);
1654 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
1655 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
1656 ERF_DD_EVQ_IND_RPTR,
1657 channel->eventq_read_ptr &
1658 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
1659 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
1660 channel->channel);
1661 } else {
1662 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
1663 channel->eventq_read_ptr &
1664 channel->eventq_mask);
1665 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
1666 }
1667}
1668
1669static void efx_ef10_ev_test_generate(struct efx_channel *channel)
1670{
1671 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1672 struct efx_nic *efx = channel->efx;
1673 efx_qword_t event;
1674 int rc;
1675
1676 EFX_POPULATE_QWORD_2(event,
1677 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1678 ESF_DZ_EV_DATA, EFX_EF10_TEST);
1679
1680 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1681
1682 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1683 * already swapped the data to little-endian order.
1684 */
1685 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1686 sizeof(efx_qword_t));
1687
1688 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
1689 NULL, 0, NULL);
1690 if (rc != 0)
1691 goto fail;
1692
1693 return;
1694
1695fail:
1696 WARN_ON(true);
1697 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1698}
1699
1700void efx_ef10_handle_drain_event(struct efx_nic *efx)
1701{
1702 if (atomic_dec_and_test(&efx->active_queues))
1703 wake_up(&efx->flush_wq);
1704
1705 WARN_ON(atomic_read(&efx->active_queues) < 0);
1706}
1707
1708static int efx_ef10_fini_dmaq(struct efx_nic *efx)
1709{
1710 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1711 struct efx_channel *channel;
1712 struct efx_tx_queue *tx_queue;
1713 struct efx_rx_queue *rx_queue;
1714 int pending;
1715
1716 /* If the MC has just rebooted, the TX/RX queues will have already been
1717 * torn down, but efx->active_queues needs to be set to zero.
1718 */
1719 if (nic_data->must_realloc_vis) {
1720 atomic_set(&efx->active_queues, 0);
1721 return 0;
1722 }
1723
1724 /* Do not attempt to write to the NIC during EEH recovery */
1725 if (efx->state != STATE_RECOVERY) {
1726 efx_for_each_channel(channel, efx) {
1727 efx_for_each_channel_rx_queue(rx_queue, channel)
1728 efx_ef10_rx_fini(rx_queue);
1729 efx_for_each_channel_tx_queue(tx_queue, channel)
1730 efx_ef10_tx_fini(tx_queue);
1731 }
1732
1733 wait_event_timeout(efx->flush_wq,
1734 atomic_read(&efx->active_queues) == 0,
1735 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
1736 pending = atomic_read(&efx->active_queues);
1737 if (pending) {
1738 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
1739 pending);
1740 return -ETIMEDOUT;
1741 }
1742 }
1743
1744 return 0;
1745}
1746
1747static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
1748 const struct efx_filter_spec *right)
1749{
1750 if ((left->match_flags ^ right->match_flags) |
1751 ((left->flags ^ right->flags) &
1752 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
1753 return false;
1754
1755 return memcmp(&left->outer_vid, &right->outer_vid,
1756 sizeof(struct efx_filter_spec) -
1757 offsetof(struct efx_filter_spec, outer_vid)) == 0;
1758}
1759
1760static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
1761{
1762 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
1763 return jhash2((const u32 *)&spec->outer_vid,
1764 (sizeof(struct efx_filter_spec) -
1765 offsetof(struct efx_filter_spec, outer_vid)) / 4,
1766 0);
1767 /* XXX should we randomise the initval? */
1768}
1769
1770/* Decide whether a filter should be exclusive or else should allow
1771 * delivery to additional recipients. Currently we decide that
1772 * filters for specific local unicast MAC and IP addresses are
1773 * exclusive.
1774 */
1775static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
1776{
1777 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
1778 !is_multicast_ether_addr(spec->loc_mac))
1779 return true;
1780
1781 if ((spec->match_flags &
1782 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
1783 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
1784 if (spec->ether_type == htons(ETH_P_IP) &&
1785 !ipv4_is_multicast(spec->loc_host[0]))
1786 return true;
1787 if (spec->ether_type == htons(ETH_P_IPV6) &&
1788 ((const u8 *)spec->loc_host)[0] != 0xff)
1789 return true;
1790 }
1791
1792 return false;
1793}
1794
1795static struct efx_filter_spec *
1796efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
1797 unsigned int filter_idx)
1798{
1799 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
1800 ~EFX_EF10_FILTER_FLAGS);
1801}
1802
1803static unsigned int
1804efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
1805 unsigned int filter_idx)
1806{
1807 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
1808}
1809
1810static void
1811efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
1812 unsigned int filter_idx,
1813 const struct efx_filter_spec *spec,
1814 unsigned int flags)
1815{
1816 table->entry[filter_idx].spec = (unsigned long)spec | flags;
1817}
1818
1819static void efx_ef10_filter_push_prep(struct efx_nic *efx,
1820 const struct efx_filter_spec *spec,
1821 efx_dword_t *inbuf, u64 handle,
1822 bool replacing)
1823{
1824 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1825
1826 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
1827
1828 if (replacing) {
1829 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
1830 MC_CMD_FILTER_OP_IN_OP_REPLACE);
1831 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
1832 } else {
1833 u32 match_fields = 0;
1834
1835 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
1836 efx_ef10_filter_is_exclusive(spec) ?
1837 MC_CMD_FILTER_OP_IN_OP_INSERT :
1838 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
1839
1840 /* Convert match flags and values. Unlike almost
1841 * everything else in MCDI, these fields are in
1842 * network byte order.
1843 */
1844 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
1845 match_fields |=
1846 is_multicast_ether_addr(spec->loc_mac) ?
1847 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
1848 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
1849#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
1850 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
1851 match_fields |= \
1852 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
1853 mcdi_field ## _LBN; \
1854 BUILD_BUG_ON( \
1855 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
1856 sizeof(spec->gen_field)); \
1857 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
1858 &spec->gen_field, sizeof(spec->gen_field)); \
1859 }
1860 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
1861 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
1862 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
1863 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
1864 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
1865 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
1866 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
1867 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
1868 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
1869 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
1870#undef COPY_FIELD
1871 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
1872 match_fields);
1873 }
1874
1875 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1876 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
1877 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
1878 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
1879 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
1880 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
1881 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
1882 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, spec->dmaq_id);
1883 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
1884 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
1885 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
1886 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
1887 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
1888 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
1889 spec->rss_context !=
1890 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
1891 spec->rss_context : nic_data->rx_rss_context);
1892}
1893
1894static int efx_ef10_filter_push(struct efx_nic *efx,
1895 const struct efx_filter_spec *spec,
1896 u64 *handle, bool replacing)
1897{
1898 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
1899 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
1900 int rc;
1901
1902 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
1903 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
1904 outbuf, sizeof(outbuf), NULL);
1905 if (rc == 0)
1906 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
1907 return rc;
1908}
1909
1910static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
1911 enum efx_filter_match_flags match_flags)
1912{
1913 unsigned int match_pri;
1914
1915 for (match_pri = 0;
1916 match_pri < table->rx_match_count;
1917 match_pri++)
1918 if (table->rx_match_flags[match_pri] == match_flags)
1919 return match_pri;
1920
1921 return -EPROTONOSUPPORT;
1922}
1923
1924static s32 efx_ef10_filter_insert(struct efx_nic *efx,
1925 struct efx_filter_spec *spec,
1926 bool replace_equal)
1927{
1928 struct efx_ef10_filter_table *table = efx->filter_state;
1929 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
1930 struct efx_filter_spec *saved_spec;
1931 unsigned int match_pri, hash;
1932 unsigned int priv_flags;
1933 bool replacing = false;
1934 int ins_index = -1;
1935 DEFINE_WAIT(wait);
1936 bool is_mc_recip;
1937 s32 rc;
1938
1939 /* For now, only support RX filters */
1940 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
1941 EFX_FILTER_FLAG_RX)
1942 return -EINVAL;
1943
1944 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
1945 if (rc < 0)
1946 return rc;
1947 match_pri = rc;
1948
1949 hash = efx_ef10_filter_hash(spec);
1950 is_mc_recip = efx_filter_is_mc_recipient(spec);
1951 if (is_mc_recip)
1952 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
1953
1954 /* Find any existing filters with the same match tuple or
1955 * else a free slot to insert at. If any of them are busy,
1956 * we have to wait and retry.
1957 */
1958 for (;;) {
1959 unsigned int depth = 1;
1960 unsigned int i;
1961
1962 spin_lock_bh(&efx->filter_lock);
1963
1964 for (;;) {
1965 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
1966 saved_spec = efx_ef10_filter_entry_spec(table, i);
1967
1968 if (!saved_spec) {
1969 if (ins_index < 0)
1970 ins_index = i;
1971 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
1972 if (table->entry[i].spec &
1973 EFX_EF10_FILTER_FLAG_BUSY)
1974 break;
1975 if (spec->priority < saved_spec->priority &&
1976 !(saved_spec->priority ==
1977 EFX_FILTER_PRI_REQUIRED &&
1978 saved_spec->flags &
1979 EFX_FILTER_FLAG_RX_STACK)) {
1980 rc = -EPERM;
1981 goto out_unlock;
1982 }
1983 if (!is_mc_recip) {
1984 /* This is the only one */
1985 if (spec->priority ==
1986 saved_spec->priority &&
1987 !replace_equal) {
1988 rc = -EEXIST;
1989 goto out_unlock;
1990 }
1991 ins_index = i;
1992 goto found;
1993 } else if (spec->priority >
1994 saved_spec->priority ||
1995 (spec->priority ==
1996 saved_spec->priority &&
1997 replace_equal)) {
1998 if (ins_index < 0)
1999 ins_index = i;
2000 else
2001 __set_bit(depth, mc_rem_map);
2002 }
2003 }
2004
2005 /* Once we reach the maximum search depth, use
2006 * the first suitable slot or return -EBUSY if
2007 * there was none
2008 */
2009 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2010 if (ins_index < 0) {
2011 rc = -EBUSY;
2012 goto out_unlock;
2013 }
2014 goto found;
2015 }
2016
2017 ++depth;
2018 }
2019
2020 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2021 spin_unlock_bh(&efx->filter_lock);
2022 schedule();
2023 }
2024
2025found:
2026 /* Create a software table entry if necessary, and mark it
2027 * busy. We might yet fail to insert, but any attempt to
2028 * insert a conflicting filter while we're waiting for the
2029 * firmware must find the busy entry.
2030 */
2031 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2032 if (saved_spec) {
2033 if (spec->flags & EFX_FILTER_FLAG_RX_STACK) {
2034 /* Just make sure it won't be removed */
2035 saved_spec->flags |= EFX_FILTER_FLAG_RX_STACK;
2036 table->entry[ins_index].spec &=
2037 ~EFX_EF10_FILTER_FLAG_STACK_OLD;
2038 rc = ins_index;
2039 goto out_unlock;
2040 }
2041 replacing = true;
2042 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2043 } else {
2044 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2045 if (!saved_spec) {
2046 rc = -ENOMEM;
2047 goto out_unlock;
2048 }
2049 *saved_spec = *spec;
2050 priv_flags = 0;
2051 }
2052 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2053 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2054
2055 /* Mark lower-priority multicast recipients busy prior to removal */
2056 if (is_mc_recip) {
2057 unsigned int depth, i;
2058
2059 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2060 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2061 if (test_bit(depth, mc_rem_map))
2062 table->entry[i].spec |=
2063 EFX_EF10_FILTER_FLAG_BUSY;
2064 }
2065 }
2066
2067 spin_unlock_bh(&efx->filter_lock);
2068
2069 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2070 replacing);
2071
2072 /* Finalise the software table entry */
2073 spin_lock_bh(&efx->filter_lock);
2074 if (rc == 0) {
2075 if (replacing) {
2076 /* Update the fields that may differ */
2077 saved_spec->priority = spec->priority;
2078 saved_spec->flags &= EFX_FILTER_FLAG_RX_STACK;
2079 saved_spec->flags |= spec->flags;
2080 saved_spec->rss_context = spec->rss_context;
2081 saved_spec->dmaq_id = spec->dmaq_id;
2082 }
2083 } else if (!replacing) {
2084 kfree(saved_spec);
2085 saved_spec = NULL;
2086 }
2087 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2088
2089 /* Remove and finalise entries for lower-priority multicast
2090 * recipients
2091 */
2092 if (is_mc_recip) {
2093 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2094 unsigned int depth, i;
2095
2096 memset(inbuf, 0, sizeof(inbuf));
2097
2098 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2099 if (!test_bit(depth, mc_rem_map))
2100 continue;
2101
2102 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2103 saved_spec = efx_ef10_filter_entry_spec(table, i);
2104 priv_flags = efx_ef10_filter_entry_flags(table, i);
2105
2106 if (rc == 0) {
2107 spin_unlock_bh(&efx->filter_lock);
2108 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2109 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2110 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2111 table->entry[i].handle);
2112 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2113 inbuf, sizeof(inbuf),
2114 NULL, 0, NULL);
2115 spin_lock_bh(&efx->filter_lock);
2116 }
2117
2118 if (rc == 0) {
2119 kfree(saved_spec);
2120 saved_spec = NULL;
2121 priv_flags = 0;
2122 } else {
2123 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2124 }
2125 efx_ef10_filter_set_entry(table, i, saved_spec,
2126 priv_flags);
2127 }
2128 }
2129
2130 /* If successful, return the inserted filter ID */
2131 if (rc == 0)
2132 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2133
2134 wake_up_all(&table->waitq);
2135out_unlock:
2136 spin_unlock_bh(&efx->filter_lock);
2137 finish_wait(&table->waitq, &wait);
2138 return rc;
2139}
2140
2141void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
2142{
2143 /* no need to do anything here on EF10 */
2144}
2145
2146/* Remove a filter.
2147 * If !stack_requested, remove by ID
2148 * If stack_requested, remove by index
2149 * Filter ID may come from userland and must be range-checked.
2150 */
2151static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2152 enum efx_filter_priority priority,
2153 u32 filter_id, bool stack_requested)
2154{
2155 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2156 struct efx_ef10_filter_table *table = efx->filter_state;
2157 MCDI_DECLARE_BUF(inbuf,
2158 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2159 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2160 struct efx_filter_spec *spec;
2161 DEFINE_WAIT(wait);
2162 int rc;
2163
2164 /* Find the software table entry and mark it busy. Don't
2165 * remove it yet; any attempt to update while we're waiting
2166 * for the firmware must find the busy entry.
2167 */
2168 for (;;) {
2169 spin_lock_bh(&efx->filter_lock);
2170 if (!(table->entry[filter_idx].spec &
2171 EFX_EF10_FILTER_FLAG_BUSY))
2172 break;
2173 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2174 spin_unlock_bh(&efx->filter_lock);
2175 schedule();
2176 }
2177 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2178 if (!spec || spec->priority > priority ||
2179 (!stack_requested &&
2180 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2181 filter_id / HUNT_FILTER_TBL_ROWS)) {
2182 rc = -ENOENT;
2183 goto out_unlock;
2184 }
2185 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2186 spin_unlock_bh(&efx->filter_lock);
2187
2188 if (spec->flags & EFX_FILTER_FLAG_RX_STACK && !stack_requested) {
2189 /* Reset steering of a stack-owned filter */
2190
2191 struct efx_filter_spec new_spec = *spec;
2192
2193 new_spec.priority = EFX_FILTER_PRI_REQUIRED;
2194 new_spec.flags = (EFX_FILTER_FLAG_RX |
2195 EFX_FILTER_FLAG_RX_RSS |
2196 EFX_FILTER_FLAG_RX_STACK);
2197 new_spec.dmaq_id = 0;
2198 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2199 rc = efx_ef10_filter_push(efx, &new_spec,
2200 &table->entry[filter_idx].handle,
2201 true);
2202
2203 spin_lock_bh(&efx->filter_lock);
2204 if (rc == 0)
2205 *spec = new_spec;
2206 } else {
2207 /* Really remove the filter */
2208
2209 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2210 efx_ef10_filter_is_exclusive(spec) ?
2211 MC_CMD_FILTER_OP_IN_OP_REMOVE :
2212 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2213 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2214 table->entry[filter_idx].handle);
2215 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2216 inbuf, sizeof(inbuf), NULL, 0, NULL);
2217
2218 spin_lock_bh(&efx->filter_lock);
2219 if (rc == 0) {
2220 kfree(spec);
2221 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2222 }
2223 }
2224 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2225 wake_up_all(&table->waitq);
2226out_unlock:
2227 spin_unlock_bh(&efx->filter_lock);
2228 finish_wait(&table->waitq, &wait);
2229 return rc;
2230}
2231
2232static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2233 enum efx_filter_priority priority,
2234 u32 filter_id)
2235{
2236 return efx_ef10_filter_remove_internal(efx, priority, filter_id, false);
2237}
2238
2239static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2240 enum efx_filter_priority priority,
2241 u32 filter_id, struct efx_filter_spec *spec)
2242{
2243 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2244 struct efx_ef10_filter_table *table = efx->filter_state;
2245 const struct efx_filter_spec *saved_spec;
2246 int rc;
2247
2248 spin_lock_bh(&efx->filter_lock);
2249 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2250 if (saved_spec && saved_spec->priority == priority &&
2251 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2252 filter_id / HUNT_FILTER_TBL_ROWS) {
2253 *spec = *saved_spec;
2254 rc = 0;
2255 } else {
2256 rc = -ENOENT;
2257 }
2258 spin_unlock_bh(&efx->filter_lock);
2259 return rc;
2260}
2261
2262static void efx_ef10_filter_clear_rx(struct efx_nic *efx,
2263 enum efx_filter_priority priority)
2264{
2265 /* TODO */
2266}
2267
2268static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2269 enum efx_filter_priority priority)
2270{
2271 struct efx_ef10_filter_table *table = efx->filter_state;
2272 unsigned int filter_idx;
2273 s32 count = 0;
2274
2275 spin_lock_bh(&efx->filter_lock);
2276 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2277 if (table->entry[filter_idx].spec &&
2278 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2279 priority)
2280 ++count;
2281 }
2282 spin_unlock_bh(&efx->filter_lock);
2283 return count;
2284}
2285
2286static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2287{
2288 struct efx_ef10_filter_table *table = efx->filter_state;
2289
2290 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2291}
2292
2293static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2294 enum efx_filter_priority priority,
2295 u32 *buf, u32 size)
2296{
2297 struct efx_ef10_filter_table *table = efx->filter_state;
2298 struct efx_filter_spec *spec;
2299 unsigned int filter_idx;
2300 s32 count = 0;
2301
2302 spin_lock_bh(&efx->filter_lock);
2303 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2304 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2305 if (spec && spec->priority == priority) {
2306 if (count == size) {
2307 count = -EMSGSIZE;
2308 break;
2309 }
2310 buf[count++] = (efx_ef10_filter_rx_match_pri(
2311 table, spec->match_flags) *
2312 HUNT_FILTER_TBL_ROWS +
2313 filter_idx);
2314 }
2315 }
2316 spin_unlock_bh(&efx->filter_lock);
2317 return count;
2318}
2319
2320#ifdef CONFIG_RFS_ACCEL
2321
2322static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2323
2324static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2325 struct efx_filter_spec *spec)
2326{
2327 struct efx_ef10_filter_table *table = efx->filter_state;
2328 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2329 struct efx_filter_spec *saved_spec;
2330 unsigned int hash, i, depth = 1;
2331 bool replacing = false;
2332 int ins_index = -1;
2333 u64 cookie;
2334 s32 rc;
2335
2336 /* Must be an RX filter without RSS and not for a multicast
2337 * destination address (RFS only works for connected sockets).
2338 * These restrictions allow us to pass only a tiny amount of
2339 * data through to the completion function.
2340 */
2341 EFX_WARN_ON_PARANOID(spec->flags !=
2342 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2343 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2344 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2345
2346 hash = efx_ef10_filter_hash(spec);
2347
2348 spin_lock_bh(&efx->filter_lock);
2349
2350 /* Find any existing filter with the same match tuple or else
2351 * a free slot to insert at. If an existing filter is busy,
2352 * we have to give up.
2353 */
2354 for (;;) {
2355 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2356 saved_spec = efx_ef10_filter_entry_spec(table, i);
2357
2358 if (!saved_spec) {
2359 if (ins_index < 0)
2360 ins_index = i;
2361 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2362 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2363 rc = -EBUSY;
2364 goto fail_unlock;
2365 }
2366 EFX_WARN_ON_PARANOID(saved_spec->flags &
2367 EFX_FILTER_FLAG_RX_STACK);
2368 if (spec->priority < saved_spec->priority) {
2369 rc = -EPERM;
2370 goto fail_unlock;
2371 }
2372 ins_index = i;
2373 break;
2374 }
2375
2376 /* Once we reach the maximum search depth, use the
2377 * first suitable slot or return -EBUSY if there was
2378 * none
2379 */
2380 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2381 if (ins_index < 0) {
2382 rc = -EBUSY;
2383 goto fail_unlock;
2384 }
2385 break;
2386 }
2387
2388 ++depth;
2389 }
2390
2391 /* Create a software table entry if necessary, and mark it
2392 * busy. We might yet fail to insert, but any attempt to
2393 * insert a conflicting filter while we're waiting for the
2394 * firmware must find the busy entry.
2395 */
2396 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2397 if (saved_spec) {
2398 replacing = true;
2399 } else {
2400 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2401 if (!saved_spec) {
2402 rc = -ENOMEM;
2403 goto fail_unlock;
2404 }
2405 *saved_spec = *spec;
2406 }
2407 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2408 EFX_EF10_FILTER_FLAG_BUSY);
2409
2410 spin_unlock_bh(&efx->filter_lock);
2411
2412 /* Pack up the variables needed on completion */
2413 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2414
2415 efx_ef10_filter_push_prep(efx, spec, inbuf,
2416 table->entry[ins_index].handle, replacing);
2417 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2418 MC_CMD_FILTER_OP_OUT_LEN,
2419 efx_ef10_filter_rfs_insert_complete, cookie);
2420
2421 return ins_index;
2422
2423fail_unlock:
2424 spin_unlock_bh(&efx->filter_lock);
2425 return rc;
2426}
2427
2428static void
2429efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2430 int rc, efx_dword_t *outbuf,
2431 size_t outlen_actual)
2432{
2433 struct efx_ef10_filter_table *table = efx->filter_state;
2434 unsigned int ins_index, dmaq_id;
2435 struct efx_filter_spec *spec;
2436 bool replacing;
2437
2438 /* Unpack the cookie */
2439 replacing = cookie >> 31;
2440 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2441 dmaq_id = cookie & 0xffff;
2442
2443 spin_lock_bh(&efx->filter_lock);
2444 spec = efx_ef10_filter_entry_spec(table, ins_index);
2445 if (rc == 0) {
2446 table->entry[ins_index].handle =
2447 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2448 if (replacing)
2449 spec->dmaq_id = dmaq_id;
2450 } else if (!replacing) {
2451 kfree(spec);
2452 spec = NULL;
2453 }
2454 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2455 spin_unlock_bh(&efx->filter_lock);
2456
2457 wake_up_all(&table->waitq);
2458}
2459
2460static void
2461efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2462 unsigned long filter_idx,
2463 int rc, efx_dword_t *outbuf,
2464 size_t outlen_actual);
2465
2466static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2467 unsigned int filter_idx)
2468{
2469 struct efx_ef10_filter_table *table = efx->filter_state;
2470 struct efx_filter_spec *spec =
2471 efx_ef10_filter_entry_spec(table, filter_idx);
2472 MCDI_DECLARE_BUF(inbuf,
2473 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2474 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2475
2476 if (!spec ||
2477 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2478 spec->priority != EFX_FILTER_PRI_HINT ||
2479 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2480 flow_id, filter_idx))
2481 return false;
2482
2483 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2484 MC_CMD_FILTER_OP_IN_OP_REMOVE);
2485 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2486 table->entry[filter_idx].handle);
2487 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2488 efx_ef10_filter_rfs_expire_complete, filter_idx))
2489 return false;
2490
2491 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2492 return true;
2493}
2494
2495static void
2496efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2497 unsigned long filter_idx,
2498 int rc, efx_dword_t *outbuf,
2499 size_t outlen_actual)
2500{
2501 struct efx_ef10_filter_table *table = efx->filter_state;
2502 struct efx_filter_spec *spec =
2503 efx_ef10_filter_entry_spec(table, filter_idx);
2504
2505 spin_lock_bh(&efx->filter_lock);
2506 if (rc == 0) {
2507 kfree(spec);
2508 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2509 }
2510 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2511 wake_up_all(&table->waitq);
2512 spin_unlock_bh(&efx->filter_lock);
2513}
2514
2515#endif /* CONFIG_RFS_ACCEL */
2516
2517static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2518{
2519 int match_flags = 0;
2520
2521#define MAP_FLAG(gen_flag, mcdi_field) { \
2522 u32 old_mcdi_flags = mcdi_flags; \
2523 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2524 mcdi_field ## _LBN); \
2525 if (mcdi_flags != old_mcdi_flags) \
2526 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
2527 }
2528 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2529 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2530 MAP_FLAG(REM_HOST, SRC_IP);
2531 MAP_FLAG(LOC_HOST, DST_IP);
2532 MAP_FLAG(REM_MAC, SRC_MAC);
2533 MAP_FLAG(REM_PORT, SRC_PORT);
2534 MAP_FLAG(LOC_MAC, DST_MAC);
2535 MAP_FLAG(LOC_PORT, DST_PORT);
2536 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
2537 MAP_FLAG(INNER_VID, INNER_VLAN);
2538 MAP_FLAG(OUTER_VID, OUTER_VLAN);
2539 MAP_FLAG(IP_PROTO, IP_PROTO);
2540#undef MAP_FLAG
2541
2542 /* Did we map them all? */
2543 if (mcdi_flags)
2544 return -EINVAL;
2545
2546 return match_flags;
2547}
2548
2549static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2550{
2551 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
2552 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
2553 unsigned int pd_match_pri, pd_match_count;
2554 struct efx_ef10_filter_table *table;
2555 size_t outlen;
2556 int rc;
2557
2558 table = kzalloc(sizeof(*table), GFP_KERNEL);
2559 if (!table)
2560 return -ENOMEM;
2561
2562 /* Find out which RX filter types are supported, and their priorities */
2563 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
2564 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
2565 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
2566 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
2567 &outlen);
2568 if (rc)
2569 goto fail;
2570 pd_match_count = MCDI_VAR_ARRAY_LEN(
2571 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
2572 table->rx_match_count = 0;
2573
2574 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
2575 u32 mcdi_flags =
2576 MCDI_ARRAY_DWORD(
2577 outbuf,
2578 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
2579 pd_match_pri);
2580 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
2581 if (rc < 0) {
2582 netif_dbg(efx, probe, efx->net_dev,
2583 "%s: fw flags %#x pri %u not supported in driver\n",
2584 __func__, mcdi_flags, pd_match_pri);
2585 } else {
2586 netif_dbg(efx, probe, efx->net_dev,
2587 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
2588 __func__, mcdi_flags, pd_match_pri,
2589 rc, table->rx_match_count);
2590 table->rx_match_flags[table->rx_match_count++] = rc;
2591 }
2592 }
2593
2594 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
2595 if (!table->entry) {
2596 rc = -ENOMEM;
2597 goto fail;
2598 }
2599
2600 efx->filter_state = table;
2601 init_waitqueue_head(&table->waitq);
2602 return 0;
2603
2604fail:
2605 kfree(table);
2606 return rc;
2607}
2608
2609static void efx_ef10_filter_table_restore(struct efx_nic *efx)
2610{
2611 struct efx_ef10_filter_table *table = efx->filter_state;
2612 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2613 struct efx_filter_spec *spec;
2614 unsigned int filter_idx;
2615 bool failed = false;
2616 int rc;
2617
2618 if (!nic_data->must_restore_filters)
2619 return;
2620
2621 spin_lock_bh(&efx->filter_lock);
2622
2623 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2624 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2625 if (!spec)
2626 continue;
2627
2628 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2629 spin_unlock_bh(&efx->filter_lock);
2630
2631 rc = efx_ef10_filter_push(efx, spec,
2632 &table->entry[filter_idx].handle,
2633 false);
2634 if (rc)
2635 failed = true;
2636
2637 spin_lock_bh(&efx->filter_lock);
2638 if (rc) {
2639 kfree(spec);
2640 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2641 } else {
2642 table->entry[filter_idx].spec &=
2643 ~EFX_EF10_FILTER_FLAG_BUSY;
2644 }
2645 }
2646
2647 spin_unlock_bh(&efx->filter_lock);
2648
2649 if (failed)
2650 netif_err(efx, hw, efx->net_dev,
2651 "unable to restore all filters\n");
2652 else
2653 nic_data->must_restore_filters = false;
2654}
2655
2656static void efx_ef10_filter_table_remove(struct efx_nic *efx)
2657{
2658 struct efx_ef10_filter_table *table = efx->filter_state;
2659 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2660 struct efx_filter_spec *spec;
2661 unsigned int filter_idx;
2662 int rc;
2663
2664 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2665 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2666 if (!spec)
2667 continue;
2668
2669 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2670 efx_ef10_filter_is_exclusive(spec) ?
2671 MC_CMD_FILTER_OP_IN_OP_REMOVE :
2672 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2673 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2674 table->entry[filter_idx].handle);
2675 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2676 NULL, 0, NULL);
2677
2678 WARN_ON(rc != 0);
2679 kfree(spec);
2680 }
2681
2682 vfree(table->entry);
2683 kfree(table);
2684}
2685
2686static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
2687{
2688 struct efx_ef10_filter_table *table = efx->filter_state;
2689 struct net_device *net_dev = efx->net_dev;
2690 struct efx_filter_spec spec;
2691 bool remove_failed = false;
2692 struct netdev_hw_addr *uc;
2693 struct netdev_hw_addr *mc;
2694 unsigned int filter_idx;
2695 int i, n, rc;
2696
2697 if (!efx_dev_registered(efx))
2698 return;
2699
2700 /* Mark old filters that may need to be removed */
2701 spin_lock_bh(&efx->filter_lock);
2702 n = table->stack_uc_count < 0 ? 1 : table->stack_uc_count;
2703 for (i = 0; i < n; i++) {
2704 filter_idx = table->stack_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
2705 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_STACK_OLD;
2706 }
2707 n = table->stack_mc_count < 0 ? 1 : table->stack_mc_count;
2708 for (i = 0; i < n; i++) {
2709 filter_idx = table->stack_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
2710 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_STACK_OLD;
2711 }
2712 spin_unlock_bh(&efx->filter_lock);
2713
2714 /* Copy/convert the address lists; add the primary station
2715 * address and broadcast address
2716 */
2717 netif_addr_lock_bh(net_dev);
2718 if (net_dev->flags & IFF_PROMISC ||
2719 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_STACK_UC_MAX) {
2720 table->stack_uc_count = -1;
2721 } else {
2722 table->stack_uc_count = 1 + netdev_uc_count(net_dev);
2723 memcpy(table->stack_uc_list[0].addr, net_dev->dev_addr,
2724 ETH_ALEN);
2725 i = 1;
2726 netdev_for_each_uc_addr(uc, net_dev) {
2727 memcpy(table->stack_uc_list[i].addr,
2728 uc->addr, ETH_ALEN);
2729 i++;
2730 }
2731 }
2732 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
2733 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_STACK_MC_MAX) {
2734 table->stack_mc_count = -1;
2735 } else {
2736 table->stack_mc_count = 1 + netdev_mc_count(net_dev);
2737 eth_broadcast_addr(table->stack_mc_list[0].addr);
2738 i = 1;
2739 netdev_for_each_mc_addr(mc, net_dev) {
2740 memcpy(table->stack_mc_list[i].addr,
2741 mc->addr, ETH_ALEN);
2742 i++;
2743 }
2744 }
2745 netif_addr_unlock_bh(net_dev);
2746
2747 /* Insert/renew unicast filters */
2748 if (table->stack_uc_count >= 0) {
2749 for (i = 0; i < table->stack_uc_count; i++) {
2750 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2751 EFX_FILTER_FLAG_RX_RSS |
2752 EFX_FILTER_FLAG_RX_STACK,
2753 0);
2754 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
2755 table->stack_uc_list[i].addr);
2756 rc = efx_ef10_filter_insert(efx, &spec, true);
2757 if (rc < 0) {
2758 /* Fall back to unicast-promisc */
2759 while (i--)
2760 efx_ef10_filter_remove_safe(
2761 efx, EFX_FILTER_PRI_REQUIRED,
2762 table->stack_uc_list[i].id);
2763 table->stack_uc_count = -1;
2764 break;
2765 }
2766 table->stack_uc_list[i].id = rc;
2767 }
2768 }
2769 if (table->stack_uc_count < 0) {
2770 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2771 EFX_FILTER_FLAG_RX_RSS |
2772 EFX_FILTER_FLAG_RX_STACK,
2773 0);
2774 efx_filter_set_uc_def(&spec);
2775 rc = efx_ef10_filter_insert(efx, &spec, true);
2776 if (rc < 0) {
2777 WARN_ON(1);
2778 table->stack_uc_count = 0;
2779 } else {
2780 table->stack_uc_list[0].id = rc;
2781 }
2782 }
2783
2784 /* Insert/renew multicast filters */
2785 if (table->stack_mc_count >= 0) {
2786 for (i = 0; i < table->stack_mc_count; i++) {
2787 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2788 EFX_FILTER_FLAG_RX_RSS |
2789 EFX_FILTER_FLAG_RX_STACK,
2790 0);
2791 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
2792 table->stack_mc_list[i].addr);
2793 rc = efx_ef10_filter_insert(efx, &spec, true);
2794 if (rc < 0) {
2795 /* Fall back to multicast-promisc */
2796 while (i--)
2797 efx_ef10_filter_remove_safe(
2798 efx, EFX_FILTER_PRI_REQUIRED,
2799 table->stack_mc_list[i].id);
2800 table->stack_mc_count = -1;
2801 break;
2802 }
2803 table->stack_mc_list[i].id = rc;
2804 }
2805 }
2806 if (table->stack_mc_count < 0) {
2807 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2808 EFX_FILTER_FLAG_RX_RSS |
2809 EFX_FILTER_FLAG_RX_STACK,
2810 0);
2811 efx_filter_set_mc_def(&spec);
2812 rc = efx_ef10_filter_insert(efx, &spec, true);
2813 if (rc < 0) {
2814 WARN_ON(1);
2815 table->stack_mc_count = 0;
2816 } else {
2817 table->stack_mc_list[0].id = rc;
2818 }
2819 }
2820
2821 /* Remove filters that weren't renewed. Since nothing else
2822 * changes the STACK_OLD flag or removes these filters, we
2823 * don't need to hold the filter_lock while scanning for
2824 * these filters.
2825 */
2826 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2827 if (ACCESS_ONCE(table->entry[i].spec) &
2828 EFX_EF10_FILTER_FLAG_STACK_OLD) {
2829 if (efx_ef10_filter_remove_internal(efx,
2830 EFX_FILTER_PRI_REQUIRED,
2831 i, true) < 0)
2832 remove_failed = true;
2833 }
2834 }
2835 WARN_ON(remove_failed);
2836}
2837
2838static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
2839{
2840 efx_ef10_filter_sync_rx_mode(efx);
2841
2842 return efx_mcdi_set_mac(efx);
2843}
2844
2845#ifdef CONFIG_SFC_MTD
2846
2847struct efx_ef10_nvram_type_info {
2848 u16 type, type_mask;
2849 u8 port;
2850 const char *name;
2851};
2852
2853static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
2854 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
2855 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
2856 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
2857 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
2858 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
2859 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
2860 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
2861 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
2862 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
2863 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
2864};
2865
2866static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
2867 struct efx_mcdi_mtd_partition *part,
2868 unsigned int type)
2869{
2870 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
2871 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
2872 const struct efx_ef10_nvram_type_info *info;
2873 size_t size, erase_size, outlen;
2874 bool protected;
2875 int rc;
2876
2877 for (info = efx_ef10_nvram_types; ; info++) {
2878 if (info ==
2879 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
2880 return -ENODEV;
2881 if ((type & ~info->type_mask) == info->type)
2882 break;
2883 }
2884 if (info->port != efx_port_num(efx))
2885 return -ENODEV;
2886
2887 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
2888 if (rc)
2889 return rc;
2890 if (protected)
2891 return -ENODEV; /* hide it */
2892
2893 part->nvram_type = type;
2894
2895 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
2896 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
2897 outbuf, sizeof(outbuf), &outlen);
2898 if (rc)
2899 return rc;
2900 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
2901 return -EIO;
2902 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
2903 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
2904 part->fw_subtype = MCDI_DWORD(outbuf,
2905 NVRAM_METADATA_OUT_SUBTYPE);
2906
2907 part->common.dev_type_name = "EF10 NVRAM manager";
2908 part->common.type_name = info->name;
2909
2910 part->common.mtd.type = MTD_NORFLASH;
2911 part->common.mtd.flags = MTD_CAP_NORFLASH;
2912 part->common.mtd.size = size;
2913 part->common.mtd.erasesize = erase_size;
2914
2915 return 0;
2916}
2917
2918static int efx_ef10_mtd_probe(struct efx_nic *efx)
2919{
2920 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
2921 struct efx_mcdi_mtd_partition *parts;
2922 size_t outlen, n_parts_total, i, n_parts;
2923 unsigned int type;
2924 int rc;
2925
2926 ASSERT_RTNL();
2927
2928 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
2929 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
2930 outbuf, sizeof(outbuf), &outlen);
2931 if (rc)
2932 return rc;
2933 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
2934 return -EIO;
2935
2936 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
2937 if (n_parts_total >
2938 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
2939 return -EIO;
2940
2941 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
2942 if (!parts)
2943 return -ENOMEM;
2944
2945 n_parts = 0;
2946 for (i = 0; i < n_parts_total; i++) {
2947 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
2948 i);
2949 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
2950 if (rc == 0)
2951 n_parts++;
2952 else if (rc != -ENODEV)
2953 goto fail;
2954 }
2955
2956 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
2957fail:
2958 if (rc)
2959 kfree(parts);
2960 return rc;
2961}
2962
2963#endif /* CONFIG_SFC_MTD */
2964
2965static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
2966{
2967 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
2968}
2969
2970const struct efx_nic_type efx_hunt_a0_nic_type = {
2971 .mem_map_size = efx_ef10_mem_map_size,
2972 .probe = efx_ef10_probe,
2973 .remove = efx_ef10_remove,
2974 .dimension_resources = efx_ef10_dimension_resources,
2975 .init = efx_ef10_init_nic,
2976 .fini = efx_port_dummy_op_void,
2977 .map_reset_reason = efx_mcdi_map_reset_reason,
2978 .map_reset_flags = efx_ef10_map_reset_flags,
2979 .reset = efx_mcdi_reset,
2980 .probe_port = efx_mcdi_port_probe,
2981 .remove_port = efx_mcdi_port_remove,
2982 .fini_dmaq = efx_ef10_fini_dmaq,
2983 .describe_stats = efx_ef10_describe_stats,
2984 .update_stats = efx_ef10_update_stats,
2985 .start_stats = efx_mcdi_mac_start_stats,
2986 .stop_stats = efx_mcdi_mac_stop_stats,
2987 .set_id_led = efx_mcdi_set_id_led,
2988 .push_irq_moderation = efx_ef10_push_irq_moderation,
2989 .reconfigure_mac = efx_ef10_mac_reconfigure,
2990 .check_mac_fault = efx_mcdi_mac_check_fault,
2991 .reconfigure_port = efx_mcdi_port_reconfigure,
2992 .get_wol = efx_ef10_get_wol,
2993 .set_wol = efx_ef10_set_wol,
2994 .resume_wol = efx_port_dummy_op_void,
2995 /* TODO: test_chip */
2996 .test_nvram = efx_mcdi_nvram_test_all,
2997 .mcdi_request = efx_ef10_mcdi_request,
2998 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
2999 .mcdi_read_response = efx_ef10_mcdi_read_response,
3000 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3001 .irq_enable_master = efx_port_dummy_op_void,
3002 .irq_test_generate = efx_ef10_irq_test_generate,
3003 .irq_disable_non_ev = efx_port_dummy_op_void,
3004 .irq_handle_msi = efx_ef10_msi_interrupt,
3005 .irq_handle_legacy = efx_ef10_legacy_interrupt,
3006 .tx_probe = efx_ef10_tx_probe,
3007 .tx_init = efx_ef10_tx_init,
3008 .tx_remove = efx_ef10_tx_remove,
3009 .tx_write = efx_ef10_tx_write,
3010 .rx_push_indir_table = efx_ef10_rx_push_indir_table,
3011 .rx_probe = efx_ef10_rx_probe,
3012 .rx_init = efx_ef10_rx_init,
3013 .rx_remove = efx_ef10_rx_remove,
3014 .rx_write = efx_ef10_rx_write,
3015 .rx_defer_refill = efx_ef10_rx_defer_refill,
3016 .ev_probe = efx_ef10_ev_probe,
3017 .ev_init = efx_ef10_ev_init,
3018 .ev_fini = efx_ef10_ev_fini,
3019 .ev_remove = efx_ef10_ev_remove,
3020 .ev_process = efx_ef10_ev_process,
3021 .ev_read_ack = efx_ef10_ev_read_ack,
3022 .ev_test_generate = efx_ef10_ev_test_generate,
3023 .filter_table_probe = efx_ef10_filter_table_probe,
3024 .filter_table_restore = efx_ef10_filter_table_restore,
3025 .filter_table_remove = efx_ef10_filter_table_remove,
3026 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3027 .filter_insert = efx_ef10_filter_insert,
3028 .filter_remove_safe = efx_ef10_filter_remove_safe,
3029 .filter_get_safe = efx_ef10_filter_get_safe,
3030 .filter_clear_rx = efx_ef10_filter_clear_rx,
3031 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3032 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3033 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3034#ifdef CONFIG_RFS_ACCEL
3035 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3036 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3037#endif
3038#ifdef CONFIG_SFC_MTD
3039 .mtd_probe = efx_ef10_mtd_probe,
3040 .mtd_rename = efx_mcdi_mtd_rename,
3041 .mtd_read = efx_mcdi_mtd_read,
3042 .mtd_erase = efx_mcdi_mtd_erase,
3043 .mtd_write = efx_mcdi_mtd_write,
3044 .mtd_sync = efx_mcdi_mtd_sync,
3045#endif
3046 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
3047
3048 .revision = EFX_REV_HUNT_A0,
3049 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3050 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3051 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
3052 .can_rx_scatter = true,
3053 .always_rx_scatter = true,
3054 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3055 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3056 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3057 NETIF_F_RXHASH | NETIF_F_NTUPLE),
3058 .mcdi_max_ver = 2,
3059 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
3060};
Linux kernel - Deliverables
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