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8127d661 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare network controllers and boards | |
3 | * Copyright 2012-2013 Solarflare Communications Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include "net_driver.h" | |
11 | #include "ef10_regs.h" | |
12 | #include "io.h" | |
13 | #include "mcdi.h" | |
14 | #include "mcdi_pcol.h" | |
15 | #include "nic.h" | |
16 | #include "workarounds.h" | |
74cd60a4 | 17 | #include "selftest.h" |
8127d661 BH |
18 | #include <linux/in.h> |
19 | #include <linux/jhash.h> | |
20 | #include <linux/wait.h> | |
21 | #include <linux/workqueue.h> | |
22 | ||
23 | /* Hardware control for EF10 architecture including 'Huntington'. */ | |
24 | ||
25 | #define EFX_EF10_DRVGEN_EV 7 | |
26 | enum { | |
27 | EFX_EF10_TEST = 1, | |
28 | EFX_EF10_REFILL, | |
29 | }; | |
30 | ||
31 | /* The reserved RSS context value */ | |
32 | #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff | |
33 | ||
34 | /* The filter table(s) are managed by firmware and we have write-only | |
35 | * access. When removing filters we must identify them to the | |
36 | * firmware by a 64-bit handle, but this is too wide for Linux kernel | |
37 | * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to | |
38 | * be able to tell in advance whether a requested insertion will | |
39 | * replace an existing filter. Therefore we maintain a software hash | |
40 | * table, which should be at least as large as the hardware hash | |
41 | * table. | |
42 | * | |
43 | * Huntington has a single 8K filter table shared between all filter | |
44 | * types and both ports. | |
45 | */ | |
46 | #define HUNT_FILTER_TBL_ROWS 8192 | |
47 | ||
48 | struct efx_ef10_filter_table { | |
49 | /* The RX match field masks supported by this fw & hw, in order of priority */ | |
50 | enum efx_filter_match_flags rx_match_flags[ | |
51 | MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; | |
52 | unsigned int rx_match_count; | |
53 | ||
54 | struct { | |
55 | unsigned long spec; /* pointer to spec plus flag bits */ | |
b59e6ef8 BH |
56 | /* BUSY flag indicates that an update is in progress. AUTO_OLD is |
57 | * used to mark and sweep MAC filters for the device address lists. | |
8127d661 BH |
58 | */ |
59 | #define EFX_EF10_FILTER_FLAG_BUSY 1UL | |
b59e6ef8 | 60 | #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL |
8127d661 BH |
61 | #define EFX_EF10_FILTER_FLAGS 3UL |
62 | u64 handle; /* firmware handle */ | |
63 | } *entry; | |
64 | wait_queue_head_t waitq; | |
65 | /* Shadow of net_device address lists, guarded by mac_lock */ | |
b59e6ef8 BH |
66 | #define EFX_EF10_FILTER_DEV_UC_MAX 32 |
67 | #define EFX_EF10_FILTER_DEV_MC_MAX 256 | |
8127d661 BH |
68 | struct { |
69 | u8 addr[ETH_ALEN]; | |
70 | u16 id; | |
b59e6ef8 BH |
71 | } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX], |
72 | dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; | |
73 | int dev_uc_count; /* negative for PROMISC */ | |
74 | int dev_mc_count; /* negative for PROMISC/ALLMULTI */ | |
8127d661 BH |
75 | }; |
76 | ||
77 | /* An arbitrary search limit for the software hash table */ | |
78 | #define EFX_EF10_FILTER_SEARCH_LIMIT 200 | |
79 | ||
d43050c0 | 80 | static void efx_ef10_rx_push_rss_config(struct efx_nic *efx); |
8127d661 BH |
81 | static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); |
82 | static void efx_ef10_filter_table_remove(struct efx_nic *efx); | |
83 | ||
84 | static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) | |
85 | { | |
86 | efx_dword_t reg; | |
87 | ||
88 | efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); | |
89 | return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? | |
90 | EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; | |
91 | } | |
92 | ||
93 | static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) | |
94 | { | |
95 | return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]); | |
96 | } | |
97 | ||
e5a2538a | 98 | static int efx_ef10_init_datapath_caps(struct efx_nic *efx) |
8127d661 BH |
99 | { |
100 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN); | |
101 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
102 | size_t outlen; | |
103 | int rc; | |
104 | ||
105 | BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); | |
106 | ||
107 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, | |
108 | outbuf, sizeof(outbuf), &outlen); | |
109 | if (rc) | |
110 | return rc; | |
e5a2538a BH |
111 | if (outlen < sizeof(outbuf)) { |
112 | netif_err(efx, drv, efx->net_dev, | |
113 | "unable to read datapath firmware capabilities\n"); | |
114 | return -EIO; | |
115 | } | |
116 | ||
117 | nic_data->datapath_caps = | |
118 | MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); | |
8127d661 | 119 | |
e5a2538a BH |
120 | if (!(nic_data->datapath_caps & |
121 | (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) { | |
122 | netif_err(efx, drv, efx->net_dev, | |
123 | "current firmware does not support TSO\n"); | |
124 | return -ENODEV; | |
125 | } | |
126 | ||
127 | if (!(nic_data->datapath_caps & | |
128 | (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { | |
129 | netif_err(efx, probe, efx->net_dev, | |
130 | "current firmware does not support an RX prefix\n"); | |
131 | return -ENODEV; | |
8127d661 BH |
132 | } |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
137 | static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) | |
138 | { | |
139 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); | |
140 | int rc; | |
141 | ||
142 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, | |
143 | outbuf, sizeof(outbuf), NULL); | |
144 | if (rc) | |
145 | return rc; | |
146 | rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); | |
147 | return rc > 0 ? rc : -ERANGE; | |
148 | } | |
149 | ||
150 | static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address) | |
151 | { | |
152 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); | |
153 | size_t outlen; | |
154 | int rc; | |
155 | ||
156 | BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); | |
157 | ||
158 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, | |
159 | outbuf, sizeof(outbuf), &outlen); | |
160 | if (rc) | |
161 | return rc; | |
162 | if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) | |
163 | return -EIO; | |
164 | ||
165 | memcpy(mac_address, | |
166 | MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE), ETH_ALEN); | |
167 | return 0; | |
168 | } | |
169 | ||
170 | static int efx_ef10_probe(struct efx_nic *efx) | |
171 | { | |
172 | struct efx_ef10_nic_data *nic_data; | |
173 | int i, rc; | |
174 | ||
175 | /* We can have one VI for each 8K region. However we need | |
176 | * multiple TX queues per channel. | |
177 | */ | |
178 | efx->max_channels = | |
179 | min_t(unsigned int, | |
180 | EFX_MAX_CHANNELS, | |
181 | resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) / | |
182 | (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); | |
183 | BUG_ON(efx->max_channels == 0); | |
184 | ||
185 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
186 | if (!nic_data) | |
187 | return -ENOMEM; | |
188 | efx->nic_data = nic_data; | |
189 | ||
190 | rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, | |
191 | 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); | |
192 | if (rc) | |
193 | goto fail1; | |
194 | ||
195 | /* Get the MC's warm boot count. In case it's rebooting right | |
196 | * now, be prepared to retry. | |
197 | */ | |
198 | i = 0; | |
199 | for (;;) { | |
200 | rc = efx_ef10_get_warm_boot_count(efx); | |
201 | if (rc >= 0) | |
202 | break; | |
203 | if (++i == 5) | |
204 | goto fail2; | |
205 | ssleep(1); | |
206 | } | |
207 | nic_data->warm_boot_count = rc; | |
208 | ||
209 | nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; | |
210 | ||
211 | /* In case we're recovering from a crash (kexec), we want to | |
212 | * cancel any outstanding request by the previous user of this | |
213 | * function. We send a special message using the least | |
214 | * significant bits of the 'high' (doorbell) register. | |
215 | */ | |
216 | _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); | |
217 | ||
218 | rc = efx_mcdi_init(efx); | |
219 | if (rc) | |
220 | goto fail2; | |
221 | ||
222 | /* Reset (most) configuration for this function */ | |
223 | rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); | |
224 | if (rc) | |
225 | goto fail3; | |
226 | ||
227 | /* Enable event logging */ | |
228 | rc = efx_mcdi_log_ctrl(efx, true, false, 0); | |
229 | if (rc) | |
230 | goto fail3; | |
231 | ||
e5a2538a | 232 | rc = efx_ef10_init_datapath_caps(efx); |
8127d661 BH |
233 | if (rc < 0) |
234 | goto fail3; | |
235 | ||
236 | efx->rx_packet_len_offset = | |
237 | ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; | |
238 | ||
8127d661 BH |
239 | rc = efx_mcdi_port_get_number(efx); |
240 | if (rc < 0) | |
241 | goto fail3; | |
242 | efx->port_num = rc; | |
243 | ||
244 | rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr); | |
245 | if (rc) | |
246 | goto fail3; | |
247 | ||
248 | rc = efx_ef10_get_sysclk_freq(efx); | |
249 | if (rc < 0) | |
250 | goto fail3; | |
251 | efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */ | |
252 | ||
253 | /* Check whether firmware supports bug 35388 workaround */ | |
254 | rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true); | |
255 | if (rc == 0) | |
256 | nic_data->workaround_35388 = true; | |
257 | else if (rc != -ENOSYS && rc != -ENOENT) | |
258 | goto fail3; | |
259 | netif_dbg(efx, probe, efx->net_dev, | |
260 | "workaround for bug 35388 is %sabled\n", | |
261 | nic_data->workaround_35388 ? "en" : "dis"); | |
262 | ||
263 | rc = efx_mcdi_mon_probe(efx); | |
264 | if (rc) | |
265 | goto fail3; | |
266 | ||
9aecda95 BH |
267 | efx_ptp_probe(efx, NULL); |
268 | ||
8127d661 BH |
269 | return 0; |
270 | ||
271 | fail3: | |
272 | efx_mcdi_fini(efx); | |
273 | fail2: | |
274 | efx_nic_free_buffer(efx, &nic_data->mcdi_buf); | |
275 | fail1: | |
276 | kfree(nic_data); | |
277 | efx->nic_data = NULL; | |
278 | return rc; | |
279 | } | |
280 | ||
281 | static int efx_ef10_free_vis(struct efx_nic *efx) | |
282 | { | |
1e0b8120 EC |
283 | MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0); |
284 | size_t outlen; | |
285 | int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, | |
286 | outbuf, sizeof(outbuf), &outlen); | |
8127d661 BH |
287 | |
288 | /* -EALREADY means nothing to free, so ignore */ | |
289 | if (rc == -EALREADY) | |
290 | rc = 0; | |
1e0b8120 EC |
291 | if (rc) |
292 | efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, | |
293 | rc); | |
8127d661 BH |
294 | return rc; |
295 | } | |
296 | ||
183233be BH |
297 | #ifdef EFX_USE_PIO |
298 | ||
299 | static void efx_ef10_free_piobufs(struct efx_nic *efx) | |
300 | { | |
301 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
302 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); | |
303 | unsigned int i; | |
304 | int rc; | |
305 | ||
306 | BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); | |
307 | ||
308 | for (i = 0; i < nic_data->n_piobufs; i++) { | |
309 | MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, | |
310 | nic_data->piobuf_handle[i]); | |
311 | rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), | |
312 | NULL, 0, NULL); | |
313 | WARN_ON(rc); | |
314 | } | |
315 | ||
316 | nic_data->n_piobufs = 0; | |
317 | } | |
318 | ||
319 | static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) | |
320 | { | |
321 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
322 | MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); | |
323 | unsigned int i; | |
324 | size_t outlen; | |
325 | int rc = 0; | |
326 | ||
327 | BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); | |
328 | ||
329 | for (i = 0; i < n; i++) { | |
330 | rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, | |
331 | outbuf, sizeof(outbuf), &outlen); | |
332 | if (rc) | |
333 | break; | |
334 | if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { | |
335 | rc = -EIO; | |
336 | break; | |
337 | } | |
338 | nic_data->piobuf_handle[i] = | |
339 | MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); | |
340 | netif_dbg(efx, probe, efx->net_dev, | |
341 | "allocated PIO buffer %u handle %x\n", i, | |
342 | nic_data->piobuf_handle[i]); | |
343 | } | |
344 | ||
345 | nic_data->n_piobufs = i; | |
346 | if (rc) | |
347 | efx_ef10_free_piobufs(efx); | |
348 | return rc; | |
349 | } | |
350 | ||
351 | static int efx_ef10_link_piobufs(struct efx_nic *efx) | |
352 | { | |
353 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
354 | MCDI_DECLARE_BUF(inbuf, | |
355 | max(MC_CMD_LINK_PIOBUF_IN_LEN, | |
356 | MC_CMD_UNLINK_PIOBUF_IN_LEN)); | |
357 | struct efx_channel *channel; | |
358 | struct efx_tx_queue *tx_queue; | |
359 | unsigned int offset, index; | |
360 | int rc; | |
361 | ||
362 | BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); | |
363 | BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); | |
364 | ||
365 | /* Link a buffer to each VI in the write-combining mapping */ | |
366 | for (index = 0; index < nic_data->n_piobufs; ++index) { | |
367 | MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, | |
368 | nic_data->piobuf_handle[index]); | |
369 | MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, | |
370 | nic_data->pio_write_vi_base + index); | |
371 | rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, | |
372 | inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, | |
373 | NULL, 0, NULL); | |
374 | if (rc) { | |
375 | netif_err(efx, drv, efx->net_dev, | |
376 | "failed to link VI %u to PIO buffer %u (%d)\n", | |
377 | nic_data->pio_write_vi_base + index, index, | |
378 | rc); | |
379 | goto fail; | |
380 | } | |
381 | netif_dbg(efx, probe, efx->net_dev, | |
382 | "linked VI %u to PIO buffer %u\n", | |
383 | nic_data->pio_write_vi_base + index, index); | |
384 | } | |
385 | ||
386 | /* Link a buffer to each TX queue */ | |
387 | efx_for_each_channel(channel, efx) { | |
388 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
389 | /* We assign the PIO buffers to queues in | |
390 | * reverse order to allow for the following | |
391 | * special case. | |
392 | */ | |
393 | offset = ((efx->tx_channel_offset + efx->n_tx_channels - | |
394 | tx_queue->channel->channel - 1) * | |
395 | efx_piobuf_size); | |
396 | index = offset / ER_DZ_TX_PIOBUF_SIZE; | |
397 | offset = offset % ER_DZ_TX_PIOBUF_SIZE; | |
398 | ||
399 | /* When the host page size is 4K, the first | |
400 | * host page in the WC mapping may be within | |
401 | * the same VI page as the last TX queue. We | |
402 | * can only link one buffer to each VI. | |
403 | */ | |
404 | if (tx_queue->queue == nic_data->pio_write_vi_base) { | |
405 | BUG_ON(index != 0); | |
406 | rc = 0; | |
407 | } else { | |
408 | MCDI_SET_DWORD(inbuf, | |
409 | LINK_PIOBUF_IN_PIOBUF_HANDLE, | |
410 | nic_data->piobuf_handle[index]); | |
411 | MCDI_SET_DWORD(inbuf, | |
412 | LINK_PIOBUF_IN_TXQ_INSTANCE, | |
413 | tx_queue->queue); | |
414 | rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, | |
415 | inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, | |
416 | NULL, 0, NULL); | |
417 | } | |
418 | ||
419 | if (rc) { | |
420 | /* This is non-fatal; the TX path just | |
421 | * won't use PIO for this queue | |
422 | */ | |
423 | netif_err(efx, drv, efx->net_dev, | |
424 | "failed to link VI %u to PIO buffer %u (%d)\n", | |
425 | tx_queue->queue, index, rc); | |
426 | tx_queue->piobuf = NULL; | |
427 | } else { | |
428 | tx_queue->piobuf = | |
429 | nic_data->pio_write_base + | |
430 | index * EFX_VI_PAGE_SIZE + offset; | |
431 | tx_queue->piobuf_offset = offset; | |
432 | netif_dbg(efx, probe, efx->net_dev, | |
433 | "linked VI %u to PIO buffer %u offset %x addr %p\n", | |
434 | tx_queue->queue, index, | |
435 | tx_queue->piobuf_offset, | |
436 | tx_queue->piobuf); | |
437 | } | |
438 | } | |
439 | } | |
440 | ||
441 | return 0; | |
442 | ||
443 | fail: | |
444 | while (index--) { | |
445 | MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, | |
446 | nic_data->pio_write_vi_base + index); | |
447 | efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, | |
448 | inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, | |
449 | NULL, 0, NULL); | |
450 | } | |
451 | return rc; | |
452 | } | |
453 | ||
454 | #else /* !EFX_USE_PIO */ | |
455 | ||
456 | static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) | |
457 | { | |
458 | return n == 0 ? 0 : -ENOBUFS; | |
459 | } | |
460 | ||
461 | static int efx_ef10_link_piobufs(struct efx_nic *efx) | |
462 | { | |
463 | return 0; | |
464 | } | |
465 | ||
466 | static void efx_ef10_free_piobufs(struct efx_nic *efx) | |
467 | { | |
468 | } | |
469 | ||
470 | #endif /* EFX_USE_PIO */ | |
471 | ||
8127d661 BH |
472 | static void efx_ef10_remove(struct efx_nic *efx) |
473 | { | |
474 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
475 | int rc; | |
476 | ||
9aecda95 BH |
477 | efx_ptp_remove(efx); |
478 | ||
8127d661 BH |
479 | efx_mcdi_mon_remove(efx); |
480 | ||
8127d661 BH |
481 | efx_ef10_rx_free_indir_table(efx); |
482 | ||
183233be BH |
483 | if (nic_data->wc_membase) |
484 | iounmap(nic_data->wc_membase); | |
485 | ||
8127d661 BH |
486 | rc = efx_ef10_free_vis(efx); |
487 | WARN_ON(rc != 0); | |
488 | ||
183233be BH |
489 | if (!nic_data->must_restore_piobufs) |
490 | efx_ef10_free_piobufs(efx); | |
491 | ||
8127d661 BH |
492 | efx_mcdi_fini(efx); |
493 | efx_nic_free_buffer(efx, &nic_data->mcdi_buf); | |
494 | kfree(nic_data); | |
495 | } | |
496 | ||
497 | static int efx_ef10_alloc_vis(struct efx_nic *efx, | |
498 | unsigned int min_vis, unsigned int max_vis) | |
499 | { | |
500 | MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); | |
501 | MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); | |
502 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
503 | size_t outlen; | |
504 | int rc; | |
505 | ||
506 | MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); | |
507 | MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); | |
508 | rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), | |
509 | outbuf, sizeof(outbuf), &outlen); | |
510 | if (rc != 0) | |
511 | return rc; | |
512 | ||
513 | if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) | |
514 | return -EIO; | |
515 | ||
516 | netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", | |
517 | MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); | |
518 | ||
519 | nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); | |
520 | nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); | |
521 | return 0; | |
522 | } | |
523 | ||
183233be BH |
524 | /* Note that the failure path of this function does not free |
525 | * resources, as this will be done by efx_ef10_remove(). | |
526 | */ | |
8127d661 BH |
527 | static int efx_ef10_dimension_resources(struct efx_nic *efx) |
528 | { | |
183233be BH |
529 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
530 | unsigned int uc_mem_map_size, wc_mem_map_size; | |
531 | unsigned int min_vis, pio_write_vi_base, max_vis; | |
532 | void __iomem *membase; | |
533 | int rc; | |
534 | ||
535 | min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); | |
8127d661 | 536 | |
183233be BH |
537 | #ifdef EFX_USE_PIO |
538 | /* Try to allocate PIO buffers if wanted and if the full | |
539 | * number of PIO buffers would be sufficient to allocate one | |
540 | * copy-buffer per TX channel. Failure is non-fatal, as there | |
541 | * are only a small number of PIO buffers shared between all | |
542 | * functions of the controller. | |
543 | */ | |
544 | if (efx_piobuf_size != 0 && | |
545 | ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= | |
546 | efx->n_tx_channels) { | |
547 | unsigned int n_piobufs = | |
548 | DIV_ROUND_UP(efx->n_tx_channels, | |
549 | ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); | |
550 | ||
551 | rc = efx_ef10_alloc_piobufs(efx, n_piobufs); | |
552 | if (rc) | |
553 | netif_err(efx, probe, efx->net_dev, | |
554 | "failed to allocate PIO buffers (%d)\n", rc); | |
555 | else | |
556 | netif_dbg(efx, probe, efx->net_dev, | |
557 | "allocated %u PIO buffers\n", n_piobufs); | |
558 | } | |
559 | #else | |
560 | nic_data->n_piobufs = 0; | |
561 | #endif | |
562 | ||
563 | /* PIO buffers should be mapped with write-combining enabled, | |
564 | * and we want to make single UC and WC mappings rather than | |
565 | * several of each (in fact that's the only option if host | |
566 | * page size is >4K). So we may allocate some extra VIs just | |
567 | * for writing PIO buffers through. | |
568 | */ | |
569 | uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE + | |
570 | ER_DZ_TX_PIOBUF); | |
571 | if (nic_data->n_piobufs) { | |
572 | pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; | |
573 | wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + | |
574 | nic_data->n_piobufs) * | |
575 | EFX_VI_PAGE_SIZE) - | |
576 | uc_mem_map_size); | |
577 | max_vis = pio_write_vi_base + nic_data->n_piobufs; | |
578 | } else { | |
579 | pio_write_vi_base = 0; | |
580 | wc_mem_map_size = 0; | |
581 | max_vis = min_vis; | |
582 | } | |
583 | ||
584 | /* In case the last attached driver failed to free VIs, do it now */ | |
585 | rc = efx_ef10_free_vis(efx); | |
586 | if (rc != 0) | |
587 | return rc; | |
588 | ||
589 | rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); | |
590 | if (rc != 0) | |
591 | return rc; | |
592 | ||
593 | /* If we didn't get enough VIs to map all the PIO buffers, free the | |
594 | * PIO buffers | |
595 | */ | |
596 | if (nic_data->n_piobufs && | |
597 | nic_data->n_allocated_vis < | |
598 | pio_write_vi_base + nic_data->n_piobufs) { | |
599 | netif_dbg(efx, probe, efx->net_dev, | |
600 | "%u VIs are not sufficient to map %u PIO buffers\n", | |
601 | nic_data->n_allocated_vis, nic_data->n_piobufs); | |
602 | efx_ef10_free_piobufs(efx); | |
603 | } | |
604 | ||
605 | /* Shrink the original UC mapping of the memory BAR */ | |
606 | membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); | |
607 | if (!membase) { | |
608 | netif_err(efx, probe, efx->net_dev, | |
609 | "could not shrink memory BAR to %x\n", | |
610 | uc_mem_map_size); | |
611 | return -ENOMEM; | |
612 | } | |
613 | iounmap(efx->membase); | |
614 | efx->membase = membase; | |
615 | ||
616 | /* Set up the WC mapping if needed */ | |
617 | if (wc_mem_map_size) { | |
618 | nic_data->wc_membase = ioremap_wc(efx->membase_phys + | |
619 | uc_mem_map_size, | |
620 | wc_mem_map_size); | |
621 | if (!nic_data->wc_membase) { | |
622 | netif_err(efx, probe, efx->net_dev, | |
623 | "could not allocate WC mapping of size %x\n", | |
624 | wc_mem_map_size); | |
625 | return -ENOMEM; | |
626 | } | |
627 | nic_data->pio_write_vi_base = pio_write_vi_base; | |
628 | nic_data->pio_write_base = | |
629 | nic_data->wc_membase + | |
630 | (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - | |
631 | uc_mem_map_size); | |
632 | ||
633 | rc = efx_ef10_link_piobufs(efx); | |
634 | if (rc) | |
635 | efx_ef10_free_piobufs(efx); | |
636 | } | |
637 | ||
638 | netif_dbg(efx, probe, efx->net_dev, | |
639 | "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", | |
640 | &efx->membase_phys, efx->membase, uc_mem_map_size, | |
641 | nic_data->wc_membase, wc_mem_map_size); | |
642 | ||
643 | return 0; | |
8127d661 BH |
644 | } |
645 | ||
646 | static int efx_ef10_init_nic(struct efx_nic *efx) | |
647 | { | |
648 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
649 | int rc; | |
650 | ||
a915ccc9 BH |
651 | if (nic_data->must_check_datapath_caps) { |
652 | rc = efx_ef10_init_datapath_caps(efx); | |
653 | if (rc) | |
654 | return rc; | |
655 | nic_data->must_check_datapath_caps = false; | |
656 | } | |
657 | ||
8127d661 BH |
658 | if (nic_data->must_realloc_vis) { |
659 | /* We cannot let the number of VIs change now */ | |
660 | rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, | |
661 | nic_data->n_allocated_vis); | |
662 | if (rc) | |
663 | return rc; | |
664 | nic_data->must_realloc_vis = false; | |
665 | } | |
666 | ||
183233be BH |
667 | if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { |
668 | rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); | |
669 | if (rc == 0) { | |
670 | rc = efx_ef10_link_piobufs(efx); | |
671 | if (rc) | |
672 | efx_ef10_free_piobufs(efx); | |
673 | } | |
674 | ||
675 | /* Log an error on failure, but this is non-fatal */ | |
676 | if (rc) | |
677 | netif_err(efx, drv, efx->net_dev, | |
678 | "failed to restore PIO buffers (%d)\n", rc); | |
679 | nic_data->must_restore_piobufs = false; | |
680 | } | |
681 | ||
d43050c0 | 682 | efx_ef10_rx_push_rss_config(efx); |
8127d661 BH |
683 | return 0; |
684 | } | |
685 | ||
686 | static int efx_ef10_map_reset_flags(u32 *flags) | |
687 | { | |
688 | enum { | |
689 | EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << | |
690 | ETH_RESET_SHARED_SHIFT), | |
691 | EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | | |
692 | ETH_RESET_OFFLOAD | ETH_RESET_MAC | | |
693 | ETH_RESET_PHY | ETH_RESET_MGMT) << | |
694 | ETH_RESET_SHARED_SHIFT) | |
695 | }; | |
696 | ||
697 | /* We assume for now that our PCI function is permitted to | |
698 | * reset everything. | |
699 | */ | |
700 | ||
701 | if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { | |
702 | *flags &= ~EF10_RESET_MC; | |
703 | return RESET_TYPE_WORLD; | |
704 | } | |
705 | ||
706 | if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { | |
707 | *flags &= ~EF10_RESET_PORT; | |
708 | return RESET_TYPE_ALL; | |
709 | } | |
710 | ||
711 | /* no invisible reset implemented */ | |
712 | ||
713 | return -EINVAL; | |
714 | } | |
715 | ||
716 | #define EF10_DMA_STAT(ext_name, mcdi_name) \ | |
717 | [EF10_STAT_ ## ext_name] = \ | |
718 | { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } | |
719 | #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ | |
720 | [EF10_STAT_ ## int_name] = \ | |
721 | { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } | |
722 | #define EF10_OTHER_STAT(ext_name) \ | |
723 | [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } | |
724 | ||
725 | static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { | |
726 | EF10_DMA_STAT(tx_bytes, TX_BYTES), | |
727 | EF10_DMA_STAT(tx_packets, TX_PKTS), | |
728 | EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS), | |
729 | EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS), | |
730 | EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS), | |
731 | EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS), | |
732 | EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS), | |
733 | EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS), | |
734 | EF10_DMA_STAT(tx_64, TX_64_PKTS), | |
735 | EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS), | |
736 | EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS), | |
737 | EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS), | |
738 | EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS), | |
739 | EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), | |
740 | EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), | |
741 | EF10_DMA_STAT(rx_bytes, RX_BYTES), | |
742 | EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES), | |
743 | EF10_OTHER_STAT(rx_good_bytes), | |
744 | EF10_OTHER_STAT(rx_bad_bytes), | |
745 | EF10_DMA_STAT(rx_packets, RX_PKTS), | |
746 | EF10_DMA_STAT(rx_good, RX_GOOD_PKTS), | |
747 | EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS), | |
748 | EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS), | |
749 | EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS), | |
750 | EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS), | |
751 | EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS), | |
752 | EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS), | |
753 | EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS), | |
754 | EF10_DMA_STAT(rx_64, RX_64_PKTS), | |
755 | EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS), | |
756 | EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS), | |
757 | EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS), | |
758 | EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS), | |
759 | EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), | |
760 | EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), | |
761 | EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS), | |
762 | EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS), | |
763 | EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS), | |
764 | EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS), | |
765 | EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS), | |
766 | EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS), | |
568d7a00 EC |
767 | EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), |
768 | EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), | |
769 | EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), | |
770 | EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), | |
771 | EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB), | |
772 | EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB), | |
773 | EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING), | |
774 | EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), | |
775 | EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), | |
776 | EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS), | |
777 | EF10_DMA_STAT(rx_dp_emerg_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS), | |
778 | EF10_DMA_STAT(rx_dp_emerg_wait, RXDP_EMERGENCY_WAIT_CONDITIONS), | |
8127d661 BH |
779 | }; |
780 | ||
781 | #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \ | |
782 | (1ULL << EF10_STAT_tx_packets) | \ | |
783 | (1ULL << EF10_STAT_tx_pause) | \ | |
784 | (1ULL << EF10_STAT_tx_unicast) | \ | |
785 | (1ULL << EF10_STAT_tx_multicast) | \ | |
786 | (1ULL << EF10_STAT_tx_broadcast) | \ | |
787 | (1ULL << EF10_STAT_rx_bytes) | \ | |
788 | (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \ | |
789 | (1ULL << EF10_STAT_rx_good_bytes) | \ | |
790 | (1ULL << EF10_STAT_rx_bad_bytes) | \ | |
791 | (1ULL << EF10_STAT_rx_packets) | \ | |
792 | (1ULL << EF10_STAT_rx_good) | \ | |
793 | (1ULL << EF10_STAT_rx_bad) | \ | |
794 | (1ULL << EF10_STAT_rx_pause) | \ | |
795 | (1ULL << EF10_STAT_rx_control) | \ | |
796 | (1ULL << EF10_STAT_rx_unicast) | \ | |
797 | (1ULL << EF10_STAT_rx_multicast) | \ | |
798 | (1ULL << EF10_STAT_rx_broadcast) | \ | |
799 | (1ULL << EF10_STAT_rx_lt64) | \ | |
800 | (1ULL << EF10_STAT_rx_64) | \ | |
801 | (1ULL << EF10_STAT_rx_65_to_127) | \ | |
802 | (1ULL << EF10_STAT_rx_128_to_255) | \ | |
803 | (1ULL << EF10_STAT_rx_256_to_511) | \ | |
804 | (1ULL << EF10_STAT_rx_512_to_1023) | \ | |
805 | (1ULL << EF10_STAT_rx_1024_to_15xx) | \ | |
806 | (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \ | |
807 | (1ULL << EF10_STAT_rx_gtjumbo) | \ | |
808 | (1ULL << EF10_STAT_rx_bad_gtjumbo) | \ | |
809 | (1ULL << EF10_STAT_rx_overflow) | \ | |
810 | (1ULL << EF10_STAT_rx_nodesc_drops)) | |
811 | ||
812 | /* These statistics are only provided by the 10G MAC. For a 10G/40G | |
813 | * switchable port we do not expose these because they might not | |
814 | * include all the packets they should. | |
815 | */ | |
816 | #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \ | |
817 | (1ULL << EF10_STAT_tx_lt64) | \ | |
818 | (1ULL << EF10_STAT_tx_64) | \ | |
819 | (1ULL << EF10_STAT_tx_65_to_127) | \ | |
820 | (1ULL << EF10_STAT_tx_128_to_255) | \ | |
821 | (1ULL << EF10_STAT_tx_256_to_511) | \ | |
822 | (1ULL << EF10_STAT_tx_512_to_1023) | \ | |
823 | (1ULL << EF10_STAT_tx_1024_to_15xx) | \ | |
824 | (1ULL << EF10_STAT_tx_15xx_to_jumbo)) | |
825 | ||
826 | /* These statistics are only provided by the 40G MAC. For a 10G/40G | |
827 | * switchable port we do expose these because the errors will otherwise | |
828 | * be silent. | |
829 | */ | |
830 | #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \ | |
831 | (1ULL << EF10_STAT_rx_length_error)) | |
832 | ||
568d7a00 EC |
833 | /* These statistics are only provided if the firmware supports the |
834 | * capability PM_AND_RXDP_COUNTERS. | |
835 | */ | |
836 | #define HUNT_PM_AND_RXDP_STAT_MASK ( \ | |
837 | (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \ | |
838 | (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \ | |
839 | (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \ | |
840 | (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \ | |
841 | (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \ | |
842 | (1ULL << EF10_STAT_rx_pm_discard_qbb) | \ | |
843 | (1ULL << EF10_STAT_rx_pm_discard_mapping) | \ | |
844 | (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \ | |
845 | (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \ | |
846 | (1ULL << EF10_STAT_rx_dp_streaming_packets) | \ | |
847 | (1ULL << EF10_STAT_rx_dp_emerg_fetch) | \ | |
848 | (1ULL << EF10_STAT_rx_dp_emerg_wait)) | |
849 | ||
4bae913b | 850 | static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) |
8127d661 | 851 | { |
4bae913b | 852 | u64 raw_mask = HUNT_COMMON_STAT_MASK; |
8127d661 | 853 | u32 port_caps = efx_mcdi_phy_get_caps(efx); |
568d7a00 | 854 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
8127d661 BH |
855 | |
856 | if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) | |
4bae913b | 857 | raw_mask |= HUNT_40G_EXTRA_STAT_MASK; |
8127d661 | 858 | else |
4bae913b | 859 | raw_mask |= HUNT_10G_ONLY_STAT_MASK; |
568d7a00 EC |
860 | |
861 | if (nic_data->datapath_caps & | |
862 | (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) | |
863 | raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; | |
864 | ||
4bae913b EC |
865 | return raw_mask; |
866 | } | |
867 | ||
868 | static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) | |
869 | { | |
870 | u64 raw_mask = efx_ef10_raw_stat_mask(efx); | |
871 | ||
872 | #if BITS_PER_LONG == 64 | |
873 | mask[0] = raw_mask; | |
874 | #else | |
875 | mask[0] = raw_mask & 0xffffffff; | |
876 | mask[1] = raw_mask >> 32; | |
877 | #endif | |
8127d661 BH |
878 | } |
879 | ||
880 | static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) | |
881 | { | |
4bae913b EC |
882 | DECLARE_BITMAP(mask, EF10_STAT_COUNT); |
883 | ||
884 | efx_ef10_get_stat_mask(efx, mask); | |
8127d661 | 885 | return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, |
4bae913b | 886 | mask, names); |
8127d661 BH |
887 | } |
888 | ||
889 | static int efx_ef10_try_update_nic_stats(struct efx_nic *efx) | |
890 | { | |
891 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
4bae913b | 892 | DECLARE_BITMAP(mask, EF10_STAT_COUNT); |
8127d661 BH |
893 | __le64 generation_start, generation_end; |
894 | u64 *stats = nic_data->stats; | |
895 | __le64 *dma_stats; | |
896 | ||
4bae913b EC |
897 | efx_ef10_get_stat_mask(efx, mask); |
898 | ||
8127d661 BH |
899 | dma_stats = efx->stats_buffer.addr; |
900 | nic_data = efx->nic_data; | |
901 | ||
902 | generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; | |
903 | if (generation_end == EFX_MC_STATS_GENERATION_INVALID) | |
904 | return 0; | |
905 | rmb(); | |
4bae913b | 906 | efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, |
8127d661 | 907 | stats, efx->stats_buffer.addr, false); |
d546a893 | 908 | rmb(); |
8127d661 BH |
909 | generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; |
910 | if (generation_end != generation_start) | |
911 | return -EAGAIN; | |
912 | ||
913 | /* Update derived statistics */ | |
f8f3b5ae | 914 | efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]); |
8127d661 BH |
915 | stats[EF10_STAT_rx_good_bytes] = |
916 | stats[EF10_STAT_rx_bytes] - | |
917 | stats[EF10_STAT_rx_bytes_minus_good_bytes]; | |
918 | efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes], | |
919 | stats[EF10_STAT_rx_bytes_minus_good_bytes]); | |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
924 | ||
925 | static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats, | |
926 | struct rtnl_link_stats64 *core_stats) | |
927 | { | |
4bae913b | 928 | DECLARE_BITMAP(mask, EF10_STAT_COUNT); |
8127d661 BH |
929 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
930 | u64 *stats = nic_data->stats; | |
931 | size_t stats_count = 0, index; | |
932 | int retry; | |
933 | ||
4bae913b EC |
934 | efx_ef10_get_stat_mask(efx, mask); |
935 | ||
8127d661 BH |
936 | /* If we're unlucky enough to read statistics during the DMA, wait |
937 | * up to 10ms for it to finish (typically takes <500us) | |
938 | */ | |
939 | for (retry = 0; retry < 100; ++retry) { | |
940 | if (efx_ef10_try_update_nic_stats(efx) == 0) | |
941 | break; | |
942 | udelay(100); | |
943 | } | |
944 | ||
945 | if (full_stats) { | |
946 | for_each_set_bit(index, mask, EF10_STAT_COUNT) { | |
947 | if (efx_ef10_stat_desc[index].name) { | |
948 | *full_stats++ = stats[index]; | |
949 | ++stats_count; | |
950 | } | |
951 | } | |
952 | } | |
953 | ||
954 | if (core_stats) { | |
955 | core_stats->rx_packets = stats[EF10_STAT_rx_packets]; | |
956 | core_stats->tx_packets = stats[EF10_STAT_tx_packets]; | |
957 | core_stats->rx_bytes = stats[EF10_STAT_rx_bytes]; | |
958 | core_stats->tx_bytes = stats[EF10_STAT_tx_bytes]; | |
959 | core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops]; | |
960 | core_stats->multicast = stats[EF10_STAT_rx_multicast]; | |
961 | core_stats->rx_length_errors = | |
962 | stats[EF10_STAT_rx_gtjumbo] + | |
963 | stats[EF10_STAT_rx_length_error]; | |
964 | core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; | |
965 | core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error]; | |
966 | core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; | |
967 | core_stats->rx_errors = (core_stats->rx_length_errors + | |
968 | core_stats->rx_crc_errors + | |
969 | core_stats->rx_frame_errors); | |
970 | } | |
971 | ||
972 | return stats_count; | |
973 | } | |
974 | ||
975 | static void efx_ef10_push_irq_moderation(struct efx_channel *channel) | |
976 | { | |
977 | struct efx_nic *efx = channel->efx; | |
978 | unsigned int mode, value; | |
979 | efx_dword_t timer_cmd; | |
980 | ||
981 | if (channel->irq_moderation) { | |
982 | mode = 3; | |
983 | value = channel->irq_moderation - 1; | |
984 | } else { | |
985 | mode = 0; | |
986 | value = 0; | |
987 | } | |
988 | ||
989 | if (EFX_EF10_WORKAROUND_35388(efx)) { | |
990 | EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, | |
991 | EFE_DD_EVQ_IND_TIMER_FLAGS, | |
992 | ERF_DD_EVQ_IND_TIMER_MODE, mode, | |
993 | ERF_DD_EVQ_IND_TIMER_VAL, value); | |
994 | efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, | |
995 | channel->channel); | |
996 | } else { | |
997 | EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, | |
998 | ERF_DZ_TC_TIMER_VAL, value); | |
999 | efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, | |
1000 | channel->channel); | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) | |
1005 | { | |
1006 | wol->supported = 0; | |
1007 | wol->wolopts = 0; | |
1008 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
1009 | } | |
1010 | ||
1011 | static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) | |
1012 | { | |
1013 | if (type != 0) | |
1014 | return -EINVAL; | |
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | static void efx_ef10_mcdi_request(struct efx_nic *efx, | |
1019 | const efx_dword_t *hdr, size_t hdr_len, | |
1020 | const efx_dword_t *sdu, size_t sdu_len) | |
1021 | { | |
1022 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1023 | u8 *pdu = nic_data->mcdi_buf.addr; | |
1024 | ||
1025 | memcpy(pdu, hdr, hdr_len); | |
1026 | memcpy(pdu + hdr_len, sdu, sdu_len); | |
1027 | wmb(); | |
1028 | ||
1029 | /* The hardware provides 'low' and 'high' (doorbell) registers | |
1030 | * for passing the 64-bit address of an MCDI request to | |
1031 | * firmware. However the dwords are swapped by firmware. The | |
1032 | * least significant bits of the doorbell are then 0 for all | |
1033 | * MCDI requests due to alignment. | |
1034 | */ | |
1035 | _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), | |
1036 | ER_DZ_MC_DB_LWRD); | |
1037 | _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), | |
1038 | ER_DZ_MC_DB_HWRD); | |
1039 | } | |
1040 | ||
1041 | static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) | |
1042 | { | |
1043 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1044 | const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; | |
1045 | ||
1046 | rmb(); | |
1047 | return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); | |
1048 | } | |
1049 | ||
1050 | static void | |
1051 | efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, | |
1052 | size_t offset, size_t outlen) | |
1053 | { | |
1054 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1055 | const u8 *pdu = nic_data->mcdi_buf.addr; | |
1056 | ||
1057 | memcpy(outbuf, pdu + offset, outlen); | |
1058 | } | |
1059 | ||
1060 | static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) | |
1061 | { | |
1062 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1063 | int rc; | |
1064 | ||
1065 | rc = efx_ef10_get_warm_boot_count(efx); | |
1066 | if (rc < 0) { | |
1067 | /* The firmware is presumably in the process of | |
1068 | * rebooting. However, we are supposed to report each | |
1069 | * reboot just once, so we must only do that once we | |
1070 | * can read and store the updated warm boot count. | |
1071 | */ | |
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | if (rc == nic_data->warm_boot_count) | |
1076 | return 0; | |
1077 | ||
1078 | nic_data->warm_boot_count = rc; | |
1079 | ||
1080 | /* All our allocations have been reset */ | |
1081 | nic_data->must_realloc_vis = true; | |
1082 | nic_data->must_restore_filters = true; | |
183233be | 1083 | nic_data->must_restore_piobufs = true; |
8127d661 BH |
1084 | nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; |
1085 | ||
a915ccc9 BH |
1086 | /* The datapath firmware might have been changed */ |
1087 | nic_data->must_check_datapath_caps = true; | |
1088 | ||
869070c5 BH |
1089 | /* MAC statistics have been cleared on the NIC; clear the local |
1090 | * statistic that we update with efx_update_diff_stat(). | |
1091 | */ | |
1092 | nic_data->stats[EF10_STAT_rx_bad_bytes] = 0; | |
1093 | ||
8127d661 BH |
1094 | return -EIO; |
1095 | } | |
1096 | ||
1097 | /* Handle an MSI interrupt | |
1098 | * | |
1099 | * Handle an MSI hardware interrupt. This routine schedules event | |
1100 | * queue processing. No interrupt acknowledgement cycle is necessary. | |
1101 | * Also, we never need to check that the interrupt is for us, since | |
1102 | * MSI interrupts cannot be shared. | |
1103 | */ | |
1104 | static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) | |
1105 | { | |
1106 | struct efx_msi_context *context = dev_id; | |
1107 | struct efx_nic *efx = context->efx; | |
1108 | ||
1109 | netif_vdbg(efx, intr, efx->net_dev, | |
1110 | "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); | |
1111 | ||
1112 | if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { | |
1113 | /* Note test interrupts */ | |
1114 | if (context->index == efx->irq_level) | |
1115 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1116 | ||
1117 | /* Schedule processing of the channel */ | |
1118 | efx_schedule_channel_irq(efx->channel[context->index]); | |
1119 | } | |
1120 | ||
1121 | return IRQ_HANDLED; | |
1122 | } | |
1123 | ||
1124 | static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) | |
1125 | { | |
1126 | struct efx_nic *efx = dev_id; | |
1127 | bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); | |
1128 | struct efx_channel *channel; | |
1129 | efx_dword_t reg; | |
1130 | u32 queues; | |
1131 | ||
1132 | /* Read the ISR which also ACKs the interrupts */ | |
1133 | efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); | |
1134 | queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); | |
1135 | ||
1136 | if (queues == 0) | |
1137 | return IRQ_NONE; | |
1138 | ||
1139 | if (likely(soft_enabled)) { | |
1140 | /* Note test interrupts */ | |
1141 | if (queues & (1U << efx->irq_level)) | |
1142 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1143 | ||
1144 | efx_for_each_channel(channel, efx) { | |
1145 | if (queues & 1) | |
1146 | efx_schedule_channel_irq(channel); | |
1147 | queues >>= 1; | |
1148 | } | |
1149 | } | |
1150 | ||
1151 | netif_vdbg(efx, intr, efx->net_dev, | |
1152 | "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", | |
1153 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); | |
1154 | ||
1155 | return IRQ_HANDLED; | |
1156 | } | |
1157 | ||
1158 | static void efx_ef10_irq_test_generate(struct efx_nic *efx) | |
1159 | { | |
1160 | MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); | |
1161 | ||
1162 | BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); | |
1163 | ||
1164 | MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); | |
1165 | (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, | |
1166 | inbuf, sizeof(inbuf), NULL, 0, NULL); | |
1167 | } | |
1168 | ||
1169 | static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) | |
1170 | { | |
1171 | return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, | |
1172 | (tx_queue->ptr_mask + 1) * | |
1173 | sizeof(efx_qword_t), | |
1174 | GFP_KERNEL); | |
1175 | } | |
1176 | ||
1177 | /* This writes to the TX_DESC_WPTR and also pushes data */ | |
1178 | static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, | |
1179 | const efx_qword_t *txd) | |
1180 | { | |
1181 | unsigned int write_ptr; | |
1182 | efx_oword_t reg; | |
1183 | ||
1184 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; | |
1185 | EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); | |
1186 | reg.qword[0] = *txd; | |
1187 | efx_writeo_page(tx_queue->efx, ®, | |
1188 | ER_DZ_TX_DESC_UPD, tx_queue->queue); | |
1189 | } | |
1190 | ||
1191 | static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) | |
1192 | { | |
1193 | MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / | |
1194 | EFX_BUF_SIZE)); | |
1195 | MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN); | |
1196 | bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; | |
1197 | size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; | |
1198 | struct efx_channel *channel = tx_queue->channel; | |
1199 | struct efx_nic *efx = tx_queue->efx; | |
1200 | size_t inlen, outlen; | |
1201 | dma_addr_t dma_addr; | |
1202 | efx_qword_t *txd; | |
1203 | int rc; | |
1204 | int i; | |
1205 | ||
1206 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); | |
1207 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); | |
1208 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); | |
1209 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); | |
1210 | MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS, | |
1211 | INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, | |
1212 | INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); | |
1213 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); | |
1214 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); | |
1215 | ||
1216 | dma_addr = tx_queue->txd.buf.dma_addr; | |
1217 | ||
1218 | netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", | |
1219 | tx_queue->queue, entries, (u64)dma_addr); | |
1220 | ||
1221 | for (i = 0; i < entries; ++i) { | |
1222 | MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); | |
1223 | dma_addr += EFX_BUF_SIZE; | |
1224 | } | |
1225 | ||
1226 | inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); | |
1227 | ||
1228 | rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen, | |
1229 | outbuf, sizeof(outbuf), &outlen); | |
1230 | if (rc) | |
1231 | goto fail; | |
1232 | ||
1233 | /* A previous user of this TX queue might have set us up the | |
1234 | * bomb by writing a descriptor to the TX push collector but | |
1235 | * not the doorbell. (Each collector belongs to a port, not a | |
1236 | * queue or function, so cannot easily be reset.) We must | |
1237 | * attempt to push a no-op descriptor in its place. | |
1238 | */ | |
1239 | tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; | |
1240 | tx_queue->insert_count = 1; | |
1241 | txd = efx_tx_desc(tx_queue, 0); | |
1242 | EFX_POPULATE_QWORD_4(*txd, | |
1243 | ESF_DZ_TX_DESC_IS_OPT, true, | |
1244 | ESF_DZ_TX_OPTION_TYPE, | |
1245 | ESE_DZ_TX_OPTION_DESC_CRC_CSUM, | |
1246 | ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, | |
1247 | ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); | |
1248 | tx_queue->write_count = 1; | |
1249 | wmb(); | |
1250 | efx_ef10_push_tx_desc(tx_queue, txd); | |
1251 | ||
1252 | return; | |
1253 | ||
1254 | fail: | |
48ce5634 BH |
1255 | netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", |
1256 | tx_queue->queue); | |
8127d661 BH |
1257 | } |
1258 | ||
1259 | static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) | |
1260 | { | |
1261 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); | |
1262 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN); | |
1263 | struct efx_nic *efx = tx_queue->efx; | |
1264 | size_t outlen; | |
1265 | int rc; | |
1266 | ||
1267 | MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, | |
1268 | tx_queue->queue); | |
1269 | ||
1e0b8120 | 1270 | rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), |
8127d661 BH |
1271 | outbuf, sizeof(outbuf), &outlen); |
1272 | ||
1273 | if (rc && rc != -EALREADY) | |
1274 | goto fail; | |
1275 | ||
1276 | return; | |
1277 | ||
1278 | fail: | |
1e0b8120 EC |
1279 | efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, |
1280 | outbuf, outlen, rc); | |
8127d661 BH |
1281 | } |
1282 | ||
1283 | static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) | |
1284 | { | |
1285 | efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); | |
1286 | } | |
1287 | ||
1288 | /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ | |
1289 | static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) | |
1290 | { | |
1291 | unsigned int write_ptr; | |
1292 | efx_dword_t reg; | |
1293 | ||
1294 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; | |
1295 | EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); | |
1296 | efx_writed_page(tx_queue->efx, ®, | |
1297 | ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); | |
1298 | } | |
1299 | ||
1300 | static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) | |
1301 | { | |
1302 | unsigned int old_write_count = tx_queue->write_count; | |
1303 | struct efx_tx_buffer *buffer; | |
1304 | unsigned int write_ptr; | |
1305 | efx_qword_t *txd; | |
1306 | ||
1307 | BUG_ON(tx_queue->write_count == tx_queue->insert_count); | |
1308 | ||
1309 | do { | |
1310 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; | |
1311 | buffer = &tx_queue->buffer[write_ptr]; | |
1312 | txd = efx_tx_desc(tx_queue, write_ptr); | |
1313 | ++tx_queue->write_count; | |
1314 | ||
1315 | /* Create TX descriptor ring entry */ | |
1316 | if (buffer->flags & EFX_TX_BUF_OPTION) { | |
1317 | *txd = buffer->option; | |
1318 | } else { | |
1319 | BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); | |
1320 | EFX_POPULATE_QWORD_3( | |
1321 | *txd, | |
1322 | ESF_DZ_TX_KER_CONT, | |
1323 | buffer->flags & EFX_TX_BUF_CONT, | |
1324 | ESF_DZ_TX_KER_BYTE_CNT, buffer->len, | |
1325 | ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); | |
1326 | } | |
1327 | } while (tx_queue->write_count != tx_queue->insert_count); | |
1328 | ||
1329 | wmb(); /* Ensure descriptors are written before they are fetched */ | |
1330 | ||
1331 | if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { | |
1332 | txd = efx_tx_desc(tx_queue, | |
1333 | old_write_count & tx_queue->ptr_mask); | |
1334 | efx_ef10_push_tx_desc(tx_queue, txd); | |
1335 | ++tx_queue->pushes; | |
1336 | } else { | |
1337 | efx_ef10_notify_tx_desc(tx_queue); | |
1338 | } | |
1339 | } | |
1340 | ||
1341 | static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context) | |
1342 | { | |
1343 | MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); | |
1344 | MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); | |
1345 | size_t outlen; | |
1346 | int rc; | |
1347 | ||
1348 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, | |
1349 | EVB_PORT_ID_ASSIGNED); | |
1350 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, | |
1351 | MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE); | |
1352 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, | |
1353 | EFX_MAX_CHANNELS); | |
1354 | ||
1355 | rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), | |
1356 | outbuf, sizeof(outbuf), &outlen); | |
1357 | if (rc != 0) | |
1358 | return rc; | |
1359 | ||
1360 | if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) | |
1361 | return -EIO; | |
1362 | ||
1363 | *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); | |
1364 | ||
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) | |
1369 | { | |
1370 | MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); | |
1371 | int rc; | |
1372 | ||
1373 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, | |
1374 | context); | |
1375 | ||
1376 | rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), | |
1377 | NULL, 0, NULL); | |
1378 | WARN_ON(rc != 0); | |
1379 | } | |
1380 | ||
1381 | static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context) | |
1382 | { | |
1383 | MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); | |
1384 | MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); | |
1385 | int i, rc; | |
1386 | ||
1387 | MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, | |
1388 | context); | |
1389 | BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != | |
1390 | MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); | |
1391 | ||
1392 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) | |
1393 | MCDI_PTR(tablebuf, | |
1394 | RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = | |
1395 | (u8) efx->rx_indir_table[i]; | |
1396 | ||
1397 | rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, | |
1398 | sizeof(tablebuf), NULL, 0, NULL); | |
1399 | if (rc != 0) | |
1400 | return rc; | |
1401 | ||
1402 | MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, | |
1403 | context); | |
1404 | BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != | |
1405 | MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); | |
1406 | for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) | |
1407 | MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = | |
1408 | efx->rx_hash_key[i]; | |
1409 | ||
1410 | return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, | |
1411 | sizeof(keybuf), NULL, 0, NULL); | |
1412 | } | |
1413 | ||
1414 | static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) | |
1415 | { | |
1416 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1417 | ||
1418 | if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) | |
1419 | efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); | |
1420 | nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; | |
1421 | } | |
1422 | ||
d43050c0 | 1423 | static void efx_ef10_rx_push_rss_config(struct efx_nic *efx) |
8127d661 BH |
1424 | { |
1425 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
1426 | int rc; | |
1427 | ||
d43050c0 | 1428 | netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n"); |
8127d661 BH |
1429 | |
1430 | if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) { | |
1431 | rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context); | |
1432 | if (rc != 0) | |
1433 | goto fail; | |
1434 | } | |
1435 | ||
1436 | rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context); | |
1437 | if (rc != 0) | |
1438 | goto fail; | |
1439 | ||
1440 | return; | |
1441 | ||
1442 | fail: | |
1443 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); | |
1444 | } | |
1445 | ||
1446 | static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) | |
1447 | { | |
1448 | return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, | |
1449 | (rx_queue->ptr_mask + 1) * | |
1450 | sizeof(efx_qword_t), | |
1451 | GFP_KERNEL); | |
1452 | } | |
1453 | ||
1454 | static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) | |
1455 | { | |
1456 | MCDI_DECLARE_BUF(inbuf, | |
1457 | MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / | |
1458 | EFX_BUF_SIZE)); | |
1459 | MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN); | |
1460 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); | |
1461 | size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; | |
1462 | struct efx_nic *efx = rx_queue->efx; | |
1463 | size_t inlen, outlen; | |
1464 | dma_addr_t dma_addr; | |
1465 | int rc; | |
1466 | int i; | |
1467 | ||
1468 | rx_queue->scatter_n = 0; | |
1469 | rx_queue->scatter_len = 0; | |
1470 | ||
1471 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); | |
1472 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); | |
1473 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); | |
1474 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, | |
1475 | efx_rx_queue_index(rx_queue)); | |
bd9a265d JC |
1476 | MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, |
1477 | INIT_RXQ_IN_FLAG_PREFIX, 1, | |
1478 | INIT_RXQ_IN_FLAG_TIMESTAMP, 1); | |
8127d661 BH |
1479 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); |
1480 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); | |
1481 | ||
1482 | dma_addr = rx_queue->rxd.buf.dma_addr; | |
1483 | ||
1484 | netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", | |
1485 | efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); | |
1486 | ||
1487 | for (i = 0; i < entries; ++i) { | |
1488 | MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); | |
1489 | dma_addr += EFX_BUF_SIZE; | |
1490 | } | |
1491 | ||
1492 | inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); | |
1493 | ||
1494 | rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, | |
1495 | outbuf, sizeof(outbuf), &outlen); | |
48ce5634 BH |
1496 | if (rc) |
1497 | netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", | |
1498 | efx_rx_queue_index(rx_queue)); | |
8127d661 BH |
1499 | } |
1500 | ||
1501 | static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) | |
1502 | { | |
1503 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); | |
1504 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN); | |
1505 | struct efx_nic *efx = rx_queue->efx; | |
1506 | size_t outlen; | |
1507 | int rc; | |
1508 | ||
1509 | MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, | |
1510 | efx_rx_queue_index(rx_queue)); | |
1511 | ||
1e0b8120 | 1512 | rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), |
8127d661 BH |
1513 | outbuf, sizeof(outbuf), &outlen); |
1514 | ||
1515 | if (rc && rc != -EALREADY) | |
1516 | goto fail; | |
1517 | ||
1518 | return; | |
1519 | ||
1520 | fail: | |
1e0b8120 EC |
1521 | efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, |
1522 | outbuf, outlen, rc); | |
8127d661 BH |
1523 | } |
1524 | ||
1525 | static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) | |
1526 | { | |
1527 | efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); | |
1528 | } | |
1529 | ||
1530 | /* This creates an entry in the RX descriptor queue */ | |
1531 | static inline void | |
1532 | efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) | |
1533 | { | |
1534 | struct efx_rx_buffer *rx_buf; | |
1535 | efx_qword_t *rxd; | |
1536 | ||
1537 | rxd = efx_rx_desc(rx_queue, index); | |
1538 | rx_buf = efx_rx_buffer(rx_queue, index); | |
1539 | EFX_POPULATE_QWORD_2(*rxd, | |
1540 | ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, | |
1541 | ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); | |
1542 | } | |
1543 | ||
1544 | static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) | |
1545 | { | |
1546 | struct efx_nic *efx = rx_queue->efx; | |
1547 | unsigned int write_count; | |
1548 | efx_dword_t reg; | |
1549 | ||
1550 | /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ | |
1551 | write_count = rx_queue->added_count & ~7; | |
1552 | if (rx_queue->notified_count == write_count) | |
1553 | return; | |
1554 | ||
1555 | do | |
1556 | efx_ef10_build_rx_desc( | |
1557 | rx_queue, | |
1558 | rx_queue->notified_count & rx_queue->ptr_mask); | |
1559 | while (++rx_queue->notified_count != write_count); | |
1560 | ||
1561 | wmb(); | |
1562 | EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, | |
1563 | write_count & rx_queue->ptr_mask); | |
1564 | efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, | |
1565 | efx_rx_queue_index(rx_queue)); | |
1566 | } | |
1567 | ||
1568 | static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; | |
1569 | ||
1570 | static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) | |
1571 | { | |
1572 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); | |
1573 | MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); | |
1574 | efx_qword_t event; | |
1575 | ||
1576 | EFX_POPULATE_QWORD_2(event, | |
1577 | ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, | |
1578 | ESF_DZ_EV_DATA, EFX_EF10_REFILL); | |
1579 | ||
1580 | MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); | |
1581 | ||
1582 | /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has | |
1583 | * already swapped the data to little-endian order. | |
1584 | */ | |
1585 | memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], | |
1586 | sizeof(efx_qword_t)); | |
1587 | ||
1588 | efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, | |
1589 | inbuf, sizeof(inbuf), 0, | |
1590 | efx_ef10_rx_defer_refill_complete, 0); | |
1591 | } | |
1592 | ||
1593 | static void | |
1594 | efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, | |
1595 | int rc, efx_dword_t *outbuf, | |
1596 | size_t outlen_actual) | |
1597 | { | |
1598 | /* nothing to do */ | |
1599 | } | |
1600 | ||
1601 | static int efx_ef10_ev_probe(struct efx_channel *channel) | |
1602 | { | |
1603 | return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, | |
1604 | (channel->eventq_mask + 1) * | |
1605 | sizeof(efx_qword_t), | |
1606 | GFP_KERNEL); | |
1607 | } | |
1608 | ||
1609 | static int efx_ef10_ev_init(struct efx_channel *channel) | |
1610 | { | |
1611 | MCDI_DECLARE_BUF(inbuf, | |
1612 | MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / | |
1613 | EFX_BUF_SIZE)); | |
1614 | MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN); | |
1615 | size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; | |
1616 | struct efx_nic *efx = channel->efx; | |
1617 | struct efx_ef10_nic_data *nic_data; | |
1618 | bool supports_rx_merge; | |
1619 | size_t inlen, outlen; | |
1620 | dma_addr_t dma_addr; | |
1621 | int rc; | |
1622 | int i; | |
1623 | ||
1624 | nic_data = efx->nic_data; | |
1625 | supports_rx_merge = | |
1626 | !!(nic_data->datapath_caps & | |
1627 | 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); | |
1628 | ||
1629 | /* Fill event queue with all ones (i.e. empty events) */ | |
1630 | memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); | |
1631 | ||
1632 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); | |
1633 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); | |
1634 | /* INIT_EVQ expects index in vector table, not absolute */ | |
1635 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); | |
1636 | MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, | |
1637 | INIT_EVQ_IN_FLAG_INTERRUPTING, 1, | |
1638 | INIT_EVQ_IN_FLAG_RX_MERGE, 1, | |
1639 | INIT_EVQ_IN_FLAG_TX_MERGE, 1, | |
1640 | INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge); | |
1641 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, | |
1642 | MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); | |
1643 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); | |
1644 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); | |
1645 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, | |
1646 | MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); | |
1647 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); | |
1648 | ||
1649 | dma_addr = channel->eventq.buf.dma_addr; | |
1650 | for (i = 0; i < entries; ++i) { | |
1651 | MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); | |
1652 | dma_addr += EFX_BUF_SIZE; | |
1653 | } | |
1654 | ||
1655 | inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); | |
1656 | ||
1657 | rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, | |
1658 | outbuf, sizeof(outbuf), &outlen); | |
8127d661 | 1659 | /* IRQ return is ignored */ |
8127d661 BH |
1660 | return rc; |
1661 | } | |
1662 | ||
1663 | static void efx_ef10_ev_fini(struct efx_channel *channel) | |
1664 | { | |
1665 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); | |
1666 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN); | |
1667 | struct efx_nic *efx = channel->efx; | |
1668 | size_t outlen; | |
1669 | int rc; | |
1670 | ||
1671 | MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); | |
1672 | ||
1e0b8120 | 1673 | rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), |
8127d661 BH |
1674 | outbuf, sizeof(outbuf), &outlen); |
1675 | ||
1676 | if (rc && rc != -EALREADY) | |
1677 | goto fail; | |
1678 | ||
1679 | return; | |
1680 | ||
1681 | fail: | |
1e0b8120 EC |
1682 | efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, |
1683 | outbuf, outlen, rc); | |
8127d661 BH |
1684 | } |
1685 | ||
1686 | static void efx_ef10_ev_remove(struct efx_channel *channel) | |
1687 | { | |
1688 | efx_nic_free_buffer(channel->efx, &channel->eventq.buf); | |
1689 | } | |
1690 | ||
1691 | static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, | |
1692 | unsigned int rx_queue_label) | |
1693 | { | |
1694 | struct efx_nic *efx = rx_queue->efx; | |
1695 | ||
1696 | netif_info(efx, hw, efx->net_dev, | |
1697 | "rx event arrived on queue %d labeled as queue %u\n", | |
1698 | efx_rx_queue_index(rx_queue), rx_queue_label); | |
1699 | ||
1700 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1701 | } | |
1702 | ||
1703 | static void | |
1704 | efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, | |
1705 | unsigned int actual, unsigned int expected) | |
1706 | { | |
1707 | unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; | |
1708 | struct efx_nic *efx = rx_queue->efx; | |
1709 | ||
1710 | netif_info(efx, hw, efx->net_dev, | |
1711 | "dropped %d events (index=%d expected=%d)\n", | |
1712 | dropped, actual, expected); | |
1713 | ||
1714 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1715 | } | |
1716 | ||
1717 | /* partially received RX was aborted. clean up. */ | |
1718 | static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) | |
1719 | { | |
1720 | unsigned int rx_desc_ptr; | |
1721 | ||
8127d661 BH |
1722 | netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, |
1723 | "scattered RX aborted (dropping %u buffers)\n", | |
1724 | rx_queue->scatter_n); | |
1725 | ||
1726 | rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; | |
1727 | ||
1728 | efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, | |
1729 | 0, EFX_RX_PKT_DISCARD); | |
1730 | ||
1731 | rx_queue->removed_count += rx_queue->scatter_n; | |
1732 | rx_queue->scatter_n = 0; | |
1733 | rx_queue->scatter_len = 0; | |
1734 | ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; | |
1735 | } | |
1736 | ||
1737 | static int efx_ef10_handle_rx_event(struct efx_channel *channel, | |
1738 | const efx_qword_t *event) | |
1739 | { | |
1740 | unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; | |
1741 | unsigned int n_descs, n_packets, i; | |
1742 | struct efx_nic *efx = channel->efx; | |
1743 | struct efx_rx_queue *rx_queue; | |
1744 | bool rx_cont; | |
1745 | u16 flags = 0; | |
1746 | ||
1747 | if (unlikely(ACCESS_ONCE(efx->reset_pending))) | |
1748 | return 0; | |
1749 | ||
1750 | /* Basic packet information */ | |
1751 | rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); | |
1752 | next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); | |
1753 | rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); | |
1754 | rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); | |
1755 | rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); | |
1756 | ||
48ce5634 BH |
1757 | if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) |
1758 | netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" | |
1759 | EFX_QWORD_FMT "\n", | |
1760 | EFX_QWORD_VAL(*event)); | |
8127d661 BH |
1761 | |
1762 | rx_queue = efx_channel_get_rx_queue(channel); | |
1763 | ||
1764 | if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) | |
1765 | efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); | |
1766 | ||
1767 | n_descs = ((next_ptr_lbits - rx_queue->removed_count) & | |
1768 | ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); | |
1769 | ||
1770 | if (n_descs != rx_queue->scatter_n + 1) { | |
92a04168 BH |
1771 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
1772 | ||
8127d661 BH |
1773 | /* detect rx abort */ |
1774 | if (unlikely(n_descs == rx_queue->scatter_n)) { | |
48ce5634 BH |
1775 | if (rx_queue->scatter_n == 0 || rx_bytes != 0) |
1776 | netdev_WARN(efx->net_dev, | |
1777 | "invalid RX abort: scatter_n=%u event=" | |
1778 | EFX_QWORD_FMT "\n", | |
1779 | rx_queue->scatter_n, | |
1780 | EFX_QWORD_VAL(*event)); | |
8127d661 BH |
1781 | efx_ef10_handle_rx_abort(rx_queue); |
1782 | return 0; | |
1783 | } | |
1784 | ||
92a04168 BH |
1785 | /* Check that RX completion merging is valid, i.e. |
1786 | * the current firmware supports it and this is a | |
1787 | * non-scattered packet. | |
1788 | */ | |
1789 | if (!(nic_data->datapath_caps & | |
1790 | (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || | |
1791 | rx_queue->scatter_n != 0 || rx_cont) { | |
8127d661 BH |
1792 | efx_ef10_handle_rx_bad_lbits( |
1793 | rx_queue, next_ptr_lbits, | |
1794 | (rx_queue->removed_count + | |
1795 | rx_queue->scatter_n + 1) & | |
1796 | ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); | |
1797 | return 0; | |
1798 | } | |
1799 | ||
1800 | /* Merged completion for multiple non-scattered packets */ | |
1801 | rx_queue->scatter_n = 1; | |
1802 | rx_queue->scatter_len = 0; | |
1803 | n_packets = n_descs; | |
1804 | ++channel->n_rx_merge_events; | |
1805 | channel->n_rx_merge_packets += n_packets; | |
1806 | flags |= EFX_RX_PKT_PREFIX_LEN; | |
1807 | } else { | |
1808 | ++rx_queue->scatter_n; | |
1809 | rx_queue->scatter_len += rx_bytes; | |
1810 | if (rx_cont) | |
1811 | return 0; | |
1812 | n_packets = 1; | |
1813 | } | |
1814 | ||
1815 | if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) | |
1816 | flags |= EFX_RX_PKT_DISCARD; | |
1817 | ||
1818 | if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { | |
1819 | channel->n_rx_ip_hdr_chksum_err += n_packets; | |
1820 | } else if (unlikely(EFX_QWORD_FIELD(*event, | |
1821 | ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { | |
1822 | channel->n_rx_tcp_udp_chksum_err += n_packets; | |
1823 | } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || | |
1824 | rx_l4_class == ESE_DZ_L4_CLASS_UDP) { | |
1825 | flags |= EFX_RX_PKT_CSUMMED; | |
1826 | } | |
1827 | ||
1828 | if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) | |
1829 | flags |= EFX_RX_PKT_TCP; | |
1830 | ||
1831 | channel->irq_mod_score += 2 * n_packets; | |
1832 | ||
1833 | /* Handle received packet(s) */ | |
1834 | for (i = 0; i < n_packets; i++) { | |
1835 | efx_rx_packet(rx_queue, | |
1836 | rx_queue->removed_count & rx_queue->ptr_mask, | |
1837 | rx_queue->scatter_n, rx_queue->scatter_len, | |
1838 | flags); | |
1839 | rx_queue->removed_count += rx_queue->scatter_n; | |
1840 | } | |
1841 | ||
1842 | rx_queue->scatter_n = 0; | |
1843 | rx_queue->scatter_len = 0; | |
1844 | ||
1845 | return n_packets; | |
1846 | } | |
1847 | ||
1848 | static int | |
1849 | efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) | |
1850 | { | |
1851 | struct efx_nic *efx = channel->efx; | |
1852 | struct efx_tx_queue *tx_queue; | |
1853 | unsigned int tx_ev_desc_ptr; | |
1854 | unsigned int tx_ev_q_label; | |
1855 | int tx_descs = 0; | |
1856 | ||
1857 | if (unlikely(ACCESS_ONCE(efx->reset_pending))) | |
1858 | return 0; | |
1859 | ||
1860 | if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) | |
1861 | return 0; | |
1862 | ||
1863 | /* Transmit completion */ | |
1864 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); | |
1865 | tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); | |
1866 | tx_queue = efx_channel_get_tx_queue(channel, | |
1867 | tx_ev_q_label % EFX_TXQ_TYPES); | |
1868 | tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & | |
1869 | tx_queue->ptr_mask); | |
1870 | efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); | |
1871 | ||
1872 | return tx_descs; | |
1873 | } | |
1874 | ||
1875 | static void | |
1876 | efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) | |
1877 | { | |
1878 | struct efx_nic *efx = channel->efx; | |
1879 | int subcode; | |
1880 | ||
1881 | subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); | |
1882 | ||
1883 | switch (subcode) { | |
1884 | case ESE_DZ_DRV_TIMER_EV: | |
1885 | case ESE_DZ_DRV_WAKE_UP_EV: | |
1886 | break; | |
1887 | case ESE_DZ_DRV_START_UP_EV: | |
1888 | /* event queue init complete. ok. */ | |
1889 | break; | |
1890 | default: | |
1891 | netif_err(efx, hw, efx->net_dev, | |
1892 | "channel %d unknown driver event type %d" | |
1893 | " (data " EFX_QWORD_FMT ")\n", | |
1894 | channel->channel, subcode, | |
1895 | EFX_QWORD_VAL(*event)); | |
1896 | ||
1897 | } | |
1898 | } | |
1899 | ||
1900 | static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, | |
1901 | efx_qword_t *event) | |
1902 | { | |
1903 | struct efx_nic *efx = channel->efx; | |
1904 | u32 subcode; | |
1905 | ||
1906 | subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); | |
1907 | ||
1908 | switch (subcode) { | |
1909 | case EFX_EF10_TEST: | |
1910 | channel->event_test_cpu = raw_smp_processor_id(); | |
1911 | break; | |
1912 | case EFX_EF10_REFILL: | |
1913 | /* The queue must be empty, so we won't receive any rx | |
1914 | * events, so efx_process_channel() won't refill the | |
1915 | * queue. Refill it here | |
1916 | */ | |
cce28794 | 1917 | efx_fast_push_rx_descriptors(&channel->rx_queue, true); |
8127d661 BH |
1918 | break; |
1919 | default: | |
1920 | netif_err(efx, hw, efx->net_dev, | |
1921 | "channel %d unknown driver event type %u" | |
1922 | " (data " EFX_QWORD_FMT ")\n", | |
1923 | channel->channel, (unsigned) subcode, | |
1924 | EFX_QWORD_VAL(*event)); | |
1925 | } | |
1926 | } | |
1927 | ||
1928 | static int efx_ef10_ev_process(struct efx_channel *channel, int quota) | |
1929 | { | |
1930 | struct efx_nic *efx = channel->efx; | |
1931 | efx_qword_t event, *p_event; | |
1932 | unsigned int read_ptr; | |
1933 | int ev_code; | |
1934 | int tx_descs = 0; | |
1935 | int spent = 0; | |
1936 | ||
1937 | read_ptr = channel->eventq_read_ptr; | |
1938 | ||
1939 | for (;;) { | |
1940 | p_event = efx_event(channel, read_ptr); | |
1941 | event = *p_event; | |
1942 | ||
1943 | if (!efx_event_present(&event)) | |
1944 | break; | |
1945 | ||
1946 | EFX_SET_QWORD(*p_event); | |
1947 | ||
1948 | ++read_ptr; | |
1949 | ||
1950 | ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); | |
1951 | ||
1952 | netif_vdbg(efx, drv, efx->net_dev, | |
1953 | "processing event on %d " EFX_QWORD_FMT "\n", | |
1954 | channel->channel, EFX_QWORD_VAL(event)); | |
1955 | ||
1956 | switch (ev_code) { | |
1957 | case ESE_DZ_EV_CODE_MCDI_EV: | |
1958 | efx_mcdi_process_event(channel, &event); | |
1959 | break; | |
1960 | case ESE_DZ_EV_CODE_RX_EV: | |
1961 | spent += efx_ef10_handle_rx_event(channel, &event); | |
1962 | if (spent >= quota) { | |
1963 | /* XXX can we split a merged event to | |
1964 | * avoid going over-quota? | |
1965 | */ | |
1966 | spent = quota; | |
1967 | goto out; | |
1968 | } | |
1969 | break; | |
1970 | case ESE_DZ_EV_CODE_TX_EV: | |
1971 | tx_descs += efx_ef10_handle_tx_event(channel, &event); | |
1972 | if (tx_descs > efx->txq_entries) { | |
1973 | spent = quota; | |
1974 | goto out; | |
1975 | } else if (++spent == quota) { | |
1976 | goto out; | |
1977 | } | |
1978 | break; | |
1979 | case ESE_DZ_EV_CODE_DRIVER_EV: | |
1980 | efx_ef10_handle_driver_event(channel, &event); | |
1981 | if (++spent == quota) | |
1982 | goto out; | |
1983 | break; | |
1984 | case EFX_EF10_DRVGEN_EV: | |
1985 | efx_ef10_handle_driver_generated_event(channel, &event); | |
1986 | break; | |
1987 | default: | |
1988 | netif_err(efx, hw, efx->net_dev, | |
1989 | "channel %d unknown event type %d" | |
1990 | " (data " EFX_QWORD_FMT ")\n", | |
1991 | channel->channel, ev_code, | |
1992 | EFX_QWORD_VAL(event)); | |
1993 | } | |
1994 | } | |
1995 | ||
1996 | out: | |
1997 | channel->eventq_read_ptr = read_ptr; | |
1998 | return spent; | |
1999 | } | |
2000 | ||
2001 | static void efx_ef10_ev_read_ack(struct efx_channel *channel) | |
2002 | { | |
2003 | struct efx_nic *efx = channel->efx; | |
2004 | efx_dword_t rptr; | |
2005 | ||
2006 | if (EFX_EF10_WORKAROUND_35388(efx)) { | |
2007 | BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < | |
2008 | (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); | |
2009 | BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > | |
2010 | (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); | |
2011 | ||
2012 | EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, | |
2013 | EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, | |
2014 | ERF_DD_EVQ_IND_RPTR, | |
2015 | (channel->eventq_read_ptr & | |
2016 | channel->eventq_mask) >> | |
2017 | ERF_DD_EVQ_IND_RPTR_WIDTH); | |
2018 | efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, | |
2019 | channel->channel); | |
2020 | EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, | |
2021 | EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, | |
2022 | ERF_DD_EVQ_IND_RPTR, | |
2023 | channel->eventq_read_ptr & | |
2024 | ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); | |
2025 | efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, | |
2026 | channel->channel); | |
2027 | } else { | |
2028 | EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, | |
2029 | channel->eventq_read_ptr & | |
2030 | channel->eventq_mask); | |
2031 | efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); | |
2032 | } | |
2033 | } | |
2034 | ||
2035 | static void efx_ef10_ev_test_generate(struct efx_channel *channel) | |
2036 | { | |
2037 | MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); | |
2038 | struct efx_nic *efx = channel->efx; | |
2039 | efx_qword_t event; | |
2040 | int rc; | |
2041 | ||
2042 | EFX_POPULATE_QWORD_2(event, | |
2043 | ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, | |
2044 | ESF_DZ_EV_DATA, EFX_EF10_TEST); | |
2045 | ||
2046 | MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); | |
2047 | ||
2048 | /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has | |
2049 | * already swapped the data to little-endian order. | |
2050 | */ | |
2051 | memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], | |
2052 | sizeof(efx_qword_t)); | |
2053 | ||
2054 | rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), | |
2055 | NULL, 0, NULL); | |
2056 | if (rc != 0) | |
2057 | goto fail; | |
2058 | ||
2059 | return; | |
2060 | ||
2061 | fail: | |
2062 | WARN_ON(true); | |
2063 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); | |
2064 | } | |
2065 | ||
2066 | void efx_ef10_handle_drain_event(struct efx_nic *efx) | |
2067 | { | |
2068 | if (atomic_dec_and_test(&efx->active_queues)) | |
2069 | wake_up(&efx->flush_wq); | |
2070 | ||
2071 | WARN_ON(atomic_read(&efx->active_queues) < 0); | |
2072 | } | |
2073 | ||
2074 | static int efx_ef10_fini_dmaq(struct efx_nic *efx) | |
2075 | { | |
2076 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
2077 | struct efx_channel *channel; | |
2078 | struct efx_tx_queue *tx_queue; | |
2079 | struct efx_rx_queue *rx_queue; | |
2080 | int pending; | |
2081 | ||
2082 | /* If the MC has just rebooted, the TX/RX queues will have already been | |
2083 | * torn down, but efx->active_queues needs to be set to zero. | |
2084 | */ | |
2085 | if (nic_data->must_realloc_vis) { | |
2086 | atomic_set(&efx->active_queues, 0); | |
2087 | return 0; | |
2088 | } | |
2089 | ||
2090 | /* Do not attempt to write to the NIC during EEH recovery */ | |
2091 | if (efx->state != STATE_RECOVERY) { | |
2092 | efx_for_each_channel(channel, efx) { | |
2093 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
2094 | efx_ef10_rx_fini(rx_queue); | |
2095 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
2096 | efx_ef10_tx_fini(tx_queue); | |
2097 | } | |
2098 | ||
2099 | wait_event_timeout(efx->flush_wq, | |
2100 | atomic_read(&efx->active_queues) == 0, | |
2101 | msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); | |
2102 | pending = atomic_read(&efx->active_queues); | |
2103 | if (pending) { | |
2104 | netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", | |
2105 | pending); | |
2106 | return -ETIMEDOUT; | |
2107 | } | |
2108 | } | |
2109 | ||
2110 | return 0; | |
2111 | } | |
2112 | ||
2113 | static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, | |
2114 | const struct efx_filter_spec *right) | |
2115 | { | |
2116 | if ((left->match_flags ^ right->match_flags) | | |
2117 | ((left->flags ^ right->flags) & | |
2118 | (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) | |
2119 | return false; | |
2120 | ||
2121 | return memcmp(&left->outer_vid, &right->outer_vid, | |
2122 | sizeof(struct efx_filter_spec) - | |
2123 | offsetof(struct efx_filter_spec, outer_vid)) == 0; | |
2124 | } | |
2125 | ||
2126 | static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) | |
2127 | { | |
2128 | BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); | |
2129 | return jhash2((const u32 *)&spec->outer_vid, | |
2130 | (sizeof(struct efx_filter_spec) - | |
2131 | offsetof(struct efx_filter_spec, outer_vid)) / 4, | |
2132 | 0); | |
2133 | /* XXX should we randomise the initval? */ | |
2134 | } | |
2135 | ||
2136 | /* Decide whether a filter should be exclusive or else should allow | |
2137 | * delivery to additional recipients. Currently we decide that | |
2138 | * filters for specific local unicast MAC and IP addresses are | |
2139 | * exclusive. | |
2140 | */ | |
2141 | static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) | |
2142 | { | |
2143 | if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && | |
2144 | !is_multicast_ether_addr(spec->loc_mac)) | |
2145 | return true; | |
2146 | ||
2147 | if ((spec->match_flags & | |
2148 | (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == | |
2149 | (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { | |
2150 | if (spec->ether_type == htons(ETH_P_IP) && | |
2151 | !ipv4_is_multicast(spec->loc_host[0])) | |
2152 | return true; | |
2153 | if (spec->ether_type == htons(ETH_P_IPV6) && | |
2154 | ((const u8 *)spec->loc_host)[0] != 0xff) | |
2155 | return true; | |
2156 | } | |
2157 | ||
2158 | return false; | |
2159 | } | |
2160 | ||
2161 | static struct efx_filter_spec * | |
2162 | efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, | |
2163 | unsigned int filter_idx) | |
2164 | { | |
2165 | return (struct efx_filter_spec *)(table->entry[filter_idx].spec & | |
2166 | ~EFX_EF10_FILTER_FLAGS); | |
2167 | } | |
2168 | ||
2169 | static unsigned int | |
2170 | efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, | |
2171 | unsigned int filter_idx) | |
2172 | { | |
2173 | return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; | |
2174 | } | |
2175 | ||
2176 | static void | |
2177 | efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, | |
2178 | unsigned int filter_idx, | |
2179 | const struct efx_filter_spec *spec, | |
2180 | unsigned int flags) | |
2181 | { | |
2182 | table->entry[filter_idx].spec = (unsigned long)spec | flags; | |
2183 | } | |
2184 | ||
2185 | static void efx_ef10_filter_push_prep(struct efx_nic *efx, | |
2186 | const struct efx_filter_spec *spec, | |
2187 | efx_dword_t *inbuf, u64 handle, | |
2188 | bool replacing) | |
2189 | { | |
2190 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
2191 | ||
2192 | memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); | |
2193 | ||
2194 | if (replacing) { | |
2195 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
2196 | MC_CMD_FILTER_OP_IN_OP_REPLACE); | |
2197 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); | |
2198 | } else { | |
2199 | u32 match_fields = 0; | |
2200 | ||
2201 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
2202 | efx_ef10_filter_is_exclusive(spec) ? | |
2203 | MC_CMD_FILTER_OP_IN_OP_INSERT : | |
2204 | MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); | |
2205 | ||
2206 | /* Convert match flags and values. Unlike almost | |
2207 | * everything else in MCDI, these fields are in | |
2208 | * network byte order. | |
2209 | */ | |
2210 | if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) | |
2211 | match_fields |= | |
2212 | is_multicast_ether_addr(spec->loc_mac) ? | |
2213 | 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : | |
2214 | 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; | |
2215 | #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ | |
2216 | if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ | |
2217 | match_fields |= \ | |
2218 | 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ | |
2219 | mcdi_field ## _LBN; \ | |
2220 | BUILD_BUG_ON( \ | |
2221 | MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ | |
2222 | sizeof(spec->gen_field)); \ | |
2223 | memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ | |
2224 | &spec->gen_field, sizeof(spec->gen_field)); \ | |
2225 | } | |
2226 | COPY_FIELD(REM_HOST, rem_host, SRC_IP); | |
2227 | COPY_FIELD(LOC_HOST, loc_host, DST_IP); | |
2228 | COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); | |
2229 | COPY_FIELD(REM_PORT, rem_port, SRC_PORT); | |
2230 | COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); | |
2231 | COPY_FIELD(LOC_PORT, loc_port, DST_PORT); | |
2232 | COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); | |
2233 | COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); | |
2234 | COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); | |
2235 | COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); | |
2236 | #undef COPY_FIELD | |
2237 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, | |
2238 | match_fields); | |
2239 | } | |
2240 | ||
2241 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); | |
2242 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, | |
2243 | spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? | |
2244 | MC_CMD_FILTER_OP_IN_RX_DEST_DROP : | |
2245 | MC_CMD_FILTER_OP_IN_RX_DEST_HOST); | |
2246 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, | |
2247 | MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); | |
2248 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, spec->dmaq_id); | |
2249 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, | |
2250 | (spec->flags & EFX_FILTER_FLAG_RX_RSS) ? | |
2251 | MC_CMD_FILTER_OP_IN_RX_MODE_RSS : | |
2252 | MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); | |
2253 | if (spec->flags & EFX_FILTER_FLAG_RX_RSS) | |
2254 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, | |
2255 | spec->rss_context != | |
2256 | EFX_FILTER_RSS_CONTEXT_DEFAULT ? | |
2257 | spec->rss_context : nic_data->rx_rss_context); | |
2258 | } | |
2259 | ||
2260 | static int efx_ef10_filter_push(struct efx_nic *efx, | |
2261 | const struct efx_filter_spec *spec, | |
2262 | u64 *handle, bool replacing) | |
2263 | { | |
2264 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); | |
2265 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); | |
2266 | int rc; | |
2267 | ||
2268 | efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); | |
2269 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), | |
2270 | outbuf, sizeof(outbuf), NULL); | |
2271 | if (rc == 0) | |
2272 | *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); | |
065e64c4 BH |
2273 | if (rc == -ENOSPC) |
2274 | rc = -EBUSY; /* to match efx_farch_filter_insert() */ | |
8127d661 BH |
2275 | return rc; |
2276 | } | |
2277 | ||
2278 | static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table, | |
2279 | enum efx_filter_match_flags match_flags) | |
2280 | { | |
2281 | unsigned int match_pri; | |
2282 | ||
2283 | for (match_pri = 0; | |
2284 | match_pri < table->rx_match_count; | |
2285 | match_pri++) | |
2286 | if (table->rx_match_flags[match_pri] == match_flags) | |
2287 | return match_pri; | |
2288 | ||
2289 | return -EPROTONOSUPPORT; | |
2290 | } | |
2291 | ||
2292 | static s32 efx_ef10_filter_insert(struct efx_nic *efx, | |
2293 | struct efx_filter_spec *spec, | |
2294 | bool replace_equal) | |
2295 | { | |
2296 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2297 | DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); | |
2298 | struct efx_filter_spec *saved_spec; | |
2299 | unsigned int match_pri, hash; | |
2300 | unsigned int priv_flags; | |
2301 | bool replacing = false; | |
2302 | int ins_index = -1; | |
2303 | DEFINE_WAIT(wait); | |
2304 | bool is_mc_recip; | |
2305 | s32 rc; | |
2306 | ||
2307 | /* For now, only support RX filters */ | |
2308 | if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != | |
2309 | EFX_FILTER_FLAG_RX) | |
2310 | return -EINVAL; | |
2311 | ||
2312 | rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags); | |
2313 | if (rc < 0) | |
2314 | return rc; | |
2315 | match_pri = rc; | |
2316 | ||
2317 | hash = efx_ef10_filter_hash(spec); | |
2318 | is_mc_recip = efx_filter_is_mc_recipient(spec); | |
2319 | if (is_mc_recip) | |
2320 | bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); | |
2321 | ||
2322 | /* Find any existing filters with the same match tuple or | |
2323 | * else a free slot to insert at. If any of them are busy, | |
2324 | * we have to wait and retry. | |
2325 | */ | |
2326 | for (;;) { | |
2327 | unsigned int depth = 1; | |
2328 | unsigned int i; | |
2329 | ||
2330 | spin_lock_bh(&efx->filter_lock); | |
2331 | ||
2332 | for (;;) { | |
2333 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); | |
2334 | saved_spec = efx_ef10_filter_entry_spec(table, i); | |
2335 | ||
2336 | if (!saved_spec) { | |
2337 | if (ins_index < 0) | |
2338 | ins_index = i; | |
2339 | } else if (efx_ef10_filter_equal(spec, saved_spec)) { | |
2340 | if (table->entry[i].spec & | |
2341 | EFX_EF10_FILTER_FLAG_BUSY) | |
2342 | break; | |
2343 | if (spec->priority < saved_spec->priority && | |
7665d1ab | 2344 | spec->priority != EFX_FILTER_PRI_AUTO) { |
8127d661 BH |
2345 | rc = -EPERM; |
2346 | goto out_unlock; | |
2347 | } | |
2348 | if (!is_mc_recip) { | |
2349 | /* This is the only one */ | |
2350 | if (spec->priority == | |
2351 | saved_spec->priority && | |
2352 | !replace_equal) { | |
2353 | rc = -EEXIST; | |
2354 | goto out_unlock; | |
2355 | } | |
2356 | ins_index = i; | |
2357 | goto found; | |
2358 | } else if (spec->priority > | |
2359 | saved_spec->priority || | |
2360 | (spec->priority == | |
2361 | saved_spec->priority && | |
2362 | replace_equal)) { | |
2363 | if (ins_index < 0) | |
2364 | ins_index = i; | |
2365 | else | |
2366 | __set_bit(depth, mc_rem_map); | |
2367 | } | |
2368 | } | |
2369 | ||
2370 | /* Once we reach the maximum search depth, use | |
2371 | * the first suitable slot or return -EBUSY if | |
2372 | * there was none | |
2373 | */ | |
2374 | if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { | |
2375 | if (ins_index < 0) { | |
2376 | rc = -EBUSY; | |
2377 | goto out_unlock; | |
2378 | } | |
2379 | goto found; | |
2380 | } | |
2381 | ||
2382 | ++depth; | |
2383 | } | |
2384 | ||
2385 | prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); | |
2386 | spin_unlock_bh(&efx->filter_lock); | |
2387 | schedule(); | |
2388 | } | |
2389 | ||
2390 | found: | |
2391 | /* Create a software table entry if necessary, and mark it | |
2392 | * busy. We might yet fail to insert, but any attempt to | |
2393 | * insert a conflicting filter while we're waiting for the | |
2394 | * firmware must find the busy entry. | |
2395 | */ | |
2396 | saved_spec = efx_ef10_filter_entry_spec(table, ins_index); | |
2397 | if (saved_spec) { | |
7665d1ab BH |
2398 | if (spec->priority == EFX_FILTER_PRI_AUTO && |
2399 | saved_spec->priority >= EFX_FILTER_PRI_AUTO) { | |
8127d661 | 2400 | /* Just make sure it won't be removed */ |
7665d1ab BH |
2401 | if (saved_spec->priority > EFX_FILTER_PRI_AUTO) |
2402 | saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; | |
8127d661 | 2403 | table->entry[ins_index].spec &= |
b59e6ef8 | 2404 | ~EFX_EF10_FILTER_FLAG_AUTO_OLD; |
8127d661 BH |
2405 | rc = ins_index; |
2406 | goto out_unlock; | |
2407 | } | |
2408 | replacing = true; | |
2409 | priv_flags = efx_ef10_filter_entry_flags(table, ins_index); | |
2410 | } else { | |
2411 | saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); | |
2412 | if (!saved_spec) { | |
2413 | rc = -ENOMEM; | |
2414 | goto out_unlock; | |
2415 | } | |
2416 | *saved_spec = *spec; | |
2417 | priv_flags = 0; | |
2418 | } | |
2419 | efx_ef10_filter_set_entry(table, ins_index, saved_spec, | |
2420 | priv_flags | EFX_EF10_FILTER_FLAG_BUSY); | |
2421 | ||
2422 | /* Mark lower-priority multicast recipients busy prior to removal */ | |
2423 | if (is_mc_recip) { | |
2424 | unsigned int depth, i; | |
2425 | ||
2426 | for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { | |
2427 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); | |
2428 | if (test_bit(depth, mc_rem_map)) | |
2429 | table->entry[i].spec |= | |
2430 | EFX_EF10_FILTER_FLAG_BUSY; | |
2431 | } | |
2432 | } | |
2433 | ||
2434 | spin_unlock_bh(&efx->filter_lock); | |
2435 | ||
2436 | rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, | |
2437 | replacing); | |
2438 | ||
2439 | /* Finalise the software table entry */ | |
2440 | spin_lock_bh(&efx->filter_lock); | |
2441 | if (rc == 0) { | |
2442 | if (replacing) { | |
2443 | /* Update the fields that may differ */ | |
7665d1ab BH |
2444 | if (saved_spec->priority == EFX_FILTER_PRI_AUTO) |
2445 | saved_spec->flags |= | |
2446 | EFX_FILTER_FLAG_RX_OVER_AUTO; | |
8127d661 | 2447 | saved_spec->priority = spec->priority; |
7665d1ab | 2448 | saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; |
8127d661 BH |
2449 | saved_spec->flags |= spec->flags; |
2450 | saved_spec->rss_context = spec->rss_context; | |
2451 | saved_spec->dmaq_id = spec->dmaq_id; | |
2452 | } | |
2453 | } else if (!replacing) { | |
2454 | kfree(saved_spec); | |
2455 | saved_spec = NULL; | |
2456 | } | |
2457 | efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); | |
2458 | ||
2459 | /* Remove and finalise entries for lower-priority multicast | |
2460 | * recipients | |
2461 | */ | |
2462 | if (is_mc_recip) { | |
2463 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); | |
2464 | unsigned int depth, i; | |
2465 | ||
2466 | memset(inbuf, 0, sizeof(inbuf)); | |
2467 | ||
2468 | for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { | |
2469 | if (!test_bit(depth, mc_rem_map)) | |
2470 | continue; | |
2471 | ||
2472 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); | |
2473 | saved_spec = efx_ef10_filter_entry_spec(table, i); | |
2474 | priv_flags = efx_ef10_filter_entry_flags(table, i); | |
2475 | ||
2476 | if (rc == 0) { | |
2477 | spin_unlock_bh(&efx->filter_lock); | |
2478 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
2479 | MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); | |
2480 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, | |
2481 | table->entry[i].handle); | |
2482 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, | |
2483 | inbuf, sizeof(inbuf), | |
2484 | NULL, 0, NULL); | |
2485 | spin_lock_bh(&efx->filter_lock); | |
2486 | } | |
2487 | ||
2488 | if (rc == 0) { | |
2489 | kfree(saved_spec); | |
2490 | saved_spec = NULL; | |
2491 | priv_flags = 0; | |
2492 | } else { | |
2493 | priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; | |
2494 | } | |
2495 | efx_ef10_filter_set_entry(table, i, saved_spec, | |
2496 | priv_flags); | |
2497 | } | |
2498 | } | |
2499 | ||
2500 | /* If successful, return the inserted filter ID */ | |
2501 | if (rc == 0) | |
2502 | rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; | |
2503 | ||
2504 | wake_up_all(&table->waitq); | |
2505 | out_unlock: | |
2506 | spin_unlock_bh(&efx->filter_lock); | |
2507 | finish_wait(&table->waitq, &wait); | |
2508 | return rc; | |
2509 | } | |
2510 | ||
9fd8095d | 2511 | static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) |
8127d661 BH |
2512 | { |
2513 | /* no need to do anything here on EF10 */ | |
2514 | } | |
2515 | ||
2516 | /* Remove a filter. | |
b59e6ef8 BH |
2517 | * If !by_index, remove by ID |
2518 | * If by_index, remove by index | |
8127d661 BH |
2519 | * Filter ID may come from userland and must be range-checked. |
2520 | */ | |
2521 | static int efx_ef10_filter_remove_internal(struct efx_nic *efx, | |
2522 | enum efx_filter_priority priority, | |
b59e6ef8 | 2523 | u32 filter_id, bool by_index) |
8127d661 BH |
2524 | { |
2525 | unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; | |
2526 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2527 | MCDI_DECLARE_BUF(inbuf, | |
2528 | MC_CMD_FILTER_OP_IN_HANDLE_OFST + | |
2529 | MC_CMD_FILTER_OP_IN_HANDLE_LEN); | |
2530 | struct efx_filter_spec *spec; | |
2531 | DEFINE_WAIT(wait); | |
2532 | int rc; | |
2533 | ||
2534 | /* Find the software table entry and mark it busy. Don't | |
2535 | * remove it yet; any attempt to update while we're waiting | |
2536 | * for the firmware must find the busy entry. | |
2537 | */ | |
2538 | for (;;) { | |
2539 | spin_lock_bh(&efx->filter_lock); | |
2540 | if (!(table->entry[filter_idx].spec & | |
2541 | EFX_EF10_FILTER_FLAG_BUSY)) | |
2542 | break; | |
2543 | prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); | |
2544 | spin_unlock_bh(&efx->filter_lock); | |
2545 | schedule(); | |
2546 | } | |
7665d1ab | 2547 | |
8127d661 | 2548 | spec = efx_ef10_filter_entry_spec(table, filter_idx); |
7665d1ab | 2549 | if (!spec || |
b59e6ef8 | 2550 | (!by_index && |
8127d661 BH |
2551 | efx_ef10_filter_rx_match_pri(table, spec->match_flags) != |
2552 | filter_id / HUNT_FILTER_TBL_ROWS)) { | |
2553 | rc = -ENOENT; | |
2554 | goto out_unlock; | |
2555 | } | |
7665d1ab BH |
2556 | |
2557 | if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && | |
2558 | priority == EFX_FILTER_PRI_AUTO) { | |
2559 | /* Just remove flags */ | |
2560 | spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; | |
b59e6ef8 | 2561 | table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; |
7665d1ab BH |
2562 | rc = 0; |
2563 | goto out_unlock; | |
2564 | } | |
2565 | ||
f7284802 | 2566 | if (spec->priority != priority) { |
7665d1ab BH |
2567 | rc = -ENOENT; |
2568 | goto out_unlock; | |
2569 | } | |
2570 | ||
8127d661 BH |
2571 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; |
2572 | spin_unlock_bh(&efx->filter_lock); | |
2573 | ||
7665d1ab | 2574 | if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { |
b59e6ef8 | 2575 | /* Reset to an automatic filter */ |
8127d661 BH |
2576 | |
2577 | struct efx_filter_spec new_spec = *spec; | |
2578 | ||
7665d1ab | 2579 | new_spec.priority = EFX_FILTER_PRI_AUTO; |
8127d661 | 2580 | new_spec.flags = (EFX_FILTER_FLAG_RX | |
7665d1ab | 2581 | EFX_FILTER_FLAG_RX_RSS); |
8127d661 BH |
2582 | new_spec.dmaq_id = 0; |
2583 | new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; | |
2584 | rc = efx_ef10_filter_push(efx, &new_spec, | |
2585 | &table->entry[filter_idx].handle, | |
2586 | true); | |
2587 | ||
2588 | spin_lock_bh(&efx->filter_lock); | |
2589 | if (rc == 0) | |
2590 | *spec = new_spec; | |
2591 | } else { | |
2592 | /* Really remove the filter */ | |
2593 | ||
2594 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
2595 | efx_ef10_filter_is_exclusive(spec) ? | |
2596 | MC_CMD_FILTER_OP_IN_OP_REMOVE : | |
2597 | MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); | |
2598 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, | |
2599 | table->entry[filter_idx].handle); | |
2600 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, | |
2601 | inbuf, sizeof(inbuf), NULL, 0, NULL); | |
2602 | ||
2603 | spin_lock_bh(&efx->filter_lock); | |
2604 | if (rc == 0) { | |
2605 | kfree(spec); | |
2606 | efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); | |
2607 | } | |
2608 | } | |
7665d1ab | 2609 | |
8127d661 BH |
2610 | table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; |
2611 | wake_up_all(&table->waitq); | |
2612 | out_unlock: | |
2613 | spin_unlock_bh(&efx->filter_lock); | |
2614 | finish_wait(&table->waitq, &wait); | |
2615 | return rc; | |
2616 | } | |
2617 | ||
2618 | static int efx_ef10_filter_remove_safe(struct efx_nic *efx, | |
2619 | enum efx_filter_priority priority, | |
2620 | u32 filter_id) | |
2621 | { | |
2622 | return efx_ef10_filter_remove_internal(efx, priority, filter_id, false); | |
2623 | } | |
2624 | ||
2625 | static int efx_ef10_filter_get_safe(struct efx_nic *efx, | |
2626 | enum efx_filter_priority priority, | |
2627 | u32 filter_id, struct efx_filter_spec *spec) | |
2628 | { | |
2629 | unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; | |
2630 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2631 | const struct efx_filter_spec *saved_spec; | |
2632 | int rc; | |
2633 | ||
2634 | spin_lock_bh(&efx->filter_lock); | |
2635 | saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); | |
2636 | if (saved_spec && saved_spec->priority == priority && | |
2637 | efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) == | |
2638 | filter_id / HUNT_FILTER_TBL_ROWS) { | |
2639 | *spec = *saved_spec; | |
2640 | rc = 0; | |
2641 | } else { | |
2642 | rc = -ENOENT; | |
2643 | } | |
2644 | spin_unlock_bh(&efx->filter_lock); | |
2645 | return rc; | |
2646 | } | |
2647 | ||
2648 | static void efx_ef10_filter_clear_rx(struct efx_nic *efx, | |
2649 | enum efx_filter_priority priority) | |
2650 | { | |
2651 | /* TODO */ | |
2652 | } | |
2653 | ||
2654 | static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, | |
2655 | enum efx_filter_priority priority) | |
2656 | { | |
2657 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2658 | unsigned int filter_idx; | |
2659 | s32 count = 0; | |
2660 | ||
2661 | spin_lock_bh(&efx->filter_lock); | |
2662 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { | |
2663 | if (table->entry[filter_idx].spec && | |
2664 | efx_ef10_filter_entry_spec(table, filter_idx)->priority == | |
2665 | priority) | |
2666 | ++count; | |
2667 | } | |
2668 | spin_unlock_bh(&efx->filter_lock); | |
2669 | return count; | |
2670 | } | |
2671 | ||
2672 | static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) | |
2673 | { | |
2674 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2675 | ||
2676 | return table->rx_match_count * HUNT_FILTER_TBL_ROWS; | |
2677 | } | |
2678 | ||
2679 | static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, | |
2680 | enum efx_filter_priority priority, | |
2681 | u32 *buf, u32 size) | |
2682 | { | |
2683 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2684 | struct efx_filter_spec *spec; | |
2685 | unsigned int filter_idx; | |
2686 | s32 count = 0; | |
2687 | ||
2688 | spin_lock_bh(&efx->filter_lock); | |
2689 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { | |
2690 | spec = efx_ef10_filter_entry_spec(table, filter_idx); | |
2691 | if (spec && spec->priority == priority) { | |
2692 | if (count == size) { | |
2693 | count = -EMSGSIZE; | |
2694 | break; | |
2695 | } | |
2696 | buf[count++] = (efx_ef10_filter_rx_match_pri( | |
2697 | table, spec->match_flags) * | |
2698 | HUNT_FILTER_TBL_ROWS + | |
2699 | filter_idx); | |
2700 | } | |
2701 | } | |
2702 | spin_unlock_bh(&efx->filter_lock); | |
2703 | return count; | |
2704 | } | |
2705 | ||
2706 | #ifdef CONFIG_RFS_ACCEL | |
2707 | ||
2708 | static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; | |
2709 | ||
2710 | static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, | |
2711 | struct efx_filter_spec *spec) | |
2712 | { | |
2713 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2714 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); | |
2715 | struct efx_filter_spec *saved_spec; | |
2716 | unsigned int hash, i, depth = 1; | |
2717 | bool replacing = false; | |
2718 | int ins_index = -1; | |
2719 | u64 cookie; | |
2720 | s32 rc; | |
2721 | ||
2722 | /* Must be an RX filter without RSS and not for a multicast | |
2723 | * destination address (RFS only works for connected sockets). | |
2724 | * These restrictions allow us to pass only a tiny amount of | |
2725 | * data through to the completion function. | |
2726 | */ | |
2727 | EFX_WARN_ON_PARANOID(spec->flags != | |
2728 | (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); | |
2729 | EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); | |
2730 | EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); | |
2731 | ||
2732 | hash = efx_ef10_filter_hash(spec); | |
2733 | ||
2734 | spin_lock_bh(&efx->filter_lock); | |
2735 | ||
2736 | /* Find any existing filter with the same match tuple or else | |
2737 | * a free slot to insert at. If an existing filter is busy, | |
2738 | * we have to give up. | |
2739 | */ | |
2740 | for (;;) { | |
2741 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); | |
2742 | saved_spec = efx_ef10_filter_entry_spec(table, i); | |
2743 | ||
2744 | if (!saved_spec) { | |
2745 | if (ins_index < 0) | |
2746 | ins_index = i; | |
2747 | } else if (efx_ef10_filter_equal(spec, saved_spec)) { | |
2748 | if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { | |
2749 | rc = -EBUSY; | |
2750 | goto fail_unlock; | |
2751 | } | |
8127d661 BH |
2752 | if (spec->priority < saved_spec->priority) { |
2753 | rc = -EPERM; | |
2754 | goto fail_unlock; | |
2755 | } | |
2756 | ins_index = i; | |
2757 | break; | |
2758 | } | |
2759 | ||
2760 | /* Once we reach the maximum search depth, use the | |
2761 | * first suitable slot or return -EBUSY if there was | |
2762 | * none | |
2763 | */ | |
2764 | if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { | |
2765 | if (ins_index < 0) { | |
2766 | rc = -EBUSY; | |
2767 | goto fail_unlock; | |
2768 | } | |
2769 | break; | |
2770 | } | |
2771 | ||
2772 | ++depth; | |
2773 | } | |
2774 | ||
2775 | /* Create a software table entry if necessary, and mark it | |
2776 | * busy. We might yet fail to insert, but any attempt to | |
2777 | * insert a conflicting filter while we're waiting for the | |
2778 | * firmware must find the busy entry. | |
2779 | */ | |
2780 | saved_spec = efx_ef10_filter_entry_spec(table, ins_index); | |
2781 | if (saved_spec) { | |
2782 | replacing = true; | |
2783 | } else { | |
2784 | saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); | |
2785 | if (!saved_spec) { | |
2786 | rc = -ENOMEM; | |
2787 | goto fail_unlock; | |
2788 | } | |
2789 | *saved_spec = *spec; | |
2790 | } | |
2791 | efx_ef10_filter_set_entry(table, ins_index, saved_spec, | |
2792 | EFX_EF10_FILTER_FLAG_BUSY); | |
2793 | ||
2794 | spin_unlock_bh(&efx->filter_lock); | |
2795 | ||
2796 | /* Pack up the variables needed on completion */ | |
2797 | cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; | |
2798 | ||
2799 | efx_ef10_filter_push_prep(efx, spec, inbuf, | |
2800 | table->entry[ins_index].handle, replacing); | |
2801 | efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), | |
2802 | MC_CMD_FILTER_OP_OUT_LEN, | |
2803 | efx_ef10_filter_rfs_insert_complete, cookie); | |
2804 | ||
2805 | return ins_index; | |
2806 | ||
2807 | fail_unlock: | |
2808 | spin_unlock_bh(&efx->filter_lock); | |
2809 | return rc; | |
2810 | } | |
2811 | ||
2812 | static void | |
2813 | efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, | |
2814 | int rc, efx_dword_t *outbuf, | |
2815 | size_t outlen_actual) | |
2816 | { | |
2817 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2818 | unsigned int ins_index, dmaq_id; | |
2819 | struct efx_filter_spec *spec; | |
2820 | bool replacing; | |
2821 | ||
2822 | /* Unpack the cookie */ | |
2823 | replacing = cookie >> 31; | |
2824 | ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); | |
2825 | dmaq_id = cookie & 0xffff; | |
2826 | ||
2827 | spin_lock_bh(&efx->filter_lock); | |
2828 | spec = efx_ef10_filter_entry_spec(table, ins_index); | |
2829 | if (rc == 0) { | |
2830 | table->entry[ins_index].handle = | |
2831 | MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); | |
2832 | if (replacing) | |
2833 | spec->dmaq_id = dmaq_id; | |
2834 | } else if (!replacing) { | |
2835 | kfree(spec); | |
2836 | spec = NULL; | |
2837 | } | |
2838 | efx_ef10_filter_set_entry(table, ins_index, spec, 0); | |
2839 | spin_unlock_bh(&efx->filter_lock); | |
2840 | ||
2841 | wake_up_all(&table->waitq); | |
2842 | } | |
2843 | ||
2844 | static void | |
2845 | efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, | |
2846 | unsigned long filter_idx, | |
2847 | int rc, efx_dword_t *outbuf, | |
2848 | size_t outlen_actual); | |
2849 | ||
2850 | static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, | |
2851 | unsigned int filter_idx) | |
2852 | { | |
2853 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2854 | struct efx_filter_spec *spec = | |
2855 | efx_ef10_filter_entry_spec(table, filter_idx); | |
2856 | MCDI_DECLARE_BUF(inbuf, | |
2857 | MC_CMD_FILTER_OP_IN_HANDLE_OFST + | |
2858 | MC_CMD_FILTER_OP_IN_HANDLE_LEN); | |
2859 | ||
2860 | if (!spec || | |
2861 | (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || | |
2862 | spec->priority != EFX_FILTER_PRI_HINT || | |
2863 | !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, | |
2864 | flow_id, filter_idx)) | |
2865 | return false; | |
2866 | ||
2867 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
2868 | MC_CMD_FILTER_OP_IN_OP_REMOVE); | |
2869 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, | |
2870 | table->entry[filter_idx].handle); | |
2871 | if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, | |
2872 | efx_ef10_filter_rfs_expire_complete, filter_idx)) | |
2873 | return false; | |
2874 | ||
2875 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; | |
2876 | return true; | |
2877 | } | |
2878 | ||
2879 | static void | |
2880 | efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, | |
2881 | unsigned long filter_idx, | |
2882 | int rc, efx_dword_t *outbuf, | |
2883 | size_t outlen_actual) | |
2884 | { | |
2885 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2886 | struct efx_filter_spec *spec = | |
2887 | efx_ef10_filter_entry_spec(table, filter_idx); | |
2888 | ||
2889 | spin_lock_bh(&efx->filter_lock); | |
2890 | if (rc == 0) { | |
2891 | kfree(spec); | |
2892 | efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); | |
2893 | } | |
2894 | table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; | |
2895 | wake_up_all(&table->waitq); | |
2896 | spin_unlock_bh(&efx->filter_lock); | |
2897 | } | |
2898 | ||
2899 | #endif /* CONFIG_RFS_ACCEL */ | |
2900 | ||
2901 | static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) | |
2902 | { | |
2903 | int match_flags = 0; | |
2904 | ||
2905 | #define MAP_FLAG(gen_flag, mcdi_field) { \ | |
2906 | u32 old_mcdi_flags = mcdi_flags; \ | |
2907 | mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ | |
2908 | mcdi_field ## _LBN); \ | |
2909 | if (mcdi_flags != old_mcdi_flags) \ | |
2910 | match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ | |
2911 | } | |
2912 | MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); | |
2913 | MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); | |
2914 | MAP_FLAG(REM_HOST, SRC_IP); | |
2915 | MAP_FLAG(LOC_HOST, DST_IP); | |
2916 | MAP_FLAG(REM_MAC, SRC_MAC); | |
2917 | MAP_FLAG(REM_PORT, SRC_PORT); | |
2918 | MAP_FLAG(LOC_MAC, DST_MAC); | |
2919 | MAP_FLAG(LOC_PORT, DST_PORT); | |
2920 | MAP_FLAG(ETHER_TYPE, ETHER_TYPE); | |
2921 | MAP_FLAG(INNER_VID, INNER_VLAN); | |
2922 | MAP_FLAG(OUTER_VID, OUTER_VLAN); | |
2923 | MAP_FLAG(IP_PROTO, IP_PROTO); | |
2924 | #undef MAP_FLAG | |
2925 | ||
2926 | /* Did we map them all? */ | |
2927 | if (mcdi_flags) | |
2928 | return -EINVAL; | |
2929 | ||
2930 | return match_flags; | |
2931 | } | |
2932 | ||
2933 | static int efx_ef10_filter_table_probe(struct efx_nic *efx) | |
2934 | { | |
2935 | MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); | |
2936 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); | |
2937 | unsigned int pd_match_pri, pd_match_count; | |
2938 | struct efx_ef10_filter_table *table; | |
2939 | size_t outlen; | |
2940 | int rc; | |
2941 | ||
2942 | table = kzalloc(sizeof(*table), GFP_KERNEL); | |
2943 | if (!table) | |
2944 | return -ENOMEM; | |
2945 | ||
2946 | /* Find out which RX filter types are supported, and their priorities */ | |
2947 | MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, | |
2948 | MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); | |
2949 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, | |
2950 | inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), | |
2951 | &outlen); | |
2952 | if (rc) | |
2953 | goto fail; | |
2954 | pd_match_count = MCDI_VAR_ARRAY_LEN( | |
2955 | outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); | |
2956 | table->rx_match_count = 0; | |
2957 | ||
2958 | for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { | |
2959 | u32 mcdi_flags = | |
2960 | MCDI_ARRAY_DWORD( | |
2961 | outbuf, | |
2962 | GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, | |
2963 | pd_match_pri); | |
2964 | rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); | |
2965 | if (rc < 0) { | |
2966 | netif_dbg(efx, probe, efx->net_dev, | |
2967 | "%s: fw flags %#x pri %u not supported in driver\n", | |
2968 | __func__, mcdi_flags, pd_match_pri); | |
2969 | } else { | |
2970 | netif_dbg(efx, probe, efx->net_dev, | |
2971 | "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", | |
2972 | __func__, mcdi_flags, pd_match_pri, | |
2973 | rc, table->rx_match_count); | |
2974 | table->rx_match_flags[table->rx_match_count++] = rc; | |
2975 | } | |
2976 | } | |
2977 | ||
2978 | table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); | |
2979 | if (!table->entry) { | |
2980 | rc = -ENOMEM; | |
2981 | goto fail; | |
2982 | } | |
2983 | ||
2984 | efx->filter_state = table; | |
2985 | init_waitqueue_head(&table->waitq); | |
2986 | return 0; | |
2987 | ||
2988 | fail: | |
2989 | kfree(table); | |
2990 | return rc; | |
2991 | } | |
2992 | ||
2993 | static void efx_ef10_filter_table_restore(struct efx_nic *efx) | |
2994 | { | |
2995 | struct efx_ef10_filter_table *table = efx->filter_state; | |
2996 | struct efx_ef10_nic_data *nic_data = efx->nic_data; | |
2997 | struct efx_filter_spec *spec; | |
2998 | unsigned int filter_idx; | |
2999 | bool failed = false; | |
3000 | int rc; | |
3001 | ||
3002 | if (!nic_data->must_restore_filters) | |
3003 | return; | |
3004 | ||
3005 | spin_lock_bh(&efx->filter_lock); | |
3006 | ||
3007 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { | |
3008 | spec = efx_ef10_filter_entry_spec(table, filter_idx); | |
3009 | if (!spec) | |
3010 | continue; | |
3011 | ||
3012 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; | |
3013 | spin_unlock_bh(&efx->filter_lock); | |
3014 | ||
3015 | rc = efx_ef10_filter_push(efx, spec, | |
3016 | &table->entry[filter_idx].handle, | |
3017 | false); | |
3018 | if (rc) | |
3019 | failed = true; | |
3020 | ||
3021 | spin_lock_bh(&efx->filter_lock); | |
3022 | if (rc) { | |
3023 | kfree(spec); | |
3024 | efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); | |
3025 | } else { | |
3026 | table->entry[filter_idx].spec &= | |
3027 | ~EFX_EF10_FILTER_FLAG_BUSY; | |
3028 | } | |
3029 | } | |
3030 | ||
3031 | spin_unlock_bh(&efx->filter_lock); | |
3032 | ||
3033 | if (failed) | |
3034 | netif_err(efx, hw, efx->net_dev, | |
3035 | "unable to restore all filters\n"); | |
3036 | else | |
3037 | nic_data->must_restore_filters = false; | |
3038 | } | |
3039 | ||
3040 | static void efx_ef10_filter_table_remove(struct efx_nic *efx) | |
3041 | { | |
3042 | struct efx_ef10_filter_table *table = efx->filter_state; | |
3043 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); | |
3044 | struct efx_filter_spec *spec; | |
3045 | unsigned int filter_idx; | |
3046 | int rc; | |
3047 | ||
3048 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { | |
3049 | spec = efx_ef10_filter_entry_spec(table, filter_idx); | |
3050 | if (!spec) | |
3051 | continue; | |
3052 | ||
3053 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, | |
3054 | efx_ef10_filter_is_exclusive(spec) ? | |
3055 | MC_CMD_FILTER_OP_IN_OP_REMOVE : | |
3056 | MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); | |
3057 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, | |
3058 | table->entry[filter_idx].handle); | |
3059 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), | |
3060 | NULL, 0, NULL); | |
48ce5634 BH |
3061 | if (rc) |
3062 | netdev_WARN(efx->net_dev, | |
3063 | "filter_idx=%#x handle=%#llx\n", | |
3064 | filter_idx, | |
3065 | table->entry[filter_idx].handle); | |
8127d661 BH |
3066 | kfree(spec); |
3067 | } | |
3068 | ||
3069 | vfree(table->entry); | |
3070 | kfree(table); | |
3071 | } | |
3072 | ||
3073 | static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) | |
3074 | { | |
3075 | struct efx_ef10_filter_table *table = efx->filter_state; | |
3076 | struct net_device *net_dev = efx->net_dev; | |
3077 | struct efx_filter_spec spec; | |
3078 | bool remove_failed = false; | |
3079 | struct netdev_hw_addr *uc; | |
3080 | struct netdev_hw_addr *mc; | |
3081 | unsigned int filter_idx; | |
3082 | int i, n, rc; | |
3083 | ||
3084 | if (!efx_dev_registered(efx)) | |
3085 | return; | |
3086 | ||
3087 | /* Mark old filters that may need to be removed */ | |
3088 | spin_lock_bh(&efx->filter_lock); | |
b59e6ef8 | 3089 | n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count; |
8127d661 | 3090 | for (i = 0; i < n; i++) { |
b59e6ef8 BH |
3091 | filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS; |
3092 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; | |
8127d661 | 3093 | } |
b59e6ef8 | 3094 | n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count; |
8127d661 | 3095 | for (i = 0; i < n; i++) { |
b59e6ef8 BH |
3096 | filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS; |
3097 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; | |
8127d661 BH |
3098 | } |
3099 | spin_unlock_bh(&efx->filter_lock); | |
3100 | ||
3101 | /* Copy/convert the address lists; add the primary station | |
3102 | * address and broadcast address | |
3103 | */ | |
3104 | netif_addr_lock_bh(net_dev); | |
3105 | if (net_dev->flags & IFF_PROMISC || | |
b59e6ef8 BH |
3106 | netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) { |
3107 | table->dev_uc_count = -1; | |
8127d661 | 3108 | } else { |
b59e6ef8 BH |
3109 | table->dev_uc_count = 1 + netdev_uc_count(net_dev); |
3110 | memcpy(table->dev_uc_list[0].addr, net_dev->dev_addr, | |
8127d661 BH |
3111 | ETH_ALEN); |
3112 | i = 1; | |
3113 | netdev_for_each_uc_addr(uc, net_dev) { | |
b59e6ef8 | 3114 | memcpy(table->dev_uc_list[i].addr, |
8127d661 BH |
3115 | uc->addr, ETH_ALEN); |
3116 | i++; | |
3117 | } | |
3118 | } | |
3119 | if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) || | |
b59e6ef8 BH |
3120 | netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) { |
3121 | table->dev_mc_count = -1; | |
8127d661 | 3122 | } else { |
b59e6ef8 BH |
3123 | table->dev_mc_count = 1 + netdev_mc_count(net_dev); |
3124 | eth_broadcast_addr(table->dev_mc_list[0].addr); | |
8127d661 BH |
3125 | i = 1; |
3126 | netdev_for_each_mc_addr(mc, net_dev) { | |
b59e6ef8 | 3127 | memcpy(table->dev_mc_list[i].addr, |
8127d661 BH |
3128 | mc->addr, ETH_ALEN); |
3129 | i++; | |
3130 | } | |
3131 | } | |
3132 | netif_addr_unlock_bh(net_dev); | |
3133 | ||
3134 | /* Insert/renew unicast filters */ | |
b59e6ef8 BH |
3135 | if (table->dev_uc_count >= 0) { |
3136 | for (i = 0; i < table->dev_uc_count; i++) { | |
7665d1ab BH |
3137 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
3138 | EFX_FILTER_FLAG_RX_RSS, | |
8127d661 BH |
3139 | 0); |
3140 | efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, | |
b59e6ef8 | 3141 | table->dev_uc_list[i].addr); |
8127d661 BH |
3142 | rc = efx_ef10_filter_insert(efx, &spec, true); |
3143 | if (rc < 0) { | |
3144 | /* Fall back to unicast-promisc */ | |
3145 | while (i--) | |
3146 | efx_ef10_filter_remove_safe( | |
7665d1ab | 3147 | efx, EFX_FILTER_PRI_AUTO, |
b59e6ef8 BH |
3148 | table->dev_uc_list[i].id); |
3149 | table->dev_uc_count = -1; | |
8127d661 BH |
3150 | break; |
3151 | } | |
b59e6ef8 | 3152 | table->dev_uc_list[i].id = rc; |
8127d661 BH |
3153 | } |
3154 | } | |
b59e6ef8 | 3155 | if (table->dev_uc_count < 0) { |
7665d1ab BH |
3156 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
3157 | EFX_FILTER_FLAG_RX_RSS, | |
8127d661 BH |
3158 | 0); |
3159 | efx_filter_set_uc_def(&spec); | |
3160 | rc = efx_ef10_filter_insert(efx, &spec, true); | |
3161 | if (rc < 0) { | |
3162 | WARN_ON(1); | |
b59e6ef8 | 3163 | table->dev_uc_count = 0; |
8127d661 | 3164 | } else { |
b59e6ef8 | 3165 | table->dev_uc_list[0].id = rc; |
8127d661 BH |
3166 | } |
3167 | } | |
3168 | ||
3169 | /* Insert/renew multicast filters */ | |
b59e6ef8 BH |
3170 | if (table->dev_mc_count >= 0) { |
3171 | for (i = 0; i < table->dev_mc_count; i++) { | |
7665d1ab BH |
3172 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
3173 | EFX_FILTER_FLAG_RX_RSS, | |
8127d661 BH |
3174 | 0); |
3175 | efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, | |
b59e6ef8 | 3176 | table->dev_mc_list[i].addr); |
8127d661 BH |
3177 | rc = efx_ef10_filter_insert(efx, &spec, true); |
3178 | if (rc < 0) { | |
3179 | /* Fall back to multicast-promisc */ | |
3180 | while (i--) | |
3181 | efx_ef10_filter_remove_safe( | |
7665d1ab | 3182 | efx, EFX_FILTER_PRI_AUTO, |
b59e6ef8 BH |
3183 | table->dev_mc_list[i].id); |
3184 | table->dev_mc_count = -1; | |
8127d661 BH |
3185 | break; |
3186 | } | |
b59e6ef8 | 3187 | table->dev_mc_list[i].id = rc; |
8127d661 BH |
3188 | } |
3189 | } | |
b59e6ef8 | 3190 | if (table->dev_mc_count < 0) { |
7665d1ab BH |
3191 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
3192 | EFX_FILTER_FLAG_RX_RSS, | |
8127d661 BH |
3193 | 0); |
3194 | efx_filter_set_mc_def(&spec); | |
3195 | rc = efx_ef10_filter_insert(efx, &spec, true); | |
3196 | if (rc < 0) { | |
3197 | WARN_ON(1); | |
b59e6ef8 | 3198 | table->dev_mc_count = 0; |
8127d661 | 3199 | } else { |
b59e6ef8 | 3200 | table->dev_mc_list[0].id = rc; |
8127d661 BH |
3201 | } |
3202 | } | |
3203 | ||
3204 | /* Remove filters that weren't renewed. Since nothing else | |
b59e6ef8 | 3205 | * changes the AUTO_OLD flag or removes these filters, we |
8127d661 BH |
3206 | * don't need to hold the filter_lock while scanning for |
3207 | * these filters. | |
3208 | */ | |
3209 | for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { | |
3210 | if (ACCESS_ONCE(table->entry[i].spec) & | |
b59e6ef8 | 3211 | EFX_EF10_FILTER_FLAG_AUTO_OLD) { |
7665d1ab BH |
3212 | if (efx_ef10_filter_remove_internal( |
3213 | efx, EFX_FILTER_PRI_AUTO, i, true) < 0) | |
8127d661 BH |
3214 | remove_failed = true; |
3215 | } | |
3216 | } | |
3217 | WARN_ON(remove_failed); | |
3218 | } | |
3219 | ||
3220 | static int efx_ef10_mac_reconfigure(struct efx_nic *efx) | |
3221 | { | |
3222 | efx_ef10_filter_sync_rx_mode(efx); | |
3223 | ||
3224 | return efx_mcdi_set_mac(efx); | |
3225 | } | |
3226 | ||
74cd60a4 JC |
3227 | static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) |
3228 | { | |
3229 | MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); | |
3230 | ||
3231 | MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); | |
3232 | return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), | |
3233 | NULL, 0, NULL); | |
3234 | } | |
3235 | ||
3236 | /* MC BISTs follow a different poll mechanism to phy BISTs. | |
3237 | * The BIST is done in the poll handler on the MC, and the MCDI command | |
3238 | * will block until the BIST is done. | |
3239 | */ | |
3240 | static int efx_ef10_poll_bist(struct efx_nic *efx) | |
3241 | { | |
3242 | int rc; | |
3243 | MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); | |
3244 | size_t outlen; | |
3245 | u32 result; | |
3246 | ||
3247 | rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, | |
3248 | outbuf, sizeof(outbuf), &outlen); | |
3249 | if (rc != 0) | |
3250 | return rc; | |
3251 | ||
3252 | if (outlen < MC_CMD_POLL_BIST_OUT_LEN) | |
3253 | return -EIO; | |
3254 | ||
3255 | result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); | |
3256 | switch (result) { | |
3257 | case MC_CMD_POLL_BIST_PASSED: | |
3258 | netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); | |
3259 | return 0; | |
3260 | case MC_CMD_POLL_BIST_TIMEOUT: | |
3261 | netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); | |
3262 | return -EIO; | |
3263 | case MC_CMD_POLL_BIST_FAILED: | |
3264 | netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); | |
3265 | return -EIO; | |
3266 | default: | |
3267 | netif_err(efx, hw, efx->net_dev, | |
3268 | "BIST returned unknown result %u", result); | |
3269 | return -EIO; | |
3270 | } | |
3271 | } | |
3272 | ||
3273 | static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) | |
3274 | { | |
3275 | int rc; | |
3276 | ||
3277 | netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); | |
3278 | ||
3279 | rc = efx_ef10_start_bist(efx, bist_type); | |
3280 | if (rc != 0) | |
3281 | return rc; | |
3282 | ||
3283 | return efx_ef10_poll_bist(efx); | |
3284 | } | |
3285 | ||
3286 | static int | |
3287 | efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) | |
3288 | { | |
3289 | int rc, rc2; | |
3290 | ||
3291 | efx_reset_down(efx, RESET_TYPE_WORLD); | |
3292 | ||
3293 | rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, | |
3294 | NULL, 0, NULL, 0, NULL); | |
3295 | if (rc != 0) | |
3296 | goto out; | |
3297 | ||
3298 | tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; | |
3299 | tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; | |
3300 | ||
3301 | rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); | |
3302 | ||
3303 | out: | |
3304 | rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); | |
3305 | return rc ? rc : rc2; | |
3306 | } | |
3307 | ||
8127d661 BH |
3308 | #ifdef CONFIG_SFC_MTD |
3309 | ||
3310 | struct efx_ef10_nvram_type_info { | |
3311 | u16 type, type_mask; | |
3312 | u8 port; | |
3313 | const char *name; | |
3314 | }; | |
3315 | ||
3316 | static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { | |
3317 | { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, | |
3318 | { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, | |
3319 | { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, | |
3320 | { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, | |
3321 | { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, | |
3322 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, | |
3323 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, | |
3324 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, | |
3325 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, | |
a84f3bf9 | 3326 | { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, |
8127d661 BH |
3327 | { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, |
3328 | }; | |
3329 | ||
3330 | static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, | |
3331 | struct efx_mcdi_mtd_partition *part, | |
3332 | unsigned int type) | |
3333 | { | |
3334 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); | |
3335 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); | |
3336 | const struct efx_ef10_nvram_type_info *info; | |
3337 | size_t size, erase_size, outlen; | |
3338 | bool protected; | |
3339 | int rc; | |
3340 | ||
3341 | for (info = efx_ef10_nvram_types; ; info++) { | |
3342 | if (info == | |
3343 | efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) | |
3344 | return -ENODEV; | |
3345 | if ((type & ~info->type_mask) == info->type) | |
3346 | break; | |
3347 | } | |
3348 | if (info->port != efx_port_num(efx)) | |
3349 | return -ENODEV; | |
3350 | ||
3351 | rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); | |
3352 | if (rc) | |
3353 | return rc; | |
3354 | if (protected) | |
3355 | return -ENODEV; /* hide it */ | |
3356 | ||
3357 | part->nvram_type = type; | |
3358 | ||
3359 | MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); | |
3360 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), | |
3361 | outbuf, sizeof(outbuf), &outlen); | |
3362 | if (rc) | |
3363 | return rc; | |
3364 | if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) | |
3365 | return -EIO; | |
3366 | if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & | |
3367 | (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) | |
3368 | part->fw_subtype = MCDI_DWORD(outbuf, | |
3369 | NVRAM_METADATA_OUT_SUBTYPE); | |
3370 | ||
3371 | part->common.dev_type_name = "EF10 NVRAM manager"; | |
3372 | part->common.type_name = info->name; | |
3373 | ||
3374 | part->common.mtd.type = MTD_NORFLASH; | |
3375 | part->common.mtd.flags = MTD_CAP_NORFLASH; | |
3376 | part->common.mtd.size = size; | |
3377 | part->common.mtd.erasesize = erase_size; | |
3378 | ||
3379 | return 0; | |
3380 | } | |
3381 | ||
3382 | static int efx_ef10_mtd_probe(struct efx_nic *efx) | |
3383 | { | |
3384 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); | |
3385 | struct efx_mcdi_mtd_partition *parts; | |
3386 | size_t outlen, n_parts_total, i, n_parts; | |
3387 | unsigned int type; | |
3388 | int rc; | |
3389 | ||
3390 | ASSERT_RTNL(); | |
3391 | ||
3392 | BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); | |
3393 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, | |
3394 | outbuf, sizeof(outbuf), &outlen); | |
3395 | if (rc) | |
3396 | return rc; | |
3397 | if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) | |
3398 | return -EIO; | |
3399 | ||
3400 | n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); | |
3401 | if (n_parts_total > | |
3402 | MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) | |
3403 | return -EIO; | |
3404 | ||
3405 | parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); | |
3406 | if (!parts) | |
3407 | return -ENOMEM; | |
3408 | ||
3409 | n_parts = 0; | |
3410 | for (i = 0; i < n_parts_total; i++) { | |
3411 | type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, | |
3412 | i); | |
3413 | rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); | |
3414 | if (rc == 0) | |
3415 | n_parts++; | |
3416 | else if (rc != -ENODEV) | |
3417 | goto fail; | |
3418 | } | |
3419 | ||
3420 | rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); | |
3421 | fail: | |
3422 | if (rc) | |
3423 | kfree(parts); | |
3424 | return rc; | |
3425 | } | |
3426 | ||
3427 | #endif /* CONFIG_SFC_MTD */ | |
3428 | ||
3429 | static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) | |
3430 | { | |
3431 | _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); | |
3432 | } | |
3433 | ||
bd9a265d JC |
3434 | static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, |
3435 | bool temp) | |
3436 | { | |
3437 | MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); | |
3438 | int rc; | |
3439 | ||
3440 | if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || | |
3441 | channel->sync_events_state == SYNC_EVENTS_VALID || | |
3442 | (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) | |
3443 | return 0; | |
3444 | channel->sync_events_state = SYNC_EVENTS_REQUESTED; | |
3445 | ||
3446 | MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); | |
3447 | MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); | |
3448 | MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, | |
3449 | channel->channel); | |
3450 | ||
3451 | rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, | |
3452 | inbuf, sizeof(inbuf), NULL, 0, NULL); | |
3453 | ||
3454 | if (rc != 0) | |
3455 | channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : | |
3456 | SYNC_EVENTS_DISABLED; | |
3457 | ||
3458 | return rc; | |
3459 | } | |
3460 | ||
3461 | static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, | |
3462 | bool temp) | |
3463 | { | |
3464 | MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); | |
3465 | int rc; | |
3466 | ||
3467 | if (channel->sync_events_state == SYNC_EVENTS_DISABLED || | |
3468 | (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) | |
3469 | return 0; | |
3470 | if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { | |
3471 | channel->sync_events_state = SYNC_EVENTS_DISABLED; | |
3472 | return 0; | |
3473 | } | |
3474 | channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : | |
3475 | SYNC_EVENTS_DISABLED; | |
3476 | ||
3477 | MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); | |
3478 | MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); | |
3479 | MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, | |
3480 | MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); | |
3481 | MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, | |
3482 | channel->channel); | |
3483 | ||
3484 | rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, | |
3485 | inbuf, sizeof(inbuf), NULL, 0, NULL); | |
3486 | ||
3487 | return rc; | |
3488 | } | |
3489 | ||
3490 | static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, | |
3491 | bool temp) | |
3492 | { | |
3493 | int (*set)(struct efx_channel *channel, bool temp); | |
3494 | struct efx_channel *channel; | |
3495 | ||
3496 | set = en ? | |
3497 | efx_ef10_rx_enable_timestamping : | |
3498 | efx_ef10_rx_disable_timestamping; | |
3499 | ||
3500 | efx_for_each_channel(channel, efx) { | |
3501 | int rc = set(channel, temp); | |
3502 | if (en && rc != 0) { | |
3503 | efx_ef10_ptp_set_ts_sync_events(efx, false, temp); | |
3504 | return rc; | |
3505 | } | |
3506 | } | |
3507 | ||
3508 | return 0; | |
3509 | } | |
3510 | ||
3511 | static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, | |
3512 | struct hwtstamp_config *init) | |
3513 | { | |
3514 | int rc; | |
3515 | ||
3516 | switch (init->rx_filter) { | |
3517 | case HWTSTAMP_FILTER_NONE: | |
3518 | efx_ef10_ptp_set_ts_sync_events(efx, false, false); | |
3519 | /* if TX timestamping is still requested then leave PTP on */ | |
3520 | return efx_ptp_change_mode(efx, | |
3521 | init->tx_type != HWTSTAMP_TX_OFF, 0); | |
3522 | case HWTSTAMP_FILTER_ALL: | |
3523 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
3524 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
3525 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
3526 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
3527 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3528 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
3529 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
3530 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
3531 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
3532 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
3533 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
3534 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
3535 | init->rx_filter = HWTSTAMP_FILTER_ALL; | |
3536 | rc = efx_ptp_change_mode(efx, true, 0); | |
3537 | if (!rc) | |
3538 | rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); | |
3539 | if (rc) | |
3540 | efx_ptp_change_mode(efx, false, 0); | |
3541 | return rc; | |
3542 | default: | |
3543 | return -ERANGE; | |
3544 | } | |
3545 | } | |
3546 | ||
8127d661 BH |
3547 | const struct efx_nic_type efx_hunt_a0_nic_type = { |
3548 | .mem_map_size = efx_ef10_mem_map_size, | |
3549 | .probe = efx_ef10_probe, | |
3550 | .remove = efx_ef10_remove, | |
3551 | .dimension_resources = efx_ef10_dimension_resources, | |
3552 | .init = efx_ef10_init_nic, | |
3553 | .fini = efx_port_dummy_op_void, | |
3554 | .map_reset_reason = efx_mcdi_map_reset_reason, | |
3555 | .map_reset_flags = efx_ef10_map_reset_flags, | |
3556 | .reset = efx_mcdi_reset, | |
3557 | .probe_port = efx_mcdi_port_probe, | |
3558 | .remove_port = efx_mcdi_port_remove, | |
3559 | .fini_dmaq = efx_ef10_fini_dmaq, | |
3560 | .describe_stats = efx_ef10_describe_stats, | |
3561 | .update_stats = efx_ef10_update_stats, | |
3562 | .start_stats = efx_mcdi_mac_start_stats, | |
f8f3b5ae | 3563 | .pull_stats = efx_mcdi_mac_pull_stats, |
8127d661 BH |
3564 | .stop_stats = efx_mcdi_mac_stop_stats, |
3565 | .set_id_led = efx_mcdi_set_id_led, | |
3566 | .push_irq_moderation = efx_ef10_push_irq_moderation, | |
3567 | .reconfigure_mac = efx_ef10_mac_reconfigure, | |
3568 | .check_mac_fault = efx_mcdi_mac_check_fault, | |
3569 | .reconfigure_port = efx_mcdi_port_reconfigure, | |
3570 | .get_wol = efx_ef10_get_wol, | |
3571 | .set_wol = efx_ef10_set_wol, | |
3572 | .resume_wol = efx_port_dummy_op_void, | |
74cd60a4 | 3573 | .test_chip = efx_ef10_test_chip, |
8127d661 BH |
3574 | .test_nvram = efx_mcdi_nvram_test_all, |
3575 | .mcdi_request = efx_ef10_mcdi_request, | |
3576 | .mcdi_poll_response = efx_ef10_mcdi_poll_response, | |
3577 | .mcdi_read_response = efx_ef10_mcdi_read_response, | |
3578 | .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, | |
3579 | .irq_enable_master = efx_port_dummy_op_void, | |
3580 | .irq_test_generate = efx_ef10_irq_test_generate, | |
3581 | .irq_disable_non_ev = efx_port_dummy_op_void, | |
3582 | .irq_handle_msi = efx_ef10_msi_interrupt, | |
3583 | .irq_handle_legacy = efx_ef10_legacy_interrupt, | |
3584 | .tx_probe = efx_ef10_tx_probe, | |
3585 | .tx_init = efx_ef10_tx_init, | |
3586 | .tx_remove = efx_ef10_tx_remove, | |
3587 | .tx_write = efx_ef10_tx_write, | |
d43050c0 | 3588 | .rx_push_rss_config = efx_ef10_rx_push_rss_config, |
8127d661 BH |
3589 | .rx_probe = efx_ef10_rx_probe, |
3590 | .rx_init = efx_ef10_rx_init, | |
3591 | .rx_remove = efx_ef10_rx_remove, | |
3592 | .rx_write = efx_ef10_rx_write, | |
3593 | .rx_defer_refill = efx_ef10_rx_defer_refill, | |
3594 | .ev_probe = efx_ef10_ev_probe, | |
3595 | .ev_init = efx_ef10_ev_init, | |
3596 | .ev_fini = efx_ef10_ev_fini, | |
3597 | .ev_remove = efx_ef10_ev_remove, | |
3598 | .ev_process = efx_ef10_ev_process, | |
3599 | .ev_read_ack = efx_ef10_ev_read_ack, | |
3600 | .ev_test_generate = efx_ef10_ev_test_generate, | |
3601 | .filter_table_probe = efx_ef10_filter_table_probe, | |
3602 | .filter_table_restore = efx_ef10_filter_table_restore, | |
3603 | .filter_table_remove = efx_ef10_filter_table_remove, | |
3604 | .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, | |
3605 | .filter_insert = efx_ef10_filter_insert, | |
3606 | .filter_remove_safe = efx_ef10_filter_remove_safe, | |
3607 | .filter_get_safe = efx_ef10_filter_get_safe, | |
3608 | .filter_clear_rx = efx_ef10_filter_clear_rx, | |
3609 | .filter_count_rx_used = efx_ef10_filter_count_rx_used, | |
3610 | .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, | |
3611 | .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, | |
3612 | #ifdef CONFIG_RFS_ACCEL | |
3613 | .filter_rfs_insert = efx_ef10_filter_rfs_insert, | |
3614 | .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, | |
3615 | #endif | |
3616 | #ifdef CONFIG_SFC_MTD | |
3617 | .mtd_probe = efx_ef10_mtd_probe, | |
3618 | .mtd_rename = efx_mcdi_mtd_rename, | |
3619 | .mtd_read = efx_mcdi_mtd_read, | |
3620 | .mtd_erase = efx_mcdi_mtd_erase, | |
3621 | .mtd_write = efx_mcdi_mtd_write, | |
3622 | .mtd_sync = efx_mcdi_mtd_sync, | |
3623 | #endif | |
3624 | .ptp_write_host_time = efx_ef10_ptp_write_host_time, | |
bd9a265d JC |
3625 | .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, |
3626 | .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, | |
8127d661 BH |
3627 | |
3628 | .revision = EFX_REV_HUNT_A0, | |
3629 | .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), | |
3630 | .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, | |
3631 | .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, | |
bd9a265d | 3632 | .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, |
8127d661 BH |
3633 | .can_rx_scatter = true, |
3634 | .always_rx_scatter = true, | |
3635 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
3636 | .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, | |
3637 | .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
3638 | NETIF_F_RXHASH | NETIF_F_NTUPLE), | |
3639 | .mcdi_max_ver = 2, | |
3640 | .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, | |
bd9a265d JC |
3641 | .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | |
3642 | 1 << HWTSTAMP_FILTER_ALL, | |
8127d661 | 3643 | }; |