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uapi: export ila.h
[deliverable/linux.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
822b96f8
DP		 53struct efx_ef10_dev_addr {
54 u8 addr[ETH_ALEN];
55 u16 id;
56};
57
8127d661
BH		 58struct efx_ef10_filter_table {
59/* The RX match field masks supported by this fw & hw, in order of priority */
60 enum efx_filter_match_flags rx_match_flags[
61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
62 unsigned int rx_match_count;
63
64 struct {
65 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 66/* BUSY flag indicates that an update is in progress. AUTO_OLD is
67 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 68 */
69#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 70#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 71#define EFX_EF10_FILTER_FLAGS 3UL
72 u64 handle; /* firmware handle */
73 } *entry;
74 wait_queue_head_t waitq;
75/* Shadow of net_device address lists, guarded by mac_lock */
b59e6ef8
BH		 76#define EFX_EF10_FILTER_DEV_UC_MAX 32
77#define EFX_EF10_FILTER_DEV_MC_MAX 256
822b96f8
DP		 78 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
79 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 80 int dev_uc_count;
81 int dev_mc_count;
82/* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */
83 u16 ucdef_id;
84 u16 bcast_id;
85 u16 mcdef_id;
8127d661
BH		 86};
87
88/* An arbitrary search limit for the software hash table */
89#define EFX_EF10_FILTER_SEARCH_LIMIT 200
90
8127d661
BH		 91static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
92static void efx_ef10_filter_table_remove(struct efx_nic *efx);
93
94static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
95{
96 efx_dword_t reg;
97
98 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
99 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
100 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
101}
102
103static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
104{
02246a7f
SS		 105 int bar;
106
107 bar = efx->type->mem_bar;
108 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 109}
110
7a186f47
DP		 111static bool efx_ef10_is_vf(struct efx_nic *efx)
112{
113 return efx->type->is_vf;
114}
115
1cd9ecbb
DP		 116static int efx_ef10_get_pf_index(struct efx_nic *efx)
117{
118 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
119 struct efx_ef10_nic_data *nic_data = efx->nic_data;
120 size_t outlen;
121 int rc;
122
123 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
124 sizeof(outbuf), &outlen);
125 if (rc)
126 return rc;
127 if (outlen < sizeof(outbuf))
128 return -EIO;
129
130 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
131 return 0;
132}
133
88a37de6
SS		 134#ifdef CONFIG_SFC_SRIOV
135static int efx_ef10_get_vf_index(struct efx_nic *efx)
136{
137 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
138 struct efx_ef10_nic_data *nic_data = efx->nic_data;
139 size_t outlen;
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
143 sizeof(outbuf), &outlen);
144 if (rc)
145 return rc;
146 if (outlen < sizeof(outbuf))
147 return -EIO;
148
149 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
150 return 0;
151}
152#endif
153
e5a2538a 154static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661
BH		 155{
156 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
157 struct efx_ef10_nic_data *nic_data = efx->nic_data;
158 size_t outlen;
159 int rc;
160
161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
162
163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
164 outbuf, sizeof(outbuf), &outlen);
165 if (rc)
166 return rc;
e5a2538a
BH		 167 if (outlen < sizeof(outbuf)) {
168 netif_err(efx, drv, efx->net_dev,
169 "unable to read datapath firmware capabilities\n");
170 return -EIO;
171 }
172
173 nic_data->datapath_caps =
174 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 175
8d9f9dd4
DP		 176 /* record the DPCPU firmware IDs to determine VEB vswitching support.
177 */
178 nic_data->rx_dpcpu_fw_id =
179 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
180 nic_data->tx_dpcpu_fw_id =
181 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
182
e5a2538a
BH		 183 if (!(nic_data->datapath_caps &
184 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
185 netif_err(efx, drv, efx->net_dev,
186 "current firmware does not support TSO\n");
187 return -ENODEV;
188 }
189
190 if (!(nic_data->datapath_caps &
191 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
192 netif_err(efx, probe, efx->net_dev,
193 "current firmware does not support an RX prefix\n");
194 return -ENODEV;
8127d661
BH		 195 }
196
197 return 0;
198}
199
200static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
201{
202 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
203 int rc;
204
205 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
206 outbuf, sizeof(outbuf), NULL);
207 if (rc)
208 return rc;
209 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
210 return rc > 0 ? rc : -ERANGE;
211}
212
0d5e0fbb 213static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 214{
215 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
216 size_t outlen;
217 int rc;
218
219 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
220
221 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
222 outbuf, sizeof(outbuf), &outlen);
223 if (rc)
224 return rc;
225 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
226 return -EIO;
227
cd84ff4d
EC		 228 ether_addr_copy(mac_address,
229 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 230 return 0;
231}
232
0d5e0fbb
DP		 233static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
234{
235 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
236 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
237 size_t outlen;
238 int num_addrs, rc;
239
240 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
241 EVB_PORT_ID_ASSIGNED);
242 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
243 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
244
245 if (rc)
246 return rc;
247 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
248 return -EIO;
249
250 num_addrs = MCDI_DWORD(outbuf,
251 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
252
253 WARN_ON(num_addrs != 1);
254
255 ether_addr_copy(mac_address,
256 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
257
258 return 0;
259}
260
0f5c0845
SS		 261static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
262 struct device_attribute *attr,
263 char *buf)
264{
265 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
266
267 return sprintf(buf, "%d\n",
268 ((efx->mcdi->fn_flags) &
269 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
270 ? 1 : 0);
271}
272
273static ssize_t efx_ef10_show_primary_flag(struct device *dev,
274 struct device_attribute *attr,
275 char *buf)
276{
277 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
278
279 return sprintf(buf, "%d\n",
280 ((efx->mcdi->fn_flags) &
281 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
282 ? 1 : 0);
283}
284
285static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
286 NULL);
287static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
288
8127d661
BH		 289static int efx_ef10_probe(struct efx_nic *efx)
290{
291 struct efx_ef10_nic_data *nic_data;
8be41320 292 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 293 int i, rc;
294
aa3930ee
BH		 295 /* We can have one VI for each 8K region. However, until we
296 * use TX option descriptors we need two TX queues per channel.
8127d661 297 */
b0fbdae1
SS		 298 efx->max_channels = min_t(unsigned int,
299 EFX_MAX_CHANNELS,
300 efx_ef10_mem_map_size(efx) /
301 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
302 efx->max_tx_channels = efx->max_channels;
9fd3d3a4
EC		 303 if (WARN_ON(efx->max_channels == 0))
304 return -EIO;
8127d661
BH		 305
306 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
307 if (!nic_data)
308 return -ENOMEM;
309 efx->nic_data = nic_data;
310
75aba2a5
EC		 311 /* we assume later that we can copy from this buffer in dwords */
312 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
313
8127d661
BH		 314 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
315 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
316 if (rc)
317 goto fail1;
318
319 /* Get the MC's warm boot count. In case it's rebooting right
320 * now, be prepared to retry.
321 */
322 i = 0;
323 for (;;) {
324 rc = efx_ef10_get_warm_boot_count(efx);
325 if (rc >= 0)
326 break;
327 if (++i == 5)
328 goto fail2;
329 ssleep(1);
330 }
331 nic_data->warm_boot_count = rc;
332
333 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
334
45b2449e
DP		 335 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
336
8127d661
BH		 337 /* In case we're recovering from a crash (kexec), we want to
338 * cancel any outstanding request by the previous user of this
339 * function. We send a special message using the least
340 * significant bits of the 'high' (doorbell) register.
341 */
342 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
343
344 rc = efx_mcdi_init(efx);
345 if (rc)
346 goto fail2;
347
348 /* Reset (most) configuration for this function */
349 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
350 if (rc)
351 goto fail3;
352
353 /* Enable event logging */
354 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
355 if (rc)
356 goto fail3;
357
0f5c0845
SS		 358 rc = device_create_file(&efx->pci_dev->dev,
359 &dev_attr_link_control_flag);
1cd9ecbb
DP		 360 if (rc)
361 goto fail3;
362
0f5c0845
SS		 363 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
364 if (rc)
365 goto fail4;
366
367 rc = efx_ef10_get_pf_index(efx);
368 if (rc)
369 goto fail5;
370
e5a2538a 371 rc = efx_ef10_init_datapath_caps(efx);
8127d661 372 if (rc < 0)
0f5c0845 373 goto fail5;
8127d661
BH		 374
375 efx->rx_packet_len_offset =
376 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
377
8127d661
BH		 378 rc = efx_mcdi_port_get_number(efx);
379 if (rc < 0)
0f5c0845 380 goto fail5;
8127d661 381 efx->port_num = rc;
8be41320 382 net_dev->dev_port = rc;
8127d661 383
0d5e0fbb 384 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 385 if (rc)
0f5c0845 386 goto fail5;
8127d661
BH		 387
388 rc = efx_ef10_get_sysclk_freq(efx);
389 if (rc < 0)
0f5c0845 390 goto fail5;
8127d661
BH		 391 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
392
267d9d73
EC		 393 /* Check whether firmware supports bug 35388 workaround.
394 * First try to enable it, then if we get EPERM, just
395 * ask if it's already enabled
396 */
34ccfe6f 397 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
c9012e00 398 if (rc == 0) {
8127d661 399 nic_data->workaround_35388 = true;
c9012e00 400 } else if (rc == -EPERM) {
267d9d73
EC		 401 unsigned int enabled;
402
403 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
404 if (rc)
405 goto fail3;
406 nic_data->workaround_35388 = enabled &
407 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
c9012e00 408 } else if (rc != -ENOSYS && rc != -ENOENT) {
0f5c0845 409 goto fail5;
c9012e00 410 }
8127d661
BH		 411 netif_dbg(efx, probe, efx->net_dev,
412 "workaround for bug 35388 is %sabled\n",
413 nic_data->workaround_35388 ? "en" : "dis");
414
415 rc = efx_mcdi_mon_probe(efx);
267d9d73 416 if (rc && rc != -EPERM)
0f5c0845 417 goto fail5;
8127d661 418
9aecda95
BH		 419 efx_ptp_probe(efx, NULL);
420
1d051e00
SS		 421#ifdef CONFIG_SFC_SRIOV
422 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
423 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
424 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
425
426 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
427 } else
428#endif
429 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
430
8127d661
BH		 431 return 0;
432
0f5c0845
SS		 433fail5:
434 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
435fail4:
436 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661
BH		 437fail3:
438 efx_mcdi_fini(efx);
439fail2:
440 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
441fail1:
442 kfree(nic_data);
443 efx->nic_data = NULL;
444 return rc;
445}
446
447static int efx_ef10_free_vis(struct efx_nic *efx)
448{
aa09a3da 449 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 450 size_t outlen;
451 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
452 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 453
454 /* -EALREADY means nothing to free, so ignore */
455 if (rc == -EALREADY)
456 rc = 0;
1e0b8120
EC		 457 if (rc)
458 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
459 rc);
8127d661
BH		 460 return rc;
461}
462
183233be
BH		 463#ifdef EFX_USE_PIO
464
465static void efx_ef10_free_piobufs(struct efx_nic *efx)
466{
467 struct efx_ef10_nic_data *nic_data = efx->nic_data;
468 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
469 unsigned int i;
470 int rc;
471
472 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
473
474 for (i = 0; i < nic_data->n_piobufs; i++) {
475 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
476 nic_data->piobuf_handle[i]);
477 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
478 NULL, 0, NULL);
479 WARN_ON(rc);
480 }
481
482 nic_data->n_piobufs = 0;
483}
484
485static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
486{
487 struct efx_ef10_nic_data *nic_data = efx->nic_data;
488 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
489 unsigned int i;
490 size_t outlen;
491 int rc = 0;
492
493 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
494
495 for (i = 0; i < n; i++) {
496 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
497 outbuf, sizeof(outbuf), &outlen);
498 if (rc)
499 break;
500 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
501 rc = -EIO;
502 break;
503 }
504 nic_data->piobuf_handle[i] =
505 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
506 netif_dbg(efx, probe, efx->net_dev,
507 "allocated PIO buffer %u handle %x\n", i,
508 nic_data->piobuf_handle[i]);
509 }
510
511 nic_data->n_piobufs = i;
512 if (rc)
513 efx_ef10_free_piobufs(efx);
514 return rc;
515}
516
517static int efx_ef10_link_piobufs(struct efx_nic *efx)
518{
519 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 520 _MCDI_DECLARE_BUF(inbuf,
521 max(MC_CMD_LINK_PIOBUF_IN_LEN,
522 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 523 struct efx_channel *channel;
524 struct efx_tx_queue *tx_queue;
525 unsigned int offset, index;
526 int rc;
527
528 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
529 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
530
aa09a3da
JC		 531 memset(inbuf, 0, sizeof(inbuf));
532
183233be
BH		 533 /* Link a buffer to each VI in the write-combining mapping */
534 for (index = 0; index < nic_data->n_piobufs; ++index) {
535 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
536 nic_data->piobuf_handle[index]);
537 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
538 nic_data->pio_write_vi_base + index);
539 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
540 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
541 NULL, 0, NULL);
542 if (rc) {
543 netif_err(efx, drv, efx->net_dev,
544 "failed to link VI %u to PIO buffer %u (%d)\n",
545 nic_data->pio_write_vi_base + index, index,
546 rc);
547 goto fail;
548 }
549 netif_dbg(efx, probe, efx->net_dev,
550 "linked VI %u to PIO buffer %u\n",
551 nic_data->pio_write_vi_base + index, index);
552 }
553
554 /* Link a buffer to each TX queue */
555 efx_for_each_channel(channel, efx) {
556 efx_for_each_channel_tx_queue(tx_queue, channel) {
557 /* We assign the PIO buffers to queues in
558 * reverse order to allow for the following
559 * special case.
560 */
561 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
562 tx_queue->channel->channel - 1) *
563 efx_piobuf_size);
564 index = offset / ER_DZ_TX_PIOBUF_SIZE;
565 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
566
567 /* When the host page size is 4K, the first
568 * host page in the WC mapping may be within
569 * the same VI page as the last TX queue. We
570 * can only link one buffer to each VI.
571 */
572 if (tx_queue->queue == nic_data->pio_write_vi_base) {
573 BUG_ON(index != 0);
574 rc = 0;
575 } else {
576 MCDI_SET_DWORD(inbuf,
577 LINK_PIOBUF_IN_PIOBUF_HANDLE,
578 nic_data->piobuf_handle[index]);
579 MCDI_SET_DWORD(inbuf,
580 LINK_PIOBUF_IN_TXQ_INSTANCE,
581 tx_queue->queue);
582 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
583 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
584 NULL, 0, NULL);
585 }
586
587 if (rc) {
588 /* This is non-fatal; the TX path just
589 * won't use PIO for this queue
590 */
591 netif_err(efx, drv, efx->net_dev,
592 "failed to link VI %u to PIO buffer %u (%d)\n",
593 tx_queue->queue, index, rc);
594 tx_queue->piobuf = NULL;
595 } else {
596 tx_queue->piobuf =
597 nic_data->pio_write_base +
598 index * EFX_VI_PAGE_SIZE + offset;
599 tx_queue->piobuf_offset = offset;
600 netif_dbg(efx, probe, efx->net_dev,
601 "linked VI %u to PIO buffer %u offset %x addr %p\n",
602 tx_queue->queue, index,
603 tx_queue->piobuf_offset,
604 tx_queue->piobuf);
605 }
606 }
607 }
608
609 return 0;
610
611fail:
612 while (index--) {
613 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
614 nic_data->pio_write_vi_base + index);
615 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
616 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
617 NULL, 0, NULL);
618 }
619 return rc;
620}
621
622#else /* !EFX_USE_PIO */
623
624static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
625{
626 return n == 0 ? 0 : -ENOBUFS;
627}
628
629static int efx_ef10_link_piobufs(struct efx_nic *efx)
630{
631 return 0;
632}
633
634static void efx_ef10_free_piobufs(struct efx_nic *efx)
635{
636}
637
638#endif /* EFX_USE_PIO */
639
8127d661
BH		 640static void efx_ef10_remove(struct efx_nic *efx)
641{
642 struct efx_ef10_nic_data *nic_data = efx->nic_data;
643 int rc;
644
f1122a34
SS		 645#ifdef CONFIG_SFC_SRIOV
646 struct efx_ef10_nic_data *nic_data_pf;
647 struct pci_dev *pci_dev_pf;
648 struct efx_nic *efx_pf;
649 struct ef10_vf *vf;
650
651 if (efx->pci_dev->is_virtfn) {
652 pci_dev_pf = efx->pci_dev->physfn;
653 if (pci_dev_pf) {
654 efx_pf = pci_get_drvdata(pci_dev_pf);
655 nic_data_pf = efx_pf->nic_data;
656 vf = nic_data_pf->vf + nic_data->vf_index;
657 vf->efx = NULL;
658 } else
659 netif_info(efx, drv, efx->net_dev,
660 "Could not get the PF id from VF\n");
661 }
662#endif
663
9aecda95
BH		 664 efx_ptp_remove(efx);
665
8127d661
BH		 666 efx_mcdi_mon_remove(efx);
667
8127d661
BH		 668 efx_ef10_rx_free_indir_table(efx);
669
183233be
BH		 670 if (nic_data->wc_membase)
671 iounmap(nic_data->wc_membase);
672
8127d661
BH		 673 rc = efx_ef10_free_vis(efx);
674 WARN_ON(rc != 0);
675
183233be
BH		 676 if (!nic_data->must_restore_piobufs)
677 efx_ef10_free_piobufs(efx);
678
0f5c0845
SS		 679 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
680 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
681
8127d661
BH		 682 efx_mcdi_fini(efx);
683 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
684 kfree(nic_data);
685}
686
88a37de6
SS		 687static int efx_ef10_probe_pf(struct efx_nic *efx)
688{
689 return efx_ef10_probe(efx);
690}
691
7a186f47
DP		 692int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
693{
694 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
695
696 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
697 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
698 NULL, 0, NULL);
699}
700
701int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
702{
703 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
704
705 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
706 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
707 NULL, 0, NULL);
708}
709
710int efx_ef10_vport_add_mac(struct efx_nic *efx,
711 unsigned int port_id, u8 *mac)
712{
713 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
714
715 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
716 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
717
718 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
719 sizeof(inbuf), NULL, 0, NULL);
720}
721
722int efx_ef10_vport_del_mac(struct efx_nic *efx,
723 unsigned int port_id, u8 *mac)
724{
725 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
726
727 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
728 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
729
730 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
731 sizeof(inbuf), NULL, 0, NULL);
732}
733
88a37de6
SS		 734#ifdef CONFIG_SFC_SRIOV
735static int efx_ef10_probe_vf(struct efx_nic *efx)
736{
737 int rc;
6598dad2
DP		 738 struct pci_dev *pci_dev_pf;
739
740 /* If the parent PF has no VF data structure, it doesn't know about this
741 * VF so fail probe. The VF needs to be re-created. This can happen
742 * if the PF driver is unloaded while the VF is assigned to a guest.
743 */
744 pci_dev_pf = efx->pci_dev->physfn;
745 if (pci_dev_pf) {
746 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
747 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
748
749 if (!nic_data_pf->vf) {
750 netif_info(efx, drv, efx->net_dev,
751 "The VF cannot link to its parent PF; "
752 "please destroy and re-create the VF\n");
753 return -EBUSY;
754 }
755 }
88a37de6
SS		 756
757 rc = efx_ef10_probe(efx);
758 if (rc)
759 return rc;
760
761 rc = efx_ef10_get_vf_index(efx);
762 if (rc)
763 goto fail;
764
f1122a34
SS		 765 if (efx->pci_dev->is_virtfn) {
766 if (efx->pci_dev->physfn) {
767 struct efx_nic *efx_pf =
768 pci_get_drvdata(efx->pci_dev->physfn);
769 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
770 struct efx_ef10_nic_data *nic_data = efx->nic_data;
771
772 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 773 nic_data_p->vf[nic_data->vf_index].pci_dev =
774 efx->pci_dev;
f1122a34
SS		 775 } else
776 netif_info(efx, drv, efx->net_dev,
777 "Could not get the PF id from VF\n");
778 }
779
88a37de6
SS		 780 return 0;
781
782fail:
783 efx_ef10_remove(efx);
784 return rc;
785}
786#else
787static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
788{
789 return 0;
790}
791#endif
792
8127d661
BH		 793static int efx_ef10_alloc_vis(struct efx_nic *efx,
794 unsigned int min_vis, unsigned int max_vis)
795{
796 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
797 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
798 struct efx_ef10_nic_data *nic_data = efx->nic_data;
799 size_t outlen;
800 int rc;
801
802 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
803 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
804 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
805 outbuf, sizeof(outbuf), &outlen);
806 if (rc != 0)
807 return rc;
808
809 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
810 return -EIO;
811
812 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
813 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
814
815 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
816 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
817 return 0;
818}
819
183233be
BH		 820/* Note that the failure path of this function does not free
821 * resources, as this will be done by efx_ef10_remove().
822 */
8127d661
BH		 823static int efx_ef10_dimension_resources(struct efx_nic *efx)
824{
183233be
BH		 825 struct efx_ef10_nic_data *nic_data = efx->nic_data;
826 unsigned int uc_mem_map_size, wc_mem_map_size;
b0fbdae1
SS		 827 unsigned int min_vis = max(EFX_TXQ_TYPES,
828 efx_separate_tx_channels ? 2 : 1);
829 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 830 void __iomem *membase;
831 int rc;
832
b0fbdae1 833 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 834
183233be
BH		 835#ifdef EFX_USE_PIO
836 /* Try to allocate PIO buffers if wanted and if the full
837 * number of PIO buffers would be sufficient to allocate one
838 * copy-buffer per TX channel. Failure is non-fatal, as there
839 * are only a small number of PIO buffers shared between all
840 * functions of the controller.
841 */
842 if (efx_piobuf_size != 0 &&
843 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
844 efx->n_tx_channels) {
845 unsigned int n_piobufs =
846 DIV_ROUND_UP(efx->n_tx_channels,
847 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
848
849 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
850 if (rc)
851 netif_err(efx, probe, efx->net_dev,
852 "failed to allocate PIO buffers (%d)\n", rc);
853 else
854 netif_dbg(efx, probe, efx->net_dev,
855 "allocated %u PIO buffers\n", n_piobufs);
856 }
857#else
858 nic_data->n_piobufs = 0;
859#endif
860
861 /* PIO buffers should be mapped with write-combining enabled,
862 * and we want to make single UC and WC mappings rather than
863 * several of each (in fact that's the only option if host
864 * page size is >4K). So we may allocate some extra VIs just
865 * for writing PIO buffers through.
52ad762b 866 *
b0fbdae1 867 * The UC mapping contains (channel_vis - 1) complete VIs and the
52ad762b
DP		 868 * first half of the next VI. Then the WC mapping begins with
869 * the second half of this last VI.
183233be 870 */
b0fbdae1 871 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
183233be
BH		 872 ER_DZ_TX_PIOBUF);
873 if (nic_data->n_piobufs) {
52ad762b
DP		 874 /* pio_write_vi_base rounds down to give the number of complete
875 * VIs inside the UC mapping.
876 */
183233be
BH		 877 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
878 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
879 nic_data->n_piobufs) *
880 EFX_VI_PAGE_SIZE) -
881 uc_mem_map_size);
882 max_vis = pio_write_vi_base + nic_data->n_piobufs;
883 } else {
884 pio_write_vi_base = 0;
885 wc_mem_map_size = 0;
b0fbdae1 886 max_vis = channel_vis;
183233be
BH		 887 }
888
889 /* In case the last attached driver failed to free VIs, do it now */
890 rc = efx_ef10_free_vis(efx);
891 if (rc != 0)
892 return rc;
893
894 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
895 if (rc != 0)
896 return rc;
897
b0fbdae1
SS		 898 if (nic_data->n_allocated_vis < channel_vis) {
899 netif_info(efx, drv, efx->net_dev,
900 "Could not allocate enough VIs to satisfy RSS"
901 " requirements. Performance may not be optimal.\n");
902 /* We didn't get the VIs to populate our channels.
903 * We could keep what we got but then we'd have more
904 * interrupts than we need.
905 * Instead calculate new max_channels and restart
906 */
907 efx->max_channels = nic_data->n_allocated_vis;
908 efx->max_tx_channels =
909 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
910
911 efx_ef10_free_vis(efx);
912 return -EAGAIN;
913 }
914
183233be
BH		 915 /* If we didn't get enough VIs to map all the PIO buffers, free the
916 * PIO buffers
917 */
918 if (nic_data->n_piobufs &&
919 nic_data->n_allocated_vis <
920 pio_write_vi_base + nic_data->n_piobufs) {
921 netif_dbg(efx, probe, efx->net_dev,
922 "%u VIs are not sufficient to map %u PIO buffers\n",
923 nic_data->n_allocated_vis, nic_data->n_piobufs);
924 efx_ef10_free_piobufs(efx);
925 }
926
927 /* Shrink the original UC mapping of the memory BAR */
928 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
929 if (!membase) {
930 netif_err(efx, probe, efx->net_dev,
931 "could not shrink memory BAR to %x\n",
932 uc_mem_map_size);
933 return -ENOMEM;
934 }
935 iounmap(efx->membase);
936 efx->membase = membase;
937
938 /* Set up the WC mapping if needed */
939 if (wc_mem_map_size) {
940 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
941 uc_mem_map_size,
942 wc_mem_map_size);
943 if (!nic_data->wc_membase) {
944 netif_err(efx, probe, efx->net_dev,
945 "could not allocate WC mapping of size %x\n",
946 wc_mem_map_size);
947 return -ENOMEM;
948 }
949 nic_data->pio_write_vi_base = pio_write_vi_base;
950 nic_data->pio_write_base =
951 nic_data->wc_membase +
952 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
953 uc_mem_map_size);
954
955 rc = efx_ef10_link_piobufs(efx);
956 if (rc)
957 efx_ef10_free_piobufs(efx);
958 }
959
960 netif_dbg(efx, probe, efx->net_dev,
961 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
962 &efx->membase_phys, efx->membase, uc_mem_map_size,
963 nic_data->wc_membase, wc_mem_map_size);
964
965 return 0;
8127d661
BH		 966}
967
968static int efx_ef10_init_nic(struct efx_nic *efx)
969{
970 struct efx_ef10_nic_data *nic_data = efx->nic_data;
971 int rc;
972
a915ccc9
BH		 973 if (nic_data->must_check_datapath_caps) {
974 rc = efx_ef10_init_datapath_caps(efx);
975 if (rc)
976 return rc;
977 nic_data->must_check_datapath_caps = false;
978 }
979
8127d661
BH		 980 if (nic_data->must_realloc_vis) {
981 /* We cannot let the number of VIs change now */
982 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
983 nic_data->n_allocated_vis);
984 if (rc)
985 return rc;
986 nic_data->must_realloc_vis = false;
987 }
988
183233be
BH		 989 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
990 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
991 if (rc == 0) {
992 rc = efx_ef10_link_piobufs(efx);
993 if (rc)
994 efx_ef10_free_piobufs(efx);
995 }
996
997 /* Log an error on failure, but this is non-fatal */
998 if (rc)
999 netif_err(efx, drv, efx->net_dev,
1000 "failed to restore PIO buffers (%d)\n", rc);
1001 nic_data->must_restore_piobufs = false;
1002 }
1003
267c0157
JC		 1004 /* don't fail init if RSS setup doesn't work */
1005 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1006
8127d661
BH		 1007 return 0;
1008}
1009
3e336261
JC		 1010static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1011{
1012 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1013#ifdef CONFIG_SFC_SRIOV
1014 unsigned int i;
1015#endif
3e336261
JC		 1016
1017 /* All our allocations have been reset */
1018 nic_data->must_realloc_vis = true;
1019 nic_data->must_restore_filters = true;
1020 nic_data->must_restore_piobufs = true;
1021 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
774ad031
DP		 1022
1023 /* Driver-created vswitches and vports must be re-created */
1024 nic_data->must_probe_vswitching = true;
1025 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1026#ifdef CONFIG_SFC_SRIOV
1027 if (nic_data->vf)
1028 for (i = 0; i < efx->vf_count; i++)
1029 nic_data->vf[i].vport_id = 0;
1030#endif
3e336261
JC		 1031}
1032
087e9025
JC		 1033static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1034{
1035 if (reason == RESET_TYPE_MC_FAILURE)
1036 return RESET_TYPE_DATAPATH;
1037
1038 return efx_mcdi_map_reset_reason(reason);
1039}
1040
8127d661
BH		 1041static int efx_ef10_map_reset_flags(u32 *flags)
1042{
1043 enum {
1044 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1045 ETH_RESET_SHARED_SHIFT),
1046 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1047 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1048 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1049 ETH_RESET_SHARED_SHIFT)
1050 };
1051
1052 /* We assume for now that our PCI function is permitted to
1053 * reset everything.
1054 */
1055
1056 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1057 *flags &= ~EF10_RESET_MC;
1058 return RESET_TYPE_WORLD;
1059 }
1060
1061 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1062 *flags &= ~EF10_RESET_PORT;
1063 return RESET_TYPE_ALL;
1064 }
1065
1066 /* no invisible reset implemented */
1067
1068 return -EINVAL;
1069}
1070
3e336261
JC		 1071static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1072{
1073 int rc = efx_mcdi_reset(efx, reset_type);
1074
27324820
DP		 1075 /* Unprivileged functions return -EPERM, but need to return success
1076 * here so that the datapath is brought back up.
1077 */
1078 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1079 rc = 0;
1080
3e336261
JC		 1081 /* If it was a port reset, trigger reallocation of MC resources.
1082 * Note that on an MC reset nothing needs to be done now because we'll
1083 * detect the MC reset later and handle it then.
e283546c
EC		 1084 * For an FLR, we never get an MC reset event, but the MC has reset all
1085 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1086 */
e283546c
EC		 1087 if ((reset_type == RESET_TYPE_ALL ||
1088 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1089 efx_ef10_reset_mc_allocations(efx);
1090 return rc;
1091}
1092
8127d661
BH		 1093#define EF10_DMA_STAT(ext_name, mcdi_name) \
1094 [EF10_STAT_ ## ext_name] = \
1095 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1096#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1097 [EF10_STAT_ ## int_name] = \
1098 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1099#define EF10_OTHER_STAT(ext_name) \
1100 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1101#define GENERIC_SW_STAT(ext_name) \
1102 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1103
1104static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1105 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1106 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1107 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1108 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1109 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1110 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1111 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1112 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1113 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1114 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1115 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1116 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1117 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1118 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1119 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1120 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1121 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1122 EF10_OTHER_STAT(port_rx_good_bytes),
1123 EF10_OTHER_STAT(port_rx_bad_bytes),
1124 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1125 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1126 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1127 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1128 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1129 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1130 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1131 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1132 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1133 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1134 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1135 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1136 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1137 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1138 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1139 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1140 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1141 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1142 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1143 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1144 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1145 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1146 GENERIC_SW_STAT(rx_nodesc_trunc),
1147 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1148 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1149 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1150 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1151 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1152 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1153 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1154 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1155 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1156 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1157 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1158 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1159 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1160 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1161 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1162 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1163 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1164 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1165 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1166 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1167 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1168 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1169 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1170 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1171 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1172 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1173 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1174 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1175 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1176 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1177 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1178};
1179
e80ca013
DP		 1180#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1181 (1ULL << EF10_STAT_port_tx_packets) | \
1182 (1ULL << EF10_STAT_port_tx_pause) | \
1183 (1ULL << EF10_STAT_port_tx_unicast) | \
1184 (1ULL << EF10_STAT_port_tx_multicast) | \
1185 (1ULL << EF10_STAT_port_tx_broadcast) | \
1186 (1ULL << EF10_STAT_port_rx_bytes) | \
1187 (1ULL << \
1188 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1189 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1190 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1191 (1ULL << EF10_STAT_port_rx_packets) | \
1192 (1ULL << EF10_STAT_port_rx_good) | \
1193 (1ULL << EF10_STAT_port_rx_bad) | \
1194 (1ULL << EF10_STAT_port_rx_pause) | \
1195 (1ULL << EF10_STAT_port_rx_control) | \
1196 (1ULL << EF10_STAT_port_rx_unicast) | \
1197 (1ULL << EF10_STAT_port_rx_multicast) | \
1198 (1ULL << EF10_STAT_port_rx_broadcast) | \
1199 (1ULL << EF10_STAT_port_rx_lt64) | \
1200 (1ULL << EF10_STAT_port_rx_64) | \
1201 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1202 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1203 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1204 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1205 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1206 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1207 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1208 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1209 (1ULL << EF10_STAT_port_rx_overflow) | \
1210 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1211 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1212 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661
BH		 1213
1214/* These statistics are only provided by the 10G MAC. For a 10G/40G
1215 * switchable port we do not expose these because they might not
1216 * include all the packets they should.
1217 */
e80ca013
DP		 1218#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1219 (1ULL << EF10_STAT_port_tx_lt64) | \
1220 (1ULL << EF10_STAT_port_tx_64) | \
1221 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1222 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1223 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1224 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1225 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1226 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1227
1228/* These statistics are only provided by the 40G MAC. For a 10G/40G
1229 * switchable port we do expose these because the errors will otherwise
1230 * be silent.
1231 */
e80ca013
DP		 1232#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1233 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1234
568d7a00
EC		 1235/* These statistics are only provided if the firmware supports the
1236 * capability PM_AND_RXDP_COUNTERS.
1237 */
1238#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1239 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1240 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1241 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1242 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1243 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1244 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1245 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1246 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1247 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1248 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1249 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1250 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1251
4bae913b 1252static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1253{
4bae913b 1254 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1255 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1256 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1257
3c36a2ad
DP		 1258 if (!(efx->mcdi->fn_flags &
1259 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1260 return 0;
1261
8127d661 1262 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
4bae913b 1263 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
8127d661 1264 else
4bae913b 1265 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
568d7a00
EC		 1266
1267 if (nic_data->datapath_caps &
1268 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1269 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1270
4bae913b
EC		 1271 return raw_mask;
1272}
1273
1274static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1275{
d94619cd 1276 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1277 u64 raw_mask[2];
1278
1279 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1280
d94619cd
DP		 1281 /* Only show vadaptor stats when EVB capability is present */
1282 if (nic_data->datapath_caps &
1283 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1284 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1285 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1286 } else {
1287 raw_mask[1] = 0;
1288 }
4bae913b
EC		 1289
1290#if BITS_PER_LONG == 64
3c36a2ad
DP		 1291 mask[0] = raw_mask[0];
1292 mask[1] = raw_mask[1];
4bae913b 1293#else
3c36a2ad
DP		 1294 mask[0] = raw_mask[0] & 0xffffffff;
1295 mask[1] = raw_mask[0] >> 32;
1296 mask[2] = raw_mask[1] & 0xffffffff;
1297 mask[3] = raw_mask[1] >> 32;
4bae913b 1298#endif
8127d661
BH		 1299}
1300
1301static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1302{
4bae913b
EC		 1303 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1304
1305 efx_ef10_get_stat_mask(efx, mask);
8127d661 1306 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1307 mask, names);
8127d661
BH		 1308}
1309
d7788196
DP		 1310static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1311 struct rtnl_link_stats64 *core_stats)
1312{
1313 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1314 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1315 u64 *stats = nic_data->stats;
1316 size_t stats_count = 0, index;
1317
1318 efx_ef10_get_stat_mask(efx, mask);
1319
1320 if (full_stats) {
1321 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1322 if (efx_ef10_stat_desc[index].name) {
1323 *full_stats++ = stats[index];
1324 ++stats_count;
1325 }
1326 }
1327 }
1328
fbe4307e
BK		 1329 if (!core_stats)
1330 return stats_count;
1331
1332 if (nic_data->datapath_caps &
1333 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1334 /* Use vadaptor stats. */
0fc95fca
DP		 1335 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1336 stats[EF10_STAT_rx_multicast] +
1337 stats[EF10_STAT_rx_broadcast];
1338 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1339 stats[EF10_STAT_tx_multicast] +
1340 stats[EF10_STAT_tx_broadcast];
1341 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1342 stats[EF10_STAT_rx_multicast_bytes] +
1343 stats[EF10_STAT_rx_broadcast_bytes];
1344 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1345 stats[EF10_STAT_tx_multicast_bytes] +
1346 stats[EF10_STAT_tx_broadcast_bytes];
1347 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1348 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1349 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1350 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1351 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1352 core_stats->rx_errors = core_stats->rx_crc_errors;
1353 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1354 } else {
1355 /* Use port stats. */
1356 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1357 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1358 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1359 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1360 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1361 stats[GENERIC_STAT_rx_nodesc_trunc] +
1362 stats[GENERIC_STAT_rx_noskb_drops];
1363 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1364 core_stats->rx_length_errors =
1365 stats[EF10_STAT_port_rx_gtjumbo] +
1366 stats[EF10_STAT_port_rx_length_error];
1367 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1368 core_stats->rx_frame_errors =
1369 stats[EF10_STAT_port_rx_align_error];
1370 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1371 core_stats->rx_errors = (core_stats->rx_length_errors +
1372 core_stats->rx_crc_errors +
1373 core_stats->rx_frame_errors);
d7788196
DP		 1374 }
1375
1376 return stats_count;
1377}
1378
1379static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1380{
1381 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1382 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1383 __le64 generation_start, generation_end;
1384 u64 *stats = nic_data->stats;
1385 __le64 *dma_stats;
1386
4bae913b
EC		 1387 efx_ef10_get_stat_mask(efx, mask);
1388
8127d661
BH		 1389 dma_stats = efx->stats_buffer.addr;
1390 nic_data = efx->nic_data;
1391
1392 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1393 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1394 return 0;
1395 rmb();
4bae913b 1396 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1397 stats, efx->stats_buffer.addr, false);
d546a893 1398 rmb();
8127d661
BH		 1399 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1400 if (generation_end != generation_start)
1401 return -EAGAIN;
1402
1403 /* Update derived statistics */
e80ca013
DP		 1404 efx_nic_fix_nodesc_drop_stat(efx,
1405 &stats[EF10_STAT_port_rx_nodesc_drops]);
1406 stats[EF10_STAT_port_rx_good_bytes] =
1407 stats[EF10_STAT_port_rx_bytes] -
1408 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1409 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1410 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1411 efx_update_sw_stats(efx, stats);
8127d661
BH		 1412 return 0;
1413}
1414
1415
d7788196
DP		 1416static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1417 struct rtnl_link_stats64 *core_stats)
8127d661 1418{
8127d661
BH		 1419 int retry;
1420
1421 /* If we're unlucky enough to read statistics during the DMA, wait
1422 * up to 10ms for it to finish (typically takes <500us)
1423 */
1424 for (retry = 0; retry < 100; ++retry) {
d7788196 1425 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1426 break;
1427 udelay(100);
1428 }
1429
d7788196
DP		 1430 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1431}
8127d661 1432
d7788196
DP		 1433static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1434{
1435 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1436 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1437 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1438 __le64 generation_start, generation_end;
1439 u64 *stats = nic_data->stats;
1440 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1441 struct efx_buffer stats_buf;
1442 __le64 *dma_stats;
1443 int rc;
1444
f00bf230
DP		 1445 spin_unlock_bh(&efx->stats_lock);
1446
1447 if (in_interrupt()) {
1448 /* If in atomic context, cannot update stats. Just update the
1449 * software stats and return so the caller can continue.
1450 */
1451 spin_lock_bh(&efx->stats_lock);
1452 efx_update_sw_stats(efx, stats);
1453 return 0;
1454 }
1455
d7788196
DP		 1456 efx_ef10_get_stat_mask(efx, mask);
1457
1458 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1459 if (rc) {
1460 spin_lock_bh(&efx->stats_lock);
d7788196 1461 return rc;
f00bf230 1462 }
d7788196
DP		 1463
1464 dma_stats = stats_buf.addr;
1465 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1466
1467 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1468 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1469 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1470 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1471 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1472
6dd4859b
DP		 1473 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1474 NULL, 0, NULL);
d7788196 1475 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1476 if (rc) {
1477 /* Expect ENOENT if DMA queues have not been set up */
1478 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1479 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1480 sizeof(inbuf), NULL, 0, rc);
d7788196 1481 goto out;
6dd4859b 1482 }
d7788196
DP		 1483
1484 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1485 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1486 WARN_ON_ONCE(1);
d7788196 1487 goto out;
0fc95fca 1488 }
d7788196
DP		 1489 rmb();
1490 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1491 stats, stats_buf.addr, false);
1492 rmb();
1493 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1494 if (generation_end != generation_start) {
1495 rc = -EAGAIN;
1496 goto out;
8127d661
BH		 1497 }
1498
d7788196
DP		 1499 efx_update_sw_stats(efx, stats);
1500out:
1501 efx_nic_free_buffer(efx, &stats_buf);
1502 return rc;
1503}
1504
1505static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1506 struct rtnl_link_stats64 *core_stats)
1507{
1508 if (efx_ef10_try_update_nic_stats_vf(efx))
1509 return 0;
1510
1511 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1512}
1513
1514static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1515{
1516 struct efx_nic *efx = channel->efx;
1517 unsigned int mode, value;
1518 efx_dword_t timer_cmd;
1519
1520 if (channel->irq_moderation) {
1521 mode = 3;
1522 value = channel->irq_moderation - 1;
1523 } else {
1524 mode = 0;
1525 value = 0;
1526 }
1527
1528 if (EFX_EF10_WORKAROUND_35388(efx)) {
1529 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1530 EFE_DD_EVQ_IND_TIMER_FLAGS,
1531 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1532 ERF_DD_EVQ_IND_TIMER_VAL, value);
1533 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1534 channel->channel);
1535 } else {
1536 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1537 ERF_DZ_TC_TIMER_VAL, value);
1538 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1539 channel->channel);
1540 }
1541}
1542
02246a7f
SS		 1543static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1544 struct ethtool_wolinfo *wol) {}
1545
1546static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1547{
1548 return -EOPNOTSUPP;
1549}
1550
8127d661
BH		 1551static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1552{
1553 wol->supported = 0;
1554 wol->wolopts = 0;
1555 memset(&wol->sopass, 0, sizeof(wol->sopass));
1556}
1557
1558static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1559{
1560 if (type != 0)
1561 return -EINVAL;
1562 return 0;
1563}
1564
1565static void efx_ef10_mcdi_request(struct efx_nic *efx,
1566 const efx_dword_t *hdr, size_t hdr_len,
1567 const efx_dword_t *sdu, size_t sdu_len)
1568{
1569 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1570 u8 *pdu = nic_data->mcdi_buf.addr;
1571
1572 memcpy(pdu, hdr, hdr_len);
1573 memcpy(pdu + hdr_len, sdu, sdu_len);
1574 wmb();
1575
1576 /* The hardware provides 'low' and 'high' (doorbell) registers
1577 * for passing the 64-bit address of an MCDI request to
1578 * firmware. However the dwords are swapped by firmware. The
1579 * least significant bits of the doorbell are then 0 for all
1580 * MCDI requests due to alignment.
1581 */
1582 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1583 ER_DZ_MC_DB_LWRD);
1584 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1585 ER_DZ_MC_DB_HWRD);
1586}
1587
1588static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1589{
1590 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1591 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1592
1593 rmb();
1594 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1595}
1596
1597static void
1598efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1599 size_t offset, size_t outlen)
1600{
1601 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1602 const u8 *pdu = nic_data->mcdi_buf.addr;
1603
1604 memcpy(outbuf, pdu + offset, outlen);
1605}
1606
c577e59e
DP		 1607static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1608{
1609 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1610
1611 /* All our allocations have been reset */
1612 efx_ef10_reset_mc_allocations(efx);
1613
1614 /* The datapath firmware might have been changed */
1615 nic_data->must_check_datapath_caps = true;
1616
1617 /* MAC statistics have been cleared on the NIC; clear the local
1618 * statistic that we update with efx_update_diff_stat().
1619 */
1620 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1621}
1622
8127d661
BH		 1623static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1624{
1625 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1626 int rc;
1627
1628 rc = efx_ef10_get_warm_boot_count(efx);
1629 if (rc < 0) {
1630 /* The firmware is presumably in the process of
1631 * rebooting. However, we are supposed to report each
1632 * reboot just once, so we must only do that once we
1633 * can read and store the updated warm boot count.
1634 */
1635 return 0;
1636 }
1637
1638 if (rc == nic_data->warm_boot_count)
1639 return 0;
1640
1641 nic_data->warm_boot_count = rc;
c577e59e 1642 efx_ef10_mcdi_reboot_detected(efx);
869070c5 1643
8127d661
BH		 1644 return -EIO;
1645}
1646
1647/* Handle an MSI interrupt
1648 *
1649 * Handle an MSI hardware interrupt. This routine schedules event
1650 * queue processing. No interrupt acknowledgement cycle is necessary.
1651 * Also, we never need to check that the interrupt is for us, since
1652 * MSI interrupts cannot be shared.
1653 */
1654static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1655{
1656 struct efx_msi_context *context = dev_id;
1657 struct efx_nic *efx = context->efx;
1658
1659 netif_vdbg(efx, intr, efx->net_dev,
1660 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1661
1662 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1663 /* Note test interrupts */
1664 if (context->index == efx->irq_level)
1665 efx->last_irq_cpu = raw_smp_processor_id();
1666
1667 /* Schedule processing of the channel */
1668 efx_schedule_channel_irq(efx->channel[context->index]);
1669 }
1670
1671 return IRQ_HANDLED;
1672}
1673
1674static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1675{
1676 struct efx_nic *efx = dev_id;
1677 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1678 struct efx_channel *channel;
1679 efx_dword_t reg;
1680 u32 queues;
1681
1682 /* Read the ISR which also ACKs the interrupts */
1683 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1684 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1685
1686 if (queues == 0)
1687 return IRQ_NONE;
1688
1689 if (likely(soft_enabled)) {
1690 /* Note test interrupts */
1691 if (queues & (1U << efx->irq_level))
1692 efx->last_irq_cpu = raw_smp_processor_id();
1693
1694 efx_for_each_channel(channel, efx) {
1695 if (queues & 1)
1696 efx_schedule_channel_irq(channel);
1697 queues >>= 1;
1698 }
1699 }
1700
1701 netif_vdbg(efx, intr, efx->net_dev,
1702 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1703 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1704
1705 return IRQ_HANDLED;
1706}
1707
1708static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1709{
1710 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1711
1712 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1713
1714 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1715 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1716 inbuf, sizeof(inbuf), NULL, 0, NULL);
1717}
1718
1719static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1720{
1721 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1722 (tx_queue->ptr_mask + 1) *
1723 sizeof(efx_qword_t),
1724 GFP_KERNEL);
1725}
1726
1727/* This writes to the TX_DESC_WPTR and also pushes data */
1728static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1729 const efx_qword_t *txd)
1730{
1731 unsigned int write_ptr;
1732 efx_oword_t reg;
1733
1734 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1735 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1736 reg.qword[0] = *txd;
1737 efx_writeo_page(tx_queue->efx, &reg,
1738 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1739}
1740
1741static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1742{
1743 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1744 EFX_BUF_SIZE));
8127d661
BH		 1745 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1746 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1747 struct efx_channel *channel = tx_queue->channel;
1748 struct efx_nic *efx = tx_queue->efx;
45b2449e 1749 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 1750 size_t inlen;
8127d661
BH		 1751 dma_addr_t dma_addr;
1752 efx_qword_t *txd;
1753 int rc;
1754 int i;
aa09a3da 1755 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661
BH		 1756
1757 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1758 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1759 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1760 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1761 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1762 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1763 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1764 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 1765 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 1766
1767 dma_addr = tx_queue->txd.buf.dma_addr;
1768
1769 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1770 tx_queue->queue, entries, (u64)dma_addr);
1771
1772 for (i = 0; i < entries; ++i) {
1773 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1774 dma_addr += EFX_BUF_SIZE;
1775 }
1776
1777 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1778
1779 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
aa09a3da 1780 NULL, 0, NULL);
8127d661
BH		 1781 if (rc)
1782 goto fail;
1783
1784 /* A previous user of this TX queue might have set us up the
1785 * bomb by writing a descriptor to the TX push collector but
1786 * not the doorbell. (Each collector belongs to a port, not a
1787 * queue or function, so cannot easily be reset.) We must
1788 * attempt to push a no-op descriptor in its place.
1789 */
1790 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1791 tx_queue->insert_count = 1;
1792 txd = efx_tx_desc(tx_queue, 0);
1793 EFX_POPULATE_QWORD_4(*txd,
1794 ESF_DZ_TX_DESC_IS_OPT, true,
1795 ESF_DZ_TX_OPTION_TYPE,
1796 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1797 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1798 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1799 tx_queue->write_count = 1;
1800 wmb();
1801 efx_ef10_push_tx_desc(tx_queue, txd);
1802
1803 return;
1804
1805fail:
48ce5634
BH		 1806 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1807 tx_queue->queue);
8127d661
BH		 1808}
1809
1810static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1811{
1812 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 1813 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 1814 struct efx_nic *efx = tx_queue->efx;
1815 size_t outlen;
1816 int rc;
1817
1818 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1819 tx_queue->queue);
1820
1e0b8120 1821 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1822 outbuf, sizeof(outbuf), &outlen);
1823
1824 if (rc && rc != -EALREADY)
1825 goto fail;
1826
1827 return;
1828
1829fail:
1e0b8120
EC		 1830 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1831 outbuf, outlen, rc);
8127d661
BH		 1832}
1833
1834static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1835{
1836 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1837}
1838
1839/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1840static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1841{
1842 unsigned int write_ptr;
1843 efx_dword_t reg;
1844
1845 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1846 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1847 efx_writed_page(tx_queue->efx, &reg,
1848 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1849}
1850
1851static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1852{
1853 unsigned int old_write_count = tx_queue->write_count;
1854 struct efx_tx_buffer *buffer;
1855 unsigned int write_ptr;
1856 efx_qword_t *txd;
1857
b2663a4f
MH		 1858 tx_queue->xmit_more_available = false;
1859 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
1860 return;
8127d661
BH		 1861
1862 do {
1863 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1864 buffer = &tx_queue->buffer[write_ptr];
1865 txd = efx_tx_desc(tx_queue, write_ptr);
1866 ++tx_queue->write_count;
1867
1868 /* Create TX descriptor ring entry */
1869 if (buffer->flags & EFX_TX_BUF_OPTION) {
1870 *txd = buffer->option;
1871 } else {
1872 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1873 EFX_POPULATE_QWORD_3(
1874 *txd,
1875 ESF_DZ_TX_KER_CONT,
1876 buffer->flags & EFX_TX_BUF_CONT,
1877 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1878 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1879 }
1880 } while (tx_queue->write_count != tx_queue->insert_count);
1881
1882 wmb(); /* Ensure descriptors are written before they are fetched */
1883
1884 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1885 txd = efx_tx_desc(tx_queue,
1886 old_write_count & tx_queue->ptr_mask);
1887 efx_ef10_push_tx_desc(tx_queue, txd);
1888 ++tx_queue->pushes;
1889 } else {
1890 efx_ef10_notify_tx_desc(tx_queue);
1891 }
1892}
1893
267c0157
JC		 1894static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1895 bool exclusive, unsigned *context_size)
8127d661
BH		 1896{
1897 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1898 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 1899 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 1900 size_t outlen;
1901 int rc;
267c0157
JC		 1902 u32 alloc_type = exclusive ?
1903 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1904 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1905 unsigned rss_spread = exclusive ?
1906 efx->rss_spread :
1907 min(rounddown_pow_of_two(efx->rss_spread),
1908 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1909
1910 if (!exclusive && rss_spread == 1) {
1911 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1912 if (context_size)
1913 *context_size = 1;
1914 return 0;
1915 }
8127d661
BH		 1916
1917 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 1918 nic_data->vport_id);
267c0157
JC		 1919 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1920 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 1921
1922 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1923 outbuf, sizeof(outbuf), &outlen);
1924 if (rc != 0)
1925 return rc;
1926
1927 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1928 return -EIO;
1929
1930 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1931
267c0157
JC		 1932 if (context_size)
1933 *context_size = rss_spread;
1934
8127d661
BH		 1935 return 0;
1936}
1937
1938static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1939{
1940 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1941 int rc;
1942
1943 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1944 context);
1945
1946 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1947 NULL, 0, NULL);
1948 WARN_ON(rc != 0);
1949}
1950
267c0157
JC		 1951static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1952 const u32 *rx_indir_table)
8127d661
BH		 1953{
1954 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1955 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1956 int i, rc;
1957
1958 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1959 context);
1960 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1961 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1962
1963 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1964 MCDI_PTR(tablebuf,
1965 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 1966 (u8) rx_indir_table[i];
8127d661
BH		 1967
1968 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1969 sizeof(tablebuf), NULL, 0, NULL);
1970 if (rc != 0)
1971 return rc;
1972
1973 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1974 context);
1975 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1976 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1977 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1978 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1979 efx->rx_hash_key[i];
1980
1981 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1982 sizeof(keybuf), NULL, 0, NULL);
1983}
1984
1985static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1986{
1987 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1988
1989 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1990 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1991 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1992}
1993
267c0157
JC		 1994static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1995 unsigned *context_size)
8127d661 1996{
267c0157 1997 u32 new_rx_rss_context;
8127d661 1998 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 1999 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2000 false, context_size);
2001
2002 if (rc != 0)
2003 return rc;
8127d661 2004
267c0157
JC		 2005 nic_data->rx_rss_context = new_rx_rss_context;
2006 nic_data->rx_rss_context_exclusive = false;
2007 efx_set_default_rx_indir_table(efx);
2008 return 0;
2009}
8127d661 2010
267c0157
JC		 2011static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2012 const u32 *rx_indir_table)
2013{
2014 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2015 int rc;
2016 u32 new_rx_rss_context;
2017
2018 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2019 !nic_data->rx_rss_context_exclusive) {
2020 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2021 true, NULL);
2022 if (rc == -EOPNOTSUPP)
2023 return rc;
2024 else if (rc != 0)
2025 goto fail1;
2026 } else {
2027 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 2028 }
2029
267c0157
JC		 2030 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2031 rx_indir_table);
8127d661 2032 if (rc != 0)
267c0157 2033 goto fail2;
8127d661 2034
267c0157
JC		 2035 if (nic_data->rx_rss_context != new_rx_rss_context)
2036 efx_ef10_rx_free_indir_table(efx);
2037 nic_data->rx_rss_context = new_rx_rss_context;
2038 nic_data->rx_rss_context_exclusive = true;
2039 if (rx_indir_table != efx->rx_indir_table)
2040 memcpy(efx->rx_indir_table, rx_indir_table,
2041 sizeof(efx->rx_indir_table));
2042 return 0;
8127d661 2043
267c0157
JC		 2044fail2:
2045 if (new_rx_rss_context != nic_data->rx_rss_context)
2046 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2047fail1:
8127d661 2048 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 2049 return rc;
2050}
2051
2052static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2053 const u32 *rx_indir_table)
2054{
2055 int rc;
2056
2057 if (efx->rss_spread == 1)
2058 return 0;
2059
2060 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2061
2062 if (rc == -ENOBUFS && !user) {
2063 unsigned context_size;
2064 bool mismatch = false;
2065 size_t i;
2066
2067 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2068 i++)
2069 mismatch = rx_indir_table[i] !=
2070 ethtool_rxfh_indir_default(i, efx->rss_spread);
2071
2072 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2073 if (rc == 0) {
2074 if (context_size != efx->rss_spread)
2075 netif_warn(efx, probe, efx->net_dev,
2076 "Could not allocate an exclusive RSS"
2077 " context; allocated a shared one of"
2078 " different size."
2079 " Wanted %u, got %u.\n",
2080 efx->rss_spread, context_size);
2081 else if (mismatch)
2082 netif_warn(efx, probe, efx->net_dev,
2083 "Could not allocate an exclusive RSS"
2084 " context; allocated a shared one but"
2085 " could not apply custom"
2086 " indirection.\n");
2087 else
2088 netif_info(efx, probe, efx->net_dev,
2089 "Could not allocate an exclusive RSS"
2090 " context; allocated a shared one.\n");
2091 }
2092 }
2093 return rc;
2094}
2095
2096static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2097 const u32 *rx_indir_table
2098 __attribute__ ((unused)))
2099{
2100 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2101
2102 if (user)
2103 return -EOPNOTSUPP;
2104 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2105 return 0;
2106 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2107}
2108
2109static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2110{
2111 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2112 (rx_queue->ptr_mask + 1) *
2113 sizeof(efx_qword_t),
2114 GFP_KERNEL);
2115}
2116
2117static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2118{
2119 MCDI_DECLARE_BUF(inbuf,
2120 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2121 EFX_BUF_SIZE));
8127d661
BH		 2122 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2123 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2124 struct efx_nic *efx = rx_queue->efx;
45b2449e 2125 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2126 size_t inlen;
8127d661
BH		 2127 dma_addr_t dma_addr;
2128 int rc;
2129 int i;
aa09a3da 2130 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2131
2132 rx_queue->scatter_n = 0;
2133 rx_queue->scatter_len = 0;
2134
2135 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2136 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2137 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2138 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2139 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2140 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2141 INIT_RXQ_IN_FLAG_PREFIX, 1,
2142 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2143 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2144 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2145
2146 dma_addr = rx_queue->rxd.buf.dma_addr;
2147
2148 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2149 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2150
2151 for (i = 0; i < entries; ++i) {
2152 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2153 dma_addr += EFX_BUF_SIZE;
2154 }
2155
2156 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2157
2158 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2159 NULL, 0, NULL);
48ce5634
BH		 2160 if (rc)
2161 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2162 efx_rx_queue_index(rx_queue));
8127d661
BH		 2163}
2164
2165static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2166{
2167 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2168 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2169 struct efx_nic *efx = rx_queue->efx;
2170 size_t outlen;
2171 int rc;
2172
2173 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2174 efx_rx_queue_index(rx_queue));
2175
1e0b8120 2176 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2177 outbuf, sizeof(outbuf), &outlen);
2178
2179 if (rc && rc != -EALREADY)
2180 goto fail;
2181
2182 return;
2183
2184fail:
1e0b8120
EC		 2185 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2186 outbuf, outlen, rc);
8127d661
BH		 2187}
2188
2189static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2190{
2191 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2192}
2193
2194/* This creates an entry in the RX descriptor queue */
2195static inline void
2196efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2197{
2198 struct efx_rx_buffer *rx_buf;
2199 efx_qword_t *rxd;
2200
2201 rxd = efx_rx_desc(rx_queue, index);
2202 rx_buf = efx_rx_buffer(rx_queue, index);
2203 EFX_POPULATE_QWORD_2(*rxd,
2204 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2205 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2206}
2207
2208static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2209{
2210 struct efx_nic *efx = rx_queue->efx;
2211 unsigned int write_count;
2212 efx_dword_t reg;
2213
2214 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2215 write_count = rx_queue->added_count & ~7;
2216 if (rx_queue->notified_count == write_count)
2217 return;
2218
2219 do
2220 efx_ef10_build_rx_desc(
2221 rx_queue,
2222 rx_queue->notified_count & rx_queue->ptr_mask);
2223 while (++rx_queue->notified_count != write_count);
2224
2225 wmb();
2226 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2227 write_count & rx_queue->ptr_mask);
2228 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2229 efx_rx_queue_index(rx_queue));
2230}
2231
2232static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2233
2234static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2235{
2236 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2237 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2238 efx_qword_t event;
2239
2240 EFX_POPULATE_QWORD_2(event,
2241 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2242 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2243
2244 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2245
2246 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2247 * already swapped the data to little-endian order.
2248 */
2249 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2250 sizeof(efx_qword_t));
2251
2252 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2253 inbuf, sizeof(inbuf), 0,
2254 efx_ef10_rx_defer_refill_complete, 0);
2255}
2256
2257static void
2258efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2259 int rc, efx_dword_t *outbuf,
2260 size_t outlen_actual)
2261{
2262 /* nothing to do */
2263}
2264
2265static int efx_ef10_ev_probe(struct efx_channel *channel)
2266{
2267 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2268 (channel->eventq_mask + 1) *
2269 sizeof(efx_qword_t),
2270 GFP_KERNEL);
2271}
2272
46e612b0
DP		 2273static void efx_ef10_ev_fini(struct efx_channel *channel)
2274{
2275 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2276 MCDI_DECLARE_BUF_ERR(outbuf);
2277 struct efx_nic *efx = channel->efx;
2278 size_t outlen;
2279 int rc;
2280
2281 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2282
2283 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2284 outbuf, sizeof(outbuf), &outlen);
2285
2286 if (rc && rc != -EALREADY)
2287 goto fail;
2288
2289 return;
2290
2291fail:
2292 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2293 outbuf, outlen, rc);
2294}
2295
8127d661
BH		 2296static int efx_ef10_ev_init(struct efx_channel *channel)
2297{
2298 MCDI_DECLARE_BUF(inbuf,
2299 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2300 EFX_BUF_SIZE));
2301 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2302 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2303 struct efx_nic *efx = channel->efx;
2304 struct efx_ef10_nic_data *nic_data;
2305 bool supports_rx_merge;
2306 size_t inlen, outlen;
46e612b0 2307 unsigned int enabled, implemented;
8127d661
BH		 2308 dma_addr_t dma_addr;
2309 int rc;
2310 int i;
2311
2312 nic_data = efx->nic_data;
2313 supports_rx_merge =
2314 !!(nic_data->datapath_caps &
2315 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2316
2317 /* Fill event queue with all ones (i.e. empty events) */
2318 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2319
2320 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2321 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2322 /* INIT_EVQ expects index in vector table, not absolute */
2323 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2324 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2325 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2326 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2327 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2328 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2329 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2330 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2331 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2332 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2333 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2334 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2335 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2336
2337 dma_addr = channel->eventq.buf.dma_addr;
2338 for (i = 0; i < entries; ++i) {
2339 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2340 dma_addr += EFX_BUF_SIZE;
2341 }
2342
2343 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2344
2345 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2346 outbuf, sizeof(outbuf), &outlen);
8127d661 2347 /* IRQ return is ignored */
46e612b0
DP		 2348 if (channel->channel || rc)
2349 return rc;
8127d661 2350
46e612b0
DP		 2351 /* Successfully created event queue on channel 0 */
2352 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed
EC		 2353 if (rc == -ENOSYS) {
2354 /* GET_WORKAROUNDS was implemented before the bug26807
2355 * workaround, thus the latter must be unavailable in this fw
2356 */
2357 nic_data->workaround_26807 = false;
2358 rc = 0;
2359 } else if (rc) {
8127d661 2360 goto fail;
832dc9ed
EC		 2361 } else {
2362 nic_data->workaround_26807 =
2363 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2364
2365 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2366 !nic_data->workaround_26807) {
5a55a72a
DP		 2367 unsigned int flags;
2368
34ccfe6f
DP		 2369 rc = efx_mcdi_set_workaround(efx,
2370 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 2371 true, &flags);
2372
2373 if (!rc) {
2374 if (flags &
2375 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2376 netif_info(efx, drv, efx->net_dev,
2377 "other functions on NIC have been reset\n");
2378 /* MC's boot count has incremented */
2379 ++nic_data->warm_boot_count;
2380 }
832dc9ed 2381 nic_data->workaround_26807 = true;
5a55a72a 2382 } else if (rc == -EPERM) {
832dc9ed 2383 rc = 0;
5a55a72a 2384 }
832dc9ed 2385 }
46e612b0
DP		 2386 }
2387
2388 if (!rc)
2389 return 0;
8127d661
BH		 2390
2391fail:
46e612b0
DP		 2392 efx_ef10_ev_fini(channel);
2393 return rc;
8127d661
BH		 2394}
2395
2396static void efx_ef10_ev_remove(struct efx_channel *channel)
2397{
2398 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2399}
2400
2401static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2402 unsigned int rx_queue_label)
2403{
2404 struct efx_nic *efx = rx_queue->efx;
2405
2406 netif_info(efx, hw, efx->net_dev,
2407 "rx event arrived on queue %d labeled as queue %u\n",
2408 efx_rx_queue_index(rx_queue), rx_queue_label);
2409
2410 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2411}
2412
2413static void
2414efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2415 unsigned int actual, unsigned int expected)
2416{
2417 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2418 struct efx_nic *efx = rx_queue->efx;
2419
2420 netif_info(efx, hw, efx->net_dev,
2421 "dropped %d events (index=%d expected=%d)\n",
2422 dropped, actual, expected);
2423
2424 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2425}
2426
2427/* partially received RX was aborted. clean up. */
2428static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2429{
2430 unsigned int rx_desc_ptr;
2431
8127d661
BH		 2432 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2433 "scattered RX aborted (dropping %u buffers)\n",
2434 rx_queue->scatter_n);
2435
2436 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2437
2438 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2439 0, EFX_RX_PKT_DISCARD);
2440
2441 rx_queue->removed_count += rx_queue->scatter_n;
2442 rx_queue->scatter_n = 0;
2443 rx_queue->scatter_len = 0;
2444 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2445}
2446
2447static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2448 const efx_qword_t *event)
2449{
2450 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2451 unsigned int n_descs, n_packets, i;
2452 struct efx_nic *efx = channel->efx;
2453 struct efx_rx_queue *rx_queue;
2454 bool rx_cont;
2455 u16 flags = 0;
2456
2457 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2458 return 0;
2459
2460 /* Basic packet information */
2461 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2462 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2463 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2464 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2465 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2466
48ce5634
BH		 2467 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2468 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2469 EFX_QWORD_FMT "\n",
2470 EFX_QWORD_VAL(*event));
8127d661
BH		 2471
2472 rx_queue = efx_channel_get_rx_queue(channel);
2473
2474 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2475 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2476
2477 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2478 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2479
2480 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 2481 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2482
8127d661
BH		 2483 /* detect rx abort */
2484 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 2485 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2486 netdev_WARN(efx->net_dev,
2487 "invalid RX abort: scatter_n=%u event="
2488 EFX_QWORD_FMT "\n",
2489 rx_queue->scatter_n,
2490 EFX_QWORD_VAL(*event));
8127d661
BH		 2491 efx_ef10_handle_rx_abort(rx_queue);
2492 return 0;
2493 }
2494
92a04168
BH		 2495 /* Check that RX completion merging is valid, i.e.
2496 * the current firmware supports it and this is a
2497 * non-scattered packet.
2498 */
2499 if (!(nic_data->datapath_caps &
2500 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2501 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 2502 efx_ef10_handle_rx_bad_lbits(
2503 rx_queue, next_ptr_lbits,
2504 (rx_queue->removed_count +
2505 rx_queue->scatter_n + 1) &
2506 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2507 return 0;
2508 }
2509
2510 /* Merged completion for multiple non-scattered packets */
2511 rx_queue->scatter_n = 1;
2512 rx_queue->scatter_len = 0;
2513 n_packets = n_descs;
2514 ++channel->n_rx_merge_events;
2515 channel->n_rx_merge_packets += n_packets;
2516 flags |= EFX_RX_PKT_PREFIX_LEN;
2517 } else {
2518 ++rx_queue->scatter_n;
2519 rx_queue->scatter_len += rx_bytes;
2520 if (rx_cont)
2521 return 0;
2522 n_packets = 1;
2523 }
2524
2525 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2526 flags |= EFX_RX_PKT_DISCARD;
2527
2528 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2529 channel->n_rx_ip_hdr_chksum_err += n_packets;
2530 } else if (unlikely(EFX_QWORD_FIELD(*event,
2531 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2532 channel->n_rx_tcp_udp_chksum_err += n_packets;
2533 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2534 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2535 flags |= EFX_RX_PKT_CSUMMED;
2536 }
2537
2538 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2539 flags |= EFX_RX_PKT_TCP;
2540
2541 channel->irq_mod_score += 2 * n_packets;
2542
2543 /* Handle received packet(s) */
2544 for (i = 0; i < n_packets; i++) {
2545 efx_rx_packet(rx_queue,
2546 rx_queue->removed_count & rx_queue->ptr_mask,
2547 rx_queue->scatter_n, rx_queue->scatter_len,
2548 flags);
2549 rx_queue->removed_count += rx_queue->scatter_n;
2550 }
2551
2552 rx_queue->scatter_n = 0;
2553 rx_queue->scatter_len = 0;
2554
2555 return n_packets;
2556}
2557
2558static int
2559efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2560{
2561 struct efx_nic *efx = channel->efx;
2562 struct efx_tx_queue *tx_queue;
2563 unsigned int tx_ev_desc_ptr;
2564 unsigned int tx_ev_q_label;
2565 int tx_descs = 0;
2566
2567 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2568 return 0;
2569
2570 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2571 return 0;
2572
2573 /* Transmit completion */
2574 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2575 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2576 tx_queue = efx_channel_get_tx_queue(channel,
2577 tx_ev_q_label % EFX_TXQ_TYPES);
2578 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2579 tx_queue->ptr_mask);
2580 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2581
2582 return tx_descs;
2583}
2584
2585static void
2586efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2587{
2588 struct efx_nic *efx = channel->efx;
2589 int subcode;
2590
2591 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2592
2593 switch (subcode) {
2594 case ESE_DZ_DRV_TIMER_EV:
2595 case ESE_DZ_DRV_WAKE_UP_EV:
2596 break;
2597 case ESE_DZ_DRV_START_UP_EV:
2598 /* event queue init complete. ok. */
2599 break;
2600 default:
2601 netif_err(efx, hw, efx->net_dev,
2602 "channel %d unknown driver event type %d"
2603 " (data " EFX_QWORD_FMT ")\n",
2604 channel->channel, subcode,
2605 EFX_QWORD_VAL(*event));
2606
2607 }
2608}
2609
2610static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2611 efx_qword_t *event)
2612{
2613 struct efx_nic *efx = channel->efx;
2614 u32 subcode;
2615
2616 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2617
2618 switch (subcode) {
2619 case EFX_EF10_TEST:
2620 channel->event_test_cpu = raw_smp_processor_id();
2621 break;
2622 case EFX_EF10_REFILL:
2623 /* The queue must be empty, so we won't receive any rx
2624 * events, so efx_process_channel() won't refill the
2625 * queue. Refill it here
2626 */
cce28794 2627 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 2628 break;
2629 default:
2630 netif_err(efx, hw, efx->net_dev,
2631 "channel %d unknown driver event type %u"
2632 " (data " EFX_QWORD_FMT ")\n",
2633 channel->channel, (unsigned) subcode,
2634 EFX_QWORD_VAL(*event));
2635 }
2636}
2637
2638static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2639{
2640 struct efx_nic *efx = channel->efx;
2641 efx_qword_t event, *p_event;
2642 unsigned int read_ptr;
2643 int ev_code;
2644 int tx_descs = 0;
2645 int spent = 0;
2646
75363a46
EB		 2647 if (quota <= 0)
2648 return spent;
2649
8127d661
BH		 2650 read_ptr = channel->eventq_read_ptr;
2651
2652 for (;;) {
2653 p_event = efx_event(channel, read_ptr);
2654 event = *p_event;
2655
2656 if (!efx_event_present(&event))
2657 break;
2658
2659 EFX_SET_QWORD(*p_event);
2660
2661 ++read_ptr;
2662
2663 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2664
2665 netif_vdbg(efx, drv, efx->net_dev,
2666 "processing event on %d " EFX_QWORD_FMT "\n",
2667 channel->channel, EFX_QWORD_VAL(event));
2668
2669 switch (ev_code) {
2670 case ESE_DZ_EV_CODE_MCDI_EV:
2671 efx_mcdi_process_event(channel, &event);
2672 break;
2673 case ESE_DZ_EV_CODE_RX_EV:
2674 spent += efx_ef10_handle_rx_event(channel, &event);
2675 if (spent >= quota) {
2676 /* XXX can we split a merged event to
2677 * avoid going over-quota?
2678 */
2679 spent = quota;
2680 goto out;
2681 }
2682 break;
2683 case ESE_DZ_EV_CODE_TX_EV:
2684 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2685 if (tx_descs > efx->txq_entries) {
2686 spent = quota;
2687 goto out;
2688 } else if (++spent == quota) {
2689 goto out;
2690 }
2691 break;
2692 case ESE_DZ_EV_CODE_DRIVER_EV:
2693 efx_ef10_handle_driver_event(channel, &event);
2694 if (++spent == quota)
2695 goto out;
2696 break;
2697 case EFX_EF10_DRVGEN_EV:
2698 efx_ef10_handle_driver_generated_event(channel, &event);
2699 break;
2700 default:
2701 netif_err(efx, hw, efx->net_dev,
2702 "channel %d unknown event type %d"
2703 " (data " EFX_QWORD_FMT ")\n",
2704 channel->channel, ev_code,
2705 EFX_QWORD_VAL(event));
2706 }
2707 }
2708
2709out:
2710 channel->eventq_read_ptr = read_ptr;
2711 return spent;
2712}
2713
2714static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2715{
2716 struct efx_nic *efx = channel->efx;
2717 efx_dword_t rptr;
2718
2719 if (EFX_EF10_WORKAROUND_35388(efx)) {
2720 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2721 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2722 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2723 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2724
2725 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2726 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2727 ERF_DD_EVQ_IND_RPTR,
2728 (channel->eventq_read_ptr &
2729 channel->eventq_mask) >>
2730 ERF_DD_EVQ_IND_RPTR_WIDTH);
2731 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2732 channel->channel);
2733 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2734 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2735 ERF_DD_EVQ_IND_RPTR,
2736 channel->eventq_read_ptr &
2737 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2738 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2739 channel->channel);
2740 } else {
2741 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2742 channel->eventq_read_ptr &
2743 channel->eventq_mask);
2744 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2745 }
2746}
2747
2748static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2749{
2750 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2751 struct efx_nic *efx = channel->efx;
2752 efx_qword_t event;
2753 int rc;
2754
2755 EFX_POPULATE_QWORD_2(event,
2756 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2757 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2758
2759 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2760
2761 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2762 * already swapped the data to little-endian order.
2763 */
2764 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2765 sizeof(efx_qword_t));
2766
2767 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2768 NULL, 0, NULL);
2769 if (rc != 0)
2770 goto fail;
2771
2772 return;
2773
2774fail:
2775 WARN_ON(true);
2776 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2777}
2778
2779void efx_ef10_handle_drain_event(struct efx_nic *efx)
2780{
2781 if (atomic_dec_and_test(&efx->active_queues))
2782 wake_up(&efx->flush_wq);
2783
2784 WARN_ON(atomic_read(&efx->active_queues) < 0);
2785}
2786
2787static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2788{
2789 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2790 struct efx_channel *channel;
2791 struct efx_tx_queue *tx_queue;
2792 struct efx_rx_queue *rx_queue;
2793 int pending;
2794
2795 /* If the MC has just rebooted, the TX/RX queues will have already been
2796 * torn down, but efx->active_queues needs to be set to zero.
2797 */
2798 if (nic_data->must_realloc_vis) {
2799 atomic_set(&efx->active_queues, 0);
2800 return 0;
2801 }
2802
2803 /* Do not attempt to write to the NIC during EEH recovery */
2804 if (efx->state != STATE_RECOVERY) {
2805 efx_for_each_channel(channel, efx) {
2806 efx_for_each_channel_rx_queue(rx_queue, channel)
2807 efx_ef10_rx_fini(rx_queue);
2808 efx_for_each_channel_tx_queue(tx_queue, channel)
2809 efx_ef10_tx_fini(tx_queue);
2810 }
2811
2812 wait_event_timeout(efx->flush_wq,
2813 atomic_read(&efx->active_queues) == 0,
2814 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2815 pending = atomic_read(&efx->active_queues);
2816 if (pending) {
2817 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2818 pending);
2819 return -ETIMEDOUT;
2820 }
2821 }
2822
2823 return 0;
2824}
2825
e283546c
EC		 2826static void efx_ef10_prepare_flr(struct efx_nic *efx)
2827{
2828 atomic_set(&efx->active_queues, 0);
2829}
2830
8127d661
BH		 2831static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2832 const struct efx_filter_spec *right)
2833{
2834 if ((left->match_flags ^ right->match_flags) |
2835 ((left->flags ^ right->flags) &
2836 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2837 return false;
2838
2839 return memcmp(&left->outer_vid, &right->outer_vid,
2840 sizeof(struct efx_filter_spec) -
2841 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2842}
2843
2844static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2845{
2846 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2847 return jhash2((const u32 *)&spec->outer_vid,
2848 (sizeof(struct efx_filter_spec) -
2849 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2850 0);
2851 /* XXX should we randomise the initval? */
2852}
2853
2854/* Decide whether a filter should be exclusive or else should allow
2855 * delivery to additional recipients. Currently we decide that
2856 * filters for specific local unicast MAC and IP addresses are
2857 * exclusive.
2858 */
2859static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2860{
2861 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2862 !is_multicast_ether_addr(spec->loc_mac))
2863 return true;
2864
2865 if ((spec->match_flags &
2866 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2867 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2868 if (spec->ether_type == htons(ETH_P_IP) &&
2869 !ipv4_is_multicast(spec->loc_host[0]))
2870 return true;
2871 if (spec->ether_type == htons(ETH_P_IPV6) &&
2872 ((const u8 *)spec->loc_host)[0] != 0xff)
2873 return true;
2874 }
2875
2876 return false;
2877}
2878
2879static struct efx_filter_spec *
2880efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2881 unsigned int filter_idx)
2882{
2883 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2884 ~EFX_EF10_FILTER_FLAGS);
2885}
2886
2887static unsigned int
2888efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2889 unsigned int filter_idx)
2890{
2891 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2892}
2893
2894static void
2895efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2896 unsigned int filter_idx,
2897 const struct efx_filter_spec *spec,
2898 unsigned int flags)
2899{
2900 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2901}
2902
2903static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2904 const struct efx_filter_spec *spec,
2905 efx_dword_t *inbuf, u64 handle,
2906 bool replacing)
2907{
2908 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2909
2910 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2911
2912 if (replacing) {
2913 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2914 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2915 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2916 } else {
2917 u32 match_fields = 0;
2918
2919 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2920 efx_ef10_filter_is_exclusive(spec) ?
2921 MC_CMD_FILTER_OP_IN_OP_INSERT :
2922 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2923
2924 /* Convert match flags and values. Unlike almost
2925 * everything else in MCDI, these fields are in
2926 * network byte order.
2927 */
2928 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2929 match_fields |=
2930 is_multicast_ether_addr(spec->loc_mac) ?
2931 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2932 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2933#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2934 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2935 match_fields |= \
2936 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2937 mcdi_field ## _LBN; \
2938 BUILD_BUG_ON( \
2939 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2940 sizeof(spec->gen_field)); \
2941 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2942 &spec->gen_field, sizeof(spec->gen_field)); \
2943 }
2944 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2945 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2946 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2947 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2948 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2949 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2950 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2951 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2952 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2953 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2954#undef COPY_FIELD
2955 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2956 match_fields);
2957 }
2958
45b2449e 2959 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2960 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2961 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2962 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2963 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 2964 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 2965 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2966 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 2967 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2968 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2969 0 : spec->dmaq_id);
8127d661
BH		 2970 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2971 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2972 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2973 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2974 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2975 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2976 spec->rss_context !=
2977 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2978 spec->rss_context : nic_data->rx_rss_context);
2979}
2980
2981static int efx_ef10_filter_push(struct efx_nic *efx,
2982 const struct efx_filter_spec *spec,
2983 u64 *handle, bool replacing)
2984{
2985 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2986 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2987 int rc;
2988
2989 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2990 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2991 outbuf, sizeof(outbuf), NULL);
2992 if (rc == 0)
2993 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 2994 if (rc == -ENOSPC)
2995 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 2996 return rc;
2997}
2998
2999static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
3000 enum efx_filter_match_flags match_flags)
3001{
3002 unsigned int match_pri;
3003
3004 for (match_pri = 0;
3005 match_pri < table->rx_match_count;
3006 match_pri++)
3007 if (table->rx_match_flags[match_pri] == match_flags)
3008 return match_pri;
3009
3010 return -EPROTONOSUPPORT;
3011}
3012
3013static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3014 struct efx_filter_spec *spec,
3015 bool replace_equal)
3016{
3017 struct efx_ef10_filter_table *table = efx->filter_state;
3018 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3019 struct efx_filter_spec *saved_spec;
3020 unsigned int match_pri, hash;
3021 unsigned int priv_flags;
3022 bool replacing = false;
3023 int ins_index = -1;
3024 DEFINE_WAIT(wait);
3025 bool is_mc_recip;
3026 s32 rc;
3027
3028 /* For now, only support RX filters */
3029 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3030 EFX_FILTER_FLAG_RX)
3031 return -EINVAL;
3032
3033 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
3034 if (rc < 0)
3035 return rc;
3036 match_pri = rc;
3037
3038 hash = efx_ef10_filter_hash(spec);
3039 is_mc_recip = efx_filter_is_mc_recipient(spec);
3040 if (is_mc_recip)
3041 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3042
3043 /* Find any existing filters with the same match tuple or
3044 * else a free slot to insert at. If any of them are busy,
3045 * we have to wait and retry.
3046 */
3047 for (;;) {
3048 unsigned int depth = 1;
3049 unsigned int i;
3050
3051 spin_lock_bh(&efx->filter_lock);
3052
3053 for (;;) {
3054 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3055 saved_spec = efx_ef10_filter_entry_spec(table, i);
3056
3057 if (!saved_spec) {
3058 if (ins_index < 0)
3059 ins_index = i;
3060 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3061 if (table->entry[i].spec &
3062 EFX_EF10_FILTER_FLAG_BUSY)
3063 break;
3064 if (spec->priority < saved_spec->priority &&
7665d1ab 3065 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 3066 rc = -EPERM;
3067 goto out_unlock;
3068 }
3069 if (!is_mc_recip) {
3070 /* This is the only one */
3071 if (spec->priority ==
3072 saved_spec->priority &&
3073 !replace_equal) {
3074 rc = -EEXIST;
3075 goto out_unlock;
3076 }
3077 ins_index = i;
3078 goto found;
3079 } else if (spec->priority >
3080 saved_spec->priority ||
3081 (spec->priority ==
3082 saved_spec->priority &&
3083 replace_equal)) {
3084 if (ins_index < 0)
3085 ins_index = i;
3086 else
3087 __set_bit(depth, mc_rem_map);
3088 }
3089 }
3090
3091 /* Once we reach the maximum search depth, use
3092 * the first suitable slot or return -EBUSY if
3093 * there was none
3094 */
3095 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3096 if (ins_index < 0) {
3097 rc = -EBUSY;
3098 goto out_unlock;
3099 }
3100 goto found;
3101 }
3102
3103 ++depth;
3104 }
3105
3106 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3107 spin_unlock_bh(&efx->filter_lock);
3108 schedule();
3109 }
3110
3111found:
3112 /* Create a software table entry if necessary, and mark it
3113 * busy. We might yet fail to insert, but any attempt to
3114 * insert a conflicting filter while we're waiting for the
3115 * firmware must find the busy entry.
3116 */
3117 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3118 if (saved_spec) {
7665d1ab
BH		 3119 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3120 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 3121 /* Just make sure it won't be removed */
7665d1ab
BH		 3122 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3123 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3124 table->entry[ins_index].spec &=
b59e6ef8 3125 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3126 rc = ins_index;
3127 goto out_unlock;
3128 }
3129 replacing = true;
3130 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3131 } else {
3132 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3133 if (!saved_spec) {
3134 rc = -ENOMEM;
3135 goto out_unlock;
3136 }
3137 *saved_spec = *spec;
3138 priv_flags = 0;
3139 }
3140 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3141 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3142
3143 /* Mark lower-priority multicast recipients busy prior to removal */
3144 if (is_mc_recip) {
3145 unsigned int depth, i;
3146
3147 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3148 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3149 if (test_bit(depth, mc_rem_map))
3150 table->entry[i].spec |=
3151 EFX_EF10_FILTER_FLAG_BUSY;
3152 }
3153 }
3154
3155 spin_unlock_bh(&efx->filter_lock);
3156
3157 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3158 replacing);
3159
3160 /* Finalise the software table entry */
3161 spin_lock_bh(&efx->filter_lock);
3162 if (rc == 0) {
3163 if (replacing) {
3164 /* Update the fields that may differ */
7665d1ab
BH		 3165 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3166 saved_spec->flags |=
3167 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3168 saved_spec->priority = spec->priority;
7665d1ab 3169 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 3170 saved_spec->flags |= spec->flags;
3171 saved_spec->rss_context = spec->rss_context;
3172 saved_spec->dmaq_id = spec->dmaq_id;
3173 }
3174 } else if (!replacing) {
3175 kfree(saved_spec);
3176 saved_spec = NULL;
3177 }
3178 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3179
3180 /* Remove and finalise entries for lower-priority multicast
3181 * recipients
3182 */
3183 if (is_mc_recip) {
3184 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3185 unsigned int depth, i;
3186
3187 memset(inbuf, 0, sizeof(inbuf));
3188
3189 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3190 if (!test_bit(depth, mc_rem_map))
3191 continue;
3192
3193 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3194 saved_spec = efx_ef10_filter_entry_spec(table, i);
3195 priv_flags = efx_ef10_filter_entry_flags(table, i);
3196
3197 if (rc == 0) {
3198 spin_unlock_bh(&efx->filter_lock);
3199 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3200 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3201 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3202 table->entry[i].handle);
3203 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3204 inbuf, sizeof(inbuf),
3205 NULL, 0, NULL);
3206 spin_lock_bh(&efx->filter_lock);
3207 }
3208
3209 if (rc == 0) {
3210 kfree(saved_spec);
3211 saved_spec = NULL;
3212 priv_flags = 0;
3213 } else {
3214 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3215 }
3216 efx_ef10_filter_set_entry(table, i, saved_spec,
3217 priv_flags);
3218 }
3219 }
3220
3221 /* If successful, return the inserted filter ID */
3222 if (rc == 0)
3223 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3224
3225 wake_up_all(&table->waitq);
3226out_unlock:
3227 spin_unlock_bh(&efx->filter_lock);
3228 finish_wait(&table->waitq, &wait);
3229 return rc;
3230}
3231
9fd8095d 3232static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 3233{
3234 /* no need to do anything here on EF10 */
3235}
3236
3237/* Remove a filter.
b59e6ef8
BH		 3238 * If !by_index, remove by ID
3239 * If by_index, remove by index
8127d661
BH		 3240 * Filter ID may come from userland and must be range-checked.
3241 */
3242static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 3243 unsigned int priority_mask,
b59e6ef8 3244 u32 filter_id, bool by_index)
8127d661
BH		 3245{
3246 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3247 struct efx_ef10_filter_table *table = efx->filter_state;
3248 MCDI_DECLARE_BUF(inbuf,
3249 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3250 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3251 struct efx_filter_spec *spec;
3252 DEFINE_WAIT(wait);
3253 int rc;
3254
3255 /* Find the software table entry and mark it busy. Don't
3256 * remove it yet; any attempt to update while we're waiting
3257 * for the firmware must find the busy entry.
3258 */
3259 for (;;) {
3260 spin_lock_bh(&efx->filter_lock);
3261 if (!(table->entry[filter_idx].spec &
3262 EFX_EF10_FILTER_FLAG_BUSY))
3263 break;
3264 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3265 spin_unlock_bh(&efx->filter_lock);
3266 schedule();
3267 }
7665d1ab 3268
8127d661 3269 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 3270 if (!spec ||
b59e6ef8 3271 (!by_index &&
8127d661
BH		 3272 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3273 filter_id / HUNT_FILTER_TBL_ROWS)) {
3274 rc = -ENOENT;
3275 goto out_unlock;
3276 }
7665d1ab
BH		 3277
3278 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 3279 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 3280 /* Just remove flags */
3281 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 3282 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 3283 rc = 0;
3284 goto out_unlock;
3285 }
3286
fbd79120 3287 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 3288 rc = -ENOENT;
3289 goto out_unlock;
3290 }
3291
8127d661
BH		 3292 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3293 spin_unlock_bh(&efx->filter_lock);
3294
7665d1ab 3295 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 3296 /* Reset to an automatic filter */
8127d661
BH		 3297
3298 struct efx_filter_spec new_spec = *spec;
3299
7665d1ab 3300 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 3301 new_spec.flags = (EFX_FILTER_FLAG_RX |
7665d1ab 3302 EFX_FILTER_FLAG_RX_RSS);
8127d661
BH		 3303 new_spec.dmaq_id = 0;
3304 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3305 rc = efx_ef10_filter_push(efx, &new_spec,
3306 &table->entry[filter_idx].handle,
3307 true);
3308
3309 spin_lock_bh(&efx->filter_lock);
3310 if (rc == 0)
3311 *spec = new_spec;
3312 } else {
3313 /* Really remove the filter */
3314
3315 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3316 efx_ef10_filter_is_exclusive(spec) ?
3317 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3318 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3319 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3320 table->entry[filter_idx].handle);
3321 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3322 inbuf, sizeof(inbuf), NULL, 0, NULL);
3323
3324 spin_lock_bh(&efx->filter_lock);
3325 if (rc == 0) {
3326 kfree(spec);
3327 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3328 }
3329 }
7665d1ab 3330
8127d661
BH		 3331 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3332 wake_up_all(&table->waitq);
3333out_unlock:
3334 spin_unlock_bh(&efx->filter_lock);
3335 finish_wait(&table->waitq, &wait);
3336 return rc;
3337}
3338
3339static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3340 enum efx_filter_priority priority,
3341 u32 filter_id)
3342{
fbd79120
BH		 3343 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3344 filter_id, false);
8127d661
BH		 3345}
3346
12fb0da4
EC		 3347static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3348{
3349 return filter_id % HUNT_FILTER_TBL_ROWS;
3350}
3351
3352static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3353 enum efx_filter_priority priority,
3354 u32 filter_id)
3355{
3356 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3357 filter_id, true);
3358}
3359
8127d661
BH		 3360static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3361 enum efx_filter_priority priority,
3362 u32 filter_id, struct efx_filter_spec *spec)
3363{
3364 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3365 struct efx_ef10_filter_table *table = efx->filter_state;
3366 const struct efx_filter_spec *saved_spec;
3367 int rc;
3368
3369 spin_lock_bh(&efx->filter_lock);
3370 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3371 if (saved_spec && saved_spec->priority == priority &&
3372 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3373 filter_id / HUNT_FILTER_TBL_ROWS) {
3374 *spec = *saved_spec;
3375 rc = 0;
3376 } else {
3377 rc = -ENOENT;
3378 }
3379 spin_unlock_bh(&efx->filter_lock);
3380 return rc;
3381}
3382
fbd79120 3383static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 3384 enum efx_filter_priority priority)
3385{
fbd79120
BH		 3386 unsigned int priority_mask;
3387 unsigned int i;
3388 int rc;
3389
3390 priority_mask = (((1U << (priority + 1)) - 1) &
3391 ~(1U << EFX_FILTER_PRI_AUTO));
3392
3393 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3394 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3395 i, true);
3396 if (rc && rc != -ENOENT)
3397 return rc;
3398 }
3399
3400 return 0;
8127d661
BH		 3401}
3402
3403static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3404 enum efx_filter_priority priority)
3405{
3406 struct efx_ef10_filter_table *table = efx->filter_state;
3407 unsigned int filter_idx;
3408 s32 count = 0;
3409
3410 spin_lock_bh(&efx->filter_lock);
3411 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3412 if (table->entry[filter_idx].spec &&
3413 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3414 priority)
3415 ++count;
3416 }
3417 spin_unlock_bh(&efx->filter_lock);
3418 return count;
3419}
3420
3421static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3422{
3423 struct efx_ef10_filter_table *table = efx->filter_state;
3424
3425 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3426}
3427
3428static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3429 enum efx_filter_priority priority,
3430 u32 *buf, u32 size)
3431{
3432 struct efx_ef10_filter_table *table = efx->filter_state;
3433 struct efx_filter_spec *spec;
3434 unsigned int filter_idx;
3435 s32 count = 0;
3436
3437 spin_lock_bh(&efx->filter_lock);
3438 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3439 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3440 if (spec && spec->priority == priority) {
3441 if (count == size) {
3442 count = -EMSGSIZE;
3443 break;
3444 }
3445 buf[count++] = (efx_ef10_filter_rx_match_pri(
3446 table, spec->match_flags) *
3447 HUNT_FILTER_TBL_ROWS +
3448 filter_idx);
3449 }
3450 }
3451 spin_unlock_bh(&efx->filter_lock);
3452 return count;
3453}
3454
3455#ifdef CONFIG_RFS_ACCEL
3456
3457static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3458
3459static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3460 struct efx_filter_spec *spec)
3461{
3462 struct efx_ef10_filter_table *table = efx->filter_state;
3463 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3464 struct efx_filter_spec *saved_spec;
3465 unsigned int hash, i, depth = 1;
3466 bool replacing = false;
3467 int ins_index = -1;
3468 u64 cookie;
3469 s32 rc;
3470
3471 /* Must be an RX filter without RSS and not for a multicast
3472 * destination address (RFS only works for connected sockets).
3473 * These restrictions allow us to pass only a tiny amount of
3474 * data through to the completion function.
3475 */
3476 EFX_WARN_ON_PARANOID(spec->flags !=
3477 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3478 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3479 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3480
3481 hash = efx_ef10_filter_hash(spec);
3482
3483 spin_lock_bh(&efx->filter_lock);
3484
3485 /* Find any existing filter with the same match tuple or else
3486 * a free slot to insert at. If an existing filter is busy,
3487 * we have to give up.
3488 */
3489 for (;;) {
3490 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3491 saved_spec = efx_ef10_filter_entry_spec(table, i);
3492
3493 if (!saved_spec) {
3494 if (ins_index < 0)
3495 ins_index = i;
3496 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3497 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3498 rc = -EBUSY;
3499 goto fail_unlock;
3500 }
8127d661
BH		 3501 if (spec->priority < saved_spec->priority) {
3502 rc = -EPERM;
3503 goto fail_unlock;
3504 }
3505 ins_index = i;
3506 break;
3507 }
3508
3509 /* Once we reach the maximum search depth, use the
3510 * first suitable slot or return -EBUSY if there was
3511 * none
3512 */
3513 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3514 if (ins_index < 0) {
3515 rc = -EBUSY;
3516 goto fail_unlock;
3517 }
3518 break;
3519 }
3520
3521 ++depth;
3522 }
3523
3524 /* Create a software table entry if necessary, and mark it
3525 * busy. We might yet fail to insert, but any attempt to
3526 * insert a conflicting filter while we're waiting for the
3527 * firmware must find the busy entry.
3528 */
3529 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3530 if (saved_spec) {
3531 replacing = true;
3532 } else {
3533 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3534 if (!saved_spec) {
3535 rc = -ENOMEM;
3536 goto fail_unlock;
3537 }
3538 *saved_spec = *spec;
3539 }
3540 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3541 EFX_EF10_FILTER_FLAG_BUSY);
3542
3543 spin_unlock_bh(&efx->filter_lock);
3544
3545 /* Pack up the variables needed on completion */
3546 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3547
3548 efx_ef10_filter_push_prep(efx, spec, inbuf,
3549 table->entry[ins_index].handle, replacing);
3550 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3551 MC_CMD_FILTER_OP_OUT_LEN,
3552 efx_ef10_filter_rfs_insert_complete, cookie);
3553
3554 return ins_index;
3555
3556fail_unlock:
3557 spin_unlock_bh(&efx->filter_lock);
3558 return rc;
3559}
3560
3561static void
3562efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3563 int rc, efx_dword_t *outbuf,
3564 size_t outlen_actual)
3565{
3566 struct efx_ef10_filter_table *table = efx->filter_state;
3567 unsigned int ins_index, dmaq_id;
3568 struct efx_filter_spec *spec;
3569 bool replacing;
3570
3571 /* Unpack the cookie */
3572 replacing = cookie >> 31;
3573 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3574 dmaq_id = cookie & 0xffff;
3575
3576 spin_lock_bh(&efx->filter_lock);
3577 spec = efx_ef10_filter_entry_spec(table, ins_index);
3578 if (rc == 0) {
3579 table->entry[ins_index].handle =
3580 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3581 if (replacing)
3582 spec->dmaq_id = dmaq_id;
3583 } else if (!replacing) {
3584 kfree(spec);
3585 spec = NULL;
3586 }
3587 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3588 spin_unlock_bh(&efx->filter_lock);
3589
3590 wake_up_all(&table->waitq);
3591}
3592
3593static void
3594efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3595 unsigned long filter_idx,
3596 int rc, efx_dword_t *outbuf,
3597 size_t outlen_actual);
3598
3599static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3600 unsigned int filter_idx)
3601{
3602 struct efx_ef10_filter_table *table = efx->filter_state;
3603 struct efx_filter_spec *spec =
3604 efx_ef10_filter_entry_spec(table, filter_idx);
3605 MCDI_DECLARE_BUF(inbuf,
3606 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3607 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3608
3609 if (!spec ||
3610 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3611 spec->priority != EFX_FILTER_PRI_HINT ||
3612 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3613 flow_id, filter_idx))
3614 return false;
3615
3616 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3617 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3618 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3619 table->entry[filter_idx].handle);
3620 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3621 efx_ef10_filter_rfs_expire_complete, filter_idx))
3622 return false;
3623
3624 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3625 return true;
3626}
3627
3628static void
3629efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3630 unsigned long filter_idx,
3631 int rc, efx_dword_t *outbuf,
3632 size_t outlen_actual)
3633{
3634 struct efx_ef10_filter_table *table = efx->filter_state;
3635 struct efx_filter_spec *spec =
3636 efx_ef10_filter_entry_spec(table, filter_idx);
3637
3638 spin_lock_bh(&efx->filter_lock);
3639 if (rc == 0) {
3640 kfree(spec);
3641 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3642 }
3643 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3644 wake_up_all(&table->waitq);
3645 spin_unlock_bh(&efx->filter_lock);
3646}
3647
3648#endif /* CONFIG_RFS_ACCEL */
3649
3650static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3651{
3652 int match_flags = 0;
3653
3654#define MAP_FLAG(gen_flag, mcdi_field) { \
3655 u32 old_mcdi_flags = mcdi_flags; \
3656 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3657 mcdi_field ## _LBN); \
3658 if (mcdi_flags != old_mcdi_flags) \
3659 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3660 }
3661 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3662 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3663 MAP_FLAG(REM_HOST, SRC_IP);
3664 MAP_FLAG(LOC_HOST, DST_IP);
3665 MAP_FLAG(REM_MAC, SRC_MAC);
3666 MAP_FLAG(REM_PORT, SRC_PORT);
3667 MAP_FLAG(LOC_MAC, DST_MAC);
3668 MAP_FLAG(LOC_PORT, DST_PORT);
3669 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3670 MAP_FLAG(INNER_VID, INNER_VLAN);
3671 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3672 MAP_FLAG(IP_PROTO, IP_PROTO);
3673#undef MAP_FLAG
3674
3675 /* Did we map them all? */
3676 if (mcdi_flags)
3677 return -EINVAL;
3678
3679 return match_flags;
3680}
3681
3682static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3683{
3684 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3685 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3686 unsigned int pd_match_pri, pd_match_count;
3687 struct efx_ef10_filter_table *table;
3688 size_t outlen;
3689 int rc;
3690
3691 table = kzalloc(sizeof(*table), GFP_KERNEL);
3692 if (!table)
3693 return -ENOMEM;
3694
3695 /* Find out which RX filter types are supported, and their priorities */
3696 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3697 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3698 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3699 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3700 &outlen);
3701 if (rc)
3702 goto fail;
3703 pd_match_count = MCDI_VAR_ARRAY_LEN(
3704 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3705 table->rx_match_count = 0;
3706
3707 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3708 u32 mcdi_flags =
3709 MCDI_ARRAY_DWORD(
3710 outbuf,
3711 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3712 pd_match_pri);
3713 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3714 if (rc < 0) {
3715 netif_dbg(efx, probe, efx->net_dev,
3716 "%s: fw flags %#x pri %u not supported in driver\n",
3717 __func__, mcdi_flags, pd_match_pri);
3718 } else {
3719 netif_dbg(efx, probe, efx->net_dev,
3720 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3721 __func__, mcdi_flags, pd_match_pri,
3722 rc, table->rx_match_count);
3723 table->rx_match_flags[table->rx_match_count++] = rc;
3724 }
3725 }
3726
3727 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3728 if (!table->entry) {
3729 rc = -ENOMEM;
3730 goto fail;
3731 }
3732
12fb0da4
EC		 3733 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3734 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3735 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3736
8127d661
BH		 3737 efx->filter_state = table;
3738 init_waitqueue_head(&table->waitq);
3739 return 0;
3740
3741fail:
3742 kfree(table);
3743 return rc;
3744}
3745
0d322413
EC		 3746/* Caller must hold efx->filter_sem for read if race against
3747 * efx_ef10_filter_table_remove() is possible
3748 */
8127d661
BH		 3749static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3750{
3751 struct efx_ef10_filter_table *table = efx->filter_state;
3752 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3753 struct efx_filter_spec *spec;
3754 unsigned int filter_idx;
3755 bool failed = false;
3756 int rc;
3757
0d322413
EC		 3758 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3759
8127d661
BH		 3760 if (!nic_data->must_restore_filters)
3761 return;
3762
0d322413
EC		 3763 if (!table)
3764 return;
3765
8127d661
BH		 3766 spin_lock_bh(&efx->filter_lock);
3767
3768 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3769 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3770 if (!spec)
3771 continue;
3772
3773 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3774 spin_unlock_bh(&efx->filter_lock);
3775
3776 rc = efx_ef10_filter_push(efx, spec,
3777 &table->entry[filter_idx].handle,
3778 false);
3779 if (rc)
3780 failed = true;
3781
3782 spin_lock_bh(&efx->filter_lock);
3783 if (rc) {
3784 kfree(spec);
3785 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3786 } else {
3787 table->entry[filter_idx].spec &=
3788 ~EFX_EF10_FILTER_FLAG_BUSY;
3789 }
3790 }
3791
3792 spin_unlock_bh(&efx->filter_lock);
3793
3794 if (failed)
3795 netif_err(efx, hw, efx->net_dev,
3796 "unable to restore all filters\n");
3797 else
3798 nic_data->must_restore_filters = false;
3799}
3800
0d322413 3801/* Caller must hold efx->filter_sem for write */
8127d661
BH		 3802static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3803{
3804 struct efx_ef10_filter_table *table = efx->filter_state;
3805 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3806 struct efx_filter_spec *spec;
3807 unsigned int filter_idx;
3808 int rc;
3809
0d322413
EC		 3810 efx->filter_state = NULL;
3811 if (!table)
3812 return;
3813
8127d661
BH		 3814 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3815 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3816 if (!spec)
3817 continue;
3818
3819 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3820 efx_ef10_filter_is_exclusive(spec) ?
3821 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3822 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3823 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3824 table->entry[filter_idx].handle);
3825 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3826 NULL, 0, NULL);
48ce5634
BH		 3827 if (rc)
3828 netdev_WARN(efx->net_dev,
3829 "filter_idx=%#x handle=%#llx\n",
3830 filter_idx,
3831 table->entry[filter_idx].handle);
8127d661
BH		 3832 kfree(spec);
3833 }
3834
3835 vfree(table->entry);
3836 kfree(table);
3837}
3838
12fb0da4
EC		 3839#define EFX_EF10_FILTER_DO_MARK_OLD(id) \
3840 if (id != EFX_EF10_FILTER_ID_INVALID) { \
3841 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \
3842 WARN_ON(!table->entry[filter_idx].spec); \
3843 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; \
3844 }
822b96f8 3845static void efx_ef10_filter_mark_old(struct efx_nic *efx)
8127d661
BH		 3846{
3847 struct efx_ef10_filter_table *table = efx->filter_state;
822b96f8 3848 unsigned int filter_idx, i;
8127d661 3849
0d322413
EC		 3850 if (!table)
3851 return;
3852
8127d661
BH		 3853 /* Mark old filters that may need to be removed */
3854 spin_lock_bh(&efx->filter_lock);
12fb0da4
EC		 3855 for (i = 0; i < table->dev_uc_count; i++)
3856 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id);
3857 for (i = 0; i < table->dev_mc_count; i++)
3858 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id);
3859 EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id);
3860 EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id);
3861 EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id);
8127d661 3862 spin_unlock_bh(&efx->filter_lock);
822b96f8 3863}
12fb0da4 3864#undef EFX_EF10_FILTER_DO_MARK_OLD
822b96f8
DP		 3865
3866static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc)
3867{
3868 struct efx_ef10_filter_table *table = efx->filter_state;
3869 struct net_device *net_dev = efx->net_dev;
3870 struct netdev_hw_addr *uc;
12fb0da4 3871 int addr_count;
822b96f8 3872 unsigned int i;
8127d661 3873
12fb0da4
EC		 3874 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3875 addr_count = netdev_uc_count(net_dev);
3876 if (net_dev->flags & IFF_PROMISC)
822b96f8 3877 *promisc = true;
12fb0da4 3878 table->dev_uc_count = 1 + addr_count;
822b96f8
DP		 3879 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3880 i = 1;
3881 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4
EC		 3882 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
3883 *promisc = true;
3884 break;
3885 }
822b96f8 3886 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
12fb0da4 3887 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
822b96f8
DP		 3888 i++;
3889 }
3890}
3891
3892static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc)
3893{
3894 struct efx_ef10_filter_table *table = efx->filter_state;
3895 struct net_device *net_dev = efx->net_dev;
3896 struct netdev_hw_addr *mc;
ab8b1f7c 3897 unsigned int i, addr_count;
822b96f8 3898
12fb0da4
EC		 3899 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3900 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
ab8b1f7c 3901 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
822b96f8 3902 *promisc = true;
ab8b1f7c 3903
12fb0da4
EC		 3904 addr_count = netdev_mc_count(net_dev);
3905 i = 0;
ab8b1f7c 3906 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4
EC		 3907 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
3908 *promisc = true;
3909 break;
3910 }
ab8b1f7c 3911 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
12fb0da4 3912 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
ab8b1f7c 3913 i++;
8127d661 3914 }
12fb0da4
EC		 3915
3916 table->dev_mc_count = i;
822b96f8 3917}
8127d661 3918
12fb0da4
EC		 3919static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
3920 bool multicast, bool rollback)
822b96f8
DP		 3921{
3922 struct efx_ef10_filter_table *table = efx->filter_state;
3923 struct efx_ef10_dev_addr *addr_list;
3924 struct efx_filter_spec spec;
12fb0da4
EC		 3925 u8 baddr[ETH_ALEN];
3926 unsigned int i, j;
3927 int addr_count;
822b96f8
DP		 3928 int rc;
3929
3930 if (multicast) {
3931 addr_list = table->dev_mc_list;
12fb0da4 3932 addr_count = table->dev_mc_count;
822b96f8
DP		 3933 } else {
3934 addr_list = table->dev_uc_list;
12fb0da4 3935 addr_count = table->dev_uc_count;
8127d661
BH		 3936 }
3937
822b96f8 3938 /* Insert/renew filters */
12fb0da4 3939 for (i = 0; i < addr_count; i++) {
b6f568e2
JC		 3940 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3941 EFX_FILTER_FLAG_RX_RSS,
3942 0);
3943 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
822b96f8 3944 addr_list[i].addr);
b6f568e2
JC		 3945 rc = efx_ef10_filter_insert(efx, &spec, true);
3946 if (rc < 0) {
12fb0da4
EC		 3947 if (rollback) {
3948 netif_info(efx, drv, efx->net_dev,
3949 "efx_ef10_filter_insert failed rc=%d\n",
3950 rc);
3951 /* Fall back to promiscuous */
3952 for (j = 0; j < i; j++) {
3953 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3954 continue;
3955 efx_ef10_filter_remove_unsafe(
3956 efx, EFX_FILTER_PRI_AUTO,
3957 addr_list[j].id);
3958 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3959 }
3960 return rc;
3961 } else {
3962 /* mark as not inserted, and carry on */
3963 rc = EFX_EF10_FILTER_ID_INVALID;
822b96f8 3964 }
8127d661 3965 }
12fb0da4 3966 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc);
8127d661 3967 }
822b96f8 3968
12fb0da4
EC		 3969 if (multicast && rollback) {
3970 /* Also need an Ethernet broadcast filter */
7665d1ab
BH		 3971 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3972 EFX_FILTER_FLAG_RX_RSS,
8127d661 3973 0);
12fb0da4
EC		 3974 eth_broadcast_addr(baddr);
3975 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr);
8127d661 3976 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 3977 if (rc < 0) {
822b96f8 3978 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 3979 "Broadcast filter insert failed rc=%d\n", rc);
3980 /* Fall back to promiscuous */
3981 for (j = 0; j < i; j++) {
3982 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3983 continue;
3984 efx_ef10_filter_remove_unsafe(
3985 efx, EFX_FILTER_PRI_AUTO,
3986 addr_list[j].id);
3987 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3988 }
3989 return rc;
3990 } else {
3991 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
3992 }
8127d661 3993 }
12fb0da4
EC		 3994
3995 return 0;
3996}
3997
3998static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast,
3999 bool rollback)
4000{
4001 struct efx_ef10_filter_table *table = efx->filter_state;
4002 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4003 struct efx_filter_spec spec;
4004 u8 baddr[ETH_ALEN];
4005 int rc;
4006
4007 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4008 EFX_FILTER_FLAG_RX_RSS,
4009 0);
4010
4011 if (multicast)
4012 efx_filter_set_mc_def(&spec);
4013 else
4014 efx_filter_set_uc_def(&spec);
4015
4016 rc = efx_ef10_filter_insert(efx, &spec, true);
4017 if (rc < 0) {
4018 netif_warn(efx, drv, efx->net_dev,
4019 "%scast mismatch filter insert failed rc=%d\n",
4020 multicast ? "Multi" : "Uni", rc);
4021 } else if (multicast) {
4022 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4023 if (!nic_data->workaround_26807) {
4024 /* Also need an Ethernet broadcast filter */
4025 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4026 EFX_FILTER_FLAG_RX_RSS,
4027 0);
4028 eth_broadcast_addr(baddr);
4029 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
4030 baddr);
4031 rc = efx_ef10_filter_insert(efx, &spec, true);
4032 if (rc < 0) {
4033 netif_warn(efx, drv, efx->net_dev,
4034 "Broadcast filter insert failed rc=%d\n",
4035 rc);
4036 if (rollback) {
4037 /* Roll back the mc_def filter */
4038 efx_ef10_filter_remove_unsafe(
4039 efx, EFX_FILTER_PRI_AUTO,
4040 table->mcdef_id);
4041 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
4042 return rc;
4043 }
4044 } else {
4045 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4046 }
4047 }
4048 rc = 0;
4049 } else {
4050 table->ucdef_id = rc;
4051 rc = 0;
4052 }
4053 return rc;
822b96f8
DP		 4054}
4055
4056/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4057 * flag or removes these filters, we don't need to hold the filter_lock while
4058 * scanning for these filters.
4059 */
4060static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4061{
4062 struct efx_ef10_filter_table *table = efx->filter_state;
4063 bool remove_failed = false;
4064 int i;
8127d661 4065
8127d661
BH		 4066 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4067 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 4068 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
7665d1ab 4069 if (efx_ef10_filter_remove_internal(
fbd79120
BH		 4070 efx, 1U << EFX_FILTER_PRI_AUTO,
4071 i, true) < 0)
8127d661
BH		 4072 remove_failed = true;
4073 }
4074 }
4075 WARN_ON(remove_failed);
4076}
4077
7a186f47
DP		 4078static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4079{
4080 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4081 u8 mac_old[ETH_ALEN];
4082 int rc, rc2;
4083
4084 /* Only reconfigure a PF-created vport */
4085 if (is_zero_ether_addr(nic_data->vport_mac))
4086 return 0;
4087
4088 efx_device_detach_sync(efx);
4089 efx_net_stop(efx->net_dev);
4090 down_write(&efx->filter_sem);
4091 efx_ef10_filter_table_remove(efx);
4092 up_write(&efx->filter_sem);
4093
4094 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4095 if (rc)
4096 goto restore_filters;
4097
4098 ether_addr_copy(mac_old, nic_data->vport_mac);
4099 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4100 nic_data->vport_mac);
4101 if (rc)
4102 goto restore_vadaptor;
4103
4104 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4105 efx->net_dev->dev_addr);
4106 if (!rc) {
4107 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4108 } else {
4109 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4110 if (rc2) {
4111 /* Failed to add original MAC, so clear vport_mac */
4112 eth_zero_addr(nic_data->vport_mac);
4113 goto reset_nic;
4114 }
4115 }
4116
4117restore_vadaptor:
4118 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4119 if (rc2)
4120 goto reset_nic;
4121restore_filters:
4122 down_write(&efx->filter_sem);
4123 rc2 = efx_ef10_filter_table_probe(efx);
4124 up_write(&efx->filter_sem);
4125 if (rc2)
4126 goto reset_nic;
4127
4128 rc2 = efx_net_open(efx->net_dev);
4129 if (rc2)
4130 goto reset_nic;
4131
4132 netif_device_attach(efx->net_dev);
4133
4134 return rc;
4135
4136reset_nic:
4137 netif_err(efx, drv, efx->net_dev,
4138 "Failed to restore when changing MAC address - scheduling reset\n");
4139 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4140
4141 return rc ? rc : rc2;
4142}
4143
822b96f8
DP		 4144/* Caller must hold efx->filter_sem for read if race against
4145 * efx_ef10_filter_table_remove() is possible
4146 */
4147static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4148{
4149 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 4150 struct efx_ef10_nic_data *nic_data = efx->nic_data;
822b96f8
DP		 4151 struct net_device *net_dev = efx->net_dev;
4152 bool uc_promisc = false, mc_promisc = false;
4153
4154 if (!efx_dev_registered(efx))
4155 return;
4156
4157 if (!table)
4158 return;
4159
4160 efx_ef10_filter_mark_old(efx);
4161
4162 /* Copy/convert the address lists; add the primary station
4163 * address and broadcast address
4164 */
4165 netif_addr_lock_bh(net_dev);
4166 efx_ef10_filter_uc_addr_list(efx, &uc_promisc);
4167 efx_ef10_filter_mc_addr_list(efx, &mc_promisc);
4168 netif_addr_unlock_bh(net_dev);
4169
12fb0da4
EC		 4170 /* Insert/renew unicast filters */
4171 if (uc_promisc) {
4172 efx_ef10_filter_insert_def(efx, false, false);
4173 efx_ef10_filter_insert_addr_list(efx, false, false);
4174 } else {
4175 /* If any of the filters failed to insert, fall back to
4176 * promiscuous mode - add in the uc_def filter. But keep
4177 * our individual unicast filters.
4178 */
4179 if (efx_ef10_filter_insert_addr_list(efx, false, false))
4180 efx_ef10_filter_insert_def(efx, false, false);
4181 }
ab8b1f7c 4182
12fb0da4 4183 /* Insert/renew multicast filters */
ab8b1f7c
DP		 4184 /* If changing promiscuous state with cascaded multicast filters, remove
4185 * old filters first, so that packets are dropped rather than duplicated
4186 */
4187 if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc)
4188 efx_ef10_filter_remove_old(efx);
12fb0da4
EC		 4189 if (mc_promisc) {
4190 if (nic_data->workaround_26807) {
4191 /* If we failed to insert promiscuous filters, rollback
4192 * and fall back to individual multicast filters
4193 */
4194 if (efx_ef10_filter_insert_def(efx, true, true)) {
4195 /* Changing promisc state, so remove old filters */
4196 efx_ef10_filter_remove_old(efx);
4197 efx_ef10_filter_insert_addr_list(efx, true, false);
4198 }
4199 } else {
4200 /* If we failed to insert promiscuous filters, don't
4201 * rollback. Regardless, also insert the mc_list
4202 */
4203 efx_ef10_filter_insert_def(efx, true, false);
4204 efx_ef10_filter_insert_addr_list(efx, true, false);
4205 }
4206 } else {
4207 /* If any filters failed to insert, rollback and fall back to
4208 * promiscuous mode - mc_def filter and maybe broadcast. If
4209 * that fails, roll back again and insert as many of our
4210 * individual multicast filters as we can.
4211 */
4212 if (efx_ef10_filter_insert_addr_list(efx, true, true)) {
4213 /* Changing promisc state, so remove old filters */
4214 if (nic_data->workaround_26807)
4215 efx_ef10_filter_remove_old(efx);
4216 if (efx_ef10_filter_insert_def(efx, true, true))
4217 efx_ef10_filter_insert_addr_list(efx, true, false);
4218 }
4219 }
822b96f8
DP		 4220
4221 efx_ef10_filter_remove_old(efx);
ab8b1f7c 4222 efx->mc_promisc = mc_promisc;
822b96f8
DP		 4223}
4224
910c8789
SS		 4225static int efx_ef10_set_mac_address(struct efx_nic *efx)
4226{
4227 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4228 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4229 bool was_enabled = efx->port_enabled;
4230 int rc;
4231
4232 efx_device_detach_sync(efx);
4233 efx_net_stop(efx->net_dev);
4234 down_write(&efx->filter_sem);
4235 efx_ef10_filter_table_remove(efx);
4236
4237 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4238 efx->net_dev->dev_addr);
4239 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4240 nic_data->vport_id);
535a6177
DP		 4241 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4242 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 4243
4244 efx_ef10_filter_table_probe(efx);
4245 up_write(&efx->filter_sem);
4246 if (was_enabled)
4247 efx_net_open(efx->net_dev);
4248 netif_device_attach(efx->net_dev);
4249
9e9f665a
DP		 4250#ifdef CONFIG_SFC_SRIOV
4251 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 4252 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4253
9e9f665a
DP		 4254 if (rc == -EPERM) {
4255 struct efx_nic *efx_pf;
910c8789 4256
9e9f665a
DP		 4257 /* Switch to PF and change MAC address on vport */
4258 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 4259
9e9f665a
DP		 4260 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4261 nic_data->vf_index,
4262 efx->net_dev->dev_addr);
4263 } else if (!rc) {
910c8789
SS		 4264 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4265 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4266 unsigned int i;
4267
9e9f665a
DP		 4268 /* MAC address successfully changed by VF (with MAC
4269 * spoofing) so update the parent PF if possible.
4270 */
910c8789
SS		 4271 for (i = 0; i < efx_pf->vf_count; ++i) {
4272 struct ef10_vf *vf = nic_data->vf + i;
4273
4274 if (vf->efx == efx) {
4275 ether_addr_copy(vf->mac,
4276 efx->net_dev->dev_addr);
4277 return 0;
4278 }
4279 }
4280 }
9e9f665a 4281 } else
910c8789 4282#endif
9e9f665a
DP		 4283 if (rc == -EPERM) {
4284 netif_err(efx, drv, efx->net_dev,
4285 "Cannot change MAC address; use sfboot to enable"
4286 " mac-spoofing on this interface\n");
7a186f47
DP		 4287 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4288 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4289 * fall-back to the method of changing the MAC address on the
4290 * vport. This only applies to PFs because such versions of
4291 * MCFW do not support VFs.
4292 */
4293 rc = efx_ef10_vport_set_mac_address(efx);
535a6177
DP		 4294 } else {
4295 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4296 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 4297 }
4298
910c8789
SS		 4299 return rc;
4300}
4301
8127d661
BH		 4302static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4303{
4304 efx_ef10_filter_sync_rx_mode(efx);
4305
4306 return efx_mcdi_set_mac(efx);
4307}
4308
862f894c
SS		 4309static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4310{
4311 efx_ef10_filter_sync_rx_mode(efx);
4312
4313 return 0;
4314}
4315
74cd60a4
JC		 4316static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4317{
4318 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4319
4320 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4321 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4322 NULL, 0, NULL);
4323}
4324
4325/* MC BISTs follow a different poll mechanism to phy BISTs.
4326 * The BIST is done in the poll handler on the MC, and the MCDI command
4327 * will block until the BIST is done.
4328 */
4329static int efx_ef10_poll_bist(struct efx_nic *efx)
4330{
4331 int rc;
4332 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4333 size_t outlen;
4334 u32 result;
4335
4336 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4337 outbuf, sizeof(outbuf), &outlen);
4338 if (rc != 0)
4339 return rc;
4340
4341 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4342 return -EIO;
4343
4344 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4345 switch (result) {
4346 case MC_CMD_POLL_BIST_PASSED:
4347 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4348 return 0;
4349 case MC_CMD_POLL_BIST_TIMEOUT:
4350 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4351 return -EIO;
4352 case MC_CMD_POLL_BIST_FAILED:
4353 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4354 return -EIO;
4355 default:
4356 netif_err(efx, hw, efx->net_dev,
4357 "BIST returned unknown result %u", result);
4358 return -EIO;
4359 }
4360}
4361
4362static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4363{
4364 int rc;
4365
4366 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4367
4368 rc = efx_ef10_start_bist(efx, bist_type);
4369 if (rc != 0)
4370 return rc;
4371
4372 return efx_ef10_poll_bist(efx);
4373}
4374
4375static int
4376efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4377{
4378 int rc, rc2;
4379
4380 efx_reset_down(efx, RESET_TYPE_WORLD);
4381
4382 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4383 NULL, 0, NULL, 0, NULL);
4384 if (rc != 0)
4385 goto out;
4386
4387 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4388 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4389
4390 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4391
4392out:
27324820
DP		 4393 if (rc == -EPERM)
4394 rc = 0;
74cd60a4
JC		 4395 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4396 return rc ? rc : rc2;
4397}
4398
8127d661
BH		 4399#ifdef CONFIG_SFC_MTD
4400
4401struct efx_ef10_nvram_type_info {
4402 u16 type, type_mask;
4403 u8 port;
4404 const char *name;
4405};
4406
4407static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4408 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
4409 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
4410 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
4411 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
4412 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
4413 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
4414 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
4415 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
4416 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 4417 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 4418 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
4419};
4420
4421static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4422 struct efx_mcdi_mtd_partition *part,
4423 unsigned int type)
4424{
4425 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4426 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4427 const struct efx_ef10_nvram_type_info *info;
4428 size_t size, erase_size, outlen;
4429 bool protected;
4430 int rc;
4431
4432 for (info = efx_ef10_nvram_types; ; info++) {
4433 if (info ==
4434 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4435 return -ENODEV;
4436 if ((type & ~info->type_mask) == info->type)
4437 break;
4438 }
4439 if (info->port != efx_port_num(efx))
4440 return -ENODEV;
4441
4442 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4443 if (rc)
4444 return rc;
4445 if (protected)
4446 return -ENODEV; /* hide it */
4447
4448 part->nvram_type = type;
4449
4450 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4451 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4452 outbuf, sizeof(outbuf), &outlen);
4453 if (rc)
4454 return rc;
4455 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4456 return -EIO;
4457 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4458 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4459 part->fw_subtype = MCDI_DWORD(outbuf,
4460 NVRAM_METADATA_OUT_SUBTYPE);
4461
4462 part->common.dev_type_name = "EF10 NVRAM manager";
4463 part->common.type_name = info->name;
4464
4465 part->common.mtd.type = MTD_NORFLASH;
4466 part->common.mtd.flags = MTD_CAP_NORFLASH;
4467 part->common.mtd.size = size;
4468 part->common.mtd.erasesize = erase_size;
4469
4470 return 0;
4471}
4472
4473static int efx_ef10_mtd_probe(struct efx_nic *efx)
4474{
4475 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4476 struct efx_mcdi_mtd_partition *parts;
4477 size_t outlen, n_parts_total, i, n_parts;
4478 unsigned int type;
4479 int rc;
4480
4481 ASSERT_RTNL();
4482
4483 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4484 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4485 outbuf, sizeof(outbuf), &outlen);
4486 if (rc)
4487 return rc;
4488 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4489 return -EIO;
4490
4491 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4492 if (n_parts_total >
4493 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4494 return -EIO;
4495
4496 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4497 if (!parts)
4498 return -ENOMEM;
4499
4500 n_parts = 0;
4501 for (i = 0; i < n_parts_total; i++) {
4502 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4503 i);
4504 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4505 if (rc == 0)
4506 n_parts++;
4507 else if (rc != -ENODEV)
4508 goto fail;
4509 }
4510
4511 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4512fail:
4513 if (rc)
4514 kfree(parts);
4515 return rc;
4516}
4517
4518#endif /* CONFIG_SFC_MTD */
4519
4520static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4521{
4522 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4523}
4524
02246a7f
SS		 4525static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4526 u32 host_time) {}
4527
bd9a265d
JC		 4528static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4529 bool temp)
4530{
4531 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4532 int rc;
4533
4534 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4535 channel->sync_events_state == SYNC_EVENTS_VALID ||
4536 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4537 return 0;
4538 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4539
4540 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4541 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4542 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4543 channel->channel);
4544
4545 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4546 inbuf, sizeof(inbuf), NULL, 0, NULL);
4547
4548 if (rc != 0)
4549 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4550 SYNC_EVENTS_DISABLED;
4551
4552 return rc;
4553}
4554
4555static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4556 bool temp)
4557{
4558 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4559 int rc;
4560
4561 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4562 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4563 return 0;
4564 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
4565 channel->sync_events_state = SYNC_EVENTS_DISABLED;
4566 return 0;
4567 }
4568 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4569 SYNC_EVENTS_DISABLED;
4570
4571 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4572 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4573 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4574 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4575 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4576 channel->channel);
4577
4578 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4579 inbuf, sizeof(inbuf), NULL, 0, NULL);
4580
4581 return rc;
4582}
4583
4584static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4585 bool temp)
4586{
4587 int (*set)(struct efx_channel *channel, bool temp);
4588 struct efx_channel *channel;
4589
4590 set = en ?
4591 efx_ef10_rx_enable_timestamping :
4592 efx_ef10_rx_disable_timestamping;
4593
4594 efx_for_each_channel(channel, efx) {
4595 int rc = set(channel, temp);
4596 if (en && rc != 0) {
4597 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4598 return rc;
4599 }
4600 }
4601
4602 return 0;
4603}
4604
02246a7f
SS		 4605static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4606 struct hwtstamp_config *init)
4607{
4608 return -EOPNOTSUPP;
4609}
4610
bd9a265d
JC		 4611static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4612 struct hwtstamp_config *init)
4613{
4614 int rc;
4615
4616 switch (init->rx_filter) {
4617 case HWTSTAMP_FILTER_NONE:
4618 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4619 /* if TX timestamping is still requested then leave PTP on */
4620 return efx_ptp_change_mode(efx,
4621 init->tx_type != HWTSTAMP_TX_OFF, 0);
4622 case HWTSTAMP_FILTER_ALL:
4623 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4624 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4625 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4626 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4627 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4628 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4629 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4630 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4631 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4632 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4633 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4634 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4635 init->rx_filter = HWTSTAMP_FILTER_ALL;
4636 rc = efx_ptp_change_mode(efx, true, 0);
4637 if (!rc)
4638 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4639 if (rc)
4640 efx_ptp_change_mode(efx, false, 0);
4641 return rc;
4642 default:
4643 return -ERANGE;
4644 }
4645}
4646
02246a7f 4647const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 4648 .is_vf = true,
02246a7f
SS		 4649 .mem_bar = EFX_MEM_VF_BAR,
4650 .mem_map_size = efx_ef10_mem_map_size,
4651 .probe = efx_ef10_probe_vf,
4652 .remove = efx_ef10_remove,
4653 .dimension_resources = efx_ef10_dimension_resources,
4654 .init = efx_ef10_init_nic,
4655 .fini = efx_port_dummy_op_void,
087e9025 4656 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 4657 .map_reset_flags = efx_ef10_map_reset_flags,
4658 .reset = efx_ef10_reset,
4659 .probe_port = efx_mcdi_port_probe,
4660 .remove_port = efx_mcdi_port_remove,
4661 .fini_dmaq = efx_ef10_fini_dmaq,
4662 .prepare_flr = efx_ef10_prepare_flr,
4663 .finish_flr = efx_port_dummy_op_void,
4664 .describe_stats = efx_ef10_describe_stats,
d7788196 4665 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 4666 .start_stats = efx_port_dummy_op_void,
4667 .pull_stats = efx_port_dummy_op_void,
4668 .stop_stats = efx_port_dummy_op_void,
4669 .set_id_led = efx_mcdi_set_id_led,
4670 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 4671 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 4672 .check_mac_fault = efx_mcdi_mac_check_fault,
4673 .reconfigure_port = efx_mcdi_port_reconfigure,
4674 .get_wol = efx_ef10_get_wol_vf,
4675 .set_wol = efx_ef10_set_wol_vf,
4676 .resume_wol = efx_port_dummy_op_void,
4677 .mcdi_request = efx_ef10_mcdi_request,
4678 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4679 .mcdi_read_response = efx_ef10_mcdi_read_response,
4680 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 4681 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 4682 .irq_enable_master = efx_port_dummy_op_void,
4683 .irq_test_generate = efx_ef10_irq_test_generate,
4684 .irq_disable_non_ev = efx_port_dummy_op_void,
4685 .irq_handle_msi = efx_ef10_msi_interrupt,
4686 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4687 .tx_probe = efx_ef10_tx_probe,
4688 .tx_init = efx_ef10_tx_init,
4689 .tx_remove = efx_ef10_tx_remove,
4690 .tx_write = efx_ef10_tx_write,
267c0157 4691 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
02246a7f
SS		 4692 .rx_probe = efx_ef10_rx_probe,
4693 .rx_init = efx_ef10_rx_init,
4694 .rx_remove = efx_ef10_rx_remove,
4695 .rx_write = efx_ef10_rx_write,
4696 .rx_defer_refill = efx_ef10_rx_defer_refill,
4697 .ev_probe = efx_ef10_ev_probe,
4698 .ev_init = efx_ef10_ev_init,
4699 .ev_fini = efx_ef10_ev_fini,
4700 .ev_remove = efx_ef10_ev_remove,
4701 .ev_process = efx_ef10_ev_process,
4702 .ev_read_ack = efx_ef10_ev_read_ack,
4703 .ev_test_generate = efx_ef10_ev_test_generate,
4704 .filter_table_probe = efx_ef10_filter_table_probe,
4705 .filter_table_restore = efx_ef10_filter_table_restore,
4706 .filter_table_remove = efx_ef10_filter_table_remove,
4707 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4708 .filter_insert = efx_ef10_filter_insert,
4709 .filter_remove_safe = efx_ef10_filter_remove_safe,
4710 .filter_get_safe = efx_ef10_filter_get_safe,
4711 .filter_clear_rx = efx_ef10_filter_clear_rx,
4712 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4713 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4714 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4715#ifdef CONFIG_RFS_ACCEL
4716 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4717 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4718#endif
4719#ifdef CONFIG_SFC_MTD
4720 .mtd_probe = efx_port_dummy_op_int,
4721#endif
4722 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4723 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4724#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 4725 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4726 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4727 .vswitching_remove = efx_ef10_vswitching_remove_vf,
1d051e00 4728 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
02246a7f 4729#endif
0d5e0fbb 4730 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 4731 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 4732
02246a7f
SS		 4733 .revision = EFX_REV_HUNT_A0,
4734 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4735 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4736 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4737 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4738 .can_rx_scatter = true,
4739 .always_rx_scatter = true,
4740 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4741 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4742 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4743 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4744 .mcdi_max_ver = 2,
4745 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4746 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4747 1 << HWTSTAMP_FILTER_ALL,
4748};
4749
8127d661 4750const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 4751 .is_vf = false,
02246a7f 4752 .mem_bar = EFX_MEM_BAR,
8127d661 4753 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 4754 .probe = efx_ef10_probe_pf,
8127d661
BH		 4755 .remove = efx_ef10_remove,
4756 .dimension_resources = efx_ef10_dimension_resources,
4757 .init = efx_ef10_init_nic,
4758 .fini = efx_port_dummy_op_void,
087e9025 4759 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 4760 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 4761 .reset = efx_ef10_reset,
8127d661
BH		 4762 .probe_port = efx_mcdi_port_probe,
4763 .remove_port = efx_mcdi_port_remove,
4764 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 4765 .prepare_flr = efx_ef10_prepare_flr,
4766 .finish_flr = efx_port_dummy_op_void,
8127d661 4767 .describe_stats = efx_ef10_describe_stats,
d7788196 4768 .update_stats = efx_ef10_update_stats_pf,
8127d661 4769 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 4770 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 4771 .stop_stats = efx_mcdi_mac_stop_stats,
4772 .set_id_led = efx_mcdi_set_id_led,
4773 .push_irq_moderation = efx_ef10_push_irq_moderation,
4774 .reconfigure_mac = efx_ef10_mac_reconfigure,
4775 .check_mac_fault = efx_mcdi_mac_check_fault,
4776 .reconfigure_port = efx_mcdi_port_reconfigure,
4777 .get_wol = efx_ef10_get_wol,
4778 .set_wol = efx_ef10_set_wol,
4779 .resume_wol = efx_port_dummy_op_void,
74cd60a4 4780 .test_chip = efx_ef10_test_chip,
8127d661
BH		 4781 .test_nvram = efx_mcdi_nvram_test_all,
4782 .mcdi_request = efx_ef10_mcdi_request,
4783 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4784 .mcdi_read_response = efx_ef10_mcdi_read_response,
4785 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 4786 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 4787 .irq_enable_master = efx_port_dummy_op_void,
4788 .irq_test_generate = efx_ef10_irq_test_generate,
4789 .irq_disable_non_ev = efx_port_dummy_op_void,
4790 .irq_handle_msi = efx_ef10_msi_interrupt,
4791 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4792 .tx_probe = efx_ef10_tx_probe,
4793 .tx_init = efx_ef10_tx_init,
4794 .tx_remove = efx_ef10_tx_remove,
4795 .tx_write = efx_ef10_tx_write,
267c0157 4796 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
8127d661
BH		 4797 .rx_probe = efx_ef10_rx_probe,
4798 .rx_init = efx_ef10_rx_init,
4799 .rx_remove = efx_ef10_rx_remove,
4800 .rx_write = efx_ef10_rx_write,
4801 .rx_defer_refill = efx_ef10_rx_defer_refill,
4802 .ev_probe = efx_ef10_ev_probe,
4803 .ev_init = efx_ef10_ev_init,
4804 .ev_fini = efx_ef10_ev_fini,
4805 .ev_remove = efx_ef10_ev_remove,
4806 .ev_process = efx_ef10_ev_process,
4807 .ev_read_ack = efx_ef10_ev_read_ack,
4808 .ev_test_generate = efx_ef10_ev_test_generate,
4809 .filter_table_probe = efx_ef10_filter_table_probe,
4810 .filter_table_restore = efx_ef10_filter_table_restore,
4811 .filter_table_remove = efx_ef10_filter_table_remove,
4812 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4813 .filter_insert = efx_ef10_filter_insert,
4814 .filter_remove_safe = efx_ef10_filter_remove_safe,
4815 .filter_get_safe = efx_ef10_filter_get_safe,
4816 .filter_clear_rx = efx_ef10_filter_clear_rx,
4817 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4818 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4819 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4820#ifdef CONFIG_RFS_ACCEL
4821 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4822 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4823#endif
4824#ifdef CONFIG_SFC_MTD
4825 .mtd_probe = efx_ef10_mtd_probe,
4826 .mtd_rename = efx_mcdi_mtd_rename,
4827 .mtd_read = efx_mcdi_mtd_read,
4828 .mtd_erase = efx_mcdi_mtd_erase,
4829 .mtd_write = efx_mcdi_mtd_write,
4830 .mtd_sync = efx_mcdi_mtd_sync,
4831#endif
4832 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 4833 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4834 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
7fa8d547 4835#ifdef CONFIG_SFC_SRIOV
834e23dd 4836 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 4837 .sriov_init = efx_ef10_sriov_init,
4838 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 4839 .sriov_wanted = efx_ef10_sriov_wanted,
4840 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 4841 .sriov_flr = efx_ef10_sriov_flr,
4842 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4843 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4844 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4845 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 4846 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 4847 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4848 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4849 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 4850#endif
0d5e0fbb 4851 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 4852 .set_mac_address = efx_ef10_set_mac_address,
8127d661
BH		 4853
4854 .revision = EFX_REV_HUNT_A0,
4855 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4856 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4857 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 4858 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 4859 .can_rx_scatter = true,
4860 .always_rx_scatter = true,
4861 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4862 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4863 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4864 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4865 .mcdi_max_ver = 2,
4866 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 4867 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4868 1 << HWTSTAMP_FILTER_ALL,
8127d661 4869};
Linux kernel - Deliverables
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