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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2005-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
8ceee660 | 20 | #include <linux/ethtool.h> |
aa6ef27e | 21 | #include <linux/topology.h> |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
626950db | 23 | #include <linux/aer.h> |
b28405b0 | 24 | #include <linux/interrupt.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
dd40781e | 28 | #include "selftest.h" |
7fa8d547 | 29 | #include "sriov.h" |
8ceee660 | 30 | |
8880f4ec | 31 | #include "mcdi.h" |
fd371e32 | 32 | #include "workarounds.h" |
8880f4ec | 33 | |
c459302d BH |
34 | /************************************************************************** |
35 | * | |
36 | * Type name strings | |
37 | * | |
38 | ************************************************************************** | |
39 | */ | |
40 | ||
41 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
42 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 43 | const char *const efx_loopback_mode_names[] = { |
c459302d | 44 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 45 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
46 | [LOOPBACK_GMAC] = "GMAC", |
47 | [LOOPBACK_XGMII] = "XGMII", | |
48 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
49 | [LOOPBACK_XAUI] = "XAUI", |
50 | [LOOPBACK_GMII] = "GMII", | |
51 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
52 | [LOOPBACK_XGBR] = "XGBR", |
53 | [LOOPBACK_XFI] = "XFI", | |
54 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
55 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
56 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
57 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
58 | [LOOPBACK_GPHY] = "GPHY", |
59 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
60 | [LOOPBACK_PCS] = "PCS", |
61 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
62 | [LOOPBACK_XPORT] = "XPORT", |
63 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 64 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
65 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
66 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 67 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
68 | [LOOPBACK_XFI_WS] = "XFI_WS", |
69 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 70 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
71 | }; |
72 | ||
c459302d | 73 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 74 | const char *const efx_reset_type_names[] = { |
626950db AR |
75 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
76 | [RESET_TYPE_ALL] = "ALL", | |
77 | [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", | |
78 | [RESET_TYPE_WORLD] = "WORLD", | |
79 | [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", | |
087e9025 | 80 | [RESET_TYPE_DATAPATH] = "DATAPATH", |
e283546c | 81 | [RESET_TYPE_MC_BIST] = "MC_BIST", |
626950db AR |
82 | [RESET_TYPE_DISABLE] = "DISABLE", |
83 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
84 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
85 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
3de82b91 | 86 | [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", |
626950db AR |
87 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", |
88 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", | |
e283546c | 89 | [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)", |
c459302d BH |
90 | }; |
91 | ||
1ab00629 SH |
92 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
93 | * queued onto this work queue. This is not a per-nic work queue, because | |
94 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
95 | */ | |
96 | static struct workqueue_struct *reset_workqueue; | |
97 | ||
74cd60a4 JC |
98 | /* How often and how many times to poll for a reset while waiting for a |
99 | * BIST that another function started to complete. | |
100 | */ | |
101 | #define BIST_WAIT_DELAY_MS 100 | |
102 | #define BIST_WAIT_DELAY_COUNT 100 | |
103 | ||
8ceee660 BH |
104 | /************************************************************************** |
105 | * | |
106 | * Configurable values | |
107 | * | |
108 | *************************************************************************/ | |
109 | ||
8ceee660 BH |
110 | /* |
111 | * Use separate channels for TX and RX events | |
112 | * | |
28b581ab NT |
113 | * Set this to 1 to use separate channels for TX and RX. It allows us |
114 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 115 | * |
28b581ab | 116 | * This is only used in MSI-X interrupt mode |
8ceee660 | 117 | */ |
b0fbdae1 SS |
118 | bool efx_separate_tx_channels; |
119 | module_param(efx_separate_tx_channels, bool, 0444); | |
120 | MODULE_PARM_DESC(efx_separate_tx_channels, | |
28b581ab | 121 | "Use separate channels for TX and RX"); |
8ceee660 BH |
122 | |
123 | /* This is the weight assigned to each of the (per-channel) virtual | |
124 | * NAPI devices. | |
125 | */ | |
126 | static int napi_weight = 64; | |
127 | ||
128 | /* This is the time (in jiffies) between invocations of the hardware | |
626950db AR |
129 | * monitor. |
130 | * On Falcon-based NICs, this will: | |
e254c274 BH |
131 | * - Check the on-board hardware monitor; |
132 | * - Poll the link state and reconfigure the hardware as necessary. | |
626950db AR |
133 | * On Siena-based NICs for power systems with EEH support, this will give EEH a |
134 | * chance to start. | |
8ceee660 | 135 | */ |
d215697f | 136 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 137 | |
8ceee660 BH |
138 | /* Initial interrupt moderation settings. They can be modified after |
139 | * module load with ethtool. | |
140 | * | |
141 | * The default for RX should strike a balance between increasing the | |
142 | * round-trip latency and reducing overhead. | |
143 | */ | |
144 | static unsigned int rx_irq_mod_usec = 60; | |
145 | ||
146 | /* Initial interrupt moderation settings. They can be modified after | |
147 | * module load with ethtool. | |
148 | * | |
149 | * This default is chosen to ensure that a 10G link does not go idle | |
150 | * while a TX queue is stopped after it has become full. A queue is | |
151 | * restarted when it drops below half full. The time this takes (assuming | |
152 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
153 | * 512 / 3 * 1.2 = 205 usec. | |
154 | */ | |
155 | static unsigned int tx_irq_mod_usec = 150; | |
156 | ||
157 | /* This is the first interrupt mode to try out of: | |
158 | * 0 => MSI-X | |
159 | * 1 => MSI | |
160 | * 2 => legacy | |
161 | */ | |
162 | static unsigned int interrupt_mode; | |
163 | ||
164 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
165 | * i.e. the number of CPUs among which we may distribute simultaneous | |
166 | * interrupt handling. | |
167 | * | |
168 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 169 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
170 | */ |
171 | static unsigned int rss_cpus; | |
172 | module_param(rss_cpus, uint, 0444); | |
173 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
174 | ||
b9cc977d BH |
175 | static bool phy_flash_cfg; |
176 | module_param(phy_flash_cfg, bool, 0644); | |
84ae48fe BH |
177 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); |
178 | ||
e7bed9c8 | 179 | static unsigned irq_adapt_low_thresh = 8000; |
6fb70fd1 BH |
180 | module_param(irq_adapt_low_thresh, uint, 0644); |
181 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
182 | "Threshold score for reducing IRQ moderation"); | |
183 | ||
e7bed9c8 | 184 | static unsigned irq_adapt_high_thresh = 16000; |
6fb70fd1 BH |
185 | module_param(irq_adapt_high_thresh, uint, 0644); |
186 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
187 | "Threshold score for increasing IRQ moderation"); | |
188 | ||
62776d03 BH |
189 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
190 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
191 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
192 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
193 | module_param(debug, uint, 0); | |
194 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
195 | ||
8ceee660 BH |
196 | /************************************************************************** |
197 | * | |
198 | * Utility functions and prototypes | |
199 | * | |
200 | *************************************************************************/ | |
4642610c | 201 | |
261e4d96 | 202 | static int efx_soft_enable_interrupts(struct efx_nic *efx); |
d8291187 | 203 | static void efx_soft_disable_interrupts(struct efx_nic *efx); |
7f967c01 | 204 | static void efx_remove_channel(struct efx_channel *channel); |
4642610c | 205 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 206 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 207 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 208 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 209 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 210 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
211 | static void efx_fini_struct(struct efx_nic *efx); |
212 | static void efx_start_all(struct efx_nic *efx); | |
213 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
214 | |
215 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
216 | do { \ | |
f16aeea0 | 217 | if ((efx->state == STATE_READY) || \ |
626950db | 218 | (efx->state == STATE_RECOVERY) || \ |
332c1ce9 | 219 | (efx->state == STATE_DISABLED)) \ |
8ceee660 BH |
220 | ASSERT_RTNL(); \ |
221 | } while (0) | |
222 | ||
8b7325b4 BH |
223 | static int efx_check_disabled(struct efx_nic *efx) |
224 | { | |
626950db | 225 | if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { |
8b7325b4 BH |
226 | netif_err(efx, drv, efx->net_dev, |
227 | "device is disabled due to earlier errors\n"); | |
228 | return -EIO; | |
229 | } | |
230 | return 0; | |
231 | } | |
232 | ||
8ceee660 BH |
233 | /************************************************************************** |
234 | * | |
235 | * Event queue processing | |
236 | * | |
237 | *************************************************************************/ | |
238 | ||
239 | /* Process channel's event queue | |
240 | * | |
241 | * This function is responsible for processing the event queue of a | |
242 | * single channel. The caller must guarantee that this function will | |
243 | * never be concurrently called more than once on the same channel, | |
244 | * though different channels may be being processed concurrently. | |
245 | */ | |
fa236e18 | 246 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 247 | { |
c936835c | 248 | struct efx_tx_queue *tx_queue; |
fa236e18 | 249 | int spent; |
8ceee660 | 250 | |
9f2cb71c | 251 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 252 | return 0; |
8ceee660 | 253 | |
c936835c PD |
254 | efx_for_each_channel_tx_queue(tx_queue, channel) { |
255 | tx_queue->pkts_compl = 0; | |
256 | tx_queue->bytes_compl = 0; | |
257 | } | |
258 | ||
fa236e18 | 259 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
260 | if (spent && efx_channel_has_rx_queue(channel)) { |
261 | struct efx_rx_queue *rx_queue = | |
262 | efx_channel_get_rx_queue(channel); | |
263 | ||
ff734ef4 | 264 | efx_rx_flush_packet(channel); |
cce28794 | 265 | efx_fast_push_rx_descriptors(rx_queue, true); |
8ceee660 BH |
266 | } |
267 | ||
c936835c PD |
268 | /* Update BQL */ |
269 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
270 | if (tx_queue->bytes_compl) { | |
271 | netdev_tx_completed_queue(tx_queue->core_txq, | |
272 | tx_queue->pkts_compl, tx_queue->bytes_compl); | |
273 | } | |
274 | } | |
275 | ||
fa236e18 | 276 | return spent; |
8ceee660 BH |
277 | } |
278 | ||
8ceee660 BH |
279 | /* NAPI poll handler |
280 | * | |
281 | * NAPI guarantees serialisation of polls of the same device, which | |
282 | * provides the guarantee required by efx_process_channel(). | |
283 | */ | |
284 | static int efx_poll(struct napi_struct *napi, int budget) | |
285 | { | |
286 | struct efx_channel *channel = | |
287 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 288 | struct efx_nic *efx = channel->efx; |
fa236e18 | 289 | int spent; |
8ceee660 | 290 | |
36763266 AR |
291 | if (!efx_channel_lock_napi(channel)) |
292 | return budget; | |
293 | ||
62776d03 BH |
294 | netif_vdbg(efx, intr, efx->net_dev, |
295 | "channel %d NAPI poll executing on CPU %d\n", | |
296 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 297 | |
fa236e18 | 298 | spent = efx_process_channel(channel, budget); |
8ceee660 | 299 | |
fa236e18 | 300 | if (spent < budget) { |
9d9a6973 | 301 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
302 | efx->irq_rx_adaptive && |
303 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
304 | if (unlikely(channel->irq_mod_score < |
305 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
306 | if (channel->irq_moderation > 1) { |
307 | channel->irq_moderation -= 1; | |
ef2b90ee | 308 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 309 | } |
6fb70fd1 BH |
310 | } else if (unlikely(channel->irq_mod_score > |
311 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
312 | if (channel->irq_moderation < |
313 | efx->irq_rx_moderation) { | |
314 | channel->irq_moderation += 1; | |
ef2b90ee | 315 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 316 | } |
6fb70fd1 | 317 | } |
6fb70fd1 BH |
318 | channel->irq_count = 0; |
319 | channel->irq_mod_score = 0; | |
320 | } | |
321 | ||
64d8ad6d BH |
322 | efx_filter_rfs_expire(channel); |
323 | ||
8ceee660 | 324 | /* There is no race here; although napi_disable() will |
288379f0 | 325 | * only wait for napi_complete(), this isn't a problem |
514bedbc | 326 | * since efx_nic_eventq_read_ack() will have no effect if |
8ceee660 BH |
327 | * interrupts have already been disabled. |
328 | */ | |
288379f0 | 329 | napi_complete(napi); |
514bedbc | 330 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
331 | } |
332 | ||
36763266 | 333 | efx_channel_unlock_napi(channel); |
fa236e18 | 334 | return spent; |
8ceee660 BH |
335 | } |
336 | ||
8ceee660 BH |
337 | /* Create event queue |
338 | * Event queue memory allocations are done only once. If the channel | |
339 | * is reset, the memory buffer will be reused; this guards against | |
340 | * errors during channel reset and also simplifies interrupt handling. | |
341 | */ | |
342 | static int efx_probe_eventq(struct efx_channel *channel) | |
343 | { | |
ecc910f5 SH |
344 | struct efx_nic *efx = channel->efx; |
345 | unsigned long entries; | |
346 | ||
86ee5302 | 347 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 348 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 349 | |
ecc910f5 SH |
350 | /* Build an event queue with room for one event per tx and rx buffer, |
351 | * plus some extra for link state events and MCDI completions. */ | |
352 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
353 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
354 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
355 | ||
152b6a62 | 356 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
357 | } |
358 | ||
359 | /* Prepare channel's event queue */ | |
261e4d96 | 360 | static int efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 361 | { |
15acb1ce | 362 | struct efx_nic *efx = channel->efx; |
261e4d96 JC |
363 | int rc; |
364 | ||
365 | EFX_WARN_ON_PARANOID(channel->eventq_init); | |
366 | ||
15acb1ce | 367 | netif_dbg(efx, drv, efx->net_dev, |
62776d03 | 368 | "chan %d init event queue\n", channel->channel); |
8ceee660 | 369 | |
261e4d96 JC |
370 | rc = efx_nic_init_eventq(channel); |
371 | if (rc == 0) { | |
15acb1ce | 372 | efx->type->push_irq_moderation(channel); |
261e4d96 JC |
373 | channel->eventq_read_ptr = 0; |
374 | channel->eventq_init = true; | |
375 | } | |
376 | return rc; | |
8ceee660 BH |
377 | } |
378 | ||
9f2cb71c | 379 | /* Enable event queue processing and NAPI */ |
36763266 | 380 | void efx_start_eventq(struct efx_channel *channel) |
9f2cb71c BH |
381 | { |
382 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
383 | "chan %d start event queue\n", channel->channel); | |
384 | ||
514bedbc | 385 | /* Make sure the NAPI handler sees the enabled flag set */ |
9f2cb71c BH |
386 | channel->enabled = true; |
387 | smp_wmb(); | |
388 | ||
36763266 | 389 | efx_channel_enable(channel); |
9f2cb71c BH |
390 | napi_enable(&channel->napi_str); |
391 | efx_nic_eventq_read_ack(channel); | |
392 | } | |
393 | ||
394 | /* Disable event queue processing and NAPI */ | |
36763266 | 395 | void efx_stop_eventq(struct efx_channel *channel) |
9f2cb71c BH |
396 | { |
397 | if (!channel->enabled) | |
398 | return; | |
399 | ||
400 | napi_disable(&channel->napi_str); | |
36763266 AR |
401 | while (!efx_channel_disable(channel)) |
402 | usleep_range(1000, 20000); | |
9f2cb71c BH |
403 | channel->enabled = false; |
404 | } | |
405 | ||
8ceee660 BH |
406 | static void efx_fini_eventq(struct efx_channel *channel) |
407 | { | |
be3fc09c BH |
408 | if (!channel->eventq_init) |
409 | return; | |
410 | ||
62776d03 BH |
411 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
412 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 413 | |
152b6a62 | 414 | efx_nic_fini_eventq(channel); |
be3fc09c | 415 | channel->eventq_init = false; |
8ceee660 BH |
416 | } |
417 | ||
418 | static void efx_remove_eventq(struct efx_channel *channel) | |
419 | { | |
62776d03 BH |
420 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
421 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 422 | |
152b6a62 | 423 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
424 | } |
425 | ||
426 | /************************************************************************** | |
427 | * | |
428 | * Channel handling | |
429 | * | |
430 | *************************************************************************/ | |
431 | ||
7f967c01 | 432 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
433 | static struct efx_channel * |
434 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
435 | { | |
436 | struct efx_channel *channel; | |
437 | struct efx_rx_queue *rx_queue; | |
438 | struct efx_tx_queue *tx_queue; | |
439 | int j; | |
440 | ||
7f967c01 BH |
441 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
442 | if (!channel) | |
443 | return NULL; | |
4642610c | 444 | |
7f967c01 BH |
445 | channel->efx = efx; |
446 | channel->channel = i; | |
447 | channel->type = &efx_default_channel_type; | |
4642610c | 448 | |
7f967c01 BH |
449 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
450 | tx_queue = &channel->tx_queue[j]; | |
451 | tx_queue->efx = efx; | |
452 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
453 | tx_queue->channel = channel; | |
454 | } | |
4642610c | 455 | |
7f967c01 BH |
456 | rx_queue = &channel->rx_queue; |
457 | rx_queue->efx = efx; | |
458 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
459 | (unsigned long)rx_queue); | |
4642610c | 460 | |
7f967c01 BH |
461 | return channel; |
462 | } | |
463 | ||
464 | /* Allocate and initialise a channel structure, copying parameters | |
465 | * (but not resources) from an old channel structure. | |
466 | */ | |
467 | static struct efx_channel * | |
468 | efx_copy_channel(const struct efx_channel *old_channel) | |
469 | { | |
470 | struct efx_channel *channel; | |
471 | struct efx_rx_queue *rx_queue; | |
472 | struct efx_tx_queue *tx_queue; | |
473 | int j; | |
4642610c | 474 | |
7f967c01 BH |
475 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
476 | if (!channel) | |
477 | return NULL; | |
478 | ||
479 | *channel = *old_channel; | |
480 | ||
481 | channel->napi_dev = NULL; | |
482 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 483 | |
7f967c01 BH |
484 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
485 | tx_queue = &channel->tx_queue[j]; | |
486 | if (tx_queue->channel) | |
4642610c | 487 | tx_queue->channel = channel; |
7f967c01 BH |
488 | tx_queue->buffer = NULL; |
489 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
490 | } |
491 | ||
4642610c | 492 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
493 | rx_queue->buffer = NULL; |
494 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
495 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
496 | (unsigned long)rx_queue); | |
497 | ||
498 | return channel; | |
499 | } | |
500 | ||
8ceee660 BH |
501 | static int efx_probe_channel(struct efx_channel *channel) |
502 | { | |
503 | struct efx_tx_queue *tx_queue; | |
504 | struct efx_rx_queue *rx_queue; | |
505 | int rc; | |
506 | ||
62776d03 BH |
507 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
508 | "creating channel %d\n", channel->channel); | |
8ceee660 | 509 | |
7f967c01 BH |
510 | rc = channel->type->pre_probe(channel); |
511 | if (rc) | |
512 | goto fail; | |
513 | ||
8ceee660 BH |
514 | rc = efx_probe_eventq(channel); |
515 | if (rc) | |
7f967c01 | 516 | goto fail; |
8ceee660 BH |
517 | |
518 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
519 | rc = efx_probe_tx_queue(tx_queue); | |
520 | if (rc) | |
7f967c01 | 521 | goto fail; |
8ceee660 BH |
522 | } |
523 | ||
524 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
525 | rc = efx_probe_rx_queue(rx_queue); | |
526 | if (rc) | |
7f967c01 | 527 | goto fail; |
8ceee660 BH |
528 | } |
529 | ||
8ceee660 BH |
530 | return 0; |
531 | ||
7f967c01 BH |
532 | fail: |
533 | efx_remove_channel(channel); | |
8ceee660 BH |
534 | return rc; |
535 | } | |
536 | ||
7f967c01 BH |
537 | static void |
538 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
539 | { | |
540 | struct efx_nic *efx = channel->efx; | |
541 | const char *type; | |
542 | int number; | |
543 | ||
544 | number = channel->channel; | |
545 | if (efx->tx_channel_offset == 0) { | |
546 | type = ""; | |
547 | } else if (channel->channel < efx->tx_channel_offset) { | |
548 | type = "-rx"; | |
549 | } else { | |
550 | type = "-tx"; | |
551 | number -= efx->tx_channel_offset; | |
552 | } | |
553 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
554 | } | |
8ceee660 | 555 | |
56536e9c BH |
556 | static void efx_set_channel_names(struct efx_nic *efx) |
557 | { | |
558 | struct efx_channel *channel; | |
56536e9c | 559 | |
7f967c01 BH |
560 | efx_for_each_channel(channel, efx) |
561 | channel->type->get_name(channel, | |
d8291187 BH |
562 | efx->msi_context[channel->channel].name, |
563 | sizeof(efx->msi_context[0].name)); | |
56536e9c BH |
564 | } |
565 | ||
4642610c BH |
566 | static int efx_probe_channels(struct efx_nic *efx) |
567 | { | |
568 | struct efx_channel *channel; | |
569 | int rc; | |
570 | ||
571 | /* Restart special buffer allocation */ | |
572 | efx->next_buffer_table = 0; | |
573 | ||
c92aaff1 BH |
574 | /* Probe channels in reverse, so that any 'extra' channels |
575 | * use the start of the buffer table. This allows the traffic | |
576 | * channels to be resized without moving them or wasting the | |
577 | * entries before them. | |
578 | */ | |
579 | efx_for_each_channel_rev(channel, efx) { | |
4642610c BH |
580 | rc = efx_probe_channel(channel); |
581 | if (rc) { | |
582 | netif_err(efx, probe, efx->net_dev, | |
583 | "failed to create channel %d\n", | |
584 | channel->channel); | |
585 | goto fail; | |
586 | } | |
587 | } | |
588 | efx_set_channel_names(efx); | |
589 | ||
590 | return 0; | |
591 | ||
592 | fail: | |
593 | efx_remove_channels(efx); | |
594 | return rc; | |
595 | } | |
596 | ||
8ceee660 BH |
597 | /* Channels are shutdown and reinitialised whilst the NIC is running |
598 | * to propagate configuration changes (mtu, checksum offload), or | |
599 | * to clear hardware error conditions | |
600 | */ | |
9f2cb71c | 601 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 | 602 | { |
ebfcd0fd | 603 | netdev_features_t old_features = efx->net_dev->features; |
85740cdf | 604 | bool old_rx_scatter = efx->rx_scatter; |
8ceee660 BH |
605 | struct efx_tx_queue *tx_queue; |
606 | struct efx_rx_queue *rx_queue; | |
607 | struct efx_channel *channel; | |
85740cdf | 608 | size_t rx_buf_len; |
8ceee660 | 609 | |
f7f13b0b BH |
610 | /* Calculate the rx buffer allocation parameters required to |
611 | * support the current MTU, including padding for header | |
612 | * alignment and overruns. | |
613 | */ | |
43a3739d | 614 | efx->rx_dma_len = (efx->rx_prefix_size + |
272baeeb BH |
615 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + |
616 | efx->type->rx_buffer_padding); | |
85740cdf | 617 | rx_buf_len = (sizeof(struct efx_rx_page_state) + |
2ec03014 | 618 | efx->rx_ip_align + efx->rx_dma_len); |
85740cdf | 619 | if (rx_buf_len <= PAGE_SIZE) { |
e8c68c0a | 620 | efx->rx_scatter = efx->type->always_rx_scatter; |
85740cdf | 621 | efx->rx_buffer_order = 0; |
85740cdf | 622 | } else if (efx->type->can_rx_scatter) { |
950c54df | 623 | BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES); |
85740cdf | 624 | BUILD_BUG_ON(sizeof(struct efx_rx_page_state) + |
950c54df BH |
625 | 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE, |
626 | EFX_RX_BUF_ALIGNMENT) > | |
627 | PAGE_SIZE); | |
85740cdf BH |
628 | efx->rx_scatter = true; |
629 | efx->rx_dma_len = EFX_RX_USR_BUF_SIZE; | |
630 | efx->rx_buffer_order = 0; | |
85740cdf BH |
631 | } else { |
632 | efx->rx_scatter = false; | |
633 | efx->rx_buffer_order = get_order(rx_buf_len); | |
85740cdf BH |
634 | } |
635 | ||
1648a23f DP |
636 | efx_rx_config_page_split(efx); |
637 | if (efx->rx_buffer_order) | |
638 | netif_dbg(efx, drv, efx->net_dev, | |
639 | "RX buf len=%u; page order=%u batch=%u\n", | |
640 | efx->rx_dma_len, efx->rx_buffer_order, | |
641 | efx->rx_pages_per_batch); | |
642 | else | |
643 | netif_dbg(efx, drv, efx->net_dev, | |
644 | "RX buf len=%u step=%u bpp=%u; page batch=%u\n", | |
645 | efx->rx_dma_len, efx->rx_page_buf_step, | |
646 | efx->rx_bufs_per_page, efx->rx_pages_per_batch); | |
2768935a | 647 | |
ebfcd0fd AR |
648 | /* Restore previously fixed features in hw_features and remove |
649 | * features which are fixed now | |
650 | */ | |
651 | efx->net_dev->hw_features |= efx->net_dev->features; | |
652 | efx->net_dev->hw_features &= ~efx->fixed_features; | |
653 | efx->net_dev->features |= efx->fixed_features; | |
654 | if (efx->net_dev->features != old_features) | |
655 | netdev_features_change(efx->net_dev); | |
656 | ||
e8c68c0a | 657 | /* RX filters may also have scatter-enabled flags */ |
85740cdf | 658 | if (efx->rx_scatter != old_rx_scatter) |
add72477 | 659 | efx->type->filter_update_rx_scatter(efx); |
8ceee660 | 660 | |
14bf718f BH |
661 | /* We must keep at least one descriptor in a TX ring empty. |
662 | * We could avoid this when the queue size does not exactly | |
663 | * match the hardware ring size, but it's not that important. | |
664 | * Therefore we stop the queue when one more skb might fill | |
665 | * the ring completely. We wake it when half way back to | |
666 | * empty. | |
667 | */ | |
668 | efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); | |
669 | efx->txq_wake_thresh = efx->txq_stop_thresh / 2; | |
670 | ||
8ceee660 BH |
671 | /* Initialise the channels */ |
672 | efx_for_each_channel(channel, efx) { | |
3881d8ab | 673 | efx_for_each_channel_tx_queue(tx_queue, channel) { |
bc3c90a2 | 674 | efx_init_tx_queue(tx_queue); |
3881d8ab AR |
675 | atomic_inc(&efx->active_queues); |
676 | } | |
8ceee660 | 677 | |
9f2cb71c | 678 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 679 | efx_init_rx_queue(rx_queue); |
3881d8ab | 680 | atomic_inc(&efx->active_queues); |
cce28794 JC |
681 | efx_stop_eventq(channel); |
682 | efx_fast_push_rx_descriptors(rx_queue, false); | |
683 | efx_start_eventq(channel); | |
9f2cb71c | 684 | } |
8ceee660 | 685 | |
85740cdf | 686 | WARN_ON(channel->rx_pkt_n_frags); |
8ceee660 | 687 | } |
8ceee660 | 688 | |
2ea4dc28 AR |
689 | efx_ptp_start_datapath(efx); |
690 | ||
9f2cb71c BH |
691 | if (netif_device_present(efx->net_dev)) |
692 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
693 | } |
694 | ||
9f2cb71c | 695 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
696 | { |
697 | struct efx_channel *channel; | |
698 | struct efx_tx_queue *tx_queue; | |
699 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 700 | int rc; |
8ceee660 BH |
701 | |
702 | EFX_ASSERT_RESET_SERIALISED(efx); | |
703 | BUG_ON(efx->port_enabled); | |
704 | ||
2ea4dc28 AR |
705 | efx_ptp_stop_datapath(efx); |
706 | ||
d8aec745 BH |
707 | /* Stop RX refill */ |
708 | efx_for_each_channel(channel, efx) { | |
709 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
710 | rx_queue->refill_enabled = false; | |
711 | } | |
712 | ||
8ceee660 | 713 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
714 | /* RX packet processing is pipelined, so wait for the |
715 | * NAPI handler to complete. At least event queue 0 | |
716 | * might be kept active by non-data events, so don't | |
717 | * use napi_synchronize() but actually disable NAPI | |
718 | * temporarily. | |
719 | */ | |
720 | if (efx_channel_has_rx_queue(channel)) { | |
721 | efx_stop_eventq(channel); | |
722 | efx_start_eventq(channel); | |
723 | } | |
e42c3d85 | 724 | } |
8ceee660 | 725 | |
e42c3d85 BH |
726 | rc = efx->type->fini_dmaq(efx); |
727 | if (rc && EFX_WORKAROUND_7803(efx)) { | |
728 | /* Schedule a reset to recover from the flush failure. The | |
729 | * descriptor caches reference memory we're about to free, | |
730 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
731 | * the MACs because of the pending reset. | |
732 | */ | |
733 | netif_err(efx, drv, efx->net_dev, | |
734 | "Resetting to recover from flush failure\n"); | |
735 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
736 | } else if (rc) { | |
737 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); | |
738 | } else { | |
739 | netif_dbg(efx, drv, efx->net_dev, | |
740 | "successfully flushed all queues\n"); | |
741 | } | |
742 | ||
743 | efx_for_each_channel(channel, efx) { | |
8ceee660 BH |
744 | efx_for_each_channel_rx_queue(rx_queue, channel) |
745 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 746 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 747 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
748 | } |
749 | } | |
750 | ||
751 | static void efx_remove_channel(struct efx_channel *channel) | |
752 | { | |
753 | struct efx_tx_queue *tx_queue; | |
754 | struct efx_rx_queue *rx_queue; | |
755 | ||
62776d03 BH |
756 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
757 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
758 | |
759 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
760 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 761 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
762 | efx_remove_tx_queue(tx_queue); |
763 | efx_remove_eventq(channel); | |
c31e5f9f | 764 | channel->type->post_remove(channel); |
8ceee660 BH |
765 | } |
766 | ||
4642610c BH |
767 | static void efx_remove_channels(struct efx_nic *efx) |
768 | { | |
769 | struct efx_channel *channel; | |
770 | ||
771 | efx_for_each_channel(channel, efx) | |
772 | efx_remove_channel(channel); | |
773 | } | |
774 | ||
775 | int | |
776 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
777 | { | |
778 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
779 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 | 780 | unsigned i, next_buffer_table = 0; |
261e4d96 | 781 | int rc, rc2; |
8b7325b4 BH |
782 | |
783 | rc = efx_check_disabled(efx); | |
784 | if (rc) | |
785 | return rc; | |
7f967c01 BH |
786 | |
787 | /* Not all channels should be reallocated. We must avoid | |
788 | * reallocating their buffer table entries. | |
789 | */ | |
790 | efx_for_each_channel(channel, efx) { | |
791 | struct efx_rx_queue *rx_queue; | |
792 | struct efx_tx_queue *tx_queue; | |
793 | ||
794 | if (channel->type->copy) | |
795 | continue; | |
796 | next_buffer_table = max(next_buffer_table, | |
797 | channel->eventq.index + | |
798 | channel->eventq.entries); | |
799 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
800 | next_buffer_table = max(next_buffer_table, | |
801 | rx_queue->rxd.index + | |
802 | rx_queue->rxd.entries); | |
803 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
804 | next_buffer_table = max(next_buffer_table, | |
805 | tx_queue->txd.index + | |
806 | tx_queue->txd.entries); | |
807 | } | |
4642610c | 808 | |
29c69a48 | 809 | efx_device_detach_sync(efx); |
4642610c | 810 | efx_stop_all(efx); |
d8291187 | 811 | efx_soft_disable_interrupts(efx); |
4642610c | 812 | |
7f967c01 | 813 | /* Clone channels (where possible) */ |
4642610c BH |
814 | memset(other_channel, 0, sizeof(other_channel)); |
815 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
816 | channel = efx->channel[i]; |
817 | if (channel->type->copy) | |
818 | channel = channel->type->copy(channel); | |
4642610c BH |
819 | if (!channel) { |
820 | rc = -ENOMEM; | |
821 | goto out; | |
822 | } | |
823 | other_channel[i] = channel; | |
824 | } | |
825 | ||
826 | /* Swap entry counts and channel pointers */ | |
827 | old_rxq_entries = efx->rxq_entries; | |
828 | old_txq_entries = efx->txq_entries; | |
829 | efx->rxq_entries = rxq_entries; | |
830 | efx->txq_entries = txq_entries; | |
831 | for (i = 0; i < efx->n_channels; i++) { | |
832 | channel = efx->channel[i]; | |
833 | efx->channel[i] = other_channel[i]; | |
834 | other_channel[i] = channel; | |
835 | } | |
836 | ||
7f967c01 BH |
837 | /* Restart buffer table allocation */ |
838 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 839 | |
e8f14992 | 840 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
841 | channel = efx->channel[i]; |
842 | if (!channel->type->copy) | |
843 | continue; | |
844 | rc = efx_probe_channel(channel); | |
845 | if (rc) | |
846 | goto rollback; | |
847 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 848 | } |
7f967c01 | 849 | |
4642610c | 850 | out: |
7f967c01 BH |
851 | /* Destroy unused channel structures */ |
852 | for (i = 0; i < efx->n_channels; i++) { | |
853 | channel = other_channel[i]; | |
854 | if (channel && channel->type->copy) { | |
855 | efx_fini_napi_channel(channel); | |
856 | efx_remove_channel(channel); | |
857 | kfree(channel); | |
858 | } | |
859 | } | |
4642610c | 860 | |
261e4d96 JC |
861 | rc2 = efx_soft_enable_interrupts(efx); |
862 | if (rc2) { | |
863 | rc = rc ? rc : rc2; | |
864 | netif_err(efx, drv, efx->net_dev, | |
865 | "unable to restart interrupts on channel reallocation\n"); | |
866 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
867 | } else { | |
868 | efx_start_all(efx); | |
869 | netif_device_attach(efx->net_dev); | |
870 | } | |
4642610c BH |
871 | return rc; |
872 | ||
873 | rollback: | |
874 | /* Swap back */ | |
875 | efx->rxq_entries = old_rxq_entries; | |
876 | efx->txq_entries = old_txq_entries; | |
877 | for (i = 0; i < efx->n_channels; i++) { | |
878 | channel = efx->channel[i]; | |
879 | efx->channel[i] = other_channel[i]; | |
880 | other_channel[i] = channel; | |
881 | } | |
882 | goto out; | |
883 | } | |
884 | ||
90d683af | 885 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 886 | { |
90d683af | 887 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
888 | } |
889 | ||
7f967c01 BH |
890 | static const struct efx_channel_type efx_default_channel_type = { |
891 | .pre_probe = efx_channel_dummy_op_int, | |
c31e5f9f | 892 | .post_remove = efx_channel_dummy_op_void, |
7f967c01 BH |
893 | .get_name = efx_get_channel_name, |
894 | .copy = efx_copy_channel, | |
895 | .keep_eventq = false, | |
896 | }; | |
897 | ||
898 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
899 | { | |
900 | return 0; | |
901 | } | |
902 | ||
c31e5f9f SH |
903 | void efx_channel_dummy_op_void(struct efx_channel *channel) |
904 | { | |
905 | } | |
906 | ||
8ceee660 BH |
907 | /************************************************************************** |
908 | * | |
909 | * Port handling | |
910 | * | |
911 | **************************************************************************/ | |
912 | ||
913 | /* This ensures that the kernel is kept informed (via | |
914 | * netif_carrier_on/off) of the link status, and also maintains the | |
915 | * link status's stop on the port's TX queue. | |
916 | */ | |
fdaa9aed | 917 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 918 | { |
eb50c0d6 BH |
919 | struct efx_link_state *link_state = &efx->link_state; |
920 | ||
8ceee660 BH |
921 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
922 | * that no events are triggered between unregister_netdev() and the | |
923 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
924 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
925 | if (!netif_running(efx->net_dev)) | |
926 | return; | |
927 | ||
eb50c0d6 | 928 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
929 | efx->n_link_state_changes++; |
930 | ||
eb50c0d6 | 931 | if (link_state->up) |
8ceee660 BH |
932 | netif_carrier_on(efx->net_dev); |
933 | else | |
934 | netif_carrier_off(efx->net_dev); | |
935 | } | |
936 | ||
937 | /* Status message for kernel log */ | |
2aa9ef11 | 938 | if (link_state->up) |
62776d03 | 939 | netif_info(efx, link, efx->net_dev, |
964e6135 | 940 | "link up at %uMbps %s-duplex (MTU %d)\n", |
62776d03 | 941 | link_state->speed, link_state->fd ? "full" : "half", |
964e6135 | 942 | efx->net_dev->mtu); |
2aa9ef11 | 943 | else |
62776d03 | 944 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
945 | } |
946 | ||
d3245b28 BH |
947 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
948 | { | |
949 | efx->link_advertising = advertising; | |
950 | if (advertising) { | |
951 | if (advertising & ADVERTISED_Pause) | |
952 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
953 | else | |
954 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
955 | if (advertising & ADVERTISED_Asym_Pause) | |
956 | efx->wanted_fc ^= EFX_FC_TX; | |
957 | } | |
958 | } | |
959 | ||
b5626946 | 960 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
961 | { |
962 | efx->wanted_fc = wanted_fc; | |
963 | if (efx->link_advertising) { | |
964 | if (wanted_fc & EFX_FC_RX) | |
965 | efx->link_advertising |= (ADVERTISED_Pause | | |
966 | ADVERTISED_Asym_Pause); | |
967 | else | |
968 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
969 | ADVERTISED_Asym_Pause); | |
970 | if (wanted_fc & EFX_FC_TX) | |
971 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
972 | } | |
973 | } | |
974 | ||
115122af BH |
975 | static void efx_fini_port(struct efx_nic *efx); |
976 | ||
0d322413 EC |
977 | /* We assume that efx->type->reconfigure_mac will always try to sync RX |
978 | * filters and therefore needs to read-lock the filter table against freeing | |
979 | */ | |
980 | void efx_mac_reconfigure(struct efx_nic *efx) | |
981 | { | |
982 | down_read(&efx->filter_sem); | |
983 | efx->type->reconfigure_mac(efx); | |
984 | up_read(&efx->filter_sem); | |
985 | } | |
986 | ||
d3245b28 BH |
987 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
988 | * the MAC appropriately. All other PHY configuration changes are pushed | |
989 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
990 | * through efx_monitor(). | |
991 | * | |
992 | * Callers must hold the mac_lock | |
993 | */ | |
994 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 995 | { |
d3245b28 BH |
996 | enum efx_phy_mode phy_mode; |
997 | int rc; | |
8ceee660 | 998 | |
d3245b28 | 999 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 1000 | |
d3245b28 BH |
1001 | /* Disable PHY transmit in mac level loopbacks */ |
1002 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
1003 | if (LOOPBACK_INTERNAL(efx)) |
1004 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
1005 | else | |
1006 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 1007 | |
d3245b28 | 1008 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 1009 | |
d3245b28 BH |
1010 | if (rc) |
1011 | efx->phy_mode = phy_mode; | |
177dfcd8 | 1012 | |
d3245b28 | 1013 | return rc; |
8ceee660 BH |
1014 | } |
1015 | ||
1016 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
1017 | * disabled. */ | |
d3245b28 | 1018 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 1019 | { |
d3245b28 BH |
1020 | int rc; |
1021 | ||
8ceee660 BH |
1022 | EFX_ASSERT_RESET_SERIALISED(efx); |
1023 | ||
1024 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 1025 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 1026 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
1027 | |
1028 | return rc; | |
8ceee660 BH |
1029 | } |
1030 | ||
8be4f3e6 BH |
1031 | /* Asynchronous work item for changing MAC promiscuity and multicast |
1032 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
1033 | * MAC directly. */ | |
766ca0fa BH |
1034 | static void efx_mac_work(struct work_struct *data) |
1035 | { | |
1036 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
1037 | ||
1038 | mutex_lock(&efx->mac_lock); | |
30b81cda | 1039 | if (efx->port_enabled) |
0d322413 | 1040 | efx_mac_reconfigure(efx); |
766ca0fa BH |
1041 | mutex_unlock(&efx->mac_lock); |
1042 | } | |
1043 | ||
8ceee660 BH |
1044 | static int efx_probe_port(struct efx_nic *efx) |
1045 | { | |
1046 | int rc; | |
1047 | ||
62776d03 | 1048 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 1049 | |
ff3b00a0 SH |
1050 | if (phy_flash_cfg) |
1051 | efx->phy_mode = PHY_MODE_SPECIAL; | |
1052 | ||
ef2b90ee BH |
1053 | /* Connect up MAC/PHY operations table */ |
1054 | rc = efx->type->probe_port(efx); | |
8ceee660 | 1055 | if (rc) |
e42de262 | 1056 | return rc; |
8ceee660 | 1057 | |
e332bcb3 | 1058 | /* Initialise MAC address to permanent address */ |
cd84ff4d | 1059 | ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr); |
8ceee660 BH |
1060 | |
1061 | return 0; | |
8ceee660 BH |
1062 | } |
1063 | ||
1064 | static int efx_init_port(struct efx_nic *efx) | |
1065 | { | |
1066 | int rc; | |
1067 | ||
62776d03 | 1068 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 1069 | |
1dfc5cea BH |
1070 | mutex_lock(&efx->mac_lock); |
1071 | ||
177dfcd8 | 1072 | rc = efx->phy_op->init(efx); |
8ceee660 | 1073 | if (rc) |
1dfc5cea | 1074 | goto fail1; |
8ceee660 | 1075 | |
dc8cfa55 | 1076 | efx->port_initialized = true; |
1dfc5cea | 1077 | |
d3245b28 BH |
1078 | /* Reconfigure the MAC before creating dma queues (required for |
1079 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
0d322413 | 1080 | efx_mac_reconfigure(efx); |
d3245b28 BH |
1081 | |
1082 | /* Ensure the PHY advertises the correct flow control settings */ | |
1083 | rc = efx->phy_op->reconfigure(efx); | |
267d9d73 | 1084 | if (rc && rc != -EPERM) |
d3245b28 BH |
1085 | goto fail2; |
1086 | ||
1dfc5cea | 1087 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1088 | return 0; |
177dfcd8 | 1089 | |
1dfc5cea | 1090 | fail2: |
177dfcd8 | 1091 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1092 | fail1: |
1093 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1094 | return rc; |
8ceee660 BH |
1095 | } |
1096 | ||
8ceee660 BH |
1097 | static void efx_start_port(struct efx_nic *efx) |
1098 | { | |
62776d03 | 1099 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1100 | BUG_ON(efx->port_enabled); |
1101 | ||
1102 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1103 | efx->port_enabled = true; |
8be4f3e6 | 1104 | |
d615c039 | 1105 | /* Ensure MAC ingress/egress is enabled */ |
0d322413 | 1106 | efx_mac_reconfigure(efx); |
8be4f3e6 | 1107 | |
8ceee660 BH |
1108 | mutex_unlock(&efx->mac_lock); |
1109 | } | |
1110 | ||
d615c039 BH |
1111 | /* Cancel work for MAC reconfiguration, periodic hardware monitoring |
1112 | * and the async self-test, wait for them to finish and prevent them | |
1113 | * being scheduled again. This doesn't cover online resets, which | |
1114 | * should only be cancelled when removing the device. | |
1115 | */ | |
8ceee660 BH |
1116 | static void efx_stop_port(struct efx_nic *efx) |
1117 | { | |
62776d03 | 1118 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 | 1119 | |
d615c039 BH |
1120 | EFX_ASSERT_RESET_SERIALISED(efx); |
1121 | ||
8ceee660 | 1122 | mutex_lock(&efx->mac_lock); |
dc8cfa55 | 1123 | efx->port_enabled = false; |
8ceee660 BH |
1124 | mutex_unlock(&efx->mac_lock); |
1125 | ||
1126 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1127 | netif_addr_lock_bh(efx->net_dev); |
1128 | netif_addr_unlock_bh(efx->net_dev); | |
d615c039 BH |
1129 | |
1130 | cancel_delayed_work_sync(&efx->monitor_work); | |
1131 | efx_selftest_async_cancel(efx); | |
1132 | cancel_work_sync(&efx->mac_work); | |
8ceee660 BH |
1133 | } |
1134 | ||
1135 | static void efx_fini_port(struct efx_nic *efx) | |
1136 | { | |
62776d03 | 1137 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1138 | |
1139 | if (!efx->port_initialized) | |
1140 | return; | |
1141 | ||
177dfcd8 | 1142 | efx->phy_op->fini(efx); |
dc8cfa55 | 1143 | efx->port_initialized = false; |
8ceee660 | 1144 | |
eb50c0d6 | 1145 | efx->link_state.up = false; |
8ceee660 BH |
1146 | efx_link_status_changed(efx); |
1147 | } | |
1148 | ||
1149 | static void efx_remove_port(struct efx_nic *efx) | |
1150 | { | |
62776d03 | 1151 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1152 | |
ef2b90ee | 1153 | efx->type->remove_port(efx); |
8ceee660 BH |
1154 | } |
1155 | ||
1156 | /************************************************************************** | |
1157 | * | |
1158 | * NIC handling | |
1159 | * | |
1160 | **************************************************************************/ | |
1161 | ||
0bcf4a64 BH |
1162 | static LIST_HEAD(efx_primary_list); |
1163 | static LIST_HEAD(efx_unassociated_list); | |
1164 | ||
1165 | static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right) | |
1166 | { | |
1167 | return left->type == right->type && | |
1168 | left->vpd_sn && right->vpd_sn && | |
1169 | !strcmp(left->vpd_sn, right->vpd_sn); | |
1170 | } | |
1171 | ||
1172 | static void efx_associate(struct efx_nic *efx) | |
1173 | { | |
1174 | struct efx_nic *other, *next; | |
1175 | ||
1176 | if (efx->primary == efx) { | |
1177 | /* Adding primary function; look for secondaries */ | |
1178 | ||
1179 | netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n"); | |
1180 | list_add_tail(&efx->node, &efx_primary_list); | |
1181 | ||
1182 | list_for_each_entry_safe(other, next, &efx_unassociated_list, | |
1183 | node) { | |
1184 | if (efx_same_controller(efx, other)) { | |
1185 | list_del(&other->node); | |
1186 | netif_dbg(other, probe, other->net_dev, | |
1187 | "moving to secondary list of %s %s\n", | |
1188 | pci_name(efx->pci_dev), | |
1189 | efx->net_dev->name); | |
1190 | list_add_tail(&other->node, | |
1191 | &efx->secondary_list); | |
1192 | other->primary = efx; | |
1193 | } | |
1194 | } | |
1195 | } else { | |
1196 | /* Adding secondary function; look for primary */ | |
1197 | ||
1198 | list_for_each_entry(other, &efx_primary_list, node) { | |
1199 | if (efx_same_controller(efx, other)) { | |
1200 | netif_dbg(efx, probe, efx->net_dev, | |
1201 | "adding to secondary list of %s %s\n", | |
1202 | pci_name(other->pci_dev), | |
1203 | other->net_dev->name); | |
1204 | list_add_tail(&efx->node, | |
1205 | &other->secondary_list); | |
1206 | efx->primary = other; | |
1207 | return; | |
1208 | } | |
1209 | } | |
1210 | ||
1211 | netif_dbg(efx, probe, efx->net_dev, | |
1212 | "adding to unassociated list\n"); | |
1213 | list_add_tail(&efx->node, &efx_unassociated_list); | |
1214 | } | |
1215 | } | |
1216 | ||
1217 | static void efx_dissociate(struct efx_nic *efx) | |
1218 | { | |
1219 | struct efx_nic *other, *next; | |
1220 | ||
1221 | list_del(&efx->node); | |
1222 | efx->primary = NULL; | |
1223 | ||
1224 | list_for_each_entry_safe(other, next, &efx->secondary_list, node) { | |
1225 | list_del(&other->node); | |
1226 | netif_dbg(other, probe, other->net_dev, | |
1227 | "moving to unassociated list\n"); | |
1228 | list_add_tail(&other->node, &efx_unassociated_list); | |
1229 | other->primary = NULL; | |
1230 | } | |
1231 | } | |
1232 | ||
8ceee660 BH |
1233 | /* This configures the PCI device to enable I/O and DMA. */ |
1234 | static int efx_init_io(struct efx_nic *efx) | |
1235 | { | |
1236 | struct pci_dev *pci_dev = efx->pci_dev; | |
1237 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
b105798f | 1238 | unsigned int mem_map_size = efx->type->mem_map_size(efx); |
02246a7f | 1239 | int rc, bar; |
8ceee660 | 1240 | |
62776d03 | 1241 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 | 1242 | |
02246a7f SS |
1243 | bar = efx->type->mem_bar; |
1244 | ||
8ceee660 BH |
1245 | rc = pci_enable_device(pci_dev); |
1246 | if (rc) { | |
62776d03 BH |
1247 | netif_err(efx, probe, efx->net_dev, |
1248 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1249 | goto fail1; |
1250 | } | |
1251 | ||
1252 | pci_set_master(pci_dev); | |
1253 | ||
1254 | /* Set the PCI DMA mask. Try all possibilities from our | |
1255 | * genuine mask down to 32 bits, because some architectures | |
1256 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1257 | * masks event though they reject 46 bit masks. | |
1258 | */ | |
1259 | while (dma_mask > 0x7fffffffUL) { | |
8722b8fb CH |
1260 | rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask); |
1261 | if (rc == 0) | |
1262 | break; | |
8ceee660 BH |
1263 | dma_mask >>= 1; |
1264 | } | |
1265 | if (rc) { | |
62776d03 BH |
1266 | netif_err(efx, probe, efx->net_dev, |
1267 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1268 | goto fail2; |
1269 | } | |
62776d03 BH |
1270 | netif_dbg(efx, probe, efx->net_dev, |
1271 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 | 1272 | |
02246a7f SS |
1273 | efx->membase_phys = pci_resource_start(efx->pci_dev, bar); |
1274 | rc = pci_request_region(pci_dev, bar, "sfc"); | |
8ceee660 | 1275 | if (rc) { |
62776d03 BH |
1276 | netif_err(efx, probe, efx->net_dev, |
1277 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1278 | rc = -EIO; |
1279 | goto fail3; | |
1280 | } | |
b105798f | 1281 | efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); |
8ceee660 | 1282 | if (!efx->membase) { |
62776d03 BH |
1283 | netif_err(efx, probe, efx->net_dev, |
1284 | "could not map memory BAR at %llx+%x\n", | |
b105798f | 1285 | (unsigned long long)efx->membase_phys, mem_map_size); |
8ceee660 BH |
1286 | rc = -ENOMEM; |
1287 | goto fail4; | |
1288 | } | |
62776d03 BH |
1289 | netif_dbg(efx, probe, efx->net_dev, |
1290 | "memory BAR at %llx+%x (virtual %p)\n", | |
b105798f BH |
1291 | (unsigned long long)efx->membase_phys, mem_map_size, |
1292 | efx->membase); | |
8ceee660 BH |
1293 | |
1294 | return 0; | |
1295 | ||
1296 | fail4: | |
02246a7f | 1297 | pci_release_region(efx->pci_dev, bar); |
8ceee660 | 1298 | fail3: |
2c118e0f | 1299 | efx->membase_phys = 0; |
8ceee660 BH |
1300 | fail2: |
1301 | pci_disable_device(efx->pci_dev); | |
1302 | fail1: | |
1303 | return rc; | |
1304 | } | |
1305 | ||
1306 | static void efx_fini_io(struct efx_nic *efx) | |
1307 | { | |
02246a7f SS |
1308 | int bar; |
1309 | ||
62776d03 | 1310 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1311 | |
1312 | if (efx->membase) { | |
1313 | iounmap(efx->membase); | |
1314 | efx->membase = NULL; | |
1315 | } | |
1316 | ||
1317 | if (efx->membase_phys) { | |
02246a7f SS |
1318 | bar = efx->type->mem_bar; |
1319 | pci_release_region(efx->pci_dev, bar); | |
2c118e0f | 1320 | efx->membase_phys = 0; |
8ceee660 BH |
1321 | } |
1322 | ||
6598dad2 DP |
1323 | /* Don't disable bus-mastering if VFs are assigned */ |
1324 | if (!pci_vfs_assigned(efx->pci_dev)) | |
1325 | pci_disable_device(efx->pci_dev); | |
8ceee660 BH |
1326 | } |
1327 | ||
267c0157 JC |
1328 | void efx_set_default_rx_indir_table(struct efx_nic *efx) |
1329 | { | |
1330 | size_t i; | |
1331 | ||
1332 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) | |
1333 | efx->rx_indir_table[i] = | |
1334 | ethtool_rxfh_indir_default(i, efx->rss_spread); | |
8ceee660 BH |
1335 | } |
1336 | ||
a9a52506 | 1337 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1338 | { |
cdb08f8f | 1339 | cpumask_var_t thread_mask; |
a16e5b24 | 1340 | unsigned int count; |
46123d04 | 1341 | int cpu; |
5b874e25 | 1342 | |
cd2d5b52 BH |
1343 | if (rss_cpus) { |
1344 | count = rss_cpus; | |
1345 | } else { | |
1346 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1347 | netif_warn(efx, probe, efx->net_dev, | |
1348 | "RSS disabled due to allocation failure\n"); | |
1349 | return 1; | |
1350 | } | |
46123d04 | 1351 | |
cd2d5b52 BH |
1352 | count = 0; |
1353 | for_each_online_cpu(cpu) { | |
1354 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1355 | ++count; | |
1356 | cpumask_or(thread_mask, thread_mask, | |
06931e62 | 1357 | topology_sibling_cpumask(cpu)); |
cd2d5b52 BH |
1358 | } |
1359 | } | |
1360 | ||
1361 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1362 | } |
1363 | ||
cd2d5b52 BH |
1364 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1365 | * table entries that are inaccessible to VFs | |
1366 | */ | |
7fa8d547 SS |
1367 | #ifdef CONFIG_SFC_SRIOV |
1368 | if (efx->type->sriov_wanted) { | |
1369 | if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1370 | count > efx_vf_size(efx)) { | |
1371 | netif_warn(efx, probe, efx->net_dev, | |
1372 | "Reducing number of RSS channels from %u to %u for " | |
1373 | "VF support. Increase vf-msix-limit to use more " | |
1374 | "channels on the PF.\n", | |
1375 | count, efx_vf_size(efx)); | |
1376 | count = efx_vf_size(efx); | |
1377 | } | |
46123d04 | 1378 | } |
7fa8d547 | 1379 | #endif |
46123d04 BH |
1380 | |
1381 | return count; | |
1382 | } | |
1383 | ||
1384 | /* Probe the number and type of interrupts we are able to obtain, and | |
1385 | * the resulting numbers of channels and RX queues. | |
1386 | */ | |
64d8ad6d | 1387 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1388 | { |
7f967c01 BH |
1389 | unsigned int extra_channels = 0; |
1390 | unsigned int i, j; | |
a16e5b24 | 1391 | int rc; |
8ceee660 | 1392 | |
7f967c01 BH |
1393 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1394 | if (efx->extra_channel_type[i]) | |
1395 | ++extra_channels; | |
1396 | ||
8ceee660 | 1397 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1398 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1399 | unsigned int n_channels; |
aa6ef27e | 1400 | |
a9a52506 | 1401 | n_channels = efx_wanted_parallelism(efx); |
b0fbdae1 | 1402 | if (efx_separate_tx_channels) |
a4900ac9 | 1403 | n_channels *= 2; |
7f967c01 | 1404 | n_channels += extra_channels; |
b105798f | 1405 | n_channels = min(n_channels, efx->max_channels); |
8ceee660 | 1406 | |
a4900ac9 | 1407 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1408 | xentries[i].entry = i; |
184603d8 AG |
1409 | rc = pci_enable_msix_range(efx->pci_dev, |
1410 | xentries, 1, n_channels); | |
1411 | if (rc < 0) { | |
1412 | /* Fall back to single channel MSI */ | |
1413 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
1414 | netif_err(efx, drv, efx->net_dev, | |
1415 | "could not enable MSI-X\n"); | |
1416 | } else if (rc < n_channels) { | |
62776d03 BH |
1417 | netif_err(efx, drv, efx->net_dev, |
1418 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1419 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1420 | netif_err(efx, drv, efx->net_dev, |
1421 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 | 1422 | n_channels = rc; |
8ceee660 BH |
1423 | } |
1424 | ||
184603d8 | 1425 | if (rc > 0) { |
a4900ac9 | 1426 | efx->n_channels = n_channels; |
7f967c01 BH |
1427 | if (n_channels > extra_channels) |
1428 | n_channels -= extra_channels; | |
b0fbdae1 SS |
1429 | if (efx_separate_tx_channels) { |
1430 | efx->n_tx_channels = min(max(n_channels / 2, | |
1431 | 1U), | |
1432 | efx->max_tx_channels); | |
7f967c01 BH |
1433 | efx->n_rx_channels = max(n_channels - |
1434 | efx->n_tx_channels, | |
1435 | 1U); | |
a4900ac9 | 1436 | } else { |
b0fbdae1 SS |
1437 | efx->n_tx_channels = min(n_channels, |
1438 | efx->max_tx_channels); | |
7f967c01 | 1439 | efx->n_rx_channels = n_channels; |
a4900ac9 | 1440 | } |
7f967c01 | 1441 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1442 | efx_get_channel(efx, i)->irq = |
1443 | xentries[i].vector; | |
8ceee660 BH |
1444 | } |
1445 | } | |
1446 | ||
1447 | /* Try single interrupt MSI */ | |
1448 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1449 | efx->n_channels = 1; |
a4900ac9 BH |
1450 | efx->n_rx_channels = 1; |
1451 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1452 | rc = pci_enable_msi(efx->pci_dev); |
1453 | if (rc == 0) { | |
f7d12cdc | 1454 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1455 | } else { |
62776d03 BH |
1456 | netif_err(efx, drv, efx->net_dev, |
1457 | "could not enable MSI\n"); | |
8ceee660 BH |
1458 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1459 | } | |
1460 | } | |
1461 | ||
1462 | /* Assume legacy interrupts */ | |
1463 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
b0fbdae1 | 1464 | efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1465 | efx->n_rx_channels = 1; |
1466 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1467 | efx->legacy_irq = efx->pci_dev->irq; |
1468 | } | |
64d8ad6d | 1469 | |
7f967c01 BH |
1470 | /* Assign extra channels if possible */ |
1471 | j = efx->n_channels; | |
1472 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1473 | if (!efx->extra_channel_type[i]) | |
1474 | continue; | |
1475 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1476 | efx->n_channels <= extra_channels) { | |
1477 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1478 | } else { | |
1479 | --j; | |
1480 | efx_get_channel(efx, j)->type = | |
1481 | efx->extra_channel_type[i]; | |
1482 | } | |
1483 | } | |
1484 | ||
cd2d5b52 | 1485 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
7fa8d547 SS |
1486 | #ifdef CONFIG_SFC_SRIOV |
1487 | if (efx->type->sriov_wanted) { | |
1488 | efx->rss_spread = ((efx->n_rx_channels > 1 || | |
1489 | !efx->type->sriov_wanted(efx)) ? | |
1490 | efx->n_rx_channels : efx_vf_size(efx)); | |
1491 | return 0; | |
1492 | } | |
1493 | #endif | |
1494 | efx->rss_spread = efx->n_rx_channels; | |
cd2d5b52 | 1495 | |
64d8ad6d | 1496 | return 0; |
8ceee660 BH |
1497 | } |
1498 | ||
261e4d96 | 1499 | static int efx_soft_enable_interrupts(struct efx_nic *efx) |
9f2cb71c | 1500 | { |
261e4d96 JC |
1501 | struct efx_channel *channel, *end_channel; |
1502 | int rc; | |
9f2cb71c | 1503 | |
8b7325b4 BH |
1504 | BUG_ON(efx->state == STATE_DISABLED); |
1505 | ||
d8291187 BH |
1506 | efx->irq_soft_enabled = true; |
1507 | smp_wmb(); | |
9f2cb71c BH |
1508 | |
1509 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1510 | if (!channel->type->keep_eventq) { |
1511 | rc = efx_init_eventq(channel); | |
1512 | if (rc) | |
1513 | goto fail; | |
1514 | } | |
9f2cb71c BH |
1515 | efx_start_eventq(channel); |
1516 | } | |
1517 | ||
1518 | efx_mcdi_mode_event(efx); | |
261e4d96 JC |
1519 | |
1520 | return 0; | |
1521 | fail: | |
1522 | end_channel = channel; | |
1523 | efx_for_each_channel(channel, efx) { | |
1524 | if (channel == end_channel) | |
1525 | break; | |
1526 | efx_stop_eventq(channel); | |
1527 | if (!channel->type->keep_eventq) | |
1528 | efx_fini_eventq(channel); | |
1529 | } | |
1530 | ||
1531 | return rc; | |
9f2cb71c BH |
1532 | } |
1533 | ||
d8291187 | 1534 | static void efx_soft_disable_interrupts(struct efx_nic *efx) |
9f2cb71c BH |
1535 | { |
1536 | struct efx_channel *channel; | |
1537 | ||
8b7325b4 BH |
1538 | if (efx->state == STATE_DISABLED) |
1539 | return; | |
1540 | ||
9f2cb71c BH |
1541 | efx_mcdi_mode_poll(efx); |
1542 | ||
d8291187 BH |
1543 | efx->irq_soft_enabled = false; |
1544 | smp_wmb(); | |
1545 | ||
1546 | if (efx->legacy_irq) | |
9f2cb71c | 1547 | synchronize_irq(efx->legacy_irq); |
9f2cb71c BH |
1548 | |
1549 | efx_for_each_channel(channel, efx) { | |
1550 | if (channel->irq) | |
1551 | synchronize_irq(channel->irq); | |
1552 | ||
1553 | efx_stop_eventq(channel); | |
d8291187 | 1554 | if (!channel->type->keep_eventq) |
7f967c01 | 1555 | efx_fini_eventq(channel); |
9f2cb71c | 1556 | } |
cade715f BH |
1557 | |
1558 | /* Flush the asynchronous MCDI request queue */ | |
1559 | efx_mcdi_flush_async(efx); | |
9f2cb71c BH |
1560 | } |
1561 | ||
261e4d96 | 1562 | static int efx_enable_interrupts(struct efx_nic *efx) |
d8291187 | 1563 | { |
261e4d96 JC |
1564 | struct efx_channel *channel, *end_channel; |
1565 | int rc; | |
d8291187 BH |
1566 | |
1567 | BUG_ON(efx->state == STATE_DISABLED); | |
1568 | ||
1569 | if (efx->eeh_disabled_legacy_irq) { | |
1570 | enable_irq(efx->legacy_irq); | |
1571 | efx->eeh_disabled_legacy_irq = false; | |
1572 | } | |
1573 | ||
86094f7f | 1574 | efx->type->irq_enable_master(efx); |
d8291187 BH |
1575 | |
1576 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1577 | if (channel->type->keep_eventq) { |
1578 | rc = efx_init_eventq(channel); | |
1579 | if (rc) | |
1580 | goto fail; | |
1581 | } | |
1582 | } | |
1583 | ||
1584 | rc = efx_soft_enable_interrupts(efx); | |
1585 | if (rc) | |
1586 | goto fail; | |
1587 | ||
1588 | return 0; | |
1589 | ||
1590 | fail: | |
1591 | end_channel = channel; | |
1592 | efx_for_each_channel(channel, efx) { | |
1593 | if (channel == end_channel) | |
1594 | break; | |
d8291187 | 1595 | if (channel->type->keep_eventq) |
261e4d96 | 1596 | efx_fini_eventq(channel); |
d8291187 BH |
1597 | } |
1598 | ||
261e4d96 JC |
1599 | efx->type->irq_disable_non_ev(efx); |
1600 | ||
1601 | return rc; | |
d8291187 BH |
1602 | } |
1603 | ||
1604 | static void efx_disable_interrupts(struct efx_nic *efx) | |
1605 | { | |
1606 | struct efx_channel *channel; | |
1607 | ||
1608 | efx_soft_disable_interrupts(efx); | |
1609 | ||
1610 | efx_for_each_channel(channel, efx) { | |
1611 | if (channel->type->keep_eventq) | |
1612 | efx_fini_eventq(channel); | |
1613 | } | |
1614 | ||
86094f7f | 1615 | efx->type->irq_disable_non_ev(efx); |
d8291187 BH |
1616 | } |
1617 | ||
8ceee660 BH |
1618 | static void efx_remove_interrupts(struct efx_nic *efx) |
1619 | { | |
1620 | struct efx_channel *channel; | |
1621 | ||
1622 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1623 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1624 | channel->irq = 0; |
1625 | pci_disable_msi(efx->pci_dev); | |
1626 | pci_disable_msix(efx->pci_dev); | |
1627 | ||
1628 | /* Remove legacy interrupt */ | |
1629 | efx->legacy_irq = 0; | |
1630 | } | |
1631 | ||
8831da7b | 1632 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1633 | { |
602a5322 BH |
1634 | struct efx_channel *channel; |
1635 | struct efx_tx_queue *tx_queue; | |
1636 | ||
97653431 | 1637 | efx->tx_channel_offset = |
b0fbdae1 SS |
1638 | efx_separate_tx_channels ? |
1639 | efx->n_channels - efx->n_tx_channels : 0; | |
602a5322 | 1640 | |
79d68b37 SH |
1641 | /* We need to mark which channels really have RX and TX |
1642 | * queues, and adjust the TX queue numbers if we have separate | |
602a5322 BH |
1643 | * RX-only and TX-only channels. |
1644 | */ | |
1645 | efx_for_each_channel(channel, efx) { | |
79d68b37 SH |
1646 | if (channel->channel < efx->n_rx_channels) |
1647 | channel->rx_queue.core_index = channel->channel; | |
1648 | else | |
1649 | channel->rx_queue.core_index = -1; | |
1650 | ||
602a5322 BH |
1651 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1652 | tx_queue->queue -= (efx->tx_channel_offset * | |
1653 | EFX_TXQ_TYPES); | |
1654 | } | |
8ceee660 BH |
1655 | } |
1656 | ||
1657 | static int efx_probe_nic(struct efx_nic *efx) | |
1658 | { | |
1659 | int rc; | |
1660 | ||
62776d03 | 1661 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1662 | |
1663 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1664 | rc = efx->type->probe(efx); |
8ceee660 BH |
1665 | if (rc) |
1666 | return rc; | |
1667 | ||
b0fbdae1 SS |
1668 | do { |
1669 | if (!efx->max_channels || !efx->max_tx_channels) { | |
1670 | netif_err(efx, drv, efx->net_dev, | |
1671 | "Insufficient resources to allocate" | |
1672 | " any channels\n"); | |
1673 | rc = -ENOSPC; | |
1674 | goto fail1; | |
1675 | } | |
8ceee660 | 1676 | |
b0fbdae1 SS |
1677 | /* Determine the number of channels and queues by trying |
1678 | * to hook in MSI-X interrupts. | |
1679 | */ | |
1680 | rc = efx_probe_interrupts(efx); | |
1681 | if (rc) | |
1682 | goto fail1; | |
52ad762b | 1683 | |
b0fbdae1 SS |
1684 | efx_set_channels(efx); |
1685 | ||
1686 | /* dimension_resources can fail with EAGAIN */ | |
1687 | rc = efx->type->dimension_resources(efx); | |
1688 | if (rc != 0 && rc != -EAGAIN) | |
1689 | goto fail2; | |
1690 | ||
1691 | if (rc == -EAGAIN) | |
1692 | /* try again with new max_channels */ | |
1693 | efx_remove_interrupts(efx); | |
1694 | ||
1695 | } while (rc == -EAGAIN); | |
28e47c49 | 1696 | |
5d3a6fca | 1697 | if (efx->n_channels > 1) |
267c0157 JC |
1698 | netdev_rss_key_fill(&efx->rx_hash_key, |
1699 | sizeof(efx->rx_hash_key)); | |
1700 | efx_set_default_rx_indir_table(efx); | |
5d3a6fca | 1701 | |
c4f4adc7 BH |
1702 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1703 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1704 | |
1705 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1706 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1707 | true); | |
8ceee660 BH |
1708 | |
1709 | return 0; | |
64d8ad6d | 1710 | |
c15eed22 BH |
1711 | fail2: |
1712 | efx_remove_interrupts(efx); | |
1713 | fail1: | |
64d8ad6d BH |
1714 | efx->type->remove(efx); |
1715 | return rc; | |
8ceee660 BH |
1716 | } |
1717 | ||
1718 | static void efx_remove_nic(struct efx_nic *efx) | |
1719 | { | |
62776d03 | 1720 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1721 | |
1722 | efx_remove_interrupts(efx); | |
ef2b90ee | 1723 | efx->type->remove(efx); |
8ceee660 BH |
1724 | } |
1725 | ||
add72477 BH |
1726 | static int efx_probe_filters(struct efx_nic *efx) |
1727 | { | |
1728 | int rc; | |
1729 | ||
1730 | spin_lock_init(&efx->filter_lock); | |
0d322413 | 1731 | init_rwsem(&efx->filter_sem); |
d248953a | 1732 | mutex_lock(&efx->mac_lock); |
0d322413 | 1733 | down_write(&efx->filter_sem); |
add72477 BH |
1734 | rc = efx->type->filter_table_probe(efx); |
1735 | if (rc) | |
0d322413 | 1736 | goto out_unlock; |
add72477 BH |
1737 | |
1738 | #ifdef CONFIG_RFS_ACCEL | |
1739 | if (efx->type->offload_features & NETIF_F_NTUPLE) { | |
faf8dcc1 JC |
1740 | struct efx_channel *channel; |
1741 | int i, success = 1; | |
1742 | ||
1743 | efx_for_each_channel(channel, efx) { | |
1744 | channel->rps_flow_id = | |
1745 | kcalloc(efx->type->max_rx_ip_filters, | |
1746 | sizeof(*channel->rps_flow_id), | |
1747 | GFP_KERNEL); | |
1748 | if (!channel->rps_flow_id) | |
1749 | success = 0; | |
1750 | else | |
1751 | for (i = 0; | |
1752 | i < efx->type->max_rx_ip_filters; | |
1753 | ++i) | |
1754 | channel->rps_flow_id[i] = | |
1755 | RPS_FLOW_ID_INVALID; | |
1756 | } | |
1757 | ||
1758 | if (!success) { | |
1759 | efx_for_each_channel(channel, efx) | |
1760 | kfree(channel->rps_flow_id); | |
add72477 | 1761 | efx->type->filter_table_remove(efx); |
0d322413 EC |
1762 | rc = -ENOMEM; |
1763 | goto out_unlock; | |
add72477 | 1764 | } |
faf8dcc1 JC |
1765 | |
1766 | efx->rps_expire_index = efx->rps_expire_channel = 0; | |
add72477 BH |
1767 | } |
1768 | #endif | |
0d322413 EC |
1769 | out_unlock: |
1770 | up_write(&efx->filter_sem); | |
d248953a | 1771 | mutex_unlock(&efx->mac_lock); |
0d322413 | 1772 | return rc; |
add72477 BH |
1773 | } |
1774 | ||
1775 | static void efx_remove_filters(struct efx_nic *efx) | |
1776 | { | |
1777 | #ifdef CONFIG_RFS_ACCEL | |
faf8dcc1 JC |
1778 | struct efx_channel *channel; |
1779 | ||
1780 | efx_for_each_channel(channel, efx) | |
1781 | kfree(channel->rps_flow_id); | |
add72477 | 1782 | #endif |
0d322413 | 1783 | down_write(&efx->filter_sem); |
add72477 | 1784 | efx->type->filter_table_remove(efx); |
0d322413 | 1785 | up_write(&efx->filter_sem); |
add72477 BH |
1786 | } |
1787 | ||
1788 | static void efx_restore_filters(struct efx_nic *efx) | |
1789 | { | |
0d322413 | 1790 | down_read(&efx->filter_sem); |
add72477 | 1791 | efx->type->filter_table_restore(efx); |
0d322413 | 1792 | up_read(&efx->filter_sem); |
add72477 BH |
1793 | } |
1794 | ||
8ceee660 BH |
1795 | /************************************************************************** |
1796 | * | |
1797 | * NIC startup/shutdown | |
1798 | * | |
1799 | *************************************************************************/ | |
1800 | ||
1801 | static int efx_probe_all(struct efx_nic *efx) | |
1802 | { | |
8ceee660 BH |
1803 | int rc; |
1804 | ||
8ceee660 BH |
1805 | rc = efx_probe_nic(efx); |
1806 | if (rc) { | |
62776d03 | 1807 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1808 | goto fail1; |
1809 | } | |
1810 | ||
8ceee660 BH |
1811 | rc = efx_probe_port(efx); |
1812 | if (rc) { | |
62776d03 | 1813 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1814 | goto fail2; |
1815 | } | |
1816 | ||
7e6d06f0 BH |
1817 | BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); |
1818 | if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { | |
1819 | rc = -EINVAL; | |
1820 | goto fail3; | |
1821 | } | |
ecc910f5 | 1822 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1823 | |
6d8aaaf6 DP |
1824 | #ifdef CONFIG_SFC_SRIOV |
1825 | rc = efx->type->vswitching_probe(efx); | |
1826 | if (rc) /* not fatal; the PF will still work fine */ | |
1827 | netif_warn(efx, probe, efx->net_dev, | |
1828 | "failed to setup vswitching rc=%d;" | |
1829 | " VFs may not function\n", rc); | |
1830 | #endif | |
1831 | ||
64eebcfd BH |
1832 | rc = efx_probe_filters(efx); |
1833 | if (rc) { | |
1834 | netif_err(efx, probe, efx->net_dev, | |
1835 | "failed to create filter tables\n"); | |
6d8aaaf6 | 1836 | goto fail4; |
64eebcfd BH |
1837 | } |
1838 | ||
7f967c01 BH |
1839 | rc = efx_probe_channels(efx); |
1840 | if (rc) | |
6d8aaaf6 | 1841 | goto fail5; |
7f967c01 | 1842 | |
8ceee660 BH |
1843 | return 0; |
1844 | ||
6d8aaaf6 | 1845 | fail5: |
7f967c01 | 1846 | efx_remove_filters(efx); |
6d8aaaf6 DP |
1847 | fail4: |
1848 | #ifdef CONFIG_SFC_SRIOV | |
1849 | efx->type->vswitching_remove(efx); | |
1850 | #endif | |
8ceee660 | 1851 | fail3: |
8ceee660 BH |
1852 | efx_remove_port(efx); |
1853 | fail2: | |
1854 | efx_remove_nic(efx); | |
1855 | fail1: | |
1856 | return rc; | |
1857 | } | |
1858 | ||
8b7325b4 BH |
1859 | /* If the interface is supposed to be running but is not, start |
1860 | * the hardware and software data path, regular activity for the port | |
1861 | * (MAC statistics, link polling, etc.) and schedule the port to be | |
1862 | * reconfigured. Interrupts must already be enabled. This function | |
1863 | * is safe to call multiple times, so long as the NIC is not disabled. | |
1864 | * Requires the RTNL lock. | |
9f2cb71c | 1865 | */ |
8ceee660 BH |
1866 | static void efx_start_all(struct efx_nic *efx) |
1867 | { | |
8ceee660 | 1868 | EFX_ASSERT_RESET_SERIALISED(efx); |
8b7325b4 | 1869 | BUG_ON(efx->state == STATE_DISABLED); |
8ceee660 BH |
1870 | |
1871 | /* Check that it is appropriate to restart the interface. All | |
1872 | * of these flags are safe to read under just the rtnl lock */ | |
e283546c EC |
1873 | if (efx->port_enabled || !netif_running(efx->net_dev) || |
1874 | efx->reset_pending) | |
8ceee660 BH |
1875 | return; |
1876 | ||
8ceee660 | 1877 | efx_start_port(efx); |
9f2cb71c | 1878 | efx_start_datapath(efx); |
8880f4ec | 1879 | |
626950db AR |
1880 | /* Start the hardware monitor if there is one */ |
1881 | if (efx->type->monitor != NULL) | |
8ceee660 BH |
1882 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1883 | efx_monitor_interval); | |
626950db AR |
1884 | |
1885 | /* If link state detection is normally event-driven, we have | |
1886 | * to poll now because we could have missed a change | |
1887 | */ | |
1888 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { | |
78c1f0a0 SH |
1889 | mutex_lock(&efx->mac_lock); |
1890 | if (efx->phy_op->poll(efx)) | |
1891 | efx_link_status_changed(efx); | |
1892 | mutex_unlock(&efx->mac_lock); | |
1893 | } | |
55edc6e6 | 1894 | |
ef2b90ee | 1895 | efx->type->start_stats(efx); |
f8f3b5ae JC |
1896 | efx->type->pull_stats(efx); |
1897 | spin_lock_bh(&efx->stats_lock); | |
1898 | efx->type->update_stats(efx, NULL, NULL); | |
1899 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
1900 | } |
1901 | ||
8b7325b4 BH |
1902 | /* Quiesce the hardware and software data path, and regular activity |
1903 | * for the port without bringing the link down. Safe to call multiple | |
1904 | * times with the NIC in almost any state, but interrupts should be | |
1905 | * enabled. Requires the RTNL lock. | |
1906 | */ | |
8ceee660 BH |
1907 | static void efx_stop_all(struct efx_nic *efx) |
1908 | { | |
8ceee660 BH |
1909 | EFX_ASSERT_RESET_SERIALISED(efx); |
1910 | ||
1911 | /* port_enabled can be read safely under the rtnl lock */ | |
1912 | if (!efx->port_enabled) | |
1913 | return; | |
1914 | ||
f8f3b5ae JC |
1915 | /* update stats before we go down so we can accurately count |
1916 | * rx_nodesc_drops | |
1917 | */ | |
1918 | efx->type->pull_stats(efx); | |
1919 | spin_lock_bh(&efx->stats_lock); | |
1920 | efx->type->update_stats(efx, NULL, NULL); | |
1921 | spin_unlock_bh(&efx->stats_lock); | |
ef2b90ee | 1922 | efx->type->stop_stats(efx); |
8ceee660 BH |
1923 | efx_stop_port(efx); |
1924 | ||
29c69a48 BH |
1925 | /* Stop the kernel transmit interface. This is only valid if |
1926 | * the device is stopped or detached; otherwise the watchdog | |
1927 | * may fire immediately. | |
1928 | */ | |
1929 | WARN_ON(netif_running(efx->net_dev) && | |
1930 | netif_device_present(efx->net_dev)); | |
9f2cb71c BH |
1931 | netif_tx_disable(efx->net_dev); |
1932 | ||
1933 | efx_stop_datapath(efx); | |
8ceee660 BH |
1934 | } |
1935 | ||
1936 | static void efx_remove_all(struct efx_nic *efx) | |
1937 | { | |
4642610c | 1938 | efx_remove_channels(efx); |
7f967c01 | 1939 | efx_remove_filters(efx); |
6d8aaaf6 DP |
1940 | #ifdef CONFIG_SFC_SRIOV |
1941 | efx->type->vswitching_remove(efx); | |
1942 | #endif | |
8ceee660 BH |
1943 | efx_remove_port(efx); |
1944 | efx_remove_nic(efx); | |
1945 | } | |
1946 | ||
8ceee660 BH |
1947 | /************************************************************************** |
1948 | * | |
1949 | * Interrupt moderation | |
1950 | * | |
1951 | **************************************************************************/ | |
1952 | ||
cc180b69 | 1953 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1954 | { |
b548f976 BH |
1955 | if (usecs == 0) |
1956 | return 0; | |
cc180b69 | 1957 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1958 | return 1; /* never round down to 0 */ |
cc180b69 | 1959 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1960 | } |
1961 | ||
8ceee660 | 1962 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1963 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1964 | unsigned int rx_usecs, bool rx_adaptive, | |
1965 | bool rx_may_override_tx) | |
8ceee660 | 1966 | { |
f7d12cdc | 1967 | struct efx_channel *channel; |
cc180b69 BH |
1968 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1969 | efx->timer_quantum_ns, | |
1970 | 1000); | |
1971 | unsigned int tx_ticks; | |
1972 | unsigned int rx_ticks; | |
8ceee660 BH |
1973 | |
1974 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1975 | ||
cc180b69 | 1976 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1977 | return -EINVAL; |
1978 | ||
cc180b69 BH |
1979 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1980 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1981 | ||
9e393b30 BH |
1982 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1983 | !rx_may_override_tx) { | |
1984 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1985 | "RX and TX IRQ moderation must be equal\n"); | |
1986 | return -EINVAL; | |
1987 | } | |
1988 | ||
6fb70fd1 | 1989 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1990 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1991 | efx_for_each_channel(channel, efx) { |
525da907 | 1992 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1993 | channel->irq_moderation = rx_ticks; |
525da907 | 1994 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1995 | channel->irq_moderation = tx_ticks; |
1996 | } | |
9e393b30 BH |
1997 | |
1998 | return 0; | |
8ceee660 BH |
1999 | } |
2000 | ||
a0c4faf5 BH |
2001 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
2002 | unsigned int *rx_usecs, bool *rx_adaptive) | |
2003 | { | |
cc180b69 BH |
2004 | /* We must round up when converting ticks to microseconds |
2005 | * because we round down when converting the other way. | |
2006 | */ | |
2007 | ||
a0c4faf5 | 2008 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
2009 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
2010 | efx->timer_quantum_ns, | |
2011 | 1000); | |
a0c4faf5 BH |
2012 | |
2013 | /* If channels are shared between RX and TX, so is IRQ | |
2014 | * moderation. Otherwise, IRQ moderation is the same for all | |
2015 | * TX channels and is not adaptive. | |
2016 | */ | |
2017 | if (efx->tx_channel_offset == 0) | |
2018 | *tx_usecs = *rx_usecs; | |
2019 | else | |
cc180b69 | 2020 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 2021 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
2022 | efx->timer_quantum_ns, |
2023 | 1000); | |
a0c4faf5 BH |
2024 | } |
2025 | ||
8ceee660 BH |
2026 | /************************************************************************** |
2027 | * | |
2028 | * Hardware monitor | |
2029 | * | |
2030 | **************************************************************************/ | |
2031 | ||
e254c274 | 2032 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
2033 | static void efx_monitor(struct work_struct *data) |
2034 | { | |
2035 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
2036 | monitor_work.work); | |
8ceee660 | 2037 | |
62776d03 BH |
2038 | netif_vdbg(efx, timer, efx->net_dev, |
2039 | "hardware monitor executing on CPU %d\n", | |
2040 | raw_smp_processor_id()); | |
ef2b90ee | 2041 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 2042 | |
8ceee660 BH |
2043 | /* If the mac_lock is already held then it is likely a port |
2044 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
2045 | * most of the work of monitor() anyway. */ |
2046 | if (mutex_trylock(&efx->mac_lock)) { | |
2047 | if (efx->port_enabled) | |
2048 | efx->type->monitor(efx); | |
2049 | mutex_unlock(&efx->mac_lock); | |
2050 | } | |
8ceee660 | 2051 | |
8ceee660 BH |
2052 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
2053 | efx_monitor_interval); | |
2054 | } | |
2055 | ||
2056 | /************************************************************************** | |
2057 | * | |
2058 | * ioctls | |
2059 | * | |
2060 | *************************************************************************/ | |
2061 | ||
2062 | /* Net device ioctl | |
2063 | * Context: process, rtnl_lock() held. | |
2064 | */ | |
2065 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
2066 | { | |
767e468c | 2067 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 2068 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 | 2069 | |
7c236c43 | 2070 | if (cmd == SIOCSHWTSTAMP) |
433dc9b3 BH |
2071 | return efx_ptp_set_ts_config(efx, ifr); |
2072 | if (cmd == SIOCGHWTSTAMP) | |
2073 | return efx_ptp_get_ts_config(efx, ifr); | |
7c236c43 | 2074 | |
68e7f45e BH |
2075 | /* Convert phy_id from older PRTAD/DEVAD format */ |
2076 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
2077 | (data->phy_id & 0xfc00) == 0x0400) | |
2078 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
2079 | ||
2080 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
2081 | } |
2082 | ||
2083 | /************************************************************************** | |
2084 | * | |
2085 | * NAPI interface | |
2086 | * | |
2087 | **************************************************************************/ | |
2088 | ||
7f967c01 BH |
2089 | static void efx_init_napi_channel(struct efx_channel *channel) |
2090 | { | |
2091 | struct efx_nic *efx = channel->efx; | |
2092 | ||
2093 | channel->napi_dev = efx->net_dev; | |
2094 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
2095 | efx_poll, napi_weight); | |
c0f9c7e4 | 2096 | efx_channel_busy_poll_init(channel); |
7f967c01 BH |
2097 | } |
2098 | ||
e8f14992 | 2099 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
2100 | { |
2101 | struct efx_channel *channel; | |
8ceee660 | 2102 | |
7f967c01 BH |
2103 | efx_for_each_channel(channel, efx) |
2104 | efx_init_napi_channel(channel); | |
e8f14992 BH |
2105 | } |
2106 | ||
2107 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
2108 | { | |
36763266 | 2109 | if (channel->napi_dev) { |
e8f14992 | 2110 | netif_napi_del(&channel->napi_str); |
36763266 AR |
2111 | napi_hash_del(&channel->napi_str); |
2112 | } | |
e8f14992 | 2113 | channel->napi_dev = NULL; |
8ceee660 BH |
2114 | } |
2115 | ||
2116 | static void efx_fini_napi(struct efx_nic *efx) | |
2117 | { | |
2118 | struct efx_channel *channel; | |
2119 | ||
e8f14992 BH |
2120 | efx_for_each_channel(channel, efx) |
2121 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
2122 | } |
2123 | ||
2124 | /************************************************************************** | |
2125 | * | |
2126 | * Kernel netpoll interface | |
2127 | * | |
2128 | *************************************************************************/ | |
2129 | ||
2130 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2131 | ||
2132 | /* Although in the common case interrupts will be disabled, this is not | |
2133 | * guaranteed. However, all our work happens inside the NAPI callback, | |
2134 | * so no locking is required. | |
2135 | */ | |
2136 | static void efx_netpoll(struct net_device *net_dev) | |
2137 | { | |
767e468c | 2138 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
2139 | struct efx_channel *channel; |
2140 | ||
64ee3120 | 2141 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
2142 | efx_schedule_channel(channel); |
2143 | } | |
2144 | ||
2145 | #endif | |
2146 | ||
36763266 AR |
2147 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2148 | static int efx_busy_poll(struct napi_struct *napi) | |
2149 | { | |
2150 | struct efx_channel *channel = | |
2151 | container_of(napi, struct efx_channel, napi_str); | |
2152 | struct efx_nic *efx = channel->efx; | |
2153 | int budget = 4; | |
2154 | int old_rx_packets, rx_packets; | |
2155 | ||
2156 | if (!netif_running(efx->net_dev)) | |
2157 | return LL_FLUSH_FAILED; | |
2158 | ||
c0f9c7e4 | 2159 | if (!efx_channel_try_lock_poll(channel)) |
36763266 AR |
2160 | return LL_FLUSH_BUSY; |
2161 | ||
2162 | old_rx_packets = channel->rx_queue.rx_packets; | |
2163 | efx_process_channel(channel, budget); | |
2164 | ||
2165 | rx_packets = channel->rx_queue.rx_packets - old_rx_packets; | |
2166 | ||
2167 | /* There is no race condition with NAPI here. | |
2168 | * NAPI will automatically be rescheduled if it yielded during busy | |
2169 | * polling, because it was not able to take the lock and thus returned | |
2170 | * the full budget. | |
2171 | */ | |
2172 | efx_channel_unlock_poll(channel); | |
2173 | ||
2174 | return rx_packets; | |
2175 | } | |
2176 | #endif | |
2177 | ||
8ceee660 BH |
2178 | /************************************************************************** |
2179 | * | |
2180 | * Kernel net device interface | |
2181 | * | |
2182 | *************************************************************************/ | |
2183 | ||
2184 | /* Context: process, rtnl_lock() held. */ | |
e340be92 | 2185 | int efx_net_open(struct net_device *net_dev) |
8ceee660 | 2186 | { |
767e468c | 2187 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 BH |
2188 | int rc; |
2189 | ||
62776d03 BH |
2190 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
2191 | raw_smp_processor_id()); | |
8ceee660 | 2192 | |
8b7325b4 BH |
2193 | rc = efx_check_disabled(efx); |
2194 | if (rc) | |
2195 | return rc; | |
f8b87c17 BH |
2196 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
2197 | return -EBUSY; | |
8880f4ec BH |
2198 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
2199 | return -EIO; | |
f8b87c17 | 2200 | |
78c1f0a0 SH |
2201 | /* Notify the kernel of the link state polled during driver load, |
2202 | * before the monitor starts running */ | |
2203 | efx_link_status_changed(efx); | |
2204 | ||
8ceee660 | 2205 | efx_start_all(efx); |
dd40781e | 2206 | efx_selftest_async_start(efx); |
8ceee660 BH |
2207 | return 0; |
2208 | } | |
2209 | ||
2210 | /* Context: process, rtnl_lock() held. | |
2211 | * Note that the kernel will ignore our return code; this method | |
2212 | * should really be a void. | |
2213 | */ | |
e340be92 | 2214 | int efx_net_stop(struct net_device *net_dev) |
8ceee660 | 2215 | { |
767e468c | 2216 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2217 | |
62776d03 BH |
2218 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
2219 | raw_smp_processor_id()); | |
8ceee660 | 2220 | |
8b7325b4 BH |
2221 | /* Stop the device and flush all the channels */ |
2222 | efx_stop_all(efx); | |
8ceee660 BH |
2223 | |
2224 | return 0; | |
2225 | } | |
2226 | ||
5b9e207c | 2227 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
2228 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
2229 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 2230 | { |
767e468c | 2231 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2232 | |
55edc6e6 | 2233 | spin_lock_bh(&efx->stats_lock); |
cd0ecc9a | 2234 | efx->type->update_stats(efx, NULL, stats); |
1cb34522 BH |
2235 | spin_unlock_bh(&efx->stats_lock); |
2236 | ||
8ceee660 BH |
2237 | return stats; |
2238 | } | |
2239 | ||
2240 | /* Context: netif_tx_lock held, BHs disabled. */ | |
2241 | static void efx_watchdog(struct net_device *net_dev) | |
2242 | { | |
767e468c | 2243 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2244 | |
62776d03 BH |
2245 | netif_err(efx, tx_err, efx->net_dev, |
2246 | "TX stuck with port_enabled=%d: resetting channels\n", | |
2247 | efx->port_enabled); | |
8ceee660 | 2248 | |
739bb23d | 2249 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
2250 | } |
2251 | ||
2252 | ||
2253 | /* Context: process, rtnl_lock() held. */ | |
2254 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
2255 | { | |
767e468c | 2256 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 | 2257 | int rc; |
8ceee660 | 2258 | |
8b7325b4 BH |
2259 | rc = efx_check_disabled(efx); |
2260 | if (rc) | |
2261 | return rc; | |
8ceee660 BH |
2262 | if (new_mtu > EFX_MAX_MTU) |
2263 | return -EINVAL; | |
2264 | ||
62776d03 | 2265 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 2266 | |
29c69a48 BH |
2267 | efx_device_detach_sync(efx); |
2268 | efx_stop_all(efx); | |
2269 | ||
d3245b28 | 2270 | mutex_lock(&efx->mac_lock); |
8ceee660 | 2271 | net_dev->mtu = new_mtu; |
0d322413 | 2272 | efx_mac_reconfigure(efx); |
d3245b28 BH |
2273 | mutex_unlock(&efx->mac_lock); |
2274 | ||
8ceee660 | 2275 | efx_start_all(efx); |
29c69a48 | 2276 | netif_device_attach(efx->net_dev); |
6c8eef4a | 2277 | return 0; |
8ceee660 BH |
2278 | } |
2279 | ||
2280 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
2281 | { | |
767e468c | 2282 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2283 | struct sockaddr *addr = data; |
e0b3ae30 | 2284 | u8 *new_addr = addr->sa_data; |
cfc77c2f SS |
2285 | u8 old_addr[6]; |
2286 | int rc; | |
8ceee660 | 2287 | |
8ceee660 | 2288 | if (!is_valid_ether_addr(new_addr)) { |
62776d03 BH |
2289 | netif_err(efx, drv, efx->net_dev, |
2290 | "invalid ethernet MAC address requested: %pM\n", | |
2291 | new_addr); | |
504f9b5a | 2292 | return -EADDRNOTAVAIL; |
8ceee660 BH |
2293 | } |
2294 | ||
cfc77c2f SS |
2295 | /* save old address */ |
2296 | ether_addr_copy(old_addr, net_dev->dev_addr); | |
cd84ff4d | 2297 | ether_addr_copy(net_dev->dev_addr, new_addr); |
910c8789 SS |
2298 | if (efx->type->set_mac_address) { |
2299 | rc = efx->type->set_mac_address(efx); | |
cfc77c2f SS |
2300 | if (rc) { |
2301 | ether_addr_copy(net_dev->dev_addr, old_addr); | |
2302 | return rc; | |
2303 | } | |
2304 | } | |
8ceee660 BH |
2305 | |
2306 | /* Reconfigure the MAC */ | |
d3245b28 | 2307 | mutex_lock(&efx->mac_lock); |
0d322413 | 2308 | efx_mac_reconfigure(efx); |
d3245b28 | 2309 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
2310 | |
2311 | return 0; | |
2312 | } | |
2313 | ||
a816f75a | 2314 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 2315 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 2316 | { |
767e468c | 2317 | struct efx_nic *efx = netdev_priv(net_dev); |
a816f75a | 2318 | |
8be4f3e6 BH |
2319 | if (efx->port_enabled) |
2320 | queue_work(efx->workqueue, &efx->mac_work); | |
2321 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
2322 | } |
2323 | ||
c8f44aff | 2324 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
2325 | { |
2326 | struct efx_nic *efx = netdev_priv(net_dev); | |
4a53ea8a | 2327 | int rc; |
abfe9039 BH |
2328 | |
2329 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
4a53ea8a AR |
2330 | if (net_dev->features & ~data & NETIF_F_NTUPLE) { |
2331 | rc = efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
2332 | if (rc) | |
2333 | return rc; | |
2334 | } | |
2335 | ||
2336 | /* If Rx VLAN filter is changed, update filters via mac_reconfigure */ | |
2337 | if ((net_dev->features ^ data) & NETIF_F_HW_VLAN_CTAG_FILTER) { | |
2338 | /* efx_set_rx_mode() will schedule MAC work to update filters | |
2339 | * when a new features are finally set in net_dev. | |
2340 | */ | |
2341 | efx_set_rx_mode(net_dev); | |
2342 | } | |
abfe9039 BH |
2343 | |
2344 | return 0; | |
2345 | } | |
2346 | ||
4a53ea8a AR |
2347 | static int efx_vlan_rx_add_vid(struct net_device *net_dev, __be16 proto, u16 vid) |
2348 | { | |
2349 | struct efx_nic *efx = netdev_priv(net_dev); | |
2350 | ||
2351 | if (efx->type->vlan_rx_add_vid) | |
2352 | return efx->type->vlan_rx_add_vid(efx, proto, vid); | |
2353 | else | |
2354 | return -EOPNOTSUPP; | |
2355 | } | |
2356 | ||
2357 | static int efx_vlan_rx_kill_vid(struct net_device *net_dev, __be16 proto, u16 vid) | |
2358 | { | |
2359 | struct efx_nic *efx = netdev_priv(net_dev); | |
2360 | ||
2361 | if (efx->type->vlan_rx_kill_vid) | |
2362 | return efx->type->vlan_rx_kill_vid(efx, proto, vid); | |
2363 | else | |
2364 | return -EOPNOTSUPP; | |
2365 | } | |
2366 | ||
7fa8d547 | 2367 | static const struct net_device_ops efx_netdev_ops = { |
c3ecb9f3 SH |
2368 | .ndo_open = efx_net_open, |
2369 | .ndo_stop = efx_net_stop, | |
4472702e | 2370 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
2371 | .ndo_tx_timeout = efx_watchdog, |
2372 | .ndo_start_xmit = efx_hard_start_xmit, | |
2373 | .ndo_validate_addr = eth_validate_addr, | |
2374 | .ndo_do_ioctl = efx_ioctl, | |
2375 | .ndo_change_mtu = efx_change_mtu, | |
2376 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2377 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2378 | .ndo_set_features = efx_set_features, |
4a53ea8a AR |
2379 | .ndo_vlan_rx_add_vid = efx_vlan_rx_add_vid, |
2380 | .ndo_vlan_rx_kill_vid = efx_vlan_rx_kill_vid, | |
cd2d5b52 | 2381 | #ifdef CONFIG_SFC_SRIOV |
7fa8d547 SS |
2382 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, |
2383 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2384 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2385 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
4392dc69 | 2386 | .ndo_set_vf_link_state = efx_sriov_set_vf_link_state, |
1d051e00 | 2387 | .ndo_get_phys_port_id = efx_sriov_get_phys_port_id, |
cd2d5b52 | 2388 | #endif |
c3ecb9f3 SH |
2389 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2390 | .ndo_poll_controller = efx_netpoll, | |
2391 | #endif | |
94b274bf | 2392 | .ndo_setup_tc = efx_setup_tc, |
36763266 AR |
2393 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2394 | .ndo_busy_poll = efx_busy_poll, | |
2395 | #endif | |
64d8ad6d BH |
2396 | #ifdef CONFIG_RFS_ACCEL |
2397 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2398 | #endif | |
c3ecb9f3 SH |
2399 | }; |
2400 | ||
7dde596e BH |
2401 | static void efx_update_name(struct efx_nic *efx) |
2402 | { | |
2403 | strcpy(efx->name, efx->net_dev->name); | |
2404 | efx_mtd_rename(efx); | |
2405 | efx_set_channel_names(efx); | |
2406 | } | |
2407 | ||
8ceee660 BH |
2408 | static int efx_netdev_event(struct notifier_block *this, |
2409 | unsigned long event, void *ptr) | |
2410 | { | |
351638e7 | 2411 | struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); |
8ceee660 | 2412 | |
7fa8d547 | 2413 | if ((net_dev->netdev_ops == &efx_netdev_ops) && |
7dde596e BH |
2414 | event == NETDEV_CHANGENAME) |
2415 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2416 | |
2417 | return NOTIFY_DONE; | |
2418 | } | |
2419 | ||
2420 | static struct notifier_block efx_netdev_notifier = { | |
2421 | .notifier_call = efx_netdev_event, | |
2422 | }; | |
2423 | ||
06d5e193 BH |
2424 | static ssize_t |
2425 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2426 | { | |
2427 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2428 | return sprintf(buf, "%d\n", efx->phy_type); | |
2429 | } | |
776fbcc9 | 2430 | static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); |
06d5e193 | 2431 | |
e7fef9b4 EC |
2432 | #ifdef CONFIG_SFC_MCDI_LOGGING |
2433 | static ssize_t show_mcdi_log(struct device *dev, struct device_attribute *attr, | |
2434 | char *buf) | |
2435 | { | |
2436 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2437 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
2438 | ||
2439 | return scnprintf(buf, PAGE_SIZE, "%d\n", mcdi->logging_enabled); | |
2440 | } | |
2441 | static ssize_t set_mcdi_log(struct device *dev, struct device_attribute *attr, | |
2442 | const char *buf, size_t count) | |
2443 | { | |
2444 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2445 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
2446 | bool enable = count > 0 && *buf != '0'; | |
2447 | ||
2448 | mcdi->logging_enabled = enable; | |
2449 | return count; | |
2450 | } | |
2451 | static DEVICE_ATTR(mcdi_logging, 0644, show_mcdi_log, set_mcdi_log); | |
2452 | #endif | |
2453 | ||
8ceee660 BH |
2454 | static int efx_register_netdev(struct efx_nic *efx) |
2455 | { | |
2456 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2457 | struct efx_channel *channel; |
8ceee660 BH |
2458 | int rc; |
2459 | ||
2460 | net_dev->watchdog_timeo = 5 * HZ; | |
2461 | net_dev->irq = efx->pci_dev->irq; | |
7fa8d547 SS |
2462 | net_dev->netdev_ops = &efx_netdev_ops; |
2463 | if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) | |
8127d661 | 2464 | net_dev->priv_flags |= IFF_UNICAST_FLT; |
7ad24ea4 | 2465 | net_dev->ethtool_ops = &efx_ethtool_ops; |
7e6d06f0 | 2466 | net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; |
8ceee660 | 2467 | |
7dde596e | 2468 | rtnl_lock(); |
aed0628d | 2469 | |
7153f623 BH |
2470 | /* Enable resets to be scheduled and check whether any were |
2471 | * already requested. If so, the NIC is probably hosed so we | |
2472 | * abort. | |
2473 | */ | |
2474 | efx->state = STATE_READY; | |
2475 | smp_mb(); /* ensure we change state before checking reset_pending */ | |
2476 | if (efx->reset_pending) { | |
2477 | netif_err(efx, probe, efx->net_dev, | |
2478 | "aborting probe due to scheduled reset\n"); | |
2479 | rc = -EIO; | |
2480 | goto fail_locked; | |
2481 | } | |
2482 | ||
aed0628d BH |
2483 | rc = dev_alloc_name(net_dev, net_dev->name); |
2484 | if (rc < 0) | |
2485 | goto fail_locked; | |
7dde596e | 2486 | efx_update_name(efx); |
aed0628d | 2487 | |
8f8b3d51 BH |
2488 | /* Always start with carrier off; PHY events will detect the link */ |
2489 | netif_carrier_off(net_dev); | |
2490 | ||
aed0628d BH |
2491 | rc = register_netdevice(net_dev); |
2492 | if (rc) | |
2493 | goto fail_locked; | |
2494 | ||
c04bfc6b BH |
2495 | efx_for_each_channel(channel, efx) { |
2496 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2497 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2498 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2499 | } |
2500 | ||
0bcf4a64 BH |
2501 | efx_associate(efx); |
2502 | ||
7dde596e | 2503 | rtnl_unlock(); |
8ceee660 | 2504 | |
06d5e193 BH |
2505 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2506 | if (rc) { | |
62776d03 BH |
2507 | netif_err(efx, drv, efx->net_dev, |
2508 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2509 | goto fail_registered; |
2510 | } | |
e7fef9b4 EC |
2511 | #ifdef CONFIG_SFC_MCDI_LOGGING |
2512 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging); | |
2513 | if (rc) { | |
2514 | netif_err(efx, drv, efx->net_dev, | |
2515 | "failed to init net dev attributes\n"); | |
2516 | goto fail_attr_mcdi_logging; | |
2517 | } | |
2518 | #endif | |
06d5e193 | 2519 | |
8ceee660 | 2520 | return 0; |
06d5e193 | 2521 | |
e7fef9b4 EC |
2522 | #ifdef CONFIG_SFC_MCDI_LOGGING |
2523 | fail_attr_mcdi_logging: | |
2524 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
2525 | #endif | |
7153f623 BH |
2526 | fail_registered: |
2527 | rtnl_lock(); | |
0bcf4a64 | 2528 | efx_dissociate(efx); |
7153f623 | 2529 | unregister_netdevice(net_dev); |
aed0628d | 2530 | fail_locked: |
7153f623 | 2531 | efx->state = STATE_UNINIT; |
aed0628d | 2532 | rtnl_unlock(); |
62776d03 | 2533 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d | 2534 | return rc; |
8ceee660 BH |
2535 | } |
2536 | ||
2537 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2538 | { | |
8ceee660 BH |
2539 | if (!efx->net_dev) |
2540 | return; | |
2541 | ||
767e468c | 2542 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 | 2543 | |
e7fef9b4 EC |
2544 | if (efx_dev_registered(efx)) { |
2545 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); | |
2546 | #ifdef CONFIG_SFC_MCDI_LOGGING | |
2547 | device_remove_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging); | |
2548 | #endif | |
2549 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
2550 | unregister_netdev(efx->net_dev); | |
2551 | } | |
8ceee660 BH |
2552 | } |
2553 | ||
2554 | /************************************************************************** | |
2555 | * | |
2556 | * Device reset and suspend | |
2557 | * | |
2558 | **************************************************************************/ | |
2559 | ||
2467ca46 BH |
2560 | /* Tears down the entire software state and most of the hardware state |
2561 | * before reset. */ | |
d3245b28 | 2562 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2563 | { |
8ceee660 BH |
2564 | EFX_ASSERT_RESET_SERIALISED(efx); |
2565 | ||
e283546c EC |
2566 | if (method == RESET_TYPE_MCDI_TIMEOUT) |
2567 | efx->type->prepare_flr(efx); | |
2568 | ||
2467ca46 | 2569 | efx_stop_all(efx); |
d8291187 | 2570 | efx_disable_interrupts(efx); |
5642ceef BH |
2571 | |
2572 | mutex_lock(&efx->mac_lock); | |
087e9025 JC |
2573 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE && |
2574 | method != RESET_TYPE_DATAPATH) | |
4b988280 | 2575 | efx->phy_op->fini(efx); |
ef2b90ee | 2576 | efx->type->fini(efx); |
8ceee660 BH |
2577 | } |
2578 | ||
2467ca46 BH |
2579 | /* This function will always ensure that the locks acquired in |
2580 | * efx_reset_down() are released. A failure return code indicates | |
2581 | * that we were unable to reinitialise the hardware, and the | |
2582 | * driver should be disabled. If ok is false, then the rx and tx | |
2583 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2584 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2585 | { |
2586 | int rc; | |
2587 | ||
2467ca46 | 2588 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2589 | |
e283546c EC |
2590 | if (method == RESET_TYPE_MCDI_TIMEOUT) |
2591 | efx->type->finish_flr(efx); | |
2592 | ||
2593 | /* Ensure that SRAM is initialised even if we're disabling the device */ | |
ef2b90ee | 2594 | rc = efx->type->init(efx); |
8ceee660 | 2595 | if (rc) { |
62776d03 | 2596 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2597 | goto fail; |
8ceee660 BH |
2598 | } |
2599 | ||
eb9f6744 BH |
2600 | if (!ok) |
2601 | goto fail; | |
2602 | ||
087e9025 JC |
2603 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE && |
2604 | method != RESET_TYPE_DATAPATH) { | |
eb9f6744 BH |
2605 | rc = efx->phy_op->init(efx); |
2606 | if (rc) | |
2607 | goto fail; | |
267d9d73 EC |
2608 | rc = efx->phy_op->reconfigure(efx); |
2609 | if (rc && rc != -EPERM) | |
62776d03 BH |
2610 | netif_err(efx, drv, efx->net_dev, |
2611 | "could not restore PHY settings\n"); | |
4b988280 SH |
2612 | } |
2613 | ||
261e4d96 JC |
2614 | rc = efx_enable_interrupts(efx); |
2615 | if (rc) | |
2616 | goto fail; | |
6d8aaaf6 DP |
2617 | |
2618 | #ifdef CONFIG_SFC_SRIOV | |
2619 | rc = efx->type->vswitching_restore(efx); | |
2620 | if (rc) /* not fatal; the PF will still work fine */ | |
2621 | netif_warn(efx, probe, efx->net_dev, | |
2622 | "failed to restore vswitching rc=%d;" | |
2623 | " VFs may not function\n", rc); | |
2624 | #endif | |
2625 | ||
0d322413 | 2626 | down_read(&efx->filter_sem); |
64eebcfd | 2627 | efx_restore_filters(efx); |
0d322413 | 2628 | up_read(&efx->filter_sem); |
7fa8d547 SS |
2629 | if (efx->type->sriov_reset) |
2630 | efx->type->sriov_reset(efx); | |
eb9f6744 | 2631 | |
eb9f6744 BH |
2632 | mutex_unlock(&efx->mac_lock); |
2633 | ||
2634 | efx_start_all(efx); | |
2635 | ||
2636 | return 0; | |
2637 | ||
2638 | fail: | |
2639 | efx->port_initialized = false; | |
2467ca46 BH |
2640 | |
2641 | mutex_unlock(&efx->mac_lock); | |
2642 | ||
8ceee660 BH |
2643 | return rc; |
2644 | } | |
2645 | ||
eb9f6744 BH |
2646 | /* Reset the NIC using the specified method. Note that the reset may |
2647 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2648 | * |
eb9f6744 | 2649 | * Caller must hold the rtnl_lock. |
8ceee660 | 2650 | */ |
eb9f6744 | 2651 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2652 | { |
eb9f6744 BH |
2653 | int rc, rc2; |
2654 | bool disabled; | |
8ceee660 | 2655 | |
62776d03 BH |
2656 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2657 | RESET_TYPE(method)); | |
8ceee660 | 2658 | |
c2f3b8e3 | 2659 | efx_device_detach_sync(efx); |
d3245b28 | 2660 | efx_reset_down(efx, method); |
8ceee660 | 2661 | |
ef2b90ee | 2662 | rc = efx->type->reset(efx, method); |
8ceee660 | 2663 | if (rc) { |
62776d03 | 2664 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2665 | goto out; |
8ceee660 BH |
2666 | } |
2667 | ||
a7d529ae BH |
2668 | /* Clear flags for the scopes we covered. We assume the NIC and |
2669 | * driver are now quiescent so that there is no race here. | |
2670 | */ | |
e283546c EC |
2671 | if (method < RESET_TYPE_MAX_METHOD) |
2672 | efx->reset_pending &= -(1 << (method + 1)); | |
2673 | else /* it doesn't fit into the well-ordered scope hierarchy */ | |
2674 | __clear_bit(method, &efx->reset_pending); | |
8ceee660 BH |
2675 | |
2676 | /* Reinitialise bus-mastering, which may have been turned off before | |
2677 | * the reset was scheduled. This is still appropriate, even in the | |
2678 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2679 | * can respond to requests. */ | |
2680 | pci_set_master(efx->pci_dev); | |
2681 | ||
eb9f6744 | 2682 | out: |
8ceee660 | 2683 | /* Leave device stopped if necessary */ |
626950db AR |
2684 | disabled = rc || |
2685 | method == RESET_TYPE_DISABLE || | |
2686 | method == RESET_TYPE_RECOVER_OR_DISABLE; | |
eb9f6744 BH |
2687 | rc2 = efx_reset_up(efx, method, !disabled); |
2688 | if (rc2) { | |
2689 | disabled = true; | |
2690 | if (!rc) | |
2691 | rc = rc2; | |
8ceee660 BH |
2692 | } |
2693 | ||
eb9f6744 | 2694 | if (disabled) { |
f49a4589 | 2695 | dev_close(efx->net_dev); |
62776d03 | 2696 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2697 | efx->state = STATE_DISABLED; |
f4bd954e | 2698 | } else { |
62776d03 | 2699 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2700 | netif_device_attach(efx->net_dev); |
f4bd954e | 2701 | } |
8ceee660 BH |
2702 | return rc; |
2703 | } | |
2704 | ||
626950db AR |
2705 | /* Try recovery mechanisms. |
2706 | * For now only EEH is supported. | |
2707 | * Returns 0 if the recovery mechanisms are unsuccessful. | |
2708 | * Returns a non-zero value otherwise. | |
2709 | */ | |
b28405b0 | 2710 | int efx_try_recovery(struct efx_nic *efx) |
626950db AR |
2711 | { |
2712 | #ifdef CONFIG_EEH | |
2713 | /* A PCI error can occur and not be seen by EEH because nothing | |
2714 | * happens on the PCI bus. In this case the driver may fail and | |
2715 | * schedule a 'recover or reset', leading to this recovery handler. | |
2716 | * Manually call the eeh failure check function. | |
2717 | */ | |
12a89dba | 2718 | struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev); |
626950db AR |
2719 | if (eeh_dev_check_failure(eehdev)) { |
2720 | /* The EEH mechanisms will handle the error and reset the | |
2721 | * device if necessary. | |
2722 | */ | |
2723 | return 1; | |
2724 | } | |
2725 | #endif | |
2726 | return 0; | |
2727 | } | |
2728 | ||
74cd60a4 JC |
2729 | static void efx_wait_for_bist_end(struct efx_nic *efx) |
2730 | { | |
2731 | int i; | |
2732 | ||
2733 | for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) { | |
2734 | if (efx_mcdi_poll_reboot(efx)) | |
2735 | goto out; | |
2736 | msleep(BIST_WAIT_DELAY_MS); | |
2737 | } | |
2738 | ||
2739 | netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n"); | |
2740 | out: | |
2741 | /* Either way unset the BIST flag. If we found no reboot we probably | |
2742 | * won't recover, but we should try. | |
2743 | */ | |
2744 | efx->mc_bist_for_other_fn = false; | |
2745 | } | |
2746 | ||
8ceee660 BH |
2747 | /* The worker thread exists so that code that cannot sleep can |
2748 | * schedule a reset for later. | |
2749 | */ | |
2750 | static void efx_reset_work(struct work_struct *data) | |
2751 | { | |
eb9f6744 | 2752 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
626950db AR |
2753 | unsigned long pending; |
2754 | enum reset_type method; | |
2755 | ||
2756 | pending = ACCESS_ONCE(efx->reset_pending); | |
2757 | method = fls(pending) - 1; | |
2758 | ||
74cd60a4 JC |
2759 | if (method == RESET_TYPE_MC_BIST) |
2760 | efx_wait_for_bist_end(efx); | |
2761 | ||
626950db AR |
2762 | if ((method == RESET_TYPE_RECOVER_OR_DISABLE || |
2763 | method == RESET_TYPE_RECOVER_OR_ALL) && | |
2764 | efx_try_recovery(efx)) | |
2765 | return; | |
8ceee660 | 2766 | |
a7d529ae | 2767 | if (!pending) |
319ba649 SH |
2768 | return; |
2769 | ||
eb9f6744 | 2770 | rtnl_lock(); |
7153f623 BH |
2771 | |
2772 | /* We checked the state in efx_schedule_reset() but it may | |
2773 | * have changed by now. Now that we have the RTNL lock, | |
2774 | * it cannot change again. | |
2775 | */ | |
2776 | if (efx->state == STATE_READY) | |
626950db | 2777 | (void)efx_reset(efx, method); |
7153f623 | 2778 | |
eb9f6744 | 2779 | rtnl_unlock(); |
8ceee660 BH |
2780 | } |
2781 | ||
2782 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2783 | { | |
2784 | enum reset_type method; | |
2785 | ||
626950db AR |
2786 | if (efx->state == STATE_RECOVERY) { |
2787 | netif_dbg(efx, drv, efx->net_dev, | |
2788 | "recovering: skip scheduling %s reset\n", | |
2789 | RESET_TYPE(type)); | |
2790 | return; | |
2791 | } | |
2792 | ||
8ceee660 BH |
2793 | switch (type) { |
2794 | case RESET_TYPE_INVISIBLE: | |
2795 | case RESET_TYPE_ALL: | |
626950db | 2796 | case RESET_TYPE_RECOVER_OR_ALL: |
8ceee660 BH |
2797 | case RESET_TYPE_WORLD: |
2798 | case RESET_TYPE_DISABLE: | |
626950db | 2799 | case RESET_TYPE_RECOVER_OR_DISABLE: |
087e9025 | 2800 | case RESET_TYPE_DATAPATH: |
74cd60a4 | 2801 | case RESET_TYPE_MC_BIST: |
e283546c | 2802 | case RESET_TYPE_MCDI_TIMEOUT: |
8ceee660 | 2803 | method = type; |
0e2a9c7c BH |
2804 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2805 | RESET_TYPE(method)); | |
8ceee660 | 2806 | break; |
8ceee660 | 2807 | default: |
0e2a9c7c | 2808 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2809 | netif_dbg(efx, drv, efx->net_dev, |
2810 | "scheduling %s reset for %s\n", | |
2811 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2812 | break; |
2813 | } | |
8ceee660 | 2814 | |
a7d529ae | 2815 | set_bit(method, &efx->reset_pending); |
7153f623 BH |
2816 | smp_mb(); /* ensure we change reset_pending before checking state */ |
2817 | ||
2818 | /* If we're not READY then just leave the flags set as the cue | |
2819 | * to abort probing or reschedule the reset later. | |
2820 | */ | |
2821 | if (ACCESS_ONCE(efx->state) != STATE_READY) | |
2822 | return; | |
8ceee660 | 2823 | |
8880f4ec BH |
2824 | /* efx_process_channel() will no longer read events once a |
2825 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2826 | efx_mcdi_mode_poll(efx); | |
2827 | ||
1ab00629 | 2828 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2829 | } |
2830 | ||
2831 | /************************************************************************** | |
2832 | * | |
2833 | * List of NICs we support | |
2834 | * | |
2835 | **************************************************************************/ | |
2836 | ||
2837 | /* PCI device ID table */ | |
9baa3c34 | 2838 | static const struct pci_device_id efx_pci_table[] = { |
937383a5 BH |
2839 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2840 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2841 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2842 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2843 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2844 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2845 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2846 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2847 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2848 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8127d661 BH |
2849 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */ |
2850 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
6f7f8aa6 SS |
2851 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1903), /* SFC9120 VF */ |
2852 | .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type}, | |
3b06a00e MW |
2853 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0923), /* SFC9140 PF */ |
2854 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
dd248f1b BK |
2855 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1923), /* SFC9140 VF */ |
2856 | .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type}, | |
2857 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0a03), /* SFC9220 PF */ | |
2858 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
2859 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1a03), /* SFC9220 VF */ | |
2860 | .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type}, | |
8ceee660 BH |
2861 | {0} /* end of list */ |
2862 | }; | |
2863 | ||
2864 | /************************************************************************** | |
2865 | * | |
3759433d | 2866 | * Dummy PHY/MAC operations |
8ceee660 | 2867 | * |
01aad7b6 | 2868 | * Can be used for some unimplemented operations |
8ceee660 BH |
2869 | * Needed so all function pointers are valid and do not have to be tested |
2870 | * before use | |
2871 | * | |
2872 | **************************************************************************/ | |
2873 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2874 | { | |
2875 | return 0; | |
2876 | } | |
2877 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2878 | |
2879 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2880 | { |
2881 | return false; | |
2882 | } | |
8ceee660 | 2883 | |
6c8c2513 | 2884 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2885 | .init = efx_port_dummy_op_int, |
d3245b28 | 2886 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2887 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2888 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2889 | }; |
2890 | ||
8ceee660 BH |
2891 | /************************************************************************** |
2892 | * | |
2893 | * Data housekeeping | |
2894 | * | |
2895 | **************************************************************************/ | |
2896 | ||
2897 | /* This zeroes out and then fills in the invariants in a struct | |
2898 | * efx_nic (including all sub-structures). | |
2899 | */ | |
adeb15aa | 2900 | static int efx_init_struct(struct efx_nic *efx, |
8ceee660 BH |
2901 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2902 | { | |
4642610c | 2903 | int i; |
8ceee660 BH |
2904 | |
2905 | /* Initialise common structures */ | |
0bcf4a64 BH |
2906 | INIT_LIST_HEAD(&efx->node); |
2907 | INIT_LIST_HEAD(&efx->secondary_list); | |
8ceee660 | 2908 | spin_lock_init(&efx->biu_lock); |
76884835 BH |
2909 | #ifdef CONFIG_SFC_MTD |
2910 | INIT_LIST_HEAD(&efx->mtd_list); | |
2911 | #endif | |
8ceee660 BH |
2912 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2913 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
dd40781e | 2914 | INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); |
8ceee660 | 2915 | efx->pci_dev = pci_dev; |
62776d03 | 2916 | efx->msg_enable = debug; |
f16aeea0 | 2917 | efx->state = STATE_UNINIT; |
8ceee660 | 2918 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2919 | |
2920 | efx->net_dev = net_dev; | |
43a3739d | 2921 | efx->rx_prefix_size = efx->type->rx_prefix_size; |
2ec03014 AR |
2922 | efx->rx_ip_align = |
2923 | NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0; | |
43a3739d JC |
2924 | efx->rx_packet_hash_offset = |
2925 | efx->type->rx_hash_offset - efx->type->rx_prefix_size; | |
bd9a265d JC |
2926 | efx->rx_packet_ts_offset = |
2927 | efx->type->rx_ts_offset - efx->type->rx_prefix_size; | |
8ceee660 BH |
2928 | spin_lock_init(&efx->stats_lock); |
2929 | mutex_init(&efx->mac_lock); | |
2930 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2931 | efx->mdio.dev = net_dev; |
766ca0fa | 2932 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2933 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2934 | |
2935 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2936 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2937 | if (!efx->channel[i]) | |
2938 | goto fail; | |
d8291187 BH |
2939 | efx->msi_context[i].efx = efx; |
2940 | efx->msi_context[i].index = i; | |
8ceee660 BH |
2941 | } |
2942 | ||
8ceee660 BH |
2943 | /* Higher numbered interrupt modes are less capable! */ |
2944 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2945 | interrupt_mode); | |
2946 | ||
6977dc63 BH |
2947 | /* Would be good to use the net_dev name, but we're too early */ |
2948 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2949 | pci_name(pci_dev)); | |
2950 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2951 | if (!efx->workqueue) |
4642610c | 2952 | goto fail; |
8d9853d9 | 2953 | |
8ceee660 | 2954 | return 0; |
4642610c BH |
2955 | |
2956 | fail: | |
2957 | efx_fini_struct(efx); | |
2958 | return -ENOMEM; | |
8ceee660 BH |
2959 | } |
2960 | ||
2961 | static void efx_fini_struct(struct efx_nic *efx) | |
2962 | { | |
8313aca3 BH |
2963 | int i; |
2964 | ||
2965 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2966 | kfree(efx->channel[i]); | |
2967 | ||
ef215e64 BH |
2968 | kfree(efx->vpd_sn); |
2969 | ||
8ceee660 BH |
2970 | if (efx->workqueue) { |
2971 | destroy_workqueue(efx->workqueue); | |
2972 | efx->workqueue = NULL; | |
2973 | } | |
2974 | } | |
2975 | ||
e4d112e4 EC |
2976 | void efx_update_sw_stats(struct efx_nic *efx, u64 *stats) |
2977 | { | |
2978 | u64 n_rx_nodesc_trunc = 0; | |
2979 | struct efx_channel *channel; | |
2980 | ||
2981 | efx_for_each_channel(channel, efx) | |
2982 | n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc; | |
2983 | stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc; | |
2984 | stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops); | |
2985 | } | |
2986 | ||
8ceee660 BH |
2987 | /************************************************************************** |
2988 | * | |
2989 | * PCI interface | |
2990 | * | |
2991 | **************************************************************************/ | |
2992 | ||
2993 | /* Main body of final NIC shutdown code | |
2994 | * This is called only at module unload (or hotplug removal). | |
2995 | */ | |
2996 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2997 | { | |
7153f623 BH |
2998 | /* Flush reset_work. It can no longer be scheduled since we |
2999 | * are not READY. | |
3000 | */ | |
3001 | BUG_ON(efx->state == STATE_READY); | |
3002 | cancel_work_sync(&efx->reset_work); | |
3003 | ||
d8291187 | 3004 | efx_disable_interrupts(efx); |
152b6a62 | 3005 | efx_nic_fini_interrupt(efx); |
8ceee660 | 3006 | efx_fini_port(efx); |
ef2b90ee | 3007 | efx->type->fini(efx); |
8ceee660 BH |
3008 | efx_fini_napi(efx); |
3009 | efx_remove_all(efx); | |
3010 | } | |
3011 | ||
3012 | /* Final NIC shutdown | |
2a3fc311 DP |
3013 | * This is called only at module unload (or hotplug removal). A PF can call |
3014 | * this on its VFs to ensure they are unbound first. | |
8ceee660 BH |
3015 | */ |
3016 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
3017 | { | |
3018 | struct efx_nic *efx; | |
3019 | ||
3020 | efx = pci_get_drvdata(pci_dev); | |
3021 | if (!efx) | |
3022 | return; | |
3023 | ||
3024 | /* Mark the NIC as fini, then stop the interface */ | |
3025 | rtnl_lock(); | |
0bcf4a64 | 3026 | efx_dissociate(efx); |
8ceee660 | 3027 | dev_close(efx->net_dev); |
d8291187 | 3028 | efx_disable_interrupts(efx); |
ea6bb99e | 3029 | efx->state = STATE_UNINIT; |
8ceee660 BH |
3030 | rtnl_unlock(); |
3031 | ||
7fa8d547 SS |
3032 | if (efx->type->sriov_fini) |
3033 | efx->type->sriov_fini(efx); | |
3034 | ||
8ceee660 BH |
3035 | efx_unregister_netdev(efx); |
3036 | ||
7dde596e BH |
3037 | efx_mtd_remove(efx); |
3038 | ||
8ceee660 BH |
3039 | efx_pci_remove_main(efx); |
3040 | ||
8ceee660 | 3041 | efx_fini_io(efx); |
62776d03 | 3042 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 | 3043 | |
8ceee660 BH |
3044 | efx_fini_struct(efx); |
3045 | free_netdev(efx->net_dev); | |
626950db AR |
3046 | |
3047 | pci_disable_pcie_error_reporting(pci_dev); | |
8ceee660 BH |
3048 | }; |
3049 | ||
460eeaa0 BH |
3050 | /* NIC VPD information |
3051 | * Called during probe to display the part number of the | |
3052 | * installed NIC. VPD is potentially very large but this should | |
3053 | * always appear within the first 512 bytes. | |
3054 | */ | |
3055 | #define SFC_VPD_LEN 512 | |
ef215e64 | 3056 | static void efx_probe_vpd_strings(struct efx_nic *efx) |
460eeaa0 BH |
3057 | { |
3058 | struct pci_dev *dev = efx->pci_dev; | |
3059 | char vpd_data[SFC_VPD_LEN]; | |
3060 | ssize_t vpd_size; | |
ef215e64 | 3061 | int ro_start, ro_size, i, j; |
460eeaa0 BH |
3062 | |
3063 | /* Get the vpd data from the device */ | |
3064 | vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); | |
3065 | if (vpd_size <= 0) { | |
3066 | netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); | |
3067 | return; | |
3068 | } | |
3069 | ||
3070 | /* Get the Read only section */ | |
ef215e64 BH |
3071 | ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); |
3072 | if (ro_start < 0) { | |
460eeaa0 BH |
3073 | netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); |
3074 | return; | |
3075 | } | |
3076 | ||
ef215e64 BH |
3077 | ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); |
3078 | j = ro_size; | |
3079 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
460eeaa0 BH |
3080 | if (i + j > vpd_size) |
3081 | j = vpd_size - i; | |
3082 | ||
3083 | /* Get the Part number */ | |
3084 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); | |
3085 | if (i < 0) { | |
3086 | netif_err(efx, drv, efx->net_dev, "Part number not found\n"); | |
3087 | return; | |
3088 | } | |
3089 | ||
3090 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
3091 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
3092 | if (i + j > vpd_size) { | |
3093 | netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); | |
3094 | return; | |
3095 | } | |
3096 | ||
3097 | netif_info(efx, drv, efx->net_dev, | |
3098 | "Part Number : %.*s\n", j, &vpd_data[i]); | |
ef215e64 BH |
3099 | |
3100 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
3101 | j = ro_size; | |
3102 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN"); | |
3103 | if (i < 0) { | |
3104 | netif_err(efx, drv, efx->net_dev, "Serial number not found\n"); | |
3105 | return; | |
3106 | } | |
3107 | ||
3108 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
3109 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
3110 | if (i + j > vpd_size) { | |
3111 | netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n"); | |
3112 | return; | |
3113 | } | |
3114 | ||
3115 | efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL); | |
3116 | if (!efx->vpd_sn) | |
3117 | return; | |
3118 | ||
3119 | snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]); | |
460eeaa0 BH |
3120 | } |
3121 | ||
3122 | ||
8ceee660 BH |
3123 | /* Main body of NIC initialisation |
3124 | * This is called at module load (or hotplug insertion, theoretically). | |
3125 | */ | |
3126 | static int efx_pci_probe_main(struct efx_nic *efx) | |
3127 | { | |
3128 | int rc; | |
3129 | ||
3130 | /* Do start-of-day initialisation */ | |
3131 | rc = efx_probe_all(efx); | |
3132 | if (rc) | |
3133 | goto fail1; | |
3134 | ||
e8f14992 | 3135 | efx_init_napi(efx); |
8ceee660 | 3136 | |
ef2b90ee | 3137 | rc = efx->type->init(efx); |
8ceee660 | 3138 | if (rc) { |
62776d03 BH |
3139 | netif_err(efx, probe, efx->net_dev, |
3140 | "failed to initialise NIC\n"); | |
278c0621 | 3141 | goto fail3; |
8ceee660 BH |
3142 | } |
3143 | ||
3144 | rc = efx_init_port(efx); | |
3145 | if (rc) { | |
62776d03 BH |
3146 | netif_err(efx, probe, efx->net_dev, |
3147 | "failed to initialise port\n"); | |
278c0621 | 3148 | goto fail4; |
8ceee660 BH |
3149 | } |
3150 | ||
152b6a62 | 3151 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 3152 | if (rc) |
278c0621 | 3153 | goto fail5; |
261e4d96 JC |
3154 | rc = efx_enable_interrupts(efx); |
3155 | if (rc) | |
3156 | goto fail6; | |
8ceee660 BH |
3157 | |
3158 | return 0; | |
3159 | ||
261e4d96 JC |
3160 | fail6: |
3161 | efx_nic_fini_interrupt(efx); | |
278c0621 | 3162 | fail5: |
8ceee660 | 3163 | efx_fini_port(efx); |
8ceee660 | 3164 | fail4: |
ef2b90ee | 3165 | efx->type->fini(efx); |
8ceee660 BH |
3166 | fail3: |
3167 | efx_fini_napi(efx); | |
8ceee660 BH |
3168 | efx_remove_all(efx); |
3169 | fail1: | |
3170 | return rc; | |
3171 | } | |
3172 | ||
3173 | /* NIC initialisation | |
3174 | * | |
3175 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 3176 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
3177 | * sets up and registers the network devices with the kernel and hooks |
3178 | * the interrupt service routine. It does not prepare the device for | |
3179 | * transmission; this is left to the first time one of the network | |
3180 | * interfaces is brought up (i.e. efx_net_open). | |
3181 | */ | |
87d1fc11 | 3182 | static int efx_pci_probe(struct pci_dev *pci_dev, |
1dd06ae8 | 3183 | const struct pci_device_id *entry) |
8ceee660 | 3184 | { |
8ceee660 BH |
3185 | struct net_device *net_dev; |
3186 | struct efx_nic *efx; | |
fadac6aa | 3187 | int rc; |
8ceee660 BH |
3188 | |
3189 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
3190 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
3191 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
3192 | if (!net_dev) |
3193 | return -ENOMEM; | |
adeb15aa BH |
3194 | efx = netdev_priv(net_dev); |
3195 | efx->type = (const struct efx_nic_type *) entry->driver_data; | |
ebfcd0fd | 3196 | efx->fixed_features |= NETIF_F_HIGHDMA; |
adeb15aa | 3197 | net_dev->features |= (efx->type->offload_features | NETIF_F_SG | |
ebfcd0fd | 3198 | NETIF_F_TSO | NETIF_F_RXCSUM); |
c8cd0989 | 3199 | if (efx->type->offload_features & (NETIF_F_IPV6_CSUM | NETIF_F_HW_CSUM)) |
738a8f4b | 3200 | net_dev->features |= NETIF_F_TSO6; |
28506563 | 3201 | /* Mask for features that also apply to VLAN devices */ |
a188222b | 3202 | net_dev->vlan_features |= (NETIF_F_HW_CSUM | NETIF_F_SG | |
abfe9039 BH |
3203 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
3204 | NETIF_F_RXCSUM); | |
eb7cfd8c | 3205 | |
ebfcd0fd | 3206 | net_dev->hw_features = net_dev->features & ~efx->fixed_features; |
eb7cfd8c AR |
3207 | |
3208 | /* Disable VLAN filtering by default. It may be enforced if | |
3209 | * the feature is fixed (i.e. VLAN filters are required to | |
3210 | * receive VLAN tagged packets due to vPort restrictions). | |
3211 | */ | |
3212 | net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; | |
3213 | net_dev->features |= efx->fixed_features; | |
3214 | ||
8ceee660 | 3215 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 3216 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
adeb15aa | 3217 | rc = efx_init_struct(efx, pci_dev, net_dev); |
8ceee660 BH |
3218 | if (rc) |
3219 | goto fail1; | |
3220 | ||
62776d03 | 3221 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 3222 | "Solarflare NIC detected\n"); |
8ceee660 | 3223 | |
6f7f8aa6 SS |
3224 | if (!efx->type->is_vf) |
3225 | efx_probe_vpd_strings(efx); | |
460eeaa0 | 3226 | |
8ceee660 BH |
3227 | /* Set up basic I/O (BAR mappings etc) */ |
3228 | rc = efx_init_io(efx); | |
3229 | if (rc) | |
3230 | goto fail2; | |
3231 | ||
fadac6aa | 3232 | rc = efx_pci_probe_main(efx); |
fadac6aa BH |
3233 | if (rc) |
3234 | goto fail3; | |
8ceee660 | 3235 | |
8ceee660 BH |
3236 | rc = efx_register_netdev(efx); |
3237 | if (rc) | |
fadac6aa | 3238 | goto fail4; |
8ceee660 | 3239 | |
7fa8d547 SS |
3240 | if (efx->type->sriov_init) { |
3241 | rc = efx->type->sriov_init(efx); | |
3242 | if (rc) | |
3243 | netif_err(efx, probe, efx->net_dev, | |
3244 | "SR-IOV can't be enabled rc %d\n", rc); | |
3245 | } | |
cd2d5b52 | 3246 | |
62776d03 | 3247 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 3248 | |
7c43161c | 3249 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 3250 | rtnl_lock(); |
7c43161c | 3251 | rc = efx_mtd_probe(efx); |
a5211bb5 | 3252 | rtnl_unlock(); |
09a04204 | 3253 | if (rc && rc != -EPERM) |
7c43161c BH |
3254 | netif_warn(efx, probe, efx->net_dev, |
3255 | "failed to create MTDs (%d)\n", rc); | |
3256 | ||
626950db AR |
3257 | rc = pci_enable_pcie_error_reporting(pci_dev); |
3258 | if (rc && rc != -EINVAL) | |
09a04204 BK |
3259 | netif_notice(efx, probe, efx->net_dev, |
3260 | "PCIE error reporting unavailable (%d).\n", | |
3261 | rc); | |
626950db | 3262 | |
8ceee660 BH |
3263 | return 0; |
3264 | ||
8ceee660 | 3265 | fail4: |
fadac6aa | 3266 | efx_pci_remove_main(efx); |
8ceee660 BH |
3267 | fail3: |
3268 | efx_fini_io(efx); | |
3269 | fail2: | |
3270 | efx_fini_struct(efx); | |
3271 | fail1: | |
5e2a911c | 3272 | WARN_ON(rc > 0); |
62776d03 | 3273 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
3274 | free_netdev(net_dev); |
3275 | return rc; | |
3276 | } | |
3277 | ||
834e23dd SS |
3278 | /* efx_pci_sriov_configure returns the actual number of Virtual Functions |
3279 | * enabled on success | |
3280 | */ | |
3281 | #ifdef CONFIG_SFC_SRIOV | |
3282 | static int efx_pci_sriov_configure(struct pci_dev *dev, int num_vfs) | |
3283 | { | |
3284 | int rc; | |
3285 | struct efx_nic *efx = pci_get_drvdata(dev); | |
3286 | ||
3287 | if (efx->type->sriov_configure) { | |
3288 | rc = efx->type->sriov_configure(efx, num_vfs); | |
3289 | if (rc) | |
3290 | return rc; | |
3291 | else | |
3292 | return num_vfs; | |
3293 | } else | |
3294 | return -EOPNOTSUPP; | |
3295 | } | |
3296 | #endif | |
3297 | ||
89c758fa BH |
3298 | static int efx_pm_freeze(struct device *dev) |
3299 | { | |
3300 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
3301 | ||
61da026d BH |
3302 | rtnl_lock(); |
3303 | ||
6032fb56 BH |
3304 | if (efx->state != STATE_DISABLED) { |
3305 | efx->state = STATE_UNINIT; | |
89c758fa | 3306 | |
c2f3b8e3 | 3307 | efx_device_detach_sync(efx); |
89c758fa | 3308 | |
6032fb56 | 3309 | efx_stop_all(efx); |
d8291187 | 3310 | efx_disable_interrupts(efx); |
6032fb56 | 3311 | } |
89c758fa | 3312 | |
61da026d BH |
3313 | rtnl_unlock(); |
3314 | ||
89c758fa BH |
3315 | return 0; |
3316 | } | |
3317 | ||
3318 | static int efx_pm_thaw(struct device *dev) | |
3319 | { | |
261e4d96 | 3320 | int rc; |
89c758fa BH |
3321 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); |
3322 | ||
61da026d BH |
3323 | rtnl_lock(); |
3324 | ||
6032fb56 | 3325 | if (efx->state != STATE_DISABLED) { |
261e4d96 JC |
3326 | rc = efx_enable_interrupts(efx); |
3327 | if (rc) | |
3328 | goto fail; | |
89c758fa | 3329 | |
6032fb56 BH |
3330 | mutex_lock(&efx->mac_lock); |
3331 | efx->phy_op->reconfigure(efx); | |
3332 | mutex_unlock(&efx->mac_lock); | |
89c758fa | 3333 | |
6032fb56 | 3334 | efx_start_all(efx); |
89c758fa | 3335 | |
6032fb56 | 3336 | netif_device_attach(efx->net_dev); |
89c758fa | 3337 | |
6032fb56 | 3338 | efx->state = STATE_READY; |
89c758fa | 3339 | |
6032fb56 BH |
3340 | efx->type->resume_wol(efx); |
3341 | } | |
89c758fa | 3342 | |
61da026d BH |
3343 | rtnl_unlock(); |
3344 | ||
319ba649 SH |
3345 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
3346 | queue_work(reset_workqueue, &efx->reset_work); | |
3347 | ||
89c758fa | 3348 | return 0; |
261e4d96 JC |
3349 | |
3350 | fail: | |
3351 | rtnl_unlock(); | |
3352 | ||
3353 | return rc; | |
89c758fa BH |
3354 | } |
3355 | ||
3356 | static int efx_pm_poweroff(struct device *dev) | |
3357 | { | |
3358 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
3359 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
3360 | ||
3361 | efx->type->fini(efx); | |
3362 | ||
a7d529ae | 3363 | efx->reset_pending = 0; |
89c758fa BH |
3364 | |
3365 | pci_save_state(pci_dev); | |
3366 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
3367 | } | |
3368 | ||
3369 | /* Used for both resume and restore */ | |
3370 | static int efx_pm_resume(struct device *dev) | |
3371 | { | |
3372 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
3373 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
3374 | int rc; | |
3375 | ||
3376 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
3377 | if (rc) | |
3378 | return rc; | |
3379 | pci_restore_state(pci_dev); | |
3380 | rc = pci_enable_device(pci_dev); | |
3381 | if (rc) | |
3382 | return rc; | |
3383 | pci_set_master(efx->pci_dev); | |
3384 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
3385 | if (rc) | |
3386 | return rc; | |
3387 | rc = efx->type->init(efx); | |
3388 | if (rc) | |
3389 | return rc; | |
261e4d96 JC |
3390 | rc = efx_pm_thaw(dev); |
3391 | return rc; | |
89c758fa BH |
3392 | } |
3393 | ||
3394 | static int efx_pm_suspend(struct device *dev) | |
3395 | { | |
3396 | int rc; | |
3397 | ||
3398 | efx_pm_freeze(dev); | |
3399 | rc = efx_pm_poweroff(dev); | |
3400 | if (rc) | |
3401 | efx_pm_resume(dev); | |
3402 | return rc; | |
3403 | } | |
3404 | ||
18e83e4c | 3405 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
3406 | .suspend = efx_pm_suspend, |
3407 | .resume = efx_pm_resume, | |
3408 | .freeze = efx_pm_freeze, | |
3409 | .thaw = efx_pm_thaw, | |
3410 | .poweroff = efx_pm_poweroff, | |
3411 | .restore = efx_pm_resume, | |
3412 | }; | |
3413 | ||
626950db AR |
3414 | /* A PCI error affecting this device was detected. |
3415 | * At this point MMIO and DMA may be disabled. | |
3416 | * Stop the software path and request a slot reset. | |
3417 | */ | |
debd0034 | 3418 | static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev, |
3419 | enum pci_channel_state state) | |
626950db AR |
3420 | { |
3421 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3422 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3423 | ||
3424 | if (state == pci_channel_io_perm_failure) | |
3425 | return PCI_ERS_RESULT_DISCONNECT; | |
3426 | ||
3427 | rtnl_lock(); | |
3428 | ||
3429 | if (efx->state != STATE_DISABLED) { | |
3430 | efx->state = STATE_RECOVERY; | |
3431 | efx->reset_pending = 0; | |
3432 | ||
3433 | efx_device_detach_sync(efx); | |
3434 | ||
3435 | efx_stop_all(efx); | |
d8291187 | 3436 | efx_disable_interrupts(efx); |
626950db AR |
3437 | |
3438 | status = PCI_ERS_RESULT_NEED_RESET; | |
3439 | } else { | |
3440 | /* If the interface is disabled we don't want to do anything | |
3441 | * with it. | |
3442 | */ | |
3443 | status = PCI_ERS_RESULT_RECOVERED; | |
3444 | } | |
3445 | ||
3446 | rtnl_unlock(); | |
3447 | ||
3448 | pci_disable_device(pdev); | |
3449 | ||
3450 | return status; | |
3451 | } | |
3452 | ||
dbedd44e | 3453 | /* Fake a successful reset, which will be performed later in efx_io_resume. */ |
debd0034 | 3454 | static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev) |
626950db AR |
3455 | { |
3456 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3457 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3458 | int rc; | |
3459 | ||
3460 | if (pci_enable_device(pdev)) { | |
3461 | netif_err(efx, hw, efx->net_dev, | |
3462 | "Cannot re-enable PCI device after reset.\n"); | |
3463 | status = PCI_ERS_RESULT_DISCONNECT; | |
3464 | } | |
3465 | ||
3466 | rc = pci_cleanup_aer_uncorrect_error_status(pdev); | |
3467 | if (rc) { | |
3468 | netif_err(efx, hw, efx->net_dev, | |
3469 | "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc); | |
3470 | /* Non-fatal error. Continue. */ | |
3471 | } | |
3472 | ||
3473 | return status; | |
3474 | } | |
3475 | ||
3476 | /* Perform the actual reset and resume I/O operations. */ | |
3477 | static void efx_io_resume(struct pci_dev *pdev) | |
3478 | { | |
3479 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3480 | int rc; | |
3481 | ||
3482 | rtnl_lock(); | |
3483 | ||
3484 | if (efx->state == STATE_DISABLED) | |
3485 | goto out; | |
3486 | ||
3487 | rc = efx_reset(efx, RESET_TYPE_ALL); | |
3488 | if (rc) { | |
3489 | netif_err(efx, hw, efx->net_dev, | |
3490 | "efx_reset failed after PCI error (%d)\n", rc); | |
3491 | } else { | |
3492 | efx->state = STATE_READY; | |
3493 | netif_dbg(efx, hw, efx->net_dev, | |
3494 | "Done resetting and resuming IO after PCI error.\n"); | |
3495 | } | |
3496 | ||
3497 | out: | |
3498 | rtnl_unlock(); | |
3499 | } | |
3500 | ||
3501 | /* For simplicity and reliability, we always require a slot reset and try to | |
3502 | * reset the hardware when a pci error affecting the device is detected. | |
3503 | * We leave both the link_reset and mmio_enabled callback unimplemented: | |
3504 | * with our request for slot reset the mmio_enabled callback will never be | |
3505 | * called, and the link_reset callback is not used by AER or EEH mechanisms. | |
3506 | */ | |
c300366b | 3507 | static const struct pci_error_handlers efx_err_handlers = { |
626950db AR |
3508 | .error_detected = efx_io_error_detected, |
3509 | .slot_reset = efx_io_slot_reset, | |
3510 | .resume = efx_io_resume, | |
3511 | }; | |
3512 | ||
8ceee660 | 3513 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 3514 | .name = KBUILD_MODNAME, |
8ceee660 BH |
3515 | .id_table = efx_pci_table, |
3516 | .probe = efx_pci_probe, | |
3517 | .remove = efx_pci_remove, | |
89c758fa | 3518 | .driver.pm = &efx_pm_ops, |
626950db | 3519 | .err_handler = &efx_err_handlers, |
834e23dd SS |
3520 | #ifdef CONFIG_SFC_SRIOV |
3521 | .sriov_configure = efx_pci_sriov_configure, | |
3522 | #endif | |
8ceee660 BH |
3523 | }; |
3524 | ||
3525 | /************************************************************************** | |
3526 | * | |
3527 | * Kernel module interface | |
3528 | * | |
3529 | *************************************************************************/ | |
3530 | ||
3531 | module_param(interrupt_mode, uint, 0444); | |
3532 | MODULE_PARM_DESC(interrupt_mode, | |
3533 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
3534 | ||
3535 | static int __init efx_init_module(void) | |
3536 | { | |
3537 | int rc; | |
3538 | ||
3539 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
3540 | ||
3541 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
3542 | if (rc) | |
3543 | goto err_notifier; | |
3544 | ||
7fa8d547 | 3545 | #ifdef CONFIG_SFC_SRIOV |
cd2d5b52 BH |
3546 | rc = efx_init_sriov(); |
3547 | if (rc) | |
3548 | goto err_sriov; | |
7fa8d547 | 3549 | #endif |
cd2d5b52 | 3550 | |
1ab00629 SH |
3551 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
3552 | if (!reset_workqueue) { | |
3553 | rc = -ENOMEM; | |
3554 | goto err_reset; | |
3555 | } | |
8ceee660 BH |
3556 | |
3557 | rc = pci_register_driver(&efx_pci_driver); | |
3558 | if (rc < 0) | |
3559 | goto err_pci; | |
3560 | ||
3561 | return 0; | |
3562 | ||
3563 | err_pci: | |
1ab00629 SH |
3564 | destroy_workqueue(reset_workqueue); |
3565 | err_reset: | |
7fa8d547 | 3566 | #ifdef CONFIG_SFC_SRIOV |
cd2d5b52 BH |
3567 | efx_fini_sriov(); |
3568 | err_sriov: | |
7fa8d547 | 3569 | #endif |
8ceee660 BH |
3570 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3571 | err_notifier: | |
3572 | return rc; | |
3573 | } | |
3574 | ||
3575 | static void __exit efx_exit_module(void) | |
3576 | { | |
3577 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
3578 | ||
3579 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 3580 | destroy_workqueue(reset_workqueue); |
7fa8d547 | 3581 | #ifdef CONFIG_SFC_SRIOV |
cd2d5b52 | 3582 | efx_fini_sriov(); |
7fa8d547 | 3583 | #endif |
8ceee660 BH |
3584 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3585 | ||
3586 | } | |
3587 | ||
3588 | module_init(efx_init_module); | |
3589 | module_exit(efx_exit_module); | |
3590 | ||
906bb26c BH |
3591 | MODULE_AUTHOR("Solarflare Communications and " |
3592 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
6a350fdb | 3593 | MODULE_DESCRIPTION("Solarflare network driver"); |
8ceee660 BH |
3594 | MODULE_LICENSE("GPL"); |
3595 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |