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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2005-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
8ceee660 | 20 | #include <linux/ethtool.h> |
aa6ef27e | 21 | #include <linux/topology.h> |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
626950db | 23 | #include <linux/aer.h> |
b28405b0 | 24 | #include <linux/interrupt.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
dd40781e | 28 | #include "selftest.h" |
8ceee660 | 29 | |
8880f4ec | 30 | #include "mcdi.h" |
fd371e32 | 31 | #include "workarounds.h" |
8880f4ec | 32 | |
c459302d BH |
33 | /************************************************************************** |
34 | * | |
35 | * Type name strings | |
36 | * | |
37 | ************************************************************************** | |
38 | */ | |
39 | ||
40 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
41 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 42 | const char *const efx_loopback_mode_names[] = { |
c459302d | 43 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 44 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
45 | [LOOPBACK_GMAC] = "GMAC", |
46 | [LOOPBACK_XGMII] = "XGMII", | |
47 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
48 | [LOOPBACK_XAUI] = "XAUI", |
49 | [LOOPBACK_GMII] = "GMII", | |
50 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
51 | [LOOPBACK_XGBR] = "XGBR", |
52 | [LOOPBACK_XFI] = "XFI", | |
53 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
54 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
55 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
56 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
57 | [LOOPBACK_GPHY] = "GPHY", |
58 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
59 | [LOOPBACK_PCS] = "PCS", |
60 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
61 | [LOOPBACK_XPORT] = "XPORT", |
62 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 63 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
64 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
65 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 66 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
67 | [LOOPBACK_XFI_WS] = "XFI_WS", |
68 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 69 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
70 | }; |
71 | ||
c459302d | 72 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 73 | const char *const efx_reset_type_names[] = { |
626950db AR |
74 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
75 | [RESET_TYPE_ALL] = "ALL", | |
76 | [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", | |
77 | [RESET_TYPE_WORLD] = "WORLD", | |
78 | [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", | |
e283546c | 79 | [RESET_TYPE_MC_BIST] = "MC_BIST", |
626950db AR |
80 | [RESET_TYPE_DISABLE] = "DISABLE", |
81 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
82 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
83 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
3de82b91 | 84 | [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", |
626950db AR |
85 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", |
86 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", | |
e283546c | 87 | [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)", |
c459302d BH |
88 | }; |
89 | ||
1ab00629 SH |
90 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
91 | * queued onto this work queue. This is not a per-nic work queue, because | |
92 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
93 | */ | |
94 | static struct workqueue_struct *reset_workqueue; | |
95 | ||
74cd60a4 JC |
96 | /* How often and how many times to poll for a reset while waiting for a |
97 | * BIST that another function started to complete. | |
98 | */ | |
99 | #define BIST_WAIT_DELAY_MS 100 | |
100 | #define BIST_WAIT_DELAY_COUNT 100 | |
101 | ||
8ceee660 BH |
102 | /************************************************************************** |
103 | * | |
104 | * Configurable values | |
105 | * | |
106 | *************************************************************************/ | |
107 | ||
8ceee660 BH |
108 | /* |
109 | * Use separate channels for TX and RX events | |
110 | * | |
28b581ab NT |
111 | * Set this to 1 to use separate channels for TX and RX. It allows us |
112 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 113 | * |
28b581ab | 114 | * This is only used in MSI-X interrupt mode |
8ceee660 | 115 | */ |
b9cc977d BH |
116 | static bool separate_tx_channels; |
117 | module_param(separate_tx_channels, bool, 0444); | |
28b581ab NT |
118 | MODULE_PARM_DESC(separate_tx_channels, |
119 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
120 | |
121 | /* This is the weight assigned to each of the (per-channel) virtual | |
122 | * NAPI devices. | |
123 | */ | |
124 | static int napi_weight = 64; | |
125 | ||
126 | /* This is the time (in jiffies) between invocations of the hardware | |
626950db AR |
127 | * monitor. |
128 | * On Falcon-based NICs, this will: | |
e254c274 BH |
129 | * - Check the on-board hardware monitor; |
130 | * - Poll the link state and reconfigure the hardware as necessary. | |
626950db AR |
131 | * On Siena-based NICs for power systems with EEH support, this will give EEH a |
132 | * chance to start. | |
8ceee660 | 133 | */ |
d215697f | 134 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 135 | |
8ceee660 BH |
136 | /* Initial interrupt moderation settings. They can be modified after |
137 | * module load with ethtool. | |
138 | * | |
139 | * The default for RX should strike a balance between increasing the | |
140 | * round-trip latency and reducing overhead. | |
141 | */ | |
142 | static unsigned int rx_irq_mod_usec = 60; | |
143 | ||
144 | /* Initial interrupt moderation settings. They can be modified after | |
145 | * module load with ethtool. | |
146 | * | |
147 | * This default is chosen to ensure that a 10G link does not go idle | |
148 | * while a TX queue is stopped after it has become full. A queue is | |
149 | * restarted when it drops below half full. The time this takes (assuming | |
150 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
151 | * 512 / 3 * 1.2 = 205 usec. | |
152 | */ | |
153 | static unsigned int tx_irq_mod_usec = 150; | |
154 | ||
155 | /* This is the first interrupt mode to try out of: | |
156 | * 0 => MSI-X | |
157 | * 1 => MSI | |
158 | * 2 => legacy | |
159 | */ | |
160 | static unsigned int interrupt_mode; | |
161 | ||
162 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
163 | * i.e. the number of CPUs among which we may distribute simultaneous | |
164 | * interrupt handling. | |
165 | * | |
166 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 167 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
168 | */ |
169 | static unsigned int rss_cpus; | |
170 | module_param(rss_cpus, uint, 0444); | |
171 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
172 | ||
b9cc977d BH |
173 | static bool phy_flash_cfg; |
174 | module_param(phy_flash_cfg, bool, 0644); | |
84ae48fe BH |
175 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); |
176 | ||
e7bed9c8 | 177 | static unsigned irq_adapt_low_thresh = 8000; |
6fb70fd1 BH |
178 | module_param(irq_adapt_low_thresh, uint, 0644); |
179 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
180 | "Threshold score for reducing IRQ moderation"); | |
181 | ||
e7bed9c8 | 182 | static unsigned irq_adapt_high_thresh = 16000; |
6fb70fd1 BH |
183 | module_param(irq_adapt_high_thresh, uint, 0644); |
184 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
185 | "Threshold score for increasing IRQ moderation"); | |
186 | ||
62776d03 BH |
187 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
188 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
189 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
190 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
191 | module_param(debug, uint, 0); | |
192 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
193 | ||
8ceee660 BH |
194 | /************************************************************************** |
195 | * | |
196 | * Utility functions and prototypes | |
197 | * | |
198 | *************************************************************************/ | |
4642610c | 199 | |
261e4d96 | 200 | static int efx_soft_enable_interrupts(struct efx_nic *efx); |
d8291187 | 201 | static void efx_soft_disable_interrupts(struct efx_nic *efx); |
7f967c01 | 202 | static void efx_remove_channel(struct efx_channel *channel); |
4642610c | 203 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 204 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 205 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 206 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 207 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 208 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
209 | static void efx_fini_struct(struct efx_nic *efx); |
210 | static void efx_start_all(struct efx_nic *efx); | |
211 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
212 | |
213 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
214 | do { \ | |
f16aeea0 | 215 | if ((efx->state == STATE_READY) || \ |
626950db | 216 | (efx->state == STATE_RECOVERY) || \ |
332c1ce9 | 217 | (efx->state == STATE_DISABLED)) \ |
8ceee660 BH |
218 | ASSERT_RTNL(); \ |
219 | } while (0) | |
220 | ||
8b7325b4 BH |
221 | static int efx_check_disabled(struct efx_nic *efx) |
222 | { | |
626950db | 223 | if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { |
8b7325b4 BH |
224 | netif_err(efx, drv, efx->net_dev, |
225 | "device is disabled due to earlier errors\n"); | |
226 | return -EIO; | |
227 | } | |
228 | return 0; | |
229 | } | |
230 | ||
8ceee660 BH |
231 | /************************************************************************** |
232 | * | |
233 | * Event queue processing | |
234 | * | |
235 | *************************************************************************/ | |
236 | ||
237 | /* Process channel's event queue | |
238 | * | |
239 | * This function is responsible for processing the event queue of a | |
240 | * single channel. The caller must guarantee that this function will | |
241 | * never be concurrently called more than once on the same channel, | |
242 | * though different channels may be being processed concurrently. | |
243 | */ | |
fa236e18 | 244 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 245 | { |
fa236e18 | 246 | int spent; |
8ceee660 | 247 | |
9f2cb71c | 248 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 249 | return 0; |
8ceee660 | 250 | |
fa236e18 | 251 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
252 | if (spent && efx_channel_has_rx_queue(channel)) { |
253 | struct efx_rx_queue *rx_queue = | |
254 | efx_channel_get_rx_queue(channel); | |
255 | ||
ff734ef4 | 256 | efx_rx_flush_packet(channel); |
cce28794 | 257 | efx_fast_push_rx_descriptors(rx_queue, true); |
8ceee660 BH |
258 | } |
259 | ||
fa236e18 | 260 | return spent; |
8ceee660 BH |
261 | } |
262 | ||
8ceee660 BH |
263 | /* NAPI poll handler |
264 | * | |
265 | * NAPI guarantees serialisation of polls of the same device, which | |
266 | * provides the guarantee required by efx_process_channel(). | |
267 | */ | |
268 | static int efx_poll(struct napi_struct *napi, int budget) | |
269 | { | |
270 | struct efx_channel *channel = | |
271 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 272 | struct efx_nic *efx = channel->efx; |
fa236e18 | 273 | int spent; |
8ceee660 | 274 | |
62776d03 BH |
275 | netif_vdbg(efx, intr, efx->net_dev, |
276 | "channel %d NAPI poll executing on CPU %d\n", | |
277 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 278 | |
fa236e18 | 279 | spent = efx_process_channel(channel, budget); |
8ceee660 | 280 | |
fa236e18 | 281 | if (spent < budget) { |
9d9a6973 | 282 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
283 | efx->irq_rx_adaptive && |
284 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
285 | if (unlikely(channel->irq_mod_score < |
286 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
287 | if (channel->irq_moderation > 1) { |
288 | channel->irq_moderation -= 1; | |
ef2b90ee | 289 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 290 | } |
6fb70fd1 BH |
291 | } else if (unlikely(channel->irq_mod_score > |
292 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
293 | if (channel->irq_moderation < |
294 | efx->irq_rx_moderation) { | |
295 | channel->irq_moderation += 1; | |
ef2b90ee | 296 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 297 | } |
6fb70fd1 | 298 | } |
6fb70fd1 BH |
299 | channel->irq_count = 0; |
300 | channel->irq_mod_score = 0; | |
301 | } | |
302 | ||
64d8ad6d BH |
303 | efx_filter_rfs_expire(channel); |
304 | ||
8ceee660 | 305 | /* There is no race here; although napi_disable() will |
288379f0 | 306 | * only wait for napi_complete(), this isn't a problem |
514bedbc | 307 | * since efx_nic_eventq_read_ack() will have no effect if |
8ceee660 BH |
308 | * interrupts have already been disabled. |
309 | */ | |
288379f0 | 310 | napi_complete(napi); |
514bedbc | 311 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
312 | } |
313 | ||
fa236e18 | 314 | return spent; |
8ceee660 BH |
315 | } |
316 | ||
8ceee660 BH |
317 | /* Create event queue |
318 | * Event queue memory allocations are done only once. If the channel | |
319 | * is reset, the memory buffer will be reused; this guards against | |
320 | * errors during channel reset and also simplifies interrupt handling. | |
321 | */ | |
322 | static int efx_probe_eventq(struct efx_channel *channel) | |
323 | { | |
ecc910f5 SH |
324 | struct efx_nic *efx = channel->efx; |
325 | unsigned long entries; | |
326 | ||
86ee5302 | 327 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 328 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 329 | |
ecc910f5 SH |
330 | /* Build an event queue with room for one event per tx and rx buffer, |
331 | * plus some extra for link state events and MCDI completions. */ | |
332 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
333 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
334 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
335 | ||
152b6a62 | 336 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
337 | } |
338 | ||
339 | /* Prepare channel's event queue */ | |
261e4d96 | 340 | static int efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 341 | { |
15acb1ce | 342 | struct efx_nic *efx = channel->efx; |
261e4d96 JC |
343 | int rc; |
344 | ||
345 | EFX_WARN_ON_PARANOID(channel->eventq_init); | |
346 | ||
15acb1ce | 347 | netif_dbg(efx, drv, efx->net_dev, |
62776d03 | 348 | "chan %d init event queue\n", channel->channel); |
8ceee660 | 349 | |
261e4d96 JC |
350 | rc = efx_nic_init_eventq(channel); |
351 | if (rc == 0) { | |
15acb1ce | 352 | efx->type->push_irq_moderation(channel); |
261e4d96 JC |
353 | channel->eventq_read_ptr = 0; |
354 | channel->eventq_init = true; | |
355 | } | |
356 | return rc; | |
8ceee660 BH |
357 | } |
358 | ||
9f2cb71c BH |
359 | /* Enable event queue processing and NAPI */ |
360 | static void efx_start_eventq(struct efx_channel *channel) | |
361 | { | |
362 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
363 | "chan %d start event queue\n", channel->channel); | |
364 | ||
514bedbc | 365 | /* Make sure the NAPI handler sees the enabled flag set */ |
9f2cb71c BH |
366 | channel->enabled = true; |
367 | smp_wmb(); | |
368 | ||
369 | napi_enable(&channel->napi_str); | |
370 | efx_nic_eventq_read_ack(channel); | |
371 | } | |
372 | ||
373 | /* Disable event queue processing and NAPI */ | |
374 | static void efx_stop_eventq(struct efx_channel *channel) | |
375 | { | |
376 | if (!channel->enabled) | |
377 | return; | |
378 | ||
379 | napi_disable(&channel->napi_str); | |
380 | channel->enabled = false; | |
381 | } | |
382 | ||
8ceee660 BH |
383 | static void efx_fini_eventq(struct efx_channel *channel) |
384 | { | |
be3fc09c BH |
385 | if (!channel->eventq_init) |
386 | return; | |
387 | ||
62776d03 BH |
388 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
389 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 390 | |
152b6a62 | 391 | efx_nic_fini_eventq(channel); |
be3fc09c | 392 | channel->eventq_init = false; |
8ceee660 BH |
393 | } |
394 | ||
395 | static void efx_remove_eventq(struct efx_channel *channel) | |
396 | { | |
62776d03 BH |
397 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
398 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 399 | |
152b6a62 | 400 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
401 | } |
402 | ||
403 | /************************************************************************** | |
404 | * | |
405 | * Channel handling | |
406 | * | |
407 | *************************************************************************/ | |
408 | ||
7f967c01 | 409 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
410 | static struct efx_channel * |
411 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
412 | { | |
413 | struct efx_channel *channel; | |
414 | struct efx_rx_queue *rx_queue; | |
415 | struct efx_tx_queue *tx_queue; | |
416 | int j; | |
417 | ||
7f967c01 BH |
418 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
419 | if (!channel) | |
420 | return NULL; | |
4642610c | 421 | |
7f967c01 BH |
422 | channel->efx = efx; |
423 | channel->channel = i; | |
424 | channel->type = &efx_default_channel_type; | |
4642610c | 425 | |
7f967c01 BH |
426 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
427 | tx_queue = &channel->tx_queue[j]; | |
428 | tx_queue->efx = efx; | |
429 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
430 | tx_queue->channel = channel; | |
431 | } | |
4642610c | 432 | |
7f967c01 BH |
433 | rx_queue = &channel->rx_queue; |
434 | rx_queue->efx = efx; | |
435 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
436 | (unsigned long)rx_queue); | |
4642610c | 437 | |
7f967c01 BH |
438 | return channel; |
439 | } | |
440 | ||
441 | /* Allocate and initialise a channel structure, copying parameters | |
442 | * (but not resources) from an old channel structure. | |
443 | */ | |
444 | static struct efx_channel * | |
445 | efx_copy_channel(const struct efx_channel *old_channel) | |
446 | { | |
447 | struct efx_channel *channel; | |
448 | struct efx_rx_queue *rx_queue; | |
449 | struct efx_tx_queue *tx_queue; | |
450 | int j; | |
4642610c | 451 | |
7f967c01 BH |
452 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
453 | if (!channel) | |
454 | return NULL; | |
455 | ||
456 | *channel = *old_channel; | |
457 | ||
458 | channel->napi_dev = NULL; | |
459 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 460 | |
7f967c01 BH |
461 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
462 | tx_queue = &channel->tx_queue[j]; | |
463 | if (tx_queue->channel) | |
4642610c | 464 | tx_queue->channel = channel; |
7f967c01 BH |
465 | tx_queue->buffer = NULL; |
466 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
467 | } |
468 | ||
4642610c | 469 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
470 | rx_queue->buffer = NULL; |
471 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
472 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
473 | (unsigned long)rx_queue); | |
474 | ||
475 | return channel; | |
476 | } | |
477 | ||
8ceee660 BH |
478 | static int efx_probe_channel(struct efx_channel *channel) |
479 | { | |
480 | struct efx_tx_queue *tx_queue; | |
481 | struct efx_rx_queue *rx_queue; | |
482 | int rc; | |
483 | ||
62776d03 BH |
484 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
485 | "creating channel %d\n", channel->channel); | |
8ceee660 | 486 | |
7f967c01 BH |
487 | rc = channel->type->pre_probe(channel); |
488 | if (rc) | |
489 | goto fail; | |
490 | ||
8ceee660 BH |
491 | rc = efx_probe_eventq(channel); |
492 | if (rc) | |
7f967c01 | 493 | goto fail; |
8ceee660 BH |
494 | |
495 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
496 | rc = efx_probe_tx_queue(tx_queue); | |
497 | if (rc) | |
7f967c01 | 498 | goto fail; |
8ceee660 BH |
499 | } |
500 | ||
501 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
502 | rc = efx_probe_rx_queue(rx_queue); | |
503 | if (rc) | |
7f967c01 | 504 | goto fail; |
8ceee660 BH |
505 | } |
506 | ||
8ceee660 BH |
507 | return 0; |
508 | ||
7f967c01 BH |
509 | fail: |
510 | efx_remove_channel(channel); | |
8ceee660 BH |
511 | return rc; |
512 | } | |
513 | ||
7f967c01 BH |
514 | static void |
515 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
516 | { | |
517 | struct efx_nic *efx = channel->efx; | |
518 | const char *type; | |
519 | int number; | |
520 | ||
521 | number = channel->channel; | |
522 | if (efx->tx_channel_offset == 0) { | |
523 | type = ""; | |
524 | } else if (channel->channel < efx->tx_channel_offset) { | |
525 | type = "-rx"; | |
526 | } else { | |
527 | type = "-tx"; | |
528 | number -= efx->tx_channel_offset; | |
529 | } | |
530 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
531 | } | |
8ceee660 | 532 | |
56536e9c BH |
533 | static void efx_set_channel_names(struct efx_nic *efx) |
534 | { | |
535 | struct efx_channel *channel; | |
56536e9c | 536 | |
7f967c01 BH |
537 | efx_for_each_channel(channel, efx) |
538 | channel->type->get_name(channel, | |
d8291187 BH |
539 | efx->msi_context[channel->channel].name, |
540 | sizeof(efx->msi_context[0].name)); | |
56536e9c BH |
541 | } |
542 | ||
4642610c BH |
543 | static int efx_probe_channels(struct efx_nic *efx) |
544 | { | |
545 | struct efx_channel *channel; | |
546 | int rc; | |
547 | ||
548 | /* Restart special buffer allocation */ | |
549 | efx->next_buffer_table = 0; | |
550 | ||
c92aaff1 BH |
551 | /* Probe channels in reverse, so that any 'extra' channels |
552 | * use the start of the buffer table. This allows the traffic | |
553 | * channels to be resized without moving them or wasting the | |
554 | * entries before them. | |
555 | */ | |
556 | efx_for_each_channel_rev(channel, efx) { | |
4642610c BH |
557 | rc = efx_probe_channel(channel); |
558 | if (rc) { | |
559 | netif_err(efx, probe, efx->net_dev, | |
560 | "failed to create channel %d\n", | |
561 | channel->channel); | |
562 | goto fail; | |
563 | } | |
564 | } | |
565 | efx_set_channel_names(efx); | |
566 | ||
567 | return 0; | |
568 | ||
569 | fail: | |
570 | efx_remove_channels(efx); | |
571 | return rc; | |
572 | } | |
573 | ||
8ceee660 BH |
574 | /* Channels are shutdown and reinitialised whilst the NIC is running |
575 | * to propagate configuration changes (mtu, checksum offload), or | |
576 | * to clear hardware error conditions | |
577 | */ | |
9f2cb71c | 578 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 | 579 | { |
85740cdf | 580 | bool old_rx_scatter = efx->rx_scatter; |
8ceee660 BH |
581 | struct efx_tx_queue *tx_queue; |
582 | struct efx_rx_queue *rx_queue; | |
583 | struct efx_channel *channel; | |
85740cdf | 584 | size_t rx_buf_len; |
8ceee660 | 585 | |
f7f13b0b BH |
586 | /* Calculate the rx buffer allocation parameters required to |
587 | * support the current MTU, including padding for header | |
588 | * alignment and overruns. | |
589 | */ | |
43a3739d | 590 | efx->rx_dma_len = (efx->rx_prefix_size + |
272baeeb BH |
591 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + |
592 | efx->type->rx_buffer_padding); | |
85740cdf | 593 | rx_buf_len = (sizeof(struct efx_rx_page_state) + |
2ec03014 | 594 | efx->rx_ip_align + efx->rx_dma_len); |
85740cdf | 595 | if (rx_buf_len <= PAGE_SIZE) { |
e8c68c0a | 596 | efx->rx_scatter = efx->type->always_rx_scatter; |
85740cdf | 597 | efx->rx_buffer_order = 0; |
85740cdf | 598 | } else if (efx->type->can_rx_scatter) { |
950c54df | 599 | BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES); |
85740cdf | 600 | BUILD_BUG_ON(sizeof(struct efx_rx_page_state) + |
950c54df BH |
601 | 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE, |
602 | EFX_RX_BUF_ALIGNMENT) > | |
603 | PAGE_SIZE); | |
85740cdf BH |
604 | efx->rx_scatter = true; |
605 | efx->rx_dma_len = EFX_RX_USR_BUF_SIZE; | |
606 | efx->rx_buffer_order = 0; | |
85740cdf BH |
607 | } else { |
608 | efx->rx_scatter = false; | |
609 | efx->rx_buffer_order = get_order(rx_buf_len); | |
85740cdf BH |
610 | } |
611 | ||
1648a23f DP |
612 | efx_rx_config_page_split(efx); |
613 | if (efx->rx_buffer_order) | |
614 | netif_dbg(efx, drv, efx->net_dev, | |
615 | "RX buf len=%u; page order=%u batch=%u\n", | |
616 | efx->rx_dma_len, efx->rx_buffer_order, | |
617 | efx->rx_pages_per_batch); | |
618 | else | |
619 | netif_dbg(efx, drv, efx->net_dev, | |
620 | "RX buf len=%u step=%u bpp=%u; page batch=%u\n", | |
621 | efx->rx_dma_len, efx->rx_page_buf_step, | |
622 | efx->rx_bufs_per_page, efx->rx_pages_per_batch); | |
2768935a | 623 | |
e8c68c0a | 624 | /* RX filters may also have scatter-enabled flags */ |
85740cdf | 625 | if (efx->rx_scatter != old_rx_scatter) |
add72477 | 626 | efx->type->filter_update_rx_scatter(efx); |
8ceee660 | 627 | |
14bf718f BH |
628 | /* We must keep at least one descriptor in a TX ring empty. |
629 | * We could avoid this when the queue size does not exactly | |
630 | * match the hardware ring size, but it's not that important. | |
631 | * Therefore we stop the queue when one more skb might fill | |
632 | * the ring completely. We wake it when half way back to | |
633 | * empty. | |
634 | */ | |
635 | efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); | |
636 | efx->txq_wake_thresh = efx->txq_stop_thresh / 2; | |
637 | ||
8ceee660 BH |
638 | /* Initialise the channels */ |
639 | efx_for_each_channel(channel, efx) { | |
3881d8ab | 640 | efx_for_each_channel_tx_queue(tx_queue, channel) { |
bc3c90a2 | 641 | efx_init_tx_queue(tx_queue); |
3881d8ab AR |
642 | atomic_inc(&efx->active_queues); |
643 | } | |
8ceee660 | 644 | |
9f2cb71c | 645 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 646 | efx_init_rx_queue(rx_queue); |
3881d8ab | 647 | atomic_inc(&efx->active_queues); |
cce28794 JC |
648 | efx_stop_eventq(channel); |
649 | efx_fast_push_rx_descriptors(rx_queue, false); | |
650 | efx_start_eventq(channel); | |
9f2cb71c | 651 | } |
8ceee660 | 652 | |
85740cdf | 653 | WARN_ON(channel->rx_pkt_n_frags); |
8ceee660 | 654 | } |
8ceee660 | 655 | |
2ea4dc28 AR |
656 | efx_ptp_start_datapath(efx); |
657 | ||
9f2cb71c BH |
658 | if (netif_device_present(efx->net_dev)) |
659 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
660 | } |
661 | ||
9f2cb71c | 662 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
663 | { |
664 | struct efx_channel *channel; | |
665 | struct efx_tx_queue *tx_queue; | |
666 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 667 | int rc; |
8ceee660 BH |
668 | |
669 | EFX_ASSERT_RESET_SERIALISED(efx); | |
670 | BUG_ON(efx->port_enabled); | |
671 | ||
2ea4dc28 AR |
672 | efx_ptp_stop_datapath(efx); |
673 | ||
d8aec745 BH |
674 | /* Stop RX refill */ |
675 | efx_for_each_channel(channel, efx) { | |
676 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
677 | rx_queue->refill_enabled = false; | |
678 | } | |
679 | ||
8ceee660 | 680 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
681 | /* RX packet processing is pipelined, so wait for the |
682 | * NAPI handler to complete. At least event queue 0 | |
683 | * might be kept active by non-data events, so don't | |
684 | * use napi_synchronize() but actually disable NAPI | |
685 | * temporarily. | |
686 | */ | |
687 | if (efx_channel_has_rx_queue(channel)) { | |
688 | efx_stop_eventq(channel); | |
689 | efx_start_eventq(channel); | |
690 | } | |
e42c3d85 | 691 | } |
8ceee660 | 692 | |
e42c3d85 BH |
693 | rc = efx->type->fini_dmaq(efx); |
694 | if (rc && EFX_WORKAROUND_7803(efx)) { | |
695 | /* Schedule a reset to recover from the flush failure. The | |
696 | * descriptor caches reference memory we're about to free, | |
697 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
698 | * the MACs because of the pending reset. | |
699 | */ | |
700 | netif_err(efx, drv, efx->net_dev, | |
701 | "Resetting to recover from flush failure\n"); | |
702 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
703 | } else if (rc) { | |
704 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); | |
705 | } else { | |
706 | netif_dbg(efx, drv, efx->net_dev, | |
707 | "successfully flushed all queues\n"); | |
708 | } | |
709 | ||
710 | efx_for_each_channel(channel, efx) { | |
8ceee660 BH |
711 | efx_for_each_channel_rx_queue(rx_queue, channel) |
712 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 713 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 714 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
715 | } |
716 | } | |
717 | ||
718 | static void efx_remove_channel(struct efx_channel *channel) | |
719 | { | |
720 | struct efx_tx_queue *tx_queue; | |
721 | struct efx_rx_queue *rx_queue; | |
722 | ||
62776d03 BH |
723 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
724 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
725 | |
726 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
727 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 728 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
729 | efx_remove_tx_queue(tx_queue); |
730 | efx_remove_eventq(channel); | |
c31e5f9f | 731 | channel->type->post_remove(channel); |
8ceee660 BH |
732 | } |
733 | ||
4642610c BH |
734 | static void efx_remove_channels(struct efx_nic *efx) |
735 | { | |
736 | struct efx_channel *channel; | |
737 | ||
738 | efx_for_each_channel(channel, efx) | |
739 | efx_remove_channel(channel); | |
740 | } | |
741 | ||
742 | int | |
743 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
744 | { | |
745 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
746 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 | 747 | unsigned i, next_buffer_table = 0; |
261e4d96 | 748 | int rc, rc2; |
8b7325b4 BH |
749 | |
750 | rc = efx_check_disabled(efx); | |
751 | if (rc) | |
752 | return rc; | |
7f967c01 BH |
753 | |
754 | /* Not all channels should be reallocated. We must avoid | |
755 | * reallocating their buffer table entries. | |
756 | */ | |
757 | efx_for_each_channel(channel, efx) { | |
758 | struct efx_rx_queue *rx_queue; | |
759 | struct efx_tx_queue *tx_queue; | |
760 | ||
761 | if (channel->type->copy) | |
762 | continue; | |
763 | next_buffer_table = max(next_buffer_table, | |
764 | channel->eventq.index + | |
765 | channel->eventq.entries); | |
766 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
767 | next_buffer_table = max(next_buffer_table, | |
768 | rx_queue->rxd.index + | |
769 | rx_queue->rxd.entries); | |
770 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
771 | next_buffer_table = max(next_buffer_table, | |
772 | tx_queue->txd.index + | |
773 | tx_queue->txd.entries); | |
774 | } | |
4642610c | 775 | |
29c69a48 | 776 | efx_device_detach_sync(efx); |
4642610c | 777 | efx_stop_all(efx); |
d8291187 | 778 | efx_soft_disable_interrupts(efx); |
4642610c | 779 | |
7f967c01 | 780 | /* Clone channels (where possible) */ |
4642610c BH |
781 | memset(other_channel, 0, sizeof(other_channel)); |
782 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
783 | channel = efx->channel[i]; |
784 | if (channel->type->copy) | |
785 | channel = channel->type->copy(channel); | |
4642610c BH |
786 | if (!channel) { |
787 | rc = -ENOMEM; | |
788 | goto out; | |
789 | } | |
790 | other_channel[i] = channel; | |
791 | } | |
792 | ||
793 | /* Swap entry counts and channel pointers */ | |
794 | old_rxq_entries = efx->rxq_entries; | |
795 | old_txq_entries = efx->txq_entries; | |
796 | efx->rxq_entries = rxq_entries; | |
797 | efx->txq_entries = txq_entries; | |
798 | for (i = 0; i < efx->n_channels; i++) { | |
799 | channel = efx->channel[i]; | |
800 | efx->channel[i] = other_channel[i]; | |
801 | other_channel[i] = channel; | |
802 | } | |
803 | ||
7f967c01 BH |
804 | /* Restart buffer table allocation */ |
805 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 806 | |
e8f14992 | 807 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
808 | channel = efx->channel[i]; |
809 | if (!channel->type->copy) | |
810 | continue; | |
811 | rc = efx_probe_channel(channel); | |
812 | if (rc) | |
813 | goto rollback; | |
814 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 815 | } |
7f967c01 | 816 | |
4642610c | 817 | out: |
7f967c01 BH |
818 | /* Destroy unused channel structures */ |
819 | for (i = 0; i < efx->n_channels; i++) { | |
820 | channel = other_channel[i]; | |
821 | if (channel && channel->type->copy) { | |
822 | efx_fini_napi_channel(channel); | |
823 | efx_remove_channel(channel); | |
824 | kfree(channel); | |
825 | } | |
826 | } | |
4642610c | 827 | |
261e4d96 JC |
828 | rc2 = efx_soft_enable_interrupts(efx); |
829 | if (rc2) { | |
830 | rc = rc ? rc : rc2; | |
831 | netif_err(efx, drv, efx->net_dev, | |
832 | "unable to restart interrupts on channel reallocation\n"); | |
833 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
834 | } else { | |
835 | efx_start_all(efx); | |
836 | netif_device_attach(efx->net_dev); | |
837 | } | |
4642610c BH |
838 | return rc; |
839 | ||
840 | rollback: | |
841 | /* Swap back */ | |
842 | efx->rxq_entries = old_rxq_entries; | |
843 | efx->txq_entries = old_txq_entries; | |
844 | for (i = 0; i < efx->n_channels; i++) { | |
845 | channel = efx->channel[i]; | |
846 | efx->channel[i] = other_channel[i]; | |
847 | other_channel[i] = channel; | |
848 | } | |
849 | goto out; | |
850 | } | |
851 | ||
90d683af | 852 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 853 | { |
90d683af | 854 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
855 | } |
856 | ||
7f967c01 BH |
857 | static const struct efx_channel_type efx_default_channel_type = { |
858 | .pre_probe = efx_channel_dummy_op_int, | |
c31e5f9f | 859 | .post_remove = efx_channel_dummy_op_void, |
7f967c01 BH |
860 | .get_name = efx_get_channel_name, |
861 | .copy = efx_copy_channel, | |
862 | .keep_eventq = false, | |
863 | }; | |
864 | ||
865 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
866 | { | |
867 | return 0; | |
868 | } | |
869 | ||
c31e5f9f SH |
870 | void efx_channel_dummy_op_void(struct efx_channel *channel) |
871 | { | |
872 | } | |
873 | ||
8ceee660 BH |
874 | /************************************************************************** |
875 | * | |
876 | * Port handling | |
877 | * | |
878 | **************************************************************************/ | |
879 | ||
880 | /* This ensures that the kernel is kept informed (via | |
881 | * netif_carrier_on/off) of the link status, and also maintains the | |
882 | * link status's stop on the port's TX queue. | |
883 | */ | |
fdaa9aed | 884 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 885 | { |
eb50c0d6 BH |
886 | struct efx_link_state *link_state = &efx->link_state; |
887 | ||
8ceee660 BH |
888 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
889 | * that no events are triggered between unregister_netdev() and the | |
890 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
891 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
892 | if (!netif_running(efx->net_dev)) | |
893 | return; | |
894 | ||
eb50c0d6 | 895 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
896 | efx->n_link_state_changes++; |
897 | ||
eb50c0d6 | 898 | if (link_state->up) |
8ceee660 BH |
899 | netif_carrier_on(efx->net_dev); |
900 | else | |
901 | netif_carrier_off(efx->net_dev); | |
902 | } | |
903 | ||
904 | /* Status message for kernel log */ | |
2aa9ef11 | 905 | if (link_state->up) |
62776d03 | 906 | netif_info(efx, link, efx->net_dev, |
964e6135 | 907 | "link up at %uMbps %s-duplex (MTU %d)\n", |
62776d03 | 908 | link_state->speed, link_state->fd ? "full" : "half", |
964e6135 | 909 | efx->net_dev->mtu); |
2aa9ef11 | 910 | else |
62776d03 | 911 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
912 | } |
913 | ||
d3245b28 BH |
914 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
915 | { | |
916 | efx->link_advertising = advertising; | |
917 | if (advertising) { | |
918 | if (advertising & ADVERTISED_Pause) | |
919 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
920 | else | |
921 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
922 | if (advertising & ADVERTISED_Asym_Pause) | |
923 | efx->wanted_fc ^= EFX_FC_TX; | |
924 | } | |
925 | } | |
926 | ||
b5626946 | 927 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
928 | { |
929 | efx->wanted_fc = wanted_fc; | |
930 | if (efx->link_advertising) { | |
931 | if (wanted_fc & EFX_FC_RX) | |
932 | efx->link_advertising |= (ADVERTISED_Pause | | |
933 | ADVERTISED_Asym_Pause); | |
934 | else | |
935 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
936 | ADVERTISED_Asym_Pause); | |
937 | if (wanted_fc & EFX_FC_TX) | |
938 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
939 | } | |
940 | } | |
941 | ||
115122af BH |
942 | static void efx_fini_port(struct efx_nic *efx); |
943 | ||
d3245b28 BH |
944 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
945 | * the MAC appropriately. All other PHY configuration changes are pushed | |
946 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
947 | * through efx_monitor(). | |
948 | * | |
949 | * Callers must hold the mac_lock | |
950 | */ | |
951 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 952 | { |
d3245b28 BH |
953 | enum efx_phy_mode phy_mode; |
954 | int rc; | |
8ceee660 | 955 | |
d3245b28 | 956 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 957 | |
d3245b28 BH |
958 | /* Disable PHY transmit in mac level loopbacks */ |
959 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
960 | if (LOOPBACK_INTERNAL(efx)) |
961 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
962 | else | |
963 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 964 | |
d3245b28 | 965 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 966 | |
d3245b28 BH |
967 | if (rc) |
968 | efx->phy_mode = phy_mode; | |
177dfcd8 | 969 | |
d3245b28 | 970 | return rc; |
8ceee660 BH |
971 | } |
972 | ||
973 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
974 | * disabled. */ | |
d3245b28 | 975 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 976 | { |
d3245b28 BH |
977 | int rc; |
978 | ||
8ceee660 BH |
979 | EFX_ASSERT_RESET_SERIALISED(efx); |
980 | ||
981 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 982 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 983 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
984 | |
985 | return rc; | |
8ceee660 BH |
986 | } |
987 | ||
8be4f3e6 BH |
988 | /* Asynchronous work item for changing MAC promiscuity and multicast |
989 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
990 | * MAC directly. */ | |
766ca0fa BH |
991 | static void efx_mac_work(struct work_struct *data) |
992 | { | |
993 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
994 | ||
995 | mutex_lock(&efx->mac_lock); | |
30b81cda | 996 | if (efx->port_enabled) |
710b208d | 997 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
998 | mutex_unlock(&efx->mac_lock); |
999 | } | |
1000 | ||
8ceee660 BH |
1001 | static int efx_probe_port(struct efx_nic *efx) |
1002 | { | |
1003 | int rc; | |
1004 | ||
62776d03 | 1005 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 1006 | |
ff3b00a0 SH |
1007 | if (phy_flash_cfg) |
1008 | efx->phy_mode = PHY_MODE_SPECIAL; | |
1009 | ||
ef2b90ee BH |
1010 | /* Connect up MAC/PHY operations table */ |
1011 | rc = efx->type->probe_port(efx); | |
8ceee660 | 1012 | if (rc) |
e42de262 | 1013 | return rc; |
8ceee660 | 1014 | |
e332bcb3 | 1015 | /* Initialise MAC address to permanent address */ |
cd84ff4d | 1016 | ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr); |
8ceee660 BH |
1017 | |
1018 | return 0; | |
8ceee660 BH |
1019 | } |
1020 | ||
1021 | static int efx_init_port(struct efx_nic *efx) | |
1022 | { | |
1023 | int rc; | |
1024 | ||
62776d03 | 1025 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 1026 | |
1dfc5cea BH |
1027 | mutex_lock(&efx->mac_lock); |
1028 | ||
177dfcd8 | 1029 | rc = efx->phy_op->init(efx); |
8ceee660 | 1030 | if (rc) |
1dfc5cea | 1031 | goto fail1; |
8ceee660 | 1032 | |
dc8cfa55 | 1033 | efx->port_initialized = true; |
1dfc5cea | 1034 | |
d3245b28 BH |
1035 | /* Reconfigure the MAC before creating dma queues (required for |
1036 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 1037 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1038 | |
1039 | /* Ensure the PHY advertises the correct flow control settings */ | |
1040 | rc = efx->phy_op->reconfigure(efx); | |
1041 | if (rc) | |
1042 | goto fail2; | |
1043 | ||
1dfc5cea | 1044 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1045 | return 0; |
177dfcd8 | 1046 | |
1dfc5cea | 1047 | fail2: |
177dfcd8 | 1048 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1049 | fail1: |
1050 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1051 | return rc; |
8ceee660 BH |
1052 | } |
1053 | ||
8ceee660 BH |
1054 | static void efx_start_port(struct efx_nic *efx) |
1055 | { | |
62776d03 | 1056 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1057 | BUG_ON(efx->port_enabled); |
1058 | ||
1059 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1060 | efx->port_enabled = true; |
8be4f3e6 | 1061 | |
d615c039 | 1062 | /* Ensure MAC ingress/egress is enabled */ |
710b208d | 1063 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 1064 | |
8ceee660 BH |
1065 | mutex_unlock(&efx->mac_lock); |
1066 | } | |
1067 | ||
d615c039 BH |
1068 | /* Cancel work for MAC reconfiguration, periodic hardware monitoring |
1069 | * and the async self-test, wait for them to finish and prevent them | |
1070 | * being scheduled again. This doesn't cover online resets, which | |
1071 | * should only be cancelled when removing the device. | |
1072 | */ | |
8ceee660 BH |
1073 | static void efx_stop_port(struct efx_nic *efx) |
1074 | { | |
62776d03 | 1075 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 | 1076 | |
d615c039 BH |
1077 | EFX_ASSERT_RESET_SERIALISED(efx); |
1078 | ||
8ceee660 | 1079 | mutex_lock(&efx->mac_lock); |
dc8cfa55 | 1080 | efx->port_enabled = false; |
8ceee660 BH |
1081 | mutex_unlock(&efx->mac_lock); |
1082 | ||
1083 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1084 | netif_addr_lock_bh(efx->net_dev); |
1085 | netif_addr_unlock_bh(efx->net_dev); | |
d615c039 BH |
1086 | |
1087 | cancel_delayed_work_sync(&efx->monitor_work); | |
1088 | efx_selftest_async_cancel(efx); | |
1089 | cancel_work_sync(&efx->mac_work); | |
8ceee660 BH |
1090 | } |
1091 | ||
1092 | static void efx_fini_port(struct efx_nic *efx) | |
1093 | { | |
62776d03 | 1094 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1095 | |
1096 | if (!efx->port_initialized) | |
1097 | return; | |
1098 | ||
177dfcd8 | 1099 | efx->phy_op->fini(efx); |
dc8cfa55 | 1100 | efx->port_initialized = false; |
8ceee660 | 1101 | |
eb50c0d6 | 1102 | efx->link_state.up = false; |
8ceee660 BH |
1103 | efx_link_status_changed(efx); |
1104 | } | |
1105 | ||
1106 | static void efx_remove_port(struct efx_nic *efx) | |
1107 | { | |
62776d03 | 1108 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1109 | |
ef2b90ee | 1110 | efx->type->remove_port(efx); |
8ceee660 BH |
1111 | } |
1112 | ||
1113 | /************************************************************************** | |
1114 | * | |
1115 | * NIC handling | |
1116 | * | |
1117 | **************************************************************************/ | |
1118 | ||
0bcf4a64 BH |
1119 | static LIST_HEAD(efx_primary_list); |
1120 | static LIST_HEAD(efx_unassociated_list); | |
1121 | ||
1122 | static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right) | |
1123 | { | |
1124 | return left->type == right->type && | |
1125 | left->vpd_sn && right->vpd_sn && | |
1126 | !strcmp(left->vpd_sn, right->vpd_sn); | |
1127 | } | |
1128 | ||
1129 | static void efx_associate(struct efx_nic *efx) | |
1130 | { | |
1131 | struct efx_nic *other, *next; | |
1132 | ||
1133 | if (efx->primary == efx) { | |
1134 | /* Adding primary function; look for secondaries */ | |
1135 | ||
1136 | netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n"); | |
1137 | list_add_tail(&efx->node, &efx_primary_list); | |
1138 | ||
1139 | list_for_each_entry_safe(other, next, &efx_unassociated_list, | |
1140 | node) { | |
1141 | if (efx_same_controller(efx, other)) { | |
1142 | list_del(&other->node); | |
1143 | netif_dbg(other, probe, other->net_dev, | |
1144 | "moving to secondary list of %s %s\n", | |
1145 | pci_name(efx->pci_dev), | |
1146 | efx->net_dev->name); | |
1147 | list_add_tail(&other->node, | |
1148 | &efx->secondary_list); | |
1149 | other->primary = efx; | |
1150 | } | |
1151 | } | |
1152 | } else { | |
1153 | /* Adding secondary function; look for primary */ | |
1154 | ||
1155 | list_for_each_entry(other, &efx_primary_list, node) { | |
1156 | if (efx_same_controller(efx, other)) { | |
1157 | netif_dbg(efx, probe, efx->net_dev, | |
1158 | "adding to secondary list of %s %s\n", | |
1159 | pci_name(other->pci_dev), | |
1160 | other->net_dev->name); | |
1161 | list_add_tail(&efx->node, | |
1162 | &other->secondary_list); | |
1163 | efx->primary = other; | |
1164 | return; | |
1165 | } | |
1166 | } | |
1167 | ||
1168 | netif_dbg(efx, probe, efx->net_dev, | |
1169 | "adding to unassociated list\n"); | |
1170 | list_add_tail(&efx->node, &efx_unassociated_list); | |
1171 | } | |
1172 | } | |
1173 | ||
1174 | static void efx_dissociate(struct efx_nic *efx) | |
1175 | { | |
1176 | struct efx_nic *other, *next; | |
1177 | ||
1178 | list_del(&efx->node); | |
1179 | efx->primary = NULL; | |
1180 | ||
1181 | list_for_each_entry_safe(other, next, &efx->secondary_list, node) { | |
1182 | list_del(&other->node); | |
1183 | netif_dbg(other, probe, other->net_dev, | |
1184 | "moving to unassociated list\n"); | |
1185 | list_add_tail(&other->node, &efx_unassociated_list); | |
1186 | other->primary = NULL; | |
1187 | } | |
1188 | } | |
1189 | ||
8ceee660 BH |
1190 | /* This configures the PCI device to enable I/O and DMA. */ |
1191 | static int efx_init_io(struct efx_nic *efx) | |
1192 | { | |
1193 | struct pci_dev *pci_dev = efx->pci_dev; | |
1194 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
b105798f | 1195 | unsigned int mem_map_size = efx->type->mem_map_size(efx); |
8ceee660 BH |
1196 | int rc; |
1197 | ||
62776d03 | 1198 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1199 | |
1200 | rc = pci_enable_device(pci_dev); | |
1201 | if (rc) { | |
62776d03 BH |
1202 | netif_err(efx, probe, efx->net_dev, |
1203 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1204 | goto fail1; |
1205 | } | |
1206 | ||
1207 | pci_set_master(pci_dev); | |
1208 | ||
1209 | /* Set the PCI DMA mask. Try all possibilities from our | |
1210 | * genuine mask down to 32 bits, because some architectures | |
1211 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1212 | * masks event though they reject 46 bit masks. | |
1213 | */ | |
1214 | while (dma_mask > 0x7fffffffUL) { | |
0e33d870 | 1215 | if (dma_supported(&pci_dev->dev, dma_mask)) { |
9663deda | 1216 | rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask); |
e9e01846 BH |
1217 | if (rc == 0) |
1218 | break; | |
1219 | } | |
8ceee660 BH |
1220 | dma_mask >>= 1; |
1221 | } | |
1222 | if (rc) { | |
62776d03 BH |
1223 | netif_err(efx, probe, efx->net_dev, |
1224 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1225 | goto fail2; |
1226 | } | |
62776d03 BH |
1227 | netif_dbg(efx, probe, efx->net_dev, |
1228 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 | 1229 | |
dc803df8 BH |
1230 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1231 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1232 | if (rc) { |
62776d03 BH |
1233 | netif_err(efx, probe, efx->net_dev, |
1234 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1235 | rc = -EIO; |
1236 | goto fail3; | |
1237 | } | |
b105798f | 1238 | efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); |
8ceee660 | 1239 | if (!efx->membase) { |
62776d03 BH |
1240 | netif_err(efx, probe, efx->net_dev, |
1241 | "could not map memory BAR at %llx+%x\n", | |
b105798f | 1242 | (unsigned long long)efx->membase_phys, mem_map_size); |
8ceee660 BH |
1243 | rc = -ENOMEM; |
1244 | goto fail4; | |
1245 | } | |
62776d03 BH |
1246 | netif_dbg(efx, probe, efx->net_dev, |
1247 | "memory BAR at %llx+%x (virtual %p)\n", | |
b105798f BH |
1248 | (unsigned long long)efx->membase_phys, mem_map_size, |
1249 | efx->membase); | |
8ceee660 BH |
1250 | |
1251 | return 0; | |
1252 | ||
1253 | fail4: | |
dc803df8 | 1254 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1255 | fail3: |
2c118e0f | 1256 | efx->membase_phys = 0; |
8ceee660 BH |
1257 | fail2: |
1258 | pci_disable_device(efx->pci_dev); | |
1259 | fail1: | |
1260 | return rc; | |
1261 | } | |
1262 | ||
1263 | static void efx_fini_io(struct efx_nic *efx) | |
1264 | { | |
62776d03 | 1265 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1266 | |
1267 | if (efx->membase) { | |
1268 | iounmap(efx->membase); | |
1269 | efx->membase = NULL; | |
1270 | } | |
1271 | ||
1272 | if (efx->membase_phys) { | |
dc803df8 | 1273 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1274 | efx->membase_phys = 0; |
8ceee660 BH |
1275 | } |
1276 | ||
1277 | pci_disable_device(efx->pci_dev); | |
1278 | } | |
1279 | ||
a9a52506 | 1280 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1281 | { |
cdb08f8f | 1282 | cpumask_var_t thread_mask; |
a16e5b24 | 1283 | unsigned int count; |
46123d04 | 1284 | int cpu; |
5b874e25 | 1285 | |
cd2d5b52 BH |
1286 | if (rss_cpus) { |
1287 | count = rss_cpus; | |
1288 | } else { | |
1289 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1290 | netif_warn(efx, probe, efx->net_dev, | |
1291 | "RSS disabled due to allocation failure\n"); | |
1292 | return 1; | |
1293 | } | |
46123d04 | 1294 | |
cd2d5b52 BH |
1295 | count = 0; |
1296 | for_each_online_cpu(cpu) { | |
1297 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1298 | ++count; | |
1299 | cpumask_or(thread_mask, thread_mask, | |
1300 | topology_thread_cpumask(cpu)); | |
1301 | } | |
1302 | } | |
1303 | ||
1304 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1305 | } |
1306 | ||
cd2d5b52 BH |
1307 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1308 | * table entries that are inaccessible to VFs | |
1309 | */ | |
1310 | if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1311 | count > efx_vf_size(efx)) { | |
1312 | netif_warn(efx, probe, efx->net_dev, | |
1313 | "Reducing number of RSS channels from %u to %u for " | |
1314 | "VF support. Increase vf-msix-limit to use more " | |
1315 | "channels on the PF.\n", | |
1316 | count, efx_vf_size(efx)); | |
1317 | count = efx_vf_size(efx); | |
46123d04 BH |
1318 | } |
1319 | ||
1320 | return count; | |
1321 | } | |
1322 | ||
1323 | /* Probe the number and type of interrupts we are able to obtain, and | |
1324 | * the resulting numbers of channels and RX queues. | |
1325 | */ | |
64d8ad6d | 1326 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1327 | { |
7f967c01 BH |
1328 | unsigned int extra_channels = 0; |
1329 | unsigned int i, j; | |
a16e5b24 | 1330 | int rc; |
8ceee660 | 1331 | |
7f967c01 BH |
1332 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1333 | if (efx->extra_channel_type[i]) | |
1334 | ++extra_channels; | |
1335 | ||
8ceee660 | 1336 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1337 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1338 | unsigned int n_channels; |
aa6ef27e | 1339 | |
a9a52506 | 1340 | n_channels = efx_wanted_parallelism(efx); |
a4900ac9 BH |
1341 | if (separate_tx_channels) |
1342 | n_channels *= 2; | |
7f967c01 | 1343 | n_channels += extra_channels; |
b105798f | 1344 | n_channels = min(n_channels, efx->max_channels); |
8ceee660 | 1345 | |
a4900ac9 | 1346 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1347 | xentries[i].entry = i; |
184603d8 AG |
1348 | rc = pci_enable_msix_range(efx->pci_dev, |
1349 | xentries, 1, n_channels); | |
1350 | if (rc < 0) { | |
1351 | /* Fall back to single channel MSI */ | |
1352 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
1353 | netif_err(efx, drv, efx->net_dev, | |
1354 | "could not enable MSI-X\n"); | |
1355 | } else if (rc < n_channels) { | |
62776d03 BH |
1356 | netif_err(efx, drv, efx->net_dev, |
1357 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1358 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1359 | netif_err(efx, drv, efx->net_dev, |
1360 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 | 1361 | n_channels = rc; |
8ceee660 BH |
1362 | } |
1363 | ||
184603d8 | 1364 | if (rc > 0) { |
a4900ac9 | 1365 | efx->n_channels = n_channels; |
7f967c01 BH |
1366 | if (n_channels > extra_channels) |
1367 | n_channels -= extra_channels; | |
a4900ac9 | 1368 | if (separate_tx_channels) { |
7f967c01 BH |
1369 | efx->n_tx_channels = max(n_channels / 2, 1U); |
1370 | efx->n_rx_channels = max(n_channels - | |
1371 | efx->n_tx_channels, | |
1372 | 1U); | |
a4900ac9 | 1373 | } else { |
7f967c01 BH |
1374 | efx->n_tx_channels = n_channels; |
1375 | efx->n_rx_channels = n_channels; | |
a4900ac9 | 1376 | } |
7f967c01 | 1377 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1378 | efx_get_channel(efx, i)->irq = |
1379 | xentries[i].vector; | |
8ceee660 BH |
1380 | } |
1381 | } | |
1382 | ||
1383 | /* Try single interrupt MSI */ | |
1384 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1385 | efx->n_channels = 1; |
a4900ac9 BH |
1386 | efx->n_rx_channels = 1; |
1387 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1388 | rc = pci_enable_msi(efx->pci_dev); |
1389 | if (rc == 0) { | |
f7d12cdc | 1390 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1391 | } else { |
62776d03 BH |
1392 | netif_err(efx, drv, efx->net_dev, |
1393 | "could not enable MSI\n"); | |
8ceee660 BH |
1394 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1395 | } | |
1396 | } | |
1397 | ||
1398 | /* Assume legacy interrupts */ | |
1399 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1400 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1401 | efx->n_rx_channels = 1; |
1402 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1403 | efx->legacy_irq = efx->pci_dev->irq; |
1404 | } | |
64d8ad6d | 1405 | |
7f967c01 BH |
1406 | /* Assign extra channels if possible */ |
1407 | j = efx->n_channels; | |
1408 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1409 | if (!efx->extra_channel_type[i]) | |
1410 | continue; | |
1411 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1412 | efx->n_channels <= extra_channels) { | |
1413 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1414 | } else { | |
1415 | --j; | |
1416 | efx_get_channel(efx, j)->type = | |
1417 | efx->extra_channel_type[i]; | |
1418 | } | |
1419 | } | |
1420 | ||
cd2d5b52 | 1421 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
3132d282 | 1422 | efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ? |
cd2d5b52 BH |
1423 | efx->n_rx_channels : efx_vf_size(efx)); |
1424 | ||
64d8ad6d | 1425 | return 0; |
8ceee660 BH |
1426 | } |
1427 | ||
261e4d96 | 1428 | static int efx_soft_enable_interrupts(struct efx_nic *efx) |
9f2cb71c | 1429 | { |
261e4d96 JC |
1430 | struct efx_channel *channel, *end_channel; |
1431 | int rc; | |
9f2cb71c | 1432 | |
8b7325b4 BH |
1433 | BUG_ON(efx->state == STATE_DISABLED); |
1434 | ||
d8291187 BH |
1435 | efx->irq_soft_enabled = true; |
1436 | smp_wmb(); | |
9f2cb71c BH |
1437 | |
1438 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1439 | if (!channel->type->keep_eventq) { |
1440 | rc = efx_init_eventq(channel); | |
1441 | if (rc) | |
1442 | goto fail; | |
1443 | } | |
9f2cb71c BH |
1444 | efx_start_eventq(channel); |
1445 | } | |
1446 | ||
1447 | efx_mcdi_mode_event(efx); | |
261e4d96 JC |
1448 | |
1449 | return 0; | |
1450 | fail: | |
1451 | end_channel = channel; | |
1452 | efx_for_each_channel(channel, efx) { | |
1453 | if (channel == end_channel) | |
1454 | break; | |
1455 | efx_stop_eventq(channel); | |
1456 | if (!channel->type->keep_eventq) | |
1457 | efx_fini_eventq(channel); | |
1458 | } | |
1459 | ||
1460 | return rc; | |
9f2cb71c BH |
1461 | } |
1462 | ||
d8291187 | 1463 | static void efx_soft_disable_interrupts(struct efx_nic *efx) |
9f2cb71c BH |
1464 | { |
1465 | struct efx_channel *channel; | |
1466 | ||
8b7325b4 BH |
1467 | if (efx->state == STATE_DISABLED) |
1468 | return; | |
1469 | ||
9f2cb71c BH |
1470 | efx_mcdi_mode_poll(efx); |
1471 | ||
d8291187 BH |
1472 | efx->irq_soft_enabled = false; |
1473 | smp_wmb(); | |
1474 | ||
1475 | if (efx->legacy_irq) | |
9f2cb71c | 1476 | synchronize_irq(efx->legacy_irq); |
9f2cb71c BH |
1477 | |
1478 | efx_for_each_channel(channel, efx) { | |
1479 | if (channel->irq) | |
1480 | synchronize_irq(channel->irq); | |
1481 | ||
1482 | efx_stop_eventq(channel); | |
d8291187 | 1483 | if (!channel->type->keep_eventq) |
7f967c01 | 1484 | efx_fini_eventq(channel); |
9f2cb71c | 1485 | } |
cade715f BH |
1486 | |
1487 | /* Flush the asynchronous MCDI request queue */ | |
1488 | efx_mcdi_flush_async(efx); | |
9f2cb71c BH |
1489 | } |
1490 | ||
261e4d96 | 1491 | static int efx_enable_interrupts(struct efx_nic *efx) |
d8291187 | 1492 | { |
261e4d96 JC |
1493 | struct efx_channel *channel, *end_channel; |
1494 | int rc; | |
d8291187 BH |
1495 | |
1496 | BUG_ON(efx->state == STATE_DISABLED); | |
1497 | ||
1498 | if (efx->eeh_disabled_legacy_irq) { | |
1499 | enable_irq(efx->legacy_irq); | |
1500 | efx->eeh_disabled_legacy_irq = false; | |
1501 | } | |
1502 | ||
86094f7f | 1503 | efx->type->irq_enable_master(efx); |
d8291187 BH |
1504 | |
1505 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1506 | if (channel->type->keep_eventq) { |
1507 | rc = efx_init_eventq(channel); | |
1508 | if (rc) | |
1509 | goto fail; | |
1510 | } | |
1511 | } | |
1512 | ||
1513 | rc = efx_soft_enable_interrupts(efx); | |
1514 | if (rc) | |
1515 | goto fail; | |
1516 | ||
1517 | return 0; | |
1518 | ||
1519 | fail: | |
1520 | end_channel = channel; | |
1521 | efx_for_each_channel(channel, efx) { | |
1522 | if (channel == end_channel) | |
1523 | break; | |
d8291187 | 1524 | if (channel->type->keep_eventq) |
261e4d96 | 1525 | efx_fini_eventq(channel); |
d8291187 BH |
1526 | } |
1527 | ||
261e4d96 JC |
1528 | efx->type->irq_disable_non_ev(efx); |
1529 | ||
1530 | return rc; | |
d8291187 BH |
1531 | } |
1532 | ||
1533 | static void efx_disable_interrupts(struct efx_nic *efx) | |
1534 | { | |
1535 | struct efx_channel *channel; | |
1536 | ||
1537 | efx_soft_disable_interrupts(efx); | |
1538 | ||
1539 | efx_for_each_channel(channel, efx) { | |
1540 | if (channel->type->keep_eventq) | |
1541 | efx_fini_eventq(channel); | |
1542 | } | |
1543 | ||
86094f7f | 1544 | efx->type->irq_disable_non_ev(efx); |
d8291187 BH |
1545 | } |
1546 | ||
8ceee660 BH |
1547 | static void efx_remove_interrupts(struct efx_nic *efx) |
1548 | { | |
1549 | struct efx_channel *channel; | |
1550 | ||
1551 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1552 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1553 | channel->irq = 0; |
1554 | pci_disable_msi(efx->pci_dev); | |
1555 | pci_disable_msix(efx->pci_dev); | |
1556 | ||
1557 | /* Remove legacy interrupt */ | |
1558 | efx->legacy_irq = 0; | |
1559 | } | |
1560 | ||
8831da7b | 1561 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1562 | { |
602a5322 BH |
1563 | struct efx_channel *channel; |
1564 | struct efx_tx_queue *tx_queue; | |
1565 | ||
97653431 | 1566 | efx->tx_channel_offset = |
a4900ac9 | 1567 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 | 1568 | |
79d68b37 SH |
1569 | /* We need to mark which channels really have RX and TX |
1570 | * queues, and adjust the TX queue numbers if we have separate | |
602a5322 BH |
1571 | * RX-only and TX-only channels. |
1572 | */ | |
1573 | efx_for_each_channel(channel, efx) { | |
79d68b37 SH |
1574 | if (channel->channel < efx->n_rx_channels) |
1575 | channel->rx_queue.core_index = channel->channel; | |
1576 | else | |
1577 | channel->rx_queue.core_index = -1; | |
1578 | ||
602a5322 BH |
1579 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1580 | tx_queue->queue -= (efx->tx_channel_offset * | |
1581 | EFX_TXQ_TYPES); | |
1582 | } | |
8ceee660 BH |
1583 | } |
1584 | ||
1585 | static int efx_probe_nic(struct efx_nic *efx) | |
1586 | { | |
765c9f46 | 1587 | size_t i; |
8ceee660 BH |
1588 | int rc; |
1589 | ||
62776d03 | 1590 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1591 | |
1592 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1593 | rc = efx->type->probe(efx); |
8ceee660 BH |
1594 | if (rc) |
1595 | return rc; | |
1596 | ||
a4900ac9 | 1597 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1598 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1599 | rc = efx_probe_interrupts(efx); |
1600 | if (rc) | |
c15eed22 | 1601 | goto fail1; |
8ceee660 | 1602 | |
52ad762b DP |
1603 | efx_set_channels(efx); |
1604 | ||
c15eed22 BH |
1605 | rc = efx->type->dimension_resources(efx); |
1606 | if (rc) | |
1607 | goto fail2; | |
28e47c49 | 1608 | |
5d3a6fca BH |
1609 | if (efx->n_channels > 1) |
1610 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1611 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 | 1612 | efx->rx_indir_table[i] = |
cd2d5b52 | 1613 | ethtool_rxfh_indir_default(i, efx->rss_spread); |
5d3a6fca | 1614 | |
c4f4adc7 BH |
1615 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1616 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1617 | |
1618 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1619 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1620 | true); | |
8ceee660 BH |
1621 | |
1622 | return 0; | |
64d8ad6d | 1623 | |
c15eed22 BH |
1624 | fail2: |
1625 | efx_remove_interrupts(efx); | |
1626 | fail1: | |
64d8ad6d BH |
1627 | efx->type->remove(efx); |
1628 | return rc; | |
8ceee660 BH |
1629 | } |
1630 | ||
1631 | static void efx_remove_nic(struct efx_nic *efx) | |
1632 | { | |
62776d03 | 1633 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1634 | |
1635 | efx_remove_interrupts(efx); | |
ef2b90ee | 1636 | efx->type->remove(efx); |
8ceee660 BH |
1637 | } |
1638 | ||
add72477 BH |
1639 | static int efx_probe_filters(struct efx_nic *efx) |
1640 | { | |
1641 | int rc; | |
1642 | ||
1643 | spin_lock_init(&efx->filter_lock); | |
1644 | ||
1645 | rc = efx->type->filter_table_probe(efx); | |
1646 | if (rc) | |
1647 | return rc; | |
1648 | ||
1649 | #ifdef CONFIG_RFS_ACCEL | |
1650 | if (efx->type->offload_features & NETIF_F_NTUPLE) { | |
1651 | efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters, | |
1652 | sizeof(*efx->rps_flow_id), | |
1653 | GFP_KERNEL); | |
1654 | if (!efx->rps_flow_id) { | |
1655 | efx->type->filter_table_remove(efx); | |
1656 | return -ENOMEM; | |
1657 | } | |
1658 | } | |
1659 | #endif | |
1660 | ||
1661 | return 0; | |
1662 | } | |
1663 | ||
1664 | static void efx_remove_filters(struct efx_nic *efx) | |
1665 | { | |
1666 | #ifdef CONFIG_RFS_ACCEL | |
1667 | kfree(efx->rps_flow_id); | |
1668 | #endif | |
1669 | efx->type->filter_table_remove(efx); | |
1670 | } | |
1671 | ||
1672 | static void efx_restore_filters(struct efx_nic *efx) | |
1673 | { | |
1674 | efx->type->filter_table_restore(efx); | |
1675 | } | |
1676 | ||
8ceee660 BH |
1677 | /************************************************************************** |
1678 | * | |
1679 | * NIC startup/shutdown | |
1680 | * | |
1681 | *************************************************************************/ | |
1682 | ||
1683 | static int efx_probe_all(struct efx_nic *efx) | |
1684 | { | |
8ceee660 BH |
1685 | int rc; |
1686 | ||
8ceee660 BH |
1687 | rc = efx_probe_nic(efx); |
1688 | if (rc) { | |
62776d03 | 1689 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1690 | goto fail1; |
1691 | } | |
1692 | ||
8ceee660 BH |
1693 | rc = efx_probe_port(efx); |
1694 | if (rc) { | |
62776d03 | 1695 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1696 | goto fail2; |
1697 | } | |
1698 | ||
7e6d06f0 BH |
1699 | BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); |
1700 | if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { | |
1701 | rc = -EINVAL; | |
1702 | goto fail3; | |
1703 | } | |
ecc910f5 | 1704 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1705 | |
64eebcfd BH |
1706 | rc = efx_probe_filters(efx); |
1707 | if (rc) { | |
1708 | netif_err(efx, probe, efx->net_dev, | |
1709 | "failed to create filter tables\n"); | |
7f967c01 | 1710 | goto fail3; |
64eebcfd BH |
1711 | } |
1712 | ||
7f967c01 BH |
1713 | rc = efx_probe_channels(efx); |
1714 | if (rc) | |
1715 | goto fail4; | |
1716 | ||
8ceee660 BH |
1717 | return 0; |
1718 | ||
64eebcfd | 1719 | fail4: |
7f967c01 | 1720 | efx_remove_filters(efx); |
8ceee660 | 1721 | fail3: |
8ceee660 BH |
1722 | efx_remove_port(efx); |
1723 | fail2: | |
1724 | efx_remove_nic(efx); | |
1725 | fail1: | |
1726 | return rc; | |
1727 | } | |
1728 | ||
8b7325b4 BH |
1729 | /* If the interface is supposed to be running but is not, start |
1730 | * the hardware and software data path, regular activity for the port | |
1731 | * (MAC statistics, link polling, etc.) and schedule the port to be | |
1732 | * reconfigured. Interrupts must already be enabled. This function | |
1733 | * is safe to call multiple times, so long as the NIC is not disabled. | |
1734 | * Requires the RTNL lock. | |
9f2cb71c | 1735 | */ |
8ceee660 BH |
1736 | static void efx_start_all(struct efx_nic *efx) |
1737 | { | |
8ceee660 | 1738 | EFX_ASSERT_RESET_SERIALISED(efx); |
8b7325b4 | 1739 | BUG_ON(efx->state == STATE_DISABLED); |
8ceee660 BH |
1740 | |
1741 | /* Check that it is appropriate to restart the interface. All | |
1742 | * of these flags are safe to read under just the rtnl lock */ | |
e283546c EC |
1743 | if (efx->port_enabled || !netif_running(efx->net_dev) || |
1744 | efx->reset_pending) | |
8ceee660 BH |
1745 | return; |
1746 | ||
8ceee660 | 1747 | efx_start_port(efx); |
9f2cb71c | 1748 | efx_start_datapath(efx); |
8880f4ec | 1749 | |
626950db AR |
1750 | /* Start the hardware monitor if there is one */ |
1751 | if (efx->type->monitor != NULL) | |
8ceee660 BH |
1752 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1753 | efx_monitor_interval); | |
626950db AR |
1754 | |
1755 | /* If link state detection is normally event-driven, we have | |
1756 | * to poll now because we could have missed a change | |
1757 | */ | |
1758 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { | |
78c1f0a0 SH |
1759 | mutex_lock(&efx->mac_lock); |
1760 | if (efx->phy_op->poll(efx)) | |
1761 | efx_link_status_changed(efx); | |
1762 | mutex_unlock(&efx->mac_lock); | |
1763 | } | |
55edc6e6 | 1764 | |
ef2b90ee | 1765 | efx->type->start_stats(efx); |
f8f3b5ae JC |
1766 | efx->type->pull_stats(efx); |
1767 | spin_lock_bh(&efx->stats_lock); | |
1768 | efx->type->update_stats(efx, NULL, NULL); | |
1769 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
1770 | } |
1771 | ||
8b7325b4 BH |
1772 | /* Quiesce the hardware and software data path, and regular activity |
1773 | * for the port without bringing the link down. Safe to call multiple | |
1774 | * times with the NIC in almost any state, but interrupts should be | |
1775 | * enabled. Requires the RTNL lock. | |
1776 | */ | |
8ceee660 BH |
1777 | static void efx_stop_all(struct efx_nic *efx) |
1778 | { | |
8ceee660 BH |
1779 | EFX_ASSERT_RESET_SERIALISED(efx); |
1780 | ||
1781 | /* port_enabled can be read safely under the rtnl lock */ | |
1782 | if (!efx->port_enabled) | |
1783 | return; | |
1784 | ||
f8f3b5ae JC |
1785 | /* update stats before we go down so we can accurately count |
1786 | * rx_nodesc_drops | |
1787 | */ | |
1788 | efx->type->pull_stats(efx); | |
1789 | spin_lock_bh(&efx->stats_lock); | |
1790 | efx->type->update_stats(efx, NULL, NULL); | |
1791 | spin_unlock_bh(&efx->stats_lock); | |
ef2b90ee | 1792 | efx->type->stop_stats(efx); |
8ceee660 BH |
1793 | efx_stop_port(efx); |
1794 | ||
29c69a48 BH |
1795 | /* Stop the kernel transmit interface. This is only valid if |
1796 | * the device is stopped or detached; otherwise the watchdog | |
1797 | * may fire immediately. | |
1798 | */ | |
1799 | WARN_ON(netif_running(efx->net_dev) && | |
1800 | netif_device_present(efx->net_dev)); | |
9f2cb71c BH |
1801 | netif_tx_disable(efx->net_dev); |
1802 | ||
1803 | efx_stop_datapath(efx); | |
8ceee660 BH |
1804 | } |
1805 | ||
1806 | static void efx_remove_all(struct efx_nic *efx) | |
1807 | { | |
4642610c | 1808 | efx_remove_channels(efx); |
7f967c01 | 1809 | efx_remove_filters(efx); |
8ceee660 BH |
1810 | efx_remove_port(efx); |
1811 | efx_remove_nic(efx); | |
1812 | } | |
1813 | ||
8ceee660 BH |
1814 | /************************************************************************** |
1815 | * | |
1816 | * Interrupt moderation | |
1817 | * | |
1818 | **************************************************************************/ | |
1819 | ||
cc180b69 | 1820 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1821 | { |
b548f976 BH |
1822 | if (usecs == 0) |
1823 | return 0; | |
cc180b69 | 1824 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1825 | return 1; /* never round down to 0 */ |
cc180b69 | 1826 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1827 | } |
1828 | ||
8ceee660 | 1829 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1830 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1831 | unsigned int rx_usecs, bool rx_adaptive, | |
1832 | bool rx_may_override_tx) | |
8ceee660 | 1833 | { |
f7d12cdc | 1834 | struct efx_channel *channel; |
cc180b69 BH |
1835 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1836 | efx->timer_quantum_ns, | |
1837 | 1000); | |
1838 | unsigned int tx_ticks; | |
1839 | unsigned int rx_ticks; | |
8ceee660 BH |
1840 | |
1841 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1842 | ||
cc180b69 | 1843 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1844 | return -EINVAL; |
1845 | ||
cc180b69 BH |
1846 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1847 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1848 | ||
9e393b30 BH |
1849 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1850 | !rx_may_override_tx) { | |
1851 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1852 | "RX and TX IRQ moderation must be equal\n"); | |
1853 | return -EINVAL; | |
1854 | } | |
1855 | ||
6fb70fd1 | 1856 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1857 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1858 | efx_for_each_channel(channel, efx) { |
525da907 | 1859 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1860 | channel->irq_moderation = rx_ticks; |
525da907 | 1861 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1862 | channel->irq_moderation = tx_ticks; |
1863 | } | |
9e393b30 BH |
1864 | |
1865 | return 0; | |
8ceee660 BH |
1866 | } |
1867 | ||
a0c4faf5 BH |
1868 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1869 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1870 | { | |
cc180b69 BH |
1871 | /* We must round up when converting ticks to microseconds |
1872 | * because we round down when converting the other way. | |
1873 | */ | |
1874 | ||
a0c4faf5 | 1875 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1876 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1877 | efx->timer_quantum_ns, | |
1878 | 1000); | |
a0c4faf5 BH |
1879 | |
1880 | /* If channels are shared between RX and TX, so is IRQ | |
1881 | * moderation. Otherwise, IRQ moderation is the same for all | |
1882 | * TX channels and is not adaptive. | |
1883 | */ | |
1884 | if (efx->tx_channel_offset == 0) | |
1885 | *tx_usecs = *rx_usecs; | |
1886 | else | |
cc180b69 | 1887 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1888 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1889 | efx->timer_quantum_ns, |
1890 | 1000); | |
a0c4faf5 BH |
1891 | } |
1892 | ||
8ceee660 BH |
1893 | /************************************************************************** |
1894 | * | |
1895 | * Hardware monitor | |
1896 | * | |
1897 | **************************************************************************/ | |
1898 | ||
e254c274 | 1899 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1900 | static void efx_monitor(struct work_struct *data) |
1901 | { | |
1902 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1903 | monitor_work.work); | |
8ceee660 | 1904 | |
62776d03 BH |
1905 | netif_vdbg(efx, timer, efx->net_dev, |
1906 | "hardware monitor executing on CPU %d\n", | |
1907 | raw_smp_processor_id()); | |
ef2b90ee | 1908 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1909 | |
8ceee660 BH |
1910 | /* If the mac_lock is already held then it is likely a port |
1911 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1912 | * most of the work of monitor() anyway. */ |
1913 | if (mutex_trylock(&efx->mac_lock)) { | |
1914 | if (efx->port_enabled) | |
1915 | efx->type->monitor(efx); | |
1916 | mutex_unlock(&efx->mac_lock); | |
1917 | } | |
8ceee660 | 1918 | |
8ceee660 BH |
1919 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1920 | efx_monitor_interval); | |
1921 | } | |
1922 | ||
1923 | /************************************************************************** | |
1924 | * | |
1925 | * ioctls | |
1926 | * | |
1927 | *************************************************************************/ | |
1928 | ||
1929 | /* Net device ioctl | |
1930 | * Context: process, rtnl_lock() held. | |
1931 | */ | |
1932 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1933 | { | |
767e468c | 1934 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1935 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 | 1936 | |
7c236c43 | 1937 | if (cmd == SIOCSHWTSTAMP) |
433dc9b3 BH |
1938 | return efx_ptp_set_ts_config(efx, ifr); |
1939 | if (cmd == SIOCGHWTSTAMP) | |
1940 | return efx_ptp_get_ts_config(efx, ifr); | |
7c236c43 | 1941 | |
68e7f45e BH |
1942 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1943 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1944 | (data->phy_id & 0xfc00) == 0x0400) | |
1945 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1946 | ||
1947 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1948 | } |
1949 | ||
1950 | /************************************************************************** | |
1951 | * | |
1952 | * NAPI interface | |
1953 | * | |
1954 | **************************************************************************/ | |
1955 | ||
7f967c01 BH |
1956 | static void efx_init_napi_channel(struct efx_channel *channel) |
1957 | { | |
1958 | struct efx_nic *efx = channel->efx; | |
1959 | ||
1960 | channel->napi_dev = efx->net_dev; | |
1961 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
1962 | efx_poll, napi_weight); | |
1963 | } | |
1964 | ||
e8f14992 | 1965 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1966 | { |
1967 | struct efx_channel *channel; | |
8ceee660 | 1968 | |
7f967c01 BH |
1969 | efx_for_each_channel(channel, efx) |
1970 | efx_init_napi_channel(channel); | |
e8f14992 BH |
1971 | } |
1972 | ||
1973 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1974 | { | |
1975 | if (channel->napi_dev) | |
1976 | netif_napi_del(&channel->napi_str); | |
1977 | channel->napi_dev = NULL; | |
8ceee660 BH |
1978 | } |
1979 | ||
1980 | static void efx_fini_napi(struct efx_nic *efx) | |
1981 | { | |
1982 | struct efx_channel *channel; | |
1983 | ||
e8f14992 BH |
1984 | efx_for_each_channel(channel, efx) |
1985 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1986 | } |
1987 | ||
1988 | /************************************************************************** | |
1989 | * | |
1990 | * Kernel netpoll interface | |
1991 | * | |
1992 | *************************************************************************/ | |
1993 | ||
1994 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1995 | ||
1996 | /* Although in the common case interrupts will be disabled, this is not | |
1997 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1998 | * so no locking is required. | |
1999 | */ | |
2000 | static void efx_netpoll(struct net_device *net_dev) | |
2001 | { | |
767e468c | 2002 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
2003 | struct efx_channel *channel; |
2004 | ||
64ee3120 | 2005 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
2006 | efx_schedule_channel(channel); |
2007 | } | |
2008 | ||
2009 | #endif | |
2010 | ||
2011 | /************************************************************************** | |
2012 | * | |
2013 | * Kernel net device interface | |
2014 | * | |
2015 | *************************************************************************/ | |
2016 | ||
2017 | /* Context: process, rtnl_lock() held. */ | |
2018 | static int efx_net_open(struct net_device *net_dev) | |
2019 | { | |
767e468c | 2020 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 BH |
2021 | int rc; |
2022 | ||
62776d03 BH |
2023 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
2024 | raw_smp_processor_id()); | |
8ceee660 | 2025 | |
8b7325b4 BH |
2026 | rc = efx_check_disabled(efx); |
2027 | if (rc) | |
2028 | return rc; | |
f8b87c17 BH |
2029 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
2030 | return -EBUSY; | |
8880f4ec BH |
2031 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
2032 | return -EIO; | |
f8b87c17 | 2033 | |
78c1f0a0 SH |
2034 | /* Notify the kernel of the link state polled during driver load, |
2035 | * before the monitor starts running */ | |
2036 | efx_link_status_changed(efx); | |
2037 | ||
8ceee660 | 2038 | efx_start_all(efx); |
dd40781e | 2039 | efx_selftest_async_start(efx); |
8ceee660 BH |
2040 | return 0; |
2041 | } | |
2042 | ||
2043 | /* Context: process, rtnl_lock() held. | |
2044 | * Note that the kernel will ignore our return code; this method | |
2045 | * should really be a void. | |
2046 | */ | |
2047 | static int efx_net_stop(struct net_device *net_dev) | |
2048 | { | |
767e468c | 2049 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2050 | |
62776d03 BH |
2051 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
2052 | raw_smp_processor_id()); | |
8ceee660 | 2053 | |
8b7325b4 BH |
2054 | /* Stop the device and flush all the channels */ |
2055 | efx_stop_all(efx); | |
8ceee660 BH |
2056 | |
2057 | return 0; | |
2058 | } | |
2059 | ||
5b9e207c | 2060 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
2061 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
2062 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 2063 | { |
767e468c | 2064 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2065 | |
55edc6e6 | 2066 | spin_lock_bh(&efx->stats_lock); |
cd0ecc9a | 2067 | efx->type->update_stats(efx, NULL, stats); |
1cb34522 BH |
2068 | spin_unlock_bh(&efx->stats_lock); |
2069 | ||
8ceee660 BH |
2070 | return stats; |
2071 | } | |
2072 | ||
2073 | /* Context: netif_tx_lock held, BHs disabled. */ | |
2074 | static void efx_watchdog(struct net_device *net_dev) | |
2075 | { | |
767e468c | 2076 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2077 | |
62776d03 BH |
2078 | netif_err(efx, tx_err, efx->net_dev, |
2079 | "TX stuck with port_enabled=%d: resetting channels\n", | |
2080 | efx->port_enabled); | |
8ceee660 | 2081 | |
739bb23d | 2082 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
2083 | } |
2084 | ||
2085 | ||
2086 | /* Context: process, rtnl_lock() held. */ | |
2087 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
2088 | { | |
767e468c | 2089 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 | 2090 | int rc; |
8ceee660 | 2091 | |
8b7325b4 BH |
2092 | rc = efx_check_disabled(efx); |
2093 | if (rc) | |
2094 | return rc; | |
8ceee660 BH |
2095 | if (new_mtu > EFX_MAX_MTU) |
2096 | return -EINVAL; | |
2097 | ||
62776d03 | 2098 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 2099 | |
29c69a48 BH |
2100 | efx_device_detach_sync(efx); |
2101 | efx_stop_all(efx); | |
2102 | ||
d3245b28 | 2103 | mutex_lock(&efx->mac_lock); |
8ceee660 | 2104 | net_dev->mtu = new_mtu; |
710b208d | 2105 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
2106 | mutex_unlock(&efx->mac_lock); |
2107 | ||
8ceee660 | 2108 | efx_start_all(efx); |
29c69a48 | 2109 | netif_device_attach(efx->net_dev); |
6c8eef4a | 2110 | return 0; |
8ceee660 BH |
2111 | } |
2112 | ||
2113 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
2114 | { | |
767e468c | 2115 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2116 | struct sockaddr *addr = data; |
e0b3ae30 | 2117 | u8 *new_addr = addr->sa_data; |
8ceee660 | 2118 | |
8ceee660 | 2119 | if (!is_valid_ether_addr(new_addr)) { |
62776d03 BH |
2120 | netif_err(efx, drv, efx->net_dev, |
2121 | "invalid ethernet MAC address requested: %pM\n", | |
2122 | new_addr); | |
504f9b5a | 2123 | return -EADDRNOTAVAIL; |
8ceee660 BH |
2124 | } |
2125 | ||
cd84ff4d | 2126 | ether_addr_copy(net_dev->dev_addr, new_addr); |
cd2d5b52 | 2127 | efx_sriov_mac_address_changed(efx); |
8ceee660 BH |
2128 | |
2129 | /* Reconfigure the MAC */ | |
d3245b28 | 2130 | mutex_lock(&efx->mac_lock); |
710b208d | 2131 | efx->type->reconfigure_mac(efx); |
d3245b28 | 2132 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
2133 | |
2134 | return 0; | |
2135 | } | |
2136 | ||
a816f75a | 2137 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 2138 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 2139 | { |
767e468c | 2140 | struct efx_nic *efx = netdev_priv(net_dev); |
a816f75a | 2141 | |
8be4f3e6 BH |
2142 | if (efx->port_enabled) |
2143 | queue_work(efx->workqueue, &efx->mac_work); | |
2144 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
2145 | } |
2146 | ||
c8f44aff | 2147 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
2148 | { |
2149 | struct efx_nic *efx = netdev_priv(net_dev); | |
2150 | ||
2151 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
2152 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
fbd79120 | 2153 | return efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); |
abfe9039 BH |
2154 | |
2155 | return 0; | |
2156 | } | |
2157 | ||
8127d661 | 2158 | static const struct net_device_ops efx_farch_netdev_ops = { |
c3ecb9f3 SH |
2159 | .ndo_open = efx_net_open, |
2160 | .ndo_stop = efx_net_stop, | |
4472702e | 2161 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
2162 | .ndo_tx_timeout = efx_watchdog, |
2163 | .ndo_start_xmit = efx_hard_start_xmit, | |
2164 | .ndo_validate_addr = eth_validate_addr, | |
2165 | .ndo_do_ioctl = efx_ioctl, | |
2166 | .ndo_change_mtu = efx_change_mtu, | |
2167 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2168 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2169 | .ndo_set_features = efx_set_features, |
cd2d5b52 BH |
2170 | #ifdef CONFIG_SFC_SRIOV |
2171 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, | |
2172 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2173 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2174 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
2175 | #endif | |
c3ecb9f3 SH |
2176 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2177 | .ndo_poll_controller = efx_netpoll, | |
2178 | #endif | |
94b274bf | 2179 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
2180 | #ifdef CONFIG_RFS_ACCEL |
2181 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2182 | #endif | |
c3ecb9f3 SH |
2183 | }; |
2184 | ||
8127d661 BH |
2185 | static const struct net_device_ops efx_ef10_netdev_ops = { |
2186 | .ndo_open = efx_net_open, | |
2187 | .ndo_stop = efx_net_stop, | |
2188 | .ndo_get_stats64 = efx_net_stats, | |
2189 | .ndo_tx_timeout = efx_watchdog, | |
2190 | .ndo_start_xmit = efx_hard_start_xmit, | |
2191 | .ndo_validate_addr = eth_validate_addr, | |
2192 | .ndo_do_ioctl = efx_ioctl, | |
2193 | .ndo_change_mtu = efx_change_mtu, | |
2194 | .ndo_set_mac_address = efx_set_mac_address, | |
2195 | .ndo_set_rx_mode = efx_set_rx_mode, | |
2196 | .ndo_set_features = efx_set_features, | |
2197 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2198 | .ndo_poll_controller = efx_netpoll, | |
2199 | #endif | |
2200 | #ifdef CONFIG_RFS_ACCEL | |
2201 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2202 | #endif | |
2203 | }; | |
2204 | ||
7dde596e BH |
2205 | static void efx_update_name(struct efx_nic *efx) |
2206 | { | |
2207 | strcpy(efx->name, efx->net_dev->name); | |
2208 | efx_mtd_rename(efx); | |
2209 | efx_set_channel_names(efx); | |
2210 | } | |
2211 | ||
8ceee660 BH |
2212 | static int efx_netdev_event(struct notifier_block *this, |
2213 | unsigned long event, void *ptr) | |
2214 | { | |
351638e7 | 2215 | struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); |
8ceee660 | 2216 | |
8127d661 BH |
2217 | if ((net_dev->netdev_ops == &efx_farch_netdev_ops || |
2218 | net_dev->netdev_ops == &efx_ef10_netdev_ops) && | |
7dde596e BH |
2219 | event == NETDEV_CHANGENAME) |
2220 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2221 | |
2222 | return NOTIFY_DONE; | |
2223 | } | |
2224 | ||
2225 | static struct notifier_block efx_netdev_notifier = { | |
2226 | .notifier_call = efx_netdev_event, | |
2227 | }; | |
2228 | ||
06d5e193 BH |
2229 | static ssize_t |
2230 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2231 | { | |
2232 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2233 | return sprintf(buf, "%d\n", efx->phy_type); | |
2234 | } | |
776fbcc9 | 2235 | static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); |
06d5e193 | 2236 | |
8ceee660 BH |
2237 | static int efx_register_netdev(struct efx_nic *efx) |
2238 | { | |
2239 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2240 | struct efx_channel *channel; |
8ceee660 BH |
2241 | int rc; |
2242 | ||
2243 | net_dev->watchdog_timeo = 5 * HZ; | |
2244 | net_dev->irq = efx->pci_dev->irq; | |
8127d661 BH |
2245 | if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) { |
2246 | net_dev->netdev_ops = &efx_ef10_netdev_ops; | |
2247 | net_dev->priv_flags |= IFF_UNICAST_FLT; | |
2248 | } else { | |
2249 | net_dev->netdev_ops = &efx_farch_netdev_ops; | |
2250 | } | |
7ad24ea4 | 2251 | net_dev->ethtool_ops = &efx_ethtool_ops; |
7e6d06f0 | 2252 | net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; |
8ceee660 | 2253 | |
7dde596e | 2254 | rtnl_lock(); |
aed0628d | 2255 | |
7153f623 BH |
2256 | /* Enable resets to be scheduled and check whether any were |
2257 | * already requested. If so, the NIC is probably hosed so we | |
2258 | * abort. | |
2259 | */ | |
2260 | efx->state = STATE_READY; | |
2261 | smp_mb(); /* ensure we change state before checking reset_pending */ | |
2262 | if (efx->reset_pending) { | |
2263 | netif_err(efx, probe, efx->net_dev, | |
2264 | "aborting probe due to scheduled reset\n"); | |
2265 | rc = -EIO; | |
2266 | goto fail_locked; | |
2267 | } | |
2268 | ||
aed0628d BH |
2269 | rc = dev_alloc_name(net_dev, net_dev->name); |
2270 | if (rc < 0) | |
2271 | goto fail_locked; | |
7dde596e | 2272 | efx_update_name(efx); |
aed0628d | 2273 | |
8f8b3d51 BH |
2274 | /* Always start with carrier off; PHY events will detect the link */ |
2275 | netif_carrier_off(net_dev); | |
2276 | ||
aed0628d BH |
2277 | rc = register_netdevice(net_dev); |
2278 | if (rc) | |
2279 | goto fail_locked; | |
2280 | ||
c04bfc6b BH |
2281 | efx_for_each_channel(channel, efx) { |
2282 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2283 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2284 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2285 | } |
2286 | ||
0bcf4a64 BH |
2287 | efx_associate(efx); |
2288 | ||
7dde596e | 2289 | rtnl_unlock(); |
8ceee660 | 2290 | |
06d5e193 BH |
2291 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2292 | if (rc) { | |
62776d03 BH |
2293 | netif_err(efx, drv, efx->net_dev, |
2294 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2295 | goto fail_registered; |
2296 | } | |
2297 | ||
8ceee660 | 2298 | return 0; |
06d5e193 | 2299 | |
7153f623 BH |
2300 | fail_registered: |
2301 | rtnl_lock(); | |
0bcf4a64 | 2302 | efx_dissociate(efx); |
7153f623 | 2303 | unregister_netdevice(net_dev); |
aed0628d | 2304 | fail_locked: |
7153f623 | 2305 | efx->state = STATE_UNINIT; |
aed0628d | 2306 | rtnl_unlock(); |
62776d03 | 2307 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d | 2308 | return rc; |
8ceee660 BH |
2309 | } |
2310 | ||
2311 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2312 | { | |
8ceee660 BH |
2313 | if (!efx->net_dev) |
2314 | return; | |
2315 | ||
767e468c | 2316 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 | 2317 | |
73ba7b68 BH |
2318 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
2319 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
7153f623 BH |
2320 | |
2321 | rtnl_lock(); | |
2322 | unregister_netdevice(efx->net_dev); | |
2323 | efx->state = STATE_UNINIT; | |
2324 | rtnl_unlock(); | |
8ceee660 BH |
2325 | } |
2326 | ||
2327 | /************************************************************************** | |
2328 | * | |
2329 | * Device reset and suspend | |
2330 | * | |
2331 | **************************************************************************/ | |
2332 | ||
2467ca46 BH |
2333 | /* Tears down the entire software state and most of the hardware state |
2334 | * before reset. */ | |
d3245b28 | 2335 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2336 | { |
8ceee660 BH |
2337 | EFX_ASSERT_RESET_SERIALISED(efx); |
2338 | ||
e283546c EC |
2339 | if (method == RESET_TYPE_MCDI_TIMEOUT) |
2340 | efx->type->prepare_flr(efx); | |
2341 | ||
2467ca46 | 2342 | efx_stop_all(efx); |
d8291187 | 2343 | efx_disable_interrupts(efx); |
5642ceef BH |
2344 | |
2345 | mutex_lock(&efx->mac_lock); | |
4b988280 SH |
2346 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2347 | efx->phy_op->fini(efx); | |
ef2b90ee | 2348 | efx->type->fini(efx); |
8ceee660 BH |
2349 | } |
2350 | ||
2467ca46 BH |
2351 | /* This function will always ensure that the locks acquired in |
2352 | * efx_reset_down() are released. A failure return code indicates | |
2353 | * that we were unable to reinitialise the hardware, and the | |
2354 | * driver should be disabled. If ok is false, then the rx and tx | |
2355 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2356 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2357 | { |
2358 | int rc; | |
2359 | ||
2467ca46 | 2360 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2361 | |
e283546c EC |
2362 | if (method == RESET_TYPE_MCDI_TIMEOUT) |
2363 | efx->type->finish_flr(efx); | |
2364 | ||
2365 | /* Ensure that SRAM is initialised even if we're disabling the device */ | |
ef2b90ee | 2366 | rc = efx->type->init(efx); |
8ceee660 | 2367 | if (rc) { |
62776d03 | 2368 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2369 | goto fail; |
8ceee660 BH |
2370 | } |
2371 | ||
eb9f6744 BH |
2372 | if (!ok) |
2373 | goto fail; | |
2374 | ||
4b988280 | 2375 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2376 | rc = efx->phy_op->init(efx); |
2377 | if (rc) | |
2378 | goto fail; | |
2379 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2380 | netif_err(efx, drv, efx->net_dev, |
2381 | "could not restore PHY settings\n"); | |
4b988280 SH |
2382 | } |
2383 | ||
261e4d96 JC |
2384 | rc = efx_enable_interrupts(efx); |
2385 | if (rc) | |
2386 | goto fail; | |
64eebcfd | 2387 | efx_restore_filters(efx); |
cd2d5b52 | 2388 | efx_sriov_reset(efx); |
eb9f6744 | 2389 | |
eb9f6744 BH |
2390 | mutex_unlock(&efx->mac_lock); |
2391 | ||
2392 | efx_start_all(efx); | |
2393 | ||
2394 | return 0; | |
2395 | ||
2396 | fail: | |
2397 | efx->port_initialized = false; | |
2467ca46 BH |
2398 | |
2399 | mutex_unlock(&efx->mac_lock); | |
2400 | ||
8ceee660 BH |
2401 | return rc; |
2402 | } | |
2403 | ||
eb9f6744 BH |
2404 | /* Reset the NIC using the specified method. Note that the reset may |
2405 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2406 | * |
eb9f6744 | 2407 | * Caller must hold the rtnl_lock. |
8ceee660 | 2408 | */ |
eb9f6744 | 2409 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2410 | { |
eb9f6744 BH |
2411 | int rc, rc2; |
2412 | bool disabled; | |
8ceee660 | 2413 | |
62776d03 BH |
2414 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2415 | RESET_TYPE(method)); | |
8ceee660 | 2416 | |
c2f3b8e3 | 2417 | efx_device_detach_sync(efx); |
d3245b28 | 2418 | efx_reset_down(efx, method); |
8ceee660 | 2419 | |
ef2b90ee | 2420 | rc = efx->type->reset(efx, method); |
8ceee660 | 2421 | if (rc) { |
62776d03 | 2422 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2423 | goto out; |
8ceee660 BH |
2424 | } |
2425 | ||
a7d529ae BH |
2426 | /* Clear flags for the scopes we covered. We assume the NIC and |
2427 | * driver are now quiescent so that there is no race here. | |
2428 | */ | |
e283546c EC |
2429 | if (method < RESET_TYPE_MAX_METHOD) |
2430 | efx->reset_pending &= -(1 << (method + 1)); | |
2431 | else /* it doesn't fit into the well-ordered scope hierarchy */ | |
2432 | __clear_bit(method, &efx->reset_pending); | |
8ceee660 BH |
2433 | |
2434 | /* Reinitialise bus-mastering, which may have been turned off before | |
2435 | * the reset was scheduled. This is still appropriate, even in the | |
2436 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2437 | * can respond to requests. */ | |
2438 | pci_set_master(efx->pci_dev); | |
2439 | ||
eb9f6744 | 2440 | out: |
8ceee660 | 2441 | /* Leave device stopped if necessary */ |
626950db AR |
2442 | disabled = rc || |
2443 | method == RESET_TYPE_DISABLE || | |
2444 | method == RESET_TYPE_RECOVER_OR_DISABLE; | |
eb9f6744 BH |
2445 | rc2 = efx_reset_up(efx, method, !disabled); |
2446 | if (rc2) { | |
2447 | disabled = true; | |
2448 | if (!rc) | |
2449 | rc = rc2; | |
8ceee660 BH |
2450 | } |
2451 | ||
eb9f6744 | 2452 | if (disabled) { |
f49a4589 | 2453 | dev_close(efx->net_dev); |
62776d03 | 2454 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2455 | efx->state = STATE_DISABLED; |
f4bd954e | 2456 | } else { |
62776d03 | 2457 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2458 | netif_device_attach(efx->net_dev); |
f4bd954e | 2459 | } |
8ceee660 BH |
2460 | return rc; |
2461 | } | |
2462 | ||
626950db AR |
2463 | /* Try recovery mechanisms. |
2464 | * For now only EEH is supported. | |
2465 | * Returns 0 if the recovery mechanisms are unsuccessful. | |
2466 | * Returns a non-zero value otherwise. | |
2467 | */ | |
b28405b0 | 2468 | int efx_try_recovery(struct efx_nic *efx) |
626950db AR |
2469 | { |
2470 | #ifdef CONFIG_EEH | |
2471 | /* A PCI error can occur and not be seen by EEH because nothing | |
2472 | * happens on the PCI bus. In this case the driver may fail and | |
2473 | * schedule a 'recover or reset', leading to this recovery handler. | |
2474 | * Manually call the eeh failure check function. | |
2475 | */ | |
2476 | struct eeh_dev *eehdev = | |
2477 | of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev)); | |
2478 | ||
2479 | if (eeh_dev_check_failure(eehdev)) { | |
2480 | /* The EEH mechanisms will handle the error and reset the | |
2481 | * device if necessary. | |
2482 | */ | |
2483 | return 1; | |
2484 | } | |
2485 | #endif | |
2486 | return 0; | |
2487 | } | |
2488 | ||
74cd60a4 JC |
2489 | static void efx_wait_for_bist_end(struct efx_nic *efx) |
2490 | { | |
2491 | int i; | |
2492 | ||
2493 | for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) { | |
2494 | if (efx_mcdi_poll_reboot(efx)) | |
2495 | goto out; | |
2496 | msleep(BIST_WAIT_DELAY_MS); | |
2497 | } | |
2498 | ||
2499 | netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n"); | |
2500 | out: | |
2501 | /* Either way unset the BIST flag. If we found no reboot we probably | |
2502 | * won't recover, but we should try. | |
2503 | */ | |
2504 | efx->mc_bist_for_other_fn = false; | |
2505 | } | |
2506 | ||
8ceee660 BH |
2507 | /* The worker thread exists so that code that cannot sleep can |
2508 | * schedule a reset for later. | |
2509 | */ | |
2510 | static void efx_reset_work(struct work_struct *data) | |
2511 | { | |
eb9f6744 | 2512 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
626950db AR |
2513 | unsigned long pending; |
2514 | enum reset_type method; | |
2515 | ||
2516 | pending = ACCESS_ONCE(efx->reset_pending); | |
2517 | method = fls(pending) - 1; | |
2518 | ||
74cd60a4 JC |
2519 | if (method == RESET_TYPE_MC_BIST) |
2520 | efx_wait_for_bist_end(efx); | |
2521 | ||
626950db AR |
2522 | if ((method == RESET_TYPE_RECOVER_OR_DISABLE || |
2523 | method == RESET_TYPE_RECOVER_OR_ALL) && | |
2524 | efx_try_recovery(efx)) | |
2525 | return; | |
8ceee660 | 2526 | |
a7d529ae | 2527 | if (!pending) |
319ba649 SH |
2528 | return; |
2529 | ||
eb9f6744 | 2530 | rtnl_lock(); |
7153f623 BH |
2531 | |
2532 | /* We checked the state in efx_schedule_reset() but it may | |
2533 | * have changed by now. Now that we have the RTNL lock, | |
2534 | * it cannot change again. | |
2535 | */ | |
2536 | if (efx->state == STATE_READY) | |
626950db | 2537 | (void)efx_reset(efx, method); |
7153f623 | 2538 | |
eb9f6744 | 2539 | rtnl_unlock(); |
8ceee660 BH |
2540 | } |
2541 | ||
2542 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2543 | { | |
2544 | enum reset_type method; | |
2545 | ||
626950db AR |
2546 | if (efx->state == STATE_RECOVERY) { |
2547 | netif_dbg(efx, drv, efx->net_dev, | |
2548 | "recovering: skip scheduling %s reset\n", | |
2549 | RESET_TYPE(type)); | |
2550 | return; | |
2551 | } | |
2552 | ||
8ceee660 BH |
2553 | switch (type) { |
2554 | case RESET_TYPE_INVISIBLE: | |
2555 | case RESET_TYPE_ALL: | |
626950db | 2556 | case RESET_TYPE_RECOVER_OR_ALL: |
8ceee660 BH |
2557 | case RESET_TYPE_WORLD: |
2558 | case RESET_TYPE_DISABLE: | |
626950db | 2559 | case RESET_TYPE_RECOVER_OR_DISABLE: |
74cd60a4 | 2560 | case RESET_TYPE_MC_BIST: |
e283546c | 2561 | case RESET_TYPE_MCDI_TIMEOUT: |
8ceee660 | 2562 | method = type; |
0e2a9c7c BH |
2563 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2564 | RESET_TYPE(method)); | |
8ceee660 | 2565 | break; |
8ceee660 | 2566 | default: |
0e2a9c7c | 2567 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2568 | netif_dbg(efx, drv, efx->net_dev, |
2569 | "scheduling %s reset for %s\n", | |
2570 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2571 | break; |
2572 | } | |
8ceee660 | 2573 | |
a7d529ae | 2574 | set_bit(method, &efx->reset_pending); |
7153f623 BH |
2575 | smp_mb(); /* ensure we change reset_pending before checking state */ |
2576 | ||
2577 | /* If we're not READY then just leave the flags set as the cue | |
2578 | * to abort probing or reschedule the reset later. | |
2579 | */ | |
2580 | if (ACCESS_ONCE(efx->state) != STATE_READY) | |
2581 | return; | |
8ceee660 | 2582 | |
8880f4ec BH |
2583 | /* efx_process_channel() will no longer read events once a |
2584 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2585 | efx_mcdi_mode_poll(efx); | |
2586 | ||
1ab00629 | 2587 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2588 | } |
2589 | ||
2590 | /************************************************************************** | |
2591 | * | |
2592 | * List of NICs we support | |
2593 | * | |
2594 | **************************************************************************/ | |
2595 | ||
2596 | /* PCI device ID table */ | |
a3aa1884 | 2597 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2598 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2599 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2600 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2601 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2602 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2603 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2604 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2605 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2606 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2607 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8127d661 BH |
2608 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */ |
2609 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
8ceee660 BH |
2610 | {0} /* end of list */ |
2611 | }; | |
2612 | ||
2613 | /************************************************************************** | |
2614 | * | |
3759433d | 2615 | * Dummy PHY/MAC operations |
8ceee660 | 2616 | * |
01aad7b6 | 2617 | * Can be used for some unimplemented operations |
8ceee660 BH |
2618 | * Needed so all function pointers are valid and do not have to be tested |
2619 | * before use | |
2620 | * | |
2621 | **************************************************************************/ | |
2622 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2623 | { | |
2624 | return 0; | |
2625 | } | |
2626 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2627 | |
2628 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2629 | { |
2630 | return false; | |
2631 | } | |
8ceee660 | 2632 | |
6c8c2513 | 2633 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2634 | .init = efx_port_dummy_op_int, |
d3245b28 | 2635 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2636 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2637 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2638 | }; |
2639 | ||
8ceee660 BH |
2640 | /************************************************************************** |
2641 | * | |
2642 | * Data housekeeping | |
2643 | * | |
2644 | **************************************************************************/ | |
2645 | ||
2646 | /* This zeroes out and then fills in the invariants in a struct | |
2647 | * efx_nic (including all sub-structures). | |
2648 | */ | |
adeb15aa | 2649 | static int efx_init_struct(struct efx_nic *efx, |
8ceee660 BH |
2650 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2651 | { | |
4642610c | 2652 | int i; |
8ceee660 BH |
2653 | |
2654 | /* Initialise common structures */ | |
0bcf4a64 BH |
2655 | INIT_LIST_HEAD(&efx->node); |
2656 | INIT_LIST_HEAD(&efx->secondary_list); | |
8ceee660 | 2657 | spin_lock_init(&efx->biu_lock); |
76884835 BH |
2658 | #ifdef CONFIG_SFC_MTD |
2659 | INIT_LIST_HEAD(&efx->mtd_list); | |
2660 | #endif | |
8ceee660 BH |
2661 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2662 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
dd40781e | 2663 | INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); |
8ceee660 | 2664 | efx->pci_dev = pci_dev; |
62776d03 | 2665 | efx->msg_enable = debug; |
f16aeea0 | 2666 | efx->state = STATE_UNINIT; |
8ceee660 | 2667 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2668 | |
2669 | efx->net_dev = net_dev; | |
43a3739d | 2670 | efx->rx_prefix_size = efx->type->rx_prefix_size; |
2ec03014 AR |
2671 | efx->rx_ip_align = |
2672 | NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0; | |
43a3739d JC |
2673 | efx->rx_packet_hash_offset = |
2674 | efx->type->rx_hash_offset - efx->type->rx_prefix_size; | |
bd9a265d JC |
2675 | efx->rx_packet_ts_offset = |
2676 | efx->type->rx_ts_offset - efx->type->rx_prefix_size; | |
8ceee660 BH |
2677 | spin_lock_init(&efx->stats_lock); |
2678 | mutex_init(&efx->mac_lock); | |
2679 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2680 | efx->mdio.dev = net_dev; |
766ca0fa | 2681 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2682 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2683 | |
2684 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2685 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2686 | if (!efx->channel[i]) | |
2687 | goto fail; | |
d8291187 BH |
2688 | efx->msi_context[i].efx = efx; |
2689 | efx->msi_context[i].index = i; | |
8ceee660 BH |
2690 | } |
2691 | ||
8ceee660 BH |
2692 | /* Higher numbered interrupt modes are less capable! */ |
2693 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2694 | interrupt_mode); | |
2695 | ||
6977dc63 BH |
2696 | /* Would be good to use the net_dev name, but we're too early */ |
2697 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2698 | pci_name(pci_dev)); | |
2699 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2700 | if (!efx->workqueue) |
4642610c | 2701 | goto fail; |
8d9853d9 | 2702 | |
8ceee660 | 2703 | return 0; |
4642610c BH |
2704 | |
2705 | fail: | |
2706 | efx_fini_struct(efx); | |
2707 | return -ENOMEM; | |
8ceee660 BH |
2708 | } |
2709 | ||
2710 | static void efx_fini_struct(struct efx_nic *efx) | |
2711 | { | |
8313aca3 BH |
2712 | int i; |
2713 | ||
2714 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2715 | kfree(efx->channel[i]); | |
2716 | ||
ef215e64 BH |
2717 | kfree(efx->vpd_sn); |
2718 | ||
8ceee660 BH |
2719 | if (efx->workqueue) { |
2720 | destroy_workqueue(efx->workqueue); | |
2721 | efx->workqueue = NULL; | |
2722 | } | |
2723 | } | |
2724 | ||
2725 | /************************************************************************** | |
2726 | * | |
2727 | * PCI interface | |
2728 | * | |
2729 | **************************************************************************/ | |
2730 | ||
2731 | /* Main body of final NIC shutdown code | |
2732 | * This is called only at module unload (or hotplug removal). | |
2733 | */ | |
2734 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2735 | { | |
7153f623 BH |
2736 | /* Flush reset_work. It can no longer be scheduled since we |
2737 | * are not READY. | |
2738 | */ | |
2739 | BUG_ON(efx->state == STATE_READY); | |
2740 | cancel_work_sync(&efx->reset_work); | |
2741 | ||
d8291187 | 2742 | efx_disable_interrupts(efx); |
152b6a62 | 2743 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2744 | efx_fini_port(efx); |
ef2b90ee | 2745 | efx->type->fini(efx); |
8ceee660 BH |
2746 | efx_fini_napi(efx); |
2747 | efx_remove_all(efx); | |
2748 | } | |
2749 | ||
2750 | /* Final NIC shutdown | |
2751 | * This is called only at module unload (or hotplug removal). | |
2752 | */ | |
2753 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2754 | { | |
2755 | struct efx_nic *efx; | |
2756 | ||
2757 | efx = pci_get_drvdata(pci_dev); | |
2758 | if (!efx) | |
2759 | return; | |
2760 | ||
2761 | /* Mark the NIC as fini, then stop the interface */ | |
2762 | rtnl_lock(); | |
0bcf4a64 | 2763 | efx_dissociate(efx); |
8ceee660 | 2764 | dev_close(efx->net_dev); |
d8291187 | 2765 | efx_disable_interrupts(efx); |
8ceee660 BH |
2766 | rtnl_unlock(); |
2767 | ||
cd2d5b52 | 2768 | efx_sriov_fini(efx); |
8ceee660 BH |
2769 | efx_unregister_netdev(efx); |
2770 | ||
7dde596e BH |
2771 | efx_mtd_remove(efx); |
2772 | ||
8ceee660 BH |
2773 | efx_pci_remove_main(efx); |
2774 | ||
8ceee660 | 2775 | efx_fini_io(efx); |
62776d03 | 2776 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 | 2777 | |
8ceee660 BH |
2778 | efx_fini_struct(efx); |
2779 | free_netdev(efx->net_dev); | |
626950db AR |
2780 | |
2781 | pci_disable_pcie_error_reporting(pci_dev); | |
8ceee660 BH |
2782 | }; |
2783 | ||
460eeaa0 BH |
2784 | /* NIC VPD information |
2785 | * Called during probe to display the part number of the | |
2786 | * installed NIC. VPD is potentially very large but this should | |
2787 | * always appear within the first 512 bytes. | |
2788 | */ | |
2789 | #define SFC_VPD_LEN 512 | |
ef215e64 | 2790 | static void efx_probe_vpd_strings(struct efx_nic *efx) |
460eeaa0 BH |
2791 | { |
2792 | struct pci_dev *dev = efx->pci_dev; | |
2793 | char vpd_data[SFC_VPD_LEN]; | |
2794 | ssize_t vpd_size; | |
ef215e64 | 2795 | int ro_start, ro_size, i, j; |
460eeaa0 BH |
2796 | |
2797 | /* Get the vpd data from the device */ | |
2798 | vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); | |
2799 | if (vpd_size <= 0) { | |
2800 | netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); | |
2801 | return; | |
2802 | } | |
2803 | ||
2804 | /* Get the Read only section */ | |
ef215e64 BH |
2805 | ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); |
2806 | if (ro_start < 0) { | |
460eeaa0 BH |
2807 | netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); |
2808 | return; | |
2809 | } | |
2810 | ||
ef215e64 BH |
2811 | ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); |
2812 | j = ro_size; | |
2813 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
460eeaa0 BH |
2814 | if (i + j > vpd_size) |
2815 | j = vpd_size - i; | |
2816 | ||
2817 | /* Get the Part number */ | |
2818 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); | |
2819 | if (i < 0) { | |
2820 | netif_err(efx, drv, efx->net_dev, "Part number not found\n"); | |
2821 | return; | |
2822 | } | |
2823 | ||
2824 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2825 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2826 | if (i + j > vpd_size) { | |
2827 | netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); | |
2828 | return; | |
2829 | } | |
2830 | ||
2831 | netif_info(efx, drv, efx->net_dev, | |
2832 | "Part Number : %.*s\n", j, &vpd_data[i]); | |
ef215e64 BH |
2833 | |
2834 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
2835 | j = ro_size; | |
2836 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN"); | |
2837 | if (i < 0) { | |
2838 | netif_err(efx, drv, efx->net_dev, "Serial number not found\n"); | |
2839 | return; | |
2840 | } | |
2841 | ||
2842 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2843 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2844 | if (i + j > vpd_size) { | |
2845 | netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n"); | |
2846 | return; | |
2847 | } | |
2848 | ||
2849 | efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL); | |
2850 | if (!efx->vpd_sn) | |
2851 | return; | |
2852 | ||
2853 | snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]); | |
460eeaa0 BH |
2854 | } |
2855 | ||
2856 | ||
8ceee660 BH |
2857 | /* Main body of NIC initialisation |
2858 | * This is called at module load (or hotplug insertion, theoretically). | |
2859 | */ | |
2860 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2861 | { | |
2862 | int rc; | |
2863 | ||
2864 | /* Do start-of-day initialisation */ | |
2865 | rc = efx_probe_all(efx); | |
2866 | if (rc) | |
2867 | goto fail1; | |
2868 | ||
e8f14992 | 2869 | efx_init_napi(efx); |
8ceee660 | 2870 | |
ef2b90ee | 2871 | rc = efx->type->init(efx); |
8ceee660 | 2872 | if (rc) { |
62776d03 BH |
2873 | netif_err(efx, probe, efx->net_dev, |
2874 | "failed to initialise NIC\n"); | |
278c0621 | 2875 | goto fail3; |
8ceee660 BH |
2876 | } |
2877 | ||
2878 | rc = efx_init_port(efx); | |
2879 | if (rc) { | |
62776d03 BH |
2880 | netif_err(efx, probe, efx->net_dev, |
2881 | "failed to initialise port\n"); | |
278c0621 | 2882 | goto fail4; |
8ceee660 BH |
2883 | } |
2884 | ||
152b6a62 | 2885 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2886 | if (rc) |
278c0621 | 2887 | goto fail5; |
261e4d96 JC |
2888 | rc = efx_enable_interrupts(efx); |
2889 | if (rc) | |
2890 | goto fail6; | |
8ceee660 BH |
2891 | |
2892 | return 0; | |
2893 | ||
261e4d96 JC |
2894 | fail6: |
2895 | efx_nic_fini_interrupt(efx); | |
278c0621 | 2896 | fail5: |
8ceee660 | 2897 | efx_fini_port(efx); |
8ceee660 | 2898 | fail4: |
ef2b90ee | 2899 | efx->type->fini(efx); |
8ceee660 BH |
2900 | fail3: |
2901 | efx_fini_napi(efx); | |
8ceee660 BH |
2902 | efx_remove_all(efx); |
2903 | fail1: | |
2904 | return rc; | |
2905 | } | |
2906 | ||
2907 | /* NIC initialisation | |
2908 | * | |
2909 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2910 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2911 | * sets up and registers the network devices with the kernel and hooks |
2912 | * the interrupt service routine. It does not prepare the device for | |
2913 | * transmission; this is left to the first time one of the network | |
2914 | * interfaces is brought up (i.e. efx_net_open). | |
2915 | */ | |
87d1fc11 | 2916 | static int efx_pci_probe(struct pci_dev *pci_dev, |
1dd06ae8 | 2917 | const struct pci_device_id *entry) |
8ceee660 | 2918 | { |
8ceee660 BH |
2919 | struct net_device *net_dev; |
2920 | struct efx_nic *efx; | |
fadac6aa | 2921 | int rc; |
8ceee660 BH |
2922 | |
2923 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2924 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2925 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2926 | if (!net_dev) |
2927 | return -ENOMEM; | |
adeb15aa BH |
2928 | efx = netdev_priv(net_dev); |
2929 | efx->type = (const struct efx_nic_type *) entry->driver_data; | |
2930 | net_dev->features |= (efx->type->offload_features | NETIF_F_SG | | |
97bc5415 | 2931 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2932 | NETIF_F_RXCSUM); |
adeb15aa | 2933 | if (efx->type->offload_features & NETIF_F_V6_CSUM) |
738a8f4b | 2934 | net_dev->features |= NETIF_F_TSO6; |
28506563 BH |
2935 | /* Mask for features that also apply to VLAN devices */ |
2936 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2937 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2938 | NETIF_F_RXCSUM); | |
2939 | /* All offloads can be toggled */ | |
2940 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
8ceee660 | 2941 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2942 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
adeb15aa | 2943 | rc = efx_init_struct(efx, pci_dev, net_dev); |
8ceee660 BH |
2944 | if (rc) |
2945 | goto fail1; | |
2946 | ||
62776d03 | 2947 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2948 | "Solarflare NIC detected\n"); |
8ceee660 | 2949 | |
ef215e64 | 2950 | efx_probe_vpd_strings(efx); |
460eeaa0 | 2951 | |
8ceee660 BH |
2952 | /* Set up basic I/O (BAR mappings etc) */ |
2953 | rc = efx_init_io(efx); | |
2954 | if (rc) | |
2955 | goto fail2; | |
2956 | ||
fadac6aa | 2957 | rc = efx_pci_probe_main(efx); |
fadac6aa BH |
2958 | if (rc) |
2959 | goto fail3; | |
8ceee660 | 2960 | |
8ceee660 BH |
2961 | rc = efx_register_netdev(efx); |
2962 | if (rc) | |
fadac6aa | 2963 | goto fail4; |
8ceee660 | 2964 | |
cd2d5b52 BH |
2965 | rc = efx_sriov_init(efx); |
2966 | if (rc) | |
2967 | netif_err(efx, probe, efx->net_dev, | |
2968 | "SR-IOV can't be enabled rc %d\n", rc); | |
2969 | ||
62776d03 | 2970 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 2971 | |
7c43161c | 2972 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 2973 | rtnl_lock(); |
7c43161c | 2974 | rc = efx_mtd_probe(efx); |
a5211bb5 | 2975 | rtnl_unlock(); |
7c43161c BH |
2976 | if (rc) |
2977 | netif_warn(efx, probe, efx->net_dev, | |
2978 | "failed to create MTDs (%d)\n", rc); | |
2979 | ||
626950db AR |
2980 | rc = pci_enable_pcie_error_reporting(pci_dev); |
2981 | if (rc && rc != -EINVAL) | |
2982 | netif_warn(efx, probe, efx->net_dev, | |
2983 | "pci_enable_pcie_error_reporting failed (%d)\n", rc); | |
2984 | ||
8ceee660 BH |
2985 | return 0; |
2986 | ||
8ceee660 | 2987 | fail4: |
fadac6aa | 2988 | efx_pci_remove_main(efx); |
8ceee660 BH |
2989 | fail3: |
2990 | efx_fini_io(efx); | |
2991 | fail2: | |
2992 | efx_fini_struct(efx); | |
2993 | fail1: | |
5e2a911c | 2994 | WARN_ON(rc > 0); |
62776d03 | 2995 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2996 | free_netdev(net_dev); |
2997 | return rc; | |
2998 | } | |
2999 | ||
89c758fa BH |
3000 | static int efx_pm_freeze(struct device *dev) |
3001 | { | |
3002 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
3003 | ||
61da026d BH |
3004 | rtnl_lock(); |
3005 | ||
6032fb56 BH |
3006 | if (efx->state != STATE_DISABLED) { |
3007 | efx->state = STATE_UNINIT; | |
89c758fa | 3008 | |
c2f3b8e3 | 3009 | efx_device_detach_sync(efx); |
89c758fa | 3010 | |
6032fb56 | 3011 | efx_stop_all(efx); |
d8291187 | 3012 | efx_disable_interrupts(efx); |
6032fb56 | 3013 | } |
89c758fa | 3014 | |
61da026d BH |
3015 | rtnl_unlock(); |
3016 | ||
89c758fa BH |
3017 | return 0; |
3018 | } | |
3019 | ||
3020 | static int efx_pm_thaw(struct device *dev) | |
3021 | { | |
261e4d96 | 3022 | int rc; |
89c758fa BH |
3023 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); |
3024 | ||
61da026d BH |
3025 | rtnl_lock(); |
3026 | ||
6032fb56 | 3027 | if (efx->state != STATE_DISABLED) { |
261e4d96 JC |
3028 | rc = efx_enable_interrupts(efx); |
3029 | if (rc) | |
3030 | goto fail; | |
89c758fa | 3031 | |
6032fb56 BH |
3032 | mutex_lock(&efx->mac_lock); |
3033 | efx->phy_op->reconfigure(efx); | |
3034 | mutex_unlock(&efx->mac_lock); | |
89c758fa | 3035 | |
6032fb56 | 3036 | efx_start_all(efx); |
89c758fa | 3037 | |
6032fb56 | 3038 | netif_device_attach(efx->net_dev); |
89c758fa | 3039 | |
6032fb56 | 3040 | efx->state = STATE_READY; |
89c758fa | 3041 | |
6032fb56 BH |
3042 | efx->type->resume_wol(efx); |
3043 | } | |
89c758fa | 3044 | |
61da026d BH |
3045 | rtnl_unlock(); |
3046 | ||
319ba649 SH |
3047 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
3048 | queue_work(reset_workqueue, &efx->reset_work); | |
3049 | ||
89c758fa | 3050 | return 0; |
261e4d96 JC |
3051 | |
3052 | fail: | |
3053 | rtnl_unlock(); | |
3054 | ||
3055 | return rc; | |
89c758fa BH |
3056 | } |
3057 | ||
3058 | static int efx_pm_poweroff(struct device *dev) | |
3059 | { | |
3060 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
3061 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
3062 | ||
3063 | efx->type->fini(efx); | |
3064 | ||
a7d529ae | 3065 | efx->reset_pending = 0; |
89c758fa BH |
3066 | |
3067 | pci_save_state(pci_dev); | |
3068 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
3069 | } | |
3070 | ||
3071 | /* Used for both resume and restore */ | |
3072 | static int efx_pm_resume(struct device *dev) | |
3073 | { | |
3074 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
3075 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
3076 | int rc; | |
3077 | ||
3078 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
3079 | if (rc) | |
3080 | return rc; | |
3081 | pci_restore_state(pci_dev); | |
3082 | rc = pci_enable_device(pci_dev); | |
3083 | if (rc) | |
3084 | return rc; | |
3085 | pci_set_master(efx->pci_dev); | |
3086 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
3087 | if (rc) | |
3088 | return rc; | |
3089 | rc = efx->type->init(efx); | |
3090 | if (rc) | |
3091 | return rc; | |
261e4d96 JC |
3092 | rc = efx_pm_thaw(dev); |
3093 | return rc; | |
89c758fa BH |
3094 | } |
3095 | ||
3096 | static int efx_pm_suspend(struct device *dev) | |
3097 | { | |
3098 | int rc; | |
3099 | ||
3100 | efx_pm_freeze(dev); | |
3101 | rc = efx_pm_poweroff(dev); | |
3102 | if (rc) | |
3103 | efx_pm_resume(dev); | |
3104 | return rc; | |
3105 | } | |
3106 | ||
18e83e4c | 3107 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
3108 | .suspend = efx_pm_suspend, |
3109 | .resume = efx_pm_resume, | |
3110 | .freeze = efx_pm_freeze, | |
3111 | .thaw = efx_pm_thaw, | |
3112 | .poweroff = efx_pm_poweroff, | |
3113 | .restore = efx_pm_resume, | |
3114 | }; | |
3115 | ||
626950db AR |
3116 | /* A PCI error affecting this device was detected. |
3117 | * At this point MMIO and DMA may be disabled. | |
3118 | * Stop the software path and request a slot reset. | |
3119 | */ | |
debd0034 | 3120 | static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev, |
3121 | enum pci_channel_state state) | |
626950db AR |
3122 | { |
3123 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3124 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3125 | ||
3126 | if (state == pci_channel_io_perm_failure) | |
3127 | return PCI_ERS_RESULT_DISCONNECT; | |
3128 | ||
3129 | rtnl_lock(); | |
3130 | ||
3131 | if (efx->state != STATE_DISABLED) { | |
3132 | efx->state = STATE_RECOVERY; | |
3133 | efx->reset_pending = 0; | |
3134 | ||
3135 | efx_device_detach_sync(efx); | |
3136 | ||
3137 | efx_stop_all(efx); | |
d8291187 | 3138 | efx_disable_interrupts(efx); |
626950db AR |
3139 | |
3140 | status = PCI_ERS_RESULT_NEED_RESET; | |
3141 | } else { | |
3142 | /* If the interface is disabled we don't want to do anything | |
3143 | * with it. | |
3144 | */ | |
3145 | status = PCI_ERS_RESULT_RECOVERED; | |
3146 | } | |
3147 | ||
3148 | rtnl_unlock(); | |
3149 | ||
3150 | pci_disable_device(pdev); | |
3151 | ||
3152 | return status; | |
3153 | } | |
3154 | ||
3155 | /* Fake a successfull reset, which will be performed later in efx_io_resume. */ | |
debd0034 | 3156 | static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev) |
626950db AR |
3157 | { |
3158 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3159 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3160 | int rc; | |
3161 | ||
3162 | if (pci_enable_device(pdev)) { | |
3163 | netif_err(efx, hw, efx->net_dev, | |
3164 | "Cannot re-enable PCI device after reset.\n"); | |
3165 | status = PCI_ERS_RESULT_DISCONNECT; | |
3166 | } | |
3167 | ||
3168 | rc = pci_cleanup_aer_uncorrect_error_status(pdev); | |
3169 | if (rc) { | |
3170 | netif_err(efx, hw, efx->net_dev, | |
3171 | "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc); | |
3172 | /* Non-fatal error. Continue. */ | |
3173 | } | |
3174 | ||
3175 | return status; | |
3176 | } | |
3177 | ||
3178 | /* Perform the actual reset and resume I/O operations. */ | |
3179 | static void efx_io_resume(struct pci_dev *pdev) | |
3180 | { | |
3181 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3182 | int rc; | |
3183 | ||
3184 | rtnl_lock(); | |
3185 | ||
3186 | if (efx->state == STATE_DISABLED) | |
3187 | goto out; | |
3188 | ||
3189 | rc = efx_reset(efx, RESET_TYPE_ALL); | |
3190 | if (rc) { | |
3191 | netif_err(efx, hw, efx->net_dev, | |
3192 | "efx_reset failed after PCI error (%d)\n", rc); | |
3193 | } else { | |
3194 | efx->state = STATE_READY; | |
3195 | netif_dbg(efx, hw, efx->net_dev, | |
3196 | "Done resetting and resuming IO after PCI error.\n"); | |
3197 | } | |
3198 | ||
3199 | out: | |
3200 | rtnl_unlock(); | |
3201 | } | |
3202 | ||
3203 | /* For simplicity and reliability, we always require a slot reset and try to | |
3204 | * reset the hardware when a pci error affecting the device is detected. | |
3205 | * We leave both the link_reset and mmio_enabled callback unimplemented: | |
3206 | * with our request for slot reset the mmio_enabled callback will never be | |
3207 | * called, and the link_reset callback is not used by AER or EEH mechanisms. | |
3208 | */ | |
3209 | static struct pci_error_handlers efx_err_handlers = { | |
3210 | .error_detected = efx_io_error_detected, | |
3211 | .slot_reset = efx_io_slot_reset, | |
3212 | .resume = efx_io_resume, | |
3213 | }; | |
3214 | ||
8ceee660 | 3215 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 3216 | .name = KBUILD_MODNAME, |
8ceee660 BH |
3217 | .id_table = efx_pci_table, |
3218 | .probe = efx_pci_probe, | |
3219 | .remove = efx_pci_remove, | |
89c758fa | 3220 | .driver.pm = &efx_pm_ops, |
626950db | 3221 | .err_handler = &efx_err_handlers, |
8ceee660 BH |
3222 | }; |
3223 | ||
3224 | /************************************************************************** | |
3225 | * | |
3226 | * Kernel module interface | |
3227 | * | |
3228 | *************************************************************************/ | |
3229 | ||
3230 | module_param(interrupt_mode, uint, 0444); | |
3231 | MODULE_PARM_DESC(interrupt_mode, | |
3232 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
3233 | ||
3234 | static int __init efx_init_module(void) | |
3235 | { | |
3236 | int rc; | |
3237 | ||
3238 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
3239 | ||
3240 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
3241 | if (rc) | |
3242 | goto err_notifier; | |
3243 | ||
cd2d5b52 BH |
3244 | rc = efx_init_sriov(); |
3245 | if (rc) | |
3246 | goto err_sriov; | |
3247 | ||
1ab00629 SH |
3248 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
3249 | if (!reset_workqueue) { | |
3250 | rc = -ENOMEM; | |
3251 | goto err_reset; | |
3252 | } | |
8ceee660 BH |
3253 | |
3254 | rc = pci_register_driver(&efx_pci_driver); | |
3255 | if (rc < 0) | |
3256 | goto err_pci; | |
3257 | ||
3258 | return 0; | |
3259 | ||
3260 | err_pci: | |
1ab00629 SH |
3261 | destroy_workqueue(reset_workqueue); |
3262 | err_reset: | |
cd2d5b52 BH |
3263 | efx_fini_sriov(); |
3264 | err_sriov: | |
8ceee660 BH |
3265 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3266 | err_notifier: | |
3267 | return rc; | |
3268 | } | |
3269 | ||
3270 | static void __exit efx_exit_module(void) | |
3271 | { | |
3272 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
3273 | ||
3274 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 3275 | destroy_workqueue(reset_workqueue); |
cd2d5b52 | 3276 | efx_fini_sriov(); |
8ceee660 BH |
3277 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3278 | ||
3279 | } | |
3280 | ||
3281 | module_init(efx_init_module); | |
3282 | module_exit(efx_exit_module); | |
3283 | ||
906bb26c BH |
3284 | MODULE_AUTHOR("Solarflare Communications and " |
3285 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
6a350fdb | 3286 | MODULE_DESCRIPTION("Solarflare network driver"); |
8ceee660 BH |
3287 | MODULE_LICENSE("GPL"); |
3288 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |