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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
64d8ad6d | 24 | #include <linux/cpu_rmap.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 41 | const char *const efx_loopback_mode_names[] = { |
c459302d | 42 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
47 | [LOOPBACK_XAUI] = "XAUI", |
48 | [LOOPBACK_GMII] = "GMII", | |
49 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
50 | [LOOPBACK_XGBR] = "XGBR", |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
58 | [LOOPBACK_PCS] = "PCS", |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 65 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
69 | }; |
70 | ||
c459302d | 71 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 72 | const char *const efx_reset_type_names[] = { |
c459302d BH |
73 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
74 | [RESET_TYPE_ALL] = "ALL", | |
75 | [RESET_TYPE_WORLD] = "WORLD", | |
76 | [RESET_TYPE_DISABLE] = "DISABLE", | |
77 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
78 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
79 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
80 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
81 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 83 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
84 | }; |
85 | ||
8ceee660 BH |
86 | #define EFX_MAX_MTU (9 * 1024) |
87 | ||
1ab00629 SH |
88 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
89 | * queued onto this work queue. This is not a per-nic work queue, because | |
90 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
91 | */ | |
92 | static struct workqueue_struct *reset_workqueue; | |
93 | ||
8ceee660 BH |
94 | /************************************************************************** |
95 | * | |
96 | * Configurable values | |
97 | * | |
98 | *************************************************************************/ | |
99 | ||
8ceee660 BH |
100 | /* |
101 | * Use separate channels for TX and RX events | |
102 | * | |
28b581ab NT |
103 | * Set this to 1 to use separate channels for TX and RX. It allows us |
104 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 105 | * |
28b581ab | 106 | * This is only used in MSI-X interrupt mode |
8ceee660 | 107 | */ |
28b581ab | 108 | static unsigned int separate_tx_channels; |
8313aca3 | 109 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
110 | MODULE_PARM_DESC(separate_tx_channels, |
111 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
112 | |
113 | /* This is the weight assigned to each of the (per-channel) virtual | |
114 | * NAPI devices. | |
115 | */ | |
116 | static int napi_weight = 64; | |
117 | ||
118 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
119 | * monitor. On Falcon-based NICs, this will: |
120 | * - Check the on-board hardware monitor; | |
121 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 122 | */ |
d215697f | 123 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 124 | |
8ceee660 BH |
125 | /* Initial interrupt moderation settings. They can be modified after |
126 | * module load with ethtool. | |
127 | * | |
128 | * The default for RX should strike a balance between increasing the | |
129 | * round-trip latency and reducing overhead. | |
130 | */ | |
131 | static unsigned int rx_irq_mod_usec = 60; | |
132 | ||
133 | /* Initial interrupt moderation settings. They can be modified after | |
134 | * module load with ethtool. | |
135 | * | |
136 | * This default is chosen to ensure that a 10G link does not go idle | |
137 | * while a TX queue is stopped after it has become full. A queue is | |
138 | * restarted when it drops below half full. The time this takes (assuming | |
139 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
140 | * 512 / 3 * 1.2 = 205 usec. | |
141 | */ | |
142 | static unsigned int tx_irq_mod_usec = 150; | |
143 | ||
144 | /* This is the first interrupt mode to try out of: | |
145 | * 0 => MSI-X | |
146 | * 1 => MSI | |
147 | * 2 => legacy | |
148 | */ | |
149 | static unsigned int interrupt_mode; | |
150 | ||
151 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
152 | * i.e. the number of CPUs among which we may distribute simultaneous | |
153 | * interrupt handling. | |
154 | * | |
155 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 156 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
157 | */ |
158 | static unsigned int rss_cpus; | |
159 | module_param(rss_cpus, uint, 0444); | |
160 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
161 | ||
84ae48fe BH |
162 | static int phy_flash_cfg; |
163 | module_param(phy_flash_cfg, int, 0644); | |
164 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
165 | ||
6fb70fd1 BH |
166 | static unsigned irq_adapt_low_thresh = 10000; |
167 | module_param(irq_adapt_low_thresh, uint, 0644); | |
168 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
169 | "Threshold score for reducing IRQ moderation"); | |
170 | ||
171 | static unsigned irq_adapt_high_thresh = 20000; | |
172 | module_param(irq_adapt_high_thresh, uint, 0644); | |
173 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
174 | "Threshold score for increasing IRQ moderation"); | |
175 | ||
62776d03 BH |
176 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
177 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
178 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
179 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
180 | module_param(debug, uint, 0); | |
181 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
182 | ||
8ceee660 BH |
183 | /************************************************************************** |
184 | * | |
185 | * Utility functions and prototypes | |
186 | * | |
187 | *************************************************************************/ | |
4642610c | 188 | |
7f967c01 BH |
189 | static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq); |
190 | static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq); | |
191 | static void efx_remove_channel(struct efx_channel *channel); | |
4642610c | 192 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 193 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 194 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 195 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 196 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 197 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
198 | static void efx_fini_struct(struct efx_nic *efx); |
199 | static void efx_start_all(struct efx_nic *efx); | |
200 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
201 | |
202 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
203 | do { \ | |
332c1ce9 BH |
204 | if ((efx->state == STATE_RUNNING) || \ |
205 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
206 | ASSERT_RTNL(); \ |
207 | } while (0) | |
208 | ||
209 | /************************************************************************** | |
210 | * | |
211 | * Event queue processing | |
212 | * | |
213 | *************************************************************************/ | |
214 | ||
215 | /* Process channel's event queue | |
216 | * | |
217 | * This function is responsible for processing the event queue of a | |
218 | * single channel. The caller must guarantee that this function will | |
219 | * never be concurrently called more than once on the same channel, | |
220 | * though different channels may be being processed concurrently. | |
221 | */ | |
fa236e18 | 222 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 223 | { |
fa236e18 | 224 | int spent; |
8ceee660 | 225 | |
9f2cb71c | 226 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 227 | return 0; |
8ceee660 | 228 | |
fa236e18 | 229 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
230 | if (spent && efx_channel_has_rx_queue(channel)) { |
231 | struct efx_rx_queue *rx_queue = | |
232 | efx_channel_get_rx_queue(channel); | |
233 | ||
234 | /* Deliver last RX packet. */ | |
235 | if (channel->rx_pkt) { | |
236 | __efx_rx_packet(channel, channel->rx_pkt); | |
237 | channel->rx_pkt = NULL; | |
238 | } | |
9f2cb71c BH |
239 | if (rx_queue->enabled) { |
240 | efx_rx_strategy(channel); | |
241 | efx_fast_push_rx_descriptors(rx_queue); | |
242 | } | |
8ceee660 BH |
243 | } |
244 | ||
fa236e18 | 245 | return spent; |
8ceee660 BH |
246 | } |
247 | ||
248 | /* Mark channel as finished processing | |
249 | * | |
250 | * Note that since we will not receive further interrupts for this | |
251 | * channel before we finish processing and call the eventq_read_ack() | |
252 | * method, there is no need to use the interrupt hold-off timers. | |
253 | */ | |
254 | static inline void efx_channel_processed(struct efx_channel *channel) | |
255 | { | |
5b9e207c BH |
256 | /* The interrupt handler for this channel may set work_pending |
257 | * as soon as we acknowledge the events we've seen. Make sure | |
258 | * it's cleared before then. */ | |
dc8cfa55 | 259 | channel->work_pending = false; |
5b9e207c BH |
260 | smp_wmb(); |
261 | ||
152b6a62 | 262 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
263 | } |
264 | ||
265 | /* NAPI poll handler | |
266 | * | |
267 | * NAPI guarantees serialisation of polls of the same device, which | |
268 | * provides the guarantee required by efx_process_channel(). | |
269 | */ | |
270 | static int efx_poll(struct napi_struct *napi, int budget) | |
271 | { | |
272 | struct efx_channel *channel = | |
273 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 274 | struct efx_nic *efx = channel->efx; |
fa236e18 | 275 | int spent; |
8ceee660 | 276 | |
62776d03 BH |
277 | netif_vdbg(efx, intr, efx->net_dev, |
278 | "channel %d NAPI poll executing on CPU %d\n", | |
279 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 280 | |
fa236e18 | 281 | spent = efx_process_channel(channel, budget); |
8ceee660 | 282 | |
fa236e18 | 283 | if (spent < budget) { |
9d9a6973 | 284 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
285 | efx->irq_rx_adaptive && |
286 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
287 | if (unlikely(channel->irq_mod_score < |
288 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
289 | if (channel->irq_moderation > 1) { |
290 | channel->irq_moderation -= 1; | |
ef2b90ee | 291 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 292 | } |
6fb70fd1 BH |
293 | } else if (unlikely(channel->irq_mod_score > |
294 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
295 | if (channel->irq_moderation < |
296 | efx->irq_rx_moderation) { | |
297 | channel->irq_moderation += 1; | |
ef2b90ee | 298 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 299 | } |
6fb70fd1 | 300 | } |
6fb70fd1 BH |
301 | channel->irq_count = 0; |
302 | channel->irq_mod_score = 0; | |
303 | } | |
304 | ||
64d8ad6d BH |
305 | efx_filter_rfs_expire(channel); |
306 | ||
8ceee660 | 307 | /* There is no race here; although napi_disable() will |
288379f0 | 308 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
309 | * since efx_channel_processed() will have no effect if |
310 | * interrupts have already been disabled. | |
311 | */ | |
288379f0 | 312 | napi_complete(napi); |
8ceee660 BH |
313 | efx_channel_processed(channel); |
314 | } | |
315 | ||
fa236e18 | 316 | return spent; |
8ceee660 BH |
317 | } |
318 | ||
319 | /* Process the eventq of the specified channel immediately on this CPU | |
320 | * | |
321 | * Disable hardware generated interrupts, wait for any existing | |
322 | * processing to finish, then directly poll (and ack ) the eventq. | |
323 | * Finally reenable NAPI and interrupts. | |
324 | * | |
d4fabcc8 BH |
325 | * This is for use only during a loopback self-test. It must not |
326 | * deliver any packets up the stack as this can result in deadlock. | |
8ceee660 BH |
327 | */ |
328 | void efx_process_channel_now(struct efx_channel *channel) | |
329 | { | |
330 | struct efx_nic *efx = channel->efx; | |
331 | ||
8313aca3 | 332 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 | 333 | BUG_ON(!channel->enabled); |
d4fabcc8 | 334 | BUG_ON(!efx->loopback_selftest); |
8ceee660 BH |
335 | |
336 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 337 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 338 | if (efx->legacy_irq) { |
8ceee660 | 339 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
340 | efx->legacy_irq_enabled = false; |
341 | } | |
64ee3120 | 342 | if (channel->irq) |
8ceee660 BH |
343 | synchronize_irq(channel->irq); |
344 | ||
345 | /* Wait for any NAPI processing to complete */ | |
346 | napi_disable(&channel->napi_str); | |
347 | ||
348 | /* Poll the channel */ | |
ecc910f5 | 349 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
350 | |
351 | /* Ack the eventq. This may cause an interrupt to be generated | |
352 | * when they are reenabled */ | |
353 | efx_channel_processed(channel); | |
354 | ||
355 | napi_enable(&channel->napi_str); | |
94dec6a2 BH |
356 | if (efx->legacy_irq) |
357 | efx->legacy_irq_enabled = true; | |
152b6a62 | 358 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
359 | } |
360 | ||
361 | /* Create event queue | |
362 | * Event queue memory allocations are done only once. If the channel | |
363 | * is reset, the memory buffer will be reused; this guards against | |
364 | * errors during channel reset and also simplifies interrupt handling. | |
365 | */ | |
366 | static int efx_probe_eventq(struct efx_channel *channel) | |
367 | { | |
ecc910f5 SH |
368 | struct efx_nic *efx = channel->efx; |
369 | unsigned long entries; | |
370 | ||
86ee5302 | 371 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 372 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 373 | |
ecc910f5 SH |
374 | /* Build an event queue with room for one event per tx and rx buffer, |
375 | * plus some extra for link state events and MCDI completions. */ | |
376 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
377 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
378 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
379 | ||
152b6a62 | 380 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
381 | } |
382 | ||
383 | /* Prepare channel's event queue */ | |
bc3c90a2 | 384 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 385 | { |
62776d03 BH |
386 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
387 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
388 | |
389 | channel->eventq_read_ptr = 0; | |
390 | ||
152b6a62 | 391 | efx_nic_init_eventq(channel); |
8ceee660 BH |
392 | } |
393 | ||
9f2cb71c BH |
394 | /* Enable event queue processing and NAPI */ |
395 | static void efx_start_eventq(struct efx_channel *channel) | |
396 | { | |
397 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
398 | "chan %d start event queue\n", channel->channel); | |
399 | ||
400 | /* The interrupt handler for this channel may set work_pending | |
401 | * as soon as we enable it. Make sure it's cleared before | |
402 | * then. Similarly, make sure it sees the enabled flag set. | |
403 | */ | |
404 | channel->work_pending = false; | |
405 | channel->enabled = true; | |
406 | smp_wmb(); | |
407 | ||
408 | napi_enable(&channel->napi_str); | |
409 | efx_nic_eventq_read_ack(channel); | |
410 | } | |
411 | ||
412 | /* Disable event queue processing and NAPI */ | |
413 | static void efx_stop_eventq(struct efx_channel *channel) | |
414 | { | |
415 | if (!channel->enabled) | |
416 | return; | |
417 | ||
418 | napi_disable(&channel->napi_str); | |
419 | channel->enabled = false; | |
420 | } | |
421 | ||
8ceee660 BH |
422 | static void efx_fini_eventq(struct efx_channel *channel) |
423 | { | |
62776d03 BH |
424 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
425 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 426 | |
152b6a62 | 427 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
428 | } |
429 | ||
430 | static void efx_remove_eventq(struct efx_channel *channel) | |
431 | { | |
62776d03 BH |
432 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
433 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 434 | |
152b6a62 | 435 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
436 | } |
437 | ||
438 | /************************************************************************** | |
439 | * | |
440 | * Channel handling | |
441 | * | |
442 | *************************************************************************/ | |
443 | ||
7f967c01 | 444 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
445 | static struct efx_channel * |
446 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
447 | { | |
448 | struct efx_channel *channel; | |
449 | struct efx_rx_queue *rx_queue; | |
450 | struct efx_tx_queue *tx_queue; | |
451 | int j; | |
452 | ||
7f967c01 BH |
453 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
454 | if (!channel) | |
455 | return NULL; | |
4642610c | 456 | |
7f967c01 BH |
457 | channel->efx = efx; |
458 | channel->channel = i; | |
459 | channel->type = &efx_default_channel_type; | |
4642610c | 460 | |
7f967c01 BH |
461 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
462 | tx_queue = &channel->tx_queue[j]; | |
463 | tx_queue->efx = efx; | |
464 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
465 | tx_queue->channel = channel; | |
466 | } | |
4642610c | 467 | |
7f967c01 BH |
468 | rx_queue = &channel->rx_queue; |
469 | rx_queue->efx = efx; | |
470 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
471 | (unsigned long)rx_queue); | |
4642610c | 472 | |
7f967c01 BH |
473 | return channel; |
474 | } | |
475 | ||
476 | /* Allocate and initialise a channel structure, copying parameters | |
477 | * (but not resources) from an old channel structure. | |
478 | */ | |
479 | static struct efx_channel * | |
480 | efx_copy_channel(const struct efx_channel *old_channel) | |
481 | { | |
482 | struct efx_channel *channel; | |
483 | struct efx_rx_queue *rx_queue; | |
484 | struct efx_tx_queue *tx_queue; | |
485 | int j; | |
4642610c | 486 | |
7f967c01 BH |
487 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
488 | if (!channel) | |
489 | return NULL; | |
490 | ||
491 | *channel = *old_channel; | |
492 | ||
493 | channel->napi_dev = NULL; | |
494 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 495 | |
7f967c01 BH |
496 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
497 | tx_queue = &channel->tx_queue[j]; | |
498 | if (tx_queue->channel) | |
4642610c | 499 | tx_queue->channel = channel; |
7f967c01 BH |
500 | tx_queue->buffer = NULL; |
501 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
502 | } |
503 | ||
4642610c | 504 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
505 | rx_queue->buffer = NULL; |
506 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
507 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
508 | (unsigned long)rx_queue); | |
509 | ||
510 | return channel; | |
511 | } | |
512 | ||
8ceee660 BH |
513 | static int efx_probe_channel(struct efx_channel *channel) |
514 | { | |
515 | struct efx_tx_queue *tx_queue; | |
516 | struct efx_rx_queue *rx_queue; | |
517 | int rc; | |
518 | ||
62776d03 BH |
519 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
520 | "creating channel %d\n", channel->channel); | |
8ceee660 | 521 | |
7f967c01 BH |
522 | rc = channel->type->pre_probe(channel); |
523 | if (rc) | |
524 | goto fail; | |
525 | ||
8ceee660 BH |
526 | rc = efx_probe_eventq(channel); |
527 | if (rc) | |
7f967c01 | 528 | goto fail; |
8ceee660 BH |
529 | |
530 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
531 | rc = efx_probe_tx_queue(tx_queue); | |
532 | if (rc) | |
7f967c01 | 533 | goto fail; |
8ceee660 BH |
534 | } |
535 | ||
536 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
537 | rc = efx_probe_rx_queue(rx_queue); | |
538 | if (rc) | |
7f967c01 | 539 | goto fail; |
8ceee660 BH |
540 | } |
541 | ||
542 | channel->n_rx_frm_trunc = 0; | |
543 | ||
544 | return 0; | |
545 | ||
7f967c01 BH |
546 | fail: |
547 | efx_remove_channel(channel); | |
8ceee660 BH |
548 | return rc; |
549 | } | |
550 | ||
7f967c01 BH |
551 | static void |
552 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
553 | { | |
554 | struct efx_nic *efx = channel->efx; | |
555 | const char *type; | |
556 | int number; | |
557 | ||
558 | number = channel->channel; | |
559 | if (efx->tx_channel_offset == 0) { | |
560 | type = ""; | |
561 | } else if (channel->channel < efx->tx_channel_offset) { | |
562 | type = "-rx"; | |
563 | } else { | |
564 | type = "-tx"; | |
565 | number -= efx->tx_channel_offset; | |
566 | } | |
567 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
568 | } | |
8ceee660 | 569 | |
56536e9c BH |
570 | static void efx_set_channel_names(struct efx_nic *efx) |
571 | { | |
572 | struct efx_channel *channel; | |
56536e9c | 573 | |
7f967c01 BH |
574 | efx_for_each_channel(channel, efx) |
575 | channel->type->get_name(channel, | |
576 | efx->channel_name[channel->channel], | |
577 | sizeof(efx->channel_name[0])); | |
56536e9c BH |
578 | } |
579 | ||
4642610c BH |
580 | static int efx_probe_channels(struct efx_nic *efx) |
581 | { | |
582 | struct efx_channel *channel; | |
583 | int rc; | |
584 | ||
585 | /* Restart special buffer allocation */ | |
586 | efx->next_buffer_table = 0; | |
587 | ||
588 | efx_for_each_channel(channel, efx) { | |
589 | rc = efx_probe_channel(channel); | |
590 | if (rc) { | |
591 | netif_err(efx, probe, efx->net_dev, | |
592 | "failed to create channel %d\n", | |
593 | channel->channel); | |
594 | goto fail; | |
595 | } | |
596 | } | |
597 | efx_set_channel_names(efx); | |
598 | ||
599 | return 0; | |
600 | ||
601 | fail: | |
602 | efx_remove_channels(efx); | |
603 | return rc; | |
604 | } | |
605 | ||
8ceee660 BH |
606 | /* Channels are shutdown and reinitialised whilst the NIC is running |
607 | * to propagate configuration changes (mtu, checksum offload), or | |
608 | * to clear hardware error conditions | |
609 | */ | |
9f2cb71c | 610 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 BH |
611 | { |
612 | struct efx_tx_queue *tx_queue; | |
613 | struct efx_rx_queue *rx_queue; | |
614 | struct efx_channel *channel; | |
8ceee660 | 615 | |
f7f13b0b BH |
616 | /* Calculate the rx buffer allocation parameters required to |
617 | * support the current MTU, including padding for header | |
618 | * alignment and overruns. | |
619 | */ | |
620 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
621 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 622 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 623 | efx->type->rx_buffer_padding); |
62b330ba SH |
624 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
625 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
626 | |
627 | /* Initialise the channels */ | |
628 | efx_for_each_channel(channel, efx) { | |
bc3c90a2 BH |
629 | efx_for_each_channel_tx_queue(tx_queue, channel) |
630 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
631 | |
632 | /* The rx buffer allocation strategy is MTU dependent */ | |
633 | efx_rx_strategy(channel); | |
634 | ||
9f2cb71c | 635 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 636 | efx_init_rx_queue(rx_queue); |
9f2cb71c BH |
637 | efx_nic_generate_fill_event(rx_queue); |
638 | } | |
8ceee660 BH |
639 | |
640 | WARN_ON(channel->rx_pkt != NULL); | |
641 | efx_rx_strategy(channel); | |
642 | } | |
8ceee660 | 643 | |
9f2cb71c BH |
644 | if (netif_device_present(efx->net_dev)) |
645 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
646 | } |
647 | ||
9f2cb71c | 648 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
649 | { |
650 | struct efx_channel *channel; | |
651 | struct efx_tx_queue *tx_queue; | |
652 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 653 | int rc; |
8ceee660 BH |
654 | |
655 | EFX_ASSERT_RESET_SERIALISED(efx); | |
656 | BUG_ON(efx->port_enabled); | |
657 | ||
152b6a62 | 658 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
659 | if (rc && EFX_WORKAROUND_7803(efx)) { |
660 | /* Schedule a reset to recover from the flush failure. The | |
661 | * descriptor caches reference memory we're about to free, | |
662 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
663 | * the MACs because of the pending reset. */ | |
62776d03 BH |
664 | netif_err(efx, drv, efx->net_dev, |
665 | "Resetting to recover from flush failure\n"); | |
fd371e32 SH |
666 | efx_schedule_reset(efx, RESET_TYPE_ALL); |
667 | } else if (rc) { | |
62776d03 | 668 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); |
fd371e32 | 669 | } else { |
62776d03 BH |
670 | netif_dbg(efx, drv, efx->net_dev, |
671 | "successfully flushed all queues\n"); | |
fd371e32 | 672 | } |
6bc5d3a9 | 673 | |
8ceee660 | 674 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
675 | /* RX packet processing is pipelined, so wait for the |
676 | * NAPI handler to complete. At least event queue 0 | |
677 | * might be kept active by non-data events, so don't | |
678 | * use napi_synchronize() but actually disable NAPI | |
679 | * temporarily. | |
680 | */ | |
681 | if (efx_channel_has_rx_queue(channel)) { | |
682 | efx_stop_eventq(channel); | |
683 | efx_start_eventq(channel); | |
684 | } | |
8ceee660 BH |
685 | |
686 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
687 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 688 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 689 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
690 | } |
691 | } | |
692 | ||
693 | static void efx_remove_channel(struct efx_channel *channel) | |
694 | { | |
695 | struct efx_tx_queue *tx_queue; | |
696 | struct efx_rx_queue *rx_queue; | |
697 | ||
62776d03 BH |
698 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
699 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
700 | |
701 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
702 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 703 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
704 | efx_remove_tx_queue(tx_queue); |
705 | efx_remove_eventq(channel); | |
8ceee660 BH |
706 | } |
707 | ||
4642610c BH |
708 | static void efx_remove_channels(struct efx_nic *efx) |
709 | { | |
710 | struct efx_channel *channel; | |
711 | ||
712 | efx_for_each_channel(channel, efx) | |
713 | efx_remove_channel(channel); | |
714 | } | |
715 | ||
716 | int | |
717 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
718 | { | |
719 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
720 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 BH |
721 | unsigned i, next_buffer_table = 0; |
722 | int rc = 0; | |
723 | ||
724 | /* Not all channels should be reallocated. We must avoid | |
725 | * reallocating their buffer table entries. | |
726 | */ | |
727 | efx_for_each_channel(channel, efx) { | |
728 | struct efx_rx_queue *rx_queue; | |
729 | struct efx_tx_queue *tx_queue; | |
730 | ||
731 | if (channel->type->copy) | |
732 | continue; | |
733 | next_buffer_table = max(next_buffer_table, | |
734 | channel->eventq.index + | |
735 | channel->eventq.entries); | |
736 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
737 | next_buffer_table = max(next_buffer_table, | |
738 | rx_queue->rxd.index + | |
739 | rx_queue->rxd.entries); | |
740 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
741 | next_buffer_table = max(next_buffer_table, | |
742 | tx_queue->txd.index + | |
743 | tx_queue->txd.entries); | |
744 | } | |
4642610c BH |
745 | |
746 | efx_stop_all(efx); | |
7f967c01 | 747 | efx_stop_interrupts(efx, true); |
4642610c | 748 | |
7f967c01 | 749 | /* Clone channels (where possible) */ |
4642610c BH |
750 | memset(other_channel, 0, sizeof(other_channel)); |
751 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
752 | channel = efx->channel[i]; |
753 | if (channel->type->copy) | |
754 | channel = channel->type->copy(channel); | |
4642610c BH |
755 | if (!channel) { |
756 | rc = -ENOMEM; | |
757 | goto out; | |
758 | } | |
759 | other_channel[i] = channel; | |
760 | } | |
761 | ||
762 | /* Swap entry counts and channel pointers */ | |
763 | old_rxq_entries = efx->rxq_entries; | |
764 | old_txq_entries = efx->txq_entries; | |
765 | efx->rxq_entries = rxq_entries; | |
766 | efx->txq_entries = txq_entries; | |
767 | for (i = 0; i < efx->n_channels; i++) { | |
768 | channel = efx->channel[i]; | |
769 | efx->channel[i] = other_channel[i]; | |
770 | other_channel[i] = channel; | |
771 | } | |
772 | ||
7f967c01 BH |
773 | /* Restart buffer table allocation */ |
774 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 775 | |
e8f14992 | 776 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
777 | channel = efx->channel[i]; |
778 | if (!channel->type->copy) | |
779 | continue; | |
780 | rc = efx_probe_channel(channel); | |
781 | if (rc) | |
782 | goto rollback; | |
783 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 784 | } |
7f967c01 | 785 | |
4642610c | 786 | out: |
7f967c01 BH |
787 | /* Destroy unused channel structures */ |
788 | for (i = 0; i < efx->n_channels; i++) { | |
789 | channel = other_channel[i]; | |
790 | if (channel && channel->type->copy) { | |
791 | efx_fini_napi_channel(channel); | |
792 | efx_remove_channel(channel); | |
793 | kfree(channel); | |
794 | } | |
795 | } | |
4642610c | 796 | |
7f967c01 | 797 | efx_start_interrupts(efx, true); |
4642610c BH |
798 | efx_start_all(efx); |
799 | return rc; | |
800 | ||
801 | rollback: | |
802 | /* Swap back */ | |
803 | efx->rxq_entries = old_rxq_entries; | |
804 | efx->txq_entries = old_txq_entries; | |
805 | for (i = 0; i < efx->n_channels; i++) { | |
806 | channel = efx->channel[i]; | |
807 | efx->channel[i] = other_channel[i]; | |
808 | other_channel[i] = channel; | |
809 | } | |
810 | goto out; | |
811 | } | |
812 | ||
90d683af | 813 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 814 | { |
90d683af | 815 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
816 | } |
817 | ||
7f967c01 BH |
818 | static const struct efx_channel_type efx_default_channel_type = { |
819 | .pre_probe = efx_channel_dummy_op_int, | |
820 | .get_name = efx_get_channel_name, | |
821 | .copy = efx_copy_channel, | |
822 | .keep_eventq = false, | |
823 | }; | |
824 | ||
825 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
826 | { | |
827 | return 0; | |
828 | } | |
829 | ||
8ceee660 BH |
830 | /************************************************************************** |
831 | * | |
832 | * Port handling | |
833 | * | |
834 | **************************************************************************/ | |
835 | ||
836 | /* This ensures that the kernel is kept informed (via | |
837 | * netif_carrier_on/off) of the link status, and also maintains the | |
838 | * link status's stop on the port's TX queue. | |
839 | */ | |
fdaa9aed | 840 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 841 | { |
eb50c0d6 BH |
842 | struct efx_link_state *link_state = &efx->link_state; |
843 | ||
8ceee660 BH |
844 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
845 | * that no events are triggered between unregister_netdev() and the | |
846 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
847 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
848 | if (!netif_running(efx->net_dev)) | |
849 | return; | |
850 | ||
eb50c0d6 | 851 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
852 | efx->n_link_state_changes++; |
853 | ||
eb50c0d6 | 854 | if (link_state->up) |
8ceee660 BH |
855 | netif_carrier_on(efx->net_dev); |
856 | else | |
857 | netif_carrier_off(efx->net_dev); | |
858 | } | |
859 | ||
860 | /* Status message for kernel log */ | |
2aa9ef11 | 861 | if (link_state->up) |
62776d03 BH |
862 | netif_info(efx, link, efx->net_dev, |
863 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
864 | link_state->speed, link_state->fd ? "full" : "half", | |
865 | efx->net_dev->mtu, | |
866 | (efx->promiscuous ? " [PROMISC]" : "")); | |
2aa9ef11 | 867 | else |
62776d03 | 868 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
869 | } |
870 | ||
d3245b28 BH |
871 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
872 | { | |
873 | efx->link_advertising = advertising; | |
874 | if (advertising) { | |
875 | if (advertising & ADVERTISED_Pause) | |
876 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
877 | else | |
878 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
879 | if (advertising & ADVERTISED_Asym_Pause) | |
880 | efx->wanted_fc ^= EFX_FC_TX; | |
881 | } | |
882 | } | |
883 | ||
b5626946 | 884 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
885 | { |
886 | efx->wanted_fc = wanted_fc; | |
887 | if (efx->link_advertising) { | |
888 | if (wanted_fc & EFX_FC_RX) | |
889 | efx->link_advertising |= (ADVERTISED_Pause | | |
890 | ADVERTISED_Asym_Pause); | |
891 | else | |
892 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
893 | ADVERTISED_Asym_Pause); | |
894 | if (wanted_fc & EFX_FC_TX) | |
895 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
896 | } | |
897 | } | |
898 | ||
115122af BH |
899 | static void efx_fini_port(struct efx_nic *efx); |
900 | ||
d3245b28 BH |
901 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
902 | * the MAC appropriately. All other PHY configuration changes are pushed | |
903 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
904 | * through efx_monitor(). | |
905 | * | |
906 | * Callers must hold the mac_lock | |
907 | */ | |
908 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 909 | { |
d3245b28 BH |
910 | enum efx_phy_mode phy_mode; |
911 | int rc; | |
8ceee660 | 912 | |
d3245b28 | 913 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 914 | |
0fca8c97 | 915 | /* Serialise the promiscuous flag with efx_set_rx_mode. */ |
73ba7b68 BH |
916 | netif_addr_lock_bh(efx->net_dev); |
917 | netif_addr_unlock_bh(efx->net_dev); | |
a816f75a | 918 | |
d3245b28 BH |
919 | /* Disable PHY transmit in mac level loopbacks */ |
920 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
921 | if (LOOPBACK_INTERNAL(efx)) |
922 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
923 | else | |
924 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 925 | |
d3245b28 | 926 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 927 | |
d3245b28 BH |
928 | if (rc) |
929 | efx->phy_mode = phy_mode; | |
177dfcd8 | 930 | |
d3245b28 | 931 | return rc; |
8ceee660 BH |
932 | } |
933 | ||
934 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
935 | * disabled. */ | |
d3245b28 | 936 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 937 | { |
d3245b28 BH |
938 | int rc; |
939 | ||
8ceee660 BH |
940 | EFX_ASSERT_RESET_SERIALISED(efx); |
941 | ||
942 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 943 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 944 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
945 | |
946 | return rc; | |
8ceee660 BH |
947 | } |
948 | ||
8be4f3e6 BH |
949 | /* Asynchronous work item for changing MAC promiscuity and multicast |
950 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
951 | * MAC directly. */ | |
766ca0fa BH |
952 | static void efx_mac_work(struct work_struct *data) |
953 | { | |
954 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
955 | ||
956 | mutex_lock(&efx->mac_lock); | |
30b81cda | 957 | if (efx->port_enabled) |
710b208d | 958 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
959 | mutex_unlock(&efx->mac_lock); |
960 | } | |
961 | ||
8ceee660 BH |
962 | static int efx_probe_port(struct efx_nic *efx) |
963 | { | |
964 | int rc; | |
965 | ||
62776d03 | 966 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 967 | |
ff3b00a0 SH |
968 | if (phy_flash_cfg) |
969 | efx->phy_mode = PHY_MODE_SPECIAL; | |
970 | ||
ef2b90ee BH |
971 | /* Connect up MAC/PHY operations table */ |
972 | rc = efx->type->probe_port(efx); | |
8ceee660 | 973 | if (rc) |
e42de262 | 974 | return rc; |
8ceee660 | 975 | |
e332bcb3 BH |
976 | /* Initialise MAC address to permanent address */ |
977 | memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); | |
8ceee660 BH |
978 | |
979 | return 0; | |
8ceee660 BH |
980 | } |
981 | ||
982 | static int efx_init_port(struct efx_nic *efx) | |
983 | { | |
984 | int rc; | |
985 | ||
62776d03 | 986 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 987 | |
1dfc5cea BH |
988 | mutex_lock(&efx->mac_lock); |
989 | ||
177dfcd8 | 990 | rc = efx->phy_op->init(efx); |
8ceee660 | 991 | if (rc) |
1dfc5cea | 992 | goto fail1; |
8ceee660 | 993 | |
dc8cfa55 | 994 | efx->port_initialized = true; |
1dfc5cea | 995 | |
d3245b28 BH |
996 | /* Reconfigure the MAC before creating dma queues (required for |
997 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 998 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
999 | |
1000 | /* Ensure the PHY advertises the correct flow control settings */ | |
1001 | rc = efx->phy_op->reconfigure(efx); | |
1002 | if (rc) | |
1003 | goto fail2; | |
1004 | ||
1dfc5cea | 1005 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1006 | return 0; |
177dfcd8 | 1007 | |
1dfc5cea | 1008 | fail2: |
177dfcd8 | 1009 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1010 | fail1: |
1011 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1012 | return rc; |
8ceee660 BH |
1013 | } |
1014 | ||
8ceee660 BH |
1015 | static void efx_start_port(struct efx_nic *efx) |
1016 | { | |
62776d03 | 1017 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1018 | BUG_ON(efx->port_enabled); |
1019 | ||
1020 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1021 | efx->port_enabled = true; |
8be4f3e6 BH |
1022 | |
1023 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
1024 | * and then cancelled by efx_flush_all() */ | |
710b208d | 1025 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 1026 | |
8ceee660 BH |
1027 | mutex_unlock(&efx->mac_lock); |
1028 | } | |
1029 | ||
fdaa9aed | 1030 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
1031 | static void efx_stop_port(struct efx_nic *efx) |
1032 | { | |
62776d03 | 1033 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
1034 | |
1035 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1036 | efx->port_enabled = false; |
8ceee660 BH |
1037 | mutex_unlock(&efx->mac_lock); |
1038 | ||
1039 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1040 | netif_addr_lock_bh(efx->net_dev); |
1041 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
1042 | } |
1043 | ||
1044 | static void efx_fini_port(struct efx_nic *efx) | |
1045 | { | |
62776d03 | 1046 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1047 | |
1048 | if (!efx->port_initialized) | |
1049 | return; | |
1050 | ||
177dfcd8 | 1051 | efx->phy_op->fini(efx); |
dc8cfa55 | 1052 | efx->port_initialized = false; |
8ceee660 | 1053 | |
eb50c0d6 | 1054 | efx->link_state.up = false; |
8ceee660 BH |
1055 | efx_link_status_changed(efx); |
1056 | } | |
1057 | ||
1058 | static void efx_remove_port(struct efx_nic *efx) | |
1059 | { | |
62776d03 | 1060 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1061 | |
ef2b90ee | 1062 | efx->type->remove_port(efx); |
8ceee660 BH |
1063 | } |
1064 | ||
1065 | /************************************************************************** | |
1066 | * | |
1067 | * NIC handling | |
1068 | * | |
1069 | **************************************************************************/ | |
1070 | ||
1071 | /* This configures the PCI device to enable I/O and DMA. */ | |
1072 | static int efx_init_io(struct efx_nic *efx) | |
1073 | { | |
1074 | struct pci_dev *pci_dev = efx->pci_dev; | |
1075 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
1076 | int rc; | |
1077 | ||
62776d03 | 1078 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1079 | |
1080 | rc = pci_enable_device(pci_dev); | |
1081 | if (rc) { | |
62776d03 BH |
1082 | netif_err(efx, probe, efx->net_dev, |
1083 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1084 | goto fail1; |
1085 | } | |
1086 | ||
1087 | pci_set_master(pci_dev); | |
1088 | ||
1089 | /* Set the PCI DMA mask. Try all possibilities from our | |
1090 | * genuine mask down to 32 bits, because some architectures | |
1091 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1092 | * masks event though they reject 46 bit masks. | |
1093 | */ | |
1094 | while (dma_mask > 0x7fffffffUL) { | |
e9e01846 BH |
1095 | if (pci_dma_supported(pci_dev, dma_mask)) { |
1096 | rc = pci_set_dma_mask(pci_dev, dma_mask); | |
1097 | if (rc == 0) | |
1098 | break; | |
1099 | } | |
8ceee660 BH |
1100 | dma_mask >>= 1; |
1101 | } | |
1102 | if (rc) { | |
62776d03 BH |
1103 | netif_err(efx, probe, efx->net_dev, |
1104 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1105 | goto fail2; |
1106 | } | |
62776d03 BH |
1107 | netif_dbg(efx, probe, efx->net_dev, |
1108 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 BH |
1109 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); |
1110 | if (rc) { | |
1111 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
1112 | * fail with a mask that pci_set_dma_mask() accepted, | |
1113 | * but just in case... | |
1114 | */ | |
62776d03 BH |
1115 | netif_err(efx, probe, efx->net_dev, |
1116 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1117 | goto fail2; |
1118 | } | |
1119 | ||
dc803df8 BH |
1120 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1121 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1122 | if (rc) { |
62776d03 BH |
1123 | netif_err(efx, probe, efx->net_dev, |
1124 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1125 | rc = -EIO; |
1126 | goto fail3; | |
1127 | } | |
86c432ca BH |
1128 | efx->membase = ioremap_nocache(efx->membase_phys, |
1129 | efx->type->mem_map_size); | |
8ceee660 | 1130 | if (!efx->membase) { |
62776d03 BH |
1131 | netif_err(efx, probe, efx->net_dev, |
1132 | "could not map memory BAR at %llx+%x\n", | |
1133 | (unsigned long long)efx->membase_phys, | |
1134 | efx->type->mem_map_size); | |
8ceee660 BH |
1135 | rc = -ENOMEM; |
1136 | goto fail4; | |
1137 | } | |
62776d03 BH |
1138 | netif_dbg(efx, probe, efx->net_dev, |
1139 | "memory BAR at %llx+%x (virtual %p)\n", | |
1140 | (unsigned long long)efx->membase_phys, | |
1141 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1142 | |
1143 | return 0; | |
1144 | ||
1145 | fail4: | |
dc803df8 | 1146 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1147 | fail3: |
2c118e0f | 1148 | efx->membase_phys = 0; |
8ceee660 BH |
1149 | fail2: |
1150 | pci_disable_device(efx->pci_dev); | |
1151 | fail1: | |
1152 | return rc; | |
1153 | } | |
1154 | ||
1155 | static void efx_fini_io(struct efx_nic *efx) | |
1156 | { | |
62776d03 | 1157 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1158 | |
1159 | if (efx->membase) { | |
1160 | iounmap(efx->membase); | |
1161 | efx->membase = NULL; | |
1162 | } | |
1163 | ||
1164 | if (efx->membase_phys) { | |
dc803df8 | 1165 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1166 | efx->membase_phys = 0; |
8ceee660 BH |
1167 | } |
1168 | ||
1169 | pci_disable_device(efx->pci_dev); | |
1170 | } | |
1171 | ||
a9a52506 | 1172 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1173 | { |
cdb08f8f | 1174 | cpumask_var_t thread_mask; |
a16e5b24 | 1175 | unsigned int count; |
46123d04 | 1176 | int cpu; |
5b874e25 | 1177 | |
cd2d5b52 BH |
1178 | if (rss_cpus) { |
1179 | count = rss_cpus; | |
1180 | } else { | |
1181 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1182 | netif_warn(efx, probe, efx->net_dev, | |
1183 | "RSS disabled due to allocation failure\n"); | |
1184 | return 1; | |
1185 | } | |
46123d04 | 1186 | |
cd2d5b52 BH |
1187 | count = 0; |
1188 | for_each_online_cpu(cpu) { | |
1189 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1190 | ++count; | |
1191 | cpumask_or(thread_mask, thread_mask, | |
1192 | topology_thread_cpumask(cpu)); | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1197 | } |
1198 | ||
cd2d5b52 BH |
1199 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1200 | * table entries that are inaccessible to VFs | |
1201 | */ | |
1202 | if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1203 | count > efx_vf_size(efx)) { | |
1204 | netif_warn(efx, probe, efx->net_dev, | |
1205 | "Reducing number of RSS channels from %u to %u for " | |
1206 | "VF support. Increase vf-msix-limit to use more " | |
1207 | "channels on the PF.\n", | |
1208 | count, efx_vf_size(efx)); | |
1209 | count = efx_vf_size(efx); | |
46123d04 BH |
1210 | } |
1211 | ||
1212 | return count; | |
1213 | } | |
1214 | ||
64d8ad6d BH |
1215 | static int |
1216 | efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) | |
1217 | { | |
1218 | #ifdef CONFIG_RFS_ACCEL | |
a16e5b24 BH |
1219 | unsigned int i; |
1220 | int rc; | |
64d8ad6d BH |
1221 | |
1222 | efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); | |
1223 | if (!efx->net_dev->rx_cpu_rmap) | |
1224 | return -ENOMEM; | |
1225 | for (i = 0; i < efx->n_rx_channels; i++) { | |
1226 | rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, | |
1227 | xentries[i].vector); | |
1228 | if (rc) { | |
1229 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
1230 | efx->net_dev->rx_cpu_rmap = NULL; | |
1231 | return rc; | |
1232 | } | |
1233 | } | |
1234 | #endif | |
1235 | return 0; | |
1236 | } | |
1237 | ||
46123d04 BH |
1238 | /* Probe the number and type of interrupts we are able to obtain, and |
1239 | * the resulting numbers of channels and RX queues. | |
1240 | */ | |
64d8ad6d | 1241 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1242 | { |
a16e5b24 BH |
1243 | unsigned int max_channels = |
1244 | min(efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
7f967c01 BH |
1245 | unsigned int extra_channels = 0; |
1246 | unsigned int i, j; | |
a16e5b24 | 1247 | int rc; |
8ceee660 | 1248 | |
7f967c01 BH |
1249 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1250 | if (efx->extra_channel_type[i]) | |
1251 | ++extra_channels; | |
1252 | ||
8ceee660 | 1253 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1254 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1255 | unsigned int n_channels; |
aa6ef27e | 1256 | |
a9a52506 | 1257 | n_channels = efx_wanted_parallelism(efx); |
a4900ac9 BH |
1258 | if (separate_tx_channels) |
1259 | n_channels *= 2; | |
7f967c01 | 1260 | n_channels += extra_channels; |
a4900ac9 | 1261 | n_channels = min(n_channels, max_channels); |
8ceee660 | 1262 | |
a4900ac9 | 1263 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1264 | xentries[i].entry = i; |
a4900ac9 | 1265 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1266 | if (rc > 0) { |
62776d03 BH |
1267 | netif_err(efx, drv, efx->net_dev, |
1268 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1269 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1270 | netif_err(efx, drv, efx->net_dev, |
1271 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1272 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1273 | n_channels = rc; | |
8ceee660 | 1274 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1275 | n_channels); |
8ceee660 BH |
1276 | } |
1277 | ||
1278 | if (rc == 0) { | |
a4900ac9 | 1279 | efx->n_channels = n_channels; |
7f967c01 BH |
1280 | if (n_channels > extra_channels) |
1281 | n_channels -= extra_channels; | |
a4900ac9 | 1282 | if (separate_tx_channels) { |
7f967c01 BH |
1283 | efx->n_tx_channels = max(n_channels / 2, 1U); |
1284 | efx->n_rx_channels = max(n_channels - | |
1285 | efx->n_tx_channels, | |
1286 | 1U); | |
a4900ac9 | 1287 | } else { |
7f967c01 BH |
1288 | efx->n_tx_channels = n_channels; |
1289 | efx->n_rx_channels = n_channels; | |
a4900ac9 | 1290 | } |
64d8ad6d BH |
1291 | rc = efx_init_rx_cpu_rmap(efx, xentries); |
1292 | if (rc) { | |
1293 | pci_disable_msix(efx->pci_dev); | |
1294 | return rc; | |
1295 | } | |
7f967c01 | 1296 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1297 | efx_get_channel(efx, i)->irq = |
1298 | xentries[i].vector; | |
8ceee660 BH |
1299 | } else { |
1300 | /* Fall back to single channel MSI */ | |
1301 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1302 | netif_err(efx, drv, efx->net_dev, |
1303 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1304 | } |
1305 | } | |
1306 | ||
1307 | /* Try single interrupt MSI */ | |
1308 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1309 | efx->n_channels = 1; |
a4900ac9 BH |
1310 | efx->n_rx_channels = 1; |
1311 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1312 | rc = pci_enable_msi(efx->pci_dev); |
1313 | if (rc == 0) { | |
f7d12cdc | 1314 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1315 | } else { |
62776d03 BH |
1316 | netif_err(efx, drv, efx->net_dev, |
1317 | "could not enable MSI\n"); | |
8ceee660 BH |
1318 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1319 | } | |
1320 | } | |
1321 | ||
1322 | /* Assume legacy interrupts */ | |
1323 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1324 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1325 | efx->n_rx_channels = 1; |
1326 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1327 | efx->legacy_irq = efx->pci_dev->irq; |
1328 | } | |
64d8ad6d | 1329 | |
7f967c01 BH |
1330 | /* Assign extra channels if possible */ |
1331 | j = efx->n_channels; | |
1332 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1333 | if (!efx->extra_channel_type[i]) | |
1334 | continue; | |
1335 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1336 | efx->n_channels <= extra_channels) { | |
1337 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1338 | } else { | |
1339 | --j; | |
1340 | efx_get_channel(efx, j)->type = | |
1341 | efx->extra_channel_type[i]; | |
1342 | } | |
1343 | } | |
1344 | ||
cd2d5b52 BH |
1345 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
1346 | efx->rss_spread = (efx->n_rx_channels > 1 ? | |
1347 | efx->n_rx_channels : efx_vf_size(efx)); | |
1348 | ||
64d8ad6d | 1349 | return 0; |
8ceee660 BH |
1350 | } |
1351 | ||
9f2cb71c | 1352 | /* Enable interrupts, then probe and start the event queues */ |
7f967c01 | 1353 | static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq) |
9f2cb71c BH |
1354 | { |
1355 | struct efx_channel *channel; | |
1356 | ||
1357 | if (efx->legacy_irq) | |
1358 | efx->legacy_irq_enabled = true; | |
1359 | efx_nic_enable_interrupts(efx); | |
1360 | ||
1361 | efx_for_each_channel(channel, efx) { | |
7f967c01 BH |
1362 | if (!channel->type->keep_eventq || !may_keep_eventq) |
1363 | efx_init_eventq(channel); | |
9f2cb71c BH |
1364 | efx_start_eventq(channel); |
1365 | } | |
1366 | ||
1367 | efx_mcdi_mode_event(efx); | |
1368 | } | |
1369 | ||
7f967c01 | 1370 | static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq) |
9f2cb71c BH |
1371 | { |
1372 | struct efx_channel *channel; | |
1373 | ||
1374 | efx_mcdi_mode_poll(efx); | |
1375 | ||
1376 | efx_nic_disable_interrupts(efx); | |
1377 | if (efx->legacy_irq) { | |
1378 | synchronize_irq(efx->legacy_irq); | |
1379 | efx->legacy_irq_enabled = false; | |
1380 | } | |
1381 | ||
1382 | efx_for_each_channel(channel, efx) { | |
1383 | if (channel->irq) | |
1384 | synchronize_irq(channel->irq); | |
1385 | ||
1386 | efx_stop_eventq(channel); | |
7f967c01 BH |
1387 | if (!channel->type->keep_eventq || !may_keep_eventq) |
1388 | efx_fini_eventq(channel); | |
9f2cb71c BH |
1389 | } |
1390 | } | |
1391 | ||
8ceee660 BH |
1392 | static void efx_remove_interrupts(struct efx_nic *efx) |
1393 | { | |
1394 | struct efx_channel *channel; | |
1395 | ||
1396 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1397 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1398 | channel->irq = 0; |
1399 | pci_disable_msi(efx->pci_dev); | |
1400 | pci_disable_msix(efx->pci_dev); | |
1401 | ||
1402 | /* Remove legacy interrupt */ | |
1403 | efx->legacy_irq = 0; | |
1404 | } | |
1405 | ||
8831da7b | 1406 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1407 | { |
602a5322 BH |
1408 | struct efx_channel *channel; |
1409 | struct efx_tx_queue *tx_queue; | |
1410 | ||
97653431 | 1411 | efx->tx_channel_offset = |
a4900ac9 | 1412 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 BH |
1413 | |
1414 | /* We need to adjust the TX queue numbers if we have separate | |
1415 | * RX-only and TX-only channels. | |
1416 | */ | |
1417 | efx_for_each_channel(channel, efx) { | |
1418 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1419 | tx_queue->queue -= (efx->tx_channel_offset * | |
1420 | EFX_TXQ_TYPES); | |
1421 | } | |
8ceee660 BH |
1422 | } |
1423 | ||
1424 | static int efx_probe_nic(struct efx_nic *efx) | |
1425 | { | |
765c9f46 | 1426 | size_t i; |
8ceee660 BH |
1427 | int rc; |
1428 | ||
62776d03 | 1429 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1430 | |
1431 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1432 | rc = efx->type->probe(efx); |
8ceee660 BH |
1433 | if (rc) |
1434 | return rc; | |
1435 | ||
a4900ac9 | 1436 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1437 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1438 | rc = efx_probe_interrupts(efx); |
1439 | if (rc) | |
1440 | goto fail; | |
8ceee660 | 1441 | |
28e47c49 BH |
1442 | efx->type->dimension_resources(efx); |
1443 | ||
5d3a6fca BH |
1444 | if (efx->n_channels > 1) |
1445 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1446 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 | 1447 | efx->rx_indir_table[i] = |
cd2d5b52 | 1448 | ethtool_rxfh_indir_default(i, efx->rss_spread); |
5d3a6fca | 1449 | |
8831da7b | 1450 | efx_set_channels(efx); |
c4f4adc7 BH |
1451 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1452 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1453 | |
1454 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1455 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1456 | true); | |
8ceee660 BH |
1457 | |
1458 | return 0; | |
64d8ad6d BH |
1459 | |
1460 | fail: | |
1461 | efx->type->remove(efx); | |
1462 | return rc; | |
8ceee660 BH |
1463 | } |
1464 | ||
1465 | static void efx_remove_nic(struct efx_nic *efx) | |
1466 | { | |
62776d03 | 1467 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1468 | |
1469 | efx_remove_interrupts(efx); | |
ef2b90ee | 1470 | efx->type->remove(efx); |
8ceee660 BH |
1471 | } |
1472 | ||
1473 | /************************************************************************** | |
1474 | * | |
1475 | * NIC startup/shutdown | |
1476 | * | |
1477 | *************************************************************************/ | |
1478 | ||
1479 | static int efx_probe_all(struct efx_nic *efx) | |
1480 | { | |
8ceee660 BH |
1481 | int rc; |
1482 | ||
8ceee660 BH |
1483 | rc = efx_probe_nic(efx); |
1484 | if (rc) { | |
62776d03 | 1485 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1486 | goto fail1; |
1487 | } | |
1488 | ||
8ceee660 BH |
1489 | rc = efx_probe_port(efx); |
1490 | if (rc) { | |
62776d03 | 1491 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1492 | goto fail2; |
1493 | } | |
1494 | ||
ecc910f5 | 1495 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1496 | |
64eebcfd BH |
1497 | rc = efx_probe_filters(efx); |
1498 | if (rc) { | |
1499 | netif_err(efx, probe, efx->net_dev, | |
1500 | "failed to create filter tables\n"); | |
7f967c01 | 1501 | goto fail3; |
64eebcfd BH |
1502 | } |
1503 | ||
7f967c01 BH |
1504 | rc = efx_probe_channels(efx); |
1505 | if (rc) | |
1506 | goto fail4; | |
1507 | ||
8ceee660 BH |
1508 | return 0; |
1509 | ||
64eebcfd | 1510 | fail4: |
7f967c01 | 1511 | efx_remove_filters(efx); |
8ceee660 | 1512 | fail3: |
8ceee660 BH |
1513 | efx_remove_port(efx); |
1514 | fail2: | |
1515 | efx_remove_nic(efx); | |
1516 | fail1: | |
1517 | return rc; | |
1518 | } | |
1519 | ||
9f2cb71c BH |
1520 | /* Called after previous invocation(s) of efx_stop_all, restarts the port, |
1521 | * kernel transmit queues and NAPI processing, and ensures that the port is | |
1522 | * scheduled to be reconfigured. This function is safe to call multiple | |
1523 | * times when the NIC is in any state. | |
1524 | */ | |
8ceee660 BH |
1525 | static void efx_start_all(struct efx_nic *efx) |
1526 | { | |
8ceee660 BH |
1527 | EFX_ASSERT_RESET_SERIALISED(efx); |
1528 | ||
1529 | /* Check that it is appropriate to restart the interface. All | |
1530 | * of these flags are safe to read under just the rtnl lock */ | |
1531 | if (efx->port_enabled) | |
1532 | return; | |
1533 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1534 | return; | |
73ba7b68 | 1535 | if (!netif_running(efx->net_dev)) |
8ceee660 BH |
1536 | return; |
1537 | ||
8ceee660 | 1538 | efx_start_port(efx); |
9f2cb71c | 1539 | efx_start_datapath(efx); |
8880f4ec | 1540 | |
78c1f0a0 SH |
1541 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1542 | * event driven), we have to poll the PHY because after an event queue | |
1543 | * flush, we could have a missed a link state change */ | |
1544 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1545 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1546 | efx_monitor_interval); | |
78c1f0a0 SH |
1547 | } else { |
1548 | mutex_lock(&efx->mac_lock); | |
1549 | if (efx->phy_op->poll(efx)) | |
1550 | efx_link_status_changed(efx); | |
1551 | mutex_unlock(&efx->mac_lock); | |
1552 | } | |
55edc6e6 | 1553 | |
ef2b90ee | 1554 | efx->type->start_stats(efx); |
8ceee660 BH |
1555 | } |
1556 | ||
1557 | /* Flush all delayed work. Should only be called when no more delayed work | |
1558 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1559 | * since we're holding the rtnl_lock at this point. */ | |
1560 | static void efx_flush_all(struct efx_nic *efx) | |
1561 | { | |
8ceee660 BH |
1562 | /* Make sure the hardware monitor is stopped */ |
1563 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1564 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1565 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1566 | } |
1567 | ||
1568 | /* Quiesce hardware and software without bringing the link down. | |
1569 | * Safe to call multiple times, when the nic and interface is in any | |
1570 | * state. The caller is guaranteed to subsequently be in a position | |
1571 | * to modify any hardware and software state they see fit without | |
1572 | * taking locks. */ | |
1573 | static void efx_stop_all(struct efx_nic *efx) | |
1574 | { | |
8ceee660 BH |
1575 | EFX_ASSERT_RESET_SERIALISED(efx); |
1576 | ||
1577 | /* port_enabled can be read safely under the rtnl lock */ | |
1578 | if (!efx->port_enabled) | |
1579 | return; | |
1580 | ||
ef2b90ee | 1581 | efx->type->stop_stats(efx); |
8ceee660 BH |
1582 | efx_stop_port(efx); |
1583 | ||
fdaa9aed | 1584 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1585 | efx_flush_all(efx); |
1586 | ||
8ceee660 BH |
1587 | /* Stop the kernel transmit interface late, so the watchdog |
1588 | * timer isn't ticking over the flush */ | |
9f2cb71c BH |
1589 | netif_tx_disable(efx->net_dev); |
1590 | ||
1591 | efx_stop_datapath(efx); | |
8ceee660 BH |
1592 | } |
1593 | ||
1594 | static void efx_remove_all(struct efx_nic *efx) | |
1595 | { | |
4642610c | 1596 | efx_remove_channels(efx); |
7f967c01 | 1597 | efx_remove_filters(efx); |
8ceee660 BH |
1598 | efx_remove_port(efx); |
1599 | efx_remove_nic(efx); | |
1600 | } | |
1601 | ||
8ceee660 BH |
1602 | /************************************************************************** |
1603 | * | |
1604 | * Interrupt moderation | |
1605 | * | |
1606 | **************************************************************************/ | |
1607 | ||
cc180b69 | 1608 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1609 | { |
b548f976 BH |
1610 | if (usecs == 0) |
1611 | return 0; | |
cc180b69 | 1612 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1613 | return 1; /* never round down to 0 */ |
cc180b69 | 1614 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1615 | } |
1616 | ||
8ceee660 | 1617 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1618 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1619 | unsigned int rx_usecs, bool rx_adaptive, | |
1620 | bool rx_may_override_tx) | |
8ceee660 | 1621 | { |
f7d12cdc | 1622 | struct efx_channel *channel; |
cc180b69 BH |
1623 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1624 | efx->timer_quantum_ns, | |
1625 | 1000); | |
1626 | unsigned int tx_ticks; | |
1627 | unsigned int rx_ticks; | |
8ceee660 BH |
1628 | |
1629 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1630 | ||
cc180b69 | 1631 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1632 | return -EINVAL; |
1633 | ||
cc180b69 BH |
1634 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1635 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1636 | ||
9e393b30 BH |
1637 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1638 | !rx_may_override_tx) { | |
1639 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1640 | "RX and TX IRQ moderation must be equal\n"); | |
1641 | return -EINVAL; | |
1642 | } | |
1643 | ||
6fb70fd1 | 1644 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1645 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1646 | efx_for_each_channel(channel, efx) { |
525da907 | 1647 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1648 | channel->irq_moderation = rx_ticks; |
525da907 | 1649 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1650 | channel->irq_moderation = tx_ticks; |
1651 | } | |
9e393b30 BH |
1652 | |
1653 | return 0; | |
8ceee660 BH |
1654 | } |
1655 | ||
a0c4faf5 BH |
1656 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1657 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1658 | { | |
cc180b69 BH |
1659 | /* We must round up when converting ticks to microseconds |
1660 | * because we round down when converting the other way. | |
1661 | */ | |
1662 | ||
a0c4faf5 | 1663 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1664 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1665 | efx->timer_quantum_ns, | |
1666 | 1000); | |
a0c4faf5 BH |
1667 | |
1668 | /* If channels are shared between RX and TX, so is IRQ | |
1669 | * moderation. Otherwise, IRQ moderation is the same for all | |
1670 | * TX channels and is not adaptive. | |
1671 | */ | |
1672 | if (efx->tx_channel_offset == 0) | |
1673 | *tx_usecs = *rx_usecs; | |
1674 | else | |
cc180b69 | 1675 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1676 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1677 | efx->timer_quantum_ns, |
1678 | 1000); | |
a0c4faf5 BH |
1679 | } |
1680 | ||
8ceee660 BH |
1681 | /************************************************************************** |
1682 | * | |
1683 | * Hardware monitor | |
1684 | * | |
1685 | **************************************************************************/ | |
1686 | ||
e254c274 | 1687 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1688 | static void efx_monitor(struct work_struct *data) |
1689 | { | |
1690 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1691 | monitor_work.work); | |
8ceee660 | 1692 | |
62776d03 BH |
1693 | netif_vdbg(efx, timer, efx->net_dev, |
1694 | "hardware monitor executing on CPU %d\n", | |
1695 | raw_smp_processor_id()); | |
ef2b90ee | 1696 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1697 | |
8ceee660 BH |
1698 | /* If the mac_lock is already held then it is likely a port |
1699 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1700 | * most of the work of monitor() anyway. */ |
1701 | if (mutex_trylock(&efx->mac_lock)) { | |
1702 | if (efx->port_enabled) | |
1703 | efx->type->monitor(efx); | |
1704 | mutex_unlock(&efx->mac_lock); | |
1705 | } | |
8ceee660 | 1706 | |
8ceee660 BH |
1707 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1708 | efx_monitor_interval); | |
1709 | } | |
1710 | ||
1711 | /************************************************************************** | |
1712 | * | |
1713 | * ioctls | |
1714 | * | |
1715 | *************************************************************************/ | |
1716 | ||
1717 | /* Net device ioctl | |
1718 | * Context: process, rtnl_lock() held. | |
1719 | */ | |
1720 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1721 | { | |
767e468c | 1722 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1723 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1724 | |
1725 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1726 | ||
68e7f45e BH |
1727 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1728 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1729 | (data->phy_id & 0xfc00) == 0x0400) | |
1730 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1731 | ||
1732 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1733 | } |
1734 | ||
1735 | /************************************************************************** | |
1736 | * | |
1737 | * NAPI interface | |
1738 | * | |
1739 | **************************************************************************/ | |
1740 | ||
7f967c01 BH |
1741 | static void efx_init_napi_channel(struct efx_channel *channel) |
1742 | { | |
1743 | struct efx_nic *efx = channel->efx; | |
1744 | ||
1745 | channel->napi_dev = efx->net_dev; | |
1746 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
1747 | efx_poll, napi_weight); | |
1748 | } | |
1749 | ||
e8f14992 | 1750 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1751 | { |
1752 | struct efx_channel *channel; | |
8ceee660 | 1753 | |
7f967c01 BH |
1754 | efx_for_each_channel(channel, efx) |
1755 | efx_init_napi_channel(channel); | |
e8f14992 BH |
1756 | } |
1757 | ||
1758 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1759 | { | |
1760 | if (channel->napi_dev) | |
1761 | netif_napi_del(&channel->napi_str); | |
1762 | channel->napi_dev = NULL; | |
8ceee660 BH |
1763 | } |
1764 | ||
1765 | static void efx_fini_napi(struct efx_nic *efx) | |
1766 | { | |
1767 | struct efx_channel *channel; | |
1768 | ||
e8f14992 BH |
1769 | efx_for_each_channel(channel, efx) |
1770 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1771 | } |
1772 | ||
1773 | /************************************************************************** | |
1774 | * | |
1775 | * Kernel netpoll interface | |
1776 | * | |
1777 | *************************************************************************/ | |
1778 | ||
1779 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1780 | ||
1781 | /* Although in the common case interrupts will be disabled, this is not | |
1782 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1783 | * so no locking is required. | |
1784 | */ | |
1785 | static void efx_netpoll(struct net_device *net_dev) | |
1786 | { | |
767e468c | 1787 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1788 | struct efx_channel *channel; |
1789 | ||
64ee3120 | 1790 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1791 | efx_schedule_channel(channel); |
1792 | } | |
1793 | ||
1794 | #endif | |
1795 | ||
1796 | /************************************************************************** | |
1797 | * | |
1798 | * Kernel net device interface | |
1799 | * | |
1800 | *************************************************************************/ | |
1801 | ||
1802 | /* Context: process, rtnl_lock() held. */ | |
1803 | static int efx_net_open(struct net_device *net_dev) | |
1804 | { | |
767e468c | 1805 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1806 | EFX_ASSERT_RESET_SERIALISED(efx); |
1807 | ||
62776d03 BH |
1808 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1809 | raw_smp_processor_id()); | |
8ceee660 | 1810 | |
f4bd954e BH |
1811 | if (efx->state == STATE_DISABLED) |
1812 | return -EIO; | |
f8b87c17 BH |
1813 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1814 | return -EBUSY; | |
8880f4ec BH |
1815 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1816 | return -EIO; | |
f8b87c17 | 1817 | |
78c1f0a0 SH |
1818 | /* Notify the kernel of the link state polled during driver load, |
1819 | * before the monitor starts running */ | |
1820 | efx_link_status_changed(efx); | |
1821 | ||
8ceee660 BH |
1822 | efx_start_all(efx); |
1823 | return 0; | |
1824 | } | |
1825 | ||
1826 | /* Context: process, rtnl_lock() held. | |
1827 | * Note that the kernel will ignore our return code; this method | |
1828 | * should really be a void. | |
1829 | */ | |
1830 | static int efx_net_stop(struct net_device *net_dev) | |
1831 | { | |
767e468c | 1832 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1833 | |
62776d03 BH |
1834 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1835 | raw_smp_processor_id()); | |
8ceee660 | 1836 | |
f4bd954e BH |
1837 | if (efx->state != STATE_DISABLED) { |
1838 | /* Stop the device and flush all the channels */ | |
1839 | efx_stop_all(efx); | |
f4bd954e | 1840 | } |
8ceee660 BH |
1841 | |
1842 | return 0; | |
1843 | } | |
1844 | ||
5b9e207c | 1845 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
1846 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
1847 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 1848 | { |
767e468c | 1849 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1850 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1851 | |
55edc6e6 | 1852 | spin_lock_bh(&efx->stats_lock); |
1cb34522 | 1853 | |
ef2b90ee | 1854 | efx->type->update_stats(efx); |
8ceee660 BH |
1855 | |
1856 | stats->rx_packets = mac_stats->rx_packets; | |
1857 | stats->tx_packets = mac_stats->tx_packets; | |
1858 | stats->rx_bytes = mac_stats->rx_bytes; | |
1859 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1860 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1861 | stats->multicast = mac_stats->rx_multicast; |
1862 | stats->collisions = mac_stats->tx_collision; | |
1863 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1864 | mac_stats->rx_length_error); | |
8ceee660 BH |
1865 | stats->rx_crc_errors = mac_stats->rx_bad; |
1866 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1867 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1868 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1869 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1870 | ||
1871 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1872 | stats->rx_crc_errors + |
1873 | stats->rx_frame_errors + | |
8ceee660 BH |
1874 | mac_stats->rx_symbol_error); |
1875 | stats->tx_errors = (stats->tx_window_errors + | |
1876 | mac_stats->tx_bad); | |
1877 | ||
1cb34522 BH |
1878 | spin_unlock_bh(&efx->stats_lock); |
1879 | ||
8ceee660 BH |
1880 | return stats; |
1881 | } | |
1882 | ||
1883 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1884 | static void efx_watchdog(struct net_device *net_dev) | |
1885 | { | |
767e468c | 1886 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1887 | |
62776d03 BH |
1888 | netif_err(efx, tx_err, efx->net_dev, |
1889 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1890 | efx->port_enabled); | |
8ceee660 | 1891 | |
739bb23d | 1892 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1893 | } |
1894 | ||
1895 | ||
1896 | /* Context: process, rtnl_lock() held. */ | |
1897 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1898 | { | |
767e468c | 1899 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1900 | |
1901 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1902 | ||
1903 | if (new_mtu > EFX_MAX_MTU) | |
1904 | return -EINVAL; | |
1905 | ||
1906 | efx_stop_all(efx); | |
1907 | ||
62776d03 | 1908 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 1909 | |
d3245b28 BH |
1910 | mutex_lock(&efx->mac_lock); |
1911 | /* Reconfigure the MAC before enabling the dma queues so that | |
1912 | * the RX buffers don't overflow */ | |
8ceee660 | 1913 | net_dev->mtu = new_mtu; |
710b208d | 1914 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1915 | mutex_unlock(&efx->mac_lock); |
1916 | ||
8ceee660 | 1917 | efx_start_all(efx); |
6c8eef4a | 1918 | return 0; |
8ceee660 BH |
1919 | } |
1920 | ||
1921 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1922 | { | |
767e468c | 1923 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1924 | struct sockaddr *addr = data; |
1925 | char *new_addr = addr->sa_data; | |
1926 | ||
1927 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1928 | ||
1929 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1930 | netif_err(efx, drv, efx->net_dev, |
1931 | "invalid ethernet MAC address requested: %pM\n", | |
1932 | new_addr); | |
8ceee660 BH |
1933 | return -EINVAL; |
1934 | } | |
1935 | ||
1936 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
cd2d5b52 | 1937 | efx_sriov_mac_address_changed(efx); |
8ceee660 BH |
1938 | |
1939 | /* Reconfigure the MAC */ | |
d3245b28 | 1940 | mutex_lock(&efx->mac_lock); |
710b208d | 1941 | efx->type->reconfigure_mac(efx); |
d3245b28 | 1942 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
1943 | |
1944 | return 0; | |
1945 | } | |
1946 | ||
a816f75a | 1947 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 1948 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 1949 | { |
767e468c | 1950 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1951 | struct netdev_hw_addr *ha; |
8ceee660 | 1952 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1953 | u32 crc; |
1954 | int bit; | |
8ceee660 | 1955 | |
8be4f3e6 | 1956 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1957 | |
1958 | /* Build multicast hash table */ | |
8be4f3e6 | 1959 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1960 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1961 | } else { | |
1962 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1963 | netdev_for_each_mc_addr(ha, net_dev) { |
1964 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1965 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1966 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1967 | } |
8ceee660 | 1968 | |
8be4f3e6 BH |
1969 | /* Broadcast packets go through the multicast hash filter. |
1970 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1971 | * so we always add bit 0xff to the mask. | |
1972 | */ | |
1973 | set_bit_le(0xff, mc_hash->byte); | |
1974 | } | |
a816f75a | 1975 | |
8be4f3e6 BH |
1976 | if (efx->port_enabled) |
1977 | queue_work(efx->workqueue, &efx->mac_work); | |
1978 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1979 | } |
1980 | ||
c8f44aff | 1981 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
1982 | { |
1983 | struct efx_nic *efx = netdev_priv(net_dev); | |
1984 | ||
1985 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
1986 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
1987 | efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
1988 | ||
1989 | return 0; | |
1990 | } | |
1991 | ||
c3ecb9f3 SH |
1992 | static const struct net_device_ops efx_netdev_ops = { |
1993 | .ndo_open = efx_net_open, | |
1994 | .ndo_stop = efx_net_stop, | |
4472702e | 1995 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
1996 | .ndo_tx_timeout = efx_watchdog, |
1997 | .ndo_start_xmit = efx_hard_start_xmit, | |
1998 | .ndo_validate_addr = eth_validate_addr, | |
1999 | .ndo_do_ioctl = efx_ioctl, | |
2000 | .ndo_change_mtu = efx_change_mtu, | |
2001 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2002 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2003 | .ndo_set_features = efx_set_features, |
cd2d5b52 BH |
2004 | #ifdef CONFIG_SFC_SRIOV |
2005 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, | |
2006 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2007 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2008 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
2009 | #endif | |
c3ecb9f3 SH |
2010 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2011 | .ndo_poll_controller = efx_netpoll, | |
2012 | #endif | |
94b274bf | 2013 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
2014 | #ifdef CONFIG_RFS_ACCEL |
2015 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2016 | #endif | |
c3ecb9f3 SH |
2017 | }; |
2018 | ||
7dde596e BH |
2019 | static void efx_update_name(struct efx_nic *efx) |
2020 | { | |
2021 | strcpy(efx->name, efx->net_dev->name); | |
2022 | efx_mtd_rename(efx); | |
2023 | efx_set_channel_names(efx); | |
2024 | } | |
2025 | ||
8ceee660 BH |
2026 | static int efx_netdev_event(struct notifier_block *this, |
2027 | unsigned long event, void *ptr) | |
2028 | { | |
d3208b5e | 2029 | struct net_device *net_dev = ptr; |
8ceee660 | 2030 | |
7dde596e BH |
2031 | if (net_dev->netdev_ops == &efx_netdev_ops && |
2032 | event == NETDEV_CHANGENAME) | |
2033 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2034 | |
2035 | return NOTIFY_DONE; | |
2036 | } | |
2037 | ||
2038 | static struct notifier_block efx_netdev_notifier = { | |
2039 | .notifier_call = efx_netdev_event, | |
2040 | }; | |
2041 | ||
06d5e193 BH |
2042 | static ssize_t |
2043 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2044 | { | |
2045 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2046 | return sprintf(buf, "%d\n", efx->phy_type); | |
2047 | } | |
2048 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
2049 | ||
8ceee660 BH |
2050 | static int efx_register_netdev(struct efx_nic *efx) |
2051 | { | |
2052 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2053 | struct efx_channel *channel; |
8ceee660 BH |
2054 | int rc; |
2055 | ||
2056 | net_dev->watchdog_timeo = 5 * HZ; | |
2057 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 2058 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
2059 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
2060 | ||
7dde596e | 2061 | rtnl_lock(); |
aed0628d BH |
2062 | |
2063 | rc = dev_alloc_name(net_dev, net_dev->name); | |
2064 | if (rc < 0) | |
2065 | goto fail_locked; | |
7dde596e | 2066 | efx_update_name(efx); |
aed0628d BH |
2067 | |
2068 | rc = register_netdevice(net_dev); | |
2069 | if (rc) | |
2070 | goto fail_locked; | |
2071 | ||
c04bfc6b BH |
2072 | efx_for_each_channel(channel, efx) { |
2073 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2074 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2075 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2076 | } |
2077 | ||
aed0628d | 2078 | /* Always start with carrier off; PHY events will detect the link */ |
86ee5302 | 2079 | netif_carrier_off(net_dev); |
aed0628d | 2080 | |
7dde596e | 2081 | rtnl_unlock(); |
8ceee660 | 2082 | |
06d5e193 BH |
2083 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2084 | if (rc) { | |
62776d03 BH |
2085 | netif_err(efx, drv, efx->net_dev, |
2086 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2087 | goto fail_registered; |
2088 | } | |
2089 | ||
8ceee660 | 2090 | return 0; |
06d5e193 | 2091 | |
aed0628d BH |
2092 | fail_locked: |
2093 | rtnl_unlock(); | |
62776d03 | 2094 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
2095 | return rc; |
2096 | ||
06d5e193 BH |
2097 | fail_registered: |
2098 | unregister_netdev(net_dev); | |
2099 | return rc; | |
8ceee660 BH |
2100 | } |
2101 | ||
2102 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2103 | { | |
f7d12cdc | 2104 | struct efx_channel *channel; |
8ceee660 BH |
2105 | struct efx_tx_queue *tx_queue; |
2106 | ||
2107 | if (!efx->net_dev) | |
2108 | return; | |
2109 | ||
767e468c | 2110 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
2111 | |
2112 | /* Free up any skbs still remaining. This has to happen before | |
2113 | * we try to unregister the netdev as running their destructors | |
2114 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
2115 | efx_for_each_channel(channel, efx) { |
2116 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
2117 | efx_release_tx_buffers(tx_queue); | |
2118 | } | |
8ceee660 | 2119 | |
73ba7b68 BH |
2120 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
2121 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
2122 | unregister_netdev(efx->net_dev); | |
8ceee660 BH |
2123 | } |
2124 | ||
2125 | /************************************************************************** | |
2126 | * | |
2127 | * Device reset and suspend | |
2128 | * | |
2129 | **************************************************************************/ | |
2130 | ||
2467ca46 BH |
2131 | /* Tears down the entire software state and most of the hardware state |
2132 | * before reset. */ | |
d3245b28 | 2133 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2134 | { |
8ceee660 BH |
2135 | EFX_ASSERT_RESET_SERIALISED(efx); |
2136 | ||
2467ca46 BH |
2137 | efx_stop_all(efx); |
2138 | mutex_lock(&efx->mac_lock); | |
2139 | ||
7f967c01 | 2140 | efx_stop_interrupts(efx, false); |
4b988280 SH |
2141 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2142 | efx->phy_op->fini(efx); | |
ef2b90ee | 2143 | efx->type->fini(efx); |
8ceee660 BH |
2144 | } |
2145 | ||
2467ca46 BH |
2146 | /* This function will always ensure that the locks acquired in |
2147 | * efx_reset_down() are released. A failure return code indicates | |
2148 | * that we were unable to reinitialise the hardware, and the | |
2149 | * driver should be disabled. If ok is false, then the rx and tx | |
2150 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2151 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2152 | { |
2153 | int rc; | |
2154 | ||
2467ca46 | 2155 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2156 | |
ef2b90ee | 2157 | rc = efx->type->init(efx); |
8ceee660 | 2158 | if (rc) { |
62776d03 | 2159 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2160 | goto fail; |
8ceee660 BH |
2161 | } |
2162 | ||
eb9f6744 BH |
2163 | if (!ok) |
2164 | goto fail; | |
2165 | ||
4b988280 | 2166 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2167 | rc = efx->phy_op->init(efx); |
2168 | if (rc) | |
2169 | goto fail; | |
2170 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2171 | netif_err(efx, drv, efx->net_dev, |
2172 | "could not restore PHY settings\n"); | |
4b988280 SH |
2173 | } |
2174 | ||
710b208d | 2175 | efx->type->reconfigure_mac(efx); |
8ceee660 | 2176 | |
7f967c01 | 2177 | efx_start_interrupts(efx, false); |
64eebcfd | 2178 | efx_restore_filters(efx); |
cd2d5b52 | 2179 | efx_sriov_reset(efx); |
eb9f6744 | 2180 | |
eb9f6744 BH |
2181 | mutex_unlock(&efx->mac_lock); |
2182 | ||
2183 | efx_start_all(efx); | |
2184 | ||
2185 | return 0; | |
2186 | ||
2187 | fail: | |
2188 | efx->port_initialized = false; | |
2467ca46 BH |
2189 | |
2190 | mutex_unlock(&efx->mac_lock); | |
2191 | ||
8ceee660 BH |
2192 | return rc; |
2193 | } | |
2194 | ||
eb9f6744 BH |
2195 | /* Reset the NIC using the specified method. Note that the reset may |
2196 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2197 | * |
eb9f6744 | 2198 | * Caller must hold the rtnl_lock. |
8ceee660 | 2199 | */ |
eb9f6744 | 2200 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2201 | { |
eb9f6744 BH |
2202 | int rc, rc2; |
2203 | bool disabled; | |
8ceee660 | 2204 | |
62776d03 BH |
2205 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2206 | RESET_TYPE(method)); | |
8ceee660 | 2207 | |
e4abce85 | 2208 | netif_device_detach(efx->net_dev); |
d3245b28 | 2209 | efx_reset_down(efx, method); |
8ceee660 | 2210 | |
ef2b90ee | 2211 | rc = efx->type->reset(efx, method); |
8ceee660 | 2212 | if (rc) { |
62776d03 | 2213 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2214 | goto out; |
8ceee660 BH |
2215 | } |
2216 | ||
a7d529ae BH |
2217 | /* Clear flags for the scopes we covered. We assume the NIC and |
2218 | * driver are now quiescent so that there is no race here. | |
2219 | */ | |
2220 | efx->reset_pending &= -(1 << (method + 1)); | |
8ceee660 BH |
2221 | |
2222 | /* Reinitialise bus-mastering, which may have been turned off before | |
2223 | * the reset was scheduled. This is still appropriate, even in the | |
2224 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2225 | * can respond to requests. */ | |
2226 | pci_set_master(efx->pci_dev); | |
2227 | ||
eb9f6744 | 2228 | out: |
8ceee660 | 2229 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2230 | disabled = rc || method == RESET_TYPE_DISABLE; |
2231 | rc2 = efx_reset_up(efx, method, !disabled); | |
2232 | if (rc2) { | |
2233 | disabled = true; | |
2234 | if (!rc) | |
2235 | rc = rc2; | |
8ceee660 BH |
2236 | } |
2237 | ||
eb9f6744 | 2238 | if (disabled) { |
f49a4589 | 2239 | dev_close(efx->net_dev); |
62776d03 | 2240 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2241 | efx->state = STATE_DISABLED; |
f4bd954e | 2242 | } else { |
62776d03 | 2243 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2244 | netif_device_attach(efx->net_dev); |
f4bd954e | 2245 | } |
8ceee660 BH |
2246 | return rc; |
2247 | } | |
2248 | ||
2249 | /* The worker thread exists so that code that cannot sleep can | |
2250 | * schedule a reset for later. | |
2251 | */ | |
2252 | static void efx_reset_work(struct work_struct *data) | |
2253 | { | |
eb9f6744 | 2254 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
a7d529ae | 2255 | unsigned long pending = ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 2256 | |
a7d529ae | 2257 | if (!pending) |
319ba649 SH |
2258 | return; |
2259 | ||
eb9f6744 | 2260 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
a7d529ae | 2261 | * flags set so that efx_pci_probe_main will be retried */ |
eb9f6744 | 2262 | if (efx->state != STATE_RUNNING) { |
62776d03 BH |
2263 | netif_info(efx, drv, efx->net_dev, |
2264 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
2265 | return; |
2266 | } | |
2267 | ||
2268 | rtnl_lock(); | |
a7d529ae | 2269 | (void)efx_reset(efx, fls(pending) - 1); |
eb9f6744 | 2270 | rtnl_unlock(); |
8ceee660 BH |
2271 | } |
2272 | ||
2273 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2274 | { | |
2275 | enum reset_type method; | |
2276 | ||
8ceee660 BH |
2277 | switch (type) { |
2278 | case RESET_TYPE_INVISIBLE: | |
2279 | case RESET_TYPE_ALL: | |
2280 | case RESET_TYPE_WORLD: | |
2281 | case RESET_TYPE_DISABLE: | |
2282 | method = type; | |
0e2a9c7c BH |
2283 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2284 | RESET_TYPE(method)); | |
8ceee660 | 2285 | break; |
8ceee660 | 2286 | default: |
0e2a9c7c | 2287 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2288 | netif_dbg(efx, drv, efx->net_dev, |
2289 | "scheduling %s reset for %s\n", | |
2290 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2291 | break; |
2292 | } | |
8ceee660 | 2293 | |
a7d529ae | 2294 | set_bit(method, &efx->reset_pending); |
8ceee660 | 2295 | |
8880f4ec BH |
2296 | /* efx_process_channel() will no longer read events once a |
2297 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2298 | efx_mcdi_mode_poll(efx); | |
2299 | ||
1ab00629 | 2300 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2301 | } |
2302 | ||
2303 | /************************************************************************** | |
2304 | * | |
2305 | * List of NICs we support | |
2306 | * | |
2307 | **************************************************************************/ | |
2308 | ||
2309 | /* PCI device ID table */ | |
a3aa1884 | 2310 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2311 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2312 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2313 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2314 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2315 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2316 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2317 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2318 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2319 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2320 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8ceee660 BH |
2321 | {0} /* end of list */ |
2322 | }; | |
2323 | ||
2324 | /************************************************************************** | |
2325 | * | |
3759433d | 2326 | * Dummy PHY/MAC operations |
8ceee660 | 2327 | * |
01aad7b6 | 2328 | * Can be used for some unimplemented operations |
8ceee660 BH |
2329 | * Needed so all function pointers are valid and do not have to be tested |
2330 | * before use | |
2331 | * | |
2332 | **************************************************************************/ | |
2333 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2334 | { | |
2335 | return 0; | |
2336 | } | |
2337 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2338 | |
2339 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2340 | { |
2341 | return false; | |
2342 | } | |
8ceee660 | 2343 | |
6c8c2513 | 2344 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2345 | .init = efx_port_dummy_op_int, |
d3245b28 | 2346 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2347 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2348 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2349 | }; |
2350 | ||
8ceee660 BH |
2351 | /************************************************************************** |
2352 | * | |
2353 | * Data housekeeping | |
2354 | * | |
2355 | **************************************************************************/ | |
2356 | ||
2357 | /* This zeroes out and then fills in the invariants in a struct | |
2358 | * efx_nic (including all sub-structures). | |
2359 | */ | |
6c8c2513 | 2360 | static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type, |
8ceee660 BH |
2361 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2362 | { | |
4642610c | 2363 | int i; |
8ceee660 BH |
2364 | |
2365 | /* Initialise common structures */ | |
2366 | memset(efx, 0, sizeof(*efx)); | |
2367 | spin_lock_init(&efx->biu_lock); | |
76884835 BH |
2368 | #ifdef CONFIG_SFC_MTD |
2369 | INIT_LIST_HEAD(&efx->mtd_list); | |
2370 | #endif | |
8ceee660 BH |
2371 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2372 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2373 | efx->pci_dev = pci_dev; | |
62776d03 | 2374 | efx->msg_enable = debug; |
8ceee660 | 2375 | efx->state = STATE_INIT; |
8ceee660 | 2376 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2377 | |
2378 | efx->net_dev = net_dev; | |
8ceee660 BH |
2379 | spin_lock_init(&efx->stats_lock); |
2380 | mutex_init(&efx->mac_lock); | |
2381 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2382 | efx->mdio.dev = net_dev; |
766ca0fa | 2383 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2384 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2385 | |
2386 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2387 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2388 | if (!efx->channel[i]) | |
2389 | goto fail; | |
8ceee660 BH |
2390 | } |
2391 | ||
2392 | efx->type = type; | |
2393 | ||
8ceee660 BH |
2394 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2395 | ||
2396 | /* Higher numbered interrupt modes are less capable! */ | |
2397 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2398 | interrupt_mode); | |
2399 | ||
6977dc63 BH |
2400 | /* Would be good to use the net_dev name, but we're too early */ |
2401 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2402 | pci_name(pci_dev)); | |
2403 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2404 | if (!efx->workqueue) |
4642610c | 2405 | goto fail; |
8d9853d9 | 2406 | |
8ceee660 | 2407 | return 0; |
4642610c BH |
2408 | |
2409 | fail: | |
2410 | efx_fini_struct(efx); | |
2411 | return -ENOMEM; | |
8ceee660 BH |
2412 | } |
2413 | ||
2414 | static void efx_fini_struct(struct efx_nic *efx) | |
2415 | { | |
8313aca3 BH |
2416 | int i; |
2417 | ||
2418 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2419 | kfree(efx->channel[i]); | |
2420 | ||
8ceee660 BH |
2421 | if (efx->workqueue) { |
2422 | destroy_workqueue(efx->workqueue); | |
2423 | efx->workqueue = NULL; | |
2424 | } | |
2425 | } | |
2426 | ||
2427 | /************************************************************************** | |
2428 | * | |
2429 | * PCI interface | |
2430 | * | |
2431 | **************************************************************************/ | |
2432 | ||
2433 | /* Main body of final NIC shutdown code | |
2434 | * This is called only at module unload (or hotplug removal). | |
2435 | */ | |
2436 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2437 | { | |
64d8ad6d BH |
2438 | #ifdef CONFIG_RFS_ACCEL |
2439 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
2440 | efx->net_dev->rx_cpu_rmap = NULL; | |
2441 | #endif | |
7f967c01 | 2442 | efx_stop_interrupts(efx, false); |
152b6a62 | 2443 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2444 | efx_fini_port(efx); |
ef2b90ee | 2445 | efx->type->fini(efx); |
8ceee660 BH |
2446 | efx_fini_napi(efx); |
2447 | efx_remove_all(efx); | |
2448 | } | |
2449 | ||
2450 | /* Final NIC shutdown | |
2451 | * This is called only at module unload (or hotplug removal). | |
2452 | */ | |
2453 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2454 | { | |
2455 | struct efx_nic *efx; | |
2456 | ||
2457 | efx = pci_get_drvdata(pci_dev); | |
2458 | if (!efx) | |
2459 | return; | |
2460 | ||
2461 | /* Mark the NIC as fini, then stop the interface */ | |
2462 | rtnl_lock(); | |
2463 | efx->state = STATE_FINI; | |
2464 | dev_close(efx->net_dev); | |
2465 | ||
2466 | /* Allow any queued efx_resets() to complete */ | |
2467 | rtnl_unlock(); | |
2468 | ||
7f967c01 | 2469 | efx_stop_interrupts(efx, false); |
cd2d5b52 | 2470 | efx_sriov_fini(efx); |
8ceee660 BH |
2471 | efx_unregister_netdev(efx); |
2472 | ||
7dde596e BH |
2473 | efx_mtd_remove(efx); |
2474 | ||
8ceee660 BH |
2475 | /* Wait for any scheduled resets to complete. No more will be |
2476 | * scheduled from this point because efx_stop_all() has been | |
2477 | * called, we are no longer registered with driverlink, and | |
2478 | * the net_device's have been removed. */ | |
1ab00629 | 2479 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2480 | |
2481 | efx_pci_remove_main(efx); | |
2482 | ||
8ceee660 | 2483 | efx_fini_io(efx); |
62776d03 | 2484 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 BH |
2485 | |
2486 | pci_set_drvdata(pci_dev, NULL); | |
2487 | efx_fini_struct(efx); | |
2488 | free_netdev(efx->net_dev); | |
2489 | }; | |
2490 | ||
2491 | /* Main body of NIC initialisation | |
2492 | * This is called at module load (or hotplug insertion, theoretically). | |
2493 | */ | |
2494 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2495 | { | |
2496 | int rc; | |
2497 | ||
2498 | /* Do start-of-day initialisation */ | |
2499 | rc = efx_probe_all(efx); | |
2500 | if (rc) | |
2501 | goto fail1; | |
2502 | ||
e8f14992 | 2503 | efx_init_napi(efx); |
8ceee660 | 2504 | |
ef2b90ee | 2505 | rc = efx->type->init(efx); |
8ceee660 | 2506 | if (rc) { |
62776d03 BH |
2507 | netif_err(efx, probe, efx->net_dev, |
2508 | "failed to initialise NIC\n"); | |
278c0621 | 2509 | goto fail3; |
8ceee660 BH |
2510 | } |
2511 | ||
2512 | rc = efx_init_port(efx); | |
2513 | if (rc) { | |
62776d03 BH |
2514 | netif_err(efx, probe, efx->net_dev, |
2515 | "failed to initialise port\n"); | |
278c0621 | 2516 | goto fail4; |
8ceee660 BH |
2517 | } |
2518 | ||
152b6a62 | 2519 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2520 | if (rc) |
278c0621 | 2521 | goto fail5; |
7f967c01 | 2522 | efx_start_interrupts(efx, false); |
8ceee660 BH |
2523 | |
2524 | return 0; | |
2525 | ||
278c0621 | 2526 | fail5: |
8ceee660 | 2527 | efx_fini_port(efx); |
8ceee660 | 2528 | fail4: |
ef2b90ee | 2529 | efx->type->fini(efx); |
8ceee660 BH |
2530 | fail3: |
2531 | efx_fini_napi(efx); | |
8ceee660 BH |
2532 | efx_remove_all(efx); |
2533 | fail1: | |
2534 | return rc; | |
2535 | } | |
2536 | ||
2537 | /* NIC initialisation | |
2538 | * | |
2539 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2540 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2541 | * sets up and registers the network devices with the kernel and hooks |
2542 | * the interrupt service routine. It does not prepare the device for | |
2543 | * transmission; this is left to the first time one of the network | |
2544 | * interfaces is brought up (i.e. efx_net_open). | |
2545 | */ | |
2546 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2547 | const struct pci_device_id *entry) | |
2548 | { | |
6c8c2513 | 2549 | const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data; |
8ceee660 BH |
2550 | struct net_device *net_dev; |
2551 | struct efx_nic *efx; | |
fadac6aa | 2552 | int rc; |
8ceee660 BH |
2553 | |
2554 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2555 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2556 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2557 | if (!net_dev) |
2558 | return -ENOMEM; | |
c383b537 | 2559 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 | 2560 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2561 | NETIF_F_RXCSUM); |
738a8f4b BH |
2562 | if (type->offload_features & NETIF_F_V6_CSUM) |
2563 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2564 | /* Mask for features that also apply to VLAN devices */ |
2565 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2566 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2567 | NETIF_F_RXCSUM); | |
2568 | /* All offloads can be toggled */ | |
2569 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
767e468c | 2570 | efx = netdev_priv(net_dev); |
8ceee660 | 2571 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2572 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2573 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2574 | if (rc) | |
2575 | goto fail1; | |
2576 | ||
62776d03 | 2577 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2578 | "Solarflare NIC detected\n"); |
8ceee660 BH |
2579 | |
2580 | /* Set up basic I/O (BAR mappings etc) */ | |
2581 | rc = efx_init_io(efx); | |
2582 | if (rc) | |
2583 | goto fail2; | |
2584 | ||
fadac6aa | 2585 | rc = efx_pci_probe_main(efx); |
fa402b2e | 2586 | |
fadac6aa BH |
2587 | /* Serialise against efx_reset(). No more resets will be |
2588 | * scheduled since efx_stop_all() has been called, and we have | |
2589 | * not and never have been registered. | |
2590 | */ | |
2591 | cancel_work_sync(&efx->reset_work); | |
8ceee660 | 2592 | |
fadac6aa BH |
2593 | if (rc) |
2594 | goto fail3; | |
8ceee660 | 2595 | |
fadac6aa BH |
2596 | /* If there was a scheduled reset during probe, the NIC is |
2597 | * probably hosed anyway. | |
2598 | */ | |
2599 | if (efx->reset_pending) { | |
2600 | rc = -EIO; | |
8ceee660 BH |
2601 | goto fail4; |
2602 | } | |
2603 | ||
55edc6e6 BH |
2604 | /* Switch to the running state before we expose the device to the OS, |
2605 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2606 | efx->state = STATE_RUNNING; |
7dde596e | 2607 | |
8ceee660 BH |
2608 | rc = efx_register_netdev(efx); |
2609 | if (rc) | |
fadac6aa | 2610 | goto fail4; |
8ceee660 | 2611 | |
cd2d5b52 BH |
2612 | rc = efx_sriov_init(efx); |
2613 | if (rc) | |
2614 | netif_err(efx, probe, efx->net_dev, | |
2615 | "SR-IOV can't be enabled rc %d\n", rc); | |
2616 | ||
62776d03 | 2617 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 2618 | |
7c43161c | 2619 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 2620 | rtnl_lock(); |
7c43161c | 2621 | rc = efx_mtd_probe(efx); |
a5211bb5 | 2622 | rtnl_unlock(); |
7c43161c BH |
2623 | if (rc) |
2624 | netif_warn(efx, probe, efx->net_dev, | |
2625 | "failed to create MTDs (%d)\n", rc); | |
2626 | ||
8ceee660 BH |
2627 | return 0; |
2628 | ||
8ceee660 | 2629 | fail4: |
fadac6aa | 2630 | efx_pci_remove_main(efx); |
8ceee660 BH |
2631 | fail3: |
2632 | efx_fini_io(efx); | |
2633 | fail2: | |
2634 | efx_fini_struct(efx); | |
2635 | fail1: | |
5e2a911c | 2636 | WARN_ON(rc > 0); |
62776d03 | 2637 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2638 | free_netdev(net_dev); |
2639 | return rc; | |
2640 | } | |
2641 | ||
89c758fa BH |
2642 | static int efx_pm_freeze(struct device *dev) |
2643 | { | |
2644 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2645 | ||
2646 | efx->state = STATE_FINI; | |
2647 | ||
2648 | netif_device_detach(efx->net_dev); | |
2649 | ||
2650 | efx_stop_all(efx); | |
7f967c01 | 2651 | efx_stop_interrupts(efx, false); |
89c758fa BH |
2652 | |
2653 | return 0; | |
2654 | } | |
2655 | ||
2656 | static int efx_pm_thaw(struct device *dev) | |
2657 | { | |
2658 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2659 | ||
2660 | efx->state = STATE_INIT; | |
2661 | ||
7f967c01 | 2662 | efx_start_interrupts(efx, false); |
89c758fa BH |
2663 | |
2664 | mutex_lock(&efx->mac_lock); | |
2665 | efx->phy_op->reconfigure(efx); | |
2666 | mutex_unlock(&efx->mac_lock); | |
2667 | ||
2668 | efx_start_all(efx); | |
2669 | ||
2670 | netif_device_attach(efx->net_dev); | |
2671 | ||
2672 | efx->state = STATE_RUNNING; | |
2673 | ||
2674 | efx->type->resume_wol(efx); | |
2675 | ||
319ba649 SH |
2676 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2677 | queue_work(reset_workqueue, &efx->reset_work); | |
2678 | ||
89c758fa BH |
2679 | return 0; |
2680 | } | |
2681 | ||
2682 | static int efx_pm_poweroff(struct device *dev) | |
2683 | { | |
2684 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2685 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2686 | ||
2687 | efx->type->fini(efx); | |
2688 | ||
a7d529ae | 2689 | efx->reset_pending = 0; |
89c758fa BH |
2690 | |
2691 | pci_save_state(pci_dev); | |
2692 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2693 | } | |
2694 | ||
2695 | /* Used for both resume and restore */ | |
2696 | static int efx_pm_resume(struct device *dev) | |
2697 | { | |
2698 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2699 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2700 | int rc; | |
2701 | ||
2702 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2703 | if (rc) | |
2704 | return rc; | |
2705 | pci_restore_state(pci_dev); | |
2706 | rc = pci_enable_device(pci_dev); | |
2707 | if (rc) | |
2708 | return rc; | |
2709 | pci_set_master(efx->pci_dev); | |
2710 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2711 | if (rc) | |
2712 | return rc; | |
2713 | rc = efx->type->init(efx); | |
2714 | if (rc) | |
2715 | return rc; | |
2716 | efx_pm_thaw(dev); | |
2717 | return 0; | |
2718 | } | |
2719 | ||
2720 | static int efx_pm_suspend(struct device *dev) | |
2721 | { | |
2722 | int rc; | |
2723 | ||
2724 | efx_pm_freeze(dev); | |
2725 | rc = efx_pm_poweroff(dev); | |
2726 | if (rc) | |
2727 | efx_pm_resume(dev); | |
2728 | return rc; | |
2729 | } | |
2730 | ||
18e83e4c | 2731 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
2732 | .suspend = efx_pm_suspend, |
2733 | .resume = efx_pm_resume, | |
2734 | .freeze = efx_pm_freeze, | |
2735 | .thaw = efx_pm_thaw, | |
2736 | .poweroff = efx_pm_poweroff, | |
2737 | .restore = efx_pm_resume, | |
2738 | }; | |
2739 | ||
8ceee660 | 2740 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2741 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2742 | .id_table = efx_pci_table, |
2743 | .probe = efx_pci_probe, | |
2744 | .remove = efx_pci_remove, | |
89c758fa | 2745 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2746 | }; |
2747 | ||
2748 | /************************************************************************** | |
2749 | * | |
2750 | * Kernel module interface | |
2751 | * | |
2752 | *************************************************************************/ | |
2753 | ||
2754 | module_param(interrupt_mode, uint, 0444); | |
2755 | MODULE_PARM_DESC(interrupt_mode, | |
2756 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2757 | ||
2758 | static int __init efx_init_module(void) | |
2759 | { | |
2760 | int rc; | |
2761 | ||
2762 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2763 | ||
2764 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2765 | if (rc) | |
2766 | goto err_notifier; | |
2767 | ||
cd2d5b52 BH |
2768 | rc = efx_init_sriov(); |
2769 | if (rc) | |
2770 | goto err_sriov; | |
2771 | ||
1ab00629 SH |
2772 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2773 | if (!reset_workqueue) { | |
2774 | rc = -ENOMEM; | |
2775 | goto err_reset; | |
2776 | } | |
8ceee660 BH |
2777 | |
2778 | rc = pci_register_driver(&efx_pci_driver); | |
2779 | if (rc < 0) | |
2780 | goto err_pci; | |
2781 | ||
2782 | return 0; | |
2783 | ||
2784 | err_pci: | |
1ab00629 SH |
2785 | destroy_workqueue(reset_workqueue); |
2786 | err_reset: | |
cd2d5b52 BH |
2787 | efx_fini_sriov(); |
2788 | err_sriov: | |
8ceee660 BH |
2789 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2790 | err_notifier: | |
2791 | return rc; | |
2792 | } | |
2793 | ||
2794 | static void __exit efx_exit_module(void) | |
2795 | { | |
2796 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2797 | ||
2798 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2799 | destroy_workqueue(reset_workqueue); |
cd2d5b52 | 2800 | efx_fini_sriov(); |
8ceee660 BH |
2801 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2802 | ||
2803 | } | |
2804 | ||
2805 | module_init(efx_init_module); | |
2806 | module_exit(efx_exit_module); | |
2807 | ||
906bb26c BH |
2808 | MODULE_AUTHOR("Solarflare Communications and " |
2809 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2810 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2811 | MODULE_LICENSE("GPL"); | |
2812 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |