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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
64d8ad6d | 24 | #include <linux/cpu_rmap.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 41 | const char *const efx_loopback_mode_names[] = { |
c459302d | 42 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
47 | [LOOPBACK_XAUI] = "XAUI", |
48 | [LOOPBACK_GMII] = "GMII", | |
49 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
50 | [LOOPBACK_XGBR] = "XGBR", |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
58 | [LOOPBACK_PCS] = "PCS", |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 65 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
69 | }; |
70 | ||
c459302d | 71 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 72 | const char *const efx_reset_type_names[] = { |
c459302d BH |
73 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
74 | [RESET_TYPE_ALL] = "ALL", | |
75 | [RESET_TYPE_WORLD] = "WORLD", | |
76 | [RESET_TYPE_DISABLE] = "DISABLE", | |
77 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
78 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
79 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
80 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
81 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 83 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
84 | }; |
85 | ||
8ceee660 BH |
86 | #define EFX_MAX_MTU (9 * 1024) |
87 | ||
1ab00629 SH |
88 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
89 | * queued onto this work queue. This is not a per-nic work queue, because | |
90 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
91 | */ | |
92 | static struct workqueue_struct *reset_workqueue; | |
93 | ||
8ceee660 BH |
94 | /************************************************************************** |
95 | * | |
96 | * Configurable values | |
97 | * | |
98 | *************************************************************************/ | |
99 | ||
8ceee660 BH |
100 | /* |
101 | * Use separate channels for TX and RX events | |
102 | * | |
28b581ab NT |
103 | * Set this to 1 to use separate channels for TX and RX. It allows us |
104 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 105 | * |
28b581ab | 106 | * This is only used in MSI-X interrupt mode |
8ceee660 | 107 | */ |
28b581ab | 108 | static unsigned int separate_tx_channels; |
8313aca3 | 109 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
110 | MODULE_PARM_DESC(separate_tx_channels, |
111 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
112 | |
113 | /* This is the weight assigned to each of the (per-channel) virtual | |
114 | * NAPI devices. | |
115 | */ | |
116 | static int napi_weight = 64; | |
117 | ||
118 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
119 | * monitor. On Falcon-based NICs, this will: |
120 | * - Check the on-board hardware monitor; | |
121 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 122 | */ |
d215697f | 123 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 124 | |
8ceee660 BH |
125 | /* Initial interrupt moderation settings. They can be modified after |
126 | * module load with ethtool. | |
127 | * | |
128 | * The default for RX should strike a balance between increasing the | |
129 | * round-trip latency and reducing overhead. | |
130 | */ | |
131 | static unsigned int rx_irq_mod_usec = 60; | |
132 | ||
133 | /* Initial interrupt moderation settings. They can be modified after | |
134 | * module load with ethtool. | |
135 | * | |
136 | * This default is chosen to ensure that a 10G link does not go idle | |
137 | * while a TX queue is stopped after it has become full. A queue is | |
138 | * restarted when it drops below half full. The time this takes (assuming | |
139 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
140 | * 512 / 3 * 1.2 = 205 usec. | |
141 | */ | |
142 | static unsigned int tx_irq_mod_usec = 150; | |
143 | ||
144 | /* This is the first interrupt mode to try out of: | |
145 | * 0 => MSI-X | |
146 | * 1 => MSI | |
147 | * 2 => legacy | |
148 | */ | |
149 | static unsigned int interrupt_mode; | |
150 | ||
151 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
152 | * i.e. the number of CPUs among which we may distribute simultaneous | |
153 | * interrupt handling. | |
154 | * | |
155 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 156 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
157 | */ |
158 | static unsigned int rss_cpus; | |
159 | module_param(rss_cpus, uint, 0444); | |
160 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
161 | ||
84ae48fe BH |
162 | static int phy_flash_cfg; |
163 | module_param(phy_flash_cfg, int, 0644); | |
164 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
165 | ||
6fb70fd1 BH |
166 | static unsigned irq_adapt_low_thresh = 10000; |
167 | module_param(irq_adapt_low_thresh, uint, 0644); | |
168 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
169 | "Threshold score for reducing IRQ moderation"); | |
170 | ||
171 | static unsigned irq_adapt_high_thresh = 20000; | |
172 | module_param(irq_adapt_high_thresh, uint, 0644); | |
173 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
174 | "Threshold score for increasing IRQ moderation"); | |
175 | ||
62776d03 BH |
176 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
177 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
178 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
179 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
180 | module_param(debug, uint, 0); | |
181 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
182 | ||
8ceee660 BH |
183 | /************************************************************************** |
184 | * | |
185 | * Utility functions and prototypes | |
186 | * | |
187 | *************************************************************************/ | |
4642610c BH |
188 | |
189 | static void efx_remove_channels(struct efx_nic *efx); | |
8ceee660 | 190 | static void efx_remove_port(struct efx_nic *efx); |
e8f14992 | 191 | static void efx_init_napi(struct efx_nic *efx); |
8ceee660 | 192 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 193 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
194 | static void efx_fini_struct(struct efx_nic *efx); |
195 | static void efx_start_all(struct efx_nic *efx); | |
196 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
197 | |
198 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
199 | do { \ | |
332c1ce9 BH |
200 | if ((efx->state == STATE_RUNNING) || \ |
201 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
202 | ASSERT_RTNL(); \ |
203 | } while (0) | |
204 | ||
205 | /************************************************************************** | |
206 | * | |
207 | * Event queue processing | |
208 | * | |
209 | *************************************************************************/ | |
210 | ||
211 | /* Process channel's event queue | |
212 | * | |
213 | * This function is responsible for processing the event queue of a | |
214 | * single channel. The caller must guarantee that this function will | |
215 | * never be concurrently called more than once on the same channel, | |
216 | * though different channels may be being processed concurrently. | |
217 | */ | |
fa236e18 | 218 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 219 | { |
42cbe2d7 | 220 | struct efx_nic *efx = channel->efx; |
fa236e18 | 221 | int spent; |
8ceee660 | 222 | |
a7d529ae | 223 | if (unlikely(efx->reset_pending || !channel->enabled)) |
42cbe2d7 | 224 | return 0; |
8ceee660 | 225 | |
fa236e18 BH |
226 | spent = efx_nic_process_eventq(channel, budget); |
227 | if (spent == 0) | |
42cbe2d7 | 228 | return 0; |
8ceee660 BH |
229 | |
230 | /* Deliver last RX packet. */ | |
231 | if (channel->rx_pkt) { | |
232 | __efx_rx_packet(channel, channel->rx_pkt, | |
233 | channel->rx_pkt_csummed); | |
234 | channel->rx_pkt = NULL; | |
235 | } | |
236 | ||
8ceee660 BH |
237 | efx_rx_strategy(channel); |
238 | ||
f7d12cdc | 239 | efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel)); |
8ceee660 | 240 | |
fa236e18 | 241 | return spent; |
8ceee660 BH |
242 | } |
243 | ||
244 | /* Mark channel as finished processing | |
245 | * | |
246 | * Note that since we will not receive further interrupts for this | |
247 | * channel before we finish processing and call the eventq_read_ack() | |
248 | * method, there is no need to use the interrupt hold-off timers. | |
249 | */ | |
250 | static inline void efx_channel_processed(struct efx_channel *channel) | |
251 | { | |
5b9e207c BH |
252 | /* The interrupt handler for this channel may set work_pending |
253 | * as soon as we acknowledge the events we've seen. Make sure | |
254 | * it's cleared before then. */ | |
dc8cfa55 | 255 | channel->work_pending = false; |
5b9e207c BH |
256 | smp_wmb(); |
257 | ||
152b6a62 | 258 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
259 | } |
260 | ||
261 | /* NAPI poll handler | |
262 | * | |
263 | * NAPI guarantees serialisation of polls of the same device, which | |
264 | * provides the guarantee required by efx_process_channel(). | |
265 | */ | |
266 | static int efx_poll(struct napi_struct *napi, int budget) | |
267 | { | |
268 | struct efx_channel *channel = | |
269 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 270 | struct efx_nic *efx = channel->efx; |
fa236e18 | 271 | int spent; |
8ceee660 | 272 | |
62776d03 BH |
273 | netif_vdbg(efx, intr, efx->net_dev, |
274 | "channel %d NAPI poll executing on CPU %d\n", | |
275 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 276 | |
fa236e18 | 277 | spent = efx_process_channel(channel, budget); |
8ceee660 | 278 | |
fa236e18 | 279 | if (spent < budget) { |
a4900ac9 | 280 | if (channel->channel < efx->n_rx_channels && |
6fb70fd1 BH |
281 | efx->irq_rx_adaptive && |
282 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
283 | if (unlikely(channel->irq_mod_score < |
284 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
285 | if (channel->irq_moderation > 1) { |
286 | channel->irq_moderation -= 1; | |
ef2b90ee | 287 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 288 | } |
6fb70fd1 BH |
289 | } else if (unlikely(channel->irq_mod_score > |
290 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
291 | if (channel->irq_moderation < |
292 | efx->irq_rx_moderation) { | |
293 | channel->irq_moderation += 1; | |
ef2b90ee | 294 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 295 | } |
6fb70fd1 | 296 | } |
6fb70fd1 BH |
297 | channel->irq_count = 0; |
298 | channel->irq_mod_score = 0; | |
299 | } | |
300 | ||
64d8ad6d BH |
301 | efx_filter_rfs_expire(channel); |
302 | ||
8ceee660 | 303 | /* There is no race here; although napi_disable() will |
288379f0 | 304 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
305 | * since efx_channel_processed() will have no effect if |
306 | * interrupts have already been disabled. | |
307 | */ | |
288379f0 | 308 | napi_complete(napi); |
8ceee660 BH |
309 | efx_channel_processed(channel); |
310 | } | |
311 | ||
fa236e18 | 312 | return spent; |
8ceee660 BH |
313 | } |
314 | ||
315 | /* Process the eventq of the specified channel immediately on this CPU | |
316 | * | |
317 | * Disable hardware generated interrupts, wait for any existing | |
318 | * processing to finish, then directly poll (and ack ) the eventq. | |
319 | * Finally reenable NAPI and interrupts. | |
320 | * | |
d4fabcc8 BH |
321 | * This is for use only during a loopback self-test. It must not |
322 | * deliver any packets up the stack as this can result in deadlock. | |
8ceee660 BH |
323 | */ |
324 | void efx_process_channel_now(struct efx_channel *channel) | |
325 | { | |
326 | struct efx_nic *efx = channel->efx; | |
327 | ||
8313aca3 | 328 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 | 329 | BUG_ON(!channel->enabled); |
d4fabcc8 | 330 | BUG_ON(!efx->loopback_selftest); |
8ceee660 BH |
331 | |
332 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 333 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 334 | if (efx->legacy_irq) { |
8ceee660 | 335 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
336 | efx->legacy_irq_enabled = false; |
337 | } | |
64ee3120 | 338 | if (channel->irq) |
8ceee660 BH |
339 | synchronize_irq(channel->irq); |
340 | ||
341 | /* Wait for any NAPI processing to complete */ | |
342 | napi_disable(&channel->napi_str); | |
343 | ||
344 | /* Poll the channel */ | |
ecc910f5 | 345 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
346 | |
347 | /* Ack the eventq. This may cause an interrupt to be generated | |
348 | * when they are reenabled */ | |
349 | efx_channel_processed(channel); | |
350 | ||
351 | napi_enable(&channel->napi_str); | |
94dec6a2 BH |
352 | if (efx->legacy_irq) |
353 | efx->legacy_irq_enabled = true; | |
152b6a62 | 354 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
355 | } |
356 | ||
357 | /* Create event queue | |
358 | * Event queue memory allocations are done only once. If the channel | |
359 | * is reset, the memory buffer will be reused; this guards against | |
360 | * errors during channel reset and also simplifies interrupt handling. | |
361 | */ | |
362 | static int efx_probe_eventq(struct efx_channel *channel) | |
363 | { | |
ecc910f5 SH |
364 | struct efx_nic *efx = channel->efx; |
365 | unsigned long entries; | |
366 | ||
62776d03 BH |
367 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
368 | "chan %d create event queue\n", channel->channel); | |
8ceee660 | 369 | |
ecc910f5 SH |
370 | /* Build an event queue with room for one event per tx and rx buffer, |
371 | * plus some extra for link state events and MCDI completions. */ | |
372 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
373 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
374 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
375 | ||
152b6a62 | 376 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
377 | } |
378 | ||
379 | /* Prepare channel's event queue */ | |
bc3c90a2 | 380 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 381 | { |
62776d03 BH |
382 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
383 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
384 | |
385 | channel->eventq_read_ptr = 0; | |
386 | ||
152b6a62 | 387 | efx_nic_init_eventq(channel); |
8ceee660 BH |
388 | } |
389 | ||
390 | static void efx_fini_eventq(struct efx_channel *channel) | |
391 | { | |
62776d03 BH |
392 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
393 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 394 | |
152b6a62 | 395 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
396 | } |
397 | ||
398 | static void efx_remove_eventq(struct efx_channel *channel) | |
399 | { | |
62776d03 BH |
400 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
401 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 402 | |
152b6a62 | 403 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
404 | } |
405 | ||
406 | /************************************************************************** | |
407 | * | |
408 | * Channel handling | |
409 | * | |
410 | *************************************************************************/ | |
411 | ||
4642610c BH |
412 | /* Allocate and initialise a channel structure, optionally copying |
413 | * parameters (but not resources) from an old channel structure. */ | |
414 | static struct efx_channel * | |
415 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
416 | { | |
417 | struct efx_channel *channel; | |
418 | struct efx_rx_queue *rx_queue; | |
419 | struct efx_tx_queue *tx_queue; | |
420 | int j; | |
421 | ||
422 | if (old_channel) { | |
423 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); | |
424 | if (!channel) | |
425 | return NULL; | |
426 | ||
427 | *channel = *old_channel; | |
428 | ||
e8f14992 | 429 | channel->napi_dev = NULL; |
4642610c BH |
430 | memset(&channel->eventq, 0, sizeof(channel->eventq)); |
431 | ||
432 | rx_queue = &channel->rx_queue; | |
433 | rx_queue->buffer = NULL; | |
434 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
435 | ||
436 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
437 | tx_queue = &channel->tx_queue[j]; | |
438 | if (tx_queue->channel) | |
439 | tx_queue->channel = channel; | |
440 | tx_queue->buffer = NULL; | |
441 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
442 | } | |
443 | } else { | |
444 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); | |
445 | if (!channel) | |
446 | return NULL; | |
447 | ||
448 | channel->efx = efx; | |
449 | channel->channel = i; | |
450 | ||
451 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
452 | tx_queue = &channel->tx_queue[j]; | |
453 | tx_queue->efx = efx; | |
454 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
455 | tx_queue->channel = channel; | |
456 | } | |
457 | } | |
458 | ||
4642610c BH |
459 | rx_queue = &channel->rx_queue; |
460 | rx_queue->efx = efx; | |
461 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
462 | (unsigned long)rx_queue); | |
463 | ||
464 | return channel; | |
465 | } | |
466 | ||
8ceee660 BH |
467 | static int efx_probe_channel(struct efx_channel *channel) |
468 | { | |
469 | struct efx_tx_queue *tx_queue; | |
470 | struct efx_rx_queue *rx_queue; | |
471 | int rc; | |
472 | ||
62776d03 BH |
473 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
474 | "creating channel %d\n", channel->channel); | |
8ceee660 BH |
475 | |
476 | rc = efx_probe_eventq(channel); | |
477 | if (rc) | |
478 | goto fail1; | |
479 | ||
480 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
481 | rc = efx_probe_tx_queue(tx_queue); | |
482 | if (rc) | |
483 | goto fail2; | |
484 | } | |
485 | ||
486 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
487 | rc = efx_probe_rx_queue(rx_queue); | |
488 | if (rc) | |
489 | goto fail3; | |
490 | } | |
491 | ||
492 | channel->n_rx_frm_trunc = 0; | |
493 | ||
494 | return 0; | |
495 | ||
496 | fail3: | |
497 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
498 | efx_remove_rx_queue(rx_queue); | |
499 | fail2: | |
500 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
501 | efx_remove_tx_queue(tx_queue); | |
502 | fail1: | |
503 | return rc; | |
504 | } | |
505 | ||
506 | ||
56536e9c BH |
507 | static void efx_set_channel_names(struct efx_nic *efx) |
508 | { | |
509 | struct efx_channel *channel; | |
510 | const char *type = ""; | |
511 | int number; | |
512 | ||
513 | efx_for_each_channel(channel, efx) { | |
514 | number = channel->channel; | |
a4900ac9 BH |
515 | if (efx->n_channels > efx->n_rx_channels) { |
516 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
517 | type = "-rx"; |
518 | } else { | |
519 | type = "-tx"; | |
a4900ac9 | 520 | number -= efx->n_rx_channels; |
56536e9c BH |
521 | } |
522 | } | |
4642610c BH |
523 | snprintf(efx->channel_name[channel->channel], |
524 | sizeof(efx->channel_name[0]), | |
56536e9c BH |
525 | "%s%s-%d", efx->name, type, number); |
526 | } | |
527 | } | |
528 | ||
4642610c BH |
529 | static int efx_probe_channels(struct efx_nic *efx) |
530 | { | |
531 | struct efx_channel *channel; | |
532 | int rc; | |
533 | ||
534 | /* Restart special buffer allocation */ | |
535 | efx->next_buffer_table = 0; | |
536 | ||
537 | efx_for_each_channel(channel, efx) { | |
538 | rc = efx_probe_channel(channel); | |
539 | if (rc) { | |
540 | netif_err(efx, probe, efx->net_dev, | |
541 | "failed to create channel %d\n", | |
542 | channel->channel); | |
543 | goto fail; | |
544 | } | |
545 | } | |
546 | efx_set_channel_names(efx); | |
547 | ||
548 | return 0; | |
549 | ||
550 | fail: | |
551 | efx_remove_channels(efx); | |
552 | return rc; | |
553 | } | |
554 | ||
8ceee660 BH |
555 | /* Channels are shutdown and reinitialised whilst the NIC is running |
556 | * to propagate configuration changes (mtu, checksum offload), or | |
557 | * to clear hardware error conditions | |
558 | */ | |
bc3c90a2 | 559 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
560 | { |
561 | struct efx_tx_queue *tx_queue; | |
562 | struct efx_rx_queue *rx_queue; | |
563 | struct efx_channel *channel; | |
8ceee660 | 564 | |
f7f13b0b BH |
565 | /* Calculate the rx buffer allocation parameters required to |
566 | * support the current MTU, including padding for header | |
567 | * alignment and overruns. | |
568 | */ | |
569 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
570 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 571 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 572 | efx->type->rx_buffer_padding); |
62b330ba SH |
573 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
574 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
575 | |
576 | /* Initialise the channels */ | |
577 | efx_for_each_channel(channel, efx) { | |
62776d03 BH |
578 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
579 | "init chan %d\n", channel->channel); | |
8ceee660 | 580 | |
bc3c90a2 | 581 | efx_init_eventq(channel); |
8ceee660 | 582 | |
bc3c90a2 BH |
583 | efx_for_each_channel_tx_queue(tx_queue, channel) |
584 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
585 | |
586 | /* The rx buffer allocation strategy is MTU dependent */ | |
587 | efx_rx_strategy(channel); | |
588 | ||
bc3c90a2 BH |
589 | efx_for_each_channel_rx_queue(rx_queue, channel) |
590 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
591 | |
592 | WARN_ON(channel->rx_pkt != NULL); | |
593 | efx_rx_strategy(channel); | |
594 | } | |
8ceee660 BH |
595 | } |
596 | ||
597 | /* This enables event queue processing and packet transmission. | |
598 | * | |
599 | * Note that this function is not allowed to fail, since that would | |
600 | * introduce too much complexity into the suspend/resume path. | |
601 | */ | |
602 | static void efx_start_channel(struct efx_channel *channel) | |
603 | { | |
604 | struct efx_rx_queue *rx_queue; | |
605 | ||
62776d03 BH |
606 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, |
607 | "starting chan %d\n", channel->channel); | |
8ceee660 | 608 | |
5b9e207c BH |
609 | /* The interrupt handler for this channel may set work_pending |
610 | * as soon as we enable it. Make sure it's cleared before | |
611 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
612 | channel->work_pending = false; |
613 | channel->enabled = true; | |
5b9e207c | 614 | smp_wmb(); |
8ceee660 | 615 | |
90d683af | 616 | /* Fill the queues before enabling NAPI */ |
8ceee660 BH |
617 | efx_for_each_channel_rx_queue(rx_queue, channel) |
618 | efx_fast_push_rx_descriptors(rx_queue); | |
90d683af SH |
619 | |
620 | napi_enable(&channel->napi_str); | |
8ceee660 BH |
621 | } |
622 | ||
623 | /* This disables event queue processing and packet transmission. | |
624 | * This function does not guarantee that all queue processing | |
625 | * (e.g. RX refill) is complete. | |
626 | */ | |
627 | static void efx_stop_channel(struct efx_channel *channel) | |
628 | { | |
8ceee660 BH |
629 | if (!channel->enabled) |
630 | return; | |
631 | ||
62776d03 BH |
632 | netif_dbg(channel->efx, ifdown, channel->efx->net_dev, |
633 | "stop chan %d\n", channel->channel); | |
8ceee660 | 634 | |
dc8cfa55 | 635 | channel->enabled = false; |
8ceee660 | 636 | napi_disable(&channel->napi_str); |
8ceee660 BH |
637 | } |
638 | ||
639 | static void efx_fini_channels(struct efx_nic *efx) | |
640 | { | |
641 | struct efx_channel *channel; | |
642 | struct efx_tx_queue *tx_queue; | |
643 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 644 | int rc; |
8ceee660 BH |
645 | |
646 | EFX_ASSERT_RESET_SERIALISED(efx); | |
647 | BUG_ON(efx->port_enabled); | |
648 | ||
152b6a62 | 649 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
650 | if (rc && EFX_WORKAROUND_7803(efx)) { |
651 | /* Schedule a reset to recover from the flush failure. The | |
652 | * descriptor caches reference memory we're about to free, | |
653 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
654 | * the MACs because of the pending reset. */ | |
62776d03 BH |
655 | netif_err(efx, drv, efx->net_dev, |
656 | "Resetting to recover from flush failure\n"); | |
fd371e32 SH |
657 | efx_schedule_reset(efx, RESET_TYPE_ALL); |
658 | } else if (rc) { | |
62776d03 | 659 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); |
fd371e32 | 660 | } else { |
62776d03 BH |
661 | netif_dbg(efx, drv, efx->net_dev, |
662 | "successfully flushed all queues\n"); | |
fd371e32 | 663 | } |
6bc5d3a9 | 664 | |
8ceee660 | 665 | efx_for_each_channel(channel, efx) { |
62776d03 BH |
666 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
667 | "shut down chan %d\n", channel->channel); | |
8ceee660 BH |
668 | |
669 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
670 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 671 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 672 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
673 | efx_fini_eventq(channel); |
674 | } | |
675 | } | |
676 | ||
677 | static void efx_remove_channel(struct efx_channel *channel) | |
678 | { | |
679 | struct efx_tx_queue *tx_queue; | |
680 | struct efx_rx_queue *rx_queue; | |
681 | ||
62776d03 BH |
682 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
683 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
684 | |
685 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
686 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 687 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
688 | efx_remove_tx_queue(tx_queue); |
689 | efx_remove_eventq(channel); | |
8ceee660 BH |
690 | } |
691 | ||
4642610c BH |
692 | static void efx_remove_channels(struct efx_nic *efx) |
693 | { | |
694 | struct efx_channel *channel; | |
695 | ||
696 | efx_for_each_channel(channel, efx) | |
697 | efx_remove_channel(channel); | |
698 | } | |
699 | ||
700 | int | |
701 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
702 | { | |
703 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
704 | u32 old_rxq_entries, old_txq_entries; | |
705 | unsigned i; | |
706 | int rc; | |
707 | ||
708 | efx_stop_all(efx); | |
709 | efx_fini_channels(efx); | |
710 | ||
711 | /* Clone channels */ | |
712 | memset(other_channel, 0, sizeof(other_channel)); | |
713 | for (i = 0; i < efx->n_channels; i++) { | |
714 | channel = efx_alloc_channel(efx, i, efx->channel[i]); | |
715 | if (!channel) { | |
716 | rc = -ENOMEM; | |
717 | goto out; | |
718 | } | |
719 | other_channel[i] = channel; | |
720 | } | |
721 | ||
722 | /* Swap entry counts and channel pointers */ | |
723 | old_rxq_entries = efx->rxq_entries; | |
724 | old_txq_entries = efx->txq_entries; | |
725 | efx->rxq_entries = rxq_entries; | |
726 | efx->txq_entries = txq_entries; | |
727 | for (i = 0; i < efx->n_channels; i++) { | |
728 | channel = efx->channel[i]; | |
729 | efx->channel[i] = other_channel[i]; | |
730 | other_channel[i] = channel; | |
731 | } | |
732 | ||
733 | rc = efx_probe_channels(efx); | |
734 | if (rc) | |
735 | goto rollback; | |
736 | ||
e8f14992 BH |
737 | efx_init_napi(efx); |
738 | ||
4642610c | 739 | /* Destroy old channels */ |
e8f14992 BH |
740 | for (i = 0; i < efx->n_channels; i++) { |
741 | efx_fini_napi_channel(other_channel[i]); | |
4642610c | 742 | efx_remove_channel(other_channel[i]); |
e8f14992 | 743 | } |
4642610c BH |
744 | out: |
745 | /* Free unused channel structures */ | |
746 | for (i = 0; i < efx->n_channels; i++) | |
747 | kfree(other_channel[i]); | |
748 | ||
749 | efx_init_channels(efx); | |
750 | efx_start_all(efx); | |
751 | return rc; | |
752 | ||
753 | rollback: | |
754 | /* Swap back */ | |
755 | efx->rxq_entries = old_rxq_entries; | |
756 | efx->txq_entries = old_txq_entries; | |
757 | for (i = 0; i < efx->n_channels; i++) { | |
758 | channel = efx->channel[i]; | |
759 | efx->channel[i] = other_channel[i]; | |
760 | other_channel[i] = channel; | |
761 | } | |
762 | goto out; | |
763 | } | |
764 | ||
90d683af | 765 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 766 | { |
90d683af | 767 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
768 | } |
769 | ||
770 | /************************************************************************** | |
771 | * | |
772 | * Port handling | |
773 | * | |
774 | **************************************************************************/ | |
775 | ||
776 | /* This ensures that the kernel is kept informed (via | |
777 | * netif_carrier_on/off) of the link status, and also maintains the | |
778 | * link status's stop on the port's TX queue. | |
779 | */ | |
fdaa9aed | 780 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 781 | { |
eb50c0d6 BH |
782 | struct efx_link_state *link_state = &efx->link_state; |
783 | ||
8ceee660 BH |
784 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
785 | * that no events are triggered between unregister_netdev() and the | |
786 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
787 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
788 | if (!netif_running(efx->net_dev)) | |
789 | return; | |
790 | ||
eb50c0d6 | 791 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
792 | efx->n_link_state_changes++; |
793 | ||
eb50c0d6 | 794 | if (link_state->up) |
8ceee660 BH |
795 | netif_carrier_on(efx->net_dev); |
796 | else | |
797 | netif_carrier_off(efx->net_dev); | |
798 | } | |
799 | ||
800 | /* Status message for kernel log */ | |
eb50c0d6 | 801 | if (link_state->up) { |
62776d03 BH |
802 | netif_info(efx, link, efx->net_dev, |
803 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
804 | link_state->speed, link_state->fd ? "full" : "half", | |
805 | efx->net_dev->mtu, | |
806 | (efx->promiscuous ? " [PROMISC]" : "")); | |
8ceee660 | 807 | } else { |
62776d03 | 808 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
809 | } |
810 | ||
811 | } | |
812 | ||
d3245b28 BH |
813 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
814 | { | |
815 | efx->link_advertising = advertising; | |
816 | if (advertising) { | |
817 | if (advertising & ADVERTISED_Pause) | |
818 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
819 | else | |
820 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
821 | if (advertising & ADVERTISED_Asym_Pause) | |
822 | efx->wanted_fc ^= EFX_FC_TX; | |
823 | } | |
824 | } | |
825 | ||
b5626946 | 826 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
827 | { |
828 | efx->wanted_fc = wanted_fc; | |
829 | if (efx->link_advertising) { | |
830 | if (wanted_fc & EFX_FC_RX) | |
831 | efx->link_advertising |= (ADVERTISED_Pause | | |
832 | ADVERTISED_Asym_Pause); | |
833 | else | |
834 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
835 | ADVERTISED_Asym_Pause); | |
836 | if (wanted_fc & EFX_FC_TX) | |
837 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
838 | } | |
839 | } | |
840 | ||
115122af BH |
841 | static void efx_fini_port(struct efx_nic *efx); |
842 | ||
d3245b28 BH |
843 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
844 | * the MAC appropriately. All other PHY configuration changes are pushed | |
845 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
846 | * through efx_monitor(). | |
847 | * | |
848 | * Callers must hold the mac_lock | |
849 | */ | |
850 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 851 | { |
d3245b28 BH |
852 | enum efx_phy_mode phy_mode; |
853 | int rc; | |
8ceee660 | 854 | |
d3245b28 | 855 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 856 | |
a816f75a BH |
857 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
858 | if (efx_dev_registered(efx)) { | |
859 | netif_addr_lock_bh(efx->net_dev); | |
860 | netif_addr_unlock_bh(efx->net_dev); | |
861 | } | |
862 | ||
d3245b28 BH |
863 | /* Disable PHY transmit in mac level loopbacks */ |
864 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
865 | if (LOOPBACK_INTERNAL(efx)) |
866 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
867 | else | |
868 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 869 | |
d3245b28 | 870 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 871 | |
d3245b28 BH |
872 | if (rc) |
873 | efx->phy_mode = phy_mode; | |
177dfcd8 | 874 | |
d3245b28 | 875 | return rc; |
8ceee660 BH |
876 | } |
877 | ||
878 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
879 | * disabled. */ | |
d3245b28 | 880 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 881 | { |
d3245b28 BH |
882 | int rc; |
883 | ||
8ceee660 BH |
884 | EFX_ASSERT_RESET_SERIALISED(efx); |
885 | ||
886 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 887 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 888 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
889 | |
890 | return rc; | |
8ceee660 BH |
891 | } |
892 | ||
8be4f3e6 BH |
893 | /* Asynchronous work item for changing MAC promiscuity and multicast |
894 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
895 | * MAC directly. */ | |
766ca0fa BH |
896 | static void efx_mac_work(struct work_struct *data) |
897 | { | |
898 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
899 | ||
900 | mutex_lock(&efx->mac_lock); | |
8be4f3e6 | 901 | if (efx->port_enabled) { |
ef2b90ee | 902 | efx->type->push_multicast_hash(efx); |
710b208d | 903 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 904 | } |
766ca0fa BH |
905 | mutex_unlock(&efx->mac_lock); |
906 | } | |
907 | ||
8ceee660 BH |
908 | static int efx_probe_port(struct efx_nic *efx) |
909 | { | |
910 | int rc; | |
911 | ||
62776d03 | 912 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 913 | |
ff3b00a0 SH |
914 | if (phy_flash_cfg) |
915 | efx->phy_mode = PHY_MODE_SPECIAL; | |
916 | ||
ef2b90ee BH |
917 | /* Connect up MAC/PHY operations table */ |
918 | rc = efx->type->probe_port(efx); | |
8ceee660 | 919 | if (rc) |
e42de262 | 920 | return rc; |
8ceee660 | 921 | |
e332bcb3 BH |
922 | /* Initialise MAC address to permanent address */ |
923 | memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); | |
8ceee660 BH |
924 | |
925 | return 0; | |
8ceee660 BH |
926 | } |
927 | ||
928 | static int efx_init_port(struct efx_nic *efx) | |
929 | { | |
930 | int rc; | |
931 | ||
62776d03 | 932 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 933 | |
1dfc5cea BH |
934 | mutex_lock(&efx->mac_lock); |
935 | ||
177dfcd8 | 936 | rc = efx->phy_op->init(efx); |
8ceee660 | 937 | if (rc) |
1dfc5cea | 938 | goto fail1; |
8ceee660 | 939 | |
dc8cfa55 | 940 | efx->port_initialized = true; |
1dfc5cea | 941 | |
d3245b28 BH |
942 | /* Reconfigure the MAC before creating dma queues (required for |
943 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 944 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
945 | |
946 | /* Ensure the PHY advertises the correct flow control settings */ | |
947 | rc = efx->phy_op->reconfigure(efx); | |
948 | if (rc) | |
949 | goto fail2; | |
950 | ||
1dfc5cea | 951 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 952 | return 0; |
177dfcd8 | 953 | |
1dfc5cea | 954 | fail2: |
177dfcd8 | 955 | efx->phy_op->fini(efx); |
1dfc5cea BH |
956 | fail1: |
957 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 958 | return rc; |
8ceee660 BH |
959 | } |
960 | ||
8ceee660 BH |
961 | static void efx_start_port(struct efx_nic *efx) |
962 | { | |
62776d03 | 963 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
964 | BUG_ON(efx->port_enabled); |
965 | ||
966 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 967 | efx->port_enabled = true; |
8be4f3e6 BH |
968 | |
969 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
970 | * and then cancelled by efx_flush_all() */ | |
ef2b90ee | 971 | efx->type->push_multicast_hash(efx); |
710b208d | 972 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 973 | |
8ceee660 BH |
974 | mutex_unlock(&efx->mac_lock); |
975 | } | |
976 | ||
fdaa9aed | 977 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
978 | static void efx_stop_port(struct efx_nic *efx) |
979 | { | |
62776d03 | 980 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
981 | |
982 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 983 | efx->port_enabled = false; |
8ceee660 BH |
984 | mutex_unlock(&efx->mac_lock); |
985 | ||
986 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 987 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
988 | netif_addr_lock_bh(efx->net_dev); |
989 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
990 | } |
991 | } | |
992 | ||
993 | static void efx_fini_port(struct efx_nic *efx) | |
994 | { | |
62776d03 | 995 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
996 | |
997 | if (!efx->port_initialized) | |
998 | return; | |
999 | ||
177dfcd8 | 1000 | efx->phy_op->fini(efx); |
dc8cfa55 | 1001 | efx->port_initialized = false; |
8ceee660 | 1002 | |
eb50c0d6 | 1003 | efx->link_state.up = false; |
8ceee660 BH |
1004 | efx_link_status_changed(efx); |
1005 | } | |
1006 | ||
1007 | static void efx_remove_port(struct efx_nic *efx) | |
1008 | { | |
62776d03 | 1009 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1010 | |
ef2b90ee | 1011 | efx->type->remove_port(efx); |
8ceee660 BH |
1012 | } |
1013 | ||
1014 | /************************************************************************** | |
1015 | * | |
1016 | * NIC handling | |
1017 | * | |
1018 | **************************************************************************/ | |
1019 | ||
1020 | /* This configures the PCI device to enable I/O and DMA. */ | |
1021 | static int efx_init_io(struct efx_nic *efx) | |
1022 | { | |
1023 | struct pci_dev *pci_dev = efx->pci_dev; | |
1024 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
1025 | int rc; | |
1026 | ||
62776d03 | 1027 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1028 | |
1029 | rc = pci_enable_device(pci_dev); | |
1030 | if (rc) { | |
62776d03 BH |
1031 | netif_err(efx, probe, efx->net_dev, |
1032 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1033 | goto fail1; |
1034 | } | |
1035 | ||
1036 | pci_set_master(pci_dev); | |
1037 | ||
1038 | /* Set the PCI DMA mask. Try all possibilities from our | |
1039 | * genuine mask down to 32 bits, because some architectures | |
1040 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1041 | * masks event though they reject 46 bit masks. | |
1042 | */ | |
1043 | while (dma_mask > 0x7fffffffUL) { | |
e9e01846 BH |
1044 | if (pci_dma_supported(pci_dev, dma_mask)) { |
1045 | rc = pci_set_dma_mask(pci_dev, dma_mask); | |
1046 | if (rc == 0) | |
1047 | break; | |
1048 | } | |
8ceee660 BH |
1049 | dma_mask >>= 1; |
1050 | } | |
1051 | if (rc) { | |
62776d03 BH |
1052 | netif_err(efx, probe, efx->net_dev, |
1053 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1054 | goto fail2; |
1055 | } | |
62776d03 BH |
1056 | netif_dbg(efx, probe, efx->net_dev, |
1057 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 BH |
1058 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); |
1059 | if (rc) { | |
1060 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
1061 | * fail with a mask that pci_set_dma_mask() accepted, | |
1062 | * but just in case... | |
1063 | */ | |
62776d03 BH |
1064 | netif_err(efx, probe, efx->net_dev, |
1065 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1066 | goto fail2; |
1067 | } | |
1068 | ||
dc803df8 BH |
1069 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1070 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1071 | if (rc) { |
62776d03 BH |
1072 | netif_err(efx, probe, efx->net_dev, |
1073 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1074 | rc = -EIO; |
1075 | goto fail3; | |
1076 | } | |
86c432ca BH |
1077 | efx->membase = ioremap_nocache(efx->membase_phys, |
1078 | efx->type->mem_map_size); | |
8ceee660 | 1079 | if (!efx->membase) { |
62776d03 BH |
1080 | netif_err(efx, probe, efx->net_dev, |
1081 | "could not map memory BAR at %llx+%x\n", | |
1082 | (unsigned long long)efx->membase_phys, | |
1083 | efx->type->mem_map_size); | |
8ceee660 BH |
1084 | rc = -ENOMEM; |
1085 | goto fail4; | |
1086 | } | |
62776d03 BH |
1087 | netif_dbg(efx, probe, efx->net_dev, |
1088 | "memory BAR at %llx+%x (virtual %p)\n", | |
1089 | (unsigned long long)efx->membase_phys, | |
1090 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1091 | |
1092 | return 0; | |
1093 | ||
1094 | fail4: | |
dc803df8 | 1095 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1096 | fail3: |
2c118e0f | 1097 | efx->membase_phys = 0; |
8ceee660 BH |
1098 | fail2: |
1099 | pci_disable_device(efx->pci_dev); | |
1100 | fail1: | |
1101 | return rc; | |
1102 | } | |
1103 | ||
1104 | static void efx_fini_io(struct efx_nic *efx) | |
1105 | { | |
62776d03 | 1106 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1107 | |
1108 | if (efx->membase) { | |
1109 | iounmap(efx->membase); | |
1110 | efx->membase = NULL; | |
1111 | } | |
1112 | ||
1113 | if (efx->membase_phys) { | |
dc803df8 | 1114 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1115 | efx->membase_phys = 0; |
8ceee660 BH |
1116 | } |
1117 | ||
1118 | pci_disable_device(efx->pci_dev); | |
1119 | } | |
1120 | ||
fa142b9d | 1121 | static int efx_wanted_parallelism(void) |
46123d04 | 1122 | { |
cdb08f8f | 1123 | cpumask_var_t thread_mask; |
46123d04 BH |
1124 | int count; |
1125 | int cpu; | |
5b874e25 BH |
1126 | |
1127 | if (rss_cpus) | |
1128 | return rss_cpus; | |
46123d04 | 1129 | |
cdb08f8f | 1130 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { |
2f8975fb | 1131 | printk(KERN_WARNING |
3977d033 | 1132 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
1133 | return 1; |
1134 | } | |
1135 | ||
46123d04 BH |
1136 | count = 0; |
1137 | for_each_online_cpu(cpu) { | |
cdb08f8f | 1138 | if (!cpumask_test_cpu(cpu, thread_mask)) { |
46123d04 | 1139 | ++count; |
cdb08f8f BH |
1140 | cpumask_or(thread_mask, thread_mask, |
1141 | topology_thread_cpumask(cpu)); | |
46123d04 BH |
1142 | } |
1143 | } | |
1144 | ||
cdb08f8f | 1145 | free_cpumask_var(thread_mask); |
46123d04 BH |
1146 | return count; |
1147 | } | |
1148 | ||
64d8ad6d BH |
1149 | static int |
1150 | efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) | |
1151 | { | |
1152 | #ifdef CONFIG_RFS_ACCEL | |
1153 | int i, rc; | |
1154 | ||
1155 | efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); | |
1156 | if (!efx->net_dev->rx_cpu_rmap) | |
1157 | return -ENOMEM; | |
1158 | for (i = 0; i < efx->n_rx_channels; i++) { | |
1159 | rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, | |
1160 | xentries[i].vector); | |
1161 | if (rc) { | |
1162 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
1163 | efx->net_dev->rx_cpu_rmap = NULL; | |
1164 | return rc; | |
1165 | } | |
1166 | } | |
1167 | #endif | |
1168 | return 0; | |
1169 | } | |
1170 | ||
46123d04 BH |
1171 | /* Probe the number and type of interrupts we are able to obtain, and |
1172 | * the resulting numbers of channels and RX queues. | |
1173 | */ | |
64d8ad6d | 1174 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1175 | { |
46123d04 BH |
1176 | int max_channels = |
1177 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
1178 | int rc, i; |
1179 | ||
1180 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 1181 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a4900ac9 | 1182 | int n_channels; |
aa6ef27e | 1183 | |
fa142b9d | 1184 | n_channels = efx_wanted_parallelism(); |
a4900ac9 BH |
1185 | if (separate_tx_channels) |
1186 | n_channels *= 2; | |
1187 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 1188 | |
a4900ac9 | 1189 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1190 | xentries[i].entry = i; |
a4900ac9 | 1191 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1192 | if (rc > 0) { |
62776d03 BH |
1193 | netif_err(efx, drv, efx->net_dev, |
1194 | "WARNING: Insufficient MSI-X vectors" | |
1195 | " available (%d < %d).\n", rc, n_channels); | |
1196 | netif_err(efx, drv, efx->net_dev, | |
1197 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1198 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1199 | n_channels = rc; | |
8ceee660 | 1200 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1201 | n_channels); |
8ceee660 BH |
1202 | } |
1203 | ||
1204 | if (rc == 0) { | |
a4900ac9 BH |
1205 | efx->n_channels = n_channels; |
1206 | if (separate_tx_channels) { | |
1207 | efx->n_tx_channels = | |
1208 | max(efx->n_channels / 2, 1U); | |
1209 | efx->n_rx_channels = | |
1210 | max(efx->n_channels - | |
1211 | efx->n_tx_channels, 1U); | |
1212 | } else { | |
1213 | efx->n_tx_channels = efx->n_channels; | |
1214 | efx->n_rx_channels = efx->n_channels; | |
1215 | } | |
64d8ad6d BH |
1216 | rc = efx_init_rx_cpu_rmap(efx, xentries); |
1217 | if (rc) { | |
1218 | pci_disable_msix(efx->pci_dev); | |
1219 | return rc; | |
1220 | } | |
a4900ac9 | 1221 | for (i = 0; i < n_channels; i++) |
f7d12cdc BH |
1222 | efx_get_channel(efx, i)->irq = |
1223 | xentries[i].vector; | |
8ceee660 BH |
1224 | } else { |
1225 | /* Fall back to single channel MSI */ | |
1226 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1227 | netif_err(efx, drv, efx->net_dev, |
1228 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1229 | } |
1230 | } | |
1231 | ||
1232 | /* Try single interrupt MSI */ | |
1233 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1234 | efx->n_channels = 1; |
a4900ac9 BH |
1235 | efx->n_rx_channels = 1; |
1236 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1237 | rc = pci_enable_msi(efx->pci_dev); |
1238 | if (rc == 0) { | |
f7d12cdc | 1239 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1240 | } else { |
62776d03 BH |
1241 | netif_err(efx, drv, efx->net_dev, |
1242 | "could not enable MSI\n"); | |
8ceee660 BH |
1243 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1244 | } | |
1245 | } | |
1246 | ||
1247 | /* Assume legacy interrupts */ | |
1248 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1249 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1250 | efx->n_rx_channels = 1; |
1251 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1252 | efx->legacy_irq = efx->pci_dev->irq; |
1253 | } | |
64d8ad6d BH |
1254 | |
1255 | return 0; | |
8ceee660 BH |
1256 | } |
1257 | ||
1258 | static void efx_remove_interrupts(struct efx_nic *efx) | |
1259 | { | |
1260 | struct efx_channel *channel; | |
1261 | ||
1262 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1263 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1264 | channel->irq = 0; |
1265 | pci_disable_msi(efx->pci_dev); | |
1266 | pci_disable_msix(efx->pci_dev); | |
1267 | ||
1268 | /* Remove legacy interrupt */ | |
1269 | efx->legacy_irq = 0; | |
1270 | } | |
1271 | ||
8831da7b | 1272 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1273 | { |
602a5322 BH |
1274 | struct efx_channel *channel; |
1275 | struct efx_tx_queue *tx_queue; | |
1276 | ||
97653431 | 1277 | efx->tx_channel_offset = |
a4900ac9 | 1278 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 BH |
1279 | |
1280 | /* We need to adjust the TX queue numbers if we have separate | |
1281 | * RX-only and TX-only channels. | |
1282 | */ | |
1283 | efx_for_each_channel(channel, efx) { | |
1284 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1285 | tx_queue->queue -= (efx->tx_channel_offset * | |
1286 | EFX_TXQ_TYPES); | |
1287 | } | |
8ceee660 BH |
1288 | } |
1289 | ||
1290 | static int efx_probe_nic(struct efx_nic *efx) | |
1291 | { | |
765c9f46 | 1292 | size_t i; |
8ceee660 BH |
1293 | int rc; |
1294 | ||
62776d03 | 1295 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1296 | |
1297 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1298 | rc = efx->type->probe(efx); |
8ceee660 BH |
1299 | if (rc) |
1300 | return rc; | |
1301 | ||
a4900ac9 | 1302 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1303 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1304 | rc = efx_probe_interrupts(efx); |
1305 | if (rc) | |
1306 | goto fail; | |
8ceee660 | 1307 | |
5d3a6fca BH |
1308 | if (efx->n_channels > 1) |
1309 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1310 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 BH |
1311 | efx->rx_indir_table[i] = |
1312 | ethtool_rxfh_indir_default(i, efx->n_rx_channels); | |
5d3a6fca | 1313 | |
8831da7b | 1314 | efx_set_channels(efx); |
c4f4adc7 BH |
1315 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1316 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1317 | |
1318 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1319 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1320 | true); | |
8ceee660 BH |
1321 | |
1322 | return 0; | |
64d8ad6d BH |
1323 | |
1324 | fail: | |
1325 | efx->type->remove(efx); | |
1326 | return rc; | |
8ceee660 BH |
1327 | } |
1328 | ||
1329 | static void efx_remove_nic(struct efx_nic *efx) | |
1330 | { | |
62776d03 | 1331 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1332 | |
1333 | efx_remove_interrupts(efx); | |
ef2b90ee | 1334 | efx->type->remove(efx); |
8ceee660 BH |
1335 | } |
1336 | ||
1337 | /************************************************************************** | |
1338 | * | |
1339 | * NIC startup/shutdown | |
1340 | * | |
1341 | *************************************************************************/ | |
1342 | ||
1343 | static int efx_probe_all(struct efx_nic *efx) | |
1344 | { | |
8ceee660 BH |
1345 | int rc; |
1346 | ||
8ceee660 BH |
1347 | rc = efx_probe_nic(efx); |
1348 | if (rc) { | |
62776d03 | 1349 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1350 | goto fail1; |
1351 | } | |
1352 | ||
8ceee660 BH |
1353 | rc = efx_probe_port(efx); |
1354 | if (rc) { | |
62776d03 | 1355 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1356 | goto fail2; |
1357 | } | |
1358 | ||
ecc910f5 | 1359 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
4642610c BH |
1360 | rc = efx_probe_channels(efx); |
1361 | if (rc) | |
1362 | goto fail3; | |
8ceee660 | 1363 | |
64eebcfd BH |
1364 | rc = efx_probe_filters(efx); |
1365 | if (rc) { | |
1366 | netif_err(efx, probe, efx->net_dev, | |
1367 | "failed to create filter tables\n"); | |
1368 | goto fail4; | |
1369 | } | |
1370 | ||
8ceee660 BH |
1371 | return 0; |
1372 | ||
64eebcfd BH |
1373 | fail4: |
1374 | efx_remove_channels(efx); | |
8ceee660 | 1375 | fail3: |
8ceee660 BH |
1376 | efx_remove_port(efx); |
1377 | fail2: | |
1378 | efx_remove_nic(efx); | |
1379 | fail1: | |
1380 | return rc; | |
1381 | } | |
1382 | ||
1383 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1384 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1385 | * and ensures that the port is scheduled to be reconfigured. | |
1386 | * This function is safe to call multiple times when the NIC is in any | |
1387 | * state. */ | |
1388 | static void efx_start_all(struct efx_nic *efx) | |
1389 | { | |
1390 | struct efx_channel *channel; | |
1391 | ||
1392 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1393 | ||
1394 | /* Check that it is appropriate to restart the interface. All | |
1395 | * of these flags are safe to read under just the rtnl lock */ | |
1396 | if (efx->port_enabled) | |
1397 | return; | |
1398 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1399 | return; | |
55668611 | 1400 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1401 | return; |
1402 | ||
1403 | /* Mark the port as enabled so port reconfigurations can start, then | |
1404 | * restart the transmit interface early so the watchdog timer stops */ | |
1405 | efx_start_port(efx); | |
8ceee660 | 1406 | |
e4abce85 | 1407 | if (efx_dev_registered(efx) && netif_device_present(efx->net_dev)) |
c04bfc6b BH |
1408 | netif_tx_wake_all_queues(efx->net_dev); |
1409 | ||
1410 | efx_for_each_channel(channel, efx) | |
8ceee660 BH |
1411 | efx_start_channel(channel); |
1412 | ||
94dec6a2 BH |
1413 | if (efx->legacy_irq) |
1414 | efx->legacy_irq_enabled = true; | |
152b6a62 | 1415 | efx_nic_enable_interrupts(efx); |
8ceee660 | 1416 | |
8880f4ec BH |
1417 | /* Switch to event based MCDI completions after enabling interrupts. |
1418 | * If a reset has been scheduled, then we need to stay in polled mode. | |
1419 | * Rather than serialising efx_mcdi_mode_event() [which sleeps] and | |
1420 | * reset_pending [modified from an atomic context], we instead guarantee | |
1421 | * that efx_mcdi_mode_poll() isn't reverted erroneously */ | |
1422 | efx_mcdi_mode_event(efx); | |
a7d529ae | 1423 | if (efx->reset_pending) |
8880f4ec BH |
1424 | efx_mcdi_mode_poll(efx); |
1425 | ||
78c1f0a0 SH |
1426 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1427 | * event driven), we have to poll the PHY because after an event queue | |
1428 | * flush, we could have a missed a link state change */ | |
1429 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1430 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1431 | efx_monitor_interval); | |
78c1f0a0 SH |
1432 | } else { |
1433 | mutex_lock(&efx->mac_lock); | |
1434 | if (efx->phy_op->poll(efx)) | |
1435 | efx_link_status_changed(efx); | |
1436 | mutex_unlock(&efx->mac_lock); | |
1437 | } | |
55edc6e6 | 1438 | |
ef2b90ee | 1439 | efx->type->start_stats(efx); |
8ceee660 BH |
1440 | } |
1441 | ||
1442 | /* Flush all delayed work. Should only be called when no more delayed work | |
1443 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1444 | * since we're holding the rtnl_lock at this point. */ | |
1445 | static void efx_flush_all(struct efx_nic *efx) | |
1446 | { | |
8ceee660 BH |
1447 | /* Make sure the hardware monitor is stopped */ |
1448 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1449 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1450 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1451 | } |
1452 | ||
1453 | /* Quiesce hardware and software without bringing the link down. | |
1454 | * Safe to call multiple times, when the nic and interface is in any | |
1455 | * state. The caller is guaranteed to subsequently be in a position | |
1456 | * to modify any hardware and software state they see fit without | |
1457 | * taking locks. */ | |
1458 | static void efx_stop_all(struct efx_nic *efx) | |
1459 | { | |
1460 | struct efx_channel *channel; | |
1461 | ||
1462 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1463 | ||
1464 | /* port_enabled can be read safely under the rtnl lock */ | |
1465 | if (!efx->port_enabled) | |
1466 | return; | |
1467 | ||
ef2b90ee | 1468 | efx->type->stop_stats(efx); |
55edc6e6 | 1469 | |
8880f4ec BH |
1470 | /* Switch to MCDI polling on Siena before disabling interrupts */ |
1471 | efx_mcdi_mode_poll(efx); | |
1472 | ||
8ceee660 | 1473 | /* Disable interrupts and wait for ISR to complete */ |
152b6a62 | 1474 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 1475 | if (efx->legacy_irq) { |
8ceee660 | 1476 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
1477 | efx->legacy_irq_enabled = false; |
1478 | } | |
64ee3120 | 1479 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1480 | if (channel->irq) |
1481 | synchronize_irq(channel->irq); | |
b3475645 | 1482 | } |
8ceee660 BH |
1483 | |
1484 | /* Stop all NAPI processing and synchronous rx refills */ | |
1485 | efx_for_each_channel(channel, efx) | |
1486 | efx_stop_channel(channel); | |
1487 | ||
1488 | /* Stop all asynchronous port reconfigurations. Since all | |
1489 | * event processing has already been stopped, there is no | |
1490 | * window to loose phy events */ | |
1491 | efx_stop_port(efx); | |
1492 | ||
fdaa9aed | 1493 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1494 | efx_flush_all(efx); |
1495 | ||
8ceee660 BH |
1496 | /* Stop the kernel transmit interface late, so the watchdog |
1497 | * timer isn't ticking over the flush */ | |
55668611 | 1498 | if (efx_dev_registered(efx)) { |
c04bfc6b | 1499 | netif_tx_stop_all_queues(efx->net_dev); |
8ceee660 BH |
1500 | netif_tx_lock_bh(efx->net_dev); |
1501 | netif_tx_unlock_bh(efx->net_dev); | |
1502 | } | |
1503 | } | |
1504 | ||
1505 | static void efx_remove_all(struct efx_nic *efx) | |
1506 | { | |
64eebcfd | 1507 | efx_remove_filters(efx); |
4642610c | 1508 | efx_remove_channels(efx); |
8ceee660 BH |
1509 | efx_remove_port(efx); |
1510 | efx_remove_nic(efx); | |
1511 | } | |
1512 | ||
8ceee660 BH |
1513 | /************************************************************************** |
1514 | * | |
1515 | * Interrupt moderation | |
1516 | * | |
1517 | **************************************************************************/ | |
1518 | ||
b548f976 | 1519 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int resolution) |
0d86ebd8 | 1520 | { |
b548f976 BH |
1521 | if (usecs == 0) |
1522 | return 0; | |
0d86ebd8 BH |
1523 | if (usecs < resolution) |
1524 | return 1; /* never round down to 0 */ | |
1525 | return usecs / resolution; | |
1526 | } | |
1527 | ||
8ceee660 | 1528 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1529 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1530 | unsigned int rx_usecs, bool rx_adaptive, | |
1531 | bool rx_may_override_tx) | |
8ceee660 | 1532 | { |
f7d12cdc | 1533 | struct efx_channel *channel; |
152b6a62 BH |
1534 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION); |
1535 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1536 | |
1537 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1538 | ||
9e393b30 BH |
1539 | if (tx_ticks > EFX_IRQ_MOD_MAX || rx_ticks > EFX_IRQ_MOD_MAX) |
1540 | return -EINVAL; | |
1541 | ||
1542 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && | |
1543 | !rx_may_override_tx) { | |
1544 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1545 | "RX and TX IRQ moderation must be equal\n"); | |
1546 | return -EINVAL; | |
1547 | } | |
1548 | ||
6fb70fd1 | 1549 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1550 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1551 | efx_for_each_channel(channel, efx) { |
525da907 | 1552 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1553 | channel->irq_moderation = rx_ticks; |
525da907 | 1554 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1555 | channel->irq_moderation = tx_ticks; |
1556 | } | |
9e393b30 BH |
1557 | |
1558 | return 0; | |
8ceee660 BH |
1559 | } |
1560 | ||
a0c4faf5 BH |
1561 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1562 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1563 | { | |
1564 | *rx_adaptive = efx->irq_rx_adaptive; | |
1565 | *rx_usecs = efx->irq_rx_moderation * EFX_IRQ_MOD_RESOLUTION; | |
1566 | ||
1567 | /* If channels are shared between RX and TX, so is IRQ | |
1568 | * moderation. Otherwise, IRQ moderation is the same for all | |
1569 | * TX channels and is not adaptive. | |
1570 | */ | |
1571 | if (efx->tx_channel_offset == 0) | |
1572 | *tx_usecs = *rx_usecs; | |
1573 | else | |
1574 | *tx_usecs = | |
1575 | efx->channel[efx->tx_channel_offset]->irq_moderation * | |
1576 | EFX_IRQ_MOD_RESOLUTION; | |
1577 | } | |
1578 | ||
8ceee660 BH |
1579 | /************************************************************************** |
1580 | * | |
1581 | * Hardware monitor | |
1582 | * | |
1583 | **************************************************************************/ | |
1584 | ||
e254c274 | 1585 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1586 | static void efx_monitor(struct work_struct *data) |
1587 | { | |
1588 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1589 | monitor_work.work); | |
8ceee660 | 1590 | |
62776d03 BH |
1591 | netif_vdbg(efx, timer, efx->net_dev, |
1592 | "hardware monitor executing on CPU %d\n", | |
1593 | raw_smp_processor_id()); | |
ef2b90ee | 1594 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1595 | |
8ceee660 BH |
1596 | /* If the mac_lock is already held then it is likely a port |
1597 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1598 | * most of the work of monitor() anyway. */ |
1599 | if (mutex_trylock(&efx->mac_lock)) { | |
1600 | if (efx->port_enabled) | |
1601 | efx->type->monitor(efx); | |
1602 | mutex_unlock(&efx->mac_lock); | |
1603 | } | |
8ceee660 | 1604 | |
8ceee660 BH |
1605 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1606 | efx_monitor_interval); | |
1607 | } | |
1608 | ||
1609 | /************************************************************************** | |
1610 | * | |
1611 | * ioctls | |
1612 | * | |
1613 | *************************************************************************/ | |
1614 | ||
1615 | /* Net device ioctl | |
1616 | * Context: process, rtnl_lock() held. | |
1617 | */ | |
1618 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1619 | { | |
767e468c | 1620 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1621 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1622 | |
1623 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1624 | ||
68e7f45e BH |
1625 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1626 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1627 | (data->phy_id & 0xfc00) == 0x0400) | |
1628 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1629 | ||
1630 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1631 | } |
1632 | ||
1633 | /************************************************************************** | |
1634 | * | |
1635 | * NAPI interface | |
1636 | * | |
1637 | **************************************************************************/ | |
1638 | ||
e8f14992 | 1639 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1640 | { |
1641 | struct efx_channel *channel; | |
8ceee660 BH |
1642 | |
1643 | efx_for_each_channel(channel, efx) { | |
1644 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1645 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1646 | efx_poll, napi_weight); | |
8ceee660 | 1647 | } |
e8f14992 BH |
1648 | } |
1649 | ||
1650 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1651 | { | |
1652 | if (channel->napi_dev) | |
1653 | netif_napi_del(&channel->napi_str); | |
1654 | channel->napi_dev = NULL; | |
8ceee660 BH |
1655 | } |
1656 | ||
1657 | static void efx_fini_napi(struct efx_nic *efx) | |
1658 | { | |
1659 | struct efx_channel *channel; | |
1660 | ||
e8f14992 BH |
1661 | efx_for_each_channel(channel, efx) |
1662 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1663 | } |
1664 | ||
1665 | /************************************************************************** | |
1666 | * | |
1667 | * Kernel netpoll interface | |
1668 | * | |
1669 | *************************************************************************/ | |
1670 | ||
1671 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1672 | ||
1673 | /* Although in the common case interrupts will be disabled, this is not | |
1674 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1675 | * so no locking is required. | |
1676 | */ | |
1677 | static void efx_netpoll(struct net_device *net_dev) | |
1678 | { | |
767e468c | 1679 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1680 | struct efx_channel *channel; |
1681 | ||
64ee3120 | 1682 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1683 | efx_schedule_channel(channel); |
1684 | } | |
1685 | ||
1686 | #endif | |
1687 | ||
1688 | /************************************************************************** | |
1689 | * | |
1690 | * Kernel net device interface | |
1691 | * | |
1692 | *************************************************************************/ | |
1693 | ||
1694 | /* Context: process, rtnl_lock() held. */ | |
1695 | static int efx_net_open(struct net_device *net_dev) | |
1696 | { | |
767e468c | 1697 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1698 | EFX_ASSERT_RESET_SERIALISED(efx); |
1699 | ||
62776d03 BH |
1700 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1701 | raw_smp_processor_id()); | |
8ceee660 | 1702 | |
f4bd954e BH |
1703 | if (efx->state == STATE_DISABLED) |
1704 | return -EIO; | |
f8b87c17 BH |
1705 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1706 | return -EBUSY; | |
8880f4ec BH |
1707 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1708 | return -EIO; | |
f8b87c17 | 1709 | |
78c1f0a0 SH |
1710 | /* Notify the kernel of the link state polled during driver load, |
1711 | * before the monitor starts running */ | |
1712 | efx_link_status_changed(efx); | |
1713 | ||
8ceee660 BH |
1714 | efx_start_all(efx); |
1715 | return 0; | |
1716 | } | |
1717 | ||
1718 | /* Context: process, rtnl_lock() held. | |
1719 | * Note that the kernel will ignore our return code; this method | |
1720 | * should really be a void. | |
1721 | */ | |
1722 | static int efx_net_stop(struct net_device *net_dev) | |
1723 | { | |
767e468c | 1724 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1725 | |
62776d03 BH |
1726 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1727 | raw_smp_processor_id()); | |
8ceee660 | 1728 | |
f4bd954e BH |
1729 | if (efx->state != STATE_DISABLED) { |
1730 | /* Stop the device and flush all the channels */ | |
1731 | efx_stop_all(efx); | |
1732 | efx_fini_channels(efx); | |
1733 | efx_init_channels(efx); | |
1734 | } | |
8ceee660 BH |
1735 | |
1736 | return 0; | |
1737 | } | |
1738 | ||
5b9e207c | 1739 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
28172739 | 1740 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, struct rtnl_link_stats64 *stats) |
8ceee660 | 1741 | { |
767e468c | 1742 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1743 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1744 | |
55edc6e6 | 1745 | spin_lock_bh(&efx->stats_lock); |
1cb34522 | 1746 | |
ef2b90ee | 1747 | efx->type->update_stats(efx); |
8ceee660 BH |
1748 | |
1749 | stats->rx_packets = mac_stats->rx_packets; | |
1750 | stats->tx_packets = mac_stats->tx_packets; | |
1751 | stats->rx_bytes = mac_stats->rx_bytes; | |
1752 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1753 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1754 | stats->multicast = mac_stats->rx_multicast; |
1755 | stats->collisions = mac_stats->tx_collision; | |
1756 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1757 | mac_stats->rx_length_error); | |
8ceee660 BH |
1758 | stats->rx_crc_errors = mac_stats->rx_bad; |
1759 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1760 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1761 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1762 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1763 | ||
1764 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1765 | stats->rx_crc_errors + |
1766 | stats->rx_frame_errors + | |
8ceee660 BH |
1767 | mac_stats->rx_symbol_error); |
1768 | stats->tx_errors = (stats->tx_window_errors + | |
1769 | mac_stats->tx_bad); | |
1770 | ||
1cb34522 BH |
1771 | spin_unlock_bh(&efx->stats_lock); |
1772 | ||
8ceee660 BH |
1773 | return stats; |
1774 | } | |
1775 | ||
1776 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1777 | static void efx_watchdog(struct net_device *net_dev) | |
1778 | { | |
767e468c | 1779 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1780 | |
62776d03 BH |
1781 | netif_err(efx, tx_err, efx->net_dev, |
1782 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1783 | efx->port_enabled); | |
8ceee660 | 1784 | |
739bb23d | 1785 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1786 | } |
1787 | ||
1788 | ||
1789 | /* Context: process, rtnl_lock() held. */ | |
1790 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1791 | { | |
767e468c | 1792 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1793 | int rc = 0; |
1794 | ||
1795 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1796 | ||
1797 | if (new_mtu > EFX_MAX_MTU) | |
1798 | return -EINVAL; | |
1799 | ||
1800 | efx_stop_all(efx); | |
1801 | ||
62776d03 | 1802 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 BH |
1803 | |
1804 | efx_fini_channels(efx); | |
d3245b28 BH |
1805 | |
1806 | mutex_lock(&efx->mac_lock); | |
1807 | /* Reconfigure the MAC before enabling the dma queues so that | |
1808 | * the RX buffers don't overflow */ | |
8ceee660 | 1809 | net_dev->mtu = new_mtu; |
710b208d | 1810 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1811 | mutex_unlock(&efx->mac_lock); |
1812 | ||
bc3c90a2 | 1813 | efx_init_channels(efx); |
8ceee660 BH |
1814 | |
1815 | efx_start_all(efx); | |
1816 | return rc; | |
8ceee660 BH |
1817 | } |
1818 | ||
1819 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1820 | { | |
767e468c | 1821 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1822 | struct sockaddr *addr = data; |
1823 | char *new_addr = addr->sa_data; | |
1824 | ||
1825 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1826 | ||
1827 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1828 | netif_err(efx, drv, efx->net_dev, |
1829 | "invalid ethernet MAC address requested: %pM\n", | |
1830 | new_addr); | |
8ceee660 BH |
1831 | return -EINVAL; |
1832 | } | |
1833 | ||
1834 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1835 | ||
1836 | /* Reconfigure the MAC */ | |
d3245b28 | 1837 | mutex_lock(&efx->mac_lock); |
710b208d | 1838 | efx->type->reconfigure_mac(efx); |
d3245b28 | 1839 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
1840 | |
1841 | return 0; | |
1842 | } | |
1843 | ||
a816f75a | 1844 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1845 | static void efx_set_multicast_list(struct net_device *net_dev) |
1846 | { | |
767e468c | 1847 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1848 | struct netdev_hw_addr *ha; |
8ceee660 | 1849 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1850 | u32 crc; |
1851 | int bit; | |
8ceee660 | 1852 | |
8be4f3e6 | 1853 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1854 | |
1855 | /* Build multicast hash table */ | |
8be4f3e6 | 1856 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1857 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1858 | } else { | |
1859 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1860 | netdev_for_each_mc_addr(ha, net_dev) { |
1861 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1862 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1863 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1864 | } |
8ceee660 | 1865 | |
8be4f3e6 BH |
1866 | /* Broadcast packets go through the multicast hash filter. |
1867 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1868 | * so we always add bit 0xff to the mask. | |
1869 | */ | |
1870 | set_bit_le(0xff, mc_hash->byte); | |
1871 | } | |
a816f75a | 1872 | |
8be4f3e6 BH |
1873 | if (efx->port_enabled) |
1874 | queue_work(efx->workqueue, &efx->mac_work); | |
1875 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1876 | } |
1877 | ||
c8f44aff | 1878 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
1879 | { |
1880 | struct efx_nic *efx = netdev_priv(net_dev); | |
1881 | ||
1882 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
1883 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
1884 | efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | ||
c3ecb9f3 SH |
1889 | static const struct net_device_ops efx_netdev_ops = { |
1890 | .ndo_open = efx_net_open, | |
1891 | .ndo_stop = efx_net_stop, | |
4472702e | 1892 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
1893 | .ndo_tx_timeout = efx_watchdog, |
1894 | .ndo_start_xmit = efx_hard_start_xmit, | |
1895 | .ndo_validate_addr = eth_validate_addr, | |
1896 | .ndo_do_ioctl = efx_ioctl, | |
1897 | .ndo_change_mtu = efx_change_mtu, | |
1898 | .ndo_set_mac_address = efx_set_mac_address, | |
afc4b13d | 1899 | .ndo_set_rx_mode = efx_set_multicast_list, |
abfe9039 | 1900 | .ndo_set_features = efx_set_features, |
c3ecb9f3 SH |
1901 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1902 | .ndo_poll_controller = efx_netpoll, | |
1903 | #endif | |
94b274bf | 1904 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
1905 | #ifdef CONFIG_RFS_ACCEL |
1906 | .ndo_rx_flow_steer = efx_filter_rfs, | |
1907 | #endif | |
c3ecb9f3 SH |
1908 | }; |
1909 | ||
7dde596e BH |
1910 | static void efx_update_name(struct efx_nic *efx) |
1911 | { | |
1912 | strcpy(efx->name, efx->net_dev->name); | |
1913 | efx_mtd_rename(efx); | |
1914 | efx_set_channel_names(efx); | |
1915 | } | |
1916 | ||
8ceee660 BH |
1917 | static int efx_netdev_event(struct notifier_block *this, |
1918 | unsigned long event, void *ptr) | |
1919 | { | |
d3208b5e | 1920 | struct net_device *net_dev = ptr; |
8ceee660 | 1921 | |
7dde596e BH |
1922 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1923 | event == NETDEV_CHANGENAME) | |
1924 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1925 | |
1926 | return NOTIFY_DONE; | |
1927 | } | |
1928 | ||
1929 | static struct notifier_block efx_netdev_notifier = { | |
1930 | .notifier_call = efx_netdev_event, | |
1931 | }; | |
1932 | ||
06d5e193 BH |
1933 | static ssize_t |
1934 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1935 | { | |
1936 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1937 | return sprintf(buf, "%d\n", efx->phy_type); | |
1938 | } | |
1939 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1940 | ||
8ceee660 BH |
1941 | static int efx_register_netdev(struct efx_nic *efx) |
1942 | { | |
1943 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 1944 | struct efx_channel *channel; |
8ceee660 BH |
1945 | int rc; |
1946 | ||
1947 | net_dev->watchdog_timeo = 5 * HZ; | |
1948 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1949 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1950 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
1951 | ||
7dde596e | 1952 | rtnl_lock(); |
aed0628d BH |
1953 | |
1954 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1955 | if (rc < 0) | |
1956 | goto fail_locked; | |
7dde596e | 1957 | efx_update_name(efx); |
aed0628d BH |
1958 | |
1959 | rc = register_netdevice(net_dev); | |
1960 | if (rc) | |
1961 | goto fail_locked; | |
1962 | ||
c04bfc6b BH |
1963 | efx_for_each_channel(channel, efx) { |
1964 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
1965 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1966 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
1967 | } |
1968 | ||
aed0628d BH |
1969 | /* Always start with carrier off; PHY events will detect the link */ |
1970 | netif_carrier_off(efx->net_dev); | |
1971 | ||
7dde596e | 1972 | rtnl_unlock(); |
8ceee660 | 1973 | |
06d5e193 BH |
1974 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1975 | if (rc) { | |
62776d03 BH |
1976 | netif_err(efx, drv, efx->net_dev, |
1977 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
1978 | goto fail_registered; |
1979 | } | |
1980 | ||
8ceee660 | 1981 | return 0; |
06d5e193 | 1982 | |
aed0628d BH |
1983 | fail_locked: |
1984 | rtnl_unlock(); | |
62776d03 | 1985 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
1986 | return rc; |
1987 | ||
06d5e193 BH |
1988 | fail_registered: |
1989 | unregister_netdev(net_dev); | |
1990 | return rc; | |
8ceee660 BH |
1991 | } |
1992 | ||
1993 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1994 | { | |
f7d12cdc | 1995 | struct efx_channel *channel; |
8ceee660 BH |
1996 | struct efx_tx_queue *tx_queue; |
1997 | ||
1998 | if (!efx->net_dev) | |
1999 | return; | |
2000 | ||
767e468c | 2001 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
2002 | |
2003 | /* Free up any skbs still remaining. This has to happen before | |
2004 | * we try to unregister the netdev as running their destructors | |
2005 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
2006 | efx_for_each_channel(channel, efx) { |
2007 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
2008 | efx_release_tx_buffers(tx_queue); | |
2009 | } | |
8ceee660 | 2010 | |
55668611 | 2011 | if (efx_dev_registered(efx)) { |
8ceee660 | 2012 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 2013 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
2014 | unregister_netdev(efx->net_dev); |
2015 | } | |
2016 | } | |
2017 | ||
2018 | /************************************************************************** | |
2019 | * | |
2020 | * Device reset and suspend | |
2021 | * | |
2022 | **************************************************************************/ | |
2023 | ||
2467ca46 BH |
2024 | /* Tears down the entire software state and most of the hardware state |
2025 | * before reset. */ | |
d3245b28 | 2026 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2027 | { |
8ceee660 BH |
2028 | EFX_ASSERT_RESET_SERIALISED(efx); |
2029 | ||
2467ca46 BH |
2030 | efx_stop_all(efx); |
2031 | mutex_lock(&efx->mac_lock); | |
2032 | ||
8ceee660 | 2033 | efx_fini_channels(efx); |
4b988280 SH |
2034 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2035 | efx->phy_op->fini(efx); | |
ef2b90ee | 2036 | efx->type->fini(efx); |
8ceee660 BH |
2037 | } |
2038 | ||
2467ca46 BH |
2039 | /* This function will always ensure that the locks acquired in |
2040 | * efx_reset_down() are released. A failure return code indicates | |
2041 | * that we were unable to reinitialise the hardware, and the | |
2042 | * driver should be disabled. If ok is false, then the rx and tx | |
2043 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2044 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2045 | { |
2046 | int rc; | |
2047 | ||
2467ca46 | 2048 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2049 | |
ef2b90ee | 2050 | rc = efx->type->init(efx); |
8ceee660 | 2051 | if (rc) { |
62776d03 | 2052 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2053 | goto fail; |
8ceee660 BH |
2054 | } |
2055 | ||
eb9f6744 BH |
2056 | if (!ok) |
2057 | goto fail; | |
2058 | ||
4b988280 | 2059 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2060 | rc = efx->phy_op->init(efx); |
2061 | if (rc) | |
2062 | goto fail; | |
2063 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2064 | netif_err(efx, drv, efx->net_dev, |
2065 | "could not restore PHY settings\n"); | |
4b988280 SH |
2066 | } |
2067 | ||
710b208d | 2068 | efx->type->reconfigure_mac(efx); |
8ceee660 | 2069 | |
eb9f6744 | 2070 | efx_init_channels(efx); |
64eebcfd | 2071 | efx_restore_filters(efx); |
eb9f6744 | 2072 | |
eb9f6744 BH |
2073 | mutex_unlock(&efx->mac_lock); |
2074 | ||
2075 | efx_start_all(efx); | |
2076 | ||
2077 | return 0; | |
2078 | ||
2079 | fail: | |
2080 | efx->port_initialized = false; | |
2467ca46 BH |
2081 | |
2082 | mutex_unlock(&efx->mac_lock); | |
2083 | ||
8ceee660 BH |
2084 | return rc; |
2085 | } | |
2086 | ||
eb9f6744 BH |
2087 | /* Reset the NIC using the specified method. Note that the reset may |
2088 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2089 | * |
eb9f6744 | 2090 | * Caller must hold the rtnl_lock. |
8ceee660 | 2091 | */ |
eb9f6744 | 2092 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2093 | { |
eb9f6744 BH |
2094 | int rc, rc2; |
2095 | bool disabled; | |
8ceee660 | 2096 | |
62776d03 BH |
2097 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2098 | RESET_TYPE(method)); | |
8ceee660 | 2099 | |
e4abce85 | 2100 | netif_device_detach(efx->net_dev); |
d3245b28 | 2101 | efx_reset_down(efx, method); |
8ceee660 | 2102 | |
ef2b90ee | 2103 | rc = efx->type->reset(efx, method); |
8ceee660 | 2104 | if (rc) { |
62776d03 | 2105 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2106 | goto out; |
8ceee660 BH |
2107 | } |
2108 | ||
a7d529ae BH |
2109 | /* Clear flags for the scopes we covered. We assume the NIC and |
2110 | * driver are now quiescent so that there is no race here. | |
2111 | */ | |
2112 | efx->reset_pending &= -(1 << (method + 1)); | |
8ceee660 BH |
2113 | |
2114 | /* Reinitialise bus-mastering, which may have been turned off before | |
2115 | * the reset was scheduled. This is still appropriate, even in the | |
2116 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2117 | * can respond to requests. */ | |
2118 | pci_set_master(efx->pci_dev); | |
2119 | ||
eb9f6744 | 2120 | out: |
8ceee660 | 2121 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2122 | disabled = rc || method == RESET_TYPE_DISABLE; |
2123 | rc2 = efx_reset_up(efx, method, !disabled); | |
2124 | if (rc2) { | |
2125 | disabled = true; | |
2126 | if (!rc) | |
2127 | rc = rc2; | |
8ceee660 BH |
2128 | } |
2129 | ||
eb9f6744 | 2130 | if (disabled) { |
f49a4589 | 2131 | dev_close(efx->net_dev); |
62776d03 | 2132 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2133 | efx->state = STATE_DISABLED; |
f4bd954e | 2134 | } else { |
62776d03 | 2135 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2136 | netif_device_attach(efx->net_dev); |
f4bd954e | 2137 | } |
8ceee660 BH |
2138 | return rc; |
2139 | } | |
2140 | ||
2141 | /* The worker thread exists so that code that cannot sleep can | |
2142 | * schedule a reset for later. | |
2143 | */ | |
2144 | static void efx_reset_work(struct work_struct *data) | |
2145 | { | |
eb9f6744 | 2146 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
a7d529ae | 2147 | unsigned long pending = ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 2148 | |
a7d529ae | 2149 | if (!pending) |
319ba649 SH |
2150 | return; |
2151 | ||
eb9f6744 | 2152 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
a7d529ae | 2153 | * flags set so that efx_pci_probe_main will be retried */ |
eb9f6744 | 2154 | if (efx->state != STATE_RUNNING) { |
62776d03 BH |
2155 | netif_info(efx, drv, efx->net_dev, |
2156 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
2157 | return; |
2158 | } | |
2159 | ||
2160 | rtnl_lock(); | |
a7d529ae | 2161 | (void)efx_reset(efx, fls(pending) - 1); |
eb9f6744 | 2162 | rtnl_unlock(); |
8ceee660 BH |
2163 | } |
2164 | ||
2165 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2166 | { | |
2167 | enum reset_type method; | |
2168 | ||
8ceee660 BH |
2169 | switch (type) { |
2170 | case RESET_TYPE_INVISIBLE: | |
2171 | case RESET_TYPE_ALL: | |
2172 | case RESET_TYPE_WORLD: | |
2173 | case RESET_TYPE_DISABLE: | |
2174 | method = type; | |
0e2a9c7c BH |
2175 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2176 | RESET_TYPE(method)); | |
8ceee660 | 2177 | break; |
8ceee660 | 2178 | default: |
0e2a9c7c | 2179 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2180 | netif_dbg(efx, drv, efx->net_dev, |
2181 | "scheduling %s reset for %s\n", | |
2182 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2183 | break; |
2184 | } | |
8ceee660 | 2185 | |
a7d529ae | 2186 | set_bit(method, &efx->reset_pending); |
8ceee660 | 2187 | |
8880f4ec BH |
2188 | /* efx_process_channel() will no longer read events once a |
2189 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2190 | efx_mcdi_mode_poll(efx); | |
2191 | ||
1ab00629 | 2192 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2193 | } |
2194 | ||
2195 | /************************************************************************** | |
2196 | * | |
2197 | * List of NICs we support | |
2198 | * | |
2199 | **************************************************************************/ | |
2200 | ||
2201 | /* PCI device ID table */ | |
a3aa1884 | 2202 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2203 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2204 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2205 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2206 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2207 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2208 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2209 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2210 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2211 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2212 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8ceee660 BH |
2213 | {0} /* end of list */ |
2214 | }; | |
2215 | ||
2216 | /************************************************************************** | |
2217 | * | |
3759433d | 2218 | * Dummy PHY/MAC operations |
8ceee660 | 2219 | * |
01aad7b6 | 2220 | * Can be used for some unimplemented operations |
8ceee660 BH |
2221 | * Needed so all function pointers are valid and do not have to be tested |
2222 | * before use | |
2223 | * | |
2224 | **************************************************************************/ | |
2225 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2226 | { | |
2227 | return 0; | |
2228 | } | |
2229 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2230 | |
2231 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2232 | { |
2233 | return false; | |
2234 | } | |
8ceee660 | 2235 | |
6c8c2513 | 2236 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2237 | .init = efx_port_dummy_op_int, |
d3245b28 | 2238 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2239 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2240 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2241 | }; |
2242 | ||
8ceee660 BH |
2243 | /************************************************************************** |
2244 | * | |
2245 | * Data housekeeping | |
2246 | * | |
2247 | **************************************************************************/ | |
2248 | ||
2249 | /* This zeroes out and then fills in the invariants in a struct | |
2250 | * efx_nic (including all sub-structures). | |
2251 | */ | |
6c8c2513 | 2252 | static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type, |
8ceee660 BH |
2253 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2254 | { | |
4642610c | 2255 | int i; |
8ceee660 BH |
2256 | |
2257 | /* Initialise common structures */ | |
2258 | memset(efx, 0, sizeof(*efx)); | |
2259 | spin_lock_init(&efx->biu_lock); | |
76884835 BH |
2260 | #ifdef CONFIG_SFC_MTD |
2261 | INIT_LIST_HEAD(&efx->mtd_list); | |
2262 | #endif | |
8ceee660 BH |
2263 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2264 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2265 | efx->pci_dev = pci_dev; | |
62776d03 | 2266 | efx->msg_enable = debug; |
8ceee660 | 2267 | efx->state = STATE_INIT; |
8ceee660 | 2268 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2269 | |
2270 | efx->net_dev = net_dev; | |
8ceee660 BH |
2271 | spin_lock_init(&efx->stats_lock); |
2272 | mutex_init(&efx->mac_lock); | |
2273 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2274 | efx->mdio.dev = net_dev; |
766ca0fa | 2275 | INIT_WORK(&efx->mac_work, efx_mac_work); |
8ceee660 BH |
2276 | |
2277 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2278 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2279 | if (!efx->channel[i]) | |
2280 | goto fail; | |
8ceee660 BH |
2281 | } |
2282 | ||
2283 | efx->type = type; | |
2284 | ||
8ceee660 BH |
2285 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2286 | ||
2287 | /* Higher numbered interrupt modes are less capable! */ | |
2288 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2289 | interrupt_mode); | |
2290 | ||
6977dc63 BH |
2291 | /* Would be good to use the net_dev name, but we're too early */ |
2292 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2293 | pci_name(pci_dev)); | |
2294 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2295 | if (!efx->workqueue) |
4642610c | 2296 | goto fail; |
8d9853d9 | 2297 | |
8ceee660 | 2298 | return 0; |
4642610c BH |
2299 | |
2300 | fail: | |
2301 | efx_fini_struct(efx); | |
2302 | return -ENOMEM; | |
8ceee660 BH |
2303 | } |
2304 | ||
2305 | static void efx_fini_struct(struct efx_nic *efx) | |
2306 | { | |
8313aca3 BH |
2307 | int i; |
2308 | ||
2309 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2310 | kfree(efx->channel[i]); | |
2311 | ||
8ceee660 BH |
2312 | if (efx->workqueue) { |
2313 | destroy_workqueue(efx->workqueue); | |
2314 | efx->workqueue = NULL; | |
2315 | } | |
2316 | } | |
2317 | ||
2318 | /************************************************************************** | |
2319 | * | |
2320 | * PCI interface | |
2321 | * | |
2322 | **************************************************************************/ | |
2323 | ||
2324 | /* Main body of final NIC shutdown code | |
2325 | * This is called only at module unload (or hotplug removal). | |
2326 | */ | |
2327 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2328 | { | |
64d8ad6d BH |
2329 | #ifdef CONFIG_RFS_ACCEL |
2330 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
2331 | efx->net_dev->rx_cpu_rmap = NULL; | |
2332 | #endif | |
152b6a62 | 2333 | efx_nic_fini_interrupt(efx); |
8ceee660 BH |
2334 | efx_fini_channels(efx); |
2335 | efx_fini_port(efx); | |
ef2b90ee | 2336 | efx->type->fini(efx); |
8ceee660 BH |
2337 | efx_fini_napi(efx); |
2338 | efx_remove_all(efx); | |
2339 | } | |
2340 | ||
2341 | /* Final NIC shutdown | |
2342 | * This is called only at module unload (or hotplug removal). | |
2343 | */ | |
2344 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2345 | { | |
2346 | struct efx_nic *efx; | |
2347 | ||
2348 | efx = pci_get_drvdata(pci_dev); | |
2349 | if (!efx) | |
2350 | return; | |
2351 | ||
2352 | /* Mark the NIC as fini, then stop the interface */ | |
2353 | rtnl_lock(); | |
2354 | efx->state = STATE_FINI; | |
2355 | dev_close(efx->net_dev); | |
2356 | ||
2357 | /* Allow any queued efx_resets() to complete */ | |
2358 | rtnl_unlock(); | |
2359 | ||
8ceee660 BH |
2360 | efx_unregister_netdev(efx); |
2361 | ||
7dde596e BH |
2362 | efx_mtd_remove(efx); |
2363 | ||
8ceee660 BH |
2364 | /* Wait for any scheduled resets to complete. No more will be |
2365 | * scheduled from this point because efx_stop_all() has been | |
2366 | * called, we are no longer registered with driverlink, and | |
2367 | * the net_device's have been removed. */ | |
1ab00629 | 2368 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2369 | |
2370 | efx_pci_remove_main(efx); | |
2371 | ||
8ceee660 | 2372 | efx_fini_io(efx); |
62776d03 | 2373 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 BH |
2374 | |
2375 | pci_set_drvdata(pci_dev, NULL); | |
2376 | efx_fini_struct(efx); | |
2377 | free_netdev(efx->net_dev); | |
2378 | }; | |
2379 | ||
2380 | /* Main body of NIC initialisation | |
2381 | * This is called at module load (or hotplug insertion, theoretically). | |
2382 | */ | |
2383 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2384 | { | |
2385 | int rc; | |
2386 | ||
2387 | /* Do start-of-day initialisation */ | |
2388 | rc = efx_probe_all(efx); | |
2389 | if (rc) | |
2390 | goto fail1; | |
2391 | ||
e8f14992 | 2392 | efx_init_napi(efx); |
8ceee660 | 2393 | |
ef2b90ee | 2394 | rc = efx->type->init(efx); |
8ceee660 | 2395 | if (rc) { |
62776d03 BH |
2396 | netif_err(efx, probe, efx->net_dev, |
2397 | "failed to initialise NIC\n"); | |
278c0621 | 2398 | goto fail3; |
8ceee660 BH |
2399 | } |
2400 | ||
2401 | rc = efx_init_port(efx); | |
2402 | if (rc) { | |
62776d03 BH |
2403 | netif_err(efx, probe, efx->net_dev, |
2404 | "failed to initialise port\n"); | |
278c0621 | 2405 | goto fail4; |
8ceee660 BH |
2406 | } |
2407 | ||
bc3c90a2 | 2408 | efx_init_channels(efx); |
8ceee660 | 2409 | |
152b6a62 | 2410 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2411 | if (rc) |
278c0621 | 2412 | goto fail5; |
8ceee660 BH |
2413 | |
2414 | return 0; | |
2415 | ||
278c0621 | 2416 | fail5: |
bc3c90a2 | 2417 | efx_fini_channels(efx); |
8ceee660 | 2418 | efx_fini_port(efx); |
8ceee660 | 2419 | fail4: |
ef2b90ee | 2420 | efx->type->fini(efx); |
8ceee660 BH |
2421 | fail3: |
2422 | efx_fini_napi(efx); | |
8ceee660 BH |
2423 | efx_remove_all(efx); |
2424 | fail1: | |
2425 | return rc; | |
2426 | } | |
2427 | ||
2428 | /* NIC initialisation | |
2429 | * | |
2430 | * This is called at module load (or hotplug insertion, | |
2431 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2432 | * sets up and registers the network devices with the kernel and hooks | |
2433 | * the interrupt service routine. It does not prepare the device for | |
2434 | * transmission; this is left to the first time one of the network | |
2435 | * interfaces is brought up (i.e. efx_net_open). | |
2436 | */ | |
2437 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2438 | const struct pci_device_id *entry) | |
2439 | { | |
6c8c2513 | 2440 | const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data; |
8ceee660 BH |
2441 | struct net_device *net_dev; |
2442 | struct efx_nic *efx; | |
2443 | int i, rc; | |
2444 | ||
2445 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2446 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2447 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2448 | if (!net_dev) |
2449 | return -ENOMEM; | |
c383b537 | 2450 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 | 2451 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2452 | NETIF_F_RXCSUM); |
738a8f4b BH |
2453 | if (type->offload_features & NETIF_F_V6_CSUM) |
2454 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2455 | /* Mask for features that also apply to VLAN devices */ |
2456 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2457 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2458 | NETIF_F_RXCSUM); | |
2459 | /* All offloads can be toggled */ | |
2460 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
767e468c | 2461 | efx = netdev_priv(net_dev); |
8ceee660 | 2462 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2463 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2464 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2465 | if (rc) | |
2466 | goto fail1; | |
2467 | ||
62776d03 | 2468 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2469 | "Solarflare NIC detected\n"); |
8ceee660 BH |
2470 | |
2471 | /* Set up basic I/O (BAR mappings etc) */ | |
2472 | rc = efx_init_io(efx); | |
2473 | if (rc) | |
2474 | goto fail2; | |
2475 | ||
2476 | /* No serialisation is required with the reset path because | |
2477 | * we're in STATE_INIT. */ | |
2478 | for (i = 0; i < 5; i++) { | |
2479 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2480 | |
2481 | /* Serialise against efx_reset(). No more resets will be | |
2482 | * scheduled since efx_stop_all() has been called, and we | |
2483 | * have not and never have been registered with either | |
2484 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2485 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2486 | |
fa402b2e | 2487 | if (rc == 0) { |
a7d529ae | 2488 | if (efx->reset_pending) { |
fa402b2e SH |
2489 | /* If there was a scheduled reset during |
2490 | * probe, the NIC is probably hosed anyway */ | |
2491 | efx_pci_remove_main(efx); | |
2492 | rc = -EIO; | |
2493 | } else { | |
2494 | break; | |
2495 | } | |
2496 | } | |
2497 | ||
8ceee660 | 2498 | /* Retry if a recoverably reset event has been scheduled */ |
a7d529ae BH |
2499 | if (efx->reset_pending & |
2500 | ~(1 << RESET_TYPE_INVISIBLE | 1 << RESET_TYPE_ALL) || | |
2501 | !efx->reset_pending) | |
8ceee660 BH |
2502 | goto fail3; |
2503 | ||
a7d529ae | 2504 | efx->reset_pending = 0; |
8ceee660 BH |
2505 | } |
2506 | ||
2507 | if (rc) { | |
62776d03 | 2508 | netif_err(efx, probe, efx->net_dev, "Could not reset NIC\n"); |
8ceee660 BH |
2509 | goto fail4; |
2510 | } | |
2511 | ||
55edc6e6 BH |
2512 | /* Switch to the running state before we expose the device to the OS, |
2513 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2514 | efx->state = STATE_RUNNING; |
7dde596e | 2515 | |
8ceee660 BH |
2516 | rc = efx_register_netdev(efx); |
2517 | if (rc) | |
2518 | goto fail5; | |
2519 | ||
62776d03 | 2520 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 BH |
2521 | |
2522 | rtnl_lock(); | |
2523 | efx_mtd_probe(efx); /* allowed to fail */ | |
2524 | rtnl_unlock(); | |
8ceee660 BH |
2525 | return 0; |
2526 | ||
2527 | fail5: | |
2528 | efx_pci_remove_main(efx); | |
2529 | fail4: | |
2530 | fail3: | |
2531 | efx_fini_io(efx); | |
2532 | fail2: | |
2533 | efx_fini_struct(efx); | |
2534 | fail1: | |
5e2a911c | 2535 | WARN_ON(rc > 0); |
62776d03 | 2536 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2537 | free_netdev(net_dev); |
2538 | return rc; | |
2539 | } | |
2540 | ||
89c758fa BH |
2541 | static int efx_pm_freeze(struct device *dev) |
2542 | { | |
2543 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2544 | ||
2545 | efx->state = STATE_FINI; | |
2546 | ||
2547 | netif_device_detach(efx->net_dev); | |
2548 | ||
2549 | efx_stop_all(efx); | |
2550 | efx_fini_channels(efx); | |
2551 | ||
2552 | return 0; | |
2553 | } | |
2554 | ||
2555 | static int efx_pm_thaw(struct device *dev) | |
2556 | { | |
2557 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2558 | ||
2559 | efx->state = STATE_INIT; | |
2560 | ||
2561 | efx_init_channels(efx); | |
2562 | ||
2563 | mutex_lock(&efx->mac_lock); | |
2564 | efx->phy_op->reconfigure(efx); | |
2565 | mutex_unlock(&efx->mac_lock); | |
2566 | ||
2567 | efx_start_all(efx); | |
2568 | ||
2569 | netif_device_attach(efx->net_dev); | |
2570 | ||
2571 | efx->state = STATE_RUNNING; | |
2572 | ||
2573 | efx->type->resume_wol(efx); | |
2574 | ||
319ba649 SH |
2575 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2576 | queue_work(reset_workqueue, &efx->reset_work); | |
2577 | ||
89c758fa BH |
2578 | return 0; |
2579 | } | |
2580 | ||
2581 | static int efx_pm_poweroff(struct device *dev) | |
2582 | { | |
2583 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2584 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2585 | ||
2586 | efx->type->fini(efx); | |
2587 | ||
a7d529ae | 2588 | efx->reset_pending = 0; |
89c758fa BH |
2589 | |
2590 | pci_save_state(pci_dev); | |
2591 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2592 | } | |
2593 | ||
2594 | /* Used for both resume and restore */ | |
2595 | static int efx_pm_resume(struct device *dev) | |
2596 | { | |
2597 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2598 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2599 | int rc; | |
2600 | ||
2601 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2602 | if (rc) | |
2603 | return rc; | |
2604 | pci_restore_state(pci_dev); | |
2605 | rc = pci_enable_device(pci_dev); | |
2606 | if (rc) | |
2607 | return rc; | |
2608 | pci_set_master(efx->pci_dev); | |
2609 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2610 | if (rc) | |
2611 | return rc; | |
2612 | rc = efx->type->init(efx); | |
2613 | if (rc) | |
2614 | return rc; | |
2615 | efx_pm_thaw(dev); | |
2616 | return 0; | |
2617 | } | |
2618 | ||
2619 | static int efx_pm_suspend(struct device *dev) | |
2620 | { | |
2621 | int rc; | |
2622 | ||
2623 | efx_pm_freeze(dev); | |
2624 | rc = efx_pm_poweroff(dev); | |
2625 | if (rc) | |
2626 | efx_pm_resume(dev); | |
2627 | return rc; | |
2628 | } | |
2629 | ||
18e83e4c | 2630 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
2631 | .suspend = efx_pm_suspend, |
2632 | .resume = efx_pm_resume, | |
2633 | .freeze = efx_pm_freeze, | |
2634 | .thaw = efx_pm_thaw, | |
2635 | .poweroff = efx_pm_poweroff, | |
2636 | .restore = efx_pm_resume, | |
2637 | }; | |
2638 | ||
8ceee660 | 2639 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2640 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2641 | .id_table = efx_pci_table, |
2642 | .probe = efx_pci_probe, | |
2643 | .remove = efx_pci_remove, | |
89c758fa | 2644 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2645 | }; |
2646 | ||
2647 | /************************************************************************** | |
2648 | * | |
2649 | * Kernel module interface | |
2650 | * | |
2651 | *************************************************************************/ | |
2652 | ||
2653 | module_param(interrupt_mode, uint, 0444); | |
2654 | MODULE_PARM_DESC(interrupt_mode, | |
2655 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2656 | ||
2657 | static int __init efx_init_module(void) | |
2658 | { | |
2659 | int rc; | |
2660 | ||
2661 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2662 | ||
2663 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2664 | if (rc) | |
2665 | goto err_notifier; | |
2666 | ||
1ab00629 SH |
2667 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2668 | if (!reset_workqueue) { | |
2669 | rc = -ENOMEM; | |
2670 | goto err_reset; | |
2671 | } | |
8ceee660 BH |
2672 | |
2673 | rc = pci_register_driver(&efx_pci_driver); | |
2674 | if (rc < 0) | |
2675 | goto err_pci; | |
2676 | ||
2677 | return 0; | |
2678 | ||
2679 | err_pci: | |
1ab00629 SH |
2680 | destroy_workqueue(reset_workqueue); |
2681 | err_reset: | |
8ceee660 BH |
2682 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2683 | err_notifier: | |
2684 | return rc; | |
2685 | } | |
2686 | ||
2687 | static void __exit efx_exit_module(void) | |
2688 | { | |
2689 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2690 | ||
2691 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2692 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2693 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2694 | ||
2695 | } | |
2696 | ||
2697 | module_init(efx_init_module); | |
2698 | module_exit(efx_exit_module); | |
2699 | ||
906bb26c BH |
2700 | MODULE_AUTHOR("Solarflare Communications and " |
2701 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2702 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2703 | MODULE_LICENSE("GPL"); | |
2704 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |