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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2005-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
8ceee660 | 20 | #include <linux/ethtool.h> |
aa6ef27e | 21 | #include <linux/topology.h> |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
626950db | 23 | #include <linux/aer.h> |
b28405b0 | 24 | #include <linux/interrupt.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
dd40781e | 28 | #include "selftest.h" |
7fa8d547 | 29 | #include "sriov.h" |
8ceee660 | 30 | |
8880f4ec | 31 | #include "mcdi.h" |
fd371e32 | 32 | #include "workarounds.h" |
8880f4ec | 33 | |
c459302d BH |
34 | /************************************************************************** |
35 | * | |
36 | * Type name strings | |
37 | * | |
38 | ************************************************************************** | |
39 | */ | |
40 | ||
41 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
42 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 43 | const char *const efx_loopback_mode_names[] = { |
c459302d | 44 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 45 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
46 | [LOOPBACK_GMAC] = "GMAC", |
47 | [LOOPBACK_XGMII] = "XGMII", | |
48 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
49 | [LOOPBACK_XAUI] = "XAUI", |
50 | [LOOPBACK_GMII] = "GMII", | |
51 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
52 | [LOOPBACK_XGBR] = "XGBR", |
53 | [LOOPBACK_XFI] = "XFI", | |
54 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
55 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
56 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
57 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
58 | [LOOPBACK_GPHY] = "GPHY", |
59 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
60 | [LOOPBACK_PCS] = "PCS", |
61 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
62 | [LOOPBACK_XPORT] = "XPORT", |
63 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 64 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
65 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
66 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 67 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
68 | [LOOPBACK_XFI_WS] = "XFI_WS", |
69 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 70 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
71 | }; |
72 | ||
c459302d | 73 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 74 | const char *const efx_reset_type_names[] = { |
626950db AR |
75 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
76 | [RESET_TYPE_ALL] = "ALL", | |
77 | [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", | |
78 | [RESET_TYPE_WORLD] = "WORLD", | |
79 | [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", | |
e283546c | 80 | [RESET_TYPE_MC_BIST] = "MC_BIST", |
626950db AR |
81 | [RESET_TYPE_DISABLE] = "DISABLE", |
82 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
83 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
84 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
3de82b91 | 85 | [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", |
626950db AR |
86 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", |
87 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", | |
e283546c | 88 | [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)", |
c459302d BH |
89 | }; |
90 | ||
1ab00629 SH |
91 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
92 | * queued onto this work queue. This is not a per-nic work queue, because | |
93 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
94 | */ | |
95 | static struct workqueue_struct *reset_workqueue; | |
96 | ||
74cd60a4 JC |
97 | /* How often and how many times to poll for a reset while waiting for a |
98 | * BIST that another function started to complete. | |
99 | */ | |
100 | #define BIST_WAIT_DELAY_MS 100 | |
101 | #define BIST_WAIT_DELAY_COUNT 100 | |
102 | ||
8ceee660 BH |
103 | /************************************************************************** |
104 | * | |
105 | * Configurable values | |
106 | * | |
107 | *************************************************************************/ | |
108 | ||
8ceee660 BH |
109 | /* |
110 | * Use separate channels for TX and RX events | |
111 | * | |
28b581ab NT |
112 | * Set this to 1 to use separate channels for TX and RX. It allows us |
113 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 114 | * |
28b581ab | 115 | * This is only used in MSI-X interrupt mode |
8ceee660 | 116 | */ |
b9cc977d BH |
117 | static bool separate_tx_channels; |
118 | module_param(separate_tx_channels, bool, 0444); | |
28b581ab NT |
119 | MODULE_PARM_DESC(separate_tx_channels, |
120 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
121 | |
122 | /* This is the weight assigned to each of the (per-channel) virtual | |
123 | * NAPI devices. | |
124 | */ | |
125 | static int napi_weight = 64; | |
126 | ||
127 | /* This is the time (in jiffies) between invocations of the hardware | |
626950db AR |
128 | * monitor. |
129 | * On Falcon-based NICs, this will: | |
e254c274 BH |
130 | * - Check the on-board hardware monitor; |
131 | * - Poll the link state and reconfigure the hardware as necessary. | |
626950db AR |
132 | * On Siena-based NICs for power systems with EEH support, this will give EEH a |
133 | * chance to start. | |
8ceee660 | 134 | */ |
d215697f | 135 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 136 | |
8ceee660 BH |
137 | /* Initial interrupt moderation settings. They can be modified after |
138 | * module load with ethtool. | |
139 | * | |
140 | * The default for RX should strike a balance between increasing the | |
141 | * round-trip latency and reducing overhead. | |
142 | */ | |
143 | static unsigned int rx_irq_mod_usec = 60; | |
144 | ||
145 | /* Initial interrupt moderation settings. They can be modified after | |
146 | * module load with ethtool. | |
147 | * | |
148 | * This default is chosen to ensure that a 10G link does not go idle | |
149 | * while a TX queue is stopped after it has become full. A queue is | |
150 | * restarted when it drops below half full. The time this takes (assuming | |
151 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
152 | * 512 / 3 * 1.2 = 205 usec. | |
153 | */ | |
154 | static unsigned int tx_irq_mod_usec = 150; | |
155 | ||
156 | /* This is the first interrupt mode to try out of: | |
157 | * 0 => MSI-X | |
158 | * 1 => MSI | |
159 | * 2 => legacy | |
160 | */ | |
161 | static unsigned int interrupt_mode; | |
162 | ||
163 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
164 | * i.e. the number of CPUs among which we may distribute simultaneous | |
165 | * interrupt handling. | |
166 | * | |
167 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 168 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
169 | */ |
170 | static unsigned int rss_cpus; | |
171 | module_param(rss_cpus, uint, 0444); | |
172 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
173 | ||
b9cc977d BH |
174 | static bool phy_flash_cfg; |
175 | module_param(phy_flash_cfg, bool, 0644); | |
84ae48fe BH |
176 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); |
177 | ||
e7bed9c8 | 178 | static unsigned irq_adapt_low_thresh = 8000; |
6fb70fd1 BH |
179 | module_param(irq_adapt_low_thresh, uint, 0644); |
180 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
181 | "Threshold score for reducing IRQ moderation"); | |
182 | ||
e7bed9c8 | 183 | static unsigned irq_adapt_high_thresh = 16000; |
6fb70fd1 BH |
184 | module_param(irq_adapt_high_thresh, uint, 0644); |
185 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
186 | "Threshold score for increasing IRQ moderation"); | |
187 | ||
62776d03 BH |
188 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
189 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
190 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
191 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
192 | module_param(debug, uint, 0); | |
193 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
194 | ||
8ceee660 BH |
195 | /************************************************************************** |
196 | * | |
197 | * Utility functions and prototypes | |
198 | * | |
199 | *************************************************************************/ | |
4642610c | 200 | |
261e4d96 | 201 | static int efx_soft_enable_interrupts(struct efx_nic *efx); |
d8291187 | 202 | static void efx_soft_disable_interrupts(struct efx_nic *efx); |
7f967c01 | 203 | static void efx_remove_channel(struct efx_channel *channel); |
4642610c | 204 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 205 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 206 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 207 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 208 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 209 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
210 | static void efx_fini_struct(struct efx_nic *efx); |
211 | static void efx_start_all(struct efx_nic *efx); | |
212 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
213 | |
214 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
215 | do { \ | |
f16aeea0 | 216 | if ((efx->state == STATE_READY) || \ |
626950db | 217 | (efx->state == STATE_RECOVERY) || \ |
332c1ce9 | 218 | (efx->state == STATE_DISABLED)) \ |
8ceee660 BH |
219 | ASSERT_RTNL(); \ |
220 | } while (0) | |
221 | ||
8b7325b4 BH |
222 | static int efx_check_disabled(struct efx_nic *efx) |
223 | { | |
626950db | 224 | if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { |
8b7325b4 BH |
225 | netif_err(efx, drv, efx->net_dev, |
226 | "device is disabled due to earlier errors\n"); | |
227 | return -EIO; | |
228 | } | |
229 | return 0; | |
230 | } | |
231 | ||
8ceee660 BH |
232 | /************************************************************************** |
233 | * | |
234 | * Event queue processing | |
235 | * | |
236 | *************************************************************************/ | |
237 | ||
238 | /* Process channel's event queue | |
239 | * | |
240 | * This function is responsible for processing the event queue of a | |
241 | * single channel. The caller must guarantee that this function will | |
242 | * never be concurrently called more than once on the same channel, | |
243 | * though different channels may be being processed concurrently. | |
244 | */ | |
fa236e18 | 245 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 246 | { |
fa236e18 | 247 | int spent; |
8ceee660 | 248 | |
9f2cb71c | 249 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 250 | return 0; |
8ceee660 | 251 | |
fa236e18 | 252 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
253 | if (spent && efx_channel_has_rx_queue(channel)) { |
254 | struct efx_rx_queue *rx_queue = | |
255 | efx_channel_get_rx_queue(channel); | |
256 | ||
ff734ef4 | 257 | efx_rx_flush_packet(channel); |
cce28794 | 258 | efx_fast_push_rx_descriptors(rx_queue, true); |
8ceee660 BH |
259 | } |
260 | ||
fa236e18 | 261 | return spent; |
8ceee660 BH |
262 | } |
263 | ||
8ceee660 BH |
264 | /* NAPI poll handler |
265 | * | |
266 | * NAPI guarantees serialisation of polls of the same device, which | |
267 | * provides the guarantee required by efx_process_channel(). | |
268 | */ | |
269 | static int efx_poll(struct napi_struct *napi, int budget) | |
270 | { | |
271 | struct efx_channel *channel = | |
272 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 273 | struct efx_nic *efx = channel->efx; |
fa236e18 | 274 | int spent; |
8ceee660 | 275 | |
36763266 AR |
276 | if (!efx_channel_lock_napi(channel)) |
277 | return budget; | |
278 | ||
62776d03 BH |
279 | netif_vdbg(efx, intr, efx->net_dev, |
280 | "channel %d NAPI poll executing on CPU %d\n", | |
281 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 282 | |
fa236e18 | 283 | spent = efx_process_channel(channel, budget); |
8ceee660 | 284 | |
fa236e18 | 285 | if (spent < budget) { |
9d9a6973 | 286 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
287 | efx->irq_rx_adaptive && |
288 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
289 | if (unlikely(channel->irq_mod_score < |
290 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
291 | if (channel->irq_moderation > 1) { |
292 | channel->irq_moderation -= 1; | |
ef2b90ee | 293 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 294 | } |
6fb70fd1 BH |
295 | } else if (unlikely(channel->irq_mod_score > |
296 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
297 | if (channel->irq_moderation < |
298 | efx->irq_rx_moderation) { | |
299 | channel->irq_moderation += 1; | |
ef2b90ee | 300 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 301 | } |
6fb70fd1 | 302 | } |
6fb70fd1 BH |
303 | channel->irq_count = 0; |
304 | channel->irq_mod_score = 0; | |
305 | } | |
306 | ||
64d8ad6d BH |
307 | efx_filter_rfs_expire(channel); |
308 | ||
8ceee660 | 309 | /* There is no race here; although napi_disable() will |
288379f0 | 310 | * only wait for napi_complete(), this isn't a problem |
514bedbc | 311 | * since efx_nic_eventq_read_ack() will have no effect if |
8ceee660 BH |
312 | * interrupts have already been disabled. |
313 | */ | |
288379f0 | 314 | napi_complete(napi); |
514bedbc | 315 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
316 | } |
317 | ||
36763266 | 318 | efx_channel_unlock_napi(channel); |
fa236e18 | 319 | return spent; |
8ceee660 BH |
320 | } |
321 | ||
8ceee660 BH |
322 | /* Create event queue |
323 | * Event queue memory allocations are done only once. If the channel | |
324 | * is reset, the memory buffer will be reused; this guards against | |
325 | * errors during channel reset and also simplifies interrupt handling. | |
326 | */ | |
327 | static int efx_probe_eventq(struct efx_channel *channel) | |
328 | { | |
ecc910f5 SH |
329 | struct efx_nic *efx = channel->efx; |
330 | unsigned long entries; | |
331 | ||
86ee5302 | 332 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 333 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 334 | |
ecc910f5 SH |
335 | /* Build an event queue with room for one event per tx and rx buffer, |
336 | * plus some extra for link state events and MCDI completions. */ | |
337 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
338 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
339 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
340 | ||
152b6a62 | 341 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
342 | } |
343 | ||
344 | /* Prepare channel's event queue */ | |
261e4d96 | 345 | static int efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 346 | { |
15acb1ce | 347 | struct efx_nic *efx = channel->efx; |
261e4d96 JC |
348 | int rc; |
349 | ||
350 | EFX_WARN_ON_PARANOID(channel->eventq_init); | |
351 | ||
15acb1ce | 352 | netif_dbg(efx, drv, efx->net_dev, |
62776d03 | 353 | "chan %d init event queue\n", channel->channel); |
8ceee660 | 354 | |
261e4d96 JC |
355 | rc = efx_nic_init_eventq(channel); |
356 | if (rc == 0) { | |
15acb1ce | 357 | efx->type->push_irq_moderation(channel); |
261e4d96 JC |
358 | channel->eventq_read_ptr = 0; |
359 | channel->eventq_init = true; | |
360 | } | |
361 | return rc; | |
8ceee660 BH |
362 | } |
363 | ||
9f2cb71c | 364 | /* Enable event queue processing and NAPI */ |
36763266 | 365 | void efx_start_eventq(struct efx_channel *channel) |
9f2cb71c BH |
366 | { |
367 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
368 | "chan %d start event queue\n", channel->channel); | |
369 | ||
514bedbc | 370 | /* Make sure the NAPI handler sees the enabled flag set */ |
9f2cb71c BH |
371 | channel->enabled = true; |
372 | smp_wmb(); | |
373 | ||
36763266 | 374 | efx_channel_enable(channel); |
9f2cb71c BH |
375 | napi_enable(&channel->napi_str); |
376 | efx_nic_eventq_read_ack(channel); | |
377 | } | |
378 | ||
379 | /* Disable event queue processing and NAPI */ | |
36763266 | 380 | void efx_stop_eventq(struct efx_channel *channel) |
9f2cb71c BH |
381 | { |
382 | if (!channel->enabled) | |
383 | return; | |
384 | ||
385 | napi_disable(&channel->napi_str); | |
36763266 AR |
386 | while (!efx_channel_disable(channel)) |
387 | usleep_range(1000, 20000); | |
9f2cb71c BH |
388 | channel->enabled = false; |
389 | } | |
390 | ||
8ceee660 BH |
391 | static void efx_fini_eventq(struct efx_channel *channel) |
392 | { | |
be3fc09c BH |
393 | if (!channel->eventq_init) |
394 | return; | |
395 | ||
62776d03 BH |
396 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
397 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 398 | |
152b6a62 | 399 | efx_nic_fini_eventq(channel); |
be3fc09c | 400 | channel->eventq_init = false; |
8ceee660 BH |
401 | } |
402 | ||
403 | static void efx_remove_eventq(struct efx_channel *channel) | |
404 | { | |
62776d03 BH |
405 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
406 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 407 | |
152b6a62 | 408 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
409 | } |
410 | ||
411 | /************************************************************************** | |
412 | * | |
413 | * Channel handling | |
414 | * | |
415 | *************************************************************************/ | |
416 | ||
7f967c01 | 417 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
418 | static struct efx_channel * |
419 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
420 | { | |
421 | struct efx_channel *channel; | |
422 | struct efx_rx_queue *rx_queue; | |
423 | struct efx_tx_queue *tx_queue; | |
424 | int j; | |
425 | ||
7f967c01 BH |
426 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
427 | if (!channel) | |
428 | return NULL; | |
4642610c | 429 | |
7f967c01 BH |
430 | channel->efx = efx; |
431 | channel->channel = i; | |
432 | channel->type = &efx_default_channel_type; | |
4642610c | 433 | |
7f967c01 BH |
434 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
435 | tx_queue = &channel->tx_queue[j]; | |
436 | tx_queue->efx = efx; | |
437 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
438 | tx_queue->channel = channel; | |
439 | } | |
4642610c | 440 | |
7f967c01 BH |
441 | rx_queue = &channel->rx_queue; |
442 | rx_queue->efx = efx; | |
443 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
444 | (unsigned long)rx_queue); | |
4642610c | 445 | |
7f967c01 BH |
446 | return channel; |
447 | } | |
448 | ||
449 | /* Allocate and initialise a channel structure, copying parameters | |
450 | * (but not resources) from an old channel structure. | |
451 | */ | |
452 | static struct efx_channel * | |
453 | efx_copy_channel(const struct efx_channel *old_channel) | |
454 | { | |
455 | struct efx_channel *channel; | |
456 | struct efx_rx_queue *rx_queue; | |
457 | struct efx_tx_queue *tx_queue; | |
458 | int j; | |
4642610c | 459 | |
7f967c01 BH |
460 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
461 | if (!channel) | |
462 | return NULL; | |
463 | ||
464 | *channel = *old_channel; | |
465 | ||
466 | channel->napi_dev = NULL; | |
467 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 468 | |
7f967c01 BH |
469 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
470 | tx_queue = &channel->tx_queue[j]; | |
471 | if (tx_queue->channel) | |
4642610c | 472 | tx_queue->channel = channel; |
7f967c01 BH |
473 | tx_queue->buffer = NULL; |
474 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
475 | } |
476 | ||
4642610c | 477 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
478 | rx_queue->buffer = NULL; |
479 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
480 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
481 | (unsigned long)rx_queue); | |
482 | ||
483 | return channel; | |
484 | } | |
485 | ||
8ceee660 BH |
486 | static int efx_probe_channel(struct efx_channel *channel) |
487 | { | |
488 | struct efx_tx_queue *tx_queue; | |
489 | struct efx_rx_queue *rx_queue; | |
490 | int rc; | |
491 | ||
62776d03 BH |
492 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
493 | "creating channel %d\n", channel->channel); | |
8ceee660 | 494 | |
7f967c01 BH |
495 | rc = channel->type->pre_probe(channel); |
496 | if (rc) | |
497 | goto fail; | |
498 | ||
8ceee660 BH |
499 | rc = efx_probe_eventq(channel); |
500 | if (rc) | |
7f967c01 | 501 | goto fail; |
8ceee660 BH |
502 | |
503 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
504 | rc = efx_probe_tx_queue(tx_queue); | |
505 | if (rc) | |
7f967c01 | 506 | goto fail; |
8ceee660 BH |
507 | } |
508 | ||
509 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
510 | rc = efx_probe_rx_queue(rx_queue); | |
511 | if (rc) | |
7f967c01 | 512 | goto fail; |
8ceee660 BH |
513 | } |
514 | ||
8ceee660 BH |
515 | return 0; |
516 | ||
7f967c01 BH |
517 | fail: |
518 | efx_remove_channel(channel); | |
8ceee660 BH |
519 | return rc; |
520 | } | |
521 | ||
7f967c01 BH |
522 | static void |
523 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
524 | { | |
525 | struct efx_nic *efx = channel->efx; | |
526 | const char *type; | |
527 | int number; | |
528 | ||
529 | number = channel->channel; | |
530 | if (efx->tx_channel_offset == 0) { | |
531 | type = ""; | |
532 | } else if (channel->channel < efx->tx_channel_offset) { | |
533 | type = "-rx"; | |
534 | } else { | |
535 | type = "-tx"; | |
536 | number -= efx->tx_channel_offset; | |
537 | } | |
538 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
539 | } | |
8ceee660 | 540 | |
56536e9c BH |
541 | static void efx_set_channel_names(struct efx_nic *efx) |
542 | { | |
543 | struct efx_channel *channel; | |
56536e9c | 544 | |
7f967c01 BH |
545 | efx_for_each_channel(channel, efx) |
546 | channel->type->get_name(channel, | |
d8291187 BH |
547 | efx->msi_context[channel->channel].name, |
548 | sizeof(efx->msi_context[0].name)); | |
56536e9c BH |
549 | } |
550 | ||
4642610c BH |
551 | static int efx_probe_channels(struct efx_nic *efx) |
552 | { | |
553 | struct efx_channel *channel; | |
554 | int rc; | |
555 | ||
556 | /* Restart special buffer allocation */ | |
557 | efx->next_buffer_table = 0; | |
558 | ||
c92aaff1 BH |
559 | /* Probe channels in reverse, so that any 'extra' channels |
560 | * use the start of the buffer table. This allows the traffic | |
561 | * channels to be resized without moving them or wasting the | |
562 | * entries before them. | |
563 | */ | |
564 | efx_for_each_channel_rev(channel, efx) { | |
4642610c BH |
565 | rc = efx_probe_channel(channel); |
566 | if (rc) { | |
567 | netif_err(efx, probe, efx->net_dev, | |
568 | "failed to create channel %d\n", | |
569 | channel->channel); | |
570 | goto fail; | |
571 | } | |
572 | } | |
573 | efx_set_channel_names(efx); | |
574 | ||
575 | return 0; | |
576 | ||
577 | fail: | |
578 | efx_remove_channels(efx); | |
579 | return rc; | |
580 | } | |
581 | ||
8ceee660 BH |
582 | /* Channels are shutdown and reinitialised whilst the NIC is running |
583 | * to propagate configuration changes (mtu, checksum offload), or | |
584 | * to clear hardware error conditions | |
585 | */ | |
9f2cb71c | 586 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 | 587 | { |
85740cdf | 588 | bool old_rx_scatter = efx->rx_scatter; |
8ceee660 BH |
589 | struct efx_tx_queue *tx_queue; |
590 | struct efx_rx_queue *rx_queue; | |
591 | struct efx_channel *channel; | |
85740cdf | 592 | size_t rx_buf_len; |
8ceee660 | 593 | |
f7f13b0b BH |
594 | /* Calculate the rx buffer allocation parameters required to |
595 | * support the current MTU, including padding for header | |
596 | * alignment and overruns. | |
597 | */ | |
43a3739d | 598 | efx->rx_dma_len = (efx->rx_prefix_size + |
272baeeb BH |
599 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + |
600 | efx->type->rx_buffer_padding); | |
85740cdf | 601 | rx_buf_len = (sizeof(struct efx_rx_page_state) + |
2ec03014 | 602 | efx->rx_ip_align + efx->rx_dma_len); |
85740cdf | 603 | if (rx_buf_len <= PAGE_SIZE) { |
e8c68c0a | 604 | efx->rx_scatter = efx->type->always_rx_scatter; |
85740cdf | 605 | efx->rx_buffer_order = 0; |
85740cdf | 606 | } else if (efx->type->can_rx_scatter) { |
950c54df | 607 | BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES); |
85740cdf | 608 | BUILD_BUG_ON(sizeof(struct efx_rx_page_state) + |
950c54df BH |
609 | 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE, |
610 | EFX_RX_BUF_ALIGNMENT) > | |
611 | PAGE_SIZE); | |
85740cdf BH |
612 | efx->rx_scatter = true; |
613 | efx->rx_dma_len = EFX_RX_USR_BUF_SIZE; | |
614 | efx->rx_buffer_order = 0; | |
85740cdf BH |
615 | } else { |
616 | efx->rx_scatter = false; | |
617 | efx->rx_buffer_order = get_order(rx_buf_len); | |
85740cdf BH |
618 | } |
619 | ||
1648a23f DP |
620 | efx_rx_config_page_split(efx); |
621 | if (efx->rx_buffer_order) | |
622 | netif_dbg(efx, drv, efx->net_dev, | |
623 | "RX buf len=%u; page order=%u batch=%u\n", | |
624 | efx->rx_dma_len, efx->rx_buffer_order, | |
625 | efx->rx_pages_per_batch); | |
626 | else | |
627 | netif_dbg(efx, drv, efx->net_dev, | |
628 | "RX buf len=%u step=%u bpp=%u; page batch=%u\n", | |
629 | efx->rx_dma_len, efx->rx_page_buf_step, | |
630 | efx->rx_bufs_per_page, efx->rx_pages_per_batch); | |
2768935a | 631 | |
e8c68c0a | 632 | /* RX filters may also have scatter-enabled flags */ |
85740cdf | 633 | if (efx->rx_scatter != old_rx_scatter) |
add72477 | 634 | efx->type->filter_update_rx_scatter(efx); |
8ceee660 | 635 | |
14bf718f BH |
636 | /* We must keep at least one descriptor in a TX ring empty. |
637 | * We could avoid this when the queue size does not exactly | |
638 | * match the hardware ring size, but it's not that important. | |
639 | * Therefore we stop the queue when one more skb might fill | |
640 | * the ring completely. We wake it when half way back to | |
641 | * empty. | |
642 | */ | |
643 | efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); | |
644 | efx->txq_wake_thresh = efx->txq_stop_thresh / 2; | |
645 | ||
8ceee660 BH |
646 | /* Initialise the channels */ |
647 | efx_for_each_channel(channel, efx) { | |
3881d8ab | 648 | efx_for_each_channel_tx_queue(tx_queue, channel) { |
bc3c90a2 | 649 | efx_init_tx_queue(tx_queue); |
3881d8ab AR |
650 | atomic_inc(&efx->active_queues); |
651 | } | |
8ceee660 | 652 | |
9f2cb71c | 653 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 654 | efx_init_rx_queue(rx_queue); |
3881d8ab | 655 | atomic_inc(&efx->active_queues); |
cce28794 JC |
656 | efx_stop_eventq(channel); |
657 | efx_fast_push_rx_descriptors(rx_queue, false); | |
658 | efx_start_eventq(channel); | |
9f2cb71c | 659 | } |
8ceee660 | 660 | |
85740cdf | 661 | WARN_ON(channel->rx_pkt_n_frags); |
8ceee660 | 662 | } |
8ceee660 | 663 | |
2ea4dc28 AR |
664 | efx_ptp_start_datapath(efx); |
665 | ||
9f2cb71c BH |
666 | if (netif_device_present(efx->net_dev)) |
667 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
668 | } |
669 | ||
9f2cb71c | 670 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
671 | { |
672 | struct efx_channel *channel; | |
673 | struct efx_tx_queue *tx_queue; | |
674 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 675 | int rc; |
8ceee660 BH |
676 | |
677 | EFX_ASSERT_RESET_SERIALISED(efx); | |
678 | BUG_ON(efx->port_enabled); | |
679 | ||
2ea4dc28 AR |
680 | efx_ptp_stop_datapath(efx); |
681 | ||
d8aec745 BH |
682 | /* Stop RX refill */ |
683 | efx_for_each_channel(channel, efx) { | |
684 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
685 | rx_queue->refill_enabled = false; | |
686 | } | |
687 | ||
8ceee660 | 688 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
689 | /* RX packet processing is pipelined, so wait for the |
690 | * NAPI handler to complete. At least event queue 0 | |
691 | * might be kept active by non-data events, so don't | |
692 | * use napi_synchronize() but actually disable NAPI | |
693 | * temporarily. | |
694 | */ | |
695 | if (efx_channel_has_rx_queue(channel)) { | |
696 | efx_stop_eventq(channel); | |
697 | efx_start_eventq(channel); | |
698 | } | |
e42c3d85 | 699 | } |
8ceee660 | 700 | |
e42c3d85 BH |
701 | rc = efx->type->fini_dmaq(efx); |
702 | if (rc && EFX_WORKAROUND_7803(efx)) { | |
703 | /* Schedule a reset to recover from the flush failure. The | |
704 | * descriptor caches reference memory we're about to free, | |
705 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
706 | * the MACs because of the pending reset. | |
707 | */ | |
708 | netif_err(efx, drv, efx->net_dev, | |
709 | "Resetting to recover from flush failure\n"); | |
710 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
711 | } else if (rc) { | |
712 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); | |
713 | } else { | |
714 | netif_dbg(efx, drv, efx->net_dev, | |
715 | "successfully flushed all queues\n"); | |
716 | } | |
717 | ||
718 | efx_for_each_channel(channel, efx) { | |
8ceee660 BH |
719 | efx_for_each_channel_rx_queue(rx_queue, channel) |
720 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 721 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 722 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
723 | } |
724 | } | |
725 | ||
726 | static void efx_remove_channel(struct efx_channel *channel) | |
727 | { | |
728 | struct efx_tx_queue *tx_queue; | |
729 | struct efx_rx_queue *rx_queue; | |
730 | ||
62776d03 BH |
731 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
732 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
733 | |
734 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
735 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 736 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
737 | efx_remove_tx_queue(tx_queue); |
738 | efx_remove_eventq(channel); | |
c31e5f9f | 739 | channel->type->post_remove(channel); |
8ceee660 BH |
740 | } |
741 | ||
4642610c BH |
742 | static void efx_remove_channels(struct efx_nic *efx) |
743 | { | |
744 | struct efx_channel *channel; | |
745 | ||
746 | efx_for_each_channel(channel, efx) | |
747 | efx_remove_channel(channel); | |
748 | } | |
749 | ||
750 | int | |
751 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
752 | { | |
753 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
754 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 | 755 | unsigned i, next_buffer_table = 0; |
261e4d96 | 756 | int rc, rc2; |
8b7325b4 BH |
757 | |
758 | rc = efx_check_disabled(efx); | |
759 | if (rc) | |
760 | return rc; | |
7f967c01 BH |
761 | |
762 | /* Not all channels should be reallocated. We must avoid | |
763 | * reallocating their buffer table entries. | |
764 | */ | |
765 | efx_for_each_channel(channel, efx) { | |
766 | struct efx_rx_queue *rx_queue; | |
767 | struct efx_tx_queue *tx_queue; | |
768 | ||
769 | if (channel->type->copy) | |
770 | continue; | |
771 | next_buffer_table = max(next_buffer_table, | |
772 | channel->eventq.index + | |
773 | channel->eventq.entries); | |
774 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
775 | next_buffer_table = max(next_buffer_table, | |
776 | rx_queue->rxd.index + | |
777 | rx_queue->rxd.entries); | |
778 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
779 | next_buffer_table = max(next_buffer_table, | |
780 | tx_queue->txd.index + | |
781 | tx_queue->txd.entries); | |
782 | } | |
4642610c | 783 | |
29c69a48 | 784 | efx_device_detach_sync(efx); |
4642610c | 785 | efx_stop_all(efx); |
d8291187 | 786 | efx_soft_disable_interrupts(efx); |
4642610c | 787 | |
7f967c01 | 788 | /* Clone channels (where possible) */ |
4642610c BH |
789 | memset(other_channel, 0, sizeof(other_channel)); |
790 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
791 | channel = efx->channel[i]; |
792 | if (channel->type->copy) | |
793 | channel = channel->type->copy(channel); | |
4642610c BH |
794 | if (!channel) { |
795 | rc = -ENOMEM; | |
796 | goto out; | |
797 | } | |
798 | other_channel[i] = channel; | |
799 | } | |
800 | ||
801 | /* Swap entry counts and channel pointers */ | |
802 | old_rxq_entries = efx->rxq_entries; | |
803 | old_txq_entries = efx->txq_entries; | |
804 | efx->rxq_entries = rxq_entries; | |
805 | efx->txq_entries = txq_entries; | |
806 | for (i = 0; i < efx->n_channels; i++) { | |
807 | channel = efx->channel[i]; | |
808 | efx->channel[i] = other_channel[i]; | |
809 | other_channel[i] = channel; | |
810 | } | |
811 | ||
7f967c01 BH |
812 | /* Restart buffer table allocation */ |
813 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 814 | |
e8f14992 | 815 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
816 | channel = efx->channel[i]; |
817 | if (!channel->type->copy) | |
818 | continue; | |
819 | rc = efx_probe_channel(channel); | |
820 | if (rc) | |
821 | goto rollback; | |
822 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 823 | } |
7f967c01 | 824 | |
4642610c | 825 | out: |
7f967c01 BH |
826 | /* Destroy unused channel structures */ |
827 | for (i = 0; i < efx->n_channels; i++) { | |
828 | channel = other_channel[i]; | |
829 | if (channel && channel->type->copy) { | |
830 | efx_fini_napi_channel(channel); | |
831 | efx_remove_channel(channel); | |
832 | kfree(channel); | |
833 | } | |
834 | } | |
4642610c | 835 | |
261e4d96 JC |
836 | rc2 = efx_soft_enable_interrupts(efx); |
837 | if (rc2) { | |
838 | rc = rc ? rc : rc2; | |
839 | netif_err(efx, drv, efx->net_dev, | |
840 | "unable to restart interrupts on channel reallocation\n"); | |
841 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
842 | } else { | |
843 | efx_start_all(efx); | |
844 | netif_device_attach(efx->net_dev); | |
845 | } | |
4642610c BH |
846 | return rc; |
847 | ||
848 | rollback: | |
849 | /* Swap back */ | |
850 | efx->rxq_entries = old_rxq_entries; | |
851 | efx->txq_entries = old_txq_entries; | |
852 | for (i = 0; i < efx->n_channels; i++) { | |
853 | channel = efx->channel[i]; | |
854 | efx->channel[i] = other_channel[i]; | |
855 | other_channel[i] = channel; | |
856 | } | |
857 | goto out; | |
858 | } | |
859 | ||
90d683af | 860 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 861 | { |
90d683af | 862 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
863 | } |
864 | ||
7f967c01 BH |
865 | static const struct efx_channel_type efx_default_channel_type = { |
866 | .pre_probe = efx_channel_dummy_op_int, | |
c31e5f9f | 867 | .post_remove = efx_channel_dummy_op_void, |
7f967c01 BH |
868 | .get_name = efx_get_channel_name, |
869 | .copy = efx_copy_channel, | |
870 | .keep_eventq = false, | |
871 | }; | |
872 | ||
873 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
874 | { | |
875 | return 0; | |
876 | } | |
877 | ||
c31e5f9f SH |
878 | void efx_channel_dummy_op_void(struct efx_channel *channel) |
879 | { | |
880 | } | |
881 | ||
8ceee660 BH |
882 | /************************************************************************** |
883 | * | |
884 | * Port handling | |
885 | * | |
886 | **************************************************************************/ | |
887 | ||
888 | /* This ensures that the kernel is kept informed (via | |
889 | * netif_carrier_on/off) of the link status, and also maintains the | |
890 | * link status's stop on the port's TX queue. | |
891 | */ | |
fdaa9aed | 892 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 893 | { |
eb50c0d6 BH |
894 | struct efx_link_state *link_state = &efx->link_state; |
895 | ||
8ceee660 BH |
896 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
897 | * that no events are triggered between unregister_netdev() and the | |
898 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
899 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
900 | if (!netif_running(efx->net_dev)) | |
901 | return; | |
902 | ||
eb50c0d6 | 903 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
904 | efx->n_link_state_changes++; |
905 | ||
eb50c0d6 | 906 | if (link_state->up) |
8ceee660 BH |
907 | netif_carrier_on(efx->net_dev); |
908 | else | |
909 | netif_carrier_off(efx->net_dev); | |
910 | } | |
911 | ||
912 | /* Status message for kernel log */ | |
2aa9ef11 | 913 | if (link_state->up) |
62776d03 | 914 | netif_info(efx, link, efx->net_dev, |
964e6135 | 915 | "link up at %uMbps %s-duplex (MTU %d)\n", |
62776d03 | 916 | link_state->speed, link_state->fd ? "full" : "half", |
964e6135 | 917 | efx->net_dev->mtu); |
2aa9ef11 | 918 | else |
62776d03 | 919 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
920 | } |
921 | ||
d3245b28 BH |
922 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
923 | { | |
924 | efx->link_advertising = advertising; | |
925 | if (advertising) { | |
926 | if (advertising & ADVERTISED_Pause) | |
927 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
928 | else | |
929 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
930 | if (advertising & ADVERTISED_Asym_Pause) | |
931 | efx->wanted_fc ^= EFX_FC_TX; | |
932 | } | |
933 | } | |
934 | ||
b5626946 | 935 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
936 | { |
937 | efx->wanted_fc = wanted_fc; | |
938 | if (efx->link_advertising) { | |
939 | if (wanted_fc & EFX_FC_RX) | |
940 | efx->link_advertising |= (ADVERTISED_Pause | | |
941 | ADVERTISED_Asym_Pause); | |
942 | else | |
943 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
944 | ADVERTISED_Asym_Pause); | |
945 | if (wanted_fc & EFX_FC_TX) | |
946 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
947 | } | |
948 | } | |
949 | ||
115122af BH |
950 | static void efx_fini_port(struct efx_nic *efx); |
951 | ||
d3245b28 BH |
952 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
953 | * the MAC appropriately. All other PHY configuration changes are pushed | |
954 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
955 | * through efx_monitor(). | |
956 | * | |
957 | * Callers must hold the mac_lock | |
958 | */ | |
959 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 960 | { |
d3245b28 BH |
961 | enum efx_phy_mode phy_mode; |
962 | int rc; | |
8ceee660 | 963 | |
d3245b28 | 964 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 965 | |
d3245b28 BH |
966 | /* Disable PHY transmit in mac level loopbacks */ |
967 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
968 | if (LOOPBACK_INTERNAL(efx)) |
969 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
970 | else | |
971 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 972 | |
d3245b28 | 973 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 974 | |
d3245b28 BH |
975 | if (rc) |
976 | efx->phy_mode = phy_mode; | |
177dfcd8 | 977 | |
d3245b28 | 978 | return rc; |
8ceee660 BH |
979 | } |
980 | ||
981 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
982 | * disabled. */ | |
d3245b28 | 983 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 984 | { |
d3245b28 BH |
985 | int rc; |
986 | ||
8ceee660 BH |
987 | EFX_ASSERT_RESET_SERIALISED(efx); |
988 | ||
989 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 990 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 991 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
992 | |
993 | return rc; | |
8ceee660 BH |
994 | } |
995 | ||
8be4f3e6 BH |
996 | /* Asynchronous work item for changing MAC promiscuity and multicast |
997 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
998 | * MAC directly. */ | |
766ca0fa BH |
999 | static void efx_mac_work(struct work_struct *data) |
1000 | { | |
1001 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
1002 | ||
1003 | mutex_lock(&efx->mac_lock); | |
30b81cda | 1004 | if (efx->port_enabled) |
710b208d | 1005 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
1006 | mutex_unlock(&efx->mac_lock); |
1007 | } | |
1008 | ||
8ceee660 BH |
1009 | static int efx_probe_port(struct efx_nic *efx) |
1010 | { | |
1011 | int rc; | |
1012 | ||
62776d03 | 1013 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 1014 | |
ff3b00a0 SH |
1015 | if (phy_flash_cfg) |
1016 | efx->phy_mode = PHY_MODE_SPECIAL; | |
1017 | ||
ef2b90ee BH |
1018 | /* Connect up MAC/PHY operations table */ |
1019 | rc = efx->type->probe_port(efx); | |
8ceee660 | 1020 | if (rc) |
e42de262 | 1021 | return rc; |
8ceee660 | 1022 | |
e332bcb3 | 1023 | /* Initialise MAC address to permanent address */ |
cd84ff4d | 1024 | ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr); |
8ceee660 BH |
1025 | |
1026 | return 0; | |
8ceee660 BH |
1027 | } |
1028 | ||
1029 | static int efx_init_port(struct efx_nic *efx) | |
1030 | { | |
1031 | int rc; | |
1032 | ||
62776d03 | 1033 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 1034 | |
1dfc5cea BH |
1035 | mutex_lock(&efx->mac_lock); |
1036 | ||
177dfcd8 | 1037 | rc = efx->phy_op->init(efx); |
8ceee660 | 1038 | if (rc) |
1dfc5cea | 1039 | goto fail1; |
8ceee660 | 1040 | |
dc8cfa55 | 1041 | efx->port_initialized = true; |
1dfc5cea | 1042 | |
d3245b28 BH |
1043 | /* Reconfigure the MAC before creating dma queues (required for |
1044 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 1045 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1046 | |
1047 | /* Ensure the PHY advertises the correct flow control settings */ | |
1048 | rc = efx->phy_op->reconfigure(efx); | |
267d9d73 | 1049 | if (rc && rc != -EPERM) |
d3245b28 BH |
1050 | goto fail2; |
1051 | ||
1dfc5cea | 1052 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1053 | return 0; |
177dfcd8 | 1054 | |
1dfc5cea | 1055 | fail2: |
177dfcd8 | 1056 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1057 | fail1: |
1058 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1059 | return rc; |
8ceee660 BH |
1060 | } |
1061 | ||
8ceee660 BH |
1062 | static void efx_start_port(struct efx_nic *efx) |
1063 | { | |
62776d03 | 1064 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1065 | BUG_ON(efx->port_enabled); |
1066 | ||
1067 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1068 | efx->port_enabled = true; |
8be4f3e6 | 1069 | |
d615c039 | 1070 | /* Ensure MAC ingress/egress is enabled */ |
710b208d | 1071 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 1072 | |
8ceee660 BH |
1073 | mutex_unlock(&efx->mac_lock); |
1074 | } | |
1075 | ||
d615c039 BH |
1076 | /* Cancel work for MAC reconfiguration, periodic hardware monitoring |
1077 | * and the async self-test, wait for them to finish and prevent them | |
1078 | * being scheduled again. This doesn't cover online resets, which | |
1079 | * should only be cancelled when removing the device. | |
1080 | */ | |
8ceee660 BH |
1081 | static void efx_stop_port(struct efx_nic *efx) |
1082 | { | |
62776d03 | 1083 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 | 1084 | |
d615c039 BH |
1085 | EFX_ASSERT_RESET_SERIALISED(efx); |
1086 | ||
8ceee660 | 1087 | mutex_lock(&efx->mac_lock); |
dc8cfa55 | 1088 | efx->port_enabled = false; |
8ceee660 BH |
1089 | mutex_unlock(&efx->mac_lock); |
1090 | ||
1091 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1092 | netif_addr_lock_bh(efx->net_dev); |
1093 | netif_addr_unlock_bh(efx->net_dev); | |
d615c039 BH |
1094 | |
1095 | cancel_delayed_work_sync(&efx->monitor_work); | |
1096 | efx_selftest_async_cancel(efx); | |
1097 | cancel_work_sync(&efx->mac_work); | |
8ceee660 BH |
1098 | } |
1099 | ||
1100 | static void efx_fini_port(struct efx_nic *efx) | |
1101 | { | |
62776d03 | 1102 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1103 | |
1104 | if (!efx->port_initialized) | |
1105 | return; | |
1106 | ||
177dfcd8 | 1107 | efx->phy_op->fini(efx); |
dc8cfa55 | 1108 | efx->port_initialized = false; |
8ceee660 | 1109 | |
eb50c0d6 | 1110 | efx->link_state.up = false; |
8ceee660 BH |
1111 | efx_link_status_changed(efx); |
1112 | } | |
1113 | ||
1114 | static void efx_remove_port(struct efx_nic *efx) | |
1115 | { | |
62776d03 | 1116 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1117 | |
ef2b90ee | 1118 | efx->type->remove_port(efx); |
8ceee660 BH |
1119 | } |
1120 | ||
1121 | /************************************************************************** | |
1122 | * | |
1123 | * NIC handling | |
1124 | * | |
1125 | **************************************************************************/ | |
1126 | ||
0bcf4a64 BH |
1127 | static LIST_HEAD(efx_primary_list); |
1128 | static LIST_HEAD(efx_unassociated_list); | |
1129 | ||
1130 | static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right) | |
1131 | { | |
1132 | return left->type == right->type && | |
1133 | left->vpd_sn && right->vpd_sn && | |
1134 | !strcmp(left->vpd_sn, right->vpd_sn); | |
1135 | } | |
1136 | ||
1137 | static void efx_associate(struct efx_nic *efx) | |
1138 | { | |
1139 | struct efx_nic *other, *next; | |
1140 | ||
1141 | if (efx->primary == efx) { | |
1142 | /* Adding primary function; look for secondaries */ | |
1143 | ||
1144 | netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n"); | |
1145 | list_add_tail(&efx->node, &efx_primary_list); | |
1146 | ||
1147 | list_for_each_entry_safe(other, next, &efx_unassociated_list, | |
1148 | node) { | |
1149 | if (efx_same_controller(efx, other)) { | |
1150 | list_del(&other->node); | |
1151 | netif_dbg(other, probe, other->net_dev, | |
1152 | "moving to secondary list of %s %s\n", | |
1153 | pci_name(efx->pci_dev), | |
1154 | efx->net_dev->name); | |
1155 | list_add_tail(&other->node, | |
1156 | &efx->secondary_list); | |
1157 | other->primary = efx; | |
1158 | } | |
1159 | } | |
1160 | } else { | |
1161 | /* Adding secondary function; look for primary */ | |
1162 | ||
1163 | list_for_each_entry(other, &efx_primary_list, node) { | |
1164 | if (efx_same_controller(efx, other)) { | |
1165 | netif_dbg(efx, probe, efx->net_dev, | |
1166 | "adding to secondary list of %s %s\n", | |
1167 | pci_name(other->pci_dev), | |
1168 | other->net_dev->name); | |
1169 | list_add_tail(&efx->node, | |
1170 | &other->secondary_list); | |
1171 | efx->primary = other; | |
1172 | return; | |
1173 | } | |
1174 | } | |
1175 | ||
1176 | netif_dbg(efx, probe, efx->net_dev, | |
1177 | "adding to unassociated list\n"); | |
1178 | list_add_tail(&efx->node, &efx_unassociated_list); | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | static void efx_dissociate(struct efx_nic *efx) | |
1183 | { | |
1184 | struct efx_nic *other, *next; | |
1185 | ||
1186 | list_del(&efx->node); | |
1187 | efx->primary = NULL; | |
1188 | ||
1189 | list_for_each_entry_safe(other, next, &efx->secondary_list, node) { | |
1190 | list_del(&other->node); | |
1191 | netif_dbg(other, probe, other->net_dev, | |
1192 | "moving to unassociated list\n"); | |
1193 | list_add_tail(&other->node, &efx_unassociated_list); | |
1194 | other->primary = NULL; | |
1195 | } | |
1196 | } | |
1197 | ||
8ceee660 BH |
1198 | /* This configures the PCI device to enable I/O and DMA. */ |
1199 | static int efx_init_io(struct efx_nic *efx) | |
1200 | { | |
1201 | struct pci_dev *pci_dev = efx->pci_dev; | |
1202 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
b105798f | 1203 | unsigned int mem_map_size = efx->type->mem_map_size(efx); |
02246a7f | 1204 | int rc, bar; |
8ceee660 | 1205 | |
62776d03 | 1206 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 | 1207 | |
02246a7f SS |
1208 | bar = efx->type->mem_bar; |
1209 | ||
8ceee660 BH |
1210 | rc = pci_enable_device(pci_dev); |
1211 | if (rc) { | |
62776d03 BH |
1212 | netif_err(efx, probe, efx->net_dev, |
1213 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1214 | goto fail1; |
1215 | } | |
1216 | ||
1217 | pci_set_master(pci_dev); | |
1218 | ||
1219 | /* Set the PCI DMA mask. Try all possibilities from our | |
1220 | * genuine mask down to 32 bits, because some architectures | |
1221 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1222 | * masks event though they reject 46 bit masks. | |
1223 | */ | |
1224 | while (dma_mask > 0x7fffffffUL) { | |
0e33d870 | 1225 | if (dma_supported(&pci_dev->dev, dma_mask)) { |
9663deda | 1226 | rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask); |
e9e01846 BH |
1227 | if (rc == 0) |
1228 | break; | |
1229 | } | |
8ceee660 BH |
1230 | dma_mask >>= 1; |
1231 | } | |
1232 | if (rc) { | |
62776d03 BH |
1233 | netif_err(efx, probe, efx->net_dev, |
1234 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1235 | goto fail2; |
1236 | } | |
62776d03 BH |
1237 | netif_dbg(efx, probe, efx->net_dev, |
1238 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 | 1239 | |
02246a7f SS |
1240 | efx->membase_phys = pci_resource_start(efx->pci_dev, bar); |
1241 | rc = pci_request_region(pci_dev, bar, "sfc"); | |
8ceee660 | 1242 | if (rc) { |
62776d03 BH |
1243 | netif_err(efx, probe, efx->net_dev, |
1244 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1245 | rc = -EIO; |
1246 | goto fail3; | |
1247 | } | |
b105798f | 1248 | efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); |
8ceee660 | 1249 | if (!efx->membase) { |
62776d03 BH |
1250 | netif_err(efx, probe, efx->net_dev, |
1251 | "could not map memory BAR at %llx+%x\n", | |
b105798f | 1252 | (unsigned long long)efx->membase_phys, mem_map_size); |
8ceee660 BH |
1253 | rc = -ENOMEM; |
1254 | goto fail4; | |
1255 | } | |
62776d03 BH |
1256 | netif_dbg(efx, probe, efx->net_dev, |
1257 | "memory BAR at %llx+%x (virtual %p)\n", | |
b105798f BH |
1258 | (unsigned long long)efx->membase_phys, mem_map_size, |
1259 | efx->membase); | |
8ceee660 BH |
1260 | |
1261 | return 0; | |
1262 | ||
1263 | fail4: | |
02246a7f | 1264 | pci_release_region(efx->pci_dev, bar); |
8ceee660 | 1265 | fail3: |
2c118e0f | 1266 | efx->membase_phys = 0; |
8ceee660 BH |
1267 | fail2: |
1268 | pci_disable_device(efx->pci_dev); | |
1269 | fail1: | |
1270 | return rc; | |
1271 | } | |
1272 | ||
1273 | static void efx_fini_io(struct efx_nic *efx) | |
1274 | { | |
02246a7f SS |
1275 | int bar; |
1276 | ||
62776d03 | 1277 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1278 | |
1279 | if (efx->membase) { | |
1280 | iounmap(efx->membase); | |
1281 | efx->membase = NULL; | |
1282 | } | |
1283 | ||
1284 | if (efx->membase_phys) { | |
02246a7f SS |
1285 | bar = efx->type->mem_bar; |
1286 | pci_release_region(efx->pci_dev, bar); | |
2c118e0f | 1287 | efx->membase_phys = 0; |
8ceee660 BH |
1288 | } |
1289 | ||
1290 | pci_disable_device(efx->pci_dev); | |
1291 | } | |
1292 | ||
a9a52506 | 1293 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1294 | { |
cdb08f8f | 1295 | cpumask_var_t thread_mask; |
a16e5b24 | 1296 | unsigned int count; |
46123d04 | 1297 | int cpu; |
5b874e25 | 1298 | |
cd2d5b52 BH |
1299 | if (rss_cpus) { |
1300 | count = rss_cpus; | |
1301 | } else { | |
1302 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1303 | netif_warn(efx, probe, efx->net_dev, | |
1304 | "RSS disabled due to allocation failure\n"); | |
1305 | return 1; | |
1306 | } | |
46123d04 | 1307 | |
cd2d5b52 BH |
1308 | count = 0; |
1309 | for_each_online_cpu(cpu) { | |
1310 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1311 | ++count; | |
1312 | cpumask_or(thread_mask, thread_mask, | |
1313 | topology_thread_cpumask(cpu)); | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1318 | } |
1319 | ||
cd2d5b52 BH |
1320 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1321 | * table entries that are inaccessible to VFs | |
1322 | */ | |
7fa8d547 SS |
1323 | #ifdef CONFIG_SFC_SRIOV |
1324 | if (efx->type->sriov_wanted) { | |
1325 | if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1326 | count > efx_vf_size(efx)) { | |
1327 | netif_warn(efx, probe, efx->net_dev, | |
1328 | "Reducing number of RSS channels from %u to %u for " | |
1329 | "VF support. Increase vf-msix-limit to use more " | |
1330 | "channels on the PF.\n", | |
1331 | count, efx_vf_size(efx)); | |
1332 | count = efx_vf_size(efx); | |
1333 | } | |
46123d04 | 1334 | } |
7fa8d547 | 1335 | #endif |
46123d04 BH |
1336 | |
1337 | return count; | |
1338 | } | |
1339 | ||
1340 | /* Probe the number and type of interrupts we are able to obtain, and | |
1341 | * the resulting numbers of channels and RX queues. | |
1342 | */ | |
64d8ad6d | 1343 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1344 | { |
7f967c01 BH |
1345 | unsigned int extra_channels = 0; |
1346 | unsigned int i, j; | |
a16e5b24 | 1347 | int rc; |
8ceee660 | 1348 | |
7f967c01 BH |
1349 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1350 | if (efx->extra_channel_type[i]) | |
1351 | ++extra_channels; | |
1352 | ||
8ceee660 | 1353 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1354 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1355 | unsigned int n_channels; |
aa6ef27e | 1356 | |
a9a52506 | 1357 | n_channels = efx_wanted_parallelism(efx); |
a4900ac9 BH |
1358 | if (separate_tx_channels) |
1359 | n_channels *= 2; | |
7f967c01 | 1360 | n_channels += extra_channels; |
b105798f | 1361 | n_channels = min(n_channels, efx->max_channels); |
8ceee660 | 1362 | |
a4900ac9 | 1363 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1364 | xentries[i].entry = i; |
184603d8 AG |
1365 | rc = pci_enable_msix_range(efx->pci_dev, |
1366 | xentries, 1, n_channels); | |
1367 | if (rc < 0) { | |
1368 | /* Fall back to single channel MSI */ | |
1369 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
1370 | netif_err(efx, drv, efx->net_dev, | |
1371 | "could not enable MSI-X\n"); | |
1372 | } else if (rc < n_channels) { | |
62776d03 BH |
1373 | netif_err(efx, drv, efx->net_dev, |
1374 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1375 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1376 | netif_err(efx, drv, efx->net_dev, |
1377 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 | 1378 | n_channels = rc; |
8ceee660 BH |
1379 | } |
1380 | ||
184603d8 | 1381 | if (rc > 0) { |
a4900ac9 | 1382 | efx->n_channels = n_channels; |
7f967c01 BH |
1383 | if (n_channels > extra_channels) |
1384 | n_channels -= extra_channels; | |
a4900ac9 | 1385 | if (separate_tx_channels) { |
7f967c01 BH |
1386 | efx->n_tx_channels = max(n_channels / 2, 1U); |
1387 | efx->n_rx_channels = max(n_channels - | |
1388 | efx->n_tx_channels, | |
1389 | 1U); | |
a4900ac9 | 1390 | } else { |
7f967c01 BH |
1391 | efx->n_tx_channels = n_channels; |
1392 | efx->n_rx_channels = n_channels; | |
a4900ac9 | 1393 | } |
7f967c01 | 1394 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1395 | efx_get_channel(efx, i)->irq = |
1396 | xentries[i].vector; | |
8ceee660 BH |
1397 | } |
1398 | } | |
1399 | ||
1400 | /* Try single interrupt MSI */ | |
1401 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1402 | efx->n_channels = 1; |
a4900ac9 BH |
1403 | efx->n_rx_channels = 1; |
1404 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1405 | rc = pci_enable_msi(efx->pci_dev); |
1406 | if (rc == 0) { | |
f7d12cdc | 1407 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1408 | } else { |
62776d03 BH |
1409 | netif_err(efx, drv, efx->net_dev, |
1410 | "could not enable MSI\n"); | |
8ceee660 BH |
1411 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1412 | } | |
1413 | } | |
1414 | ||
1415 | /* Assume legacy interrupts */ | |
1416 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1417 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1418 | efx->n_rx_channels = 1; |
1419 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1420 | efx->legacy_irq = efx->pci_dev->irq; |
1421 | } | |
64d8ad6d | 1422 | |
7f967c01 BH |
1423 | /* Assign extra channels if possible */ |
1424 | j = efx->n_channels; | |
1425 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1426 | if (!efx->extra_channel_type[i]) | |
1427 | continue; | |
1428 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1429 | efx->n_channels <= extra_channels) { | |
1430 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1431 | } else { | |
1432 | --j; | |
1433 | efx_get_channel(efx, j)->type = | |
1434 | efx->extra_channel_type[i]; | |
1435 | } | |
1436 | } | |
1437 | ||
cd2d5b52 | 1438 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
7fa8d547 SS |
1439 | #ifdef CONFIG_SFC_SRIOV |
1440 | if (efx->type->sriov_wanted) { | |
1441 | efx->rss_spread = ((efx->n_rx_channels > 1 || | |
1442 | !efx->type->sriov_wanted(efx)) ? | |
1443 | efx->n_rx_channels : efx_vf_size(efx)); | |
1444 | return 0; | |
1445 | } | |
1446 | #endif | |
1447 | efx->rss_spread = efx->n_rx_channels; | |
64d8ad6d | 1448 | return 0; |
8ceee660 BH |
1449 | } |
1450 | ||
261e4d96 | 1451 | static int efx_soft_enable_interrupts(struct efx_nic *efx) |
9f2cb71c | 1452 | { |
261e4d96 JC |
1453 | struct efx_channel *channel, *end_channel; |
1454 | int rc; | |
9f2cb71c | 1455 | |
8b7325b4 BH |
1456 | BUG_ON(efx->state == STATE_DISABLED); |
1457 | ||
d8291187 BH |
1458 | efx->irq_soft_enabled = true; |
1459 | smp_wmb(); | |
9f2cb71c BH |
1460 | |
1461 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1462 | if (!channel->type->keep_eventq) { |
1463 | rc = efx_init_eventq(channel); | |
1464 | if (rc) | |
1465 | goto fail; | |
1466 | } | |
9f2cb71c BH |
1467 | efx_start_eventq(channel); |
1468 | } | |
1469 | ||
1470 | efx_mcdi_mode_event(efx); | |
261e4d96 JC |
1471 | |
1472 | return 0; | |
1473 | fail: | |
1474 | end_channel = channel; | |
1475 | efx_for_each_channel(channel, efx) { | |
1476 | if (channel == end_channel) | |
1477 | break; | |
1478 | efx_stop_eventq(channel); | |
1479 | if (!channel->type->keep_eventq) | |
1480 | efx_fini_eventq(channel); | |
1481 | } | |
1482 | ||
1483 | return rc; | |
9f2cb71c BH |
1484 | } |
1485 | ||
d8291187 | 1486 | static void efx_soft_disable_interrupts(struct efx_nic *efx) |
9f2cb71c BH |
1487 | { |
1488 | struct efx_channel *channel; | |
1489 | ||
8b7325b4 BH |
1490 | if (efx->state == STATE_DISABLED) |
1491 | return; | |
1492 | ||
9f2cb71c BH |
1493 | efx_mcdi_mode_poll(efx); |
1494 | ||
d8291187 BH |
1495 | efx->irq_soft_enabled = false; |
1496 | smp_wmb(); | |
1497 | ||
1498 | if (efx->legacy_irq) | |
9f2cb71c | 1499 | synchronize_irq(efx->legacy_irq); |
9f2cb71c BH |
1500 | |
1501 | efx_for_each_channel(channel, efx) { | |
1502 | if (channel->irq) | |
1503 | synchronize_irq(channel->irq); | |
1504 | ||
1505 | efx_stop_eventq(channel); | |
d8291187 | 1506 | if (!channel->type->keep_eventq) |
7f967c01 | 1507 | efx_fini_eventq(channel); |
9f2cb71c | 1508 | } |
cade715f BH |
1509 | |
1510 | /* Flush the asynchronous MCDI request queue */ | |
1511 | efx_mcdi_flush_async(efx); | |
9f2cb71c BH |
1512 | } |
1513 | ||
261e4d96 | 1514 | static int efx_enable_interrupts(struct efx_nic *efx) |
d8291187 | 1515 | { |
261e4d96 JC |
1516 | struct efx_channel *channel, *end_channel; |
1517 | int rc; | |
d8291187 BH |
1518 | |
1519 | BUG_ON(efx->state == STATE_DISABLED); | |
1520 | ||
1521 | if (efx->eeh_disabled_legacy_irq) { | |
1522 | enable_irq(efx->legacy_irq); | |
1523 | efx->eeh_disabled_legacy_irq = false; | |
1524 | } | |
1525 | ||
86094f7f | 1526 | efx->type->irq_enable_master(efx); |
d8291187 BH |
1527 | |
1528 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1529 | if (channel->type->keep_eventq) { |
1530 | rc = efx_init_eventq(channel); | |
1531 | if (rc) | |
1532 | goto fail; | |
1533 | } | |
1534 | } | |
1535 | ||
1536 | rc = efx_soft_enable_interrupts(efx); | |
1537 | if (rc) | |
1538 | goto fail; | |
1539 | ||
1540 | return 0; | |
1541 | ||
1542 | fail: | |
1543 | end_channel = channel; | |
1544 | efx_for_each_channel(channel, efx) { | |
1545 | if (channel == end_channel) | |
1546 | break; | |
d8291187 | 1547 | if (channel->type->keep_eventq) |
261e4d96 | 1548 | efx_fini_eventq(channel); |
d8291187 BH |
1549 | } |
1550 | ||
261e4d96 JC |
1551 | efx->type->irq_disable_non_ev(efx); |
1552 | ||
1553 | return rc; | |
d8291187 BH |
1554 | } |
1555 | ||
1556 | static void efx_disable_interrupts(struct efx_nic *efx) | |
1557 | { | |
1558 | struct efx_channel *channel; | |
1559 | ||
1560 | efx_soft_disable_interrupts(efx); | |
1561 | ||
1562 | efx_for_each_channel(channel, efx) { | |
1563 | if (channel->type->keep_eventq) | |
1564 | efx_fini_eventq(channel); | |
1565 | } | |
1566 | ||
86094f7f | 1567 | efx->type->irq_disable_non_ev(efx); |
d8291187 BH |
1568 | } |
1569 | ||
8ceee660 BH |
1570 | static void efx_remove_interrupts(struct efx_nic *efx) |
1571 | { | |
1572 | struct efx_channel *channel; | |
1573 | ||
1574 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1575 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1576 | channel->irq = 0; |
1577 | pci_disable_msi(efx->pci_dev); | |
1578 | pci_disable_msix(efx->pci_dev); | |
1579 | ||
1580 | /* Remove legacy interrupt */ | |
1581 | efx->legacy_irq = 0; | |
1582 | } | |
1583 | ||
8831da7b | 1584 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1585 | { |
602a5322 BH |
1586 | struct efx_channel *channel; |
1587 | struct efx_tx_queue *tx_queue; | |
1588 | ||
97653431 | 1589 | efx->tx_channel_offset = |
a4900ac9 | 1590 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 | 1591 | |
79d68b37 SH |
1592 | /* We need to mark which channels really have RX and TX |
1593 | * queues, and adjust the TX queue numbers if we have separate | |
602a5322 BH |
1594 | * RX-only and TX-only channels. |
1595 | */ | |
1596 | efx_for_each_channel(channel, efx) { | |
79d68b37 SH |
1597 | if (channel->channel < efx->n_rx_channels) |
1598 | channel->rx_queue.core_index = channel->channel; | |
1599 | else | |
1600 | channel->rx_queue.core_index = -1; | |
1601 | ||
602a5322 BH |
1602 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1603 | tx_queue->queue -= (efx->tx_channel_offset * | |
1604 | EFX_TXQ_TYPES); | |
1605 | } | |
8ceee660 BH |
1606 | } |
1607 | ||
1608 | static int efx_probe_nic(struct efx_nic *efx) | |
1609 | { | |
765c9f46 | 1610 | size_t i; |
8ceee660 BH |
1611 | int rc; |
1612 | ||
62776d03 | 1613 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1614 | |
1615 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1616 | rc = efx->type->probe(efx); |
8ceee660 BH |
1617 | if (rc) |
1618 | return rc; | |
1619 | ||
a4900ac9 | 1620 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1621 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1622 | rc = efx_probe_interrupts(efx); |
1623 | if (rc) | |
c15eed22 | 1624 | goto fail1; |
8ceee660 | 1625 | |
52ad762b DP |
1626 | efx_set_channels(efx); |
1627 | ||
c15eed22 BH |
1628 | rc = efx->type->dimension_resources(efx); |
1629 | if (rc) | |
1630 | goto fail2; | |
28e47c49 | 1631 | |
5d3a6fca | 1632 | if (efx->n_channels > 1) |
7a20db37 | 1633 | netdev_rss_key_fill(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); |
765c9f46 | 1634 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 | 1635 | efx->rx_indir_table[i] = |
cd2d5b52 | 1636 | ethtool_rxfh_indir_default(i, efx->rss_spread); |
5d3a6fca | 1637 | |
c4f4adc7 BH |
1638 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1639 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1640 | |
1641 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1642 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1643 | true); | |
8ceee660 BH |
1644 | |
1645 | return 0; | |
64d8ad6d | 1646 | |
c15eed22 BH |
1647 | fail2: |
1648 | efx_remove_interrupts(efx); | |
1649 | fail1: | |
64d8ad6d BH |
1650 | efx->type->remove(efx); |
1651 | return rc; | |
8ceee660 BH |
1652 | } |
1653 | ||
1654 | static void efx_remove_nic(struct efx_nic *efx) | |
1655 | { | |
62776d03 | 1656 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1657 | |
1658 | efx_remove_interrupts(efx); | |
ef2b90ee | 1659 | efx->type->remove(efx); |
8ceee660 BH |
1660 | } |
1661 | ||
add72477 BH |
1662 | static int efx_probe_filters(struct efx_nic *efx) |
1663 | { | |
1664 | int rc; | |
1665 | ||
1666 | spin_lock_init(&efx->filter_lock); | |
1667 | ||
1668 | rc = efx->type->filter_table_probe(efx); | |
1669 | if (rc) | |
1670 | return rc; | |
1671 | ||
1672 | #ifdef CONFIG_RFS_ACCEL | |
1673 | if (efx->type->offload_features & NETIF_F_NTUPLE) { | |
1674 | efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters, | |
1675 | sizeof(*efx->rps_flow_id), | |
1676 | GFP_KERNEL); | |
1677 | if (!efx->rps_flow_id) { | |
1678 | efx->type->filter_table_remove(efx); | |
1679 | return -ENOMEM; | |
1680 | } | |
1681 | } | |
1682 | #endif | |
1683 | ||
1684 | return 0; | |
1685 | } | |
1686 | ||
1687 | static void efx_remove_filters(struct efx_nic *efx) | |
1688 | { | |
1689 | #ifdef CONFIG_RFS_ACCEL | |
1690 | kfree(efx->rps_flow_id); | |
1691 | #endif | |
1692 | efx->type->filter_table_remove(efx); | |
1693 | } | |
1694 | ||
1695 | static void efx_restore_filters(struct efx_nic *efx) | |
1696 | { | |
1697 | efx->type->filter_table_restore(efx); | |
1698 | } | |
1699 | ||
8ceee660 BH |
1700 | /************************************************************************** |
1701 | * | |
1702 | * NIC startup/shutdown | |
1703 | * | |
1704 | *************************************************************************/ | |
1705 | ||
1706 | static int efx_probe_all(struct efx_nic *efx) | |
1707 | { | |
8ceee660 BH |
1708 | int rc; |
1709 | ||
8ceee660 BH |
1710 | rc = efx_probe_nic(efx); |
1711 | if (rc) { | |
62776d03 | 1712 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1713 | goto fail1; |
1714 | } | |
1715 | ||
8ceee660 BH |
1716 | rc = efx_probe_port(efx); |
1717 | if (rc) { | |
62776d03 | 1718 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1719 | goto fail2; |
1720 | } | |
1721 | ||
7e6d06f0 BH |
1722 | BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); |
1723 | if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { | |
1724 | rc = -EINVAL; | |
1725 | goto fail3; | |
1726 | } | |
ecc910f5 | 1727 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1728 | |
6d8aaaf6 DP |
1729 | #ifdef CONFIG_SFC_SRIOV |
1730 | rc = efx->type->vswitching_probe(efx); | |
1731 | if (rc) /* not fatal; the PF will still work fine */ | |
1732 | netif_warn(efx, probe, efx->net_dev, | |
1733 | "failed to setup vswitching rc=%d;" | |
1734 | " VFs may not function\n", rc); | |
1735 | #endif | |
1736 | ||
64eebcfd BH |
1737 | rc = efx_probe_filters(efx); |
1738 | if (rc) { | |
1739 | netif_err(efx, probe, efx->net_dev, | |
1740 | "failed to create filter tables\n"); | |
6d8aaaf6 | 1741 | goto fail4; |
64eebcfd BH |
1742 | } |
1743 | ||
7f967c01 BH |
1744 | rc = efx_probe_channels(efx); |
1745 | if (rc) | |
6d8aaaf6 | 1746 | goto fail5; |
7f967c01 | 1747 | |
8ceee660 BH |
1748 | return 0; |
1749 | ||
6d8aaaf6 | 1750 | fail5: |
7f967c01 | 1751 | efx_remove_filters(efx); |
6d8aaaf6 DP |
1752 | fail4: |
1753 | #ifdef CONFIG_SFC_SRIOV | |
1754 | efx->type->vswitching_remove(efx); | |
1755 | #endif | |
8ceee660 | 1756 | fail3: |
8ceee660 BH |
1757 | efx_remove_port(efx); |
1758 | fail2: | |
1759 | efx_remove_nic(efx); | |
1760 | fail1: | |
1761 | return rc; | |
1762 | } | |
1763 | ||
8b7325b4 BH |
1764 | /* If the interface is supposed to be running but is not, start |
1765 | * the hardware and software data path, regular activity for the port | |
1766 | * (MAC statistics, link polling, etc.) and schedule the port to be | |
1767 | * reconfigured. Interrupts must already be enabled. This function | |
1768 | * is safe to call multiple times, so long as the NIC is not disabled. | |
1769 | * Requires the RTNL lock. | |
9f2cb71c | 1770 | */ |
8ceee660 BH |
1771 | static void efx_start_all(struct efx_nic *efx) |
1772 | { | |
8ceee660 | 1773 | EFX_ASSERT_RESET_SERIALISED(efx); |
8b7325b4 | 1774 | BUG_ON(efx->state == STATE_DISABLED); |
8ceee660 BH |
1775 | |
1776 | /* Check that it is appropriate to restart the interface. All | |
1777 | * of these flags are safe to read under just the rtnl lock */ | |
e283546c EC |
1778 | if (efx->port_enabled || !netif_running(efx->net_dev) || |
1779 | efx->reset_pending) | |
8ceee660 BH |
1780 | return; |
1781 | ||
8ceee660 | 1782 | efx_start_port(efx); |
9f2cb71c | 1783 | efx_start_datapath(efx); |
8880f4ec | 1784 | |
626950db AR |
1785 | /* Start the hardware monitor if there is one */ |
1786 | if (efx->type->monitor != NULL) | |
8ceee660 BH |
1787 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1788 | efx_monitor_interval); | |
626950db AR |
1789 | |
1790 | /* If link state detection is normally event-driven, we have | |
1791 | * to poll now because we could have missed a change | |
1792 | */ | |
1793 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { | |
78c1f0a0 SH |
1794 | mutex_lock(&efx->mac_lock); |
1795 | if (efx->phy_op->poll(efx)) | |
1796 | efx_link_status_changed(efx); | |
1797 | mutex_unlock(&efx->mac_lock); | |
1798 | } | |
55edc6e6 | 1799 | |
ef2b90ee | 1800 | efx->type->start_stats(efx); |
f8f3b5ae JC |
1801 | efx->type->pull_stats(efx); |
1802 | spin_lock_bh(&efx->stats_lock); | |
1803 | efx->type->update_stats(efx, NULL, NULL); | |
1804 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
1805 | } |
1806 | ||
8b7325b4 BH |
1807 | /* Quiesce the hardware and software data path, and regular activity |
1808 | * for the port without bringing the link down. Safe to call multiple | |
1809 | * times with the NIC in almost any state, but interrupts should be | |
1810 | * enabled. Requires the RTNL lock. | |
1811 | */ | |
8ceee660 BH |
1812 | static void efx_stop_all(struct efx_nic *efx) |
1813 | { | |
8ceee660 BH |
1814 | EFX_ASSERT_RESET_SERIALISED(efx); |
1815 | ||
1816 | /* port_enabled can be read safely under the rtnl lock */ | |
1817 | if (!efx->port_enabled) | |
1818 | return; | |
1819 | ||
f8f3b5ae JC |
1820 | /* update stats before we go down so we can accurately count |
1821 | * rx_nodesc_drops | |
1822 | */ | |
1823 | efx->type->pull_stats(efx); | |
1824 | spin_lock_bh(&efx->stats_lock); | |
1825 | efx->type->update_stats(efx, NULL, NULL); | |
1826 | spin_unlock_bh(&efx->stats_lock); | |
ef2b90ee | 1827 | efx->type->stop_stats(efx); |
8ceee660 BH |
1828 | efx_stop_port(efx); |
1829 | ||
29c69a48 BH |
1830 | /* Stop the kernel transmit interface. This is only valid if |
1831 | * the device is stopped or detached; otherwise the watchdog | |
1832 | * may fire immediately. | |
1833 | */ | |
1834 | WARN_ON(netif_running(efx->net_dev) && | |
1835 | netif_device_present(efx->net_dev)); | |
9f2cb71c BH |
1836 | netif_tx_disable(efx->net_dev); |
1837 | ||
1838 | efx_stop_datapath(efx); | |
8ceee660 BH |
1839 | } |
1840 | ||
1841 | static void efx_remove_all(struct efx_nic *efx) | |
1842 | { | |
4642610c | 1843 | efx_remove_channels(efx); |
7f967c01 | 1844 | efx_remove_filters(efx); |
6d8aaaf6 DP |
1845 | #ifdef CONFIG_SFC_SRIOV |
1846 | efx->type->vswitching_remove(efx); | |
1847 | #endif | |
8ceee660 BH |
1848 | efx_remove_port(efx); |
1849 | efx_remove_nic(efx); | |
1850 | } | |
1851 | ||
8ceee660 BH |
1852 | /************************************************************************** |
1853 | * | |
1854 | * Interrupt moderation | |
1855 | * | |
1856 | **************************************************************************/ | |
1857 | ||
cc180b69 | 1858 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1859 | { |
b548f976 BH |
1860 | if (usecs == 0) |
1861 | return 0; | |
cc180b69 | 1862 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1863 | return 1; /* never round down to 0 */ |
cc180b69 | 1864 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1865 | } |
1866 | ||
8ceee660 | 1867 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1868 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1869 | unsigned int rx_usecs, bool rx_adaptive, | |
1870 | bool rx_may_override_tx) | |
8ceee660 | 1871 | { |
f7d12cdc | 1872 | struct efx_channel *channel; |
cc180b69 BH |
1873 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1874 | efx->timer_quantum_ns, | |
1875 | 1000); | |
1876 | unsigned int tx_ticks; | |
1877 | unsigned int rx_ticks; | |
8ceee660 BH |
1878 | |
1879 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1880 | ||
cc180b69 | 1881 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1882 | return -EINVAL; |
1883 | ||
cc180b69 BH |
1884 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1885 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1886 | ||
9e393b30 BH |
1887 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1888 | !rx_may_override_tx) { | |
1889 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1890 | "RX and TX IRQ moderation must be equal\n"); | |
1891 | return -EINVAL; | |
1892 | } | |
1893 | ||
6fb70fd1 | 1894 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1895 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1896 | efx_for_each_channel(channel, efx) { |
525da907 | 1897 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1898 | channel->irq_moderation = rx_ticks; |
525da907 | 1899 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1900 | channel->irq_moderation = tx_ticks; |
1901 | } | |
9e393b30 BH |
1902 | |
1903 | return 0; | |
8ceee660 BH |
1904 | } |
1905 | ||
a0c4faf5 BH |
1906 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1907 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1908 | { | |
cc180b69 BH |
1909 | /* We must round up when converting ticks to microseconds |
1910 | * because we round down when converting the other way. | |
1911 | */ | |
1912 | ||
a0c4faf5 | 1913 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1914 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1915 | efx->timer_quantum_ns, | |
1916 | 1000); | |
a0c4faf5 BH |
1917 | |
1918 | /* If channels are shared between RX and TX, so is IRQ | |
1919 | * moderation. Otherwise, IRQ moderation is the same for all | |
1920 | * TX channels and is not adaptive. | |
1921 | */ | |
1922 | if (efx->tx_channel_offset == 0) | |
1923 | *tx_usecs = *rx_usecs; | |
1924 | else | |
cc180b69 | 1925 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1926 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1927 | efx->timer_quantum_ns, |
1928 | 1000); | |
a0c4faf5 BH |
1929 | } |
1930 | ||
8ceee660 BH |
1931 | /************************************************************************** |
1932 | * | |
1933 | * Hardware monitor | |
1934 | * | |
1935 | **************************************************************************/ | |
1936 | ||
e254c274 | 1937 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1938 | static void efx_monitor(struct work_struct *data) |
1939 | { | |
1940 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1941 | monitor_work.work); | |
8ceee660 | 1942 | |
62776d03 BH |
1943 | netif_vdbg(efx, timer, efx->net_dev, |
1944 | "hardware monitor executing on CPU %d\n", | |
1945 | raw_smp_processor_id()); | |
ef2b90ee | 1946 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1947 | |
8ceee660 BH |
1948 | /* If the mac_lock is already held then it is likely a port |
1949 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1950 | * most of the work of monitor() anyway. */ |
1951 | if (mutex_trylock(&efx->mac_lock)) { | |
1952 | if (efx->port_enabled) | |
1953 | efx->type->monitor(efx); | |
1954 | mutex_unlock(&efx->mac_lock); | |
1955 | } | |
8ceee660 | 1956 | |
8ceee660 BH |
1957 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1958 | efx_monitor_interval); | |
1959 | } | |
1960 | ||
1961 | /************************************************************************** | |
1962 | * | |
1963 | * ioctls | |
1964 | * | |
1965 | *************************************************************************/ | |
1966 | ||
1967 | /* Net device ioctl | |
1968 | * Context: process, rtnl_lock() held. | |
1969 | */ | |
1970 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1971 | { | |
767e468c | 1972 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1973 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 | 1974 | |
7c236c43 | 1975 | if (cmd == SIOCSHWTSTAMP) |
433dc9b3 BH |
1976 | return efx_ptp_set_ts_config(efx, ifr); |
1977 | if (cmd == SIOCGHWTSTAMP) | |
1978 | return efx_ptp_get_ts_config(efx, ifr); | |
7c236c43 | 1979 | |
68e7f45e BH |
1980 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1981 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1982 | (data->phy_id & 0xfc00) == 0x0400) | |
1983 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1984 | ||
1985 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1986 | } |
1987 | ||
1988 | /************************************************************************** | |
1989 | * | |
1990 | * NAPI interface | |
1991 | * | |
1992 | **************************************************************************/ | |
1993 | ||
7f967c01 BH |
1994 | static void efx_init_napi_channel(struct efx_channel *channel) |
1995 | { | |
1996 | struct efx_nic *efx = channel->efx; | |
1997 | ||
1998 | channel->napi_dev = efx->net_dev; | |
1999 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
2000 | efx_poll, napi_weight); | |
36763266 AR |
2001 | napi_hash_add(&channel->napi_str); |
2002 | efx_channel_init_lock(channel); | |
7f967c01 BH |
2003 | } |
2004 | ||
e8f14992 | 2005 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
2006 | { |
2007 | struct efx_channel *channel; | |
8ceee660 | 2008 | |
7f967c01 BH |
2009 | efx_for_each_channel(channel, efx) |
2010 | efx_init_napi_channel(channel); | |
e8f14992 BH |
2011 | } |
2012 | ||
2013 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
2014 | { | |
36763266 | 2015 | if (channel->napi_dev) { |
e8f14992 | 2016 | netif_napi_del(&channel->napi_str); |
36763266 AR |
2017 | napi_hash_del(&channel->napi_str); |
2018 | } | |
e8f14992 | 2019 | channel->napi_dev = NULL; |
8ceee660 BH |
2020 | } |
2021 | ||
2022 | static void efx_fini_napi(struct efx_nic *efx) | |
2023 | { | |
2024 | struct efx_channel *channel; | |
2025 | ||
e8f14992 BH |
2026 | efx_for_each_channel(channel, efx) |
2027 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
2028 | } |
2029 | ||
2030 | /************************************************************************** | |
2031 | * | |
2032 | * Kernel netpoll interface | |
2033 | * | |
2034 | *************************************************************************/ | |
2035 | ||
2036 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2037 | ||
2038 | /* Although in the common case interrupts will be disabled, this is not | |
2039 | * guaranteed. However, all our work happens inside the NAPI callback, | |
2040 | * so no locking is required. | |
2041 | */ | |
2042 | static void efx_netpoll(struct net_device *net_dev) | |
2043 | { | |
767e468c | 2044 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
2045 | struct efx_channel *channel; |
2046 | ||
64ee3120 | 2047 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
2048 | efx_schedule_channel(channel); |
2049 | } | |
2050 | ||
2051 | #endif | |
2052 | ||
36763266 AR |
2053 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2054 | static int efx_busy_poll(struct napi_struct *napi) | |
2055 | { | |
2056 | struct efx_channel *channel = | |
2057 | container_of(napi, struct efx_channel, napi_str); | |
2058 | struct efx_nic *efx = channel->efx; | |
2059 | int budget = 4; | |
2060 | int old_rx_packets, rx_packets; | |
2061 | ||
2062 | if (!netif_running(efx->net_dev)) | |
2063 | return LL_FLUSH_FAILED; | |
2064 | ||
2065 | if (!efx_channel_lock_poll(channel)) | |
2066 | return LL_FLUSH_BUSY; | |
2067 | ||
2068 | old_rx_packets = channel->rx_queue.rx_packets; | |
2069 | efx_process_channel(channel, budget); | |
2070 | ||
2071 | rx_packets = channel->rx_queue.rx_packets - old_rx_packets; | |
2072 | ||
2073 | /* There is no race condition with NAPI here. | |
2074 | * NAPI will automatically be rescheduled if it yielded during busy | |
2075 | * polling, because it was not able to take the lock and thus returned | |
2076 | * the full budget. | |
2077 | */ | |
2078 | efx_channel_unlock_poll(channel); | |
2079 | ||
2080 | return rx_packets; | |
2081 | } | |
2082 | #endif | |
2083 | ||
8ceee660 BH |
2084 | /************************************************************************** |
2085 | * | |
2086 | * Kernel net device interface | |
2087 | * | |
2088 | *************************************************************************/ | |
2089 | ||
2090 | /* Context: process, rtnl_lock() held. */ | |
2091 | static int efx_net_open(struct net_device *net_dev) | |
2092 | { | |
767e468c | 2093 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 BH |
2094 | int rc; |
2095 | ||
62776d03 BH |
2096 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
2097 | raw_smp_processor_id()); | |
8ceee660 | 2098 | |
8b7325b4 BH |
2099 | rc = efx_check_disabled(efx); |
2100 | if (rc) | |
2101 | return rc; | |
f8b87c17 BH |
2102 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
2103 | return -EBUSY; | |
8880f4ec BH |
2104 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
2105 | return -EIO; | |
f8b87c17 | 2106 | |
78c1f0a0 SH |
2107 | /* Notify the kernel of the link state polled during driver load, |
2108 | * before the monitor starts running */ | |
2109 | efx_link_status_changed(efx); | |
2110 | ||
8ceee660 | 2111 | efx_start_all(efx); |
dd40781e | 2112 | efx_selftest_async_start(efx); |
8ceee660 BH |
2113 | return 0; |
2114 | } | |
2115 | ||
2116 | /* Context: process, rtnl_lock() held. | |
2117 | * Note that the kernel will ignore our return code; this method | |
2118 | * should really be a void. | |
2119 | */ | |
2120 | static int efx_net_stop(struct net_device *net_dev) | |
2121 | { | |
767e468c | 2122 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2123 | |
62776d03 BH |
2124 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
2125 | raw_smp_processor_id()); | |
8ceee660 | 2126 | |
8b7325b4 BH |
2127 | /* Stop the device and flush all the channels */ |
2128 | efx_stop_all(efx); | |
8ceee660 BH |
2129 | |
2130 | return 0; | |
2131 | } | |
2132 | ||
5b9e207c | 2133 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
2134 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
2135 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 2136 | { |
767e468c | 2137 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2138 | |
55edc6e6 | 2139 | spin_lock_bh(&efx->stats_lock); |
cd0ecc9a | 2140 | efx->type->update_stats(efx, NULL, stats); |
1cb34522 BH |
2141 | spin_unlock_bh(&efx->stats_lock); |
2142 | ||
8ceee660 BH |
2143 | return stats; |
2144 | } | |
2145 | ||
2146 | /* Context: netif_tx_lock held, BHs disabled. */ | |
2147 | static void efx_watchdog(struct net_device *net_dev) | |
2148 | { | |
767e468c | 2149 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2150 | |
62776d03 BH |
2151 | netif_err(efx, tx_err, efx->net_dev, |
2152 | "TX stuck with port_enabled=%d: resetting channels\n", | |
2153 | efx->port_enabled); | |
8ceee660 | 2154 | |
739bb23d | 2155 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
2156 | } |
2157 | ||
2158 | ||
2159 | /* Context: process, rtnl_lock() held. */ | |
2160 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
2161 | { | |
767e468c | 2162 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 | 2163 | int rc; |
8ceee660 | 2164 | |
8b7325b4 BH |
2165 | rc = efx_check_disabled(efx); |
2166 | if (rc) | |
2167 | return rc; | |
8ceee660 BH |
2168 | if (new_mtu > EFX_MAX_MTU) |
2169 | return -EINVAL; | |
2170 | ||
62776d03 | 2171 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 2172 | |
29c69a48 BH |
2173 | efx_device_detach_sync(efx); |
2174 | efx_stop_all(efx); | |
2175 | ||
d3245b28 | 2176 | mutex_lock(&efx->mac_lock); |
8ceee660 | 2177 | net_dev->mtu = new_mtu; |
710b208d | 2178 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
2179 | mutex_unlock(&efx->mac_lock); |
2180 | ||
8ceee660 | 2181 | efx_start_all(efx); |
29c69a48 | 2182 | netif_device_attach(efx->net_dev); |
6c8eef4a | 2183 | return 0; |
8ceee660 BH |
2184 | } |
2185 | ||
2186 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
2187 | { | |
767e468c | 2188 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2189 | struct sockaddr *addr = data; |
e0b3ae30 | 2190 | u8 *new_addr = addr->sa_data; |
8ceee660 | 2191 | |
8ceee660 | 2192 | if (!is_valid_ether_addr(new_addr)) { |
62776d03 BH |
2193 | netif_err(efx, drv, efx->net_dev, |
2194 | "invalid ethernet MAC address requested: %pM\n", | |
2195 | new_addr); | |
504f9b5a | 2196 | return -EADDRNOTAVAIL; |
8ceee660 BH |
2197 | } |
2198 | ||
cd84ff4d | 2199 | ether_addr_copy(net_dev->dev_addr, new_addr); |
7fa8d547 SS |
2200 | if (efx->type->sriov_mac_address_changed) |
2201 | efx->type->sriov_mac_address_changed(efx); | |
8ceee660 BH |
2202 | |
2203 | /* Reconfigure the MAC */ | |
d3245b28 | 2204 | mutex_lock(&efx->mac_lock); |
710b208d | 2205 | efx->type->reconfigure_mac(efx); |
d3245b28 | 2206 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
2207 | |
2208 | return 0; | |
2209 | } | |
2210 | ||
a816f75a | 2211 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 2212 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 2213 | { |
767e468c | 2214 | struct efx_nic *efx = netdev_priv(net_dev); |
a816f75a | 2215 | |
8be4f3e6 BH |
2216 | if (efx->port_enabled) |
2217 | queue_work(efx->workqueue, &efx->mac_work); | |
2218 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
2219 | } |
2220 | ||
c8f44aff | 2221 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
2222 | { |
2223 | struct efx_nic *efx = netdev_priv(net_dev); | |
2224 | ||
2225 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
2226 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
fbd79120 | 2227 | return efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); |
abfe9039 BH |
2228 | |
2229 | return 0; | |
2230 | } | |
2231 | ||
7fa8d547 | 2232 | static const struct net_device_ops efx_netdev_ops = { |
c3ecb9f3 SH |
2233 | .ndo_open = efx_net_open, |
2234 | .ndo_stop = efx_net_stop, | |
4472702e | 2235 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
2236 | .ndo_tx_timeout = efx_watchdog, |
2237 | .ndo_start_xmit = efx_hard_start_xmit, | |
2238 | .ndo_validate_addr = eth_validate_addr, | |
2239 | .ndo_do_ioctl = efx_ioctl, | |
2240 | .ndo_change_mtu = efx_change_mtu, | |
2241 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2242 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2243 | .ndo_set_features = efx_set_features, |
cd2d5b52 | 2244 | #ifdef CONFIG_SFC_SRIOV |
7fa8d547 SS |
2245 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, |
2246 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2247 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2248 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
cd2d5b52 | 2249 | #endif |
c3ecb9f3 SH |
2250 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2251 | .ndo_poll_controller = efx_netpoll, | |
2252 | #endif | |
94b274bf | 2253 | .ndo_setup_tc = efx_setup_tc, |
36763266 AR |
2254 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2255 | .ndo_busy_poll = efx_busy_poll, | |
2256 | #endif | |
64d8ad6d BH |
2257 | #ifdef CONFIG_RFS_ACCEL |
2258 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2259 | #endif | |
c3ecb9f3 SH |
2260 | }; |
2261 | ||
7dde596e BH |
2262 | static void efx_update_name(struct efx_nic *efx) |
2263 | { | |
2264 | strcpy(efx->name, efx->net_dev->name); | |
2265 | efx_mtd_rename(efx); | |
2266 | efx_set_channel_names(efx); | |
2267 | } | |
2268 | ||
8ceee660 BH |
2269 | static int efx_netdev_event(struct notifier_block *this, |
2270 | unsigned long event, void *ptr) | |
2271 | { | |
351638e7 | 2272 | struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); |
8ceee660 | 2273 | |
7fa8d547 | 2274 | if ((net_dev->netdev_ops == &efx_netdev_ops) && |
7dde596e BH |
2275 | event == NETDEV_CHANGENAME) |
2276 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2277 | |
2278 | return NOTIFY_DONE; | |
2279 | } | |
2280 | ||
2281 | static struct notifier_block efx_netdev_notifier = { | |
2282 | .notifier_call = efx_netdev_event, | |
2283 | }; | |
2284 | ||
06d5e193 BH |
2285 | static ssize_t |
2286 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2287 | { | |
2288 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2289 | return sprintf(buf, "%d\n", efx->phy_type); | |
2290 | } | |
776fbcc9 | 2291 | static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); |
06d5e193 | 2292 | |
8ceee660 BH |
2293 | static int efx_register_netdev(struct efx_nic *efx) |
2294 | { | |
2295 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2296 | struct efx_channel *channel; |
8ceee660 BH |
2297 | int rc; |
2298 | ||
2299 | net_dev->watchdog_timeo = 5 * HZ; | |
2300 | net_dev->irq = efx->pci_dev->irq; | |
7fa8d547 SS |
2301 | net_dev->netdev_ops = &efx_netdev_ops; |
2302 | if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) | |
8127d661 | 2303 | net_dev->priv_flags |= IFF_UNICAST_FLT; |
7ad24ea4 | 2304 | net_dev->ethtool_ops = &efx_ethtool_ops; |
7e6d06f0 | 2305 | net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; |
8ceee660 | 2306 | |
7dde596e | 2307 | rtnl_lock(); |
aed0628d | 2308 | |
7153f623 BH |
2309 | /* Enable resets to be scheduled and check whether any were |
2310 | * already requested. If so, the NIC is probably hosed so we | |
2311 | * abort. | |
2312 | */ | |
2313 | efx->state = STATE_READY; | |
2314 | smp_mb(); /* ensure we change state before checking reset_pending */ | |
2315 | if (efx->reset_pending) { | |
2316 | netif_err(efx, probe, efx->net_dev, | |
2317 | "aborting probe due to scheduled reset\n"); | |
2318 | rc = -EIO; | |
2319 | goto fail_locked; | |
2320 | } | |
2321 | ||
aed0628d BH |
2322 | rc = dev_alloc_name(net_dev, net_dev->name); |
2323 | if (rc < 0) | |
2324 | goto fail_locked; | |
7dde596e | 2325 | efx_update_name(efx); |
aed0628d | 2326 | |
8f8b3d51 BH |
2327 | /* Always start with carrier off; PHY events will detect the link */ |
2328 | netif_carrier_off(net_dev); | |
2329 | ||
aed0628d BH |
2330 | rc = register_netdevice(net_dev); |
2331 | if (rc) | |
2332 | goto fail_locked; | |
2333 | ||
c04bfc6b BH |
2334 | efx_for_each_channel(channel, efx) { |
2335 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2336 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2337 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2338 | } |
2339 | ||
0bcf4a64 BH |
2340 | efx_associate(efx); |
2341 | ||
7dde596e | 2342 | rtnl_unlock(); |
8ceee660 | 2343 | |
06d5e193 BH |
2344 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2345 | if (rc) { | |
62776d03 BH |
2346 | netif_err(efx, drv, efx->net_dev, |
2347 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2348 | goto fail_registered; |
2349 | } | |
2350 | ||
8ceee660 | 2351 | return 0; |
06d5e193 | 2352 | |
7153f623 BH |
2353 | fail_registered: |
2354 | rtnl_lock(); | |
0bcf4a64 | 2355 | efx_dissociate(efx); |
7153f623 | 2356 | unregister_netdevice(net_dev); |
aed0628d | 2357 | fail_locked: |
7153f623 | 2358 | efx->state = STATE_UNINIT; |
aed0628d | 2359 | rtnl_unlock(); |
62776d03 | 2360 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d | 2361 | return rc; |
8ceee660 BH |
2362 | } |
2363 | ||
2364 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2365 | { | |
8ceee660 BH |
2366 | if (!efx->net_dev) |
2367 | return; | |
2368 | ||
767e468c | 2369 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 | 2370 | |
73ba7b68 BH |
2371 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
2372 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
7153f623 BH |
2373 | |
2374 | rtnl_lock(); | |
2375 | unregister_netdevice(efx->net_dev); | |
2376 | efx->state = STATE_UNINIT; | |
2377 | rtnl_unlock(); | |
8ceee660 BH |
2378 | } |
2379 | ||
2380 | /************************************************************************** | |
2381 | * | |
2382 | * Device reset and suspend | |
2383 | * | |
2384 | **************************************************************************/ | |
2385 | ||
2467ca46 BH |
2386 | /* Tears down the entire software state and most of the hardware state |
2387 | * before reset. */ | |
d3245b28 | 2388 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2389 | { |
8ceee660 BH |
2390 | EFX_ASSERT_RESET_SERIALISED(efx); |
2391 | ||
e283546c EC |
2392 | if (method == RESET_TYPE_MCDI_TIMEOUT) |
2393 | efx->type->prepare_flr(efx); | |
2394 | ||
2467ca46 | 2395 | efx_stop_all(efx); |
d8291187 | 2396 | efx_disable_interrupts(efx); |
5642ceef BH |
2397 | |
2398 | mutex_lock(&efx->mac_lock); | |
4b988280 SH |
2399 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2400 | efx->phy_op->fini(efx); | |
ef2b90ee | 2401 | efx->type->fini(efx); |
8ceee660 BH |
2402 | } |
2403 | ||
2467ca46 BH |
2404 | /* This function will always ensure that the locks acquired in |
2405 | * efx_reset_down() are released. A failure return code indicates | |
2406 | * that we were unable to reinitialise the hardware, and the | |
2407 | * driver should be disabled. If ok is false, then the rx and tx | |
2408 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2409 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2410 | { |
2411 | int rc; | |
2412 | ||
2467ca46 | 2413 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2414 | |
e283546c EC |
2415 | if (method == RESET_TYPE_MCDI_TIMEOUT) |
2416 | efx->type->finish_flr(efx); | |
2417 | ||
2418 | /* Ensure that SRAM is initialised even if we're disabling the device */ | |
ef2b90ee | 2419 | rc = efx->type->init(efx); |
8ceee660 | 2420 | if (rc) { |
62776d03 | 2421 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2422 | goto fail; |
8ceee660 BH |
2423 | } |
2424 | ||
eb9f6744 BH |
2425 | if (!ok) |
2426 | goto fail; | |
2427 | ||
4b988280 | 2428 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2429 | rc = efx->phy_op->init(efx); |
2430 | if (rc) | |
2431 | goto fail; | |
267d9d73 EC |
2432 | rc = efx->phy_op->reconfigure(efx); |
2433 | if (rc && rc != -EPERM) | |
62776d03 BH |
2434 | netif_err(efx, drv, efx->net_dev, |
2435 | "could not restore PHY settings\n"); | |
4b988280 SH |
2436 | } |
2437 | ||
261e4d96 JC |
2438 | rc = efx_enable_interrupts(efx); |
2439 | if (rc) | |
2440 | goto fail; | |
6d8aaaf6 DP |
2441 | |
2442 | #ifdef CONFIG_SFC_SRIOV | |
2443 | rc = efx->type->vswitching_restore(efx); | |
2444 | if (rc) /* not fatal; the PF will still work fine */ | |
2445 | netif_warn(efx, probe, efx->net_dev, | |
2446 | "failed to restore vswitching rc=%d;" | |
2447 | " VFs may not function\n", rc); | |
2448 | #endif | |
2449 | ||
64eebcfd | 2450 | efx_restore_filters(efx); |
7fa8d547 SS |
2451 | if (efx->type->sriov_reset) |
2452 | efx->type->sriov_reset(efx); | |
eb9f6744 | 2453 | |
eb9f6744 BH |
2454 | mutex_unlock(&efx->mac_lock); |
2455 | ||
2456 | efx_start_all(efx); | |
2457 | ||
2458 | return 0; | |
2459 | ||
2460 | fail: | |
2461 | efx->port_initialized = false; | |
2467ca46 BH |
2462 | |
2463 | mutex_unlock(&efx->mac_lock); | |
2464 | ||
8ceee660 BH |
2465 | return rc; |
2466 | } | |
2467 | ||
eb9f6744 BH |
2468 | /* Reset the NIC using the specified method. Note that the reset may |
2469 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2470 | * |
eb9f6744 | 2471 | * Caller must hold the rtnl_lock. |
8ceee660 | 2472 | */ |
eb9f6744 | 2473 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2474 | { |
eb9f6744 BH |
2475 | int rc, rc2; |
2476 | bool disabled; | |
8ceee660 | 2477 | |
62776d03 BH |
2478 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2479 | RESET_TYPE(method)); | |
8ceee660 | 2480 | |
c2f3b8e3 | 2481 | efx_device_detach_sync(efx); |
d3245b28 | 2482 | efx_reset_down(efx, method); |
8ceee660 | 2483 | |
ef2b90ee | 2484 | rc = efx->type->reset(efx, method); |
8ceee660 | 2485 | if (rc) { |
62776d03 | 2486 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2487 | goto out; |
8ceee660 BH |
2488 | } |
2489 | ||
a7d529ae BH |
2490 | /* Clear flags for the scopes we covered. We assume the NIC and |
2491 | * driver are now quiescent so that there is no race here. | |
2492 | */ | |
e283546c EC |
2493 | if (method < RESET_TYPE_MAX_METHOD) |
2494 | efx->reset_pending &= -(1 << (method + 1)); | |
2495 | else /* it doesn't fit into the well-ordered scope hierarchy */ | |
2496 | __clear_bit(method, &efx->reset_pending); | |
8ceee660 BH |
2497 | |
2498 | /* Reinitialise bus-mastering, which may have been turned off before | |
2499 | * the reset was scheduled. This is still appropriate, even in the | |
2500 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2501 | * can respond to requests. */ | |
2502 | pci_set_master(efx->pci_dev); | |
2503 | ||
eb9f6744 | 2504 | out: |
8ceee660 | 2505 | /* Leave device stopped if necessary */ |
626950db AR |
2506 | disabled = rc || |
2507 | method == RESET_TYPE_DISABLE || | |
2508 | method == RESET_TYPE_RECOVER_OR_DISABLE; | |
eb9f6744 BH |
2509 | rc2 = efx_reset_up(efx, method, !disabled); |
2510 | if (rc2) { | |
2511 | disabled = true; | |
2512 | if (!rc) | |
2513 | rc = rc2; | |
8ceee660 BH |
2514 | } |
2515 | ||
eb9f6744 | 2516 | if (disabled) { |
f49a4589 | 2517 | dev_close(efx->net_dev); |
62776d03 | 2518 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2519 | efx->state = STATE_DISABLED; |
f4bd954e | 2520 | } else { |
62776d03 | 2521 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2522 | netif_device_attach(efx->net_dev); |
f4bd954e | 2523 | } |
8ceee660 BH |
2524 | return rc; |
2525 | } | |
2526 | ||
626950db AR |
2527 | /* Try recovery mechanisms. |
2528 | * For now only EEH is supported. | |
2529 | * Returns 0 if the recovery mechanisms are unsuccessful. | |
2530 | * Returns a non-zero value otherwise. | |
2531 | */ | |
b28405b0 | 2532 | int efx_try_recovery(struct efx_nic *efx) |
626950db AR |
2533 | { |
2534 | #ifdef CONFIG_EEH | |
2535 | /* A PCI error can occur and not be seen by EEH because nothing | |
2536 | * happens on the PCI bus. In this case the driver may fail and | |
2537 | * schedule a 'recover or reset', leading to this recovery handler. | |
2538 | * Manually call the eeh failure check function. | |
2539 | */ | |
12a89dba | 2540 | struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev); |
626950db AR |
2541 | if (eeh_dev_check_failure(eehdev)) { |
2542 | /* The EEH mechanisms will handle the error and reset the | |
2543 | * device if necessary. | |
2544 | */ | |
2545 | return 1; | |
2546 | } | |
2547 | #endif | |
2548 | return 0; | |
2549 | } | |
2550 | ||
74cd60a4 JC |
2551 | static void efx_wait_for_bist_end(struct efx_nic *efx) |
2552 | { | |
2553 | int i; | |
2554 | ||
2555 | for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) { | |
2556 | if (efx_mcdi_poll_reboot(efx)) | |
2557 | goto out; | |
2558 | msleep(BIST_WAIT_DELAY_MS); | |
2559 | } | |
2560 | ||
2561 | netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n"); | |
2562 | out: | |
2563 | /* Either way unset the BIST flag. If we found no reboot we probably | |
2564 | * won't recover, but we should try. | |
2565 | */ | |
2566 | efx->mc_bist_for_other_fn = false; | |
2567 | } | |
2568 | ||
8ceee660 BH |
2569 | /* The worker thread exists so that code that cannot sleep can |
2570 | * schedule a reset for later. | |
2571 | */ | |
2572 | static void efx_reset_work(struct work_struct *data) | |
2573 | { | |
eb9f6744 | 2574 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
626950db AR |
2575 | unsigned long pending; |
2576 | enum reset_type method; | |
2577 | ||
2578 | pending = ACCESS_ONCE(efx->reset_pending); | |
2579 | method = fls(pending) - 1; | |
2580 | ||
74cd60a4 JC |
2581 | if (method == RESET_TYPE_MC_BIST) |
2582 | efx_wait_for_bist_end(efx); | |
2583 | ||
626950db AR |
2584 | if ((method == RESET_TYPE_RECOVER_OR_DISABLE || |
2585 | method == RESET_TYPE_RECOVER_OR_ALL) && | |
2586 | efx_try_recovery(efx)) | |
2587 | return; | |
8ceee660 | 2588 | |
a7d529ae | 2589 | if (!pending) |
319ba649 SH |
2590 | return; |
2591 | ||
eb9f6744 | 2592 | rtnl_lock(); |
7153f623 BH |
2593 | |
2594 | /* We checked the state in efx_schedule_reset() but it may | |
2595 | * have changed by now. Now that we have the RTNL lock, | |
2596 | * it cannot change again. | |
2597 | */ | |
2598 | if (efx->state == STATE_READY) | |
626950db | 2599 | (void)efx_reset(efx, method); |
7153f623 | 2600 | |
eb9f6744 | 2601 | rtnl_unlock(); |
8ceee660 BH |
2602 | } |
2603 | ||
2604 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2605 | { | |
2606 | enum reset_type method; | |
2607 | ||
626950db AR |
2608 | if (efx->state == STATE_RECOVERY) { |
2609 | netif_dbg(efx, drv, efx->net_dev, | |
2610 | "recovering: skip scheduling %s reset\n", | |
2611 | RESET_TYPE(type)); | |
2612 | return; | |
2613 | } | |
2614 | ||
8ceee660 BH |
2615 | switch (type) { |
2616 | case RESET_TYPE_INVISIBLE: | |
2617 | case RESET_TYPE_ALL: | |
626950db | 2618 | case RESET_TYPE_RECOVER_OR_ALL: |
8ceee660 BH |
2619 | case RESET_TYPE_WORLD: |
2620 | case RESET_TYPE_DISABLE: | |
626950db | 2621 | case RESET_TYPE_RECOVER_OR_DISABLE: |
74cd60a4 | 2622 | case RESET_TYPE_MC_BIST: |
e283546c | 2623 | case RESET_TYPE_MCDI_TIMEOUT: |
8ceee660 | 2624 | method = type; |
0e2a9c7c BH |
2625 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2626 | RESET_TYPE(method)); | |
8ceee660 | 2627 | break; |
8ceee660 | 2628 | default: |
0e2a9c7c | 2629 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2630 | netif_dbg(efx, drv, efx->net_dev, |
2631 | "scheduling %s reset for %s\n", | |
2632 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2633 | break; |
2634 | } | |
8ceee660 | 2635 | |
a7d529ae | 2636 | set_bit(method, &efx->reset_pending); |
7153f623 BH |
2637 | smp_mb(); /* ensure we change reset_pending before checking state */ |
2638 | ||
2639 | /* If we're not READY then just leave the flags set as the cue | |
2640 | * to abort probing or reschedule the reset later. | |
2641 | */ | |
2642 | if (ACCESS_ONCE(efx->state) != STATE_READY) | |
2643 | return; | |
8ceee660 | 2644 | |
8880f4ec BH |
2645 | /* efx_process_channel() will no longer read events once a |
2646 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2647 | efx_mcdi_mode_poll(efx); | |
2648 | ||
1ab00629 | 2649 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2650 | } |
2651 | ||
2652 | /************************************************************************** | |
2653 | * | |
2654 | * List of NICs we support | |
2655 | * | |
2656 | **************************************************************************/ | |
2657 | ||
2658 | /* PCI device ID table */ | |
9baa3c34 | 2659 | static const struct pci_device_id efx_pci_table[] = { |
937383a5 BH |
2660 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2661 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2662 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2663 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2664 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2665 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2666 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2667 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2668 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2669 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8127d661 BH |
2670 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */ |
2671 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
3b06a00e MW |
2672 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0923), /* SFC9140 PF */ |
2673 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
8ceee660 BH |
2674 | {0} /* end of list */ |
2675 | }; | |
2676 | ||
2677 | /************************************************************************** | |
2678 | * | |
3759433d | 2679 | * Dummy PHY/MAC operations |
8ceee660 | 2680 | * |
01aad7b6 | 2681 | * Can be used for some unimplemented operations |
8ceee660 BH |
2682 | * Needed so all function pointers are valid and do not have to be tested |
2683 | * before use | |
2684 | * | |
2685 | **************************************************************************/ | |
2686 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2687 | { | |
2688 | return 0; | |
2689 | } | |
2690 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2691 | |
2692 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2693 | { |
2694 | return false; | |
2695 | } | |
8ceee660 | 2696 | |
6c8c2513 | 2697 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2698 | .init = efx_port_dummy_op_int, |
d3245b28 | 2699 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2700 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2701 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2702 | }; |
2703 | ||
8ceee660 BH |
2704 | /************************************************************************** |
2705 | * | |
2706 | * Data housekeeping | |
2707 | * | |
2708 | **************************************************************************/ | |
2709 | ||
2710 | /* This zeroes out and then fills in the invariants in a struct | |
2711 | * efx_nic (including all sub-structures). | |
2712 | */ | |
adeb15aa | 2713 | static int efx_init_struct(struct efx_nic *efx, |
8ceee660 BH |
2714 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2715 | { | |
4642610c | 2716 | int i; |
8ceee660 BH |
2717 | |
2718 | /* Initialise common structures */ | |
0bcf4a64 BH |
2719 | INIT_LIST_HEAD(&efx->node); |
2720 | INIT_LIST_HEAD(&efx->secondary_list); | |
8ceee660 | 2721 | spin_lock_init(&efx->biu_lock); |
76884835 BH |
2722 | #ifdef CONFIG_SFC_MTD |
2723 | INIT_LIST_HEAD(&efx->mtd_list); | |
2724 | #endif | |
8ceee660 BH |
2725 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2726 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
dd40781e | 2727 | INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); |
8ceee660 | 2728 | efx->pci_dev = pci_dev; |
62776d03 | 2729 | efx->msg_enable = debug; |
f16aeea0 | 2730 | efx->state = STATE_UNINIT; |
8ceee660 | 2731 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2732 | |
2733 | efx->net_dev = net_dev; | |
43a3739d | 2734 | efx->rx_prefix_size = efx->type->rx_prefix_size; |
2ec03014 AR |
2735 | efx->rx_ip_align = |
2736 | NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0; | |
43a3739d JC |
2737 | efx->rx_packet_hash_offset = |
2738 | efx->type->rx_hash_offset - efx->type->rx_prefix_size; | |
bd9a265d JC |
2739 | efx->rx_packet_ts_offset = |
2740 | efx->type->rx_ts_offset - efx->type->rx_prefix_size; | |
8ceee660 BH |
2741 | spin_lock_init(&efx->stats_lock); |
2742 | mutex_init(&efx->mac_lock); | |
2743 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2744 | efx->mdio.dev = net_dev; |
766ca0fa | 2745 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2746 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2747 | |
2748 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2749 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2750 | if (!efx->channel[i]) | |
2751 | goto fail; | |
d8291187 BH |
2752 | efx->msi_context[i].efx = efx; |
2753 | efx->msi_context[i].index = i; | |
8ceee660 BH |
2754 | } |
2755 | ||
8ceee660 BH |
2756 | /* Higher numbered interrupt modes are less capable! */ |
2757 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2758 | interrupt_mode); | |
2759 | ||
6977dc63 BH |
2760 | /* Would be good to use the net_dev name, but we're too early */ |
2761 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2762 | pci_name(pci_dev)); | |
2763 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2764 | if (!efx->workqueue) |
4642610c | 2765 | goto fail; |
8d9853d9 | 2766 | |
8ceee660 | 2767 | return 0; |
4642610c BH |
2768 | |
2769 | fail: | |
2770 | efx_fini_struct(efx); | |
2771 | return -ENOMEM; | |
8ceee660 BH |
2772 | } |
2773 | ||
2774 | static void efx_fini_struct(struct efx_nic *efx) | |
2775 | { | |
8313aca3 BH |
2776 | int i; |
2777 | ||
2778 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2779 | kfree(efx->channel[i]); | |
2780 | ||
ef215e64 BH |
2781 | kfree(efx->vpd_sn); |
2782 | ||
8ceee660 BH |
2783 | if (efx->workqueue) { |
2784 | destroy_workqueue(efx->workqueue); | |
2785 | efx->workqueue = NULL; | |
2786 | } | |
2787 | } | |
2788 | ||
e4d112e4 EC |
2789 | void efx_update_sw_stats(struct efx_nic *efx, u64 *stats) |
2790 | { | |
2791 | u64 n_rx_nodesc_trunc = 0; | |
2792 | struct efx_channel *channel; | |
2793 | ||
2794 | efx_for_each_channel(channel, efx) | |
2795 | n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc; | |
2796 | stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc; | |
2797 | stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops); | |
2798 | } | |
2799 | ||
8ceee660 BH |
2800 | /************************************************************************** |
2801 | * | |
2802 | * PCI interface | |
2803 | * | |
2804 | **************************************************************************/ | |
2805 | ||
2806 | /* Main body of final NIC shutdown code | |
2807 | * This is called only at module unload (or hotplug removal). | |
2808 | */ | |
2809 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2810 | { | |
7153f623 BH |
2811 | /* Flush reset_work. It can no longer be scheduled since we |
2812 | * are not READY. | |
2813 | */ | |
2814 | BUG_ON(efx->state == STATE_READY); | |
2815 | cancel_work_sync(&efx->reset_work); | |
2816 | ||
d8291187 | 2817 | efx_disable_interrupts(efx); |
152b6a62 | 2818 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2819 | efx_fini_port(efx); |
ef2b90ee | 2820 | efx->type->fini(efx); |
8ceee660 BH |
2821 | efx_fini_napi(efx); |
2822 | efx_remove_all(efx); | |
2823 | } | |
2824 | ||
2825 | /* Final NIC shutdown | |
2826 | * This is called only at module unload (or hotplug removal). | |
2827 | */ | |
2828 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2829 | { | |
2830 | struct efx_nic *efx; | |
2831 | ||
2832 | efx = pci_get_drvdata(pci_dev); | |
2833 | if (!efx) | |
2834 | return; | |
2835 | ||
2836 | /* Mark the NIC as fini, then stop the interface */ | |
2837 | rtnl_lock(); | |
0bcf4a64 | 2838 | efx_dissociate(efx); |
8ceee660 | 2839 | dev_close(efx->net_dev); |
d8291187 | 2840 | efx_disable_interrupts(efx); |
8ceee660 BH |
2841 | rtnl_unlock(); |
2842 | ||
7fa8d547 SS |
2843 | if (efx->type->sriov_fini) |
2844 | efx->type->sriov_fini(efx); | |
2845 | ||
8ceee660 BH |
2846 | efx_unregister_netdev(efx); |
2847 | ||
7dde596e BH |
2848 | efx_mtd_remove(efx); |
2849 | ||
8ceee660 BH |
2850 | efx_pci_remove_main(efx); |
2851 | ||
8ceee660 | 2852 | efx_fini_io(efx); |
62776d03 | 2853 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 | 2854 | |
8ceee660 BH |
2855 | efx_fini_struct(efx); |
2856 | free_netdev(efx->net_dev); | |
626950db AR |
2857 | |
2858 | pci_disable_pcie_error_reporting(pci_dev); | |
8ceee660 BH |
2859 | }; |
2860 | ||
460eeaa0 BH |
2861 | /* NIC VPD information |
2862 | * Called during probe to display the part number of the | |
2863 | * installed NIC. VPD is potentially very large but this should | |
2864 | * always appear within the first 512 bytes. | |
2865 | */ | |
2866 | #define SFC_VPD_LEN 512 | |
ef215e64 | 2867 | static void efx_probe_vpd_strings(struct efx_nic *efx) |
460eeaa0 BH |
2868 | { |
2869 | struct pci_dev *dev = efx->pci_dev; | |
2870 | char vpd_data[SFC_VPD_LEN]; | |
2871 | ssize_t vpd_size; | |
ef215e64 | 2872 | int ro_start, ro_size, i, j; |
460eeaa0 BH |
2873 | |
2874 | /* Get the vpd data from the device */ | |
2875 | vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); | |
2876 | if (vpd_size <= 0) { | |
2877 | netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); | |
2878 | return; | |
2879 | } | |
2880 | ||
2881 | /* Get the Read only section */ | |
ef215e64 BH |
2882 | ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); |
2883 | if (ro_start < 0) { | |
460eeaa0 BH |
2884 | netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); |
2885 | return; | |
2886 | } | |
2887 | ||
ef215e64 BH |
2888 | ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); |
2889 | j = ro_size; | |
2890 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
460eeaa0 BH |
2891 | if (i + j > vpd_size) |
2892 | j = vpd_size - i; | |
2893 | ||
2894 | /* Get the Part number */ | |
2895 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); | |
2896 | if (i < 0) { | |
2897 | netif_err(efx, drv, efx->net_dev, "Part number not found\n"); | |
2898 | return; | |
2899 | } | |
2900 | ||
2901 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2902 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2903 | if (i + j > vpd_size) { | |
2904 | netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); | |
2905 | return; | |
2906 | } | |
2907 | ||
2908 | netif_info(efx, drv, efx->net_dev, | |
2909 | "Part Number : %.*s\n", j, &vpd_data[i]); | |
ef215e64 BH |
2910 | |
2911 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
2912 | j = ro_size; | |
2913 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN"); | |
2914 | if (i < 0) { | |
2915 | netif_err(efx, drv, efx->net_dev, "Serial number not found\n"); | |
2916 | return; | |
2917 | } | |
2918 | ||
2919 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2920 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2921 | if (i + j > vpd_size) { | |
2922 | netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n"); | |
2923 | return; | |
2924 | } | |
2925 | ||
2926 | efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL); | |
2927 | if (!efx->vpd_sn) | |
2928 | return; | |
2929 | ||
2930 | snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]); | |
460eeaa0 BH |
2931 | } |
2932 | ||
2933 | ||
8ceee660 BH |
2934 | /* Main body of NIC initialisation |
2935 | * This is called at module load (or hotplug insertion, theoretically). | |
2936 | */ | |
2937 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2938 | { | |
2939 | int rc; | |
2940 | ||
2941 | /* Do start-of-day initialisation */ | |
2942 | rc = efx_probe_all(efx); | |
2943 | if (rc) | |
2944 | goto fail1; | |
2945 | ||
e8f14992 | 2946 | efx_init_napi(efx); |
8ceee660 | 2947 | |
ef2b90ee | 2948 | rc = efx->type->init(efx); |
8ceee660 | 2949 | if (rc) { |
62776d03 BH |
2950 | netif_err(efx, probe, efx->net_dev, |
2951 | "failed to initialise NIC\n"); | |
278c0621 | 2952 | goto fail3; |
8ceee660 BH |
2953 | } |
2954 | ||
2955 | rc = efx_init_port(efx); | |
2956 | if (rc) { | |
62776d03 BH |
2957 | netif_err(efx, probe, efx->net_dev, |
2958 | "failed to initialise port\n"); | |
278c0621 | 2959 | goto fail4; |
8ceee660 BH |
2960 | } |
2961 | ||
152b6a62 | 2962 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2963 | if (rc) |
278c0621 | 2964 | goto fail5; |
261e4d96 JC |
2965 | rc = efx_enable_interrupts(efx); |
2966 | if (rc) | |
2967 | goto fail6; | |
8ceee660 BH |
2968 | |
2969 | return 0; | |
2970 | ||
261e4d96 JC |
2971 | fail6: |
2972 | efx_nic_fini_interrupt(efx); | |
278c0621 | 2973 | fail5: |
8ceee660 | 2974 | efx_fini_port(efx); |
8ceee660 | 2975 | fail4: |
ef2b90ee | 2976 | efx->type->fini(efx); |
8ceee660 BH |
2977 | fail3: |
2978 | efx_fini_napi(efx); | |
8ceee660 BH |
2979 | efx_remove_all(efx); |
2980 | fail1: | |
2981 | return rc; | |
2982 | } | |
2983 | ||
2984 | /* NIC initialisation | |
2985 | * | |
2986 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2987 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2988 | * sets up and registers the network devices with the kernel and hooks |
2989 | * the interrupt service routine. It does not prepare the device for | |
2990 | * transmission; this is left to the first time one of the network | |
2991 | * interfaces is brought up (i.e. efx_net_open). | |
2992 | */ | |
87d1fc11 | 2993 | static int efx_pci_probe(struct pci_dev *pci_dev, |
1dd06ae8 | 2994 | const struct pci_device_id *entry) |
8ceee660 | 2995 | { |
8ceee660 BH |
2996 | struct net_device *net_dev; |
2997 | struct efx_nic *efx; | |
fadac6aa | 2998 | int rc; |
8ceee660 BH |
2999 | |
3000 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
3001 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
3002 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
3003 | if (!net_dev) |
3004 | return -ENOMEM; | |
adeb15aa BH |
3005 | efx = netdev_priv(net_dev); |
3006 | efx->type = (const struct efx_nic_type *) entry->driver_data; | |
3007 | net_dev->features |= (efx->type->offload_features | NETIF_F_SG | | |
97bc5415 | 3008 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 3009 | NETIF_F_RXCSUM); |
adeb15aa | 3010 | if (efx->type->offload_features & NETIF_F_V6_CSUM) |
738a8f4b | 3011 | net_dev->features |= NETIF_F_TSO6; |
28506563 BH |
3012 | /* Mask for features that also apply to VLAN devices */ |
3013 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
3014 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
3015 | NETIF_F_RXCSUM); | |
3016 | /* All offloads can be toggled */ | |
3017 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
8ceee660 | 3018 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 3019 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
adeb15aa | 3020 | rc = efx_init_struct(efx, pci_dev, net_dev); |
8ceee660 BH |
3021 | if (rc) |
3022 | goto fail1; | |
3023 | ||
62776d03 | 3024 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 3025 | "Solarflare NIC detected\n"); |
8ceee660 | 3026 | |
ef215e64 | 3027 | efx_probe_vpd_strings(efx); |
460eeaa0 | 3028 | |
8ceee660 BH |
3029 | /* Set up basic I/O (BAR mappings etc) */ |
3030 | rc = efx_init_io(efx); | |
3031 | if (rc) | |
3032 | goto fail2; | |
3033 | ||
fadac6aa | 3034 | rc = efx_pci_probe_main(efx); |
fadac6aa BH |
3035 | if (rc) |
3036 | goto fail3; | |
8ceee660 | 3037 | |
8ceee660 BH |
3038 | rc = efx_register_netdev(efx); |
3039 | if (rc) | |
fadac6aa | 3040 | goto fail4; |
8ceee660 | 3041 | |
7fa8d547 SS |
3042 | if (efx->type->sriov_init) { |
3043 | rc = efx->type->sriov_init(efx); | |
3044 | if (rc) | |
3045 | netif_err(efx, probe, efx->net_dev, | |
3046 | "SR-IOV can't be enabled rc %d\n", rc); | |
3047 | } | |
cd2d5b52 | 3048 | |
62776d03 | 3049 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 3050 | |
7c43161c | 3051 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 3052 | rtnl_lock(); |
7c43161c | 3053 | rc = efx_mtd_probe(efx); |
a5211bb5 | 3054 | rtnl_unlock(); |
7c43161c BH |
3055 | if (rc) |
3056 | netif_warn(efx, probe, efx->net_dev, | |
3057 | "failed to create MTDs (%d)\n", rc); | |
3058 | ||
626950db AR |
3059 | rc = pci_enable_pcie_error_reporting(pci_dev); |
3060 | if (rc && rc != -EINVAL) | |
3061 | netif_warn(efx, probe, efx->net_dev, | |
3062 | "pci_enable_pcie_error_reporting failed (%d)\n", rc); | |
3063 | ||
8ceee660 BH |
3064 | return 0; |
3065 | ||
8ceee660 | 3066 | fail4: |
fadac6aa | 3067 | efx_pci_remove_main(efx); |
8ceee660 BH |
3068 | fail3: |
3069 | efx_fini_io(efx); | |
3070 | fail2: | |
3071 | efx_fini_struct(efx); | |
3072 | fail1: | |
5e2a911c | 3073 | WARN_ON(rc > 0); |
62776d03 | 3074 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
3075 | free_netdev(net_dev); |
3076 | return rc; | |
3077 | } | |
3078 | ||
834e23dd SS |
3079 | /* efx_pci_sriov_configure returns the actual number of Virtual Functions |
3080 | * enabled on success | |
3081 | */ | |
3082 | #ifdef CONFIG_SFC_SRIOV | |
3083 | static int efx_pci_sriov_configure(struct pci_dev *dev, int num_vfs) | |
3084 | { | |
3085 | int rc; | |
3086 | struct efx_nic *efx = pci_get_drvdata(dev); | |
3087 | ||
3088 | if (efx->type->sriov_configure) { | |
3089 | rc = efx->type->sriov_configure(efx, num_vfs); | |
3090 | if (rc) | |
3091 | return rc; | |
3092 | else | |
3093 | return num_vfs; | |
3094 | } else | |
3095 | return -EOPNOTSUPP; | |
3096 | } | |
3097 | #endif | |
3098 | ||
89c758fa BH |
3099 | static int efx_pm_freeze(struct device *dev) |
3100 | { | |
3101 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
3102 | ||
61da026d BH |
3103 | rtnl_lock(); |
3104 | ||
6032fb56 BH |
3105 | if (efx->state != STATE_DISABLED) { |
3106 | efx->state = STATE_UNINIT; | |
89c758fa | 3107 | |
c2f3b8e3 | 3108 | efx_device_detach_sync(efx); |
89c758fa | 3109 | |
6032fb56 | 3110 | efx_stop_all(efx); |
d8291187 | 3111 | efx_disable_interrupts(efx); |
6032fb56 | 3112 | } |
89c758fa | 3113 | |
61da026d BH |
3114 | rtnl_unlock(); |
3115 | ||
89c758fa BH |
3116 | return 0; |
3117 | } | |
3118 | ||
3119 | static int efx_pm_thaw(struct device *dev) | |
3120 | { | |
261e4d96 | 3121 | int rc; |
89c758fa BH |
3122 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); |
3123 | ||
61da026d BH |
3124 | rtnl_lock(); |
3125 | ||
6032fb56 | 3126 | if (efx->state != STATE_DISABLED) { |
261e4d96 JC |
3127 | rc = efx_enable_interrupts(efx); |
3128 | if (rc) | |
3129 | goto fail; | |
89c758fa | 3130 | |
6032fb56 BH |
3131 | mutex_lock(&efx->mac_lock); |
3132 | efx->phy_op->reconfigure(efx); | |
3133 | mutex_unlock(&efx->mac_lock); | |
89c758fa | 3134 | |
6032fb56 | 3135 | efx_start_all(efx); |
89c758fa | 3136 | |
6032fb56 | 3137 | netif_device_attach(efx->net_dev); |
89c758fa | 3138 | |
6032fb56 | 3139 | efx->state = STATE_READY; |
89c758fa | 3140 | |
6032fb56 BH |
3141 | efx->type->resume_wol(efx); |
3142 | } | |
89c758fa | 3143 | |
61da026d BH |
3144 | rtnl_unlock(); |
3145 | ||
319ba649 SH |
3146 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
3147 | queue_work(reset_workqueue, &efx->reset_work); | |
3148 | ||
89c758fa | 3149 | return 0; |
261e4d96 JC |
3150 | |
3151 | fail: | |
3152 | rtnl_unlock(); | |
3153 | ||
3154 | return rc; | |
89c758fa BH |
3155 | } |
3156 | ||
3157 | static int efx_pm_poweroff(struct device *dev) | |
3158 | { | |
3159 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
3160 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
3161 | ||
3162 | efx->type->fini(efx); | |
3163 | ||
a7d529ae | 3164 | efx->reset_pending = 0; |
89c758fa BH |
3165 | |
3166 | pci_save_state(pci_dev); | |
3167 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
3168 | } | |
3169 | ||
3170 | /* Used for both resume and restore */ | |
3171 | static int efx_pm_resume(struct device *dev) | |
3172 | { | |
3173 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
3174 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
3175 | int rc; | |
3176 | ||
3177 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
3178 | if (rc) | |
3179 | return rc; | |
3180 | pci_restore_state(pci_dev); | |
3181 | rc = pci_enable_device(pci_dev); | |
3182 | if (rc) | |
3183 | return rc; | |
3184 | pci_set_master(efx->pci_dev); | |
3185 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
3186 | if (rc) | |
3187 | return rc; | |
3188 | rc = efx->type->init(efx); | |
3189 | if (rc) | |
3190 | return rc; | |
261e4d96 JC |
3191 | rc = efx_pm_thaw(dev); |
3192 | return rc; | |
89c758fa BH |
3193 | } |
3194 | ||
3195 | static int efx_pm_suspend(struct device *dev) | |
3196 | { | |
3197 | int rc; | |
3198 | ||
3199 | efx_pm_freeze(dev); | |
3200 | rc = efx_pm_poweroff(dev); | |
3201 | if (rc) | |
3202 | efx_pm_resume(dev); | |
3203 | return rc; | |
3204 | } | |
3205 | ||
18e83e4c | 3206 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
3207 | .suspend = efx_pm_suspend, |
3208 | .resume = efx_pm_resume, | |
3209 | .freeze = efx_pm_freeze, | |
3210 | .thaw = efx_pm_thaw, | |
3211 | .poweroff = efx_pm_poweroff, | |
3212 | .restore = efx_pm_resume, | |
3213 | }; | |
3214 | ||
626950db AR |
3215 | /* A PCI error affecting this device was detected. |
3216 | * At this point MMIO and DMA may be disabled. | |
3217 | * Stop the software path and request a slot reset. | |
3218 | */ | |
debd0034 | 3219 | static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev, |
3220 | enum pci_channel_state state) | |
626950db AR |
3221 | { |
3222 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3223 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3224 | ||
3225 | if (state == pci_channel_io_perm_failure) | |
3226 | return PCI_ERS_RESULT_DISCONNECT; | |
3227 | ||
3228 | rtnl_lock(); | |
3229 | ||
3230 | if (efx->state != STATE_DISABLED) { | |
3231 | efx->state = STATE_RECOVERY; | |
3232 | efx->reset_pending = 0; | |
3233 | ||
3234 | efx_device_detach_sync(efx); | |
3235 | ||
3236 | efx_stop_all(efx); | |
d8291187 | 3237 | efx_disable_interrupts(efx); |
626950db AR |
3238 | |
3239 | status = PCI_ERS_RESULT_NEED_RESET; | |
3240 | } else { | |
3241 | /* If the interface is disabled we don't want to do anything | |
3242 | * with it. | |
3243 | */ | |
3244 | status = PCI_ERS_RESULT_RECOVERED; | |
3245 | } | |
3246 | ||
3247 | rtnl_unlock(); | |
3248 | ||
3249 | pci_disable_device(pdev); | |
3250 | ||
3251 | return status; | |
3252 | } | |
3253 | ||
dbedd44e | 3254 | /* Fake a successful reset, which will be performed later in efx_io_resume. */ |
debd0034 | 3255 | static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev) |
626950db AR |
3256 | { |
3257 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3258 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3259 | int rc; | |
3260 | ||
3261 | if (pci_enable_device(pdev)) { | |
3262 | netif_err(efx, hw, efx->net_dev, | |
3263 | "Cannot re-enable PCI device after reset.\n"); | |
3264 | status = PCI_ERS_RESULT_DISCONNECT; | |
3265 | } | |
3266 | ||
3267 | rc = pci_cleanup_aer_uncorrect_error_status(pdev); | |
3268 | if (rc) { | |
3269 | netif_err(efx, hw, efx->net_dev, | |
3270 | "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc); | |
3271 | /* Non-fatal error. Continue. */ | |
3272 | } | |
3273 | ||
3274 | return status; | |
3275 | } | |
3276 | ||
3277 | /* Perform the actual reset and resume I/O operations. */ | |
3278 | static void efx_io_resume(struct pci_dev *pdev) | |
3279 | { | |
3280 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3281 | int rc; | |
3282 | ||
3283 | rtnl_lock(); | |
3284 | ||
3285 | if (efx->state == STATE_DISABLED) | |
3286 | goto out; | |
3287 | ||
3288 | rc = efx_reset(efx, RESET_TYPE_ALL); | |
3289 | if (rc) { | |
3290 | netif_err(efx, hw, efx->net_dev, | |
3291 | "efx_reset failed after PCI error (%d)\n", rc); | |
3292 | } else { | |
3293 | efx->state = STATE_READY; | |
3294 | netif_dbg(efx, hw, efx->net_dev, | |
3295 | "Done resetting and resuming IO after PCI error.\n"); | |
3296 | } | |
3297 | ||
3298 | out: | |
3299 | rtnl_unlock(); | |
3300 | } | |
3301 | ||
3302 | /* For simplicity and reliability, we always require a slot reset and try to | |
3303 | * reset the hardware when a pci error affecting the device is detected. | |
3304 | * We leave both the link_reset and mmio_enabled callback unimplemented: | |
3305 | * with our request for slot reset the mmio_enabled callback will never be | |
3306 | * called, and the link_reset callback is not used by AER or EEH mechanisms. | |
3307 | */ | |
3308 | static struct pci_error_handlers efx_err_handlers = { | |
3309 | .error_detected = efx_io_error_detected, | |
3310 | .slot_reset = efx_io_slot_reset, | |
3311 | .resume = efx_io_resume, | |
3312 | }; | |
3313 | ||
8ceee660 | 3314 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 3315 | .name = KBUILD_MODNAME, |
8ceee660 BH |
3316 | .id_table = efx_pci_table, |
3317 | .probe = efx_pci_probe, | |
3318 | .remove = efx_pci_remove, | |
89c758fa | 3319 | .driver.pm = &efx_pm_ops, |
626950db | 3320 | .err_handler = &efx_err_handlers, |
834e23dd SS |
3321 | #ifdef CONFIG_SFC_SRIOV |
3322 | .sriov_configure = efx_pci_sriov_configure, | |
3323 | #endif | |
8ceee660 BH |
3324 | }; |
3325 | ||
3326 | /************************************************************************** | |
3327 | * | |
3328 | * Kernel module interface | |
3329 | * | |
3330 | *************************************************************************/ | |
3331 | ||
3332 | module_param(interrupt_mode, uint, 0444); | |
3333 | MODULE_PARM_DESC(interrupt_mode, | |
3334 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
3335 | ||
3336 | static int __init efx_init_module(void) | |
3337 | { | |
3338 | int rc; | |
3339 | ||
3340 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
3341 | ||
3342 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
3343 | if (rc) | |
3344 | goto err_notifier; | |
3345 | ||
7fa8d547 | 3346 | #ifdef CONFIG_SFC_SRIOV |
cd2d5b52 BH |
3347 | rc = efx_init_sriov(); |
3348 | if (rc) | |
3349 | goto err_sriov; | |
7fa8d547 | 3350 | #endif |
cd2d5b52 | 3351 | |
1ab00629 SH |
3352 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
3353 | if (!reset_workqueue) { | |
3354 | rc = -ENOMEM; | |
3355 | goto err_reset; | |
3356 | } | |
8ceee660 BH |
3357 | |
3358 | rc = pci_register_driver(&efx_pci_driver); | |
3359 | if (rc < 0) | |
3360 | goto err_pci; | |
3361 | ||
3362 | return 0; | |
3363 | ||
3364 | err_pci: | |
1ab00629 SH |
3365 | destroy_workqueue(reset_workqueue); |
3366 | err_reset: | |
7fa8d547 | 3367 | #ifdef CONFIG_SFC_SRIOV |
cd2d5b52 BH |
3368 | efx_fini_sriov(); |
3369 | err_sriov: | |
7fa8d547 | 3370 | #endif |
8ceee660 BH |
3371 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3372 | err_notifier: | |
3373 | return rc; | |
3374 | } | |
3375 | ||
3376 | static void __exit efx_exit_module(void) | |
3377 | { | |
3378 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
3379 | ||
3380 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 3381 | destroy_workqueue(reset_workqueue); |
7fa8d547 | 3382 | #ifdef CONFIG_SFC_SRIOV |
cd2d5b52 | 3383 | efx_fini_sriov(); |
7fa8d547 | 3384 | #endif |
8ceee660 BH |
3385 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3386 | ||
3387 | } | |
3388 | ||
3389 | module_init(efx_init_module); | |
3390 | module_exit(efx_exit_module); | |
3391 | ||
906bb26c BH |
3392 | MODULE_AUTHOR("Solarflare Communications and " |
3393 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
6a350fdb | 3394 | MODULE_DESCRIPTION("Solarflare network driver"); |
8ceee660 BH |
3395 | MODULE_LICENSE("GPL"); |
3396 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |