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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
64d8ad6d | 24 | #include <linux/cpu_rmap.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 41 | const char *const efx_loopback_mode_names[] = { |
c459302d | 42 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
47 | [LOOPBACK_XAUI] = "XAUI", |
48 | [LOOPBACK_GMII] = "GMII", | |
49 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
50 | [LOOPBACK_XGBR] = "XGBR", |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
58 | [LOOPBACK_PCS] = "PCS", |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 65 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
69 | }; |
70 | ||
c459302d | 71 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 72 | const char *const efx_reset_type_names[] = { |
c459302d BH |
73 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
74 | [RESET_TYPE_ALL] = "ALL", | |
75 | [RESET_TYPE_WORLD] = "WORLD", | |
76 | [RESET_TYPE_DISABLE] = "DISABLE", | |
77 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
78 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
79 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
80 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
81 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 83 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
84 | }; |
85 | ||
8ceee660 BH |
86 | #define EFX_MAX_MTU (9 * 1024) |
87 | ||
1ab00629 SH |
88 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
89 | * queued onto this work queue. This is not a per-nic work queue, because | |
90 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
91 | */ | |
92 | static struct workqueue_struct *reset_workqueue; | |
93 | ||
8ceee660 BH |
94 | /************************************************************************** |
95 | * | |
96 | * Configurable values | |
97 | * | |
98 | *************************************************************************/ | |
99 | ||
8ceee660 BH |
100 | /* |
101 | * Use separate channels for TX and RX events | |
102 | * | |
28b581ab NT |
103 | * Set this to 1 to use separate channels for TX and RX. It allows us |
104 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 105 | * |
28b581ab | 106 | * This is only used in MSI-X interrupt mode |
8ceee660 | 107 | */ |
28b581ab | 108 | static unsigned int separate_tx_channels; |
8313aca3 | 109 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
110 | MODULE_PARM_DESC(separate_tx_channels, |
111 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
112 | |
113 | /* This is the weight assigned to each of the (per-channel) virtual | |
114 | * NAPI devices. | |
115 | */ | |
116 | static int napi_weight = 64; | |
117 | ||
118 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
119 | * monitor. On Falcon-based NICs, this will: |
120 | * - Check the on-board hardware monitor; | |
121 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 122 | */ |
d215697f | 123 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 124 | |
8ceee660 BH |
125 | /* Initial interrupt moderation settings. They can be modified after |
126 | * module load with ethtool. | |
127 | * | |
128 | * The default for RX should strike a balance between increasing the | |
129 | * round-trip latency and reducing overhead. | |
130 | */ | |
131 | static unsigned int rx_irq_mod_usec = 60; | |
132 | ||
133 | /* Initial interrupt moderation settings. They can be modified after | |
134 | * module load with ethtool. | |
135 | * | |
136 | * This default is chosen to ensure that a 10G link does not go idle | |
137 | * while a TX queue is stopped after it has become full. A queue is | |
138 | * restarted when it drops below half full. The time this takes (assuming | |
139 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
140 | * 512 / 3 * 1.2 = 205 usec. | |
141 | */ | |
142 | static unsigned int tx_irq_mod_usec = 150; | |
143 | ||
144 | /* This is the first interrupt mode to try out of: | |
145 | * 0 => MSI-X | |
146 | * 1 => MSI | |
147 | * 2 => legacy | |
148 | */ | |
149 | static unsigned int interrupt_mode; | |
150 | ||
151 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
152 | * i.e. the number of CPUs among which we may distribute simultaneous | |
153 | * interrupt handling. | |
154 | * | |
155 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 156 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
157 | */ |
158 | static unsigned int rss_cpus; | |
159 | module_param(rss_cpus, uint, 0444); | |
160 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
161 | ||
84ae48fe BH |
162 | static int phy_flash_cfg; |
163 | module_param(phy_flash_cfg, int, 0644); | |
164 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
165 | ||
6fb70fd1 BH |
166 | static unsigned irq_adapt_low_thresh = 10000; |
167 | module_param(irq_adapt_low_thresh, uint, 0644); | |
168 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
169 | "Threshold score for reducing IRQ moderation"); | |
170 | ||
171 | static unsigned irq_adapt_high_thresh = 20000; | |
172 | module_param(irq_adapt_high_thresh, uint, 0644); | |
173 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
174 | "Threshold score for increasing IRQ moderation"); | |
175 | ||
62776d03 BH |
176 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
177 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
178 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
179 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
180 | module_param(debug, uint, 0); | |
181 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
182 | ||
8ceee660 BH |
183 | /************************************************************************** |
184 | * | |
185 | * Utility functions and prototypes | |
186 | * | |
187 | *************************************************************************/ | |
4642610c | 188 | |
7f967c01 BH |
189 | static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq); |
190 | static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq); | |
191 | static void efx_remove_channel(struct efx_channel *channel); | |
4642610c | 192 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 193 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 194 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 195 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 196 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 197 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
198 | static void efx_fini_struct(struct efx_nic *efx); |
199 | static void efx_start_all(struct efx_nic *efx); | |
200 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
201 | |
202 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
203 | do { \ | |
332c1ce9 BH |
204 | if ((efx->state == STATE_RUNNING) || \ |
205 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
206 | ASSERT_RTNL(); \ |
207 | } while (0) | |
208 | ||
209 | /************************************************************************** | |
210 | * | |
211 | * Event queue processing | |
212 | * | |
213 | *************************************************************************/ | |
214 | ||
215 | /* Process channel's event queue | |
216 | * | |
217 | * This function is responsible for processing the event queue of a | |
218 | * single channel. The caller must guarantee that this function will | |
219 | * never be concurrently called more than once on the same channel, | |
220 | * though different channels may be being processed concurrently. | |
221 | */ | |
fa236e18 | 222 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 223 | { |
fa236e18 | 224 | int spent; |
8ceee660 | 225 | |
9f2cb71c | 226 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 227 | return 0; |
8ceee660 | 228 | |
fa236e18 | 229 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
230 | if (spent && efx_channel_has_rx_queue(channel)) { |
231 | struct efx_rx_queue *rx_queue = | |
232 | efx_channel_get_rx_queue(channel); | |
233 | ||
234 | /* Deliver last RX packet. */ | |
235 | if (channel->rx_pkt) { | |
236 | __efx_rx_packet(channel, channel->rx_pkt); | |
237 | channel->rx_pkt = NULL; | |
238 | } | |
9f2cb71c BH |
239 | if (rx_queue->enabled) { |
240 | efx_rx_strategy(channel); | |
241 | efx_fast_push_rx_descriptors(rx_queue); | |
242 | } | |
8ceee660 BH |
243 | } |
244 | ||
fa236e18 | 245 | return spent; |
8ceee660 BH |
246 | } |
247 | ||
248 | /* Mark channel as finished processing | |
249 | * | |
250 | * Note that since we will not receive further interrupts for this | |
251 | * channel before we finish processing and call the eventq_read_ack() | |
252 | * method, there is no need to use the interrupt hold-off timers. | |
253 | */ | |
254 | static inline void efx_channel_processed(struct efx_channel *channel) | |
255 | { | |
5b9e207c BH |
256 | /* The interrupt handler for this channel may set work_pending |
257 | * as soon as we acknowledge the events we've seen. Make sure | |
258 | * it's cleared before then. */ | |
dc8cfa55 | 259 | channel->work_pending = false; |
5b9e207c BH |
260 | smp_wmb(); |
261 | ||
152b6a62 | 262 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
263 | } |
264 | ||
265 | /* NAPI poll handler | |
266 | * | |
267 | * NAPI guarantees serialisation of polls of the same device, which | |
268 | * provides the guarantee required by efx_process_channel(). | |
269 | */ | |
270 | static int efx_poll(struct napi_struct *napi, int budget) | |
271 | { | |
272 | struct efx_channel *channel = | |
273 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 274 | struct efx_nic *efx = channel->efx; |
fa236e18 | 275 | int spent; |
8ceee660 | 276 | |
62776d03 BH |
277 | netif_vdbg(efx, intr, efx->net_dev, |
278 | "channel %d NAPI poll executing on CPU %d\n", | |
279 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 280 | |
fa236e18 | 281 | spent = efx_process_channel(channel, budget); |
8ceee660 | 282 | |
fa236e18 | 283 | if (spent < budget) { |
9d9a6973 | 284 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
285 | efx->irq_rx_adaptive && |
286 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
287 | if (unlikely(channel->irq_mod_score < |
288 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
289 | if (channel->irq_moderation > 1) { |
290 | channel->irq_moderation -= 1; | |
ef2b90ee | 291 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 292 | } |
6fb70fd1 BH |
293 | } else if (unlikely(channel->irq_mod_score > |
294 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
295 | if (channel->irq_moderation < |
296 | efx->irq_rx_moderation) { | |
297 | channel->irq_moderation += 1; | |
ef2b90ee | 298 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 299 | } |
6fb70fd1 | 300 | } |
6fb70fd1 BH |
301 | channel->irq_count = 0; |
302 | channel->irq_mod_score = 0; | |
303 | } | |
304 | ||
64d8ad6d BH |
305 | efx_filter_rfs_expire(channel); |
306 | ||
8ceee660 | 307 | /* There is no race here; although napi_disable() will |
288379f0 | 308 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
309 | * since efx_channel_processed() will have no effect if |
310 | * interrupts have already been disabled. | |
311 | */ | |
288379f0 | 312 | napi_complete(napi); |
8ceee660 BH |
313 | efx_channel_processed(channel); |
314 | } | |
315 | ||
fa236e18 | 316 | return spent; |
8ceee660 BH |
317 | } |
318 | ||
319 | /* Process the eventq of the specified channel immediately on this CPU | |
320 | * | |
321 | * Disable hardware generated interrupts, wait for any existing | |
322 | * processing to finish, then directly poll (and ack ) the eventq. | |
323 | * Finally reenable NAPI and interrupts. | |
324 | * | |
d4fabcc8 BH |
325 | * This is for use only during a loopback self-test. It must not |
326 | * deliver any packets up the stack as this can result in deadlock. | |
8ceee660 BH |
327 | */ |
328 | void efx_process_channel_now(struct efx_channel *channel) | |
329 | { | |
330 | struct efx_nic *efx = channel->efx; | |
331 | ||
8313aca3 | 332 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 | 333 | BUG_ON(!channel->enabled); |
d4fabcc8 | 334 | BUG_ON(!efx->loopback_selftest); |
8ceee660 BH |
335 | |
336 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 337 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 338 | if (efx->legacy_irq) { |
8ceee660 | 339 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
340 | efx->legacy_irq_enabled = false; |
341 | } | |
64ee3120 | 342 | if (channel->irq) |
8ceee660 BH |
343 | synchronize_irq(channel->irq); |
344 | ||
345 | /* Wait for any NAPI processing to complete */ | |
346 | napi_disable(&channel->napi_str); | |
347 | ||
348 | /* Poll the channel */ | |
ecc910f5 | 349 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
350 | |
351 | /* Ack the eventq. This may cause an interrupt to be generated | |
352 | * when they are reenabled */ | |
353 | efx_channel_processed(channel); | |
354 | ||
355 | napi_enable(&channel->napi_str); | |
94dec6a2 BH |
356 | if (efx->legacy_irq) |
357 | efx->legacy_irq_enabled = true; | |
152b6a62 | 358 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
359 | } |
360 | ||
361 | /* Create event queue | |
362 | * Event queue memory allocations are done only once. If the channel | |
363 | * is reset, the memory buffer will be reused; this guards against | |
364 | * errors during channel reset and also simplifies interrupt handling. | |
365 | */ | |
366 | static int efx_probe_eventq(struct efx_channel *channel) | |
367 | { | |
ecc910f5 SH |
368 | struct efx_nic *efx = channel->efx; |
369 | unsigned long entries; | |
370 | ||
86ee5302 | 371 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 372 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 373 | |
ecc910f5 SH |
374 | /* Build an event queue with room for one event per tx and rx buffer, |
375 | * plus some extra for link state events and MCDI completions. */ | |
376 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
377 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
378 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
379 | ||
152b6a62 | 380 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
381 | } |
382 | ||
383 | /* Prepare channel's event queue */ | |
bc3c90a2 | 384 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 385 | { |
62776d03 BH |
386 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
387 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
388 | |
389 | channel->eventq_read_ptr = 0; | |
390 | ||
152b6a62 | 391 | efx_nic_init_eventq(channel); |
8ceee660 BH |
392 | } |
393 | ||
9f2cb71c BH |
394 | /* Enable event queue processing and NAPI */ |
395 | static void efx_start_eventq(struct efx_channel *channel) | |
396 | { | |
397 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
398 | "chan %d start event queue\n", channel->channel); | |
399 | ||
400 | /* The interrupt handler for this channel may set work_pending | |
401 | * as soon as we enable it. Make sure it's cleared before | |
402 | * then. Similarly, make sure it sees the enabled flag set. | |
403 | */ | |
404 | channel->work_pending = false; | |
405 | channel->enabled = true; | |
406 | smp_wmb(); | |
407 | ||
408 | napi_enable(&channel->napi_str); | |
409 | efx_nic_eventq_read_ack(channel); | |
410 | } | |
411 | ||
412 | /* Disable event queue processing and NAPI */ | |
413 | static void efx_stop_eventq(struct efx_channel *channel) | |
414 | { | |
415 | if (!channel->enabled) | |
416 | return; | |
417 | ||
418 | napi_disable(&channel->napi_str); | |
419 | channel->enabled = false; | |
420 | } | |
421 | ||
8ceee660 BH |
422 | static void efx_fini_eventq(struct efx_channel *channel) |
423 | { | |
62776d03 BH |
424 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
425 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 426 | |
152b6a62 | 427 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
428 | } |
429 | ||
430 | static void efx_remove_eventq(struct efx_channel *channel) | |
431 | { | |
62776d03 BH |
432 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
433 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 434 | |
152b6a62 | 435 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
436 | } |
437 | ||
438 | /************************************************************************** | |
439 | * | |
440 | * Channel handling | |
441 | * | |
442 | *************************************************************************/ | |
443 | ||
7f967c01 | 444 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
445 | static struct efx_channel * |
446 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
447 | { | |
448 | struct efx_channel *channel; | |
449 | struct efx_rx_queue *rx_queue; | |
450 | struct efx_tx_queue *tx_queue; | |
451 | int j; | |
452 | ||
7f967c01 BH |
453 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
454 | if (!channel) | |
455 | return NULL; | |
4642610c | 456 | |
7f967c01 BH |
457 | channel->efx = efx; |
458 | channel->channel = i; | |
459 | channel->type = &efx_default_channel_type; | |
4642610c | 460 | |
7f967c01 BH |
461 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
462 | tx_queue = &channel->tx_queue[j]; | |
463 | tx_queue->efx = efx; | |
464 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
465 | tx_queue->channel = channel; | |
466 | } | |
4642610c | 467 | |
7f967c01 BH |
468 | rx_queue = &channel->rx_queue; |
469 | rx_queue->efx = efx; | |
470 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
471 | (unsigned long)rx_queue); | |
4642610c | 472 | |
7f967c01 BH |
473 | return channel; |
474 | } | |
475 | ||
476 | /* Allocate and initialise a channel structure, copying parameters | |
477 | * (but not resources) from an old channel structure. | |
478 | */ | |
479 | static struct efx_channel * | |
480 | efx_copy_channel(const struct efx_channel *old_channel) | |
481 | { | |
482 | struct efx_channel *channel; | |
483 | struct efx_rx_queue *rx_queue; | |
484 | struct efx_tx_queue *tx_queue; | |
485 | int j; | |
4642610c | 486 | |
7f967c01 BH |
487 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
488 | if (!channel) | |
489 | return NULL; | |
490 | ||
491 | *channel = *old_channel; | |
492 | ||
493 | channel->napi_dev = NULL; | |
494 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 495 | |
7f967c01 BH |
496 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
497 | tx_queue = &channel->tx_queue[j]; | |
498 | if (tx_queue->channel) | |
4642610c | 499 | tx_queue->channel = channel; |
7f967c01 BH |
500 | tx_queue->buffer = NULL; |
501 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
502 | } |
503 | ||
4642610c | 504 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
505 | rx_queue->buffer = NULL; |
506 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
507 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
508 | (unsigned long)rx_queue); | |
509 | ||
510 | return channel; | |
511 | } | |
512 | ||
8ceee660 BH |
513 | static int efx_probe_channel(struct efx_channel *channel) |
514 | { | |
515 | struct efx_tx_queue *tx_queue; | |
516 | struct efx_rx_queue *rx_queue; | |
517 | int rc; | |
518 | ||
62776d03 BH |
519 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
520 | "creating channel %d\n", channel->channel); | |
8ceee660 | 521 | |
7f967c01 BH |
522 | rc = channel->type->pre_probe(channel); |
523 | if (rc) | |
524 | goto fail; | |
525 | ||
8ceee660 BH |
526 | rc = efx_probe_eventq(channel); |
527 | if (rc) | |
7f967c01 | 528 | goto fail; |
8ceee660 BH |
529 | |
530 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
531 | rc = efx_probe_tx_queue(tx_queue); | |
532 | if (rc) | |
7f967c01 | 533 | goto fail; |
8ceee660 BH |
534 | } |
535 | ||
536 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
537 | rc = efx_probe_rx_queue(rx_queue); | |
538 | if (rc) | |
7f967c01 | 539 | goto fail; |
8ceee660 BH |
540 | } |
541 | ||
542 | channel->n_rx_frm_trunc = 0; | |
543 | ||
544 | return 0; | |
545 | ||
7f967c01 BH |
546 | fail: |
547 | efx_remove_channel(channel); | |
8ceee660 BH |
548 | return rc; |
549 | } | |
550 | ||
7f967c01 BH |
551 | static void |
552 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
553 | { | |
554 | struct efx_nic *efx = channel->efx; | |
555 | const char *type; | |
556 | int number; | |
557 | ||
558 | number = channel->channel; | |
559 | if (efx->tx_channel_offset == 0) { | |
560 | type = ""; | |
561 | } else if (channel->channel < efx->tx_channel_offset) { | |
562 | type = "-rx"; | |
563 | } else { | |
564 | type = "-tx"; | |
565 | number -= efx->tx_channel_offset; | |
566 | } | |
567 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
568 | } | |
8ceee660 | 569 | |
56536e9c BH |
570 | static void efx_set_channel_names(struct efx_nic *efx) |
571 | { | |
572 | struct efx_channel *channel; | |
56536e9c | 573 | |
7f967c01 BH |
574 | efx_for_each_channel(channel, efx) |
575 | channel->type->get_name(channel, | |
576 | efx->channel_name[channel->channel], | |
577 | sizeof(efx->channel_name[0])); | |
56536e9c BH |
578 | } |
579 | ||
4642610c BH |
580 | static int efx_probe_channels(struct efx_nic *efx) |
581 | { | |
582 | struct efx_channel *channel; | |
583 | int rc; | |
584 | ||
585 | /* Restart special buffer allocation */ | |
586 | efx->next_buffer_table = 0; | |
587 | ||
c92aaff1 BH |
588 | /* Probe channels in reverse, so that any 'extra' channels |
589 | * use the start of the buffer table. This allows the traffic | |
590 | * channels to be resized without moving them or wasting the | |
591 | * entries before them. | |
592 | */ | |
593 | efx_for_each_channel_rev(channel, efx) { | |
4642610c BH |
594 | rc = efx_probe_channel(channel); |
595 | if (rc) { | |
596 | netif_err(efx, probe, efx->net_dev, | |
597 | "failed to create channel %d\n", | |
598 | channel->channel); | |
599 | goto fail; | |
600 | } | |
601 | } | |
602 | efx_set_channel_names(efx); | |
603 | ||
604 | return 0; | |
605 | ||
606 | fail: | |
607 | efx_remove_channels(efx); | |
608 | return rc; | |
609 | } | |
610 | ||
8ceee660 BH |
611 | /* Channels are shutdown and reinitialised whilst the NIC is running |
612 | * to propagate configuration changes (mtu, checksum offload), or | |
613 | * to clear hardware error conditions | |
614 | */ | |
9f2cb71c | 615 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 BH |
616 | { |
617 | struct efx_tx_queue *tx_queue; | |
618 | struct efx_rx_queue *rx_queue; | |
619 | struct efx_channel *channel; | |
8ceee660 | 620 | |
f7f13b0b BH |
621 | /* Calculate the rx buffer allocation parameters required to |
622 | * support the current MTU, including padding for header | |
623 | * alignment and overruns. | |
624 | */ | |
625 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
626 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 627 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 628 | efx->type->rx_buffer_padding); |
62b330ba SH |
629 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
630 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
631 | |
632 | /* Initialise the channels */ | |
633 | efx_for_each_channel(channel, efx) { | |
bc3c90a2 BH |
634 | efx_for_each_channel_tx_queue(tx_queue, channel) |
635 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
636 | |
637 | /* The rx buffer allocation strategy is MTU dependent */ | |
638 | efx_rx_strategy(channel); | |
639 | ||
9f2cb71c | 640 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 641 | efx_init_rx_queue(rx_queue); |
9f2cb71c BH |
642 | efx_nic_generate_fill_event(rx_queue); |
643 | } | |
8ceee660 BH |
644 | |
645 | WARN_ON(channel->rx_pkt != NULL); | |
646 | efx_rx_strategy(channel); | |
647 | } | |
8ceee660 | 648 | |
9f2cb71c BH |
649 | if (netif_device_present(efx->net_dev)) |
650 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
651 | } |
652 | ||
9f2cb71c | 653 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
654 | { |
655 | struct efx_channel *channel; | |
656 | struct efx_tx_queue *tx_queue; | |
657 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 658 | int rc; |
8ceee660 BH |
659 | |
660 | EFX_ASSERT_RESET_SERIALISED(efx); | |
661 | BUG_ON(efx->port_enabled); | |
662 | ||
152b6a62 | 663 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
664 | if (rc && EFX_WORKAROUND_7803(efx)) { |
665 | /* Schedule a reset to recover from the flush failure. The | |
666 | * descriptor caches reference memory we're about to free, | |
667 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
668 | * the MACs because of the pending reset. */ | |
62776d03 BH |
669 | netif_err(efx, drv, efx->net_dev, |
670 | "Resetting to recover from flush failure\n"); | |
fd371e32 SH |
671 | efx_schedule_reset(efx, RESET_TYPE_ALL); |
672 | } else if (rc) { | |
62776d03 | 673 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); |
fd371e32 | 674 | } else { |
62776d03 BH |
675 | netif_dbg(efx, drv, efx->net_dev, |
676 | "successfully flushed all queues\n"); | |
fd371e32 | 677 | } |
6bc5d3a9 | 678 | |
8ceee660 | 679 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
680 | /* RX packet processing is pipelined, so wait for the |
681 | * NAPI handler to complete. At least event queue 0 | |
682 | * might be kept active by non-data events, so don't | |
683 | * use napi_synchronize() but actually disable NAPI | |
684 | * temporarily. | |
685 | */ | |
686 | if (efx_channel_has_rx_queue(channel)) { | |
687 | efx_stop_eventq(channel); | |
688 | efx_start_eventq(channel); | |
689 | } | |
8ceee660 BH |
690 | |
691 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
692 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 693 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 694 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
695 | } |
696 | } | |
697 | ||
698 | static void efx_remove_channel(struct efx_channel *channel) | |
699 | { | |
700 | struct efx_tx_queue *tx_queue; | |
701 | struct efx_rx_queue *rx_queue; | |
702 | ||
62776d03 BH |
703 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
704 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
705 | |
706 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
707 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 708 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
709 | efx_remove_tx_queue(tx_queue); |
710 | efx_remove_eventq(channel); | |
8ceee660 BH |
711 | } |
712 | ||
4642610c BH |
713 | static void efx_remove_channels(struct efx_nic *efx) |
714 | { | |
715 | struct efx_channel *channel; | |
716 | ||
717 | efx_for_each_channel(channel, efx) | |
718 | efx_remove_channel(channel); | |
719 | } | |
720 | ||
721 | int | |
722 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
723 | { | |
724 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
725 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 BH |
726 | unsigned i, next_buffer_table = 0; |
727 | int rc = 0; | |
728 | ||
729 | /* Not all channels should be reallocated. We must avoid | |
730 | * reallocating their buffer table entries. | |
731 | */ | |
732 | efx_for_each_channel(channel, efx) { | |
733 | struct efx_rx_queue *rx_queue; | |
734 | struct efx_tx_queue *tx_queue; | |
735 | ||
736 | if (channel->type->copy) | |
737 | continue; | |
738 | next_buffer_table = max(next_buffer_table, | |
739 | channel->eventq.index + | |
740 | channel->eventq.entries); | |
741 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
742 | next_buffer_table = max(next_buffer_table, | |
743 | rx_queue->rxd.index + | |
744 | rx_queue->rxd.entries); | |
745 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
746 | next_buffer_table = max(next_buffer_table, | |
747 | tx_queue->txd.index + | |
748 | tx_queue->txd.entries); | |
749 | } | |
4642610c BH |
750 | |
751 | efx_stop_all(efx); | |
7f967c01 | 752 | efx_stop_interrupts(efx, true); |
4642610c | 753 | |
7f967c01 | 754 | /* Clone channels (where possible) */ |
4642610c BH |
755 | memset(other_channel, 0, sizeof(other_channel)); |
756 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
757 | channel = efx->channel[i]; |
758 | if (channel->type->copy) | |
759 | channel = channel->type->copy(channel); | |
4642610c BH |
760 | if (!channel) { |
761 | rc = -ENOMEM; | |
762 | goto out; | |
763 | } | |
764 | other_channel[i] = channel; | |
765 | } | |
766 | ||
767 | /* Swap entry counts and channel pointers */ | |
768 | old_rxq_entries = efx->rxq_entries; | |
769 | old_txq_entries = efx->txq_entries; | |
770 | efx->rxq_entries = rxq_entries; | |
771 | efx->txq_entries = txq_entries; | |
772 | for (i = 0; i < efx->n_channels; i++) { | |
773 | channel = efx->channel[i]; | |
774 | efx->channel[i] = other_channel[i]; | |
775 | other_channel[i] = channel; | |
776 | } | |
777 | ||
7f967c01 BH |
778 | /* Restart buffer table allocation */ |
779 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 780 | |
e8f14992 | 781 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
782 | channel = efx->channel[i]; |
783 | if (!channel->type->copy) | |
784 | continue; | |
785 | rc = efx_probe_channel(channel); | |
786 | if (rc) | |
787 | goto rollback; | |
788 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 789 | } |
7f967c01 | 790 | |
4642610c | 791 | out: |
7f967c01 BH |
792 | /* Destroy unused channel structures */ |
793 | for (i = 0; i < efx->n_channels; i++) { | |
794 | channel = other_channel[i]; | |
795 | if (channel && channel->type->copy) { | |
796 | efx_fini_napi_channel(channel); | |
797 | efx_remove_channel(channel); | |
798 | kfree(channel); | |
799 | } | |
800 | } | |
4642610c | 801 | |
7f967c01 | 802 | efx_start_interrupts(efx, true); |
4642610c BH |
803 | efx_start_all(efx); |
804 | return rc; | |
805 | ||
806 | rollback: | |
807 | /* Swap back */ | |
808 | efx->rxq_entries = old_rxq_entries; | |
809 | efx->txq_entries = old_txq_entries; | |
810 | for (i = 0; i < efx->n_channels; i++) { | |
811 | channel = efx->channel[i]; | |
812 | efx->channel[i] = other_channel[i]; | |
813 | other_channel[i] = channel; | |
814 | } | |
815 | goto out; | |
816 | } | |
817 | ||
90d683af | 818 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 819 | { |
90d683af | 820 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
821 | } |
822 | ||
7f967c01 BH |
823 | static const struct efx_channel_type efx_default_channel_type = { |
824 | .pre_probe = efx_channel_dummy_op_int, | |
825 | .get_name = efx_get_channel_name, | |
826 | .copy = efx_copy_channel, | |
827 | .keep_eventq = false, | |
828 | }; | |
829 | ||
830 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
831 | { | |
832 | return 0; | |
833 | } | |
834 | ||
8ceee660 BH |
835 | /************************************************************************** |
836 | * | |
837 | * Port handling | |
838 | * | |
839 | **************************************************************************/ | |
840 | ||
841 | /* This ensures that the kernel is kept informed (via | |
842 | * netif_carrier_on/off) of the link status, and also maintains the | |
843 | * link status's stop on the port's TX queue. | |
844 | */ | |
fdaa9aed | 845 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 846 | { |
eb50c0d6 BH |
847 | struct efx_link_state *link_state = &efx->link_state; |
848 | ||
8ceee660 BH |
849 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
850 | * that no events are triggered between unregister_netdev() and the | |
851 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
852 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
853 | if (!netif_running(efx->net_dev)) | |
854 | return; | |
855 | ||
eb50c0d6 | 856 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
857 | efx->n_link_state_changes++; |
858 | ||
eb50c0d6 | 859 | if (link_state->up) |
8ceee660 BH |
860 | netif_carrier_on(efx->net_dev); |
861 | else | |
862 | netif_carrier_off(efx->net_dev); | |
863 | } | |
864 | ||
865 | /* Status message for kernel log */ | |
2aa9ef11 | 866 | if (link_state->up) |
62776d03 BH |
867 | netif_info(efx, link, efx->net_dev, |
868 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
869 | link_state->speed, link_state->fd ? "full" : "half", | |
870 | efx->net_dev->mtu, | |
871 | (efx->promiscuous ? " [PROMISC]" : "")); | |
2aa9ef11 | 872 | else |
62776d03 | 873 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
874 | } |
875 | ||
d3245b28 BH |
876 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
877 | { | |
878 | efx->link_advertising = advertising; | |
879 | if (advertising) { | |
880 | if (advertising & ADVERTISED_Pause) | |
881 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
882 | else | |
883 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
884 | if (advertising & ADVERTISED_Asym_Pause) | |
885 | efx->wanted_fc ^= EFX_FC_TX; | |
886 | } | |
887 | } | |
888 | ||
b5626946 | 889 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
890 | { |
891 | efx->wanted_fc = wanted_fc; | |
892 | if (efx->link_advertising) { | |
893 | if (wanted_fc & EFX_FC_RX) | |
894 | efx->link_advertising |= (ADVERTISED_Pause | | |
895 | ADVERTISED_Asym_Pause); | |
896 | else | |
897 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
898 | ADVERTISED_Asym_Pause); | |
899 | if (wanted_fc & EFX_FC_TX) | |
900 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
901 | } | |
902 | } | |
903 | ||
115122af BH |
904 | static void efx_fini_port(struct efx_nic *efx); |
905 | ||
d3245b28 BH |
906 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
907 | * the MAC appropriately. All other PHY configuration changes are pushed | |
908 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
909 | * through efx_monitor(). | |
910 | * | |
911 | * Callers must hold the mac_lock | |
912 | */ | |
913 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 914 | { |
d3245b28 BH |
915 | enum efx_phy_mode phy_mode; |
916 | int rc; | |
8ceee660 | 917 | |
d3245b28 | 918 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 919 | |
0fca8c97 | 920 | /* Serialise the promiscuous flag with efx_set_rx_mode. */ |
73ba7b68 BH |
921 | netif_addr_lock_bh(efx->net_dev); |
922 | netif_addr_unlock_bh(efx->net_dev); | |
a816f75a | 923 | |
d3245b28 BH |
924 | /* Disable PHY transmit in mac level loopbacks */ |
925 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
926 | if (LOOPBACK_INTERNAL(efx)) |
927 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
928 | else | |
929 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 930 | |
d3245b28 | 931 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 932 | |
d3245b28 BH |
933 | if (rc) |
934 | efx->phy_mode = phy_mode; | |
177dfcd8 | 935 | |
d3245b28 | 936 | return rc; |
8ceee660 BH |
937 | } |
938 | ||
939 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
940 | * disabled. */ | |
d3245b28 | 941 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 942 | { |
d3245b28 BH |
943 | int rc; |
944 | ||
8ceee660 BH |
945 | EFX_ASSERT_RESET_SERIALISED(efx); |
946 | ||
947 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 948 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 949 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
950 | |
951 | return rc; | |
8ceee660 BH |
952 | } |
953 | ||
8be4f3e6 BH |
954 | /* Asynchronous work item for changing MAC promiscuity and multicast |
955 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
956 | * MAC directly. */ | |
766ca0fa BH |
957 | static void efx_mac_work(struct work_struct *data) |
958 | { | |
959 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
960 | ||
961 | mutex_lock(&efx->mac_lock); | |
30b81cda | 962 | if (efx->port_enabled) |
710b208d | 963 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
964 | mutex_unlock(&efx->mac_lock); |
965 | } | |
966 | ||
8ceee660 BH |
967 | static int efx_probe_port(struct efx_nic *efx) |
968 | { | |
969 | int rc; | |
970 | ||
62776d03 | 971 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 972 | |
ff3b00a0 SH |
973 | if (phy_flash_cfg) |
974 | efx->phy_mode = PHY_MODE_SPECIAL; | |
975 | ||
ef2b90ee BH |
976 | /* Connect up MAC/PHY operations table */ |
977 | rc = efx->type->probe_port(efx); | |
8ceee660 | 978 | if (rc) |
e42de262 | 979 | return rc; |
8ceee660 | 980 | |
e332bcb3 BH |
981 | /* Initialise MAC address to permanent address */ |
982 | memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); | |
8ceee660 BH |
983 | |
984 | return 0; | |
8ceee660 BH |
985 | } |
986 | ||
987 | static int efx_init_port(struct efx_nic *efx) | |
988 | { | |
989 | int rc; | |
990 | ||
62776d03 | 991 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 992 | |
1dfc5cea BH |
993 | mutex_lock(&efx->mac_lock); |
994 | ||
177dfcd8 | 995 | rc = efx->phy_op->init(efx); |
8ceee660 | 996 | if (rc) |
1dfc5cea | 997 | goto fail1; |
8ceee660 | 998 | |
dc8cfa55 | 999 | efx->port_initialized = true; |
1dfc5cea | 1000 | |
d3245b28 BH |
1001 | /* Reconfigure the MAC before creating dma queues (required for |
1002 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 1003 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1004 | |
1005 | /* Ensure the PHY advertises the correct flow control settings */ | |
1006 | rc = efx->phy_op->reconfigure(efx); | |
1007 | if (rc) | |
1008 | goto fail2; | |
1009 | ||
1dfc5cea | 1010 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1011 | return 0; |
177dfcd8 | 1012 | |
1dfc5cea | 1013 | fail2: |
177dfcd8 | 1014 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1015 | fail1: |
1016 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1017 | return rc; |
8ceee660 BH |
1018 | } |
1019 | ||
8ceee660 BH |
1020 | static void efx_start_port(struct efx_nic *efx) |
1021 | { | |
62776d03 | 1022 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1023 | BUG_ON(efx->port_enabled); |
1024 | ||
1025 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1026 | efx->port_enabled = true; |
8be4f3e6 BH |
1027 | |
1028 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
1029 | * and then cancelled by efx_flush_all() */ | |
710b208d | 1030 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 1031 | |
8ceee660 BH |
1032 | mutex_unlock(&efx->mac_lock); |
1033 | } | |
1034 | ||
fdaa9aed | 1035 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
1036 | static void efx_stop_port(struct efx_nic *efx) |
1037 | { | |
62776d03 | 1038 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
1039 | |
1040 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1041 | efx->port_enabled = false; |
8ceee660 BH |
1042 | mutex_unlock(&efx->mac_lock); |
1043 | ||
1044 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1045 | netif_addr_lock_bh(efx->net_dev); |
1046 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
1047 | } |
1048 | ||
1049 | static void efx_fini_port(struct efx_nic *efx) | |
1050 | { | |
62776d03 | 1051 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1052 | |
1053 | if (!efx->port_initialized) | |
1054 | return; | |
1055 | ||
177dfcd8 | 1056 | efx->phy_op->fini(efx); |
dc8cfa55 | 1057 | efx->port_initialized = false; |
8ceee660 | 1058 | |
eb50c0d6 | 1059 | efx->link_state.up = false; |
8ceee660 BH |
1060 | efx_link_status_changed(efx); |
1061 | } | |
1062 | ||
1063 | static void efx_remove_port(struct efx_nic *efx) | |
1064 | { | |
62776d03 | 1065 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1066 | |
ef2b90ee | 1067 | efx->type->remove_port(efx); |
8ceee660 BH |
1068 | } |
1069 | ||
1070 | /************************************************************************** | |
1071 | * | |
1072 | * NIC handling | |
1073 | * | |
1074 | **************************************************************************/ | |
1075 | ||
1076 | /* This configures the PCI device to enable I/O and DMA. */ | |
1077 | static int efx_init_io(struct efx_nic *efx) | |
1078 | { | |
1079 | struct pci_dev *pci_dev = efx->pci_dev; | |
1080 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
1081 | int rc; | |
1082 | ||
62776d03 | 1083 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1084 | |
1085 | rc = pci_enable_device(pci_dev); | |
1086 | if (rc) { | |
62776d03 BH |
1087 | netif_err(efx, probe, efx->net_dev, |
1088 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1089 | goto fail1; |
1090 | } | |
1091 | ||
1092 | pci_set_master(pci_dev); | |
1093 | ||
1094 | /* Set the PCI DMA mask. Try all possibilities from our | |
1095 | * genuine mask down to 32 bits, because some architectures | |
1096 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1097 | * masks event though they reject 46 bit masks. | |
1098 | */ | |
1099 | while (dma_mask > 0x7fffffffUL) { | |
e9e01846 BH |
1100 | if (pci_dma_supported(pci_dev, dma_mask)) { |
1101 | rc = pci_set_dma_mask(pci_dev, dma_mask); | |
1102 | if (rc == 0) | |
1103 | break; | |
1104 | } | |
8ceee660 BH |
1105 | dma_mask >>= 1; |
1106 | } | |
1107 | if (rc) { | |
62776d03 BH |
1108 | netif_err(efx, probe, efx->net_dev, |
1109 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1110 | goto fail2; |
1111 | } | |
62776d03 BH |
1112 | netif_dbg(efx, probe, efx->net_dev, |
1113 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 BH |
1114 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); |
1115 | if (rc) { | |
1116 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
1117 | * fail with a mask that pci_set_dma_mask() accepted, | |
1118 | * but just in case... | |
1119 | */ | |
62776d03 BH |
1120 | netif_err(efx, probe, efx->net_dev, |
1121 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1122 | goto fail2; |
1123 | } | |
1124 | ||
dc803df8 BH |
1125 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1126 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1127 | if (rc) { |
62776d03 BH |
1128 | netif_err(efx, probe, efx->net_dev, |
1129 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1130 | rc = -EIO; |
1131 | goto fail3; | |
1132 | } | |
86c432ca BH |
1133 | efx->membase = ioremap_nocache(efx->membase_phys, |
1134 | efx->type->mem_map_size); | |
8ceee660 | 1135 | if (!efx->membase) { |
62776d03 BH |
1136 | netif_err(efx, probe, efx->net_dev, |
1137 | "could not map memory BAR at %llx+%x\n", | |
1138 | (unsigned long long)efx->membase_phys, | |
1139 | efx->type->mem_map_size); | |
8ceee660 BH |
1140 | rc = -ENOMEM; |
1141 | goto fail4; | |
1142 | } | |
62776d03 BH |
1143 | netif_dbg(efx, probe, efx->net_dev, |
1144 | "memory BAR at %llx+%x (virtual %p)\n", | |
1145 | (unsigned long long)efx->membase_phys, | |
1146 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1147 | |
1148 | return 0; | |
1149 | ||
1150 | fail4: | |
dc803df8 | 1151 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1152 | fail3: |
2c118e0f | 1153 | efx->membase_phys = 0; |
8ceee660 BH |
1154 | fail2: |
1155 | pci_disable_device(efx->pci_dev); | |
1156 | fail1: | |
1157 | return rc; | |
1158 | } | |
1159 | ||
1160 | static void efx_fini_io(struct efx_nic *efx) | |
1161 | { | |
62776d03 | 1162 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1163 | |
1164 | if (efx->membase) { | |
1165 | iounmap(efx->membase); | |
1166 | efx->membase = NULL; | |
1167 | } | |
1168 | ||
1169 | if (efx->membase_phys) { | |
dc803df8 | 1170 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1171 | efx->membase_phys = 0; |
8ceee660 BH |
1172 | } |
1173 | ||
1174 | pci_disable_device(efx->pci_dev); | |
1175 | } | |
1176 | ||
a9a52506 | 1177 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1178 | { |
cdb08f8f | 1179 | cpumask_var_t thread_mask; |
a16e5b24 | 1180 | unsigned int count; |
46123d04 | 1181 | int cpu; |
5b874e25 | 1182 | |
cd2d5b52 BH |
1183 | if (rss_cpus) { |
1184 | count = rss_cpus; | |
1185 | } else { | |
1186 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1187 | netif_warn(efx, probe, efx->net_dev, | |
1188 | "RSS disabled due to allocation failure\n"); | |
1189 | return 1; | |
1190 | } | |
46123d04 | 1191 | |
cd2d5b52 BH |
1192 | count = 0; |
1193 | for_each_online_cpu(cpu) { | |
1194 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1195 | ++count; | |
1196 | cpumask_or(thread_mask, thread_mask, | |
1197 | topology_thread_cpumask(cpu)); | |
1198 | } | |
1199 | } | |
1200 | ||
1201 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1202 | } |
1203 | ||
cd2d5b52 BH |
1204 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1205 | * table entries that are inaccessible to VFs | |
1206 | */ | |
1207 | if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1208 | count > efx_vf_size(efx)) { | |
1209 | netif_warn(efx, probe, efx->net_dev, | |
1210 | "Reducing number of RSS channels from %u to %u for " | |
1211 | "VF support. Increase vf-msix-limit to use more " | |
1212 | "channels on the PF.\n", | |
1213 | count, efx_vf_size(efx)); | |
1214 | count = efx_vf_size(efx); | |
46123d04 BH |
1215 | } |
1216 | ||
1217 | return count; | |
1218 | } | |
1219 | ||
64d8ad6d BH |
1220 | static int |
1221 | efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) | |
1222 | { | |
1223 | #ifdef CONFIG_RFS_ACCEL | |
a16e5b24 BH |
1224 | unsigned int i; |
1225 | int rc; | |
64d8ad6d BH |
1226 | |
1227 | efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); | |
1228 | if (!efx->net_dev->rx_cpu_rmap) | |
1229 | return -ENOMEM; | |
1230 | for (i = 0; i < efx->n_rx_channels; i++) { | |
1231 | rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, | |
1232 | xentries[i].vector); | |
1233 | if (rc) { | |
1234 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
1235 | efx->net_dev->rx_cpu_rmap = NULL; | |
1236 | return rc; | |
1237 | } | |
1238 | } | |
1239 | #endif | |
1240 | return 0; | |
1241 | } | |
1242 | ||
46123d04 BH |
1243 | /* Probe the number and type of interrupts we are able to obtain, and |
1244 | * the resulting numbers of channels and RX queues. | |
1245 | */ | |
64d8ad6d | 1246 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1247 | { |
a16e5b24 BH |
1248 | unsigned int max_channels = |
1249 | min(efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
7f967c01 BH |
1250 | unsigned int extra_channels = 0; |
1251 | unsigned int i, j; | |
a16e5b24 | 1252 | int rc; |
8ceee660 | 1253 | |
7f967c01 BH |
1254 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1255 | if (efx->extra_channel_type[i]) | |
1256 | ++extra_channels; | |
1257 | ||
8ceee660 | 1258 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1259 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1260 | unsigned int n_channels; |
aa6ef27e | 1261 | |
a9a52506 | 1262 | n_channels = efx_wanted_parallelism(efx); |
a4900ac9 BH |
1263 | if (separate_tx_channels) |
1264 | n_channels *= 2; | |
7f967c01 | 1265 | n_channels += extra_channels; |
a4900ac9 | 1266 | n_channels = min(n_channels, max_channels); |
8ceee660 | 1267 | |
a4900ac9 | 1268 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1269 | xentries[i].entry = i; |
a4900ac9 | 1270 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1271 | if (rc > 0) { |
62776d03 BH |
1272 | netif_err(efx, drv, efx->net_dev, |
1273 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1274 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1275 | netif_err(efx, drv, efx->net_dev, |
1276 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1277 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1278 | n_channels = rc; | |
8ceee660 | 1279 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1280 | n_channels); |
8ceee660 BH |
1281 | } |
1282 | ||
1283 | if (rc == 0) { | |
a4900ac9 | 1284 | efx->n_channels = n_channels; |
7f967c01 BH |
1285 | if (n_channels > extra_channels) |
1286 | n_channels -= extra_channels; | |
a4900ac9 | 1287 | if (separate_tx_channels) { |
7f967c01 BH |
1288 | efx->n_tx_channels = max(n_channels / 2, 1U); |
1289 | efx->n_rx_channels = max(n_channels - | |
1290 | efx->n_tx_channels, | |
1291 | 1U); | |
a4900ac9 | 1292 | } else { |
7f967c01 BH |
1293 | efx->n_tx_channels = n_channels; |
1294 | efx->n_rx_channels = n_channels; | |
a4900ac9 | 1295 | } |
64d8ad6d BH |
1296 | rc = efx_init_rx_cpu_rmap(efx, xentries); |
1297 | if (rc) { | |
1298 | pci_disable_msix(efx->pci_dev); | |
1299 | return rc; | |
1300 | } | |
7f967c01 | 1301 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1302 | efx_get_channel(efx, i)->irq = |
1303 | xentries[i].vector; | |
8ceee660 BH |
1304 | } else { |
1305 | /* Fall back to single channel MSI */ | |
1306 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1307 | netif_err(efx, drv, efx->net_dev, |
1308 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1309 | } |
1310 | } | |
1311 | ||
1312 | /* Try single interrupt MSI */ | |
1313 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1314 | efx->n_channels = 1; |
a4900ac9 BH |
1315 | efx->n_rx_channels = 1; |
1316 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1317 | rc = pci_enable_msi(efx->pci_dev); |
1318 | if (rc == 0) { | |
f7d12cdc | 1319 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1320 | } else { |
62776d03 BH |
1321 | netif_err(efx, drv, efx->net_dev, |
1322 | "could not enable MSI\n"); | |
8ceee660 BH |
1323 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1324 | } | |
1325 | } | |
1326 | ||
1327 | /* Assume legacy interrupts */ | |
1328 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1329 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1330 | efx->n_rx_channels = 1; |
1331 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1332 | efx->legacy_irq = efx->pci_dev->irq; |
1333 | } | |
64d8ad6d | 1334 | |
7f967c01 BH |
1335 | /* Assign extra channels if possible */ |
1336 | j = efx->n_channels; | |
1337 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1338 | if (!efx->extra_channel_type[i]) | |
1339 | continue; | |
1340 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1341 | efx->n_channels <= extra_channels) { | |
1342 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1343 | } else { | |
1344 | --j; | |
1345 | efx_get_channel(efx, j)->type = | |
1346 | efx->extra_channel_type[i]; | |
1347 | } | |
1348 | } | |
1349 | ||
cd2d5b52 BH |
1350 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
1351 | efx->rss_spread = (efx->n_rx_channels > 1 ? | |
1352 | efx->n_rx_channels : efx_vf_size(efx)); | |
1353 | ||
64d8ad6d | 1354 | return 0; |
8ceee660 BH |
1355 | } |
1356 | ||
9f2cb71c | 1357 | /* Enable interrupts, then probe and start the event queues */ |
7f967c01 | 1358 | static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq) |
9f2cb71c BH |
1359 | { |
1360 | struct efx_channel *channel; | |
1361 | ||
1362 | if (efx->legacy_irq) | |
1363 | efx->legacy_irq_enabled = true; | |
1364 | efx_nic_enable_interrupts(efx); | |
1365 | ||
1366 | efx_for_each_channel(channel, efx) { | |
7f967c01 BH |
1367 | if (!channel->type->keep_eventq || !may_keep_eventq) |
1368 | efx_init_eventq(channel); | |
9f2cb71c BH |
1369 | efx_start_eventq(channel); |
1370 | } | |
1371 | ||
1372 | efx_mcdi_mode_event(efx); | |
1373 | } | |
1374 | ||
7f967c01 | 1375 | static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq) |
9f2cb71c BH |
1376 | { |
1377 | struct efx_channel *channel; | |
1378 | ||
1379 | efx_mcdi_mode_poll(efx); | |
1380 | ||
1381 | efx_nic_disable_interrupts(efx); | |
1382 | if (efx->legacy_irq) { | |
1383 | synchronize_irq(efx->legacy_irq); | |
1384 | efx->legacy_irq_enabled = false; | |
1385 | } | |
1386 | ||
1387 | efx_for_each_channel(channel, efx) { | |
1388 | if (channel->irq) | |
1389 | synchronize_irq(channel->irq); | |
1390 | ||
1391 | efx_stop_eventq(channel); | |
7f967c01 BH |
1392 | if (!channel->type->keep_eventq || !may_keep_eventq) |
1393 | efx_fini_eventq(channel); | |
9f2cb71c BH |
1394 | } |
1395 | } | |
1396 | ||
8ceee660 BH |
1397 | static void efx_remove_interrupts(struct efx_nic *efx) |
1398 | { | |
1399 | struct efx_channel *channel; | |
1400 | ||
1401 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1402 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1403 | channel->irq = 0; |
1404 | pci_disable_msi(efx->pci_dev); | |
1405 | pci_disable_msix(efx->pci_dev); | |
1406 | ||
1407 | /* Remove legacy interrupt */ | |
1408 | efx->legacy_irq = 0; | |
1409 | } | |
1410 | ||
8831da7b | 1411 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1412 | { |
602a5322 BH |
1413 | struct efx_channel *channel; |
1414 | struct efx_tx_queue *tx_queue; | |
1415 | ||
97653431 | 1416 | efx->tx_channel_offset = |
a4900ac9 | 1417 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 BH |
1418 | |
1419 | /* We need to adjust the TX queue numbers if we have separate | |
1420 | * RX-only and TX-only channels. | |
1421 | */ | |
1422 | efx_for_each_channel(channel, efx) { | |
1423 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1424 | tx_queue->queue -= (efx->tx_channel_offset * | |
1425 | EFX_TXQ_TYPES); | |
1426 | } | |
8ceee660 BH |
1427 | } |
1428 | ||
1429 | static int efx_probe_nic(struct efx_nic *efx) | |
1430 | { | |
765c9f46 | 1431 | size_t i; |
8ceee660 BH |
1432 | int rc; |
1433 | ||
62776d03 | 1434 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1435 | |
1436 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1437 | rc = efx->type->probe(efx); |
8ceee660 BH |
1438 | if (rc) |
1439 | return rc; | |
1440 | ||
a4900ac9 | 1441 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1442 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1443 | rc = efx_probe_interrupts(efx); |
1444 | if (rc) | |
1445 | goto fail; | |
8ceee660 | 1446 | |
28e47c49 BH |
1447 | efx->type->dimension_resources(efx); |
1448 | ||
5d3a6fca BH |
1449 | if (efx->n_channels > 1) |
1450 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1451 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 | 1452 | efx->rx_indir_table[i] = |
cd2d5b52 | 1453 | ethtool_rxfh_indir_default(i, efx->rss_spread); |
5d3a6fca | 1454 | |
8831da7b | 1455 | efx_set_channels(efx); |
c4f4adc7 BH |
1456 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1457 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1458 | |
1459 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1460 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1461 | true); | |
8ceee660 BH |
1462 | |
1463 | return 0; | |
64d8ad6d BH |
1464 | |
1465 | fail: | |
1466 | efx->type->remove(efx); | |
1467 | return rc; | |
8ceee660 BH |
1468 | } |
1469 | ||
1470 | static void efx_remove_nic(struct efx_nic *efx) | |
1471 | { | |
62776d03 | 1472 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1473 | |
1474 | efx_remove_interrupts(efx); | |
ef2b90ee | 1475 | efx->type->remove(efx); |
8ceee660 BH |
1476 | } |
1477 | ||
1478 | /************************************************************************** | |
1479 | * | |
1480 | * NIC startup/shutdown | |
1481 | * | |
1482 | *************************************************************************/ | |
1483 | ||
1484 | static int efx_probe_all(struct efx_nic *efx) | |
1485 | { | |
8ceee660 BH |
1486 | int rc; |
1487 | ||
8ceee660 BH |
1488 | rc = efx_probe_nic(efx); |
1489 | if (rc) { | |
62776d03 | 1490 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1491 | goto fail1; |
1492 | } | |
1493 | ||
8ceee660 BH |
1494 | rc = efx_probe_port(efx); |
1495 | if (rc) { | |
62776d03 | 1496 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1497 | goto fail2; |
1498 | } | |
1499 | ||
ecc910f5 | 1500 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1501 | |
64eebcfd BH |
1502 | rc = efx_probe_filters(efx); |
1503 | if (rc) { | |
1504 | netif_err(efx, probe, efx->net_dev, | |
1505 | "failed to create filter tables\n"); | |
7f967c01 | 1506 | goto fail3; |
64eebcfd BH |
1507 | } |
1508 | ||
7f967c01 BH |
1509 | rc = efx_probe_channels(efx); |
1510 | if (rc) | |
1511 | goto fail4; | |
1512 | ||
8ceee660 BH |
1513 | return 0; |
1514 | ||
64eebcfd | 1515 | fail4: |
7f967c01 | 1516 | efx_remove_filters(efx); |
8ceee660 | 1517 | fail3: |
8ceee660 BH |
1518 | efx_remove_port(efx); |
1519 | fail2: | |
1520 | efx_remove_nic(efx); | |
1521 | fail1: | |
1522 | return rc; | |
1523 | } | |
1524 | ||
9f2cb71c BH |
1525 | /* Called after previous invocation(s) of efx_stop_all, restarts the port, |
1526 | * kernel transmit queues and NAPI processing, and ensures that the port is | |
1527 | * scheduled to be reconfigured. This function is safe to call multiple | |
1528 | * times when the NIC is in any state. | |
1529 | */ | |
8ceee660 BH |
1530 | static void efx_start_all(struct efx_nic *efx) |
1531 | { | |
8ceee660 BH |
1532 | EFX_ASSERT_RESET_SERIALISED(efx); |
1533 | ||
1534 | /* Check that it is appropriate to restart the interface. All | |
1535 | * of these flags are safe to read under just the rtnl lock */ | |
1536 | if (efx->port_enabled) | |
1537 | return; | |
1538 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1539 | return; | |
73ba7b68 | 1540 | if (!netif_running(efx->net_dev)) |
8ceee660 BH |
1541 | return; |
1542 | ||
8ceee660 | 1543 | efx_start_port(efx); |
9f2cb71c | 1544 | efx_start_datapath(efx); |
8880f4ec | 1545 | |
78c1f0a0 SH |
1546 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1547 | * event driven), we have to poll the PHY because after an event queue | |
1548 | * flush, we could have a missed a link state change */ | |
1549 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1550 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1551 | efx_monitor_interval); | |
78c1f0a0 SH |
1552 | } else { |
1553 | mutex_lock(&efx->mac_lock); | |
1554 | if (efx->phy_op->poll(efx)) | |
1555 | efx_link_status_changed(efx); | |
1556 | mutex_unlock(&efx->mac_lock); | |
1557 | } | |
55edc6e6 | 1558 | |
ef2b90ee | 1559 | efx->type->start_stats(efx); |
8ceee660 BH |
1560 | } |
1561 | ||
1562 | /* Flush all delayed work. Should only be called when no more delayed work | |
1563 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1564 | * since we're holding the rtnl_lock at this point. */ | |
1565 | static void efx_flush_all(struct efx_nic *efx) | |
1566 | { | |
8ceee660 BH |
1567 | /* Make sure the hardware monitor is stopped */ |
1568 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1569 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1570 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1571 | } |
1572 | ||
1573 | /* Quiesce hardware and software without bringing the link down. | |
1574 | * Safe to call multiple times, when the nic and interface is in any | |
1575 | * state. The caller is guaranteed to subsequently be in a position | |
1576 | * to modify any hardware and software state they see fit without | |
1577 | * taking locks. */ | |
1578 | static void efx_stop_all(struct efx_nic *efx) | |
1579 | { | |
8ceee660 BH |
1580 | EFX_ASSERT_RESET_SERIALISED(efx); |
1581 | ||
1582 | /* port_enabled can be read safely under the rtnl lock */ | |
1583 | if (!efx->port_enabled) | |
1584 | return; | |
1585 | ||
ef2b90ee | 1586 | efx->type->stop_stats(efx); |
8ceee660 BH |
1587 | efx_stop_port(efx); |
1588 | ||
fdaa9aed | 1589 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1590 | efx_flush_all(efx); |
1591 | ||
8ceee660 BH |
1592 | /* Stop the kernel transmit interface late, so the watchdog |
1593 | * timer isn't ticking over the flush */ | |
9f2cb71c BH |
1594 | netif_tx_disable(efx->net_dev); |
1595 | ||
1596 | efx_stop_datapath(efx); | |
8ceee660 BH |
1597 | } |
1598 | ||
1599 | static void efx_remove_all(struct efx_nic *efx) | |
1600 | { | |
4642610c | 1601 | efx_remove_channels(efx); |
7f967c01 | 1602 | efx_remove_filters(efx); |
8ceee660 BH |
1603 | efx_remove_port(efx); |
1604 | efx_remove_nic(efx); | |
1605 | } | |
1606 | ||
8ceee660 BH |
1607 | /************************************************************************** |
1608 | * | |
1609 | * Interrupt moderation | |
1610 | * | |
1611 | **************************************************************************/ | |
1612 | ||
cc180b69 | 1613 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1614 | { |
b548f976 BH |
1615 | if (usecs == 0) |
1616 | return 0; | |
cc180b69 | 1617 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1618 | return 1; /* never round down to 0 */ |
cc180b69 | 1619 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1620 | } |
1621 | ||
8ceee660 | 1622 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1623 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1624 | unsigned int rx_usecs, bool rx_adaptive, | |
1625 | bool rx_may_override_tx) | |
8ceee660 | 1626 | { |
f7d12cdc | 1627 | struct efx_channel *channel; |
cc180b69 BH |
1628 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1629 | efx->timer_quantum_ns, | |
1630 | 1000); | |
1631 | unsigned int tx_ticks; | |
1632 | unsigned int rx_ticks; | |
8ceee660 BH |
1633 | |
1634 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1635 | ||
cc180b69 | 1636 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1637 | return -EINVAL; |
1638 | ||
cc180b69 BH |
1639 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1640 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1641 | ||
9e393b30 BH |
1642 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1643 | !rx_may_override_tx) { | |
1644 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1645 | "RX and TX IRQ moderation must be equal\n"); | |
1646 | return -EINVAL; | |
1647 | } | |
1648 | ||
6fb70fd1 | 1649 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1650 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1651 | efx_for_each_channel(channel, efx) { |
525da907 | 1652 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1653 | channel->irq_moderation = rx_ticks; |
525da907 | 1654 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1655 | channel->irq_moderation = tx_ticks; |
1656 | } | |
9e393b30 BH |
1657 | |
1658 | return 0; | |
8ceee660 BH |
1659 | } |
1660 | ||
a0c4faf5 BH |
1661 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1662 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1663 | { | |
cc180b69 BH |
1664 | /* We must round up when converting ticks to microseconds |
1665 | * because we round down when converting the other way. | |
1666 | */ | |
1667 | ||
a0c4faf5 | 1668 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1669 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1670 | efx->timer_quantum_ns, | |
1671 | 1000); | |
a0c4faf5 BH |
1672 | |
1673 | /* If channels are shared between RX and TX, so is IRQ | |
1674 | * moderation. Otherwise, IRQ moderation is the same for all | |
1675 | * TX channels and is not adaptive. | |
1676 | */ | |
1677 | if (efx->tx_channel_offset == 0) | |
1678 | *tx_usecs = *rx_usecs; | |
1679 | else | |
cc180b69 | 1680 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1681 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1682 | efx->timer_quantum_ns, |
1683 | 1000); | |
a0c4faf5 BH |
1684 | } |
1685 | ||
8ceee660 BH |
1686 | /************************************************************************** |
1687 | * | |
1688 | * Hardware monitor | |
1689 | * | |
1690 | **************************************************************************/ | |
1691 | ||
e254c274 | 1692 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1693 | static void efx_monitor(struct work_struct *data) |
1694 | { | |
1695 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1696 | monitor_work.work); | |
8ceee660 | 1697 | |
62776d03 BH |
1698 | netif_vdbg(efx, timer, efx->net_dev, |
1699 | "hardware monitor executing on CPU %d\n", | |
1700 | raw_smp_processor_id()); | |
ef2b90ee | 1701 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1702 | |
8ceee660 BH |
1703 | /* If the mac_lock is already held then it is likely a port |
1704 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1705 | * most of the work of monitor() anyway. */ |
1706 | if (mutex_trylock(&efx->mac_lock)) { | |
1707 | if (efx->port_enabled) | |
1708 | efx->type->monitor(efx); | |
1709 | mutex_unlock(&efx->mac_lock); | |
1710 | } | |
8ceee660 | 1711 | |
8ceee660 BH |
1712 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1713 | efx_monitor_interval); | |
1714 | } | |
1715 | ||
1716 | /************************************************************************** | |
1717 | * | |
1718 | * ioctls | |
1719 | * | |
1720 | *************************************************************************/ | |
1721 | ||
1722 | /* Net device ioctl | |
1723 | * Context: process, rtnl_lock() held. | |
1724 | */ | |
1725 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1726 | { | |
767e468c | 1727 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1728 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1729 | |
1730 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1731 | ||
68e7f45e BH |
1732 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1733 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1734 | (data->phy_id & 0xfc00) == 0x0400) | |
1735 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1736 | ||
1737 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1738 | } |
1739 | ||
1740 | /************************************************************************** | |
1741 | * | |
1742 | * NAPI interface | |
1743 | * | |
1744 | **************************************************************************/ | |
1745 | ||
7f967c01 BH |
1746 | static void efx_init_napi_channel(struct efx_channel *channel) |
1747 | { | |
1748 | struct efx_nic *efx = channel->efx; | |
1749 | ||
1750 | channel->napi_dev = efx->net_dev; | |
1751 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
1752 | efx_poll, napi_weight); | |
1753 | } | |
1754 | ||
e8f14992 | 1755 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1756 | { |
1757 | struct efx_channel *channel; | |
8ceee660 | 1758 | |
7f967c01 BH |
1759 | efx_for_each_channel(channel, efx) |
1760 | efx_init_napi_channel(channel); | |
e8f14992 BH |
1761 | } |
1762 | ||
1763 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1764 | { | |
1765 | if (channel->napi_dev) | |
1766 | netif_napi_del(&channel->napi_str); | |
1767 | channel->napi_dev = NULL; | |
8ceee660 BH |
1768 | } |
1769 | ||
1770 | static void efx_fini_napi(struct efx_nic *efx) | |
1771 | { | |
1772 | struct efx_channel *channel; | |
1773 | ||
e8f14992 BH |
1774 | efx_for_each_channel(channel, efx) |
1775 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1776 | } |
1777 | ||
1778 | /************************************************************************** | |
1779 | * | |
1780 | * Kernel netpoll interface | |
1781 | * | |
1782 | *************************************************************************/ | |
1783 | ||
1784 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1785 | ||
1786 | /* Although in the common case interrupts will be disabled, this is not | |
1787 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1788 | * so no locking is required. | |
1789 | */ | |
1790 | static void efx_netpoll(struct net_device *net_dev) | |
1791 | { | |
767e468c | 1792 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1793 | struct efx_channel *channel; |
1794 | ||
64ee3120 | 1795 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1796 | efx_schedule_channel(channel); |
1797 | } | |
1798 | ||
1799 | #endif | |
1800 | ||
1801 | /************************************************************************** | |
1802 | * | |
1803 | * Kernel net device interface | |
1804 | * | |
1805 | *************************************************************************/ | |
1806 | ||
1807 | /* Context: process, rtnl_lock() held. */ | |
1808 | static int efx_net_open(struct net_device *net_dev) | |
1809 | { | |
767e468c | 1810 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1811 | EFX_ASSERT_RESET_SERIALISED(efx); |
1812 | ||
62776d03 BH |
1813 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1814 | raw_smp_processor_id()); | |
8ceee660 | 1815 | |
f4bd954e BH |
1816 | if (efx->state == STATE_DISABLED) |
1817 | return -EIO; | |
f8b87c17 BH |
1818 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1819 | return -EBUSY; | |
8880f4ec BH |
1820 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1821 | return -EIO; | |
f8b87c17 | 1822 | |
78c1f0a0 SH |
1823 | /* Notify the kernel of the link state polled during driver load, |
1824 | * before the monitor starts running */ | |
1825 | efx_link_status_changed(efx); | |
1826 | ||
8ceee660 BH |
1827 | efx_start_all(efx); |
1828 | return 0; | |
1829 | } | |
1830 | ||
1831 | /* Context: process, rtnl_lock() held. | |
1832 | * Note that the kernel will ignore our return code; this method | |
1833 | * should really be a void. | |
1834 | */ | |
1835 | static int efx_net_stop(struct net_device *net_dev) | |
1836 | { | |
767e468c | 1837 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1838 | |
62776d03 BH |
1839 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1840 | raw_smp_processor_id()); | |
8ceee660 | 1841 | |
f4bd954e BH |
1842 | if (efx->state != STATE_DISABLED) { |
1843 | /* Stop the device and flush all the channels */ | |
1844 | efx_stop_all(efx); | |
f4bd954e | 1845 | } |
8ceee660 BH |
1846 | |
1847 | return 0; | |
1848 | } | |
1849 | ||
5b9e207c | 1850 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
1851 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
1852 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 1853 | { |
767e468c | 1854 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1855 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1856 | |
55edc6e6 | 1857 | spin_lock_bh(&efx->stats_lock); |
1cb34522 | 1858 | |
ef2b90ee | 1859 | efx->type->update_stats(efx); |
8ceee660 BH |
1860 | |
1861 | stats->rx_packets = mac_stats->rx_packets; | |
1862 | stats->tx_packets = mac_stats->tx_packets; | |
1863 | stats->rx_bytes = mac_stats->rx_bytes; | |
1864 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1865 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1866 | stats->multicast = mac_stats->rx_multicast; |
1867 | stats->collisions = mac_stats->tx_collision; | |
1868 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1869 | mac_stats->rx_length_error); | |
8ceee660 BH |
1870 | stats->rx_crc_errors = mac_stats->rx_bad; |
1871 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1872 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1873 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1874 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1875 | ||
1876 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1877 | stats->rx_crc_errors + |
1878 | stats->rx_frame_errors + | |
8ceee660 BH |
1879 | mac_stats->rx_symbol_error); |
1880 | stats->tx_errors = (stats->tx_window_errors + | |
1881 | mac_stats->tx_bad); | |
1882 | ||
1cb34522 BH |
1883 | spin_unlock_bh(&efx->stats_lock); |
1884 | ||
8ceee660 BH |
1885 | return stats; |
1886 | } | |
1887 | ||
1888 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1889 | static void efx_watchdog(struct net_device *net_dev) | |
1890 | { | |
767e468c | 1891 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1892 | |
62776d03 BH |
1893 | netif_err(efx, tx_err, efx->net_dev, |
1894 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1895 | efx->port_enabled); | |
8ceee660 | 1896 | |
739bb23d | 1897 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1898 | } |
1899 | ||
1900 | ||
1901 | /* Context: process, rtnl_lock() held. */ | |
1902 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1903 | { | |
767e468c | 1904 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1905 | |
1906 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1907 | ||
1908 | if (new_mtu > EFX_MAX_MTU) | |
1909 | return -EINVAL; | |
1910 | ||
1911 | efx_stop_all(efx); | |
1912 | ||
62776d03 | 1913 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 1914 | |
d3245b28 BH |
1915 | mutex_lock(&efx->mac_lock); |
1916 | /* Reconfigure the MAC before enabling the dma queues so that | |
1917 | * the RX buffers don't overflow */ | |
8ceee660 | 1918 | net_dev->mtu = new_mtu; |
710b208d | 1919 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1920 | mutex_unlock(&efx->mac_lock); |
1921 | ||
8ceee660 | 1922 | efx_start_all(efx); |
6c8eef4a | 1923 | return 0; |
8ceee660 BH |
1924 | } |
1925 | ||
1926 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1927 | { | |
767e468c | 1928 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1929 | struct sockaddr *addr = data; |
1930 | char *new_addr = addr->sa_data; | |
1931 | ||
1932 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1933 | ||
1934 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1935 | netif_err(efx, drv, efx->net_dev, |
1936 | "invalid ethernet MAC address requested: %pM\n", | |
1937 | new_addr); | |
8ceee660 BH |
1938 | return -EINVAL; |
1939 | } | |
1940 | ||
1941 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
cd2d5b52 | 1942 | efx_sriov_mac_address_changed(efx); |
8ceee660 BH |
1943 | |
1944 | /* Reconfigure the MAC */ | |
d3245b28 | 1945 | mutex_lock(&efx->mac_lock); |
710b208d | 1946 | efx->type->reconfigure_mac(efx); |
d3245b28 | 1947 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
1948 | |
1949 | return 0; | |
1950 | } | |
1951 | ||
a816f75a | 1952 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 1953 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 1954 | { |
767e468c | 1955 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1956 | struct netdev_hw_addr *ha; |
8ceee660 | 1957 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1958 | u32 crc; |
1959 | int bit; | |
8ceee660 | 1960 | |
8be4f3e6 | 1961 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1962 | |
1963 | /* Build multicast hash table */ | |
8be4f3e6 | 1964 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1965 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1966 | } else { | |
1967 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1968 | netdev_for_each_mc_addr(ha, net_dev) { |
1969 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1970 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1971 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1972 | } |
8ceee660 | 1973 | |
8be4f3e6 BH |
1974 | /* Broadcast packets go through the multicast hash filter. |
1975 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1976 | * so we always add bit 0xff to the mask. | |
1977 | */ | |
1978 | set_bit_le(0xff, mc_hash->byte); | |
1979 | } | |
a816f75a | 1980 | |
8be4f3e6 BH |
1981 | if (efx->port_enabled) |
1982 | queue_work(efx->workqueue, &efx->mac_work); | |
1983 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1984 | } |
1985 | ||
c8f44aff | 1986 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
1987 | { |
1988 | struct efx_nic *efx = netdev_priv(net_dev); | |
1989 | ||
1990 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
1991 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
1992 | efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
1993 | ||
1994 | return 0; | |
1995 | } | |
1996 | ||
c3ecb9f3 SH |
1997 | static const struct net_device_ops efx_netdev_ops = { |
1998 | .ndo_open = efx_net_open, | |
1999 | .ndo_stop = efx_net_stop, | |
4472702e | 2000 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
2001 | .ndo_tx_timeout = efx_watchdog, |
2002 | .ndo_start_xmit = efx_hard_start_xmit, | |
2003 | .ndo_validate_addr = eth_validate_addr, | |
2004 | .ndo_do_ioctl = efx_ioctl, | |
2005 | .ndo_change_mtu = efx_change_mtu, | |
2006 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2007 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2008 | .ndo_set_features = efx_set_features, |
cd2d5b52 BH |
2009 | #ifdef CONFIG_SFC_SRIOV |
2010 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, | |
2011 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2012 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2013 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
2014 | #endif | |
c3ecb9f3 SH |
2015 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2016 | .ndo_poll_controller = efx_netpoll, | |
2017 | #endif | |
94b274bf | 2018 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
2019 | #ifdef CONFIG_RFS_ACCEL |
2020 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2021 | #endif | |
c3ecb9f3 SH |
2022 | }; |
2023 | ||
7dde596e BH |
2024 | static void efx_update_name(struct efx_nic *efx) |
2025 | { | |
2026 | strcpy(efx->name, efx->net_dev->name); | |
2027 | efx_mtd_rename(efx); | |
2028 | efx_set_channel_names(efx); | |
2029 | } | |
2030 | ||
8ceee660 BH |
2031 | static int efx_netdev_event(struct notifier_block *this, |
2032 | unsigned long event, void *ptr) | |
2033 | { | |
d3208b5e | 2034 | struct net_device *net_dev = ptr; |
8ceee660 | 2035 | |
7dde596e BH |
2036 | if (net_dev->netdev_ops == &efx_netdev_ops && |
2037 | event == NETDEV_CHANGENAME) | |
2038 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2039 | |
2040 | return NOTIFY_DONE; | |
2041 | } | |
2042 | ||
2043 | static struct notifier_block efx_netdev_notifier = { | |
2044 | .notifier_call = efx_netdev_event, | |
2045 | }; | |
2046 | ||
06d5e193 BH |
2047 | static ssize_t |
2048 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2049 | { | |
2050 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2051 | return sprintf(buf, "%d\n", efx->phy_type); | |
2052 | } | |
2053 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
2054 | ||
8ceee660 BH |
2055 | static int efx_register_netdev(struct efx_nic *efx) |
2056 | { | |
2057 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2058 | struct efx_channel *channel; |
8ceee660 BH |
2059 | int rc; |
2060 | ||
2061 | net_dev->watchdog_timeo = 5 * HZ; | |
2062 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 2063 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
2064 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
2065 | ||
7dde596e | 2066 | rtnl_lock(); |
aed0628d BH |
2067 | |
2068 | rc = dev_alloc_name(net_dev, net_dev->name); | |
2069 | if (rc < 0) | |
2070 | goto fail_locked; | |
7dde596e | 2071 | efx_update_name(efx); |
aed0628d BH |
2072 | |
2073 | rc = register_netdevice(net_dev); | |
2074 | if (rc) | |
2075 | goto fail_locked; | |
2076 | ||
c04bfc6b BH |
2077 | efx_for_each_channel(channel, efx) { |
2078 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2079 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2080 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2081 | } |
2082 | ||
aed0628d | 2083 | /* Always start with carrier off; PHY events will detect the link */ |
86ee5302 | 2084 | netif_carrier_off(net_dev); |
aed0628d | 2085 | |
7dde596e | 2086 | rtnl_unlock(); |
8ceee660 | 2087 | |
06d5e193 BH |
2088 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2089 | if (rc) { | |
62776d03 BH |
2090 | netif_err(efx, drv, efx->net_dev, |
2091 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2092 | goto fail_registered; |
2093 | } | |
2094 | ||
8ceee660 | 2095 | return 0; |
06d5e193 | 2096 | |
aed0628d BH |
2097 | fail_locked: |
2098 | rtnl_unlock(); | |
62776d03 | 2099 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
2100 | return rc; |
2101 | ||
06d5e193 BH |
2102 | fail_registered: |
2103 | unregister_netdev(net_dev); | |
2104 | return rc; | |
8ceee660 BH |
2105 | } |
2106 | ||
2107 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2108 | { | |
f7d12cdc | 2109 | struct efx_channel *channel; |
8ceee660 BH |
2110 | struct efx_tx_queue *tx_queue; |
2111 | ||
2112 | if (!efx->net_dev) | |
2113 | return; | |
2114 | ||
767e468c | 2115 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
2116 | |
2117 | /* Free up any skbs still remaining. This has to happen before | |
2118 | * we try to unregister the netdev as running their destructors | |
2119 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
2120 | efx_for_each_channel(channel, efx) { |
2121 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
2122 | efx_release_tx_buffers(tx_queue); | |
2123 | } | |
8ceee660 | 2124 | |
73ba7b68 BH |
2125 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
2126 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
2127 | unregister_netdev(efx->net_dev); | |
8ceee660 BH |
2128 | } |
2129 | ||
2130 | /************************************************************************** | |
2131 | * | |
2132 | * Device reset and suspend | |
2133 | * | |
2134 | **************************************************************************/ | |
2135 | ||
2467ca46 BH |
2136 | /* Tears down the entire software state and most of the hardware state |
2137 | * before reset. */ | |
d3245b28 | 2138 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2139 | { |
8ceee660 BH |
2140 | EFX_ASSERT_RESET_SERIALISED(efx); |
2141 | ||
2467ca46 BH |
2142 | efx_stop_all(efx); |
2143 | mutex_lock(&efx->mac_lock); | |
2144 | ||
7f967c01 | 2145 | efx_stop_interrupts(efx, false); |
4b988280 SH |
2146 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2147 | efx->phy_op->fini(efx); | |
ef2b90ee | 2148 | efx->type->fini(efx); |
8ceee660 BH |
2149 | } |
2150 | ||
2467ca46 BH |
2151 | /* This function will always ensure that the locks acquired in |
2152 | * efx_reset_down() are released. A failure return code indicates | |
2153 | * that we were unable to reinitialise the hardware, and the | |
2154 | * driver should be disabled. If ok is false, then the rx and tx | |
2155 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2156 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2157 | { |
2158 | int rc; | |
2159 | ||
2467ca46 | 2160 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2161 | |
ef2b90ee | 2162 | rc = efx->type->init(efx); |
8ceee660 | 2163 | if (rc) { |
62776d03 | 2164 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2165 | goto fail; |
8ceee660 BH |
2166 | } |
2167 | ||
eb9f6744 BH |
2168 | if (!ok) |
2169 | goto fail; | |
2170 | ||
4b988280 | 2171 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2172 | rc = efx->phy_op->init(efx); |
2173 | if (rc) | |
2174 | goto fail; | |
2175 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2176 | netif_err(efx, drv, efx->net_dev, |
2177 | "could not restore PHY settings\n"); | |
4b988280 SH |
2178 | } |
2179 | ||
710b208d | 2180 | efx->type->reconfigure_mac(efx); |
8ceee660 | 2181 | |
7f967c01 | 2182 | efx_start_interrupts(efx, false); |
64eebcfd | 2183 | efx_restore_filters(efx); |
cd2d5b52 | 2184 | efx_sriov_reset(efx); |
eb9f6744 | 2185 | |
eb9f6744 BH |
2186 | mutex_unlock(&efx->mac_lock); |
2187 | ||
2188 | efx_start_all(efx); | |
2189 | ||
2190 | return 0; | |
2191 | ||
2192 | fail: | |
2193 | efx->port_initialized = false; | |
2467ca46 BH |
2194 | |
2195 | mutex_unlock(&efx->mac_lock); | |
2196 | ||
8ceee660 BH |
2197 | return rc; |
2198 | } | |
2199 | ||
eb9f6744 BH |
2200 | /* Reset the NIC using the specified method. Note that the reset may |
2201 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2202 | * |
eb9f6744 | 2203 | * Caller must hold the rtnl_lock. |
8ceee660 | 2204 | */ |
eb9f6744 | 2205 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2206 | { |
eb9f6744 BH |
2207 | int rc, rc2; |
2208 | bool disabled; | |
8ceee660 | 2209 | |
62776d03 BH |
2210 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2211 | RESET_TYPE(method)); | |
8ceee660 | 2212 | |
e4abce85 | 2213 | netif_device_detach(efx->net_dev); |
d3245b28 | 2214 | efx_reset_down(efx, method); |
8ceee660 | 2215 | |
ef2b90ee | 2216 | rc = efx->type->reset(efx, method); |
8ceee660 | 2217 | if (rc) { |
62776d03 | 2218 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2219 | goto out; |
8ceee660 BH |
2220 | } |
2221 | ||
a7d529ae BH |
2222 | /* Clear flags for the scopes we covered. We assume the NIC and |
2223 | * driver are now quiescent so that there is no race here. | |
2224 | */ | |
2225 | efx->reset_pending &= -(1 << (method + 1)); | |
8ceee660 BH |
2226 | |
2227 | /* Reinitialise bus-mastering, which may have been turned off before | |
2228 | * the reset was scheduled. This is still appropriate, even in the | |
2229 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2230 | * can respond to requests. */ | |
2231 | pci_set_master(efx->pci_dev); | |
2232 | ||
eb9f6744 | 2233 | out: |
8ceee660 | 2234 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2235 | disabled = rc || method == RESET_TYPE_DISABLE; |
2236 | rc2 = efx_reset_up(efx, method, !disabled); | |
2237 | if (rc2) { | |
2238 | disabled = true; | |
2239 | if (!rc) | |
2240 | rc = rc2; | |
8ceee660 BH |
2241 | } |
2242 | ||
eb9f6744 | 2243 | if (disabled) { |
f49a4589 | 2244 | dev_close(efx->net_dev); |
62776d03 | 2245 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2246 | efx->state = STATE_DISABLED; |
f4bd954e | 2247 | } else { |
62776d03 | 2248 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2249 | netif_device_attach(efx->net_dev); |
f4bd954e | 2250 | } |
8ceee660 BH |
2251 | return rc; |
2252 | } | |
2253 | ||
2254 | /* The worker thread exists so that code that cannot sleep can | |
2255 | * schedule a reset for later. | |
2256 | */ | |
2257 | static void efx_reset_work(struct work_struct *data) | |
2258 | { | |
eb9f6744 | 2259 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
a7d529ae | 2260 | unsigned long pending = ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 2261 | |
a7d529ae | 2262 | if (!pending) |
319ba649 SH |
2263 | return; |
2264 | ||
eb9f6744 | 2265 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
a7d529ae | 2266 | * flags set so that efx_pci_probe_main will be retried */ |
eb9f6744 | 2267 | if (efx->state != STATE_RUNNING) { |
62776d03 BH |
2268 | netif_info(efx, drv, efx->net_dev, |
2269 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
2270 | return; |
2271 | } | |
2272 | ||
2273 | rtnl_lock(); | |
a7d529ae | 2274 | (void)efx_reset(efx, fls(pending) - 1); |
eb9f6744 | 2275 | rtnl_unlock(); |
8ceee660 BH |
2276 | } |
2277 | ||
2278 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2279 | { | |
2280 | enum reset_type method; | |
2281 | ||
8ceee660 BH |
2282 | switch (type) { |
2283 | case RESET_TYPE_INVISIBLE: | |
2284 | case RESET_TYPE_ALL: | |
2285 | case RESET_TYPE_WORLD: | |
2286 | case RESET_TYPE_DISABLE: | |
2287 | method = type; | |
0e2a9c7c BH |
2288 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2289 | RESET_TYPE(method)); | |
8ceee660 | 2290 | break; |
8ceee660 | 2291 | default: |
0e2a9c7c | 2292 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2293 | netif_dbg(efx, drv, efx->net_dev, |
2294 | "scheduling %s reset for %s\n", | |
2295 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2296 | break; |
2297 | } | |
8ceee660 | 2298 | |
a7d529ae | 2299 | set_bit(method, &efx->reset_pending); |
8ceee660 | 2300 | |
8880f4ec BH |
2301 | /* efx_process_channel() will no longer read events once a |
2302 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2303 | efx_mcdi_mode_poll(efx); | |
2304 | ||
1ab00629 | 2305 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2306 | } |
2307 | ||
2308 | /************************************************************************** | |
2309 | * | |
2310 | * List of NICs we support | |
2311 | * | |
2312 | **************************************************************************/ | |
2313 | ||
2314 | /* PCI device ID table */ | |
a3aa1884 | 2315 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2316 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2317 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2318 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2319 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2320 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2321 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2322 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2323 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2324 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2325 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8ceee660 BH |
2326 | {0} /* end of list */ |
2327 | }; | |
2328 | ||
2329 | /************************************************************************** | |
2330 | * | |
3759433d | 2331 | * Dummy PHY/MAC operations |
8ceee660 | 2332 | * |
01aad7b6 | 2333 | * Can be used for some unimplemented operations |
8ceee660 BH |
2334 | * Needed so all function pointers are valid and do not have to be tested |
2335 | * before use | |
2336 | * | |
2337 | **************************************************************************/ | |
2338 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2339 | { | |
2340 | return 0; | |
2341 | } | |
2342 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2343 | |
2344 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2345 | { |
2346 | return false; | |
2347 | } | |
8ceee660 | 2348 | |
6c8c2513 | 2349 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2350 | .init = efx_port_dummy_op_int, |
d3245b28 | 2351 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2352 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2353 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2354 | }; |
2355 | ||
8ceee660 BH |
2356 | /************************************************************************** |
2357 | * | |
2358 | * Data housekeeping | |
2359 | * | |
2360 | **************************************************************************/ | |
2361 | ||
2362 | /* This zeroes out and then fills in the invariants in a struct | |
2363 | * efx_nic (including all sub-structures). | |
2364 | */ | |
6c8c2513 | 2365 | static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type, |
8ceee660 BH |
2366 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2367 | { | |
4642610c | 2368 | int i; |
8ceee660 BH |
2369 | |
2370 | /* Initialise common structures */ | |
2371 | memset(efx, 0, sizeof(*efx)); | |
2372 | spin_lock_init(&efx->biu_lock); | |
76884835 BH |
2373 | #ifdef CONFIG_SFC_MTD |
2374 | INIT_LIST_HEAD(&efx->mtd_list); | |
2375 | #endif | |
8ceee660 BH |
2376 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2377 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2378 | efx->pci_dev = pci_dev; | |
62776d03 | 2379 | efx->msg_enable = debug; |
8ceee660 | 2380 | efx->state = STATE_INIT; |
8ceee660 | 2381 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2382 | |
2383 | efx->net_dev = net_dev; | |
8ceee660 BH |
2384 | spin_lock_init(&efx->stats_lock); |
2385 | mutex_init(&efx->mac_lock); | |
2386 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2387 | efx->mdio.dev = net_dev; |
766ca0fa | 2388 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2389 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2390 | |
2391 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2392 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2393 | if (!efx->channel[i]) | |
2394 | goto fail; | |
8ceee660 BH |
2395 | } |
2396 | ||
2397 | efx->type = type; | |
2398 | ||
8ceee660 BH |
2399 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2400 | ||
2401 | /* Higher numbered interrupt modes are less capable! */ | |
2402 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2403 | interrupt_mode); | |
2404 | ||
6977dc63 BH |
2405 | /* Would be good to use the net_dev name, but we're too early */ |
2406 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2407 | pci_name(pci_dev)); | |
2408 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2409 | if (!efx->workqueue) |
4642610c | 2410 | goto fail; |
8d9853d9 | 2411 | |
8ceee660 | 2412 | return 0; |
4642610c BH |
2413 | |
2414 | fail: | |
2415 | efx_fini_struct(efx); | |
2416 | return -ENOMEM; | |
8ceee660 BH |
2417 | } |
2418 | ||
2419 | static void efx_fini_struct(struct efx_nic *efx) | |
2420 | { | |
8313aca3 BH |
2421 | int i; |
2422 | ||
2423 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2424 | kfree(efx->channel[i]); | |
2425 | ||
8ceee660 BH |
2426 | if (efx->workqueue) { |
2427 | destroy_workqueue(efx->workqueue); | |
2428 | efx->workqueue = NULL; | |
2429 | } | |
2430 | } | |
2431 | ||
2432 | /************************************************************************** | |
2433 | * | |
2434 | * PCI interface | |
2435 | * | |
2436 | **************************************************************************/ | |
2437 | ||
2438 | /* Main body of final NIC shutdown code | |
2439 | * This is called only at module unload (or hotplug removal). | |
2440 | */ | |
2441 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2442 | { | |
64d8ad6d BH |
2443 | #ifdef CONFIG_RFS_ACCEL |
2444 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
2445 | efx->net_dev->rx_cpu_rmap = NULL; | |
2446 | #endif | |
7f967c01 | 2447 | efx_stop_interrupts(efx, false); |
152b6a62 | 2448 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2449 | efx_fini_port(efx); |
ef2b90ee | 2450 | efx->type->fini(efx); |
8ceee660 BH |
2451 | efx_fini_napi(efx); |
2452 | efx_remove_all(efx); | |
2453 | } | |
2454 | ||
2455 | /* Final NIC shutdown | |
2456 | * This is called only at module unload (or hotplug removal). | |
2457 | */ | |
2458 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2459 | { | |
2460 | struct efx_nic *efx; | |
2461 | ||
2462 | efx = pci_get_drvdata(pci_dev); | |
2463 | if (!efx) | |
2464 | return; | |
2465 | ||
2466 | /* Mark the NIC as fini, then stop the interface */ | |
2467 | rtnl_lock(); | |
2468 | efx->state = STATE_FINI; | |
2469 | dev_close(efx->net_dev); | |
2470 | ||
2471 | /* Allow any queued efx_resets() to complete */ | |
2472 | rtnl_unlock(); | |
2473 | ||
7f967c01 | 2474 | efx_stop_interrupts(efx, false); |
cd2d5b52 | 2475 | efx_sriov_fini(efx); |
8ceee660 BH |
2476 | efx_unregister_netdev(efx); |
2477 | ||
7dde596e BH |
2478 | efx_mtd_remove(efx); |
2479 | ||
8ceee660 BH |
2480 | /* Wait for any scheduled resets to complete. No more will be |
2481 | * scheduled from this point because efx_stop_all() has been | |
2482 | * called, we are no longer registered with driverlink, and | |
2483 | * the net_device's have been removed. */ | |
1ab00629 | 2484 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2485 | |
2486 | efx_pci_remove_main(efx); | |
2487 | ||
8ceee660 | 2488 | efx_fini_io(efx); |
62776d03 | 2489 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 BH |
2490 | |
2491 | pci_set_drvdata(pci_dev, NULL); | |
2492 | efx_fini_struct(efx); | |
2493 | free_netdev(efx->net_dev); | |
2494 | }; | |
2495 | ||
2496 | /* Main body of NIC initialisation | |
2497 | * This is called at module load (or hotplug insertion, theoretically). | |
2498 | */ | |
2499 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2500 | { | |
2501 | int rc; | |
2502 | ||
2503 | /* Do start-of-day initialisation */ | |
2504 | rc = efx_probe_all(efx); | |
2505 | if (rc) | |
2506 | goto fail1; | |
2507 | ||
e8f14992 | 2508 | efx_init_napi(efx); |
8ceee660 | 2509 | |
ef2b90ee | 2510 | rc = efx->type->init(efx); |
8ceee660 | 2511 | if (rc) { |
62776d03 BH |
2512 | netif_err(efx, probe, efx->net_dev, |
2513 | "failed to initialise NIC\n"); | |
278c0621 | 2514 | goto fail3; |
8ceee660 BH |
2515 | } |
2516 | ||
2517 | rc = efx_init_port(efx); | |
2518 | if (rc) { | |
62776d03 BH |
2519 | netif_err(efx, probe, efx->net_dev, |
2520 | "failed to initialise port\n"); | |
278c0621 | 2521 | goto fail4; |
8ceee660 BH |
2522 | } |
2523 | ||
152b6a62 | 2524 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2525 | if (rc) |
278c0621 | 2526 | goto fail5; |
7f967c01 | 2527 | efx_start_interrupts(efx, false); |
8ceee660 BH |
2528 | |
2529 | return 0; | |
2530 | ||
278c0621 | 2531 | fail5: |
8ceee660 | 2532 | efx_fini_port(efx); |
8ceee660 | 2533 | fail4: |
ef2b90ee | 2534 | efx->type->fini(efx); |
8ceee660 BH |
2535 | fail3: |
2536 | efx_fini_napi(efx); | |
8ceee660 BH |
2537 | efx_remove_all(efx); |
2538 | fail1: | |
2539 | return rc; | |
2540 | } | |
2541 | ||
2542 | /* NIC initialisation | |
2543 | * | |
2544 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2545 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2546 | * sets up and registers the network devices with the kernel and hooks |
2547 | * the interrupt service routine. It does not prepare the device for | |
2548 | * transmission; this is left to the first time one of the network | |
2549 | * interfaces is brought up (i.e. efx_net_open). | |
2550 | */ | |
2551 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2552 | const struct pci_device_id *entry) | |
2553 | { | |
6c8c2513 | 2554 | const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data; |
8ceee660 BH |
2555 | struct net_device *net_dev; |
2556 | struct efx_nic *efx; | |
fadac6aa | 2557 | int rc; |
8ceee660 BH |
2558 | |
2559 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2560 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2561 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2562 | if (!net_dev) |
2563 | return -ENOMEM; | |
c383b537 | 2564 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 | 2565 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2566 | NETIF_F_RXCSUM); |
738a8f4b BH |
2567 | if (type->offload_features & NETIF_F_V6_CSUM) |
2568 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2569 | /* Mask for features that also apply to VLAN devices */ |
2570 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2571 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2572 | NETIF_F_RXCSUM); | |
2573 | /* All offloads can be toggled */ | |
2574 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
767e468c | 2575 | efx = netdev_priv(net_dev); |
8ceee660 | 2576 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2577 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2578 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2579 | if (rc) | |
2580 | goto fail1; | |
2581 | ||
62776d03 | 2582 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2583 | "Solarflare NIC detected\n"); |
8ceee660 BH |
2584 | |
2585 | /* Set up basic I/O (BAR mappings etc) */ | |
2586 | rc = efx_init_io(efx); | |
2587 | if (rc) | |
2588 | goto fail2; | |
2589 | ||
fadac6aa | 2590 | rc = efx_pci_probe_main(efx); |
fa402b2e | 2591 | |
fadac6aa BH |
2592 | /* Serialise against efx_reset(). No more resets will be |
2593 | * scheduled since efx_stop_all() has been called, and we have | |
2594 | * not and never have been registered. | |
2595 | */ | |
2596 | cancel_work_sync(&efx->reset_work); | |
8ceee660 | 2597 | |
fadac6aa BH |
2598 | if (rc) |
2599 | goto fail3; | |
8ceee660 | 2600 | |
fadac6aa BH |
2601 | /* If there was a scheduled reset during probe, the NIC is |
2602 | * probably hosed anyway. | |
2603 | */ | |
2604 | if (efx->reset_pending) { | |
2605 | rc = -EIO; | |
8ceee660 BH |
2606 | goto fail4; |
2607 | } | |
2608 | ||
55edc6e6 BH |
2609 | /* Switch to the running state before we expose the device to the OS, |
2610 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2611 | efx->state = STATE_RUNNING; |
7dde596e | 2612 | |
8ceee660 BH |
2613 | rc = efx_register_netdev(efx); |
2614 | if (rc) | |
fadac6aa | 2615 | goto fail4; |
8ceee660 | 2616 | |
cd2d5b52 BH |
2617 | rc = efx_sriov_init(efx); |
2618 | if (rc) | |
2619 | netif_err(efx, probe, efx->net_dev, | |
2620 | "SR-IOV can't be enabled rc %d\n", rc); | |
2621 | ||
62776d03 | 2622 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 2623 | |
7c43161c | 2624 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 2625 | rtnl_lock(); |
7c43161c | 2626 | rc = efx_mtd_probe(efx); |
a5211bb5 | 2627 | rtnl_unlock(); |
7c43161c BH |
2628 | if (rc) |
2629 | netif_warn(efx, probe, efx->net_dev, | |
2630 | "failed to create MTDs (%d)\n", rc); | |
2631 | ||
8ceee660 BH |
2632 | return 0; |
2633 | ||
8ceee660 | 2634 | fail4: |
fadac6aa | 2635 | efx_pci_remove_main(efx); |
8ceee660 BH |
2636 | fail3: |
2637 | efx_fini_io(efx); | |
2638 | fail2: | |
2639 | efx_fini_struct(efx); | |
2640 | fail1: | |
5e2a911c | 2641 | WARN_ON(rc > 0); |
62776d03 | 2642 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2643 | free_netdev(net_dev); |
2644 | return rc; | |
2645 | } | |
2646 | ||
89c758fa BH |
2647 | static int efx_pm_freeze(struct device *dev) |
2648 | { | |
2649 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2650 | ||
2651 | efx->state = STATE_FINI; | |
2652 | ||
2653 | netif_device_detach(efx->net_dev); | |
2654 | ||
2655 | efx_stop_all(efx); | |
7f967c01 | 2656 | efx_stop_interrupts(efx, false); |
89c758fa BH |
2657 | |
2658 | return 0; | |
2659 | } | |
2660 | ||
2661 | static int efx_pm_thaw(struct device *dev) | |
2662 | { | |
2663 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2664 | ||
2665 | efx->state = STATE_INIT; | |
2666 | ||
7f967c01 | 2667 | efx_start_interrupts(efx, false); |
89c758fa BH |
2668 | |
2669 | mutex_lock(&efx->mac_lock); | |
2670 | efx->phy_op->reconfigure(efx); | |
2671 | mutex_unlock(&efx->mac_lock); | |
2672 | ||
2673 | efx_start_all(efx); | |
2674 | ||
2675 | netif_device_attach(efx->net_dev); | |
2676 | ||
2677 | efx->state = STATE_RUNNING; | |
2678 | ||
2679 | efx->type->resume_wol(efx); | |
2680 | ||
319ba649 SH |
2681 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2682 | queue_work(reset_workqueue, &efx->reset_work); | |
2683 | ||
89c758fa BH |
2684 | return 0; |
2685 | } | |
2686 | ||
2687 | static int efx_pm_poweroff(struct device *dev) | |
2688 | { | |
2689 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2690 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2691 | ||
2692 | efx->type->fini(efx); | |
2693 | ||
a7d529ae | 2694 | efx->reset_pending = 0; |
89c758fa BH |
2695 | |
2696 | pci_save_state(pci_dev); | |
2697 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2698 | } | |
2699 | ||
2700 | /* Used for both resume and restore */ | |
2701 | static int efx_pm_resume(struct device *dev) | |
2702 | { | |
2703 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2704 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2705 | int rc; | |
2706 | ||
2707 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2708 | if (rc) | |
2709 | return rc; | |
2710 | pci_restore_state(pci_dev); | |
2711 | rc = pci_enable_device(pci_dev); | |
2712 | if (rc) | |
2713 | return rc; | |
2714 | pci_set_master(efx->pci_dev); | |
2715 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2716 | if (rc) | |
2717 | return rc; | |
2718 | rc = efx->type->init(efx); | |
2719 | if (rc) | |
2720 | return rc; | |
2721 | efx_pm_thaw(dev); | |
2722 | return 0; | |
2723 | } | |
2724 | ||
2725 | static int efx_pm_suspend(struct device *dev) | |
2726 | { | |
2727 | int rc; | |
2728 | ||
2729 | efx_pm_freeze(dev); | |
2730 | rc = efx_pm_poweroff(dev); | |
2731 | if (rc) | |
2732 | efx_pm_resume(dev); | |
2733 | return rc; | |
2734 | } | |
2735 | ||
18e83e4c | 2736 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
2737 | .suspend = efx_pm_suspend, |
2738 | .resume = efx_pm_resume, | |
2739 | .freeze = efx_pm_freeze, | |
2740 | .thaw = efx_pm_thaw, | |
2741 | .poweroff = efx_pm_poweroff, | |
2742 | .restore = efx_pm_resume, | |
2743 | }; | |
2744 | ||
8ceee660 | 2745 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2746 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2747 | .id_table = efx_pci_table, |
2748 | .probe = efx_pci_probe, | |
2749 | .remove = efx_pci_remove, | |
89c758fa | 2750 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2751 | }; |
2752 | ||
2753 | /************************************************************************** | |
2754 | * | |
2755 | * Kernel module interface | |
2756 | * | |
2757 | *************************************************************************/ | |
2758 | ||
2759 | module_param(interrupt_mode, uint, 0444); | |
2760 | MODULE_PARM_DESC(interrupt_mode, | |
2761 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2762 | ||
2763 | static int __init efx_init_module(void) | |
2764 | { | |
2765 | int rc; | |
2766 | ||
2767 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2768 | ||
2769 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2770 | if (rc) | |
2771 | goto err_notifier; | |
2772 | ||
cd2d5b52 BH |
2773 | rc = efx_init_sriov(); |
2774 | if (rc) | |
2775 | goto err_sriov; | |
2776 | ||
1ab00629 SH |
2777 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2778 | if (!reset_workqueue) { | |
2779 | rc = -ENOMEM; | |
2780 | goto err_reset; | |
2781 | } | |
8ceee660 BH |
2782 | |
2783 | rc = pci_register_driver(&efx_pci_driver); | |
2784 | if (rc < 0) | |
2785 | goto err_pci; | |
2786 | ||
2787 | return 0; | |
2788 | ||
2789 | err_pci: | |
1ab00629 SH |
2790 | destroy_workqueue(reset_workqueue); |
2791 | err_reset: | |
cd2d5b52 BH |
2792 | efx_fini_sriov(); |
2793 | err_sriov: | |
8ceee660 BH |
2794 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2795 | err_notifier: | |
2796 | return rc; | |
2797 | } | |
2798 | ||
2799 | static void __exit efx_exit_module(void) | |
2800 | { | |
2801 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2802 | ||
2803 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2804 | destroy_workqueue(reset_workqueue); |
cd2d5b52 | 2805 | efx_fini_sriov(); |
8ceee660 BH |
2806 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2807 | ||
2808 | } | |
2809 | ||
2810 | module_init(efx_init_module); | |
2811 | module_exit(efx_exit_module); | |
2812 | ||
906bb26c BH |
2813 | MODULE_AUTHOR("Solarflare Communications and " |
2814 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2815 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2816 | MODULE_LICENSE("GPL"); | |
2817 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |