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sfc: Implement ndo_vlan_rx_{add, kill}_vid() callbacks
[deliverable/linux.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660 1/****************************************************************************
f7a6d2c4 2 * Driver for Solarflare network controllers and boards
8ceee660 3 * Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4 4 * Copyright 2005-2013 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
8ceee660 20#include <linux/ethtool.h>
aa6ef27e 21#include <linux/topology.h>
5a0e3ad6 22#include <linux/gfp.h>
626950db 23#include <linux/aer.h>
b28405b0 24#include <linux/interrupt.h>
8ceee660 25#include "net_driver.h"
8ceee660 26#include "efx.h"
744093c9 27#include "nic.h"
dd40781e 28#include "selftest.h"
7fa8d547 29#include "sriov.h"
8ceee660 30
8880f4ec 31#include "mcdi.h"
fd371e32 32#include "workarounds.h"
8880f4ec 33
c459302d
BH		 34/**************************************************************************
35 *
36 * Type name strings
37 *
38 **************************************************************************
39 */
40
41/* Loopback mode names (see LOOPBACK_MODE()) */
42const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 43const char *const efx_loopback_mode_names[] = {
c459302d 44 [LOOPBACK_NONE] = "NONE",
e58f69f4 45 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 46 [LOOPBACK_GMAC] = "GMAC",
47 [LOOPBACK_XGMII] = "XGMII",
48 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH		 49 [LOOPBACK_XAUI] = "XAUI",
50 [LOOPBACK_GMII] = "GMII",
51 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH		 52 [LOOPBACK_XGBR] = "XGBR",
53 [LOOPBACK_XFI] = "XFI",
54 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
55 [LOOPBACK_GMII_FAR] = "GMII_FAR",
56 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
57 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 58 [LOOPBACK_GPHY] = "GPHY",
59 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH		 60 [LOOPBACK_PCS] = "PCS",
61 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 62 [LOOPBACK_XPORT] = "XPORT",
63 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 64 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH		 65 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
66 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 67 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH		 68 [LOOPBACK_XFI_WS] = "XFI_WS",
69 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 70 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 71};
72
c459302d 73const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 74const char *const efx_reset_type_names[] = {
626950db
AR		 75 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
76 [RESET_TYPE_ALL] = "ALL",
77 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
78 [RESET_TYPE_WORLD] = "WORLD",
79 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
087e9025 80 [RESET_TYPE_DATAPATH] = "DATAPATH",
e283546c 81 [RESET_TYPE_MC_BIST] = "MC_BIST",
626950db
AR		 82 [RESET_TYPE_DISABLE] = "DISABLE",
83 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
84 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
85 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
3de82b91 86 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
626950db
AR		 87 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
88 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
e283546c 89 [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)",
c459302d
BH		 90};
91
1ab00629
SH		 92/* Reset workqueue. If any NIC has a hardware failure then a reset will be
93 * queued onto this work queue. This is not a per-nic work queue, because
94 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
95 */
96static struct workqueue_struct *reset_workqueue;
97
74cd60a4
JC		 98/* How often and how many times to poll for a reset while waiting for a
99 * BIST that another function started to complete.
100 */
101#define BIST_WAIT_DELAY_MS 100
102#define BIST_WAIT_DELAY_COUNT 100
103
8ceee660
BH		 104/**************************************************************************
105 *
106 * Configurable values
107 *
108 *************************************************************************/
109
8ceee660
BH		 110/*
111 * Use separate channels for TX and RX events
112 *
28b581ab
NT		 113 * Set this to 1 to use separate channels for TX and RX. It allows us
114 * to control interrupt affinity separately for TX and RX.
8ceee660 115 *
28b581ab 116 * This is only used in MSI-X interrupt mode
8ceee660 117 */
b0fbdae1
SS		 118bool efx_separate_tx_channels;
119module_param(efx_separate_tx_channels, bool, 0444);
120MODULE_PARM_DESC(efx_separate_tx_channels,
28b581ab 121 "Use separate channels for TX and RX");
8ceee660
BH		 122
123/* This is the weight assigned to each of the (per-channel) virtual
124 * NAPI devices.
125 */
126static int napi_weight = 64;
127
128/* This is the time (in jiffies) between invocations of the hardware
626950db
AR		 129 * monitor.
130 * On Falcon-based NICs, this will:
e254c274
BH		 131 * - Check the on-board hardware monitor;
132 * - Poll the link state and reconfigure the hardware as necessary.
626950db
AR		 133 * On Siena-based NICs for power systems with EEH support, this will give EEH a
134 * chance to start.
8ceee660 135 */
d215697f 136static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 137
8ceee660
BH		 138/* Initial interrupt moderation settings. They can be modified after
139 * module load with ethtool.
140 *
141 * The default for RX should strike a balance between increasing the
142 * round-trip latency and reducing overhead.
143 */
144static unsigned int rx_irq_mod_usec = 60;
145
146/* Initial interrupt moderation settings. They can be modified after
147 * module load with ethtool.
148 *
149 * This default is chosen to ensure that a 10G link does not go idle
150 * while a TX queue is stopped after it has become full. A queue is
151 * restarted when it drops below half full. The time this takes (assuming
152 * worst case 3 descriptors per packet and 1024 descriptors) is
153 * 512 / 3 * 1.2 = 205 usec.
154 */
155static unsigned int tx_irq_mod_usec = 150;
156
157/* This is the first interrupt mode to try out of:
158 * 0 => MSI-X
159 * 1 => MSI
160 * 2 => legacy
161 */
162static unsigned int interrupt_mode;
163
164/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
165 * i.e. the number of CPUs among which we may distribute simultaneous
166 * interrupt handling.
167 *
168 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 169 * The default (0) means to assign an interrupt to each core.
8ceee660
BH		 170 */
171static unsigned int rss_cpus;
172module_param(rss_cpus, uint, 0444);
173MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
174
b9cc977d
BH		 175static bool phy_flash_cfg;
176module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH		 177MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
178
e7bed9c8 179static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH		 180module_param(irq_adapt_low_thresh, uint, 0644);
181MODULE_PARM_DESC(irq_adapt_low_thresh,
182 "Threshold score for reducing IRQ moderation");
183
e7bed9c8 184static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH		 185module_param(irq_adapt_high_thresh, uint, 0644);
186MODULE_PARM_DESC(irq_adapt_high_thresh,
187 "Threshold score for increasing IRQ moderation");
188
62776d03
BH		 189static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
190 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
191 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
192 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
193module_param(debug, uint, 0);
194MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
195
8ceee660
BH		 196/**************************************************************************
197 *
198 * Utility functions and prototypes
199 *
200 *************************************************************************/
4642610c 201
261e4d96 202static int efx_soft_enable_interrupts(struct efx_nic *efx);
d8291187 203static void efx_soft_disable_interrupts(struct efx_nic *efx);
7f967c01 204static void efx_remove_channel(struct efx_channel *channel);
4642610c 205static void efx_remove_channels(struct efx_nic *efx);
7f967c01 206static const struct efx_channel_type efx_default_channel_type;
8ceee660 207static void efx_remove_port(struct efx_nic *efx);
7f967c01 208static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 209static void efx_fini_napi(struct efx_nic *efx);
e8f14992 210static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH		 211static void efx_fini_struct(struct efx_nic *efx);
212static void efx_start_all(struct efx_nic *efx);
213static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH		 214
215#define EFX_ASSERT_RESET_SERIALISED(efx) \
216 do { \
f16aeea0 217 if ((efx->state == STATE_READY) || \
626950db 218 (efx->state == STATE_RECOVERY) || \
332c1ce9 219 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 220 ASSERT_RTNL(); \
221 } while (0)
222
8b7325b4
BH		 223static int efx_check_disabled(struct efx_nic *efx)
224{
626950db 225 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
8b7325b4
BH		 226 netif_err(efx, drv, efx->net_dev,
227 "device is disabled due to earlier errors\n");
228 return -EIO;
229 }
230 return 0;
231}
232
8ceee660
BH		 233/**************************************************************************
234 *
235 * Event queue processing
236 *
237 *************************************************************************/
238
239/* Process channel's event queue
240 *
241 * This function is responsible for processing the event queue of a
242 * single channel. The caller must guarantee that this function will
243 * never be concurrently called more than once on the same channel,
244 * though different channels may be being processed concurrently.
245 */
fa236e18 246static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 247{
c936835c 248 struct efx_tx_queue *tx_queue;
fa236e18 249 int spent;
8ceee660 250
9f2cb71c 251 if (unlikely(!channel->enabled))
42cbe2d7 252 return 0;
8ceee660 253
c936835c
PD		 254 efx_for_each_channel_tx_queue(tx_queue, channel) {
255 tx_queue->pkts_compl = 0;
256 tx_queue->bytes_compl = 0;
257 }
258
fa236e18 259 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH		 260 if (spent && efx_channel_has_rx_queue(channel)) {
261 struct efx_rx_queue *rx_queue =
262 efx_channel_get_rx_queue(channel);
263
ff734ef4 264 efx_rx_flush_packet(channel);
cce28794 265 efx_fast_push_rx_descriptors(rx_queue, true);
8ceee660
BH		 266 }
267
c936835c
PD		 268 /* Update BQL */
269 efx_for_each_channel_tx_queue(tx_queue, channel) {
270 if (tx_queue->bytes_compl) {
271 netdev_tx_completed_queue(tx_queue->core_txq,
272 tx_queue->pkts_compl, tx_queue->bytes_compl);
273 }
274 }
275
fa236e18 276 return spent;
8ceee660
BH		 277}
278
8ceee660
BH		 279/* NAPI poll handler
280 *
281 * NAPI guarantees serialisation of polls of the same device, which
282 * provides the guarantee required by efx_process_channel().
283 */
284static int efx_poll(struct napi_struct *napi, int budget)
285{
286 struct efx_channel *channel =
287 container_of(napi, struct efx_channel, napi_str);
62776d03 288 struct efx_nic *efx = channel->efx;
fa236e18 289 int spent;
8ceee660 290
36763266
AR		 291 if (!efx_channel_lock_napi(channel))
292 return budget;
293
62776d03
BH		 294 netif_vdbg(efx, intr, efx->net_dev,
295 "channel %d NAPI poll executing on CPU %d\n",
296 channel->channel, raw_smp_processor_id());
8ceee660 297
fa236e18 298 spent = efx_process_channel(channel, budget);
8ceee660 299
fa236e18 300 if (spent < budget) {
9d9a6973 301 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH		 302 efx->irq_rx_adaptive &&
303 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH		 304 if (unlikely(channel->irq_mod_score <
305 irq_adapt_low_thresh)) {
0d86ebd8
BH		 306 if (channel->irq_moderation > 1) {
307 channel->irq_moderation -= 1;
ef2b90ee 308 efx->type->push_irq_moderation(channel);
0d86ebd8 309 }
6fb70fd1
BH		 310 } else if (unlikely(channel->irq_mod_score >
311 irq_adapt_high_thresh)) {
0d86ebd8
BH		 312 if (channel->irq_moderation <
313 efx->irq_rx_moderation) {
314 channel->irq_moderation += 1;
ef2b90ee 315 efx->type->push_irq_moderation(channel);
0d86ebd8 316 }
6fb70fd1 317 }
6fb70fd1
BH		 318 channel->irq_count = 0;
319 channel->irq_mod_score = 0;
320 }
321
64d8ad6d
BH		 322 efx_filter_rfs_expire(channel);
323
8ceee660 324 /* There is no race here; although napi_disable() will
288379f0 325 * only wait for napi_complete(), this isn't a problem
514bedbc 326 * since efx_nic_eventq_read_ack() will have no effect if
8ceee660
BH		 327 * interrupts have already been disabled.
328 */
288379f0 329 napi_complete(napi);
514bedbc 330 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 331 }
332
36763266 333 efx_channel_unlock_napi(channel);
fa236e18 334 return spent;
8ceee660
BH		 335}
336
8ceee660
BH		 337/* Create event queue
338 * Event queue memory allocations are done only once. If the channel
339 * is reset, the memory buffer will be reused; this guards against
340 * errors during channel reset and also simplifies interrupt handling.
341 */
342static int efx_probe_eventq(struct efx_channel *channel)
343{
ecc910f5
SH		 344 struct efx_nic *efx = channel->efx;
345 unsigned long entries;
346
86ee5302 347 netif_dbg(efx, probe, efx->net_dev,
62776d03 348 "chan %d create event queue\n", channel->channel);
8ceee660 349
ecc910f5
SH		 350 /* Build an event queue with room for one event per tx and rx buffer,
351 * plus some extra for link state events and MCDI completions. */
352 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
353 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
354 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
355
152b6a62 356 return efx_nic_probe_eventq(channel);
8ceee660
BH		 357}
358
359/* Prepare channel's event queue */
261e4d96 360static int efx_init_eventq(struct efx_channel *channel)
8ceee660 361{
15acb1ce 362 struct efx_nic *efx = channel->efx;
261e4d96
JC		 363 int rc;
364
365 EFX_WARN_ON_PARANOID(channel->eventq_init);
366
15acb1ce 367 netif_dbg(efx, drv, efx->net_dev,
62776d03 368 "chan %d init event queue\n", channel->channel);
8ceee660 369
261e4d96
JC		 370 rc = efx_nic_init_eventq(channel);
371 if (rc == 0) {
15acb1ce 372 efx->type->push_irq_moderation(channel);
261e4d96
JC		 373 channel->eventq_read_ptr = 0;
374 channel->eventq_init = true;
375 }
376 return rc;
8ceee660
BH		 377}
378
9f2cb71c 379/* Enable event queue processing and NAPI */
36763266 380void efx_start_eventq(struct efx_channel *channel)
9f2cb71c
BH		 381{
382 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
383 "chan %d start event queue\n", channel->channel);
384
514bedbc 385 /* Make sure the NAPI handler sees the enabled flag set */
9f2cb71c
BH		 386 channel->enabled = true;
387 smp_wmb();
388
36763266 389 efx_channel_enable(channel);
9f2cb71c
BH		 390 napi_enable(&channel->napi_str);
391 efx_nic_eventq_read_ack(channel);
392}
393
394/* Disable event queue processing and NAPI */
36763266 395void efx_stop_eventq(struct efx_channel *channel)
9f2cb71c
BH		 396{
397 if (!channel->enabled)
398 return;
399
400 napi_disable(&channel->napi_str);
36763266
AR		 401 while (!efx_channel_disable(channel))
402 usleep_range(1000, 20000);
9f2cb71c
BH		 403 channel->enabled = false;
404}
405
8ceee660
BH		 406static void efx_fini_eventq(struct efx_channel *channel)
407{
be3fc09c
BH		 408 if (!channel->eventq_init)
409 return;
410
62776d03
BH		 411 netif_dbg(channel->efx, drv, channel->efx->net_dev,
412 "chan %d fini event queue\n", channel->channel);
8ceee660 413
152b6a62 414 efx_nic_fini_eventq(channel);
be3fc09c 415 channel->eventq_init = false;
8ceee660
BH		 416}
417
418static void efx_remove_eventq(struct efx_channel *channel)
419{
62776d03
BH		 420 netif_dbg(channel->efx, drv, channel->efx->net_dev,
421 "chan %d remove event queue\n", channel->channel);
8ceee660 422
152b6a62 423 efx_nic_remove_eventq(channel);
8ceee660
BH		 424}
425
426/**************************************************************************
427 *
428 * Channel handling
429 *
430 *************************************************************************/
431
7f967c01 432/* Allocate and initialise a channel structure. */
4642610c
BH		 433static struct efx_channel *
434efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
435{
436 struct efx_channel *channel;
437 struct efx_rx_queue *rx_queue;
438 struct efx_tx_queue *tx_queue;
439 int j;
440
7f967c01
BH		 441 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
442 if (!channel)
443 return NULL;
4642610c 444
7f967c01
BH		 445 channel->efx = efx;
446 channel->channel = i;
447 channel->type = &efx_default_channel_type;
4642610c 448
7f967c01
BH		 449 for (j = 0; j < EFX_TXQ_TYPES; j++) {
450 tx_queue = &channel->tx_queue[j];
451 tx_queue->efx = efx;
452 tx_queue->queue = i * EFX_TXQ_TYPES + j;
453 tx_queue->channel = channel;
454 }
4642610c 455
7f967c01
BH		 456 rx_queue = &channel->rx_queue;
457 rx_queue->efx = efx;
458 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
459 (unsigned long)rx_queue);
4642610c 460
7f967c01
BH		 461 return channel;
462}
463
464/* Allocate and initialise a channel structure, copying parameters
465 * (but not resources) from an old channel structure.
466 */
467static struct efx_channel *
468efx_copy_channel(const struct efx_channel *old_channel)
469{
470 struct efx_channel *channel;
471 struct efx_rx_queue *rx_queue;
472 struct efx_tx_queue *tx_queue;
473 int j;
4642610c 474
7f967c01
BH		 475 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
476 if (!channel)
477 return NULL;
478
479 *channel = *old_channel;
480
481 channel->napi_dev = NULL;
482 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 483
7f967c01
BH		 484 for (j = 0; j < EFX_TXQ_TYPES; j++) {
485 tx_queue = &channel->tx_queue[j];
486 if (tx_queue->channel)
4642610c 487 tx_queue->channel = channel;
7f967c01
BH		 488 tx_queue->buffer = NULL;
489 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH		 490 }
491
4642610c 492 rx_queue = &channel->rx_queue;
7f967c01
BH		 493 rx_queue->buffer = NULL;
494 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH		 495 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
496 (unsigned long)rx_queue);
497
498 return channel;
499}
500
8ceee660
BH		 501static int efx_probe_channel(struct efx_channel *channel)
502{
503 struct efx_tx_queue *tx_queue;
504 struct efx_rx_queue *rx_queue;
505 int rc;
506
62776d03
BH		 507 netif_dbg(channel->efx, probe, channel->efx->net_dev,
508 "creating channel %d\n", channel->channel);
8ceee660 509
7f967c01
BH		 510 rc = channel->type->pre_probe(channel);
511 if (rc)
512 goto fail;
513
8ceee660
BH		 514 rc = efx_probe_eventq(channel);
515 if (rc)
7f967c01 516 goto fail;
8ceee660
BH		 517
518 efx_for_each_channel_tx_queue(tx_queue, channel) {
519 rc = efx_probe_tx_queue(tx_queue);
520 if (rc)
7f967c01 521 goto fail;
8ceee660
BH		 522 }
523
524 efx_for_each_channel_rx_queue(rx_queue, channel) {
525 rc = efx_probe_rx_queue(rx_queue);
526 if (rc)
7f967c01 527 goto fail;
8ceee660
BH		 528 }
529
8ceee660
BH		 530 return 0;
531
7f967c01
BH		 532fail:
533 efx_remove_channel(channel);
8ceee660
BH		 534 return rc;
535}
536
7f967c01
BH		 537static void
538efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
539{
540 struct efx_nic *efx = channel->efx;
541 const char *type;
542 int number;
543
544 number = channel->channel;
545 if (efx->tx_channel_offset == 0) {
546 type = "";
547 } else if (channel->channel < efx->tx_channel_offset) {
548 type = "-rx";
549 } else {
550 type = "-tx";
551 number -= efx->tx_channel_offset;
552 }
553 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
554}
8ceee660 555
56536e9c
BH		 556static void efx_set_channel_names(struct efx_nic *efx)
557{
558 struct efx_channel *channel;
56536e9c 559
7f967c01
BH		 560 efx_for_each_channel(channel, efx)
561 channel->type->get_name(channel,
d8291187
BH		 562 efx->msi_context[channel->channel].name,
563 sizeof(efx->msi_context[0].name));
56536e9c
BH		 564}
565
4642610c
BH		 566static int efx_probe_channels(struct efx_nic *efx)
567{
568 struct efx_channel *channel;
569 int rc;
570
571 /* Restart special buffer allocation */
572 efx->next_buffer_table = 0;
573
c92aaff1
BH		 574 /* Probe channels in reverse, so that any 'extra' channels
575 * use the start of the buffer table. This allows the traffic
576 * channels to be resized without moving them or wasting the
577 * entries before them.
578 */
579 efx_for_each_channel_rev(channel, efx) {
4642610c
BH		 580 rc = efx_probe_channel(channel);
581 if (rc) {
582 netif_err(efx, probe, efx->net_dev,
583 "failed to create channel %d\n",
584 channel->channel);
585 goto fail;
586 }
587 }
588 efx_set_channel_names(efx);
589
590 return 0;
591
592fail:
593 efx_remove_channels(efx);
594 return rc;
595}
596
8ceee660
BH		 597/* Channels are shutdown and reinitialised whilst the NIC is running
598 * to propagate configuration changes (mtu, checksum offload), or
599 * to clear hardware error conditions
600 */
9f2cb71c 601static void efx_start_datapath(struct efx_nic *efx)
8ceee660 602{
ebfcd0fd 603 netdev_features_t old_features = efx->net_dev->features;
85740cdf 604 bool old_rx_scatter = efx->rx_scatter;
8ceee660
BH		 605 struct efx_tx_queue *tx_queue;
606 struct efx_rx_queue *rx_queue;
607 struct efx_channel *channel;
85740cdf 608 size_t rx_buf_len;
8ceee660 609
f7f13b0b
BH		 610 /* Calculate the rx buffer allocation parameters required to
611 * support the current MTU, including padding for header
612 * alignment and overruns.
613 */
43a3739d 614 efx->rx_dma_len = (efx->rx_prefix_size +
272baeeb
BH		 615 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
616 efx->type->rx_buffer_padding);
85740cdf 617 rx_buf_len = (sizeof(struct efx_rx_page_state) +
2ec03014 618 efx->rx_ip_align + efx->rx_dma_len);
85740cdf 619 if (rx_buf_len <= PAGE_SIZE) {
e8c68c0a 620 efx->rx_scatter = efx->type->always_rx_scatter;
85740cdf 621 efx->rx_buffer_order = 0;
85740cdf 622 } else if (efx->type->can_rx_scatter) {
950c54df 623 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
85740cdf 624 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
950c54df
BH		 625 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
626 EFX_RX_BUF_ALIGNMENT) >
627 PAGE_SIZE);
85740cdf
BH		 628 efx->rx_scatter = true;
629 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
630 efx->rx_buffer_order = 0;
85740cdf
BH		 631 } else {
632 efx->rx_scatter = false;
633 efx->rx_buffer_order = get_order(rx_buf_len);
85740cdf
BH		 634 }
635
1648a23f
DP		 636 efx_rx_config_page_split(efx);
637 if (efx->rx_buffer_order)
638 netif_dbg(efx, drv, efx->net_dev,
639 "RX buf len=%u; page order=%u batch=%u\n",
640 efx->rx_dma_len, efx->rx_buffer_order,
641 efx->rx_pages_per_batch);
642 else
643 netif_dbg(efx, drv, efx->net_dev,
644 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
645 efx->rx_dma_len, efx->rx_page_buf_step,
646 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
2768935a 647
ebfcd0fd
AR		 648 /* Restore previously fixed features in hw_features and remove
649 * features which are fixed now
650 */
651 efx->net_dev->hw_features |= efx->net_dev->features;
652 efx->net_dev->hw_features &= ~efx->fixed_features;
653 efx->net_dev->features |= efx->fixed_features;
654 if (efx->net_dev->features != old_features)
655 netdev_features_change(efx->net_dev);
656
e8c68c0a 657 /* RX filters may also have scatter-enabled flags */
85740cdf 658 if (efx->rx_scatter != old_rx_scatter)
add72477 659 efx->type->filter_update_rx_scatter(efx);
8ceee660 660
14bf718f
BH		 661 /* We must keep at least one descriptor in a TX ring empty.
662 * We could avoid this when the queue size does not exactly
663 * match the hardware ring size, but it's not that important.
664 * Therefore we stop the queue when one more skb might fill
665 * the ring completely. We wake it when half way back to
666 * empty.
667 */
668 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
669 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
670
8ceee660
BH		 671 /* Initialise the channels */
672 efx_for_each_channel(channel, efx) {
3881d8ab 673 efx_for_each_channel_tx_queue(tx_queue, channel) {
bc3c90a2 674 efx_init_tx_queue(tx_queue);
3881d8ab
AR		 675 atomic_inc(&efx->active_queues);
676 }
8ceee660 677
9f2cb71c 678 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 679 efx_init_rx_queue(rx_queue);
3881d8ab 680 atomic_inc(&efx->active_queues);
cce28794
JC		 681 efx_stop_eventq(channel);
682 efx_fast_push_rx_descriptors(rx_queue, false);
683 efx_start_eventq(channel);
9f2cb71c 684 }
8ceee660 685
85740cdf 686 WARN_ON(channel->rx_pkt_n_frags);
8ceee660 687 }
8ceee660 688
2ea4dc28
AR		 689 efx_ptp_start_datapath(efx);
690
9f2cb71c
BH		 691 if (netif_device_present(efx->net_dev))
692 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH		 693}
694
9f2cb71c 695static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH		 696{
697 struct efx_channel *channel;
698 struct efx_tx_queue *tx_queue;
699 struct efx_rx_queue *rx_queue;
6bc5d3a9 700 int rc;
8ceee660
BH		 701
702 EFX_ASSERT_RESET_SERIALISED(efx);
703 BUG_ON(efx->port_enabled);
704
2ea4dc28
AR		 705 efx_ptp_stop_datapath(efx);
706
d8aec745
BH		 707 /* Stop RX refill */
708 efx_for_each_channel(channel, efx) {
709 efx_for_each_channel_rx_queue(rx_queue, channel)
710 rx_queue->refill_enabled = false;
711 }
712
8ceee660 713 efx_for_each_channel(channel, efx) {
9f2cb71c
BH		 714 /* RX packet processing is pipelined, so wait for the
715 * NAPI handler to complete. At least event queue 0
716 * might be kept active by non-data events, so don't
717 * use napi_synchronize() but actually disable NAPI
718 * temporarily.
719 */
720 if (efx_channel_has_rx_queue(channel)) {
721 efx_stop_eventq(channel);
722 efx_start_eventq(channel);
723 }
e42c3d85 724 }
8ceee660 725
e42c3d85
BH		 726 rc = efx->type->fini_dmaq(efx);
727 if (rc && EFX_WORKAROUND_7803(efx)) {
728 /* Schedule a reset to recover from the flush failure. The
729 * descriptor caches reference memory we're about to free,
730 * but falcon_reconfigure_mac_wrapper() won't reconnect
731 * the MACs because of the pending reset.
732 */
733 netif_err(efx, drv, efx->net_dev,
734 "Resetting to recover from flush failure\n");
735 efx_schedule_reset(efx, RESET_TYPE_ALL);
736 } else if (rc) {
737 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
738 } else {
739 netif_dbg(efx, drv, efx->net_dev,
740 "successfully flushed all queues\n");
741 }
742
743 efx_for_each_channel(channel, efx) {
8ceee660
BH		 744 efx_for_each_channel_rx_queue(rx_queue, channel)
745 efx_fini_rx_queue(rx_queue);
94b274bf 746 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 747 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 748 }
749}
750
751static void efx_remove_channel(struct efx_channel *channel)
752{
753 struct efx_tx_queue *tx_queue;
754 struct efx_rx_queue *rx_queue;
755
62776d03
BH		 756 netif_dbg(channel->efx, drv, channel->efx->net_dev,
757 "destroy chan %d\n", channel->channel);
8ceee660
BH		 758
759 efx_for_each_channel_rx_queue(rx_queue, channel)
760 efx_remove_rx_queue(rx_queue);
94b274bf 761 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH		 762 efx_remove_tx_queue(tx_queue);
763 efx_remove_eventq(channel);
c31e5f9f 764 channel->type->post_remove(channel);
8ceee660
BH		 765}
766
4642610c
BH		 767static void efx_remove_channels(struct efx_nic *efx)
768{
769 struct efx_channel *channel;
770
771 efx_for_each_channel(channel, efx)
772 efx_remove_channel(channel);
773}
774
775int
776efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
777{
778 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
779 u32 old_rxq_entries, old_txq_entries;
7f967c01 780 unsigned i, next_buffer_table = 0;
261e4d96 781 int rc, rc2;
8b7325b4
BH		 782
783 rc = efx_check_disabled(efx);
784 if (rc)
785 return rc;
7f967c01
BH		 786
787 /* Not all channels should be reallocated. We must avoid
788 * reallocating their buffer table entries.
789 */
790 efx_for_each_channel(channel, efx) {
791 struct efx_rx_queue *rx_queue;
792 struct efx_tx_queue *tx_queue;
793
794 if (channel->type->copy)
795 continue;
796 next_buffer_table = max(next_buffer_table,
797 channel->eventq.index +
798 channel->eventq.entries);
799 efx_for_each_channel_rx_queue(rx_queue, channel)
800 next_buffer_table = max(next_buffer_table,
801 rx_queue->rxd.index +
802 rx_queue->rxd.entries);
803 efx_for_each_channel_tx_queue(tx_queue, channel)
804 next_buffer_table = max(next_buffer_table,
805 tx_queue->txd.index +
806 tx_queue->txd.entries);
807 }
4642610c 808
29c69a48 809 efx_device_detach_sync(efx);
4642610c 810 efx_stop_all(efx);
d8291187 811 efx_soft_disable_interrupts(efx);
4642610c 812
7f967c01 813 /* Clone channels (where possible) */
4642610c
BH		 814 memset(other_channel, 0, sizeof(other_channel));
815 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 816 channel = efx->channel[i];
817 if (channel->type->copy)
818 channel = channel->type->copy(channel);
4642610c
BH		 819 if (!channel) {
820 rc = -ENOMEM;
821 goto out;
822 }
823 other_channel[i] = channel;
824 }
825
826 /* Swap entry counts and channel pointers */
827 old_rxq_entries = efx->rxq_entries;
828 old_txq_entries = efx->txq_entries;
829 efx->rxq_entries = rxq_entries;
830 efx->txq_entries = txq_entries;
831 for (i = 0; i < efx->n_channels; i++) {
832 channel = efx->channel[i];
833 efx->channel[i] = other_channel[i];
834 other_channel[i] = channel;
835 }
836
7f967c01
BH		 837 /* Restart buffer table allocation */
838 efx->next_buffer_table = next_buffer_table;
e8f14992 839
e8f14992 840 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 841 channel = efx->channel[i];
842 if (!channel->type->copy)
843 continue;
844 rc = efx_probe_channel(channel);
845 if (rc)
846 goto rollback;
847 efx_init_napi_channel(efx->channel[i]);
e8f14992 848 }
7f967c01 849
4642610c 850out:
7f967c01
BH		 851 /* Destroy unused channel structures */
852 for (i = 0; i < efx->n_channels; i++) {
853 channel = other_channel[i];
854 if (channel && channel->type->copy) {
855 efx_fini_napi_channel(channel);
856 efx_remove_channel(channel);
857 kfree(channel);
858 }
859 }
4642610c 860
261e4d96
JC		 861 rc2 = efx_soft_enable_interrupts(efx);
862 if (rc2) {
863 rc = rc ? rc : rc2;
864 netif_err(efx, drv, efx->net_dev,
865 "unable to restart interrupts on channel reallocation\n");
866 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
867 } else {
868 efx_start_all(efx);
869 netif_device_attach(efx->net_dev);
870 }
4642610c
BH		 871 return rc;
872
873rollback:
874 /* Swap back */
875 efx->rxq_entries = old_rxq_entries;
876 efx->txq_entries = old_txq_entries;
877 for (i = 0; i < efx->n_channels; i++) {
878 channel = efx->channel[i];
879 efx->channel[i] = other_channel[i];
880 other_channel[i] = channel;
881 }
882 goto out;
883}
884
90d683af 885void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 886{
90d683af 887 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH		 888}
889
7f967c01
BH		 890static const struct efx_channel_type efx_default_channel_type = {
891 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 892 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH		 893 .get_name = efx_get_channel_name,
894 .copy = efx_copy_channel,
895 .keep_eventq = false,
896};
897
898int efx_channel_dummy_op_int(struct efx_channel *channel)
899{
900 return 0;
901}
902
c31e5f9f
SH		 903void efx_channel_dummy_op_void(struct efx_channel *channel)
904{
905}
906
8ceee660
BH		 907/**************************************************************************
908 *
909 * Port handling
910 *
911 **************************************************************************/
912
913/* This ensures that the kernel is kept informed (via
914 * netif_carrier_on/off) of the link status, and also maintains the
915 * link status's stop on the port's TX queue.
916 */
fdaa9aed 917void efx_link_status_changed(struct efx_nic *efx)
8ceee660 918{
eb50c0d6
BH		 919 struct efx_link_state *link_state = &efx->link_state;
920
8ceee660
BH		 921 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
922 * that no events are triggered between unregister_netdev() and the
923 * driver unloading. A more general condition is that NETDEV_CHANGE
924 * can only be generated between NETDEV_UP and NETDEV_DOWN */
925 if (!netif_running(efx->net_dev))
926 return;
927
eb50c0d6 928 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 929 efx->n_link_state_changes++;
930
eb50c0d6 931 if (link_state->up)
8ceee660
BH		 932 netif_carrier_on(efx->net_dev);
933 else
934 netif_carrier_off(efx->net_dev);
935 }
936
937 /* Status message for kernel log */
2aa9ef11 938 if (link_state->up)
62776d03 939 netif_info(efx, link, efx->net_dev,
964e6135 940 "link up at %uMbps %s-duplex (MTU %d)\n",
62776d03 941 link_state->speed, link_state->fd ? "full" : "half",
964e6135 942 efx->net_dev->mtu);
2aa9ef11 943 else
62776d03 944 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH		 945}
946
d3245b28
BH		 947void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
948{
949 efx->link_advertising = advertising;
950 if (advertising) {
951 if (advertising & ADVERTISED_Pause)
952 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
953 else
954 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
955 if (advertising & ADVERTISED_Asym_Pause)
956 efx->wanted_fc ^= EFX_FC_TX;
957 }
958}
959
b5626946 960void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH		 961{
962 efx->wanted_fc = wanted_fc;
963 if (efx->link_advertising) {
964 if (wanted_fc & EFX_FC_RX)
965 efx->link_advertising |= (ADVERTISED_Pause |
966 ADVERTISED_Asym_Pause);
967 else
968 efx->link_advertising &= ~(ADVERTISED_Pause |
969 ADVERTISED_Asym_Pause);
970 if (wanted_fc & EFX_FC_TX)
971 efx->link_advertising ^= ADVERTISED_Asym_Pause;
972 }
973}
974
115122af
BH		 975static void efx_fini_port(struct efx_nic *efx);
976
0d322413
EC		 977/* We assume that efx->type->reconfigure_mac will always try to sync RX
978 * filters and therefore needs to read-lock the filter table against freeing
979 */
980void efx_mac_reconfigure(struct efx_nic *efx)
981{
982 down_read(&efx->filter_sem);
983 efx->type->reconfigure_mac(efx);
984 up_read(&efx->filter_sem);
985}
986
d3245b28
BH		 987/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
988 * the MAC appropriately. All other PHY configuration changes are pushed
989 * through phy_op->set_settings(), and pushed asynchronously to the MAC
990 * through efx_monitor().
991 *
992 * Callers must hold the mac_lock
993 */
994int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 995{
d3245b28
BH		 996 enum efx_phy_mode phy_mode;
997 int rc;
8ceee660 998
d3245b28 999 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 1000
d3245b28
BH		 1001 /* Disable PHY transmit in mac level loopbacks */
1002 phy_mode = efx->phy_mode;
177dfcd8
BH		 1003 if (LOOPBACK_INTERNAL(efx))
1004 efx->phy_mode |= PHY_MODE_TX_DISABLED;
1005 else
1006 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 1007
d3245b28 1008 rc = efx->type->reconfigure_port(efx);
8ceee660 1009
d3245b28
BH		 1010 if (rc)
1011 efx->phy_mode = phy_mode;
177dfcd8 1012
d3245b28 1013 return rc;
8ceee660
BH		 1014}
1015
1016/* Reinitialise the MAC to pick up new PHY settings, even if the port is
1017 * disabled. */
d3245b28 1018int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 1019{
d3245b28
BH		 1020 int rc;
1021
8ceee660
BH		 1022 EFX_ASSERT_RESET_SERIALISED(efx);
1023
1024 mutex_lock(&efx->mac_lock);
d3245b28 1025 rc = __efx_reconfigure_port(efx);
8ceee660 1026 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 1027
1028 return rc;
8ceee660
BH		 1029}
1030
8be4f3e6
BH		 1031/* Asynchronous work item for changing MAC promiscuity and multicast
1032 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
1033 * MAC directly. */
766ca0fa
BH		 1034static void efx_mac_work(struct work_struct *data)
1035{
1036 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
1037
1038 mutex_lock(&efx->mac_lock);
30b81cda 1039 if (efx->port_enabled)
0d322413 1040 efx_mac_reconfigure(efx);
766ca0fa
BH		 1041 mutex_unlock(&efx->mac_lock);
1042}
1043
8ceee660
BH		 1044static int efx_probe_port(struct efx_nic *efx)
1045{
1046 int rc;
1047
62776d03 1048 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 1049
ff3b00a0
SH		 1050 if (phy_flash_cfg)
1051 efx->phy_mode = PHY_MODE_SPECIAL;
1052
ef2b90ee
BH		 1053 /* Connect up MAC/PHY operations table */
1054 rc = efx->type->probe_port(efx);
8ceee660 1055 if (rc)
e42de262 1056 return rc;
8ceee660 1057
e332bcb3 1058 /* Initialise MAC address to permanent address */
cd84ff4d 1059 ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr);
8ceee660
BH		 1060
1061 return 0;
8ceee660
BH		 1062}
1063
1064static int efx_init_port(struct efx_nic *efx)
1065{
1066 int rc;
1067
62776d03 1068 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 1069
1dfc5cea
BH		 1070 mutex_lock(&efx->mac_lock);
1071
177dfcd8 1072 rc = efx->phy_op->init(efx);
8ceee660 1073 if (rc)
1dfc5cea 1074 goto fail1;
8ceee660 1075
dc8cfa55 1076 efx->port_initialized = true;
1dfc5cea 1077
d3245b28
BH		 1078 /* Reconfigure the MAC before creating dma queues (required for
1079 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
0d322413 1080 efx_mac_reconfigure(efx);
d3245b28
BH		 1081
1082 /* Ensure the PHY advertises the correct flow control settings */
1083 rc = efx->phy_op->reconfigure(efx);
267d9d73 1084 if (rc && rc != -EPERM)
d3245b28
BH		 1085 goto fail2;
1086
1dfc5cea 1087 mutex_unlock(&efx->mac_lock);
8ceee660 1088 return 0;
177dfcd8 1089
1dfc5cea 1090fail2:
177dfcd8 1091 efx->phy_op->fini(efx);
1dfc5cea
BH		 1092fail1:
1093 mutex_unlock(&efx->mac_lock);
177dfcd8 1094 return rc;
8ceee660
BH		 1095}
1096
8ceee660
BH		 1097static void efx_start_port(struct efx_nic *efx)
1098{
62776d03 1099 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH		 1100 BUG_ON(efx->port_enabled);
1101
1102 mutex_lock(&efx->mac_lock);
dc8cfa55 1103 efx->port_enabled = true;
8be4f3e6 1104
d615c039 1105 /* Ensure MAC ingress/egress is enabled */
0d322413 1106 efx_mac_reconfigure(efx);
8be4f3e6 1107
8ceee660
BH		 1108 mutex_unlock(&efx->mac_lock);
1109}
1110
d615c039
BH		 1111/* Cancel work for MAC reconfiguration, periodic hardware monitoring
1112 * and the async self-test, wait for them to finish and prevent them
1113 * being scheduled again. This doesn't cover online resets, which
1114 * should only be cancelled when removing the device.
1115 */
8ceee660
BH		 1116static void efx_stop_port(struct efx_nic *efx)
1117{
62776d03 1118 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660 1119
d615c039
BH		 1120 EFX_ASSERT_RESET_SERIALISED(efx);
1121
8ceee660 1122 mutex_lock(&efx->mac_lock);
dc8cfa55 1123 efx->port_enabled = false;
8ceee660
BH		 1124 mutex_unlock(&efx->mac_lock);
1125
1126 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH		 1127 netif_addr_lock_bh(efx->net_dev);
1128 netif_addr_unlock_bh(efx->net_dev);
d615c039
BH		 1129
1130 cancel_delayed_work_sync(&efx->monitor_work);
1131 efx_selftest_async_cancel(efx);
1132 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1133}
1134
1135static void efx_fini_port(struct efx_nic *efx)
1136{
62776d03 1137 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH		 1138
1139 if (!efx->port_initialized)
1140 return;
1141
177dfcd8 1142 efx->phy_op->fini(efx);
dc8cfa55 1143 efx->port_initialized = false;
8ceee660 1144
eb50c0d6 1145 efx->link_state.up = false;
8ceee660
BH		 1146 efx_link_status_changed(efx);
1147}
1148
1149static void efx_remove_port(struct efx_nic *efx)
1150{
62776d03 1151 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1152
ef2b90ee 1153 efx->type->remove_port(efx);
8ceee660
BH		 1154}
1155
1156/**************************************************************************
1157 *
1158 * NIC handling
1159 *
1160 **************************************************************************/
1161
0bcf4a64
BH		 1162static LIST_HEAD(efx_primary_list);
1163static LIST_HEAD(efx_unassociated_list);
1164
1165static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right)
1166{
1167 return left->type == right->type &&
1168 left->vpd_sn && right->vpd_sn &&
1169 !strcmp(left->vpd_sn, right->vpd_sn);
1170}
1171
1172static void efx_associate(struct efx_nic *efx)
1173{
1174 struct efx_nic *other, *next;
1175
1176 if (efx->primary == efx) {
1177 /* Adding primary function; look for secondaries */
1178
1179 netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n");
1180 list_add_tail(&efx->node, &efx_primary_list);
1181
1182 list_for_each_entry_safe(other, next, &efx_unassociated_list,
1183 node) {
1184 if (efx_same_controller(efx, other)) {
1185 list_del(&other->node);
1186 netif_dbg(other, probe, other->net_dev,
1187 "moving to secondary list of %s %s\n",
1188 pci_name(efx->pci_dev),
1189 efx->net_dev->name);
1190 list_add_tail(&other->node,
1191 &efx->secondary_list);
1192 other->primary = efx;
1193 }
1194 }
1195 } else {
1196 /* Adding secondary function; look for primary */
1197
1198 list_for_each_entry(other, &efx_primary_list, node) {
1199 if (efx_same_controller(efx, other)) {
1200 netif_dbg(efx, probe, efx->net_dev,
1201 "adding to secondary list of %s %s\n",
1202 pci_name(other->pci_dev),
1203 other->net_dev->name);
1204 list_add_tail(&efx->node,
1205 &other->secondary_list);
1206 efx->primary = other;
1207 return;
1208 }
1209 }
1210
1211 netif_dbg(efx, probe, efx->net_dev,
1212 "adding to unassociated list\n");
1213 list_add_tail(&efx->node, &efx_unassociated_list);
1214 }
1215}
1216
1217static void efx_dissociate(struct efx_nic *efx)
1218{
1219 struct efx_nic *other, *next;
1220
1221 list_del(&efx->node);
1222 efx->primary = NULL;
1223
1224 list_for_each_entry_safe(other, next, &efx->secondary_list, node) {
1225 list_del(&other->node);
1226 netif_dbg(other, probe, other->net_dev,
1227 "moving to unassociated list\n");
1228 list_add_tail(&other->node, &efx_unassociated_list);
1229 other->primary = NULL;
1230 }
1231}
1232
8ceee660
BH		 1233/* This configures the PCI device to enable I/O and DMA. */
1234static int efx_init_io(struct efx_nic *efx)
1235{
1236 struct pci_dev *pci_dev = efx->pci_dev;
1237 dma_addr_t dma_mask = efx->type->max_dma_mask;
b105798f 1238 unsigned int mem_map_size = efx->type->mem_map_size(efx);
02246a7f 1239 int rc, bar;
8ceee660 1240
62776d03 1241 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660 1242
02246a7f
SS		 1243 bar = efx->type->mem_bar;
1244
8ceee660
BH		 1245 rc = pci_enable_device(pci_dev);
1246 if (rc) {
62776d03
BH		 1247 netif_err(efx, probe, efx->net_dev,
1248 "failed to enable PCI device\n");
8ceee660
BH		 1249 goto fail1;
1250 }
1251
1252 pci_set_master(pci_dev);
1253
1254 /* Set the PCI DMA mask. Try all possibilities from our
1255 * genuine mask down to 32 bits, because some architectures
1256 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1257 * masks event though they reject 46 bit masks.
1258 */
1259 while (dma_mask > 0x7fffffffUL) {
8722b8fb
CH		 1260 rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask);
1261 if (rc == 0)
1262 break;
8ceee660
BH		 1263 dma_mask >>= 1;
1264 }
1265 if (rc) {
62776d03
BH		 1266 netif_err(efx, probe, efx->net_dev,
1267 "could not find a suitable DMA mask\n");
8ceee660
BH		 1268 goto fail2;
1269 }
62776d03
BH		 1270 netif_dbg(efx, probe, efx->net_dev,
1271 "using DMA mask %llx\n", (unsigned long long) dma_mask);
8ceee660 1272
02246a7f
SS		 1273 efx->membase_phys = pci_resource_start(efx->pci_dev, bar);
1274 rc = pci_request_region(pci_dev, bar, "sfc");
8ceee660 1275 if (rc) {
62776d03
BH		 1276 netif_err(efx, probe, efx->net_dev,
1277 "request for memory BAR failed\n");
8ceee660
BH		 1278 rc = -EIO;
1279 goto fail3;
1280 }
b105798f 1281 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
8ceee660 1282 if (!efx->membase) {
62776d03
BH		 1283 netif_err(efx, probe, efx->net_dev,
1284 "could not map memory BAR at %llx+%x\n",
b105798f 1285 (unsigned long long)efx->membase_phys, mem_map_size);
8ceee660
BH		 1286 rc = -ENOMEM;
1287 goto fail4;
1288 }
62776d03
BH		 1289 netif_dbg(efx, probe, efx->net_dev,
1290 "memory BAR at %llx+%x (virtual %p)\n",
b105798f
BH		 1291 (unsigned long long)efx->membase_phys, mem_map_size,
1292 efx->membase);
8ceee660
BH		 1293
1294 return 0;
1295
1296 fail4:
02246a7f 1297 pci_release_region(efx->pci_dev, bar);
8ceee660 1298 fail3:
2c118e0f 1299 efx->membase_phys = 0;
8ceee660
BH		 1300 fail2:
1301 pci_disable_device(efx->pci_dev);
1302 fail1:
1303 return rc;
1304}
1305
1306static void efx_fini_io(struct efx_nic *efx)
1307{
02246a7f
SS		 1308 int bar;
1309
62776d03 1310 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH		 1311
1312 if (efx->membase) {
1313 iounmap(efx->membase);
1314 efx->membase = NULL;
1315 }
1316
1317 if (efx->membase_phys) {
02246a7f
SS		 1318 bar = efx->type->mem_bar;
1319 pci_release_region(efx->pci_dev, bar);
2c118e0f 1320 efx->membase_phys = 0;
8ceee660
BH		 1321 }
1322
6598dad2
DP		 1323 /* Don't disable bus-mastering if VFs are assigned */
1324 if (!pci_vfs_assigned(efx->pci_dev))
1325 pci_disable_device(efx->pci_dev);
8ceee660
BH		 1326}
1327
267c0157
JC		 1328void efx_set_default_rx_indir_table(struct efx_nic *efx)
1329{
1330 size_t i;
1331
1332 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
1333 efx->rx_indir_table[i] =
1334 ethtool_rxfh_indir_default(i, efx->rss_spread);
8ceee660
BH		 1335}
1336
a9a52506 1337static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1338{
cdb08f8f 1339 cpumask_var_t thread_mask;
a16e5b24 1340 unsigned int count;
46123d04 1341 int cpu;
5b874e25 1342
cd2d5b52
BH		 1343 if (rss_cpus) {
1344 count = rss_cpus;
1345 } else {
1346 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1347 netif_warn(efx, probe, efx->net_dev,
1348 "RSS disabled due to allocation failure\n");
1349 return 1;
1350 }
46123d04 1351
cd2d5b52
BH		 1352 count = 0;
1353 for_each_online_cpu(cpu) {
1354 if (!cpumask_test_cpu(cpu, thread_mask)) {
1355 ++count;
1356 cpumask_or(thread_mask, thread_mask,
06931e62 1357 topology_sibling_cpumask(cpu));
cd2d5b52
BH		 1358 }
1359 }
1360
1361 free_cpumask_var(thread_mask);
2f8975fb
RR		 1362 }
1363
cd2d5b52
BH		 1364 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1365 * table entries that are inaccessible to VFs
1366 */
7fa8d547
SS		 1367#ifdef CONFIG_SFC_SRIOV
1368 if (efx->type->sriov_wanted) {
1369 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1370 count > efx_vf_size(efx)) {
1371 netif_warn(efx, probe, efx->net_dev,
1372 "Reducing number of RSS channels from %u to %u for "
1373 "VF support. Increase vf-msix-limit to use more "
1374 "channels on the PF.\n",
1375 count, efx_vf_size(efx));
1376 count = efx_vf_size(efx);
1377 }
46123d04 1378 }
7fa8d547 1379#endif
46123d04
BH		 1380
1381 return count;
1382}
1383
1384/* Probe the number and type of interrupts we are able to obtain, and
1385 * the resulting numbers of channels and RX queues.
1386 */
64d8ad6d 1387static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1388{
7f967c01
BH		 1389 unsigned int extra_channels = 0;
1390 unsigned int i, j;
a16e5b24 1391 int rc;
8ceee660 1392
7f967c01
BH		 1393 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1394 if (efx->extra_channel_type[i])
1395 ++extra_channels;
1396
8ceee660 1397 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1398 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1399 unsigned int n_channels;
aa6ef27e 1400
a9a52506 1401 n_channels = efx_wanted_parallelism(efx);
b0fbdae1 1402 if (efx_separate_tx_channels)
a4900ac9 1403 n_channels *= 2;
7f967c01 1404 n_channels += extra_channels;
b105798f 1405 n_channels = min(n_channels, efx->max_channels);
8ceee660 1406
a4900ac9 1407 for (i = 0; i < n_channels; i++)
8ceee660 1408 xentries[i].entry = i;
184603d8
AG		 1409 rc = pci_enable_msix_range(efx->pci_dev,
1410 xentries, 1, n_channels);
1411 if (rc < 0) {
1412 /* Fall back to single channel MSI */
1413 efx->interrupt_mode = EFX_INT_MODE_MSI;
1414 netif_err(efx, drv, efx->net_dev,
1415 "could not enable MSI-X\n");
1416 } else if (rc < n_channels) {
62776d03
BH		 1417 netif_err(efx, drv, efx->net_dev,
1418 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1419 " available (%d < %u).\n", rc, n_channels);
62776d03
BH		 1420 netif_err(efx, drv, efx->net_dev,
1421 "WARNING: Performance may be reduced.\n");
a4900ac9 1422 n_channels = rc;
8ceee660
BH		 1423 }
1424
184603d8 1425 if (rc > 0) {
a4900ac9 1426 efx->n_channels = n_channels;
7f967c01
BH		 1427 if (n_channels > extra_channels)
1428 n_channels -= extra_channels;
b0fbdae1
SS		 1429 if (efx_separate_tx_channels) {
1430 efx->n_tx_channels = min(max(n_channels / 2,
1431 1U),
1432 efx->max_tx_channels);
7f967c01
BH		 1433 efx->n_rx_channels = max(n_channels -
1434 efx->n_tx_channels,
1435 1U);
a4900ac9 1436 } else {
b0fbdae1
SS		 1437 efx->n_tx_channels = min(n_channels,
1438 efx->max_tx_channels);
7f967c01 1439 efx->n_rx_channels = n_channels;
a4900ac9 1440 }
7f967c01 1441 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH		 1442 efx_get_channel(efx, i)->irq =
1443 xentries[i].vector;
8ceee660
BH		 1444 }
1445 }
1446
1447 /* Try single interrupt MSI */
1448 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1449 efx->n_channels = 1;
a4900ac9
BH		 1450 efx->n_rx_channels = 1;
1451 efx->n_tx_channels = 1;
8ceee660
BH		 1452 rc = pci_enable_msi(efx->pci_dev);
1453 if (rc == 0) {
f7d12cdc 1454 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1455 } else {
62776d03
BH		 1456 netif_err(efx, drv, efx->net_dev,
1457 "could not enable MSI\n");
8ceee660
BH		 1458 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1459 }
1460 }
1461
1462 /* Assume legacy interrupts */
1463 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
b0fbdae1 1464 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0);
a4900ac9
BH		 1465 efx->n_rx_channels = 1;
1466 efx->n_tx_channels = 1;
8ceee660
BH		 1467 efx->legacy_irq = efx->pci_dev->irq;
1468 }
64d8ad6d 1469
7f967c01
BH		 1470 /* Assign extra channels if possible */
1471 j = efx->n_channels;
1472 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1473 if (!efx->extra_channel_type[i])
1474 continue;
1475 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1476 efx->n_channels <= extra_channels) {
1477 efx->extra_channel_type[i]->handle_no_channel(efx);
1478 } else {
1479 --j;
1480 efx_get_channel(efx, j)->type =
1481 efx->extra_channel_type[i];
1482 }
1483 }
1484
cd2d5b52 1485 /* RSS might be usable on VFs even if it is disabled on the PF */
7fa8d547
SS		 1486#ifdef CONFIG_SFC_SRIOV
1487 if (efx->type->sriov_wanted) {
1488 efx->rss_spread = ((efx->n_rx_channels > 1 ||
1489 !efx->type->sriov_wanted(efx)) ?
1490 efx->n_rx_channels : efx_vf_size(efx));
1491 return 0;
1492 }
1493#endif
1494 efx->rss_spread = efx->n_rx_channels;
cd2d5b52 1495
64d8ad6d 1496 return 0;
8ceee660
BH		 1497}
1498
261e4d96 1499static int efx_soft_enable_interrupts(struct efx_nic *efx)
9f2cb71c 1500{
261e4d96
JC		 1501 struct efx_channel *channel, *end_channel;
1502 int rc;
9f2cb71c 1503
8b7325b4
BH		 1504 BUG_ON(efx->state == STATE_DISABLED);
1505
d8291187
BH		 1506 efx->irq_soft_enabled = true;
1507 smp_wmb();
9f2cb71c
BH		 1508
1509 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1510 if (!channel->type->keep_eventq) {
1511 rc = efx_init_eventq(channel);
1512 if (rc)
1513 goto fail;
1514 }
9f2cb71c
BH		 1515 efx_start_eventq(channel);
1516 }
1517
1518 efx_mcdi_mode_event(efx);
261e4d96
JC		 1519
1520 return 0;
1521fail:
1522 end_channel = channel;
1523 efx_for_each_channel(channel, efx) {
1524 if (channel == end_channel)
1525 break;
1526 efx_stop_eventq(channel);
1527 if (!channel->type->keep_eventq)
1528 efx_fini_eventq(channel);
1529 }
1530
1531 return rc;
9f2cb71c
BH		 1532}
1533
d8291187 1534static void efx_soft_disable_interrupts(struct efx_nic *efx)
9f2cb71c
BH		 1535{
1536 struct efx_channel *channel;
1537
8b7325b4
BH		 1538 if (efx->state == STATE_DISABLED)
1539 return;
1540
9f2cb71c
BH		 1541 efx_mcdi_mode_poll(efx);
1542
d8291187
BH		 1543 efx->irq_soft_enabled = false;
1544 smp_wmb();
1545
1546 if (efx->legacy_irq)
9f2cb71c 1547 synchronize_irq(efx->legacy_irq);
9f2cb71c
BH		 1548
1549 efx_for_each_channel(channel, efx) {
1550 if (channel->irq)
1551 synchronize_irq(channel->irq);
1552
1553 efx_stop_eventq(channel);
d8291187 1554 if (!channel->type->keep_eventq)
7f967c01 1555 efx_fini_eventq(channel);
9f2cb71c 1556 }
cade715f
BH		 1557
1558 /* Flush the asynchronous MCDI request queue */
1559 efx_mcdi_flush_async(efx);
9f2cb71c
BH		 1560}
1561
261e4d96 1562static int efx_enable_interrupts(struct efx_nic *efx)
d8291187 1563{
261e4d96
JC		 1564 struct efx_channel *channel, *end_channel;
1565 int rc;
d8291187
BH		 1566
1567 BUG_ON(efx->state == STATE_DISABLED);
1568
1569 if (efx->eeh_disabled_legacy_irq) {
1570 enable_irq(efx->legacy_irq);
1571 efx->eeh_disabled_legacy_irq = false;
1572 }
1573
86094f7f 1574 efx->type->irq_enable_master(efx);
d8291187
BH		 1575
1576 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1577 if (channel->type->keep_eventq) {
1578 rc = efx_init_eventq(channel);
1579 if (rc)
1580 goto fail;
1581 }
1582 }
1583
1584 rc = efx_soft_enable_interrupts(efx);
1585 if (rc)
1586 goto fail;
1587
1588 return 0;
1589
1590fail:
1591 end_channel = channel;
1592 efx_for_each_channel(channel, efx) {
1593 if (channel == end_channel)
1594 break;
d8291187 1595 if (channel->type->keep_eventq)
261e4d96 1596 efx_fini_eventq(channel);
d8291187
BH		 1597 }
1598
261e4d96
JC		 1599 efx->type->irq_disable_non_ev(efx);
1600
1601 return rc;
d8291187
BH		 1602}
1603
1604static void efx_disable_interrupts(struct efx_nic *efx)
1605{
1606 struct efx_channel *channel;
1607
1608 efx_soft_disable_interrupts(efx);
1609
1610 efx_for_each_channel(channel, efx) {
1611 if (channel->type->keep_eventq)
1612 efx_fini_eventq(channel);
1613 }
1614
86094f7f 1615 efx->type->irq_disable_non_ev(efx);
d8291187
BH		 1616}
1617
8ceee660
BH		 1618static void efx_remove_interrupts(struct efx_nic *efx)
1619{
1620 struct efx_channel *channel;
1621
1622 /* Remove MSI/MSI-X interrupts */
64ee3120 1623 efx_for_each_channel(channel, efx)
8ceee660
BH		 1624 channel->irq = 0;
1625 pci_disable_msi(efx->pci_dev);
1626 pci_disable_msix(efx->pci_dev);
1627
1628 /* Remove legacy interrupt */
1629 efx->legacy_irq = 0;
1630}
1631
8831da7b 1632static void efx_set_channels(struct efx_nic *efx)
8ceee660 1633{
602a5322
BH		 1634 struct efx_channel *channel;
1635 struct efx_tx_queue *tx_queue;
1636
97653431 1637 efx->tx_channel_offset =
b0fbdae1
SS		 1638 efx_separate_tx_channels ?
1639 efx->n_channels - efx->n_tx_channels : 0;
602a5322 1640
79d68b37
SH		 1641 /* We need to mark which channels really have RX and TX
1642 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH		 1643 * RX-only and TX-only channels.
1644 */
1645 efx_for_each_channel(channel, efx) {
79d68b37
SH		 1646 if (channel->channel < efx->n_rx_channels)
1647 channel->rx_queue.core_index = channel->channel;
1648 else
1649 channel->rx_queue.core_index = -1;
1650
602a5322
BH		 1651 efx_for_each_channel_tx_queue(tx_queue, channel)
1652 tx_queue->queue -= (efx->tx_channel_offset *
1653 EFX_TXQ_TYPES);
1654 }
8ceee660
BH		 1655}
1656
1657static int efx_probe_nic(struct efx_nic *efx)
1658{
1659 int rc;
1660
62776d03 1661 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH		 1662
1663 /* Carry out hardware-type specific initialisation */
ef2b90ee 1664 rc = efx->type->probe(efx);
8ceee660
BH		 1665 if (rc)
1666 return rc;
1667
b0fbdae1
SS		 1668 do {
1669 if (!efx->max_channels || !efx->max_tx_channels) {
1670 netif_err(efx, drv, efx->net_dev,
1671 "Insufficient resources to allocate"
1672 " any channels\n");
1673 rc = -ENOSPC;
1674 goto fail1;
1675 }
8ceee660 1676
b0fbdae1
SS		 1677 /* Determine the number of channels and queues by trying
1678 * to hook in MSI-X interrupts.
1679 */
1680 rc = efx_probe_interrupts(efx);
1681 if (rc)
1682 goto fail1;
52ad762b 1683
b0fbdae1
SS		 1684 efx_set_channels(efx);
1685
1686 /* dimension_resources can fail with EAGAIN */
1687 rc = efx->type->dimension_resources(efx);
1688 if (rc != 0 && rc != -EAGAIN)
1689 goto fail2;
1690
1691 if (rc == -EAGAIN)
1692 /* try again with new max_channels */
1693 efx_remove_interrupts(efx);
1694
1695 } while (rc == -EAGAIN);
28e47c49 1696
5d3a6fca 1697 if (efx->n_channels > 1)
267c0157
JC		 1698 netdev_rss_key_fill(&efx->rx_hash_key,
1699 sizeof(efx->rx_hash_key));
1700 efx_set_default_rx_indir_table(efx);
5d3a6fca 1701
c4f4adc7
BH		 1702 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1703 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH		 1704
1705 /* Initialise the interrupt moderation settings */
9e393b30
BH		 1706 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1707 true);
8ceee660
BH		 1708
1709 return 0;
64d8ad6d 1710
c15eed22
BH		 1711fail2:
1712 efx_remove_interrupts(efx);
1713fail1:
64d8ad6d
BH		 1714 efx->type->remove(efx);
1715 return rc;
8ceee660
BH		 1716}
1717
1718static void efx_remove_nic(struct efx_nic *efx)
1719{
62776d03 1720 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH		 1721
1722 efx_remove_interrupts(efx);
ef2b90ee 1723 efx->type->remove(efx);
8ceee660
BH		 1724}
1725
add72477
BH		 1726static int efx_probe_filters(struct efx_nic *efx)
1727{
1728 int rc;
1729
1730 spin_lock_init(&efx->filter_lock);
0d322413
EC		 1731 init_rwsem(&efx->filter_sem);
1732 down_write(&efx->filter_sem);
add72477
BH		 1733 rc = efx->type->filter_table_probe(efx);
1734 if (rc)
0d322413 1735 goto out_unlock;
add72477
BH		 1736
1737#ifdef CONFIG_RFS_ACCEL
1738 if (efx->type->offload_features & NETIF_F_NTUPLE) {
faf8dcc1
JC		 1739 struct efx_channel *channel;
1740 int i, success = 1;
1741
1742 efx_for_each_channel(channel, efx) {
1743 channel->rps_flow_id =
1744 kcalloc(efx->type->max_rx_ip_filters,
1745 sizeof(*channel->rps_flow_id),
1746 GFP_KERNEL);
1747 if (!channel->rps_flow_id)
1748 success = 0;
1749 else
1750 for (i = 0;
1751 i < efx->type->max_rx_ip_filters;
1752 ++i)
1753 channel->rps_flow_id[i] =
1754 RPS_FLOW_ID_INVALID;
1755 }
1756
1757 if (!success) {
1758 efx_for_each_channel(channel, efx)
1759 kfree(channel->rps_flow_id);
add72477 1760 efx->type->filter_table_remove(efx);
0d322413
EC		 1761 rc = -ENOMEM;
1762 goto out_unlock;
add72477 1763 }
faf8dcc1
JC		 1764
1765 efx->rps_expire_index = efx->rps_expire_channel = 0;
add72477
BH		 1766 }
1767#endif
0d322413
EC		 1768out_unlock:
1769 up_write(&efx->filter_sem);
1770 return rc;
add72477
BH		 1771}
1772
1773static void efx_remove_filters(struct efx_nic *efx)
1774{
1775#ifdef CONFIG_RFS_ACCEL
faf8dcc1
JC		 1776 struct efx_channel *channel;
1777
1778 efx_for_each_channel(channel, efx)
1779 kfree(channel->rps_flow_id);
add72477 1780#endif
0d322413 1781 down_write(&efx->filter_sem);
add72477 1782 efx->type->filter_table_remove(efx);
0d322413 1783 up_write(&efx->filter_sem);
add72477
BH		 1784}
1785
1786static void efx_restore_filters(struct efx_nic *efx)
1787{
0d322413 1788 down_read(&efx->filter_sem);
add72477 1789 efx->type->filter_table_restore(efx);
0d322413 1790 up_read(&efx->filter_sem);
add72477
BH		 1791}
1792
8ceee660
BH		 1793/**************************************************************************
1794 *
1795 * NIC startup/shutdown
1796 *
1797 *************************************************************************/
1798
1799static int efx_probe_all(struct efx_nic *efx)
1800{
8ceee660
BH		 1801 int rc;
1802
8ceee660
BH		 1803 rc = efx_probe_nic(efx);
1804 if (rc) {
62776d03 1805 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH		 1806 goto fail1;
1807 }
1808
8ceee660
BH		 1809 rc = efx_probe_port(efx);
1810 if (rc) {
62776d03 1811 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH		 1812 goto fail2;
1813 }
1814
7e6d06f0
BH		 1815 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1816 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1817 rc = -EINVAL;
1818 goto fail3;
1819 }
ecc910f5 1820 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1821
6d8aaaf6
DP		 1822#ifdef CONFIG_SFC_SRIOV
1823 rc = efx->type->vswitching_probe(efx);
1824 if (rc) /* not fatal; the PF will still work fine */
1825 netif_warn(efx, probe, efx->net_dev,
1826 "failed to setup vswitching rc=%d;"
1827 " VFs may not function\n", rc);
1828#endif
1829
64eebcfd
BH		 1830 rc = efx_probe_filters(efx);
1831 if (rc) {
1832 netif_err(efx, probe, efx->net_dev,
1833 "failed to create filter tables\n");
6d8aaaf6 1834 goto fail4;
64eebcfd
BH		 1835 }
1836
7f967c01
BH		 1837 rc = efx_probe_channels(efx);
1838 if (rc)
6d8aaaf6 1839 goto fail5;
7f967c01 1840
8ceee660
BH		 1841 return 0;
1842
6d8aaaf6 1843 fail5:
7f967c01 1844 efx_remove_filters(efx);
6d8aaaf6
DP		 1845 fail4:
1846#ifdef CONFIG_SFC_SRIOV
1847 efx->type->vswitching_remove(efx);
1848#endif
8ceee660 1849 fail3:
8ceee660
BH		 1850 efx_remove_port(efx);
1851 fail2:
1852 efx_remove_nic(efx);
1853 fail1:
1854 return rc;
1855}
1856
8b7325b4
BH		 1857/* If the interface is supposed to be running but is not, start
1858 * the hardware and software data path, regular activity for the port
1859 * (MAC statistics, link polling, etc.) and schedule the port to be
1860 * reconfigured. Interrupts must already be enabled. This function
1861 * is safe to call multiple times, so long as the NIC is not disabled.
1862 * Requires the RTNL lock.
9f2cb71c 1863 */
8ceee660
BH		 1864static void efx_start_all(struct efx_nic *efx)
1865{
8ceee660 1866 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1867 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH		 1868
1869 /* Check that it is appropriate to restart the interface. All
1870 * of these flags are safe to read under just the rtnl lock */
e283546c
EC		 1871 if (efx->port_enabled || !netif_running(efx->net_dev) ||
1872 efx->reset_pending)
8ceee660
BH		 1873 return;
1874
8ceee660 1875 efx_start_port(efx);
9f2cb71c 1876 efx_start_datapath(efx);
8880f4ec 1877
626950db
AR		 1878 /* Start the hardware monitor if there is one */
1879 if (efx->type->monitor != NULL)
8ceee660
BH		 1880 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1881 efx_monitor_interval);
626950db
AR		 1882
1883 /* If link state detection is normally event-driven, we have
1884 * to poll now because we could have missed a change
1885 */
1886 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
78c1f0a0
SH		 1887 mutex_lock(&efx->mac_lock);
1888 if (efx->phy_op->poll(efx))
1889 efx_link_status_changed(efx);
1890 mutex_unlock(&efx->mac_lock);
1891 }
55edc6e6 1892
ef2b90ee 1893 efx->type->start_stats(efx);
f8f3b5ae
JC		 1894 efx->type->pull_stats(efx);
1895 spin_lock_bh(&efx->stats_lock);
1896 efx->type->update_stats(efx, NULL, NULL);
1897 spin_unlock_bh(&efx->stats_lock);
8ceee660
BH		 1898}
1899
8b7325b4
BH		 1900/* Quiesce the hardware and software data path, and regular activity
1901 * for the port without bringing the link down. Safe to call multiple
1902 * times with the NIC in almost any state, but interrupts should be
1903 * enabled. Requires the RTNL lock.
1904 */
8ceee660
BH		 1905static void efx_stop_all(struct efx_nic *efx)
1906{
8ceee660
BH		 1907 EFX_ASSERT_RESET_SERIALISED(efx);
1908
1909 /* port_enabled can be read safely under the rtnl lock */
1910 if (!efx->port_enabled)
1911 return;
1912
f8f3b5ae
JC		 1913 /* update stats before we go down so we can accurately count
1914 * rx_nodesc_drops
1915 */
1916 efx->type->pull_stats(efx);
1917 spin_lock_bh(&efx->stats_lock);
1918 efx->type->update_stats(efx, NULL, NULL);
1919 spin_unlock_bh(&efx->stats_lock);
ef2b90ee 1920 efx->type->stop_stats(efx);
8ceee660
BH		 1921 efx_stop_port(efx);
1922
29c69a48
BH		 1923 /* Stop the kernel transmit interface. This is only valid if
1924 * the device is stopped or detached; otherwise the watchdog
1925 * may fire immediately.
1926 */
1927 WARN_ON(netif_running(efx->net_dev) &&
1928 netif_device_present(efx->net_dev));
9f2cb71c
BH		 1929 netif_tx_disable(efx->net_dev);
1930
1931 efx_stop_datapath(efx);
8ceee660
BH		 1932}
1933
1934static void efx_remove_all(struct efx_nic *efx)
1935{
4642610c 1936 efx_remove_channels(efx);
7f967c01 1937 efx_remove_filters(efx);
6d8aaaf6
DP		 1938#ifdef CONFIG_SFC_SRIOV
1939 efx->type->vswitching_remove(efx);
1940#endif
8ceee660
BH		 1941 efx_remove_port(efx);
1942 efx_remove_nic(efx);
1943}
1944
8ceee660
BH		 1945/**************************************************************************
1946 *
1947 * Interrupt moderation
1948 *
1949 **************************************************************************/
1950
cc180b69 1951static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
0d86ebd8 1952{
b548f976
BH		 1953 if (usecs == 0)
1954 return 0;
cc180b69 1955 if (usecs * 1000 < quantum_ns)
0d86ebd8 1956 return 1; /* never round down to 0 */
cc180b69 1957 return usecs * 1000 / quantum_ns;
0d86ebd8
BH		 1958}
1959
8ceee660 1960/* Set interrupt moderation parameters */
9e393b30
BH		 1961int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1962 unsigned int rx_usecs, bool rx_adaptive,
1963 bool rx_may_override_tx)
8ceee660 1964{
f7d12cdc 1965 struct efx_channel *channel;
cc180b69
BH		 1966 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1967 efx->timer_quantum_ns,
1968 1000);
1969 unsigned int tx_ticks;
1970 unsigned int rx_ticks;
8ceee660
BH		 1971
1972 EFX_ASSERT_RESET_SERIALISED(efx);
1973
cc180b69 1974 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
9e393b30
BH		 1975 return -EINVAL;
1976
cc180b69
BH		 1977 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1978 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1979
9e393b30
BH		 1980 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1981 !rx_may_override_tx) {
1982 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1983 "RX and TX IRQ moderation must be equal\n");
1984 return -EINVAL;
1985 }
1986
6fb70fd1 1987 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1988 efx->irq_rx_moderation = rx_ticks;
f7d12cdc 1989 efx_for_each_channel(channel, efx) {
525da907 1990 if (efx_channel_has_rx_queue(channel))
f7d12cdc 1991 channel->irq_moderation = rx_ticks;
525da907 1992 else if (efx_channel_has_tx_queues(channel))
f7d12cdc
BH		 1993 channel->irq_moderation = tx_ticks;
1994 }
9e393b30
BH		 1995
1996 return 0;
8ceee660
BH		 1997}
1998
a0c4faf5
BH		 1999void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
2000 unsigned int *rx_usecs, bool *rx_adaptive)
2001{
cc180b69
BH		 2002 /* We must round up when converting ticks to microseconds
2003 * because we round down when converting the other way.
2004 */
2005
a0c4faf5 2006 *rx_adaptive = efx->irq_rx_adaptive;
cc180b69
BH		 2007 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
2008 efx->timer_quantum_ns,
2009 1000);
a0c4faf5
BH		 2010
2011 /* If channels are shared between RX and TX, so is IRQ
2012 * moderation. Otherwise, IRQ moderation is the same for all
2013 * TX channels and is not adaptive.
2014 */
2015 if (efx->tx_channel_offset == 0)
2016 *tx_usecs = *rx_usecs;
2017 else
cc180b69 2018 *tx_usecs = DIV_ROUND_UP(
a0c4faf5 2019 efx->channel[efx->tx_channel_offset]->irq_moderation *
cc180b69
BH		 2020 efx->timer_quantum_ns,
2021 1000);
a0c4faf5
BH		 2022}
2023
8ceee660
BH		 2024/**************************************************************************
2025 *
2026 * Hardware monitor
2027 *
2028 **************************************************************************/
2029
e254c274 2030/* Run periodically off the general workqueue */
8ceee660
BH		 2031static void efx_monitor(struct work_struct *data)
2032{
2033 struct efx_nic *efx = container_of(data, struct efx_nic,
2034 monitor_work.work);
8ceee660 2035
62776d03
BH		 2036 netif_vdbg(efx, timer, efx->net_dev,
2037 "hardware monitor executing on CPU %d\n",
2038 raw_smp_processor_id());
ef2b90ee 2039 BUG_ON(efx->type->monitor == NULL);
8ceee660 2040
8ceee660
BH		 2041 /* If the mac_lock is already held then it is likely a port
2042 * reconfiguration is already in place, which will likely do
e254c274
BH		 2043 * most of the work of monitor() anyway. */
2044 if (mutex_trylock(&efx->mac_lock)) {
2045 if (efx->port_enabled)
2046 efx->type->monitor(efx);
2047 mutex_unlock(&efx->mac_lock);
2048 }
8ceee660 2049
8ceee660
BH		 2050 queue_delayed_work(efx->workqueue, &efx->monitor_work,
2051 efx_monitor_interval);
2052}
2053
2054/**************************************************************************
2055 *
2056 * ioctls
2057 *
2058 *************************************************************************/
2059
2060/* Net device ioctl
2061 * Context: process, rtnl_lock() held.
2062 */
2063static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
2064{
767e468c 2065 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 2066 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 2067
7c236c43 2068 if (cmd == SIOCSHWTSTAMP)
433dc9b3
BH		 2069 return efx_ptp_set_ts_config(efx, ifr);
2070 if (cmd == SIOCGHWTSTAMP)
2071 return efx_ptp_get_ts_config(efx, ifr);
7c236c43 2072
68e7f45e
BH		 2073 /* Convert phy_id from older PRTAD/DEVAD format */
2074 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
2075 (data->phy_id & 0xfc00) == 0x0400)
2076 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
2077
2078 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 2079}
2080
2081/**************************************************************************
2082 *
2083 * NAPI interface
2084 *
2085 **************************************************************************/
2086
7f967c01
BH		 2087static void efx_init_napi_channel(struct efx_channel *channel)
2088{
2089 struct efx_nic *efx = channel->efx;
2090
2091 channel->napi_dev = efx->net_dev;
2092 netif_napi_add(channel->napi_dev, &channel->napi_str,
2093 efx_poll, napi_weight);
c0f9c7e4 2094 efx_channel_busy_poll_init(channel);
7f967c01
BH		 2095}
2096
e8f14992 2097static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH		 2098{
2099 struct efx_channel *channel;
8ceee660 2100
7f967c01
BH		 2101 efx_for_each_channel(channel, efx)
2102 efx_init_napi_channel(channel);
e8f14992
BH		 2103}
2104
2105static void efx_fini_napi_channel(struct efx_channel *channel)
2106{
36763266 2107 if (channel->napi_dev) {
e8f14992 2108 netif_napi_del(&channel->napi_str);
36763266
AR		 2109 napi_hash_del(&channel->napi_str);
2110 }
e8f14992 2111 channel->napi_dev = NULL;
8ceee660
BH		 2112}
2113
2114static void efx_fini_napi(struct efx_nic *efx)
2115{
2116 struct efx_channel *channel;
2117
e8f14992
BH		 2118 efx_for_each_channel(channel, efx)
2119 efx_fini_napi_channel(channel);
8ceee660
BH		 2120}
2121
2122/**************************************************************************
2123 *
2124 * Kernel netpoll interface
2125 *
2126 *************************************************************************/
2127
2128#ifdef CONFIG_NET_POLL_CONTROLLER
2129
2130/* Although in the common case interrupts will be disabled, this is not
2131 * guaranteed. However, all our work happens inside the NAPI callback,
2132 * so no locking is required.
2133 */
2134static void efx_netpoll(struct net_device *net_dev)
2135{
767e468c 2136 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 2137 struct efx_channel *channel;
2138
64ee3120 2139 efx_for_each_channel(channel, efx)
8ceee660
BH		 2140 efx_schedule_channel(channel);
2141}
2142
2143#endif
2144
36763266
AR		 2145#ifdef CONFIG_NET_RX_BUSY_POLL
2146static int efx_busy_poll(struct napi_struct *napi)
2147{
2148 struct efx_channel *channel =
2149 container_of(napi, struct efx_channel, napi_str);
2150 struct efx_nic *efx = channel->efx;
2151 int budget = 4;
2152 int old_rx_packets, rx_packets;
2153
2154 if (!netif_running(efx->net_dev))
2155 return LL_FLUSH_FAILED;
2156
c0f9c7e4 2157 if (!efx_channel_try_lock_poll(channel))
36763266
AR		 2158 return LL_FLUSH_BUSY;
2159
2160 old_rx_packets = channel->rx_queue.rx_packets;
2161 efx_process_channel(channel, budget);
2162
2163 rx_packets = channel->rx_queue.rx_packets - old_rx_packets;
2164
2165 /* There is no race condition with NAPI here.
2166 * NAPI will automatically be rescheduled if it yielded during busy
2167 * polling, because it was not able to take the lock and thus returned
2168 * the full budget.
2169 */
2170 efx_channel_unlock_poll(channel);
2171
2172 return rx_packets;
2173}
2174#endif
2175
8ceee660
BH		 2176/**************************************************************************
2177 *
2178 * Kernel net device interface
2179 *
2180 *************************************************************************/
2181
2182/* Context: process, rtnl_lock() held. */
e340be92 2183int efx_net_open(struct net_device *net_dev)
8ceee660 2184{
767e468c 2185 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH		 2186 int rc;
2187
62776d03
BH		 2188 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
2189 raw_smp_processor_id());
8ceee660 2190
8b7325b4
BH		 2191 rc = efx_check_disabled(efx);
2192 if (rc)
2193 return rc;
f8b87c17
BH		 2194 if (efx->phy_mode & PHY_MODE_SPECIAL)
2195 return -EBUSY;
8880f4ec
BH		 2196 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
2197 return -EIO;
f8b87c17 2198
78c1f0a0
SH		 2199 /* Notify the kernel of the link state polled during driver load,
2200 * before the monitor starts running */
2201 efx_link_status_changed(efx);
2202
8ceee660 2203 efx_start_all(efx);
dd40781e 2204 efx_selftest_async_start(efx);
8ceee660
BH		 2205 return 0;
2206}
2207
2208/* Context: process, rtnl_lock() held.
2209 * Note that the kernel will ignore our return code; this method
2210 * should really be a void.
2211 */
e340be92 2212int efx_net_stop(struct net_device *net_dev)
8ceee660 2213{
767e468c 2214 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2215
62776d03
BH		 2216 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
2217 raw_smp_processor_id());
8ceee660 2218
8b7325b4
BH		 2219 /* Stop the device and flush all the channels */
2220 efx_stop_all(efx);
8ceee660
BH		 2221
2222 return 0;
2223}
2224
5b9e207c 2225/* Context: process, dev_base_lock or RTNL held, non-blocking. */
2aa9ef11
BH		 2226static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
2227 struct rtnl_link_stats64 *stats)
8ceee660 2228{
767e468c 2229 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2230
55edc6e6 2231 spin_lock_bh(&efx->stats_lock);
cd0ecc9a 2232 efx->type->update_stats(efx, NULL, stats);
1cb34522
BH		 2233 spin_unlock_bh(&efx->stats_lock);
2234
8ceee660
BH		 2235 return stats;
2236}
2237
2238/* Context: netif_tx_lock held, BHs disabled. */
2239static void efx_watchdog(struct net_device *net_dev)
2240{
767e468c 2241 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2242
62776d03
BH		 2243 netif_err(efx, tx_err, efx->net_dev,
2244 "TX stuck with port_enabled=%d: resetting channels\n",
2245 efx->port_enabled);
8ceee660 2246
739bb23d 2247 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 2248}
2249
2250
2251/* Context: process, rtnl_lock() held. */
2252static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
2253{
767e468c 2254 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 2255 int rc;
8ceee660 2256
8b7325b4
BH		 2257 rc = efx_check_disabled(efx);
2258 if (rc)
2259 return rc;
8ceee660
BH		 2260 if (new_mtu > EFX_MAX_MTU)
2261 return -EINVAL;
2262
62776d03 2263 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 2264
29c69a48
BH		 2265 efx_device_detach_sync(efx);
2266 efx_stop_all(efx);
2267
d3245b28 2268 mutex_lock(&efx->mac_lock);
8ceee660 2269 net_dev->mtu = new_mtu;
0d322413 2270 efx_mac_reconfigure(efx);
d3245b28
BH		 2271 mutex_unlock(&efx->mac_lock);
2272
8ceee660 2273 efx_start_all(efx);
29c69a48 2274 netif_device_attach(efx->net_dev);
6c8eef4a 2275 return 0;
8ceee660
BH		 2276}
2277
2278static int efx_set_mac_address(struct net_device *net_dev, void *data)
2279{
767e468c 2280 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2281 struct sockaddr *addr = data;
e0b3ae30 2282 u8 *new_addr = addr->sa_data;
cfc77c2f
SS		 2283 u8 old_addr[6];
2284 int rc;
8ceee660 2285
8ceee660 2286 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH		 2287 netif_err(efx, drv, efx->net_dev,
2288 "invalid ethernet MAC address requested: %pM\n",
2289 new_addr);
504f9b5a 2290 return -EADDRNOTAVAIL;
8ceee660
BH		 2291 }
2292
cfc77c2f
SS		 2293 /* save old address */
2294 ether_addr_copy(old_addr, net_dev->dev_addr);
cd84ff4d 2295 ether_addr_copy(net_dev->dev_addr, new_addr);
910c8789
SS		 2296 if (efx->type->set_mac_address) {
2297 rc = efx->type->set_mac_address(efx);
cfc77c2f
SS		 2298 if (rc) {
2299 ether_addr_copy(net_dev->dev_addr, old_addr);
2300 return rc;
2301 }
2302 }
8ceee660
BH		 2303
2304 /* Reconfigure the MAC */
d3245b28 2305 mutex_lock(&efx->mac_lock);
0d322413 2306 efx_mac_reconfigure(efx);
d3245b28 2307 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 2308
2309 return 0;
2310}
2311
a816f75a 2312/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 2313static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 2314{
767e468c 2315 struct efx_nic *efx = netdev_priv(net_dev);
a816f75a 2316
8be4f3e6
BH		 2317 if (efx->port_enabled)
2318 queue_work(efx->workqueue, &efx->mac_work);
2319 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 2320}
2321
c8f44aff 2322static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH		 2323{
2324 struct efx_nic *efx = netdev_priv(net_dev);
4a53ea8a 2325 int rc;
abfe9039
BH		 2326
2327 /* If disabling RX n-tuple filtering, clear existing filters */
4a53ea8a
AR		 2328 if (net_dev->features & ~data & NETIF_F_NTUPLE) {
2329 rc = efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2330 if (rc)
2331 return rc;
2332 }
2333
2334 /* If Rx VLAN filter is changed, update filters via mac_reconfigure */
2335 if ((net_dev->features ^ data) & NETIF_F_HW_VLAN_CTAG_FILTER) {
2336 /* efx_set_rx_mode() will schedule MAC work to update filters
2337 * when a new features are finally set in net_dev.
2338 */
2339 efx_set_rx_mode(net_dev);
2340 }
abfe9039
BH		 2341
2342 return 0;
2343}
2344
4a53ea8a
AR		 2345static int efx_vlan_rx_add_vid(struct net_device *net_dev, __be16 proto, u16 vid)
2346{
2347 struct efx_nic *efx = netdev_priv(net_dev);
2348
2349 if (efx->type->vlan_rx_add_vid)
2350 return efx->type->vlan_rx_add_vid(efx, proto, vid);
2351 else
2352 return -EOPNOTSUPP;
2353}
2354
2355static int efx_vlan_rx_kill_vid(struct net_device *net_dev, __be16 proto, u16 vid)
2356{
2357 struct efx_nic *efx = netdev_priv(net_dev);
2358
2359 if (efx->type->vlan_rx_kill_vid)
2360 return efx->type->vlan_rx_kill_vid(efx, proto, vid);
2361 else
2362 return -EOPNOTSUPP;
2363}
2364
7fa8d547 2365static const struct net_device_ops efx_netdev_ops = {
c3ecb9f3
SH		 2366 .ndo_open = efx_net_open,
2367 .ndo_stop = efx_net_stop,
4472702e 2368 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH		 2369 .ndo_tx_timeout = efx_watchdog,
2370 .ndo_start_xmit = efx_hard_start_xmit,
2371 .ndo_validate_addr = eth_validate_addr,
2372 .ndo_do_ioctl = efx_ioctl,
2373 .ndo_change_mtu = efx_change_mtu,
2374 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2375 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2376 .ndo_set_features = efx_set_features,
4a53ea8a
AR		 2377 .ndo_vlan_rx_add_vid = efx_vlan_rx_add_vid,
2378 .ndo_vlan_rx_kill_vid = efx_vlan_rx_kill_vid,
cd2d5b52 2379#ifdef CONFIG_SFC_SRIOV
7fa8d547
SS		 2380 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2381 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2382 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2383 .ndo_get_vf_config = efx_sriov_get_vf_config,
4392dc69 2384 .ndo_set_vf_link_state = efx_sriov_set_vf_link_state,
1d051e00 2385 .ndo_get_phys_port_id = efx_sriov_get_phys_port_id,
cd2d5b52 2386#endif
c3ecb9f3
SH		 2387#ifdef CONFIG_NET_POLL_CONTROLLER
2388 .ndo_poll_controller = efx_netpoll,
2389#endif
94b274bf 2390 .ndo_setup_tc = efx_setup_tc,
36763266
AR		 2391#ifdef CONFIG_NET_RX_BUSY_POLL
2392 .ndo_busy_poll = efx_busy_poll,
2393#endif
64d8ad6d
BH		 2394#ifdef CONFIG_RFS_ACCEL
2395 .ndo_rx_flow_steer = efx_filter_rfs,
2396#endif
c3ecb9f3
SH		 2397};
2398
7dde596e
BH		 2399static void efx_update_name(struct efx_nic *efx)
2400{
2401 strcpy(efx->name, efx->net_dev->name);
2402 efx_mtd_rename(efx);
2403 efx_set_channel_names(efx);
2404}
2405
8ceee660
BH		 2406static int efx_netdev_event(struct notifier_block *this,
2407 unsigned long event, void *ptr)
2408{
351638e7 2409 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
8ceee660 2410
7fa8d547 2411 if ((net_dev->netdev_ops == &efx_netdev_ops) &&
7dde596e
BH		 2412 event == NETDEV_CHANGENAME)
2413 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 2414
2415 return NOTIFY_DONE;
2416}
2417
2418static struct notifier_block efx_netdev_notifier = {
2419 .notifier_call = efx_netdev_event,
2420};
2421
06d5e193
BH		 2422static ssize_t
2423show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2424{
2425 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2426 return sprintf(buf, "%d\n", efx->phy_type);
2427}
776fbcc9 2428static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
06d5e193 2429
e7fef9b4
EC		 2430#ifdef CONFIG_SFC_MCDI_LOGGING
2431static ssize_t show_mcdi_log(struct device *dev, struct device_attribute *attr,
2432 char *buf)
2433{
2434 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2435 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
2436
2437 return scnprintf(buf, PAGE_SIZE, "%d\n", mcdi->logging_enabled);
2438}
2439static ssize_t set_mcdi_log(struct device *dev, struct device_attribute *attr,
2440 const char *buf, size_t count)
2441{
2442 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2443 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
2444 bool enable = count > 0 && *buf != '0';
2445
2446 mcdi->logging_enabled = enable;
2447 return count;
2448}
2449static DEVICE_ATTR(mcdi_logging, 0644, show_mcdi_log, set_mcdi_log);
2450#endif
2451
8ceee660
BH		 2452static int efx_register_netdev(struct efx_nic *efx)
2453{
2454 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2455 struct efx_channel *channel;
8ceee660
BH		 2456 int rc;
2457
2458 net_dev->watchdog_timeo = 5 * HZ;
2459 net_dev->irq = efx->pci_dev->irq;
7fa8d547
SS		 2460 net_dev->netdev_ops = &efx_netdev_ops;
2461 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
8127d661 2462 net_dev->priv_flags |= IFF_UNICAST_FLT;
7ad24ea4 2463 net_dev->ethtool_ops = &efx_ethtool_ops;
7e6d06f0 2464 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
8ceee660 2465
7dde596e 2466 rtnl_lock();
aed0628d 2467
7153f623
BH		 2468 /* Enable resets to be scheduled and check whether any were
2469 * already requested. If so, the NIC is probably hosed so we
2470 * abort.
2471 */
2472 efx->state = STATE_READY;
2473 smp_mb(); /* ensure we change state before checking reset_pending */
2474 if (efx->reset_pending) {
2475 netif_err(efx, probe, efx->net_dev,
2476 "aborting probe due to scheduled reset\n");
2477 rc = -EIO;
2478 goto fail_locked;
2479 }
2480
aed0628d
BH		 2481 rc = dev_alloc_name(net_dev, net_dev->name);
2482 if (rc < 0)
2483 goto fail_locked;
7dde596e 2484 efx_update_name(efx);
aed0628d 2485
8f8b3d51
BH		 2486 /* Always start with carrier off; PHY events will detect the link */
2487 netif_carrier_off(net_dev);
2488
aed0628d
BH		 2489 rc = register_netdevice(net_dev);
2490 if (rc)
2491 goto fail_locked;
2492
c04bfc6b
BH		 2493 efx_for_each_channel(channel, efx) {
2494 struct efx_tx_queue *tx_queue;
60031fcc
BH		 2495 efx_for_each_channel_tx_queue(tx_queue, channel)
2496 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH		 2497 }
2498
0bcf4a64
BH		 2499 efx_associate(efx);
2500
7dde596e 2501 rtnl_unlock();
8ceee660 2502
06d5e193
BH		 2503 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2504 if (rc) {
62776d03
BH		 2505 netif_err(efx, drv, efx->net_dev,
2506 "failed to init net dev attributes\n");
06d5e193
BH		 2507 goto fail_registered;
2508 }
e7fef9b4
EC		 2509#ifdef CONFIG_SFC_MCDI_LOGGING
2510 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
2511 if (rc) {
2512 netif_err(efx, drv, efx->net_dev,
2513 "failed to init net dev attributes\n");
2514 goto fail_attr_mcdi_logging;
2515 }
2516#endif
06d5e193 2517
8ceee660 2518 return 0;
06d5e193 2519
e7fef9b4
EC		 2520#ifdef CONFIG_SFC_MCDI_LOGGING
2521fail_attr_mcdi_logging:
2522 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2523#endif
7153f623
BH		 2524fail_registered:
2525 rtnl_lock();
0bcf4a64 2526 efx_dissociate(efx);
7153f623 2527 unregister_netdevice(net_dev);
aed0628d 2528fail_locked:
7153f623 2529 efx->state = STATE_UNINIT;
aed0628d 2530 rtnl_unlock();
62776d03 2531 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2532 return rc;
8ceee660
BH		 2533}
2534
2535static void efx_unregister_netdev(struct efx_nic *efx)
2536{
8ceee660
BH		 2537 if (!efx->net_dev)
2538 return;
2539
767e468c 2540 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660 2541
e7fef9b4
EC		 2542 if (efx_dev_registered(efx)) {
2543 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2544#ifdef CONFIG_SFC_MCDI_LOGGING
2545 device_remove_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
2546#endif
2547 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2548 unregister_netdev(efx->net_dev);
2549 }
8ceee660
BH		 2550}
2551
2552/**************************************************************************
2553 *
2554 * Device reset and suspend
2555 *
2556 **************************************************************************/
2557
2467ca46
BH		 2558/* Tears down the entire software state and most of the hardware state
2559 * before reset. */
d3245b28 2560void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2561{
8ceee660
BH		 2562 EFX_ASSERT_RESET_SERIALISED(efx);
2563
e283546c
EC		 2564 if (method == RESET_TYPE_MCDI_TIMEOUT)
2565 efx->type->prepare_flr(efx);
2566
2467ca46 2567 efx_stop_all(efx);
d8291187 2568 efx_disable_interrupts(efx);
5642ceef
BH		 2569
2570 mutex_lock(&efx->mac_lock);
087e9025
JC		 2571 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
2572 method != RESET_TYPE_DATAPATH)
4b988280 2573 efx->phy_op->fini(efx);
ef2b90ee 2574 efx->type->fini(efx);
8ceee660
BH		 2575}
2576
2467ca46
BH		 2577/* This function will always ensure that the locks acquired in
2578 * efx_reset_down() are released. A failure return code indicates
2579 * that we were unable to reinitialise the hardware, and the
2580 * driver should be disabled. If ok is false, then the rx and tx
2581 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2582int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 2583{
2584 int rc;
2585
2467ca46 2586 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2587
e283546c
EC		 2588 if (method == RESET_TYPE_MCDI_TIMEOUT)
2589 efx->type->finish_flr(efx);
2590
2591 /* Ensure that SRAM is initialised even if we're disabling the device */
ef2b90ee 2592 rc = efx->type->init(efx);
8ceee660 2593 if (rc) {
62776d03 2594 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2595 goto fail;
8ceee660
BH		 2596 }
2597
eb9f6744
BH		 2598 if (!ok)
2599 goto fail;
2600
087e9025
JC		 2601 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
2602 method != RESET_TYPE_DATAPATH) {
eb9f6744
BH		 2603 rc = efx->phy_op->init(efx);
2604 if (rc)
2605 goto fail;
267d9d73
EC		 2606 rc = efx->phy_op->reconfigure(efx);
2607 if (rc && rc != -EPERM)
62776d03
BH		 2608 netif_err(efx, drv, efx->net_dev,
2609 "could not restore PHY settings\n");
4b988280
SH		 2610 }
2611
261e4d96
JC		 2612 rc = efx_enable_interrupts(efx);
2613 if (rc)
2614 goto fail;
6d8aaaf6
DP		 2615
2616#ifdef CONFIG_SFC_SRIOV
2617 rc = efx->type->vswitching_restore(efx);
2618 if (rc) /* not fatal; the PF will still work fine */
2619 netif_warn(efx, probe, efx->net_dev,
2620 "failed to restore vswitching rc=%d;"
2621 " VFs may not function\n", rc);
2622#endif
2623
0d322413 2624 down_read(&efx->filter_sem);
64eebcfd 2625 efx_restore_filters(efx);
0d322413 2626 up_read(&efx->filter_sem);
7fa8d547
SS		 2627 if (efx->type->sriov_reset)
2628 efx->type->sriov_reset(efx);
eb9f6744 2629
eb9f6744
BH		 2630 mutex_unlock(&efx->mac_lock);
2631
2632 efx_start_all(efx);
2633
2634 return 0;
2635
2636fail:
2637 efx->port_initialized = false;
2467ca46
BH		 2638
2639 mutex_unlock(&efx->mac_lock);
2640
8ceee660
BH		 2641 return rc;
2642}
2643
eb9f6744
BH		 2644/* Reset the NIC using the specified method. Note that the reset may
2645 * fail, in which case the card will be left in an unusable state.
8ceee660 2646 *
eb9f6744 2647 * Caller must hold the rtnl_lock.
8ceee660 2648 */
eb9f6744 2649int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2650{
eb9f6744
BH		 2651 int rc, rc2;
2652 bool disabled;
8ceee660 2653
62776d03
BH		 2654 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2655 RESET_TYPE(method));
8ceee660 2656
c2f3b8e3 2657 efx_device_detach_sync(efx);
d3245b28 2658 efx_reset_down(efx, method);
8ceee660 2659
ef2b90ee 2660 rc = efx->type->reset(efx, method);
8ceee660 2661 if (rc) {
62776d03 2662 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2663 goto out;
8ceee660
BH		 2664 }
2665
a7d529ae
BH		 2666 /* Clear flags for the scopes we covered. We assume the NIC and
2667 * driver are now quiescent so that there is no race here.
2668 */
e283546c
EC		 2669 if (method < RESET_TYPE_MAX_METHOD)
2670 efx->reset_pending &= -(1 << (method + 1));
2671 else /* it doesn't fit into the well-ordered scope hierarchy */
2672 __clear_bit(method, &efx->reset_pending);
8ceee660
BH		 2673
2674 /* Reinitialise bus-mastering, which may have been turned off before
2675 * the reset was scheduled. This is still appropriate, even in the
2676 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2677 * can respond to requests. */
2678 pci_set_master(efx->pci_dev);
2679
eb9f6744 2680out:
8ceee660 2681 /* Leave device stopped if necessary */
626950db
AR		 2682 disabled = rc ||
2683 method == RESET_TYPE_DISABLE ||
2684 method == RESET_TYPE_RECOVER_OR_DISABLE;
eb9f6744
BH		 2685 rc2 = efx_reset_up(efx, method, !disabled);
2686 if (rc2) {
2687 disabled = true;
2688 if (!rc)
2689 rc = rc2;
8ceee660
BH		 2690 }
2691
eb9f6744 2692 if (disabled) {
f49a4589 2693 dev_close(efx->net_dev);
62776d03 2694 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2695 efx->state = STATE_DISABLED;
f4bd954e 2696 } else {
62776d03 2697 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2698 netif_device_attach(efx->net_dev);
f4bd954e 2699 }
8ceee660
BH		 2700 return rc;
2701}
2702
626950db
AR		 2703/* Try recovery mechanisms.
2704 * For now only EEH is supported.
2705 * Returns 0 if the recovery mechanisms are unsuccessful.
2706 * Returns a non-zero value otherwise.
2707 */
b28405b0 2708int efx_try_recovery(struct efx_nic *efx)
626950db
AR		 2709{
2710#ifdef CONFIG_EEH
2711 /* A PCI error can occur and not be seen by EEH because nothing
2712 * happens on the PCI bus. In this case the driver may fail and
2713 * schedule a 'recover or reset', leading to this recovery handler.
2714 * Manually call the eeh failure check function.
2715 */
12a89dba 2716 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
626950db
AR		 2717 if (eeh_dev_check_failure(eehdev)) {
2718 /* The EEH mechanisms will handle the error and reset the
2719 * device if necessary.
2720 */
2721 return 1;
2722 }
2723#endif
2724 return 0;
2725}
2726
74cd60a4
JC		 2727static void efx_wait_for_bist_end(struct efx_nic *efx)
2728{
2729 int i;
2730
2731 for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) {
2732 if (efx_mcdi_poll_reboot(efx))
2733 goto out;
2734 msleep(BIST_WAIT_DELAY_MS);
2735 }
2736
2737 netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n");
2738out:
2739 /* Either way unset the BIST flag. If we found no reboot we probably
2740 * won't recover, but we should try.
2741 */
2742 efx->mc_bist_for_other_fn = false;
2743}
2744
8ceee660
BH		 2745/* The worker thread exists so that code that cannot sleep can
2746 * schedule a reset for later.
2747 */
2748static void efx_reset_work(struct work_struct *data)
2749{
eb9f6744 2750 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
626950db
AR		 2751 unsigned long pending;
2752 enum reset_type method;
2753
2754 pending = ACCESS_ONCE(efx->reset_pending);
2755 method = fls(pending) - 1;
2756
74cd60a4
JC		 2757 if (method == RESET_TYPE_MC_BIST)
2758 efx_wait_for_bist_end(efx);
2759
626950db
AR		 2760 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2761 method == RESET_TYPE_RECOVER_OR_ALL) &&
2762 efx_try_recovery(efx))
2763 return;
8ceee660 2764
a7d529ae 2765 if (!pending)
319ba649
SH		 2766 return;
2767
eb9f6744 2768 rtnl_lock();
7153f623
BH		 2769
2770 /* We checked the state in efx_schedule_reset() but it may
2771 * have changed by now. Now that we have the RTNL lock,
2772 * it cannot change again.
2773 */
2774 if (efx->state == STATE_READY)
626950db 2775 (void)efx_reset(efx, method);
7153f623 2776
eb9f6744 2777 rtnl_unlock();
8ceee660
BH		 2778}
2779
2780void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2781{
2782 enum reset_type method;
2783
626950db
AR		 2784 if (efx->state == STATE_RECOVERY) {
2785 netif_dbg(efx, drv, efx->net_dev,
2786 "recovering: skip scheduling %s reset\n",
2787 RESET_TYPE(type));
2788 return;
2789 }
2790
8ceee660
BH		 2791 switch (type) {
2792 case RESET_TYPE_INVISIBLE:
2793 case RESET_TYPE_ALL:
626950db 2794 case RESET_TYPE_RECOVER_OR_ALL:
8ceee660
BH		 2795 case RESET_TYPE_WORLD:
2796 case RESET_TYPE_DISABLE:
626950db 2797 case RESET_TYPE_RECOVER_OR_DISABLE:
087e9025 2798 case RESET_TYPE_DATAPATH:
74cd60a4 2799 case RESET_TYPE_MC_BIST:
e283546c 2800 case RESET_TYPE_MCDI_TIMEOUT:
8ceee660 2801 method = type;
0e2a9c7c
BH		 2802 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2803 RESET_TYPE(method));
8ceee660 2804 break;
8ceee660 2805 default:
0e2a9c7c 2806 method = efx->type->map_reset_reason(type);
62776d03
BH		 2807 netif_dbg(efx, drv, efx->net_dev,
2808 "scheduling %s reset for %s\n",
2809 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH		 2810 break;
2811 }
8ceee660 2812
a7d529ae 2813 set_bit(method, &efx->reset_pending);
7153f623
BH		 2814 smp_mb(); /* ensure we change reset_pending before checking state */
2815
2816 /* If we're not READY then just leave the flags set as the cue
2817 * to abort probing or reschedule the reset later.
2818 */
2819 if (ACCESS_ONCE(efx->state) != STATE_READY)
2820 return;
8ceee660 2821
8880f4ec
BH		 2822 /* efx_process_channel() will no longer read events once a
2823 * reset is scheduled. So switch back to poll'd MCDI completions. */
2824 efx_mcdi_mode_poll(efx);
2825
1ab00629 2826 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 2827}
2828
2829/**************************************************************************
2830 *
2831 * List of NICs we support
2832 *
2833 **************************************************************************/
2834
2835/* PCI device ID table */
9baa3c34 2836static const struct pci_device_id efx_pci_table[] = {
937383a5
BH		 2837 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2838 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
daeda630 2839 .driver_data = (unsigned long) &falcon_a1_nic_type},
937383a5
BH		 2840 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2841 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
daeda630 2842 .driver_data = (unsigned long) &falcon_b0_nic_type},
547c474f 2843 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2844 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2845 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2846 .driver_data = (unsigned long) &siena_a0_nic_type},
8127d661
BH		 2847 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */
2848 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
6f7f8aa6
SS		 2849 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1903), /* SFC9120 VF */
2850 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
3b06a00e
MW		 2851 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0923), /* SFC9140 PF */
2852 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
dd248f1b
BK		 2853 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1923), /* SFC9140 VF */
2854 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
2855 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0a03), /* SFC9220 PF */
2856 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
2857 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1a03), /* SFC9220 VF */
2858 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
8ceee660
BH		 2859 {0} /* end of list */
2860};
2861
2862/**************************************************************************
2863 *
3759433d 2864 * Dummy PHY/MAC operations
8ceee660 2865 *
01aad7b6 2866 * Can be used for some unimplemented operations
8ceee660
BH		 2867 * Needed so all function pointers are valid and do not have to be tested
2868 * before use
2869 *
2870 **************************************************************************/
2871int efx_port_dummy_op_int(struct efx_nic *efx)
2872{
2873 return 0;
2874}
2875void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2876
2877static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH		 2878{
2879 return false;
2880}
8ceee660 2881
6c8c2513 2882static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2883 .init = efx_port_dummy_op_int,
d3245b28 2884 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2885 .poll = efx_port_dummy_op_poll,
8ceee660 2886 .fini = efx_port_dummy_op_void,
8ceee660
BH		 2887};
2888
8ceee660
BH		 2889/**************************************************************************
2890 *
2891 * Data housekeeping
2892 *
2893 **************************************************************************/
2894
2895/* This zeroes out and then fills in the invariants in a struct
2896 * efx_nic (including all sub-structures).
2897 */
adeb15aa 2898static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH		 2899 struct pci_dev *pci_dev, struct net_device *net_dev)
2900{
4642610c 2901 int i;
8ceee660
BH		 2902
2903 /* Initialise common structures */
0bcf4a64
BH		 2904 INIT_LIST_HEAD(&efx->node);
2905 INIT_LIST_HEAD(&efx->secondary_list);
8ceee660 2906 spin_lock_init(&efx->biu_lock);
76884835
BH		 2907#ifdef CONFIG_SFC_MTD
2908 INIT_LIST_HEAD(&efx->mtd_list);
2909#endif
8ceee660
BH		 2910 INIT_WORK(&efx->reset_work, efx_reset_work);
2911 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2912 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2913 efx->pci_dev = pci_dev;
62776d03 2914 efx->msg_enable = debug;
f16aeea0 2915 efx->state = STATE_UNINIT;
8ceee660 2916 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2917
2918 efx->net_dev = net_dev;
43a3739d 2919 efx->rx_prefix_size = efx->type->rx_prefix_size;
2ec03014
AR		 2920 efx->rx_ip_align =
2921 NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0;
43a3739d
JC		 2922 efx->rx_packet_hash_offset =
2923 efx->type->rx_hash_offset - efx->type->rx_prefix_size;
bd9a265d
JC		 2924 efx->rx_packet_ts_offset =
2925 efx->type->rx_ts_offset - efx->type->rx_prefix_size;
8ceee660
BH		 2926 spin_lock_init(&efx->stats_lock);
2927 mutex_init(&efx->mac_lock);
2928 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2929 efx->mdio.dev = net_dev;
766ca0fa 2930 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2931 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH		 2932
2933 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH		 2934 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2935 if (!efx->channel[i])
2936 goto fail;
d8291187
BH		 2937 efx->msi_context[i].efx = efx;
2938 efx->msi_context[i].index = i;
8ceee660
BH		 2939 }
2940
8ceee660
BH		 2941 /* Higher numbered interrupt modes are less capable! */
2942 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2943 interrupt_mode);
2944
6977dc63
BH		 2945 /* Would be good to use the net_dev name, but we're too early */
2946 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2947 pci_name(pci_dev));
2948 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2949 if (!efx->workqueue)
4642610c 2950 goto fail;
8d9853d9 2951
8ceee660 2952 return 0;
4642610c
BH		 2953
2954fail:
2955 efx_fini_struct(efx);
2956 return -ENOMEM;
8ceee660
BH		 2957}
2958
2959static void efx_fini_struct(struct efx_nic *efx)
2960{
8313aca3
BH		 2961 int i;
2962
2963 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2964 kfree(efx->channel[i]);
2965
ef215e64
BH		 2966 kfree(efx->vpd_sn);
2967
8ceee660
BH		 2968 if (efx->workqueue) {
2969 destroy_workqueue(efx->workqueue);
2970 efx->workqueue = NULL;
2971 }
2972}
2973
e4d112e4
EC		 2974void efx_update_sw_stats(struct efx_nic *efx, u64 *stats)
2975{
2976 u64 n_rx_nodesc_trunc = 0;
2977 struct efx_channel *channel;
2978
2979 efx_for_each_channel(channel, efx)
2980 n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc;
2981 stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc;
2982 stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops);
2983}
2984
8ceee660
BH		 2985/**************************************************************************
2986 *
2987 * PCI interface
2988 *
2989 **************************************************************************/
2990
2991/* Main body of final NIC shutdown code
2992 * This is called only at module unload (or hotplug removal).
2993 */
2994static void efx_pci_remove_main(struct efx_nic *efx)
2995{
7153f623
BH		 2996 /* Flush reset_work. It can no longer be scheduled since we
2997 * are not READY.
2998 */
2999 BUG_ON(efx->state == STATE_READY);
3000 cancel_work_sync(&efx->reset_work);
3001
d8291187 3002 efx_disable_interrupts(efx);
152b6a62 3003 efx_nic_fini_interrupt(efx);
8ceee660 3004 efx_fini_port(efx);
ef2b90ee 3005 efx->type->fini(efx);
8ceee660
BH		 3006 efx_fini_napi(efx);
3007 efx_remove_all(efx);
3008}
3009
3010/* Final NIC shutdown
2a3fc311
DP		 3011 * This is called only at module unload (or hotplug removal). A PF can call
3012 * this on its VFs to ensure they are unbound first.
8ceee660
BH		 3013 */
3014static void efx_pci_remove(struct pci_dev *pci_dev)
3015{
3016 struct efx_nic *efx;
3017
3018 efx = pci_get_drvdata(pci_dev);
3019 if (!efx)
3020 return;
3021
3022 /* Mark the NIC as fini, then stop the interface */
3023 rtnl_lock();
0bcf4a64 3024 efx_dissociate(efx);
8ceee660 3025 dev_close(efx->net_dev);
d8291187 3026 efx_disable_interrupts(efx);
ea6bb99e 3027 efx->state = STATE_UNINIT;
8ceee660
BH		 3028 rtnl_unlock();
3029
7fa8d547
SS		 3030 if (efx->type->sriov_fini)
3031 efx->type->sriov_fini(efx);
3032
8ceee660
BH		 3033 efx_unregister_netdev(efx);
3034
7dde596e
BH		 3035 efx_mtd_remove(efx);
3036
8ceee660
BH		 3037 efx_pci_remove_main(efx);
3038
8ceee660 3039 efx_fini_io(efx);
62776d03 3040 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 3041
8ceee660
BH		 3042 efx_fini_struct(efx);
3043 free_netdev(efx->net_dev);
626950db
AR		 3044
3045 pci_disable_pcie_error_reporting(pci_dev);
8ceee660
BH		 3046};
3047
460eeaa0
BH		 3048/* NIC VPD information
3049 * Called during probe to display the part number of the
3050 * installed NIC. VPD is potentially very large but this should
3051 * always appear within the first 512 bytes.
3052 */
3053#define SFC_VPD_LEN 512
ef215e64 3054static void efx_probe_vpd_strings(struct efx_nic *efx)
460eeaa0
BH		 3055{
3056 struct pci_dev *dev = efx->pci_dev;
3057 char vpd_data[SFC_VPD_LEN];
3058 ssize_t vpd_size;
ef215e64 3059 int ro_start, ro_size, i, j;
460eeaa0
BH		 3060
3061 /* Get the vpd data from the device */
3062 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
3063 if (vpd_size <= 0) {
3064 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
3065 return;
3066 }
3067
3068 /* Get the Read only section */
ef215e64
BH		 3069 ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
3070 if (ro_start < 0) {
460eeaa0
BH		 3071 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
3072 return;
3073 }
3074
ef215e64
BH		 3075 ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]);
3076 j = ro_size;
3077 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
460eeaa0
BH		 3078 if (i + j > vpd_size)
3079 j = vpd_size - i;
3080
3081 /* Get the Part number */
3082 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
3083 if (i < 0) {
3084 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
3085 return;
3086 }
3087
3088 j = pci_vpd_info_field_size(&vpd_data[i]);
3089 i += PCI_VPD_INFO_FLD_HDR_SIZE;
3090 if (i + j > vpd_size) {
3091 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
3092 return;
3093 }
3094
3095 netif_info(efx, drv, efx->net_dev,
3096 "Part Number : %.*s\n", j, &vpd_data[i]);
ef215e64
BH		 3097
3098 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
3099 j = ro_size;
3100 i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN");
3101 if (i < 0) {
3102 netif_err(efx, drv, efx->net_dev, "Serial number not found\n");
3103 return;
3104 }
3105
3106 j = pci_vpd_info_field_size(&vpd_data[i]);
3107 i += PCI_VPD_INFO_FLD_HDR_SIZE;
3108 if (i + j > vpd_size) {
3109 netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n");
3110 return;
3111 }
3112
3113 efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL);
3114 if (!efx->vpd_sn)
3115 return;
3116
3117 snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]);
460eeaa0
BH		 3118}
3119
3120
8ceee660
BH		 3121/* Main body of NIC initialisation
3122 * This is called at module load (or hotplug insertion, theoretically).
3123 */
3124static int efx_pci_probe_main(struct efx_nic *efx)
3125{
3126 int rc;
3127
3128 /* Do start-of-day initialisation */
3129 rc = efx_probe_all(efx);
3130 if (rc)
3131 goto fail1;
3132
e8f14992 3133 efx_init_napi(efx);
8ceee660 3134
ef2b90ee 3135 rc = efx->type->init(efx);
8ceee660 3136 if (rc) {
62776d03
BH		 3137 netif_err(efx, probe, efx->net_dev,
3138 "failed to initialise NIC\n");
278c0621 3139 goto fail3;
8ceee660
BH		 3140 }
3141
3142 rc = efx_init_port(efx);
3143 if (rc) {
62776d03
BH		 3144 netif_err(efx, probe, efx->net_dev,
3145 "failed to initialise port\n");
278c0621 3146 goto fail4;
8ceee660
BH		 3147 }
3148
152b6a62 3149 rc = efx_nic_init_interrupt(efx);
8ceee660 3150 if (rc)
278c0621 3151 goto fail5;
261e4d96
JC		 3152 rc = efx_enable_interrupts(efx);
3153 if (rc)
3154 goto fail6;
8ceee660
BH		 3155
3156 return 0;
3157
261e4d96
JC		 3158 fail6:
3159 efx_nic_fini_interrupt(efx);
278c0621 3160 fail5:
8ceee660 3161 efx_fini_port(efx);
8ceee660 3162 fail4:
ef2b90ee 3163 efx->type->fini(efx);
8ceee660
BH		 3164 fail3:
3165 efx_fini_napi(efx);
8ceee660
BH		 3166 efx_remove_all(efx);
3167 fail1:
3168 return rc;
3169}
3170
3171/* NIC initialisation
3172 *
3173 * This is called at module load (or hotplug insertion,
73ba7b68 3174 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH		 3175 * sets up and registers the network devices with the kernel and hooks
3176 * the interrupt service routine. It does not prepare the device for
3177 * transmission; this is left to the first time one of the network
3178 * interfaces is brought up (i.e. efx_net_open).
3179 */
87d1fc11 3180static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 3181 const struct pci_device_id *entry)
8ceee660 3182{
8ceee660
BH		 3183 struct net_device *net_dev;
3184 struct efx_nic *efx;
fadac6aa 3185 int rc;
8ceee660
BH		 3186
3187 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH		 3188 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
3189 EFX_MAX_RX_QUEUES);
8ceee660
BH		 3190 if (!net_dev)
3191 return -ENOMEM;
adeb15aa
BH		 3192 efx = netdev_priv(net_dev);
3193 efx->type = (const struct efx_nic_type *) entry->driver_data;
ebfcd0fd 3194 efx->fixed_features |= NETIF_F_HIGHDMA;
adeb15aa 3195 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
ebfcd0fd 3196 NETIF_F_TSO | NETIF_F_RXCSUM);
c8cd0989 3197 if (efx->type->offload_features & (NETIF_F_IPV6_CSUM | NETIF_F_HW_CSUM))
738a8f4b 3198 net_dev->features |= NETIF_F_TSO6;
28506563 3199 /* Mask for features that also apply to VLAN devices */
a188222b 3200 net_dev->vlan_features |= (NETIF_F_HW_CSUM | NETIF_F_SG |
abfe9039
BH		 3201 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
3202 NETIF_F_RXCSUM);
ebfcd0fd
AR		 3203 net_dev->features |= efx->fixed_features;
3204 net_dev->hw_features = net_dev->features & ~efx->fixed_features;
8ceee660 3205 pci_set_drvdata(pci_dev, efx);
62776d03 3206 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 3207 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH		 3208 if (rc)
3209 goto fail1;
3210
62776d03 3211 netif_info(efx, probe, efx->net_dev,
ff79c8ac 3212 "Solarflare NIC detected\n");
8ceee660 3213
6f7f8aa6
SS		 3214 if (!efx->type->is_vf)
3215 efx_probe_vpd_strings(efx);
460eeaa0 3216
8ceee660
BH		 3217 /* Set up basic I/O (BAR mappings etc) */
3218 rc = efx_init_io(efx);
3219 if (rc)
3220 goto fail2;
3221
fadac6aa 3222 rc = efx_pci_probe_main(efx);
fadac6aa
BH		 3223 if (rc)
3224 goto fail3;
8ceee660 3225
8ceee660
BH		 3226 rc = efx_register_netdev(efx);
3227 if (rc)
fadac6aa 3228 goto fail4;
8ceee660 3229
7fa8d547
SS		 3230 if (efx->type->sriov_init) {
3231 rc = efx->type->sriov_init(efx);
3232 if (rc)
3233 netif_err(efx, probe, efx->net_dev,
3234 "SR-IOV can't be enabled rc %d\n", rc);
3235 }
cd2d5b52 3236
62776d03 3237 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 3238
7c43161c 3239 /* Try to create MTDs, but allow this to fail */
a5211bb5 3240 rtnl_lock();
7c43161c 3241 rc = efx_mtd_probe(efx);
a5211bb5 3242 rtnl_unlock();
09a04204 3243 if (rc && rc != -EPERM)
7c43161c
BH		 3244 netif_warn(efx, probe, efx->net_dev,
3245 "failed to create MTDs (%d)\n", rc);
3246
626950db
AR		 3247 rc = pci_enable_pcie_error_reporting(pci_dev);
3248 if (rc && rc != -EINVAL)
09a04204
BK		 3249 netif_notice(efx, probe, efx->net_dev,
3250 "PCIE error reporting unavailable (%d).\n",
3251 rc);
626950db 3252
8ceee660
BH		 3253 return 0;
3254
8ceee660 3255 fail4:
fadac6aa 3256 efx_pci_remove_main(efx);
8ceee660
BH		 3257 fail3:
3258 efx_fini_io(efx);
3259 fail2:
3260 efx_fini_struct(efx);
3261 fail1:
5e2a911c 3262 WARN_ON(rc > 0);
62776d03 3263 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH		 3264 free_netdev(net_dev);
3265 return rc;
3266}
3267
834e23dd
SS		 3268/* efx_pci_sriov_configure returns the actual number of Virtual Functions
3269 * enabled on success
3270 */
3271#ifdef CONFIG_SFC_SRIOV
3272static int efx_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
3273{
3274 int rc;
3275 struct efx_nic *efx = pci_get_drvdata(dev);
3276
3277 if (efx->type->sriov_configure) {
3278 rc = efx->type->sriov_configure(efx, num_vfs);
3279 if (rc)
3280 return rc;
3281 else
3282 return num_vfs;
3283 } else
3284 return -EOPNOTSUPP;
3285}
3286#endif
3287
89c758fa
BH		 3288static int efx_pm_freeze(struct device *dev)
3289{
3290 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
3291
61da026d
BH		 3292 rtnl_lock();
3293
6032fb56
BH		 3294 if (efx->state != STATE_DISABLED) {
3295 efx->state = STATE_UNINIT;
89c758fa 3296
c2f3b8e3 3297 efx_device_detach_sync(efx);
89c758fa 3298
6032fb56 3299 efx_stop_all(efx);
d8291187 3300 efx_disable_interrupts(efx);
6032fb56 3301 }
89c758fa 3302
61da026d
BH		 3303 rtnl_unlock();
3304
89c758fa
BH		 3305 return 0;
3306}
3307
3308static int efx_pm_thaw(struct device *dev)
3309{
261e4d96 3310 int rc;
89c758fa
BH		 3311 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
3312
61da026d
BH		 3313 rtnl_lock();
3314
6032fb56 3315 if (efx->state != STATE_DISABLED) {
261e4d96
JC		 3316 rc = efx_enable_interrupts(efx);
3317 if (rc)
3318 goto fail;
89c758fa 3319
6032fb56
BH		 3320 mutex_lock(&efx->mac_lock);
3321 efx->phy_op->reconfigure(efx);
3322 mutex_unlock(&efx->mac_lock);
89c758fa 3323
6032fb56 3324 efx_start_all(efx);
89c758fa 3325
6032fb56 3326 netif_device_attach(efx->net_dev);
89c758fa 3327
6032fb56 3328 efx->state = STATE_READY;
89c758fa 3329
6032fb56
BH		 3330 efx->type->resume_wol(efx);
3331 }
89c758fa 3332
61da026d
BH		 3333 rtnl_unlock();
3334
319ba649
SH		 3335 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
3336 queue_work(reset_workqueue, &efx->reset_work);
3337
89c758fa 3338 return 0;
261e4d96
JC		 3339
3340fail:
3341 rtnl_unlock();
3342
3343 return rc;
89c758fa
BH		 3344}
3345
3346static int efx_pm_poweroff(struct device *dev)
3347{
3348 struct pci_dev *pci_dev = to_pci_dev(dev);
3349 struct efx_nic *efx = pci_get_drvdata(pci_dev);
3350
3351 efx->type->fini(efx);
3352
a7d529ae 3353 efx->reset_pending = 0;
89c758fa
BH		 3354
3355 pci_save_state(pci_dev);
3356 return pci_set_power_state(pci_dev, PCI_D3hot);
3357}
3358
3359/* Used for both resume and restore */
3360static int efx_pm_resume(struct device *dev)
3361{
3362 struct pci_dev *pci_dev = to_pci_dev(dev);
3363 struct efx_nic *efx = pci_get_drvdata(pci_dev);
3364 int rc;
3365
3366 rc = pci_set_power_state(pci_dev, PCI_D0);
3367 if (rc)
3368 return rc;
3369 pci_restore_state(pci_dev);
3370 rc = pci_enable_device(pci_dev);
3371 if (rc)
3372 return rc;
3373 pci_set_master(efx->pci_dev);
3374 rc = efx->type->reset(efx, RESET_TYPE_ALL);
3375 if (rc)
3376 return rc;
3377 rc = efx->type->init(efx);
3378 if (rc)
3379 return rc;
261e4d96
JC		 3380 rc = efx_pm_thaw(dev);
3381 return rc;
89c758fa
BH		 3382}
3383
3384static int efx_pm_suspend(struct device *dev)
3385{
3386 int rc;
3387
3388 efx_pm_freeze(dev);
3389 rc = efx_pm_poweroff(dev);
3390 if (rc)
3391 efx_pm_resume(dev);
3392 return rc;
3393}
3394
18e83e4c 3395static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH		 3396 .suspend = efx_pm_suspend,
3397 .resume = efx_pm_resume,
3398 .freeze = efx_pm_freeze,
3399 .thaw = efx_pm_thaw,
3400 .poweroff = efx_pm_poweroff,
3401 .restore = efx_pm_resume,
3402};
3403
626950db
AR		 3404/* A PCI error affecting this device was detected.
3405 * At this point MMIO and DMA may be disabled.
3406 * Stop the software path and request a slot reset.
3407 */
debd0034 3408static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
3409 enum pci_channel_state state)
626950db
AR		 3410{
3411 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3412 struct efx_nic *efx = pci_get_drvdata(pdev);
3413
3414 if (state == pci_channel_io_perm_failure)
3415 return PCI_ERS_RESULT_DISCONNECT;
3416
3417 rtnl_lock();
3418
3419 if (efx->state != STATE_DISABLED) {
3420 efx->state = STATE_RECOVERY;
3421 efx->reset_pending = 0;
3422
3423 efx_device_detach_sync(efx);
3424
3425 efx_stop_all(efx);
d8291187 3426 efx_disable_interrupts(efx);
626950db
AR		 3427
3428 status = PCI_ERS_RESULT_NEED_RESET;
3429 } else {
3430 /* If the interface is disabled we don't want to do anything
3431 * with it.
3432 */
3433 status = PCI_ERS_RESULT_RECOVERED;
3434 }
3435
3436 rtnl_unlock();
3437
3438 pci_disable_device(pdev);
3439
3440 return status;
3441}
3442
dbedd44e 3443/* Fake a successful reset, which will be performed later in efx_io_resume. */
debd0034 3444static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
626950db
AR		 3445{
3446 struct efx_nic *efx = pci_get_drvdata(pdev);
3447 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3448 int rc;
3449
3450 if (pci_enable_device(pdev)) {
3451 netif_err(efx, hw, efx->net_dev,
3452 "Cannot re-enable PCI device after reset.\n");
3453 status = PCI_ERS_RESULT_DISCONNECT;
3454 }
3455
3456 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
3457 if (rc) {
3458 netif_err(efx, hw, efx->net_dev,
3459 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
3460 /* Non-fatal error. Continue. */
3461 }
3462
3463 return status;
3464}
3465
3466/* Perform the actual reset and resume I/O operations. */
3467static void efx_io_resume(struct pci_dev *pdev)
3468{
3469 struct efx_nic *efx = pci_get_drvdata(pdev);
3470 int rc;
3471
3472 rtnl_lock();
3473
3474 if (efx->state == STATE_DISABLED)
3475 goto out;
3476
3477 rc = efx_reset(efx, RESET_TYPE_ALL);
3478 if (rc) {
3479 netif_err(efx, hw, efx->net_dev,
3480 "efx_reset failed after PCI error (%d)\n", rc);
3481 } else {
3482 efx->state = STATE_READY;
3483 netif_dbg(efx, hw, efx->net_dev,
3484 "Done resetting and resuming IO after PCI error.\n");
3485 }
3486
3487out:
3488 rtnl_unlock();
3489}
3490
3491/* For simplicity and reliability, we always require a slot reset and try to
3492 * reset the hardware when a pci error affecting the device is detected.
3493 * We leave both the link_reset and mmio_enabled callback unimplemented:
3494 * with our request for slot reset the mmio_enabled callback will never be
3495 * called, and the link_reset callback is not used by AER or EEH mechanisms.
3496 */
c300366b 3497static const struct pci_error_handlers efx_err_handlers = {
626950db
AR		 3498 .error_detected = efx_io_error_detected,
3499 .slot_reset = efx_io_slot_reset,
3500 .resume = efx_io_resume,
3501};
3502
8ceee660 3503static struct pci_driver efx_pci_driver = {
c5d5f5fd 3504 .name = KBUILD_MODNAME,
8ceee660
BH		 3505 .id_table = efx_pci_table,
3506 .probe = efx_pci_probe,
3507 .remove = efx_pci_remove,
89c758fa 3508 .driver.pm = &efx_pm_ops,
626950db 3509 .err_handler = &efx_err_handlers,
834e23dd
SS		 3510#ifdef CONFIG_SFC_SRIOV
3511 .sriov_configure = efx_pci_sriov_configure,
3512#endif
8ceee660
BH		 3513};
3514
3515/**************************************************************************
3516 *
3517 * Kernel module interface
3518 *
3519 *************************************************************************/
3520
3521module_param(interrupt_mode, uint, 0444);
3522MODULE_PARM_DESC(interrupt_mode,
3523 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
3524
3525static int __init efx_init_module(void)
3526{
3527 int rc;
3528
3529 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
3530
3531 rc = register_netdevice_notifier(&efx_netdev_notifier);
3532 if (rc)
3533 goto err_notifier;
3534
7fa8d547 3535#ifdef CONFIG_SFC_SRIOV
cd2d5b52
BH		 3536 rc = efx_init_sriov();
3537 if (rc)
3538 goto err_sriov;
7fa8d547 3539#endif
cd2d5b52 3540
1ab00629
SH		 3541 reset_workqueue = create_singlethread_workqueue("sfc_reset");
3542 if (!reset_workqueue) {
3543 rc = -ENOMEM;
3544 goto err_reset;
3545 }
8ceee660
BH		 3546
3547 rc = pci_register_driver(&efx_pci_driver);
3548 if (rc < 0)
3549 goto err_pci;
3550
3551 return 0;
3552
3553 err_pci:
1ab00629
SH		 3554 destroy_workqueue(reset_workqueue);
3555 err_reset:
7fa8d547 3556#ifdef CONFIG_SFC_SRIOV
cd2d5b52
BH		 3557 efx_fini_sriov();
3558 err_sriov:
7fa8d547 3559#endif
8ceee660
BH		 3560 unregister_netdevice_notifier(&efx_netdev_notifier);
3561 err_notifier:
3562 return rc;
3563}
3564
3565static void __exit efx_exit_module(void)
3566{
3567 printk(KERN_INFO "Solarflare NET driver unloading\n");
3568
3569 pci_unregister_driver(&efx_pci_driver);
1ab00629 3570 destroy_workqueue(reset_workqueue);
7fa8d547 3571#ifdef CONFIG_SFC_SRIOV
cd2d5b52 3572 efx_fini_sriov();
7fa8d547 3573#endif
8ceee660
BH		 3574 unregister_netdevice_notifier(&efx_netdev_notifier);
3575
3576}
3577
3578module_init(efx_init_module);
3579module_exit(efx_exit_module);
3580
906bb26c
BH		 3581MODULE_AUTHOR("Solarflare Communications and "
3582 "Michael Brown <mbrown@fensystems.co.uk>");
6a350fdb 3583MODULE_DESCRIPTION("Solarflare network driver");
8ceee660
BH		 3584MODULE_LICENSE("GPL");
3585MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux kernel - Deliverables
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