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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
64d8ad6d | 24 | #include <linux/cpu_rmap.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 41 | const char *const efx_loopback_mode_names[] = { |
c459302d | 42 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
47 | [LOOPBACK_XAUI] = "XAUI", |
48 | [LOOPBACK_GMII] = "GMII", | |
49 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
50 | [LOOPBACK_XGBR] = "XGBR", |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
58 | [LOOPBACK_PCS] = "PCS", |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 65 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
69 | }; |
70 | ||
c459302d | 71 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 72 | const char *const efx_reset_type_names[] = { |
c459302d BH |
73 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
74 | [RESET_TYPE_ALL] = "ALL", | |
75 | [RESET_TYPE_WORLD] = "WORLD", | |
76 | [RESET_TYPE_DISABLE] = "DISABLE", | |
77 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
78 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
79 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
80 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
81 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 83 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
84 | }; |
85 | ||
8ceee660 BH |
86 | #define EFX_MAX_MTU (9 * 1024) |
87 | ||
1ab00629 SH |
88 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
89 | * queued onto this work queue. This is not a per-nic work queue, because | |
90 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
91 | */ | |
92 | static struct workqueue_struct *reset_workqueue; | |
93 | ||
8ceee660 BH |
94 | /************************************************************************** |
95 | * | |
96 | * Configurable values | |
97 | * | |
98 | *************************************************************************/ | |
99 | ||
8ceee660 BH |
100 | /* |
101 | * Use separate channels for TX and RX events | |
102 | * | |
28b581ab NT |
103 | * Set this to 1 to use separate channels for TX and RX. It allows us |
104 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 105 | * |
28b581ab | 106 | * This is only used in MSI-X interrupt mode |
8ceee660 | 107 | */ |
28b581ab | 108 | static unsigned int separate_tx_channels; |
8313aca3 | 109 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
110 | MODULE_PARM_DESC(separate_tx_channels, |
111 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
112 | |
113 | /* This is the weight assigned to each of the (per-channel) virtual | |
114 | * NAPI devices. | |
115 | */ | |
116 | static int napi_weight = 64; | |
117 | ||
118 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
119 | * monitor. On Falcon-based NICs, this will: |
120 | * - Check the on-board hardware monitor; | |
121 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 122 | */ |
d215697f | 123 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 124 | |
8ceee660 BH |
125 | /* Initial interrupt moderation settings. They can be modified after |
126 | * module load with ethtool. | |
127 | * | |
128 | * The default for RX should strike a balance between increasing the | |
129 | * round-trip latency and reducing overhead. | |
130 | */ | |
131 | static unsigned int rx_irq_mod_usec = 60; | |
132 | ||
133 | /* Initial interrupt moderation settings. They can be modified after | |
134 | * module load with ethtool. | |
135 | * | |
136 | * This default is chosen to ensure that a 10G link does not go idle | |
137 | * while a TX queue is stopped after it has become full. A queue is | |
138 | * restarted when it drops below half full. The time this takes (assuming | |
139 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
140 | * 512 / 3 * 1.2 = 205 usec. | |
141 | */ | |
142 | static unsigned int tx_irq_mod_usec = 150; | |
143 | ||
144 | /* This is the first interrupt mode to try out of: | |
145 | * 0 => MSI-X | |
146 | * 1 => MSI | |
147 | * 2 => legacy | |
148 | */ | |
149 | static unsigned int interrupt_mode; | |
150 | ||
151 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
152 | * i.e. the number of CPUs among which we may distribute simultaneous | |
153 | * interrupt handling. | |
154 | * | |
155 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 156 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
157 | */ |
158 | static unsigned int rss_cpus; | |
159 | module_param(rss_cpus, uint, 0444); | |
160 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
161 | ||
84ae48fe BH |
162 | static int phy_flash_cfg; |
163 | module_param(phy_flash_cfg, int, 0644); | |
164 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
165 | ||
6fb70fd1 BH |
166 | static unsigned irq_adapt_low_thresh = 10000; |
167 | module_param(irq_adapt_low_thresh, uint, 0644); | |
168 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
169 | "Threshold score for reducing IRQ moderation"); | |
170 | ||
171 | static unsigned irq_adapt_high_thresh = 20000; | |
172 | module_param(irq_adapt_high_thresh, uint, 0644); | |
173 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
174 | "Threshold score for increasing IRQ moderation"); | |
175 | ||
62776d03 BH |
176 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
177 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
178 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
179 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
180 | module_param(debug, uint, 0); | |
181 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
182 | ||
8ceee660 BH |
183 | /************************************************************************** |
184 | * | |
185 | * Utility functions and prototypes | |
186 | * | |
187 | *************************************************************************/ | |
4642610c | 188 | |
9f2cb71c BH |
189 | static void efx_start_interrupts(struct efx_nic *efx); |
190 | static void efx_stop_interrupts(struct efx_nic *efx); | |
4642610c | 191 | static void efx_remove_channels(struct efx_nic *efx); |
8ceee660 | 192 | static void efx_remove_port(struct efx_nic *efx); |
e8f14992 | 193 | static void efx_init_napi(struct efx_nic *efx); |
8ceee660 | 194 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 195 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
196 | static void efx_fini_struct(struct efx_nic *efx); |
197 | static void efx_start_all(struct efx_nic *efx); | |
198 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
199 | |
200 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
201 | do { \ | |
332c1ce9 BH |
202 | if ((efx->state == STATE_RUNNING) || \ |
203 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
204 | ASSERT_RTNL(); \ |
205 | } while (0) | |
206 | ||
207 | /************************************************************************** | |
208 | * | |
209 | * Event queue processing | |
210 | * | |
211 | *************************************************************************/ | |
212 | ||
213 | /* Process channel's event queue | |
214 | * | |
215 | * This function is responsible for processing the event queue of a | |
216 | * single channel. The caller must guarantee that this function will | |
217 | * never be concurrently called more than once on the same channel, | |
218 | * though different channels may be being processed concurrently. | |
219 | */ | |
fa236e18 | 220 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 221 | { |
fa236e18 | 222 | int spent; |
8ceee660 | 223 | |
9f2cb71c | 224 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 225 | return 0; |
8ceee660 | 226 | |
fa236e18 | 227 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
228 | if (spent && efx_channel_has_rx_queue(channel)) { |
229 | struct efx_rx_queue *rx_queue = | |
230 | efx_channel_get_rx_queue(channel); | |
231 | ||
232 | /* Deliver last RX packet. */ | |
233 | if (channel->rx_pkt) { | |
234 | __efx_rx_packet(channel, channel->rx_pkt); | |
235 | channel->rx_pkt = NULL; | |
236 | } | |
9f2cb71c BH |
237 | if (rx_queue->enabled) { |
238 | efx_rx_strategy(channel); | |
239 | efx_fast_push_rx_descriptors(rx_queue); | |
240 | } | |
8ceee660 BH |
241 | } |
242 | ||
fa236e18 | 243 | return spent; |
8ceee660 BH |
244 | } |
245 | ||
246 | /* Mark channel as finished processing | |
247 | * | |
248 | * Note that since we will not receive further interrupts for this | |
249 | * channel before we finish processing and call the eventq_read_ack() | |
250 | * method, there is no need to use the interrupt hold-off timers. | |
251 | */ | |
252 | static inline void efx_channel_processed(struct efx_channel *channel) | |
253 | { | |
5b9e207c BH |
254 | /* The interrupt handler for this channel may set work_pending |
255 | * as soon as we acknowledge the events we've seen. Make sure | |
256 | * it's cleared before then. */ | |
dc8cfa55 | 257 | channel->work_pending = false; |
5b9e207c BH |
258 | smp_wmb(); |
259 | ||
152b6a62 | 260 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
261 | } |
262 | ||
263 | /* NAPI poll handler | |
264 | * | |
265 | * NAPI guarantees serialisation of polls of the same device, which | |
266 | * provides the guarantee required by efx_process_channel(). | |
267 | */ | |
268 | static int efx_poll(struct napi_struct *napi, int budget) | |
269 | { | |
270 | struct efx_channel *channel = | |
271 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 272 | struct efx_nic *efx = channel->efx; |
fa236e18 | 273 | int spent; |
8ceee660 | 274 | |
62776d03 BH |
275 | netif_vdbg(efx, intr, efx->net_dev, |
276 | "channel %d NAPI poll executing on CPU %d\n", | |
277 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 278 | |
fa236e18 | 279 | spent = efx_process_channel(channel, budget); |
8ceee660 | 280 | |
fa236e18 | 281 | if (spent < budget) { |
9d9a6973 | 282 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
283 | efx->irq_rx_adaptive && |
284 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
285 | if (unlikely(channel->irq_mod_score < |
286 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
287 | if (channel->irq_moderation > 1) { |
288 | channel->irq_moderation -= 1; | |
ef2b90ee | 289 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 290 | } |
6fb70fd1 BH |
291 | } else if (unlikely(channel->irq_mod_score > |
292 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
293 | if (channel->irq_moderation < |
294 | efx->irq_rx_moderation) { | |
295 | channel->irq_moderation += 1; | |
ef2b90ee | 296 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 297 | } |
6fb70fd1 | 298 | } |
6fb70fd1 BH |
299 | channel->irq_count = 0; |
300 | channel->irq_mod_score = 0; | |
301 | } | |
302 | ||
64d8ad6d BH |
303 | efx_filter_rfs_expire(channel); |
304 | ||
8ceee660 | 305 | /* There is no race here; although napi_disable() will |
288379f0 | 306 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
307 | * since efx_channel_processed() will have no effect if |
308 | * interrupts have already been disabled. | |
309 | */ | |
288379f0 | 310 | napi_complete(napi); |
8ceee660 BH |
311 | efx_channel_processed(channel); |
312 | } | |
313 | ||
fa236e18 | 314 | return spent; |
8ceee660 BH |
315 | } |
316 | ||
317 | /* Process the eventq of the specified channel immediately on this CPU | |
318 | * | |
319 | * Disable hardware generated interrupts, wait for any existing | |
320 | * processing to finish, then directly poll (and ack ) the eventq. | |
321 | * Finally reenable NAPI and interrupts. | |
322 | * | |
d4fabcc8 BH |
323 | * This is for use only during a loopback self-test. It must not |
324 | * deliver any packets up the stack as this can result in deadlock. | |
8ceee660 BH |
325 | */ |
326 | void efx_process_channel_now(struct efx_channel *channel) | |
327 | { | |
328 | struct efx_nic *efx = channel->efx; | |
329 | ||
8313aca3 | 330 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 | 331 | BUG_ON(!channel->enabled); |
d4fabcc8 | 332 | BUG_ON(!efx->loopback_selftest); |
8ceee660 BH |
333 | |
334 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 335 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 336 | if (efx->legacy_irq) { |
8ceee660 | 337 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
338 | efx->legacy_irq_enabled = false; |
339 | } | |
64ee3120 | 340 | if (channel->irq) |
8ceee660 BH |
341 | synchronize_irq(channel->irq); |
342 | ||
343 | /* Wait for any NAPI processing to complete */ | |
344 | napi_disable(&channel->napi_str); | |
345 | ||
346 | /* Poll the channel */ | |
ecc910f5 | 347 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
348 | |
349 | /* Ack the eventq. This may cause an interrupt to be generated | |
350 | * when they are reenabled */ | |
351 | efx_channel_processed(channel); | |
352 | ||
353 | napi_enable(&channel->napi_str); | |
94dec6a2 BH |
354 | if (efx->legacy_irq) |
355 | efx->legacy_irq_enabled = true; | |
152b6a62 | 356 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
357 | } |
358 | ||
359 | /* Create event queue | |
360 | * Event queue memory allocations are done only once. If the channel | |
361 | * is reset, the memory buffer will be reused; this guards against | |
362 | * errors during channel reset and also simplifies interrupt handling. | |
363 | */ | |
364 | static int efx_probe_eventq(struct efx_channel *channel) | |
365 | { | |
ecc910f5 SH |
366 | struct efx_nic *efx = channel->efx; |
367 | unsigned long entries; | |
368 | ||
86ee5302 | 369 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 370 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 371 | |
ecc910f5 SH |
372 | /* Build an event queue with room for one event per tx and rx buffer, |
373 | * plus some extra for link state events and MCDI completions. */ | |
374 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
375 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
376 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
377 | ||
152b6a62 | 378 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
379 | } |
380 | ||
381 | /* Prepare channel's event queue */ | |
bc3c90a2 | 382 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 383 | { |
62776d03 BH |
384 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
385 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
386 | |
387 | channel->eventq_read_ptr = 0; | |
388 | ||
152b6a62 | 389 | efx_nic_init_eventq(channel); |
8ceee660 BH |
390 | } |
391 | ||
9f2cb71c BH |
392 | /* Enable event queue processing and NAPI */ |
393 | static void efx_start_eventq(struct efx_channel *channel) | |
394 | { | |
395 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
396 | "chan %d start event queue\n", channel->channel); | |
397 | ||
398 | /* The interrupt handler for this channel may set work_pending | |
399 | * as soon as we enable it. Make sure it's cleared before | |
400 | * then. Similarly, make sure it sees the enabled flag set. | |
401 | */ | |
402 | channel->work_pending = false; | |
403 | channel->enabled = true; | |
404 | smp_wmb(); | |
405 | ||
406 | napi_enable(&channel->napi_str); | |
407 | efx_nic_eventq_read_ack(channel); | |
408 | } | |
409 | ||
410 | /* Disable event queue processing and NAPI */ | |
411 | static void efx_stop_eventq(struct efx_channel *channel) | |
412 | { | |
413 | if (!channel->enabled) | |
414 | return; | |
415 | ||
416 | napi_disable(&channel->napi_str); | |
417 | channel->enabled = false; | |
418 | } | |
419 | ||
8ceee660 BH |
420 | static void efx_fini_eventq(struct efx_channel *channel) |
421 | { | |
62776d03 BH |
422 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
423 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 424 | |
152b6a62 | 425 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
426 | } |
427 | ||
428 | static void efx_remove_eventq(struct efx_channel *channel) | |
429 | { | |
62776d03 BH |
430 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
431 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 432 | |
152b6a62 | 433 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
434 | } |
435 | ||
436 | /************************************************************************** | |
437 | * | |
438 | * Channel handling | |
439 | * | |
440 | *************************************************************************/ | |
441 | ||
4642610c BH |
442 | /* Allocate and initialise a channel structure, optionally copying |
443 | * parameters (but not resources) from an old channel structure. */ | |
444 | static struct efx_channel * | |
445 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
446 | { | |
447 | struct efx_channel *channel; | |
448 | struct efx_rx_queue *rx_queue; | |
449 | struct efx_tx_queue *tx_queue; | |
450 | int j; | |
451 | ||
452 | if (old_channel) { | |
453 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); | |
454 | if (!channel) | |
455 | return NULL; | |
456 | ||
457 | *channel = *old_channel; | |
458 | ||
e8f14992 | 459 | channel->napi_dev = NULL; |
4642610c BH |
460 | memset(&channel->eventq, 0, sizeof(channel->eventq)); |
461 | ||
462 | rx_queue = &channel->rx_queue; | |
463 | rx_queue->buffer = NULL; | |
464 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
465 | ||
466 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
467 | tx_queue = &channel->tx_queue[j]; | |
468 | if (tx_queue->channel) | |
469 | tx_queue->channel = channel; | |
470 | tx_queue->buffer = NULL; | |
471 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
472 | } | |
473 | } else { | |
474 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); | |
475 | if (!channel) | |
476 | return NULL; | |
477 | ||
478 | channel->efx = efx; | |
479 | channel->channel = i; | |
480 | ||
481 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
482 | tx_queue = &channel->tx_queue[j]; | |
483 | tx_queue->efx = efx; | |
484 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
485 | tx_queue->channel = channel; | |
486 | } | |
487 | } | |
488 | ||
4642610c BH |
489 | rx_queue = &channel->rx_queue; |
490 | rx_queue->efx = efx; | |
491 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
492 | (unsigned long)rx_queue); | |
493 | ||
494 | return channel; | |
495 | } | |
496 | ||
8ceee660 BH |
497 | static int efx_probe_channel(struct efx_channel *channel) |
498 | { | |
499 | struct efx_tx_queue *tx_queue; | |
500 | struct efx_rx_queue *rx_queue; | |
501 | int rc; | |
502 | ||
62776d03 BH |
503 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
504 | "creating channel %d\n", channel->channel); | |
8ceee660 BH |
505 | |
506 | rc = efx_probe_eventq(channel); | |
507 | if (rc) | |
508 | goto fail1; | |
509 | ||
510 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
511 | rc = efx_probe_tx_queue(tx_queue); | |
512 | if (rc) | |
513 | goto fail2; | |
514 | } | |
515 | ||
516 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
517 | rc = efx_probe_rx_queue(rx_queue); | |
518 | if (rc) | |
519 | goto fail3; | |
520 | } | |
521 | ||
522 | channel->n_rx_frm_trunc = 0; | |
523 | ||
524 | return 0; | |
525 | ||
526 | fail3: | |
527 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
528 | efx_remove_rx_queue(rx_queue); | |
529 | fail2: | |
530 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
531 | efx_remove_tx_queue(tx_queue); | |
532 | fail1: | |
533 | return rc; | |
534 | } | |
535 | ||
536 | ||
56536e9c BH |
537 | static void efx_set_channel_names(struct efx_nic *efx) |
538 | { | |
539 | struct efx_channel *channel; | |
540 | const char *type = ""; | |
541 | int number; | |
542 | ||
543 | efx_for_each_channel(channel, efx) { | |
544 | number = channel->channel; | |
a4900ac9 BH |
545 | if (efx->n_channels > efx->n_rx_channels) { |
546 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
547 | type = "-rx"; |
548 | } else { | |
549 | type = "-tx"; | |
a4900ac9 | 550 | number -= efx->n_rx_channels; |
56536e9c BH |
551 | } |
552 | } | |
4642610c BH |
553 | snprintf(efx->channel_name[channel->channel], |
554 | sizeof(efx->channel_name[0]), | |
56536e9c BH |
555 | "%s%s-%d", efx->name, type, number); |
556 | } | |
557 | } | |
558 | ||
4642610c BH |
559 | static int efx_probe_channels(struct efx_nic *efx) |
560 | { | |
561 | struct efx_channel *channel; | |
562 | int rc; | |
563 | ||
564 | /* Restart special buffer allocation */ | |
565 | efx->next_buffer_table = 0; | |
566 | ||
567 | efx_for_each_channel(channel, efx) { | |
568 | rc = efx_probe_channel(channel); | |
569 | if (rc) { | |
570 | netif_err(efx, probe, efx->net_dev, | |
571 | "failed to create channel %d\n", | |
572 | channel->channel); | |
573 | goto fail; | |
574 | } | |
575 | } | |
576 | efx_set_channel_names(efx); | |
577 | ||
578 | return 0; | |
579 | ||
580 | fail: | |
581 | efx_remove_channels(efx); | |
582 | return rc; | |
583 | } | |
584 | ||
8ceee660 BH |
585 | /* Channels are shutdown and reinitialised whilst the NIC is running |
586 | * to propagate configuration changes (mtu, checksum offload), or | |
587 | * to clear hardware error conditions | |
588 | */ | |
9f2cb71c | 589 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 BH |
590 | { |
591 | struct efx_tx_queue *tx_queue; | |
592 | struct efx_rx_queue *rx_queue; | |
593 | struct efx_channel *channel; | |
8ceee660 | 594 | |
f7f13b0b BH |
595 | /* Calculate the rx buffer allocation parameters required to |
596 | * support the current MTU, including padding for header | |
597 | * alignment and overruns. | |
598 | */ | |
599 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
600 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 601 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 602 | efx->type->rx_buffer_padding); |
62b330ba SH |
603 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
604 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
605 | |
606 | /* Initialise the channels */ | |
607 | efx_for_each_channel(channel, efx) { | |
bc3c90a2 BH |
608 | efx_for_each_channel_tx_queue(tx_queue, channel) |
609 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
610 | |
611 | /* The rx buffer allocation strategy is MTU dependent */ | |
612 | efx_rx_strategy(channel); | |
613 | ||
9f2cb71c | 614 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 615 | efx_init_rx_queue(rx_queue); |
9f2cb71c BH |
616 | efx_nic_generate_fill_event(rx_queue); |
617 | } | |
8ceee660 BH |
618 | |
619 | WARN_ON(channel->rx_pkt != NULL); | |
620 | efx_rx_strategy(channel); | |
621 | } | |
8ceee660 | 622 | |
9f2cb71c BH |
623 | if (netif_device_present(efx->net_dev)) |
624 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
625 | } |
626 | ||
9f2cb71c | 627 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
628 | { |
629 | struct efx_channel *channel; | |
630 | struct efx_tx_queue *tx_queue; | |
631 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 632 | int rc; |
8ceee660 BH |
633 | |
634 | EFX_ASSERT_RESET_SERIALISED(efx); | |
635 | BUG_ON(efx->port_enabled); | |
636 | ||
152b6a62 | 637 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
638 | if (rc && EFX_WORKAROUND_7803(efx)) { |
639 | /* Schedule a reset to recover from the flush failure. The | |
640 | * descriptor caches reference memory we're about to free, | |
641 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
642 | * the MACs because of the pending reset. */ | |
62776d03 BH |
643 | netif_err(efx, drv, efx->net_dev, |
644 | "Resetting to recover from flush failure\n"); | |
fd371e32 SH |
645 | efx_schedule_reset(efx, RESET_TYPE_ALL); |
646 | } else if (rc) { | |
62776d03 | 647 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); |
fd371e32 | 648 | } else { |
62776d03 BH |
649 | netif_dbg(efx, drv, efx->net_dev, |
650 | "successfully flushed all queues\n"); | |
fd371e32 | 651 | } |
6bc5d3a9 | 652 | |
8ceee660 | 653 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
654 | /* RX packet processing is pipelined, so wait for the |
655 | * NAPI handler to complete. At least event queue 0 | |
656 | * might be kept active by non-data events, so don't | |
657 | * use napi_synchronize() but actually disable NAPI | |
658 | * temporarily. | |
659 | */ | |
660 | if (efx_channel_has_rx_queue(channel)) { | |
661 | efx_stop_eventq(channel); | |
662 | efx_start_eventq(channel); | |
663 | } | |
8ceee660 BH |
664 | |
665 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
666 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 667 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 668 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
669 | } |
670 | } | |
671 | ||
672 | static void efx_remove_channel(struct efx_channel *channel) | |
673 | { | |
674 | struct efx_tx_queue *tx_queue; | |
675 | struct efx_rx_queue *rx_queue; | |
676 | ||
62776d03 BH |
677 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
678 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
679 | |
680 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
681 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 682 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
683 | efx_remove_tx_queue(tx_queue); |
684 | efx_remove_eventq(channel); | |
8ceee660 BH |
685 | } |
686 | ||
4642610c BH |
687 | static void efx_remove_channels(struct efx_nic *efx) |
688 | { | |
689 | struct efx_channel *channel; | |
690 | ||
691 | efx_for_each_channel(channel, efx) | |
692 | efx_remove_channel(channel); | |
693 | } | |
694 | ||
695 | int | |
696 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
697 | { | |
698 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
699 | u32 old_rxq_entries, old_txq_entries; | |
700 | unsigned i; | |
701 | int rc; | |
702 | ||
703 | efx_stop_all(efx); | |
9f2cb71c | 704 | efx_stop_interrupts(efx); |
4642610c BH |
705 | |
706 | /* Clone channels */ | |
707 | memset(other_channel, 0, sizeof(other_channel)); | |
708 | for (i = 0; i < efx->n_channels; i++) { | |
709 | channel = efx_alloc_channel(efx, i, efx->channel[i]); | |
710 | if (!channel) { | |
711 | rc = -ENOMEM; | |
712 | goto out; | |
713 | } | |
714 | other_channel[i] = channel; | |
715 | } | |
716 | ||
717 | /* Swap entry counts and channel pointers */ | |
718 | old_rxq_entries = efx->rxq_entries; | |
719 | old_txq_entries = efx->txq_entries; | |
720 | efx->rxq_entries = rxq_entries; | |
721 | efx->txq_entries = txq_entries; | |
722 | for (i = 0; i < efx->n_channels; i++) { | |
723 | channel = efx->channel[i]; | |
724 | efx->channel[i] = other_channel[i]; | |
725 | other_channel[i] = channel; | |
726 | } | |
727 | ||
728 | rc = efx_probe_channels(efx); | |
729 | if (rc) | |
730 | goto rollback; | |
731 | ||
e8f14992 BH |
732 | efx_init_napi(efx); |
733 | ||
4642610c | 734 | /* Destroy old channels */ |
e8f14992 BH |
735 | for (i = 0; i < efx->n_channels; i++) { |
736 | efx_fini_napi_channel(other_channel[i]); | |
4642610c | 737 | efx_remove_channel(other_channel[i]); |
e8f14992 | 738 | } |
4642610c BH |
739 | out: |
740 | /* Free unused channel structures */ | |
741 | for (i = 0; i < efx->n_channels; i++) | |
742 | kfree(other_channel[i]); | |
743 | ||
9f2cb71c | 744 | efx_start_interrupts(efx); |
4642610c BH |
745 | efx_start_all(efx); |
746 | return rc; | |
747 | ||
748 | rollback: | |
749 | /* Swap back */ | |
750 | efx->rxq_entries = old_rxq_entries; | |
751 | efx->txq_entries = old_txq_entries; | |
752 | for (i = 0; i < efx->n_channels; i++) { | |
753 | channel = efx->channel[i]; | |
754 | efx->channel[i] = other_channel[i]; | |
755 | other_channel[i] = channel; | |
756 | } | |
757 | goto out; | |
758 | } | |
759 | ||
90d683af | 760 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 761 | { |
90d683af | 762 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
763 | } |
764 | ||
765 | /************************************************************************** | |
766 | * | |
767 | * Port handling | |
768 | * | |
769 | **************************************************************************/ | |
770 | ||
771 | /* This ensures that the kernel is kept informed (via | |
772 | * netif_carrier_on/off) of the link status, and also maintains the | |
773 | * link status's stop on the port's TX queue. | |
774 | */ | |
fdaa9aed | 775 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 776 | { |
eb50c0d6 BH |
777 | struct efx_link_state *link_state = &efx->link_state; |
778 | ||
8ceee660 BH |
779 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
780 | * that no events are triggered between unregister_netdev() and the | |
781 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
782 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
783 | if (!netif_running(efx->net_dev)) | |
784 | return; | |
785 | ||
eb50c0d6 | 786 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
787 | efx->n_link_state_changes++; |
788 | ||
eb50c0d6 | 789 | if (link_state->up) |
8ceee660 BH |
790 | netif_carrier_on(efx->net_dev); |
791 | else | |
792 | netif_carrier_off(efx->net_dev); | |
793 | } | |
794 | ||
795 | /* Status message for kernel log */ | |
2aa9ef11 | 796 | if (link_state->up) |
62776d03 BH |
797 | netif_info(efx, link, efx->net_dev, |
798 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
799 | link_state->speed, link_state->fd ? "full" : "half", | |
800 | efx->net_dev->mtu, | |
801 | (efx->promiscuous ? " [PROMISC]" : "")); | |
2aa9ef11 | 802 | else |
62776d03 | 803 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
804 | } |
805 | ||
d3245b28 BH |
806 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
807 | { | |
808 | efx->link_advertising = advertising; | |
809 | if (advertising) { | |
810 | if (advertising & ADVERTISED_Pause) | |
811 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
812 | else | |
813 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
814 | if (advertising & ADVERTISED_Asym_Pause) | |
815 | efx->wanted_fc ^= EFX_FC_TX; | |
816 | } | |
817 | } | |
818 | ||
b5626946 | 819 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
820 | { |
821 | efx->wanted_fc = wanted_fc; | |
822 | if (efx->link_advertising) { | |
823 | if (wanted_fc & EFX_FC_RX) | |
824 | efx->link_advertising |= (ADVERTISED_Pause | | |
825 | ADVERTISED_Asym_Pause); | |
826 | else | |
827 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
828 | ADVERTISED_Asym_Pause); | |
829 | if (wanted_fc & EFX_FC_TX) | |
830 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
831 | } | |
832 | } | |
833 | ||
115122af BH |
834 | static void efx_fini_port(struct efx_nic *efx); |
835 | ||
d3245b28 BH |
836 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
837 | * the MAC appropriately. All other PHY configuration changes are pushed | |
838 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
839 | * through efx_monitor(). | |
840 | * | |
841 | * Callers must hold the mac_lock | |
842 | */ | |
843 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 844 | { |
d3245b28 BH |
845 | enum efx_phy_mode phy_mode; |
846 | int rc; | |
8ceee660 | 847 | |
d3245b28 | 848 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 849 | |
0fca8c97 | 850 | /* Serialise the promiscuous flag with efx_set_rx_mode. */ |
73ba7b68 BH |
851 | netif_addr_lock_bh(efx->net_dev); |
852 | netif_addr_unlock_bh(efx->net_dev); | |
a816f75a | 853 | |
d3245b28 BH |
854 | /* Disable PHY transmit in mac level loopbacks */ |
855 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
856 | if (LOOPBACK_INTERNAL(efx)) |
857 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
858 | else | |
859 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 860 | |
d3245b28 | 861 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 862 | |
d3245b28 BH |
863 | if (rc) |
864 | efx->phy_mode = phy_mode; | |
177dfcd8 | 865 | |
d3245b28 | 866 | return rc; |
8ceee660 BH |
867 | } |
868 | ||
869 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
870 | * disabled. */ | |
d3245b28 | 871 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 872 | { |
d3245b28 BH |
873 | int rc; |
874 | ||
8ceee660 BH |
875 | EFX_ASSERT_RESET_SERIALISED(efx); |
876 | ||
877 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 878 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 879 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
880 | |
881 | return rc; | |
8ceee660 BH |
882 | } |
883 | ||
8be4f3e6 BH |
884 | /* Asynchronous work item for changing MAC promiscuity and multicast |
885 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
886 | * MAC directly. */ | |
766ca0fa BH |
887 | static void efx_mac_work(struct work_struct *data) |
888 | { | |
889 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
890 | ||
891 | mutex_lock(&efx->mac_lock); | |
30b81cda | 892 | if (efx->port_enabled) |
710b208d | 893 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
894 | mutex_unlock(&efx->mac_lock); |
895 | } | |
896 | ||
8ceee660 BH |
897 | static int efx_probe_port(struct efx_nic *efx) |
898 | { | |
899 | int rc; | |
900 | ||
62776d03 | 901 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 902 | |
ff3b00a0 SH |
903 | if (phy_flash_cfg) |
904 | efx->phy_mode = PHY_MODE_SPECIAL; | |
905 | ||
ef2b90ee BH |
906 | /* Connect up MAC/PHY operations table */ |
907 | rc = efx->type->probe_port(efx); | |
8ceee660 | 908 | if (rc) |
e42de262 | 909 | return rc; |
8ceee660 | 910 | |
e332bcb3 BH |
911 | /* Initialise MAC address to permanent address */ |
912 | memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); | |
8ceee660 BH |
913 | |
914 | return 0; | |
8ceee660 BH |
915 | } |
916 | ||
917 | static int efx_init_port(struct efx_nic *efx) | |
918 | { | |
919 | int rc; | |
920 | ||
62776d03 | 921 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 922 | |
1dfc5cea BH |
923 | mutex_lock(&efx->mac_lock); |
924 | ||
177dfcd8 | 925 | rc = efx->phy_op->init(efx); |
8ceee660 | 926 | if (rc) |
1dfc5cea | 927 | goto fail1; |
8ceee660 | 928 | |
dc8cfa55 | 929 | efx->port_initialized = true; |
1dfc5cea | 930 | |
d3245b28 BH |
931 | /* Reconfigure the MAC before creating dma queues (required for |
932 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 933 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
934 | |
935 | /* Ensure the PHY advertises the correct flow control settings */ | |
936 | rc = efx->phy_op->reconfigure(efx); | |
937 | if (rc) | |
938 | goto fail2; | |
939 | ||
1dfc5cea | 940 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 941 | return 0; |
177dfcd8 | 942 | |
1dfc5cea | 943 | fail2: |
177dfcd8 | 944 | efx->phy_op->fini(efx); |
1dfc5cea BH |
945 | fail1: |
946 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 947 | return rc; |
8ceee660 BH |
948 | } |
949 | ||
8ceee660 BH |
950 | static void efx_start_port(struct efx_nic *efx) |
951 | { | |
62776d03 | 952 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
953 | BUG_ON(efx->port_enabled); |
954 | ||
955 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 956 | efx->port_enabled = true; |
8be4f3e6 BH |
957 | |
958 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
959 | * and then cancelled by efx_flush_all() */ | |
710b208d | 960 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 961 | |
8ceee660 BH |
962 | mutex_unlock(&efx->mac_lock); |
963 | } | |
964 | ||
fdaa9aed | 965 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
966 | static void efx_stop_port(struct efx_nic *efx) |
967 | { | |
62776d03 | 968 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
969 | |
970 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 971 | efx->port_enabled = false; |
8ceee660 BH |
972 | mutex_unlock(&efx->mac_lock); |
973 | ||
974 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
975 | netif_addr_lock_bh(efx->net_dev); |
976 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
977 | } |
978 | ||
979 | static void efx_fini_port(struct efx_nic *efx) | |
980 | { | |
62776d03 | 981 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
982 | |
983 | if (!efx->port_initialized) | |
984 | return; | |
985 | ||
177dfcd8 | 986 | efx->phy_op->fini(efx); |
dc8cfa55 | 987 | efx->port_initialized = false; |
8ceee660 | 988 | |
eb50c0d6 | 989 | efx->link_state.up = false; |
8ceee660 BH |
990 | efx_link_status_changed(efx); |
991 | } | |
992 | ||
993 | static void efx_remove_port(struct efx_nic *efx) | |
994 | { | |
62776d03 | 995 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 996 | |
ef2b90ee | 997 | efx->type->remove_port(efx); |
8ceee660 BH |
998 | } |
999 | ||
1000 | /************************************************************************** | |
1001 | * | |
1002 | * NIC handling | |
1003 | * | |
1004 | **************************************************************************/ | |
1005 | ||
1006 | /* This configures the PCI device to enable I/O and DMA. */ | |
1007 | static int efx_init_io(struct efx_nic *efx) | |
1008 | { | |
1009 | struct pci_dev *pci_dev = efx->pci_dev; | |
1010 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
1011 | int rc; | |
1012 | ||
62776d03 | 1013 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1014 | |
1015 | rc = pci_enable_device(pci_dev); | |
1016 | if (rc) { | |
62776d03 BH |
1017 | netif_err(efx, probe, efx->net_dev, |
1018 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1019 | goto fail1; |
1020 | } | |
1021 | ||
1022 | pci_set_master(pci_dev); | |
1023 | ||
1024 | /* Set the PCI DMA mask. Try all possibilities from our | |
1025 | * genuine mask down to 32 bits, because some architectures | |
1026 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1027 | * masks event though they reject 46 bit masks. | |
1028 | */ | |
1029 | while (dma_mask > 0x7fffffffUL) { | |
e9e01846 BH |
1030 | if (pci_dma_supported(pci_dev, dma_mask)) { |
1031 | rc = pci_set_dma_mask(pci_dev, dma_mask); | |
1032 | if (rc == 0) | |
1033 | break; | |
1034 | } | |
8ceee660 BH |
1035 | dma_mask >>= 1; |
1036 | } | |
1037 | if (rc) { | |
62776d03 BH |
1038 | netif_err(efx, probe, efx->net_dev, |
1039 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1040 | goto fail2; |
1041 | } | |
62776d03 BH |
1042 | netif_dbg(efx, probe, efx->net_dev, |
1043 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 BH |
1044 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); |
1045 | if (rc) { | |
1046 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
1047 | * fail with a mask that pci_set_dma_mask() accepted, | |
1048 | * but just in case... | |
1049 | */ | |
62776d03 BH |
1050 | netif_err(efx, probe, efx->net_dev, |
1051 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1052 | goto fail2; |
1053 | } | |
1054 | ||
dc803df8 BH |
1055 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1056 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1057 | if (rc) { |
62776d03 BH |
1058 | netif_err(efx, probe, efx->net_dev, |
1059 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1060 | rc = -EIO; |
1061 | goto fail3; | |
1062 | } | |
86c432ca BH |
1063 | efx->membase = ioremap_nocache(efx->membase_phys, |
1064 | efx->type->mem_map_size); | |
8ceee660 | 1065 | if (!efx->membase) { |
62776d03 BH |
1066 | netif_err(efx, probe, efx->net_dev, |
1067 | "could not map memory BAR at %llx+%x\n", | |
1068 | (unsigned long long)efx->membase_phys, | |
1069 | efx->type->mem_map_size); | |
8ceee660 BH |
1070 | rc = -ENOMEM; |
1071 | goto fail4; | |
1072 | } | |
62776d03 BH |
1073 | netif_dbg(efx, probe, efx->net_dev, |
1074 | "memory BAR at %llx+%x (virtual %p)\n", | |
1075 | (unsigned long long)efx->membase_phys, | |
1076 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1077 | |
1078 | return 0; | |
1079 | ||
1080 | fail4: | |
dc803df8 | 1081 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1082 | fail3: |
2c118e0f | 1083 | efx->membase_phys = 0; |
8ceee660 BH |
1084 | fail2: |
1085 | pci_disable_device(efx->pci_dev); | |
1086 | fail1: | |
1087 | return rc; | |
1088 | } | |
1089 | ||
1090 | static void efx_fini_io(struct efx_nic *efx) | |
1091 | { | |
62776d03 | 1092 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1093 | |
1094 | if (efx->membase) { | |
1095 | iounmap(efx->membase); | |
1096 | efx->membase = NULL; | |
1097 | } | |
1098 | ||
1099 | if (efx->membase_phys) { | |
dc803df8 | 1100 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1101 | efx->membase_phys = 0; |
8ceee660 BH |
1102 | } |
1103 | ||
1104 | pci_disable_device(efx->pci_dev); | |
1105 | } | |
1106 | ||
fa142b9d | 1107 | static int efx_wanted_parallelism(void) |
46123d04 | 1108 | { |
cdb08f8f | 1109 | cpumask_var_t thread_mask; |
46123d04 BH |
1110 | int count; |
1111 | int cpu; | |
5b874e25 BH |
1112 | |
1113 | if (rss_cpus) | |
1114 | return rss_cpus; | |
46123d04 | 1115 | |
cdb08f8f | 1116 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { |
2f8975fb | 1117 | printk(KERN_WARNING |
3977d033 | 1118 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
1119 | return 1; |
1120 | } | |
1121 | ||
46123d04 BH |
1122 | count = 0; |
1123 | for_each_online_cpu(cpu) { | |
cdb08f8f | 1124 | if (!cpumask_test_cpu(cpu, thread_mask)) { |
46123d04 | 1125 | ++count; |
cdb08f8f BH |
1126 | cpumask_or(thread_mask, thread_mask, |
1127 | topology_thread_cpumask(cpu)); | |
46123d04 BH |
1128 | } |
1129 | } | |
1130 | ||
cdb08f8f | 1131 | free_cpumask_var(thread_mask); |
46123d04 BH |
1132 | return count; |
1133 | } | |
1134 | ||
64d8ad6d BH |
1135 | static int |
1136 | efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) | |
1137 | { | |
1138 | #ifdef CONFIG_RFS_ACCEL | |
1139 | int i, rc; | |
1140 | ||
1141 | efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); | |
1142 | if (!efx->net_dev->rx_cpu_rmap) | |
1143 | return -ENOMEM; | |
1144 | for (i = 0; i < efx->n_rx_channels; i++) { | |
1145 | rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, | |
1146 | xentries[i].vector); | |
1147 | if (rc) { | |
1148 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
1149 | efx->net_dev->rx_cpu_rmap = NULL; | |
1150 | return rc; | |
1151 | } | |
1152 | } | |
1153 | #endif | |
1154 | return 0; | |
1155 | } | |
1156 | ||
46123d04 BH |
1157 | /* Probe the number and type of interrupts we are able to obtain, and |
1158 | * the resulting numbers of channels and RX queues. | |
1159 | */ | |
64d8ad6d | 1160 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1161 | { |
46123d04 BH |
1162 | int max_channels = |
1163 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
1164 | int rc, i; |
1165 | ||
1166 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 1167 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a4900ac9 | 1168 | int n_channels; |
aa6ef27e | 1169 | |
fa142b9d | 1170 | n_channels = efx_wanted_parallelism(); |
a4900ac9 BH |
1171 | if (separate_tx_channels) |
1172 | n_channels *= 2; | |
1173 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 1174 | |
a4900ac9 | 1175 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1176 | xentries[i].entry = i; |
a4900ac9 | 1177 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1178 | if (rc > 0) { |
62776d03 BH |
1179 | netif_err(efx, drv, efx->net_dev, |
1180 | "WARNING: Insufficient MSI-X vectors" | |
1181 | " available (%d < %d).\n", rc, n_channels); | |
1182 | netif_err(efx, drv, efx->net_dev, | |
1183 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1184 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1185 | n_channels = rc; | |
8ceee660 | 1186 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1187 | n_channels); |
8ceee660 BH |
1188 | } |
1189 | ||
1190 | if (rc == 0) { | |
a4900ac9 BH |
1191 | efx->n_channels = n_channels; |
1192 | if (separate_tx_channels) { | |
1193 | efx->n_tx_channels = | |
1194 | max(efx->n_channels / 2, 1U); | |
1195 | efx->n_rx_channels = | |
1196 | max(efx->n_channels - | |
1197 | efx->n_tx_channels, 1U); | |
1198 | } else { | |
1199 | efx->n_tx_channels = efx->n_channels; | |
1200 | efx->n_rx_channels = efx->n_channels; | |
1201 | } | |
64d8ad6d BH |
1202 | rc = efx_init_rx_cpu_rmap(efx, xentries); |
1203 | if (rc) { | |
1204 | pci_disable_msix(efx->pci_dev); | |
1205 | return rc; | |
1206 | } | |
a4900ac9 | 1207 | for (i = 0; i < n_channels; i++) |
f7d12cdc BH |
1208 | efx_get_channel(efx, i)->irq = |
1209 | xentries[i].vector; | |
8ceee660 BH |
1210 | } else { |
1211 | /* Fall back to single channel MSI */ | |
1212 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1213 | netif_err(efx, drv, efx->net_dev, |
1214 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1215 | } |
1216 | } | |
1217 | ||
1218 | /* Try single interrupt MSI */ | |
1219 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1220 | efx->n_channels = 1; |
a4900ac9 BH |
1221 | efx->n_rx_channels = 1; |
1222 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1223 | rc = pci_enable_msi(efx->pci_dev); |
1224 | if (rc == 0) { | |
f7d12cdc | 1225 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1226 | } else { |
62776d03 BH |
1227 | netif_err(efx, drv, efx->net_dev, |
1228 | "could not enable MSI\n"); | |
8ceee660 BH |
1229 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1230 | } | |
1231 | } | |
1232 | ||
1233 | /* Assume legacy interrupts */ | |
1234 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1235 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1236 | efx->n_rx_channels = 1; |
1237 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1238 | efx->legacy_irq = efx->pci_dev->irq; |
1239 | } | |
64d8ad6d BH |
1240 | |
1241 | return 0; | |
8ceee660 BH |
1242 | } |
1243 | ||
9f2cb71c BH |
1244 | /* Enable interrupts, then probe and start the event queues */ |
1245 | static void efx_start_interrupts(struct efx_nic *efx) | |
1246 | { | |
1247 | struct efx_channel *channel; | |
1248 | ||
1249 | if (efx->legacy_irq) | |
1250 | efx->legacy_irq_enabled = true; | |
1251 | efx_nic_enable_interrupts(efx); | |
1252 | ||
1253 | efx_for_each_channel(channel, efx) { | |
1254 | efx_init_eventq(channel); | |
1255 | efx_start_eventq(channel); | |
1256 | } | |
1257 | ||
1258 | efx_mcdi_mode_event(efx); | |
1259 | } | |
1260 | ||
1261 | static void efx_stop_interrupts(struct efx_nic *efx) | |
1262 | { | |
1263 | struct efx_channel *channel; | |
1264 | ||
1265 | efx_mcdi_mode_poll(efx); | |
1266 | ||
1267 | efx_nic_disable_interrupts(efx); | |
1268 | if (efx->legacy_irq) { | |
1269 | synchronize_irq(efx->legacy_irq); | |
1270 | efx->legacy_irq_enabled = false; | |
1271 | } | |
1272 | ||
1273 | efx_for_each_channel(channel, efx) { | |
1274 | if (channel->irq) | |
1275 | synchronize_irq(channel->irq); | |
1276 | ||
1277 | efx_stop_eventq(channel); | |
1278 | efx_fini_eventq(channel); | |
1279 | } | |
1280 | } | |
1281 | ||
8ceee660 BH |
1282 | static void efx_remove_interrupts(struct efx_nic *efx) |
1283 | { | |
1284 | struct efx_channel *channel; | |
1285 | ||
1286 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1287 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1288 | channel->irq = 0; |
1289 | pci_disable_msi(efx->pci_dev); | |
1290 | pci_disable_msix(efx->pci_dev); | |
1291 | ||
1292 | /* Remove legacy interrupt */ | |
1293 | efx->legacy_irq = 0; | |
1294 | } | |
1295 | ||
8831da7b | 1296 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1297 | { |
602a5322 BH |
1298 | struct efx_channel *channel; |
1299 | struct efx_tx_queue *tx_queue; | |
1300 | ||
97653431 | 1301 | efx->tx_channel_offset = |
a4900ac9 | 1302 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 BH |
1303 | |
1304 | /* We need to adjust the TX queue numbers if we have separate | |
1305 | * RX-only and TX-only channels. | |
1306 | */ | |
1307 | efx_for_each_channel(channel, efx) { | |
1308 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1309 | tx_queue->queue -= (efx->tx_channel_offset * | |
1310 | EFX_TXQ_TYPES); | |
1311 | } | |
8ceee660 BH |
1312 | } |
1313 | ||
1314 | static int efx_probe_nic(struct efx_nic *efx) | |
1315 | { | |
765c9f46 | 1316 | size_t i; |
8ceee660 BH |
1317 | int rc; |
1318 | ||
62776d03 | 1319 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1320 | |
1321 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1322 | rc = efx->type->probe(efx); |
8ceee660 BH |
1323 | if (rc) |
1324 | return rc; | |
1325 | ||
a4900ac9 | 1326 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1327 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1328 | rc = efx_probe_interrupts(efx); |
1329 | if (rc) | |
1330 | goto fail; | |
8ceee660 | 1331 | |
5d3a6fca BH |
1332 | if (efx->n_channels > 1) |
1333 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1334 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 BH |
1335 | efx->rx_indir_table[i] = |
1336 | ethtool_rxfh_indir_default(i, efx->n_rx_channels); | |
5d3a6fca | 1337 | |
8831da7b | 1338 | efx_set_channels(efx); |
c4f4adc7 BH |
1339 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1340 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1341 | |
1342 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1343 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1344 | true); | |
8ceee660 BH |
1345 | |
1346 | return 0; | |
64d8ad6d BH |
1347 | |
1348 | fail: | |
1349 | efx->type->remove(efx); | |
1350 | return rc; | |
8ceee660 BH |
1351 | } |
1352 | ||
1353 | static void efx_remove_nic(struct efx_nic *efx) | |
1354 | { | |
62776d03 | 1355 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1356 | |
1357 | efx_remove_interrupts(efx); | |
ef2b90ee | 1358 | efx->type->remove(efx); |
8ceee660 BH |
1359 | } |
1360 | ||
1361 | /************************************************************************** | |
1362 | * | |
1363 | * NIC startup/shutdown | |
1364 | * | |
1365 | *************************************************************************/ | |
1366 | ||
1367 | static int efx_probe_all(struct efx_nic *efx) | |
1368 | { | |
8ceee660 BH |
1369 | int rc; |
1370 | ||
8ceee660 BH |
1371 | rc = efx_probe_nic(efx); |
1372 | if (rc) { | |
62776d03 | 1373 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1374 | goto fail1; |
1375 | } | |
1376 | ||
8ceee660 BH |
1377 | rc = efx_probe_port(efx); |
1378 | if (rc) { | |
62776d03 | 1379 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1380 | goto fail2; |
1381 | } | |
1382 | ||
ecc910f5 | 1383 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
4642610c BH |
1384 | rc = efx_probe_channels(efx); |
1385 | if (rc) | |
1386 | goto fail3; | |
8ceee660 | 1387 | |
64eebcfd BH |
1388 | rc = efx_probe_filters(efx); |
1389 | if (rc) { | |
1390 | netif_err(efx, probe, efx->net_dev, | |
1391 | "failed to create filter tables\n"); | |
1392 | goto fail4; | |
1393 | } | |
1394 | ||
8ceee660 BH |
1395 | return 0; |
1396 | ||
64eebcfd BH |
1397 | fail4: |
1398 | efx_remove_channels(efx); | |
8ceee660 | 1399 | fail3: |
8ceee660 BH |
1400 | efx_remove_port(efx); |
1401 | fail2: | |
1402 | efx_remove_nic(efx); | |
1403 | fail1: | |
1404 | return rc; | |
1405 | } | |
1406 | ||
9f2cb71c BH |
1407 | /* Called after previous invocation(s) of efx_stop_all, restarts the port, |
1408 | * kernel transmit queues and NAPI processing, and ensures that the port is | |
1409 | * scheduled to be reconfigured. This function is safe to call multiple | |
1410 | * times when the NIC is in any state. | |
1411 | */ | |
8ceee660 BH |
1412 | static void efx_start_all(struct efx_nic *efx) |
1413 | { | |
8ceee660 BH |
1414 | EFX_ASSERT_RESET_SERIALISED(efx); |
1415 | ||
1416 | /* Check that it is appropriate to restart the interface. All | |
1417 | * of these flags are safe to read under just the rtnl lock */ | |
1418 | if (efx->port_enabled) | |
1419 | return; | |
1420 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1421 | return; | |
73ba7b68 | 1422 | if (!netif_running(efx->net_dev)) |
8ceee660 BH |
1423 | return; |
1424 | ||
8ceee660 | 1425 | efx_start_port(efx); |
9f2cb71c | 1426 | efx_start_datapath(efx); |
8880f4ec | 1427 | |
78c1f0a0 SH |
1428 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1429 | * event driven), we have to poll the PHY because after an event queue | |
1430 | * flush, we could have a missed a link state change */ | |
1431 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1432 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1433 | efx_monitor_interval); | |
78c1f0a0 SH |
1434 | } else { |
1435 | mutex_lock(&efx->mac_lock); | |
1436 | if (efx->phy_op->poll(efx)) | |
1437 | efx_link_status_changed(efx); | |
1438 | mutex_unlock(&efx->mac_lock); | |
1439 | } | |
55edc6e6 | 1440 | |
ef2b90ee | 1441 | efx->type->start_stats(efx); |
8ceee660 BH |
1442 | } |
1443 | ||
1444 | /* Flush all delayed work. Should only be called when no more delayed work | |
1445 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1446 | * since we're holding the rtnl_lock at this point. */ | |
1447 | static void efx_flush_all(struct efx_nic *efx) | |
1448 | { | |
8ceee660 BH |
1449 | /* Make sure the hardware monitor is stopped */ |
1450 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1451 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1452 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1453 | } |
1454 | ||
1455 | /* Quiesce hardware and software without bringing the link down. | |
1456 | * Safe to call multiple times, when the nic and interface is in any | |
1457 | * state. The caller is guaranteed to subsequently be in a position | |
1458 | * to modify any hardware and software state they see fit without | |
1459 | * taking locks. */ | |
1460 | static void efx_stop_all(struct efx_nic *efx) | |
1461 | { | |
8ceee660 BH |
1462 | EFX_ASSERT_RESET_SERIALISED(efx); |
1463 | ||
1464 | /* port_enabled can be read safely under the rtnl lock */ | |
1465 | if (!efx->port_enabled) | |
1466 | return; | |
1467 | ||
ef2b90ee | 1468 | efx->type->stop_stats(efx); |
8ceee660 BH |
1469 | efx_stop_port(efx); |
1470 | ||
fdaa9aed | 1471 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1472 | efx_flush_all(efx); |
1473 | ||
8ceee660 BH |
1474 | /* Stop the kernel transmit interface late, so the watchdog |
1475 | * timer isn't ticking over the flush */ | |
9f2cb71c BH |
1476 | netif_tx_disable(efx->net_dev); |
1477 | ||
1478 | efx_stop_datapath(efx); | |
8ceee660 BH |
1479 | } |
1480 | ||
1481 | static void efx_remove_all(struct efx_nic *efx) | |
1482 | { | |
64eebcfd | 1483 | efx_remove_filters(efx); |
4642610c | 1484 | efx_remove_channels(efx); |
8ceee660 BH |
1485 | efx_remove_port(efx); |
1486 | efx_remove_nic(efx); | |
1487 | } | |
1488 | ||
8ceee660 BH |
1489 | /************************************************************************** |
1490 | * | |
1491 | * Interrupt moderation | |
1492 | * | |
1493 | **************************************************************************/ | |
1494 | ||
cc180b69 | 1495 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1496 | { |
b548f976 BH |
1497 | if (usecs == 0) |
1498 | return 0; | |
cc180b69 | 1499 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1500 | return 1; /* never round down to 0 */ |
cc180b69 | 1501 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1502 | } |
1503 | ||
8ceee660 | 1504 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1505 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1506 | unsigned int rx_usecs, bool rx_adaptive, | |
1507 | bool rx_may_override_tx) | |
8ceee660 | 1508 | { |
f7d12cdc | 1509 | struct efx_channel *channel; |
cc180b69 BH |
1510 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1511 | efx->timer_quantum_ns, | |
1512 | 1000); | |
1513 | unsigned int tx_ticks; | |
1514 | unsigned int rx_ticks; | |
8ceee660 BH |
1515 | |
1516 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1517 | ||
cc180b69 | 1518 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1519 | return -EINVAL; |
1520 | ||
cc180b69 BH |
1521 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1522 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1523 | ||
9e393b30 BH |
1524 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1525 | !rx_may_override_tx) { | |
1526 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1527 | "RX and TX IRQ moderation must be equal\n"); | |
1528 | return -EINVAL; | |
1529 | } | |
1530 | ||
6fb70fd1 | 1531 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1532 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1533 | efx_for_each_channel(channel, efx) { |
525da907 | 1534 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1535 | channel->irq_moderation = rx_ticks; |
525da907 | 1536 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1537 | channel->irq_moderation = tx_ticks; |
1538 | } | |
9e393b30 BH |
1539 | |
1540 | return 0; | |
8ceee660 BH |
1541 | } |
1542 | ||
a0c4faf5 BH |
1543 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1544 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1545 | { | |
cc180b69 BH |
1546 | /* We must round up when converting ticks to microseconds |
1547 | * because we round down when converting the other way. | |
1548 | */ | |
1549 | ||
a0c4faf5 | 1550 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1551 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1552 | efx->timer_quantum_ns, | |
1553 | 1000); | |
a0c4faf5 BH |
1554 | |
1555 | /* If channels are shared between RX and TX, so is IRQ | |
1556 | * moderation. Otherwise, IRQ moderation is the same for all | |
1557 | * TX channels and is not adaptive. | |
1558 | */ | |
1559 | if (efx->tx_channel_offset == 0) | |
1560 | *tx_usecs = *rx_usecs; | |
1561 | else | |
cc180b69 | 1562 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1563 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1564 | efx->timer_quantum_ns, |
1565 | 1000); | |
a0c4faf5 BH |
1566 | } |
1567 | ||
8ceee660 BH |
1568 | /************************************************************************** |
1569 | * | |
1570 | * Hardware monitor | |
1571 | * | |
1572 | **************************************************************************/ | |
1573 | ||
e254c274 | 1574 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1575 | static void efx_monitor(struct work_struct *data) |
1576 | { | |
1577 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1578 | monitor_work.work); | |
8ceee660 | 1579 | |
62776d03 BH |
1580 | netif_vdbg(efx, timer, efx->net_dev, |
1581 | "hardware monitor executing on CPU %d\n", | |
1582 | raw_smp_processor_id()); | |
ef2b90ee | 1583 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1584 | |
8ceee660 BH |
1585 | /* If the mac_lock is already held then it is likely a port |
1586 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1587 | * most of the work of monitor() anyway. */ |
1588 | if (mutex_trylock(&efx->mac_lock)) { | |
1589 | if (efx->port_enabled) | |
1590 | efx->type->monitor(efx); | |
1591 | mutex_unlock(&efx->mac_lock); | |
1592 | } | |
8ceee660 | 1593 | |
8ceee660 BH |
1594 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1595 | efx_monitor_interval); | |
1596 | } | |
1597 | ||
1598 | /************************************************************************** | |
1599 | * | |
1600 | * ioctls | |
1601 | * | |
1602 | *************************************************************************/ | |
1603 | ||
1604 | /* Net device ioctl | |
1605 | * Context: process, rtnl_lock() held. | |
1606 | */ | |
1607 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1608 | { | |
767e468c | 1609 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1610 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1611 | |
1612 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1613 | ||
68e7f45e BH |
1614 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1615 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1616 | (data->phy_id & 0xfc00) == 0x0400) | |
1617 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1618 | ||
1619 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1620 | } |
1621 | ||
1622 | /************************************************************************** | |
1623 | * | |
1624 | * NAPI interface | |
1625 | * | |
1626 | **************************************************************************/ | |
1627 | ||
e8f14992 | 1628 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1629 | { |
1630 | struct efx_channel *channel; | |
8ceee660 BH |
1631 | |
1632 | efx_for_each_channel(channel, efx) { | |
1633 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1634 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1635 | efx_poll, napi_weight); | |
8ceee660 | 1636 | } |
e8f14992 BH |
1637 | } |
1638 | ||
1639 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1640 | { | |
1641 | if (channel->napi_dev) | |
1642 | netif_napi_del(&channel->napi_str); | |
1643 | channel->napi_dev = NULL; | |
8ceee660 BH |
1644 | } |
1645 | ||
1646 | static void efx_fini_napi(struct efx_nic *efx) | |
1647 | { | |
1648 | struct efx_channel *channel; | |
1649 | ||
e8f14992 BH |
1650 | efx_for_each_channel(channel, efx) |
1651 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1652 | } |
1653 | ||
1654 | /************************************************************************** | |
1655 | * | |
1656 | * Kernel netpoll interface | |
1657 | * | |
1658 | *************************************************************************/ | |
1659 | ||
1660 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1661 | ||
1662 | /* Although in the common case interrupts will be disabled, this is not | |
1663 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1664 | * so no locking is required. | |
1665 | */ | |
1666 | static void efx_netpoll(struct net_device *net_dev) | |
1667 | { | |
767e468c | 1668 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1669 | struct efx_channel *channel; |
1670 | ||
64ee3120 | 1671 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1672 | efx_schedule_channel(channel); |
1673 | } | |
1674 | ||
1675 | #endif | |
1676 | ||
1677 | /************************************************************************** | |
1678 | * | |
1679 | * Kernel net device interface | |
1680 | * | |
1681 | *************************************************************************/ | |
1682 | ||
1683 | /* Context: process, rtnl_lock() held. */ | |
1684 | static int efx_net_open(struct net_device *net_dev) | |
1685 | { | |
767e468c | 1686 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1687 | EFX_ASSERT_RESET_SERIALISED(efx); |
1688 | ||
62776d03 BH |
1689 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1690 | raw_smp_processor_id()); | |
8ceee660 | 1691 | |
f4bd954e BH |
1692 | if (efx->state == STATE_DISABLED) |
1693 | return -EIO; | |
f8b87c17 BH |
1694 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1695 | return -EBUSY; | |
8880f4ec BH |
1696 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1697 | return -EIO; | |
f8b87c17 | 1698 | |
78c1f0a0 SH |
1699 | /* Notify the kernel of the link state polled during driver load, |
1700 | * before the monitor starts running */ | |
1701 | efx_link_status_changed(efx); | |
1702 | ||
8ceee660 BH |
1703 | efx_start_all(efx); |
1704 | return 0; | |
1705 | } | |
1706 | ||
1707 | /* Context: process, rtnl_lock() held. | |
1708 | * Note that the kernel will ignore our return code; this method | |
1709 | * should really be a void. | |
1710 | */ | |
1711 | static int efx_net_stop(struct net_device *net_dev) | |
1712 | { | |
767e468c | 1713 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1714 | |
62776d03 BH |
1715 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1716 | raw_smp_processor_id()); | |
8ceee660 | 1717 | |
f4bd954e BH |
1718 | if (efx->state != STATE_DISABLED) { |
1719 | /* Stop the device and flush all the channels */ | |
1720 | efx_stop_all(efx); | |
f4bd954e | 1721 | } |
8ceee660 BH |
1722 | |
1723 | return 0; | |
1724 | } | |
1725 | ||
5b9e207c | 1726 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
1727 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
1728 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 1729 | { |
767e468c | 1730 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1731 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1732 | |
55edc6e6 | 1733 | spin_lock_bh(&efx->stats_lock); |
1cb34522 | 1734 | |
ef2b90ee | 1735 | efx->type->update_stats(efx); |
8ceee660 BH |
1736 | |
1737 | stats->rx_packets = mac_stats->rx_packets; | |
1738 | stats->tx_packets = mac_stats->tx_packets; | |
1739 | stats->rx_bytes = mac_stats->rx_bytes; | |
1740 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1741 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1742 | stats->multicast = mac_stats->rx_multicast; |
1743 | stats->collisions = mac_stats->tx_collision; | |
1744 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1745 | mac_stats->rx_length_error); | |
8ceee660 BH |
1746 | stats->rx_crc_errors = mac_stats->rx_bad; |
1747 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1748 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1749 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1750 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1751 | ||
1752 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1753 | stats->rx_crc_errors + |
1754 | stats->rx_frame_errors + | |
8ceee660 BH |
1755 | mac_stats->rx_symbol_error); |
1756 | stats->tx_errors = (stats->tx_window_errors + | |
1757 | mac_stats->tx_bad); | |
1758 | ||
1cb34522 BH |
1759 | spin_unlock_bh(&efx->stats_lock); |
1760 | ||
8ceee660 BH |
1761 | return stats; |
1762 | } | |
1763 | ||
1764 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1765 | static void efx_watchdog(struct net_device *net_dev) | |
1766 | { | |
767e468c | 1767 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1768 | |
62776d03 BH |
1769 | netif_err(efx, tx_err, efx->net_dev, |
1770 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1771 | efx->port_enabled); | |
8ceee660 | 1772 | |
739bb23d | 1773 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1774 | } |
1775 | ||
1776 | ||
1777 | /* Context: process, rtnl_lock() held. */ | |
1778 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1779 | { | |
767e468c | 1780 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1781 | |
1782 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1783 | ||
1784 | if (new_mtu > EFX_MAX_MTU) | |
1785 | return -EINVAL; | |
1786 | ||
1787 | efx_stop_all(efx); | |
1788 | ||
62776d03 | 1789 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 1790 | |
d3245b28 BH |
1791 | mutex_lock(&efx->mac_lock); |
1792 | /* Reconfigure the MAC before enabling the dma queues so that | |
1793 | * the RX buffers don't overflow */ | |
8ceee660 | 1794 | net_dev->mtu = new_mtu; |
710b208d | 1795 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1796 | mutex_unlock(&efx->mac_lock); |
1797 | ||
8ceee660 | 1798 | efx_start_all(efx); |
6c8eef4a | 1799 | return 0; |
8ceee660 BH |
1800 | } |
1801 | ||
1802 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1803 | { | |
767e468c | 1804 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1805 | struct sockaddr *addr = data; |
1806 | char *new_addr = addr->sa_data; | |
1807 | ||
1808 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1809 | ||
1810 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1811 | netif_err(efx, drv, efx->net_dev, |
1812 | "invalid ethernet MAC address requested: %pM\n", | |
1813 | new_addr); | |
8ceee660 BH |
1814 | return -EINVAL; |
1815 | } | |
1816 | ||
1817 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1818 | ||
1819 | /* Reconfigure the MAC */ | |
d3245b28 | 1820 | mutex_lock(&efx->mac_lock); |
710b208d | 1821 | efx->type->reconfigure_mac(efx); |
d3245b28 | 1822 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
1823 | |
1824 | return 0; | |
1825 | } | |
1826 | ||
a816f75a | 1827 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 1828 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 1829 | { |
767e468c | 1830 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1831 | struct netdev_hw_addr *ha; |
8ceee660 | 1832 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1833 | u32 crc; |
1834 | int bit; | |
8ceee660 | 1835 | |
8be4f3e6 | 1836 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1837 | |
1838 | /* Build multicast hash table */ | |
8be4f3e6 | 1839 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1840 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1841 | } else { | |
1842 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1843 | netdev_for_each_mc_addr(ha, net_dev) { |
1844 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1845 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1846 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1847 | } |
8ceee660 | 1848 | |
8be4f3e6 BH |
1849 | /* Broadcast packets go through the multicast hash filter. |
1850 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1851 | * so we always add bit 0xff to the mask. | |
1852 | */ | |
1853 | set_bit_le(0xff, mc_hash->byte); | |
1854 | } | |
a816f75a | 1855 | |
8be4f3e6 BH |
1856 | if (efx->port_enabled) |
1857 | queue_work(efx->workqueue, &efx->mac_work); | |
1858 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1859 | } |
1860 | ||
c8f44aff | 1861 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
1862 | { |
1863 | struct efx_nic *efx = netdev_priv(net_dev); | |
1864 | ||
1865 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
1866 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
1867 | efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
1868 | ||
1869 | return 0; | |
1870 | } | |
1871 | ||
c3ecb9f3 SH |
1872 | static const struct net_device_ops efx_netdev_ops = { |
1873 | .ndo_open = efx_net_open, | |
1874 | .ndo_stop = efx_net_stop, | |
4472702e | 1875 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
1876 | .ndo_tx_timeout = efx_watchdog, |
1877 | .ndo_start_xmit = efx_hard_start_xmit, | |
1878 | .ndo_validate_addr = eth_validate_addr, | |
1879 | .ndo_do_ioctl = efx_ioctl, | |
1880 | .ndo_change_mtu = efx_change_mtu, | |
1881 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 1882 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 1883 | .ndo_set_features = efx_set_features, |
c3ecb9f3 SH |
1884 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1885 | .ndo_poll_controller = efx_netpoll, | |
1886 | #endif | |
94b274bf | 1887 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
1888 | #ifdef CONFIG_RFS_ACCEL |
1889 | .ndo_rx_flow_steer = efx_filter_rfs, | |
1890 | #endif | |
c3ecb9f3 SH |
1891 | }; |
1892 | ||
7dde596e BH |
1893 | static void efx_update_name(struct efx_nic *efx) |
1894 | { | |
1895 | strcpy(efx->name, efx->net_dev->name); | |
1896 | efx_mtd_rename(efx); | |
1897 | efx_set_channel_names(efx); | |
1898 | } | |
1899 | ||
8ceee660 BH |
1900 | static int efx_netdev_event(struct notifier_block *this, |
1901 | unsigned long event, void *ptr) | |
1902 | { | |
d3208b5e | 1903 | struct net_device *net_dev = ptr; |
8ceee660 | 1904 | |
7dde596e BH |
1905 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1906 | event == NETDEV_CHANGENAME) | |
1907 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1908 | |
1909 | return NOTIFY_DONE; | |
1910 | } | |
1911 | ||
1912 | static struct notifier_block efx_netdev_notifier = { | |
1913 | .notifier_call = efx_netdev_event, | |
1914 | }; | |
1915 | ||
06d5e193 BH |
1916 | static ssize_t |
1917 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1918 | { | |
1919 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1920 | return sprintf(buf, "%d\n", efx->phy_type); | |
1921 | } | |
1922 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1923 | ||
8ceee660 BH |
1924 | static int efx_register_netdev(struct efx_nic *efx) |
1925 | { | |
1926 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 1927 | struct efx_channel *channel; |
8ceee660 BH |
1928 | int rc; |
1929 | ||
1930 | net_dev->watchdog_timeo = 5 * HZ; | |
1931 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1932 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1933 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
1934 | ||
7dde596e | 1935 | rtnl_lock(); |
aed0628d BH |
1936 | |
1937 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1938 | if (rc < 0) | |
1939 | goto fail_locked; | |
7dde596e | 1940 | efx_update_name(efx); |
aed0628d BH |
1941 | |
1942 | rc = register_netdevice(net_dev); | |
1943 | if (rc) | |
1944 | goto fail_locked; | |
1945 | ||
c04bfc6b BH |
1946 | efx_for_each_channel(channel, efx) { |
1947 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
1948 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1949 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
1950 | } |
1951 | ||
aed0628d | 1952 | /* Always start with carrier off; PHY events will detect the link */ |
86ee5302 | 1953 | netif_carrier_off(net_dev); |
aed0628d | 1954 | |
7dde596e | 1955 | rtnl_unlock(); |
8ceee660 | 1956 | |
06d5e193 BH |
1957 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1958 | if (rc) { | |
62776d03 BH |
1959 | netif_err(efx, drv, efx->net_dev, |
1960 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
1961 | goto fail_registered; |
1962 | } | |
1963 | ||
8ceee660 | 1964 | return 0; |
06d5e193 | 1965 | |
aed0628d BH |
1966 | fail_locked: |
1967 | rtnl_unlock(); | |
62776d03 | 1968 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
1969 | return rc; |
1970 | ||
06d5e193 BH |
1971 | fail_registered: |
1972 | unregister_netdev(net_dev); | |
1973 | return rc; | |
8ceee660 BH |
1974 | } |
1975 | ||
1976 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1977 | { | |
f7d12cdc | 1978 | struct efx_channel *channel; |
8ceee660 BH |
1979 | struct efx_tx_queue *tx_queue; |
1980 | ||
1981 | if (!efx->net_dev) | |
1982 | return; | |
1983 | ||
767e468c | 1984 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1985 | |
1986 | /* Free up any skbs still remaining. This has to happen before | |
1987 | * we try to unregister the netdev as running their destructors | |
1988 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
1989 | efx_for_each_channel(channel, efx) { |
1990 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1991 | efx_release_tx_buffers(tx_queue); | |
1992 | } | |
8ceee660 | 1993 | |
73ba7b68 BH |
1994 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
1995 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
1996 | unregister_netdev(efx->net_dev); | |
8ceee660 BH |
1997 | } |
1998 | ||
1999 | /************************************************************************** | |
2000 | * | |
2001 | * Device reset and suspend | |
2002 | * | |
2003 | **************************************************************************/ | |
2004 | ||
2467ca46 BH |
2005 | /* Tears down the entire software state and most of the hardware state |
2006 | * before reset. */ | |
d3245b28 | 2007 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2008 | { |
8ceee660 BH |
2009 | EFX_ASSERT_RESET_SERIALISED(efx); |
2010 | ||
2467ca46 BH |
2011 | efx_stop_all(efx); |
2012 | mutex_lock(&efx->mac_lock); | |
2013 | ||
9f2cb71c | 2014 | efx_stop_interrupts(efx); |
4b988280 SH |
2015 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2016 | efx->phy_op->fini(efx); | |
ef2b90ee | 2017 | efx->type->fini(efx); |
8ceee660 BH |
2018 | } |
2019 | ||
2467ca46 BH |
2020 | /* This function will always ensure that the locks acquired in |
2021 | * efx_reset_down() are released. A failure return code indicates | |
2022 | * that we were unable to reinitialise the hardware, and the | |
2023 | * driver should be disabled. If ok is false, then the rx and tx | |
2024 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2025 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2026 | { |
2027 | int rc; | |
2028 | ||
2467ca46 | 2029 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2030 | |
ef2b90ee | 2031 | rc = efx->type->init(efx); |
8ceee660 | 2032 | if (rc) { |
62776d03 | 2033 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2034 | goto fail; |
8ceee660 BH |
2035 | } |
2036 | ||
eb9f6744 BH |
2037 | if (!ok) |
2038 | goto fail; | |
2039 | ||
4b988280 | 2040 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2041 | rc = efx->phy_op->init(efx); |
2042 | if (rc) | |
2043 | goto fail; | |
2044 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2045 | netif_err(efx, drv, efx->net_dev, |
2046 | "could not restore PHY settings\n"); | |
4b988280 SH |
2047 | } |
2048 | ||
710b208d | 2049 | efx->type->reconfigure_mac(efx); |
8ceee660 | 2050 | |
9f2cb71c | 2051 | efx_start_interrupts(efx); |
64eebcfd | 2052 | efx_restore_filters(efx); |
eb9f6744 | 2053 | |
eb9f6744 BH |
2054 | mutex_unlock(&efx->mac_lock); |
2055 | ||
2056 | efx_start_all(efx); | |
2057 | ||
2058 | return 0; | |
2059 | ||
2060 | fail: | |
2061 | efx->port_initialized = false; | |
2467ca46 BH |
2062 | |
2063 | mutex_unlock(&efx->mac_lock); | |
2064 | ||
8ceee660 BH |
2065 | return rc; |
2066 | } | |
2067 | ||
eb9f6744 BH |
2068 | /* Reset the NIC using the specified method. Note that the reset may |
2069 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2070 | * |
eb9f6744 | 2071 | * Caller must hold the rtnl_lock. |
8ceee660 | 2072 | */ |
eb9f6744 | 2073 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2074 | { |
eb9f6744 BH |
2075 | int rc, rc2; |
2076 | bool disabled; | |
8ceee660 | 2077 | |
62776d03 BH |
2078 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2079 | RESET_TYPE(method)); | |
8ceee660 | 2080 | |
e4abce85 | 2081 | netif_device_detach(efx->net_dev); |
d3245b28 | 2082 | efx_reset_down(efx, method); |
8ceee660 | 2083 | |
ef2b90ee | 2084 | rc = efx->type->reset(efx, method); |
8ceee660 | 2085 | if (rc) { |
62776d03 | 2086 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2087 | goto out; |
8ceee660 BH |
2088 | } |
2089 | ||
a7d529ae BH |
2090 | /* Clear flags for the scopes we covered. We assume the NIC and |
2091 | * driver are now quiescent so that there is no race here. | |
2092 | */ | |
2093 | efx->reset_pending &= -(1 << (method + 1)); | |
8ceee660 BH |
2094 | |
2095 | /* Reinitialise bus-mastering, which may have been turned off before | |
2096 | * the reset was scheduled. This is still appropriate, even in the | |
2097 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2098 | * can respond to requests. */ | |
2099 | pci_set_master(efx->pci_dev); | |
2100 | ||
eb9f6744 | 2101 | out: |
8ceee660 | 2102 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2103 | disabled = rc || method == RESET_TYPE_DISABLE; |
2104 | rc2 = efx_reset_up(efx, method, !disabled); | |
2105 | if (rc2) { | |
2106 | disabled = true; | |
2107 | if (!rc) | |
2108 | rc = rc2; | |
8ceee660 BH |
2109 | } |
2110 | ||
eb9f6744 | 2111 | if (disabled) { |
f49a4589 | 2112 | dev_close(efx->net_dev); |
62776d03 | 2113 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2114 | efx->state = STATE_DISABLED; |
f4bd954e | 2115 | } else { |
62776d03 | 2116 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2117 | netif_device_attach(efx->net_dev); |
f4bd954e | 2118 | } |
8ceee660 BH |
2119 | return rc; |
2120 | } | |
2121 | ||
2122 | /* The worker thread exists so that code that cannot sleep can | |
2123 | * schedule a reset for later. | |
2124 | */ | |
2125 | static void efx_reset_work(struct work_struct *data) | |
2126 | { | |
eb9f6744 | 2127 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
a7d529ae | 2128 | unsigned long pending = ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 2129 | |
a7d529ae | 2130 | if (!pending) |
319ba649 SH |
2131 | return; |
2132 | ||
eb9f6744 | 2133 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
a7d529ae | 2134 | * flags set so that efx_pci_probe_main will be retried */ |
eb9f6744 | 2135 | if (efx->state != STATE_RUNNING) { |
62776d03 BH |
2136 | netif_info(efx, drv, efx->net_dev, |
2137 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
2138 | return; |
2139 | } | |
2140 | ||
2141 | rtnl_lock(); | |
a7d529ae | 2142 | (void)efx_reset(efx, fls(pending) - 1); |
eb9f6744 | 2143 | rtnl_unlock(); |
8ceee660 BH |
2144 | } |
2145 | ||
2146 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2147 | { | |
2148 | enum reset_type method; | |
2149 | ||
8ceee660 BH |
2150 | switch (type) { |
2151 | case RESET_TYPE_INVISIBLE: | |
2152 | case RESET_TYPE_ALL: | |
2153 | case RESET_TYPE_WORLD: | |
2154 | case RESET_TYPE_DISABLE: | |
2155 | method = type; | |
0e2a9c7c BH |
2156 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2157 | RESET_TYPE(method)); | |
8ceee660 | 2158 | break; |
8ceee660 | 2159 | default: |
0e2a9c7c | 2160 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2161 | netif_dbg(efx, drv, efx->net_dev, |
2162 | "scheduling %s reset for %s\n", | |
2163 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2164 | break; |
2165 | } | |
8ceee660 | 2166 | |
a7d529ae | 2167 | set_bit(method, &efx->reset_pending); |
8ceee660 | 2168 | |
8880f4ec BH |
2169 | /* efx_process_channel() will no longer read events once a |
2170 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2171 | efx_mcdi_mode_poll(efx); | |
2172 | ||
1ab00629 | 2173 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2174 | } |
2175 | ||
2176 | /************************************************************************** | |
2177 | * | |
2178 | * List of NICs we support | |
2179 | * | |
2180 | **************************************************************************/ | |
2181 | ||
2182 | /* PCI device ID table */ | |
a3aa1884 | 2183 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2184 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2185 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2186 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2187 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2188 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2189 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2190 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2191 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2192 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2193 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8ceee660 BH |
2194 | {0} /* end of list */ |
2195 | }; | |
2196 | ||
2197 | /************************************************************************** | |
2198 | * | |
3759433d | 2199 | * Dummy PHY/MAC operations |
8ceee660 | 2200 | * |
01aad7b6 | 2201 | * Can be used for some unimplemented operations |
8ceee660 BH |
2202 | * Needed so all function pointers are valid and do not have to be tested |
2203 | * before use | |
2204 | * | |
2205 | **************************************************************************/ | |
2206 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2207 | { | |
2208 | return 0; | |
2209 | } | |
2210 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2211 | |
2212 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2213 | { |
2214 | return false; | |
2215 | } | |
8ceee660 | 2216 | |
6c8c2513 | 2217 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2218 | .init = efx_port_dummy_op_int, |
d3245b28 | 2219 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2220 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2221 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2222 | }; |
2223 | ||
8ceee660 BH |
2224 | /************************************************************************** |
2225 | * | |
2226 | * Data housekeeping | |
2227 | * | |
2228 | **************************************************************************/ | |
2229 | ||
2230 | /* This zeroes out and then fills in the invariants in a struct | |
2231 | * efx_nic (including all sub-structures). | |
2232 | */ | |
6c8c2513 | 2233 | static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type, |
8ceee660 BH |
2234 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2235 | { | |
4642610c | 2236 | int i; |
8ceee660 BH |
2237 | |
2238 | /* Initialise common structures */ | |
2239 | memset(efx, 0, sizeof(*efx)); | |
2240 | spin_lock_init(&efx->biu_lock); | |
76884835 BH |
2241 | #ifdef CONFIG_SFC_MTD |
2242 | INIT_LIST_HEAD(&efx->mtd_list); | |
2243 | #endif | |
8ceee660 BH |
2244 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2245 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2246 | efx->pci_dev = pci_dev; | |
62776d03 | 2247 | efx->msg_enable = debug; |
8ceee660 | 2248 | efx->state = STATE_INIT; |
8ceee660 | 2249 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2250 | |
2251 | efx->net_dev = net_dev; | |
8ceee660 BH |
2252 | spin_lock_init(&efx->stats_lock); |
2253 | mutex_init(&efx->mac_lock); | |
2254 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2255 | efx->mdio.dev = net_dev; |
766ca0fa | 2256 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2257 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2258 | |
2259 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2260 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2261 | if (!efx->channel[i]) | |
2262 | goto fail; | |
8ceee660 BH |
2263 | } |
2264 | ||
2265 | efx->type = type; | |
2266 | ||
8ceee660 BH |
2267 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2268 | ||
2269 | /* Higher numbered interrupt modes are less capable! */ | |
2270 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2271 | interrupt_mode); | |
2272 | ||
6977dc63 BH |
2273 | /* Would be good to use the net_dev name, but we're too early */ |
2274 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2275 | pci_name(pci_dev)); | |
2276 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2277 | if (!efx->workqueue) |
4642610c | 2278 | goto fail; |
8d9853d9 | 2279 | |
8ceee660 | 2280 | return 0; |
4642610c BH |
2281 | |
2282 | fail: | |
2283 | efx_fini_struct(efx); | |
2284 | return -ENOMEM; | |
8ceee660 BH |
2285 | } |
2286 | ||
2287 | static void efx_fini_struct(struct efx_nic *efx) | |
2288 | { | |
8313aca3 BH |
2289 | int i; |
2290 | ||
2291 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2292 | kfree(efx->channel[i]); | |
2293 | ||
8ceee660 BH |
2294 | if (efx->workqueue) { |
2295 | destroy_workqueue(efx->workqueue); | |
2296 | efx->workqueue = NULL; | |
2297 | } | |
2298 | } | |
2299 | ||
2300 | /************************************************************************** | |
2301 | * | |
2302 | * PCI interface | |
2303 | * | |
2304 | **************************************************************************/ | |
2305 | ||
2306 | /* Main body of final NIC shutdown code | |
2307 | * This is called only at module unload (or hotplug removal). | |
2308 | */ | |
2309 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2310 | { | |
64d8ad6d BH |
2311 | #ifdef CONFIG_RFS_ACCEL |
2312 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
2313 | efx->net_dev->rx_cpu_rmap = NULL; | |
2314 | #endif | |
9f2cb71c | 2315 | efx_stop_interrupts(efx); |
152b6a62 | 2316 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2317 | efx_fini_port(efx); |
ef2b90ee | 2318 | efx->type->fini(efx); |
8ceee660 BH |
2319 | efx_fini_napi(efx); |
2320 | efx_remove_all(efx); | |
2321 | } | |
2322 | ||
2323 | /* Final NIC shutdown | |
2324 | * This is called only at module unload (or hotplug removal). | |
2325 | */ | |
2326 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2327 | { | |
2328 | struct efx_nic *efx; | |
2329 | ||
2330 | efx = pci_get_drvdata(pci_dev); | |
2331 | if (!efx) | |
2332 | return; | |
2333 | ||
2334 | /* Mark the NIC as fini, then stop the interface */ | |
2335 | rtnl_lock(); | |
2336 | efx->state = STATE_FINI; | |
2337 | dev_close(efx->net_dev); | |
2338 | ||
2339 | /* Allow any queued efx_resets() to complete */ | |
2340 | rtnl_unlock(); | |
2341 | ||
9f2cb71c | 2342 | efx_stop_interrupts(efx); |
8ceee660 BH |
2343 | efx_unregister_netdev(efx); |
2344 | ||
7dde596e BH |
2345 | efx_mtd_remove(efx); |
2346 | ||
8ceee660 BH |
2347 | /* Wait for any scheduled resets to complete. No more will be |
2348 | * scheduled from this point because efx_stop_all() has been | |
2349 | * called, we are no longer registered with driverlink, and | |
2350 | * the net_device's have been removed. */ | |
1ab00629 | 2351 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2352 | |
2353 | efx_pci_remove_main(efx); | |
2354 | ||
8ceee660 | 2355 | efx_fini_io(efx); |
62776d03 | 2356 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 BH |
2357 | |
2358 | pci_set_drvdata(pci_dev, NULL); | |
2359 | efx_fini_struct(efx); | |
2360 | free_netdev(efx->net_dev); | |
2361 | }; | |
2362 | ||
2363 | /* Main body of NIC initialisation | |
2364 | * This is called at module load (or hotplug insertion, theoretically). | |
2365 | */ | |
2366 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2367 | { | |
2368 | int rc; | |
2369 | ||
2370 | /* Do start-of-day initialisation */ | |
2371 | rc = efx_probe_all(efx); | |
2372 | if (rc) | |
2373 | goto fail1; | |
2374 | ||
e8f14992 | 2375 | efx_init_napi(efx); |
8ceee660 | 2376 | |
ef2b90ee | 2377 | rc = efx->type->init(efx); |
8ceee660 | 2378 | if (rc) { |
62776d03 BH |
2379 | netif_err(efx, probe, efx->net_dev, |
2380 | "failed to initialise NIC\n"); | |
278c0621 | 2381 | goto fail3; |
8ceee660 BH |
2382 | } |
2383 | ||
2384 | rc = efx_init_port(efx); | |
2385 | if (rc) { | |
62776d03 BH |
2386 | netif_err(efx, probe, efx->net_dev, |
2387 | "failed to initialise port\n"); | |
278c0621 | 2388 | goto fail4; |
8ceee660 BH |
2389 | } |
2390 | ||
152b6a62 | 2391 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2392 | if (rc) |
278c0621 | 2393 | goto fail5; |
9f2cb71c | 2394 | efx_start_interrupts(efx); |
8ceee660 BH |
2395 | |
2396 | return 0; | |
2397 | ||
278c0621 | 2398 | fail5: |
8ceee660 | 2399 | efx_fini_port(efx); |
8ceee660 | 2400 | fail4: |
ef2b90ee | 2401 | efx->type->fini(efx); |
8ceee660 BH |
2402 | fail3: |
2403 | efx_fini_napi(efx); | |
8ceee660 BH |
2404 | efx_remove_all(efx); |
2405 | fail1: | |
2406 | return rc; | |
2407 | } | |
2408 | ||
2409 | /* NIC initialisation | |
2410 | * | |
2411 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2412 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2413 | * sets up and registers the network devices with the kernel and hooks |
2414 | * the interrupt service routine. It does not prepare the device for | |
2415 | * transmission; this is left to the first time one of the network | |
2416 | * interfaces is brought up (i.e. efx_net_open). | |
2417 | */ | |
2418 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2419 | const struct pci_device_id *entry) | |
2420 | { | |
6c8c2513 | 2421 | const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data; |
8ceee660 BH |
2422 | struct net_device *net_dev; |
2423 | struct efx_nic *efx; | |
fadac6aa | 2424 | int rc; |
8ceee660 BH |
2425 | |
2426 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2427 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2428 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2429 | if (!net_dev) |
2430 | return -ENOMEM; | |
c383b537 | 2431 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 | 2432 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2433 | NETIF_F_RXCSUM); |
738a8f4b BH |
2434 | if (type->offload_features & NETIF_F_V6_CSUM) |
2435 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2436 | /* Mask for features that also apply to VLAN devices */ |
2437 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2438 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2439 | NETIF_F_RXCSUM); | |
2440 | /* All offloads can be toggled */ | |
2441 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
767e468c | 2442 | efx = netdev_priv(net_dev); |
8ceee660 | 2443 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2444 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2445 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2446 | if (rc) | |
2447 | goto fail1; | |
2448 | ||
62776d03 | 2449 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2450 | "Solarflare NIC detected\n"); |
8ceee660 BH |
2451 | |
2452 | /* Set up basic I/O (BAR mappings etc) */ | |
2453 | rc = efx_init_io(efx); | |
2454 | if (rc) | |
2455 | goto fail2; | |
2456 | ||
fadac6aa | 2457 | rc = efx_pci_probe_main(efx); |
fa402b2e | 2458 | |
fadac6aa BH |
2459 | /* Serialise against efx_reset(). No more resets will be |
2460 | * scheduled since efx_stop_all() has been called, and we have | |
2461 | * not and never have been registered. | |
2462 | */ | |
2463 | cancel_work_sync(&efx->reset_work); | |
8ceee660 | 2464 | |
fadac6aa BH |
2465 | if (rc) |
2466 | goto fail3; | |
8ceee660 | 2467 | |
fadac6aa BH |
2468 | /* If there was a scheduled reset during probe, the NIC is |
2469 | * probably hosed anyway. | |
2470 | */ | |
2471 | if (efx->reset_pending) { | |
2472 | rc = -EIO; | |
8ceee660 BH |
2473 | goto fail4; |
2474 | } | |
2475 | ||
55edc6e6 BH |
2476 | /* Switch to the running state before we expose the device to the OS, |
2477 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2478 | efx->state = STATE_RUNNING; |
7dde596e | 2479 | |
8ceee660 BH |
2480 | rc = efx_register_netdev(efx); |
2481 | if (rc) | |
fadac6aa | 2482 | goto fail4; |
8ceee660 | 2483 | |
62776d03 | 2484 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 2485 | |
7c43161c | 2486 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 2487 | rtnl_lock(); |
7c43161c | 2488 | rc = efx_mtd_probe(efx); |
a5211bb5 | 2489 | rtnl_unlock(); |
7c43161c BH |
2490 | if (rc) |
2491 | netif_warn(efx, probe, efx->net_dev, | |
2492 | "failed to create MTDs (%d)\n", rc); | |
2493 | ||
8ceee660 BH |
2494 | return 0; |
2495 | ||
8ceee660 | 2496 | fail4: |
fadac6aa | 2497 | efx_pci_remove_main(efx); |
8ceee660 BH |
2498 | fail3: |
2499 | efx_fini_io(efx); | |
2500 | fail2: | |
2501 | efx_fini_struct(efx); | |
2502 | fail1: | |
5e2a911c | 2503 | WARN_ON(rc > 0); |
62776d03 | 2504 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2505 | free_netdev(net_dev); |
2506 | return rc; | |
2507 | } | |
2508 | ||
89c758fa BH |
2509 | static int efx_pm_freeze(struct device *dev) |
2510 | { | |
2511 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2512 | ||
2513 | efx->state = STATE_FINI; | |
2514 | ||
2515 | netif_device_detach(efx->net_dev); | |
2516 | ||
2517 | efx_stop_all(efx); | |
9f2cb71c | 2518 | efx_stop_interrupts(efx); |
89c758fa BH |
2519 | |
2520 | return 0; | |
2521 | } | |
2522 | ||
2523 | static int efx_pm_thaw(struct device *dev) | |
2524 | { | |
2525 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2526 | ||
2527 | efx->state = STATE_INIT; | |
2528 | ||
9f2cb71c | 2529 | efx_start_interrupts(efx); |
89c758fa BH |
2530 | |
2531 | mutex_lock(&efx->mac_lock); | |
2532 | efx->phy_op->reconfigure(efx); | |
2533 | mutex_unlock(&efx->mac_lock); | |
2534 | ||
2535 | efx_start_all(efx); | |
2536 | ||
2537 | netif_device_attach(efx->net_dev); | |
2538 | ||
2539 | efx->state = STATE_RUNNING; | |
2540 | ||
2541 | efx->type->resume_wol(efx); | |
2542 | ||
319ba649 SH |
2543 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2544 | queue_work(reset_workqueue, &efx->reset_work); | |
2545 | ||
89c758fa BH |
2546 | return 0; |
2547 | } | |
2548 | ||
2549 | static int efx_pm_poweroff(struct device *dev) | |
2550 | { | |
2551 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2552 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2553 | ||
2554 | efx->type->fini(efx); | |
2555 | ||
a7d529ae | 2556 | efx->reset_pending = 0; |
89c758fa BH |
2557 | |
2558 | pci_save_state(pci_dev); | |
2559 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2560 | } | |
2561 | ||
2562 | /* Used for both resume and restore */ | |
2563 | static int efx_pm_resume(struct device *dev) | |
2564 | { | |
2565 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2566 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2567 | int rc; | |
2568 | ||
2569 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2570 | if (rc) | |
2571 | return rc; | |
2572 | pci_restore_state(pci_dev); | |
2573 | rc = pci_enable_device(pci_dev); | |
2574 | if (rc) | |
2575 | return rc; | |
2576 | pci_set_master(efx->pci_dev); | |
2577 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2578 | if (rc) | |
2579 | return rc; | |
2580 | rc = efx->type->init(efx); | |
2581 | if (rc) | |
2582 | return rc; | |
2583 | efx_pm_thaw(dev); | |
2584 | return 0; | |
2585 | } | |
2586 | ||
2587 | static int efx_pm_suspend(struct device *dev) | |
2588 | { | |
2589 | int rc; | |
2590 | ||
2591 | efx_pm_freeze(dev); | |
2592 | rc = efx_pm_poweroff(dev); | |
2593 | if (rc) | |
2594 | efx_pm_resume(dev); | |
2595 | return rc; | |
2596 | } | |
2597 | ||
18e83e4c | 2598 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
2599 | .suspend = efx_pm_suspend, |
2600 | .resume = efx_pm_resume, | |
2601 | .freeze = efx_pm_freeze, | |
2602 | .thaw = efx_pm_thaw, | |
2603 | .poweroff = efx_pm_poweroff, | |
2604 | .restore = efx_pm_resume, | |
2605 | }; | |
2606 | ||
8ceee660 | 2607 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2608 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2609 | .id_table = efx_pci_table, |
2610 | .probe = efx_pci_probe, | |
2611 | .remove = efx_pci_remove, | |
89c758fa | 2612 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2613 | }; |
2614 | ||
2615 | /************************************************************************** | |
2616 | * | |
2617 | * Kernel module interface | |
2618 | * | |
2619 | *************************************************************************/ | |
2620 | ||
2621 | module_param(interrupt_mode, uint, 0444); | |
2622 | MODULE_PARM_DESC(interrupt_mode, | |
2623 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2624 | ||
2625 | static int __init efx_init_module(void) | |
2626 | { | |
2627 | int rc; | |
2628 | ||
2629 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2630 | ||
2631 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2632 | if (rc) | |
2633 | goto err_notifier; | |
2634 | ||
1ab00629 SH |
2635 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2636 | if (!reset_workqueue) { | |
2637 | rc = -ENOMEM; | |
2638 | goto err_reset; | |
2639 | } | |
8ceee660 BH |
2640 | |
2641 | rc = pci_register_driver(&efx_pci_driver); | |
2642 | if (rc < 0) | |
2643 | goto err_pci; | |
2644 | ||
2645 | return 0; | |
2646 | ||
2647 | err_pci: | |
1ab00629 SH |
2648 | destroy_workqueue(reset_workqueue); |
2649 | err_reset: | |
8ceee660 BH |
2650 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2651 | err_notifier: | |
2652 | return rc; | |
2653 | } | |
2654 | ||
2655 | static void __exit efx_exit_module(void) | |
2656 | { | |
2657 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2658 | ||
2659 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2660 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2661 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2662 | ||
2663 | } | |
2664 | ||
2665 | module_init(efx_init_module); | |
2666 | module_exit(efx_exit_module); | |
2667 | ||
906bb26c BH |
2668 | MODULE_AUTHOR("Solarflare Communications and " |
2669 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2670 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2671 | MODULE_LICENSE("GPL"); | |
2672 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |