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sfc: Document current usage of efx_rx_buffer::len and efx_nic::rx_buffer_len
[deliverable/linux.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6 4 * Copyright 2005-2011 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
20#include <linux/crc32.h>
21#include <linux/ethtool.h>
aa6ef27e 22#include <linux/topology.h>
5a0e3ad6 23#include <linux/gfp.h>
626950db 24#include <linux/pci.h>
64d8ad6d 25#include <linux/cpu_rmap.h>
626950db 26#include <linux/aer.h>
8ceee660 27#include "net_driver.h"
8ceee660 28#include "efx.h"
744093c9 29#include "nic.h"
dd40781e 30#include "selftest.h"
8ceee660 31
8880f4ec 32#include "mcdi.h"
fd371e32 33#include "workarounds.h"
8880f4ec 34
c459302d
BH		 35/**************************************************************************
36 *
37 * Type name strings
38 *
39 **************************************************************************
40 */
41
42/* Loopback mode names (see LOOPBACK_MODE()) */
43const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 44const char *const efx_loopback_mode_names[] = {
c459302d 45 [LOOPBACK_NONE] = "NONE",
e58f69f4 46 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 47 [LOOPBACK_GMAC] = "GMAC",
48 [LOOPBACK_XGMII] = "XGMII",
49 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH		 50 [LOOPBACK_XAUI] = "XAUI",
51 [LOOPBACK_GMII] = "GMII",
52 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH		 53 [LOOPBACK_XGBR] = "XGBR",
54 [LOOPBACK_XFI] = "XFI",
55 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
56 [LOOPBACK_GMII_FAR] = "GMII_FAR",
57 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
58 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 59 [LOOPBACK_GPHY] = "GPHY",
60 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH		 61 [LOOPBACK_PCS] = "PCS",
62 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 63 [LOOPBACK_XPORT] = "XPORT",
64 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 65 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH		 66 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
67 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 68 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH		 69 [LOOPBACK_XFI_WS] = "XFI_WS",
70 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 71 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 72};
73
c459302d 74const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 75const char *const efx_reset_type_names[] = {
626950db
AR		 76 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
77 [RESET_TYPE_ALL] = "ALL",
78 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
79 [RESET_TYPE_WORLD] = "WORLD",
80 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
81 [RESET_TYPE_DISABLE] = "DISABLE",
82 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
83 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
84 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
85 [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH",
86 [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH",
87 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
88 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
c459302d
BH		 89};
90
8ceee660
BH		 91#define EFX_MAX_MTU (9 * 1024)
92
1ab00629
SH		 93/* Reset workqueue. If any NIC has a hardware failure then a reset will be
94 * queued onto this work queue. This is not a per-nic work queue, because
95 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
96 */
97static struct workqueue_struct *reset_workqueue;
98
8ceee660
BH		 99/**************************************************************************
100 *
101 * Configurable values
102 *
103 *************************************************************************/
104
8ceee660
BH		 105/*
106 * Use separate channels for TX and RX events
107 *
28b581ab
NT		 108 * Set this to 1 to use separate channels for TX and RX. It allows us
109 * to control interrupt affinity separately for TX and RX.
8ceee660 110 *
28b581ab 111 * This is only used in MSI-X interrupt mode
8ceee660 112 */
b9cc977d
BH		 113static bool separate_tx_channels;
114module_param(separate_tx_channels, bool, 0444);
28b581ab
NT		 115MODULE_PARM_DESC(separate_tx_channels,
116 "Use separate channels for TX and RX");
8ceee660
BH		 117
118/* This is the weight assigned to each of the (per-channel) virtual
119 * NAPI devices.
120 */
121static int napi_weight = 64;
122
123/* This is the time (in jiffies) between invocations of the hardware
626950db
AR		 124 * monitor.
125 * On Falcon-based NICs, this will:
e254c274
BH		 126 * - Check the on-board hardware monitor;
127 * - Poll the link state and reconfigure the hardware as necessary.
626950db
AR		 128 * On Siena-based NICs for power systems with EEH support, this will give EEH a
129 * chance to start.
8ceee660 130 */
d215697f 131static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 132
8ceee660
BH		 133/* Initial interrupt moderation settings. They can be modified after
134 * module load with ethtool.
135 *
136 * The default for RX should strike a balance between increasing the
137 * round-trip latency and reducing overhead.
138 */
139static unsigned int rx_irq_mod_usec = 60;
140
141/* Initial interrupt moderation settings. They can be modified after
142 * module load with ethtool.
143 *
144 * This default is chosen to ensure that a 10G link does not go idle
145 * while a TX queue is stopped after it has become full. A queue is
146 * restarted when it drops below half full. The time this takes (assuming
147 * worst case 3 descriptors per packet and 1024 descriptors) is
148 * 512 / 3 * 1.2 = 205 usec.
149 */
150static unsigned int tx_irq_mod_usec = 150;
151
152/* This is the first interrupt mode to try out of:
153 * 0 => MSI-X
154 * 1 => MSI
155 * 2 => legacy
156 */
157static unsigned int interrupt_mode;
158
159/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
160 * i.e. the number of CPUs among which we may distribute simultaneous
161 * interrupt handling.
162 *
163 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 164 * The default (0) means to assign an interrupt to each core.
8ceee660
BH		 165 */
166static unsigned int rss_cpus;
167module_param(rss_cpus, uint, 0444);
168MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
169
b9cc977d
BH		 170static bool phy_flash_cfg;
171module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH		 172MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
173
e7bed9c8 174static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH		 175module_param(irq_adapt_low_thresh, uint, 0644);
176MODULE_PARM_DESC(irq_adapt_low_thresh,
177 "Threshold score for reducing IRQ moderation");
178
e7bed9c8 179static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH		 180module_param(irq_adapt_high_thresh, uint, 0644);
181MODULE_PARM_DESC(irq_adapt_high_thresh,
182 "Threshold score for increasing IRQ moderation");
183
62776d03
BH		 184static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
185 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
186 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
187 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
188module_param(debug, uint, 0);
189MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
190
8ceee660
BH		 191/**************************************************************************
192 *
193 * Utility functions and prototypes
194 *
195 *************************************************************************/
4642610c 196
7f967c01
BH		 197static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq);
198static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq);
199static void efx_remove_channel(struct efx_channel *channel);
4642610c 200static void efx_remove_channels(struct efx_nic *efx);
7f967c01 201static const struct efx_channel_type efx_default_channel_type;
8ceee660 202static void efx_remove_port(struct efx_nic *efx);
7f967c01 203static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 204static void efx_fini_napi(struct efx_nic *efx);
e8f14992 205static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH		 206static void efx_fini_struct(struct efx_nic *efx);
207static void efx_start_all(struct efx_nic *efx);
208static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH		 209
210#define EFX_ASSERT_RESET_SERIALISED(efx) \
211 do { \
f16aeea0 212 if ((efx->state == STATE_READY) || \
626950db 213 (efx->state == STATE_RECOVERY) || \
332c1ce9 214 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 215 ASSERT_RTNL(); \
216 } while (0)
217
8b7325b4
BH		 218static int efx_check_disabled(struct efx_nic *efx)
219{
626950db 220 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
8b7325b4
BH		 221 netif_err(efx, drv, efx->net_dev,
222 "device is disabled due to earlier errors\n");
223 return -EIO;
224 }
225 return 0;
226}
227
8ceee660
BH		 228/**************************************************************************
229 *
230 * Event queue processing
231 *
232 *************************************************************************/
233
234/* Process channel's event queue
235 *
236 * This function is responsible for processing the event queue of a
237 * single channel. The caller must guarantee that this function will
238 * never be concurrently called more than once on the same channel,
239 * though different channels may be being processed concurrently.
240 */
fa236e18 241static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 242{
fa236e18 243 int spent;
8ceee660 244
9f2cb71c 245 if (unlikely(!channel->enabled))
42cbe2d7 246 return 0;
8ceee660 247
fa236e18 248 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH		 249 if (spent && efx_channel_has_rx_queue(channel)) {
250 struct efx_rx_queue *rx_queue =
251 efx_channel_get_rx_queue(channel);
252
253 /* Deliver last RX packet. */
254 if (channel->rx_pkt) {
255 __efx_rx_packet(channel, channel->rx_pkt);
256 channel->rx_pkt = NULL;
257 }
97d48a10 258 if (rx_queue->enabled)
9f2cb71c 259 efx_fast_push_rx_descriptors(rx_queue);
8ceee660
BH		 260 }
261
fa236e18 262 return spent;
8ceee660
BH		 263}
264
265/* Mark channel as finished processing
266 *
267 * Note that since we will not receive further interrupts for this
268 * channel before we finish processing and call the eventq_read_ack()
269 * method, there is no need to use the interrupt hold-off timers.
270 */
271static inline void efx_channel_processed(struct efx_channel *channel)
272{
5b9e207c
BH		 273 /* The interrupt handler for this channel may set work_pending
274 * as soon as we acknowledge the events we've seen. Make sure
275 * it's cleared before then. */
dc8cfa55 276 channel->work_pending = false;
5b9e207c
BH		 277 smp_wmb();
278
152b6a62 279 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 280}
281
282/* NAPI poll handler
283 *
284 * NAPI guarantees serialisation of polls of the same device, which
285 * provides the guarantee required by efx_process_channel().
286 */
287static int efx_poll(struct napi_struct *napi, int budget)
288{
289 struct efx_channel *channel =
290 container_of(napi, struct efx_channel, napi_str);
62776d03 291 struct efx_nic *efx = channel->efx;
fa236e18 292 int spent;
8ceee660 293
62776d03
BH		 294 netif_vdbg(efx, intr, efx->net_dev,
295 "channel %d NAPI poll executing on CPU %d\n",
296 channel->channel, raw_smp_processor_id());
8ceee660 297
fa236e18 298 spent = efx_process_channel(channel, budget);
8ceee660 299
fa236e18 300 if (spent < budget) {
9d9a6973 301 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH		 302 efx->irq_rx_adaptive &&
303 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH		 304 if (unlikely(channel->irq_mod_score <
305 irq_adapt_low_thresh)) {
0d86ebd8
BH		 306 if (channel->irq_moderation > 1) {
307 channel->irq_moderation -= 1;
ef2b90ee 308 efx->type->push_irq_moderation(channel);
0d86ebd8 309 }
6fb70fd1
BH		 310 } else if (unlikely(channel->irq_mod_score >
311 irq_adapt_high_thresh)) {
0d86ebd8
BH		 312 if (channel->irq_moderation <
313 efx->irq_rx_moderation) {
314 channel->irq_moderation += 1;
ef2b90ee 315 efx->type->push_irq_moderation(channel);
0d86ebd8 316 }
6fb70fd1 317 }
6fb70fd1
BH		 318 channel->irq_count = 0;
319 channel->irq_mod_score = 0;
320 }
321
64d8ad6d
BH		 322 efx_filter_rfs_expire(channel);
323
8ceee660 324 /* There is no race here; although napi_disable() will
288379f0 325 * only wait for napi_complete(), this isn't a problem
8ceee660
BH		 326 * since efx_channel_processed() will have no effect if
327 * interrupts have already been disabled.
328 */
288379f0 329 napi_complete(napi);
8ceee660
BH		 330 efx_channel_processed(channel);
331 }
332
fa236e18 333 return spent;
8ceee660
BH		 334}
335
336/* Process the eventq of the specified channel immediately on this CPU
337 *
338 * Disable hardware generated interrupts, wait for any existing
339 * processing to finish, then directly poll (and ack ) the eventq.
340 * Finally reenable NAPI and interrupts.
341 *
d4fabcc8
BH		 342 * This is for use only during a loopback self-test. It must not
343 * deliver any packets up the stack as this can result in deadlock.
8ceee660
BH		 344 */
345void efx_process_channel_now(struct efx_channel *channel)
346{
347 struct efx_nic *efx = channel->efx;
348
8313aca3 349 BUG_ON(channel->channel >= efx->n_channels);
8ceee660 350 BUG_ON(!channel->enabled);
d4fabcc8 351 BUG_ON(!efx->loopback_selftest);
8ceee660
BH		 352
353 /* Disable interrupts and wait for ISRs to complete */
152b6a62 354 efx_nic_disable_interrupts(efx);
94dec6a2 355 if (efx->legacy_irq) {
8ceee660 356 synchronize_irq(efx->legacy_irq);
94dec6a2
BH		 357 efx->legacy_irq_enabled = false;
358 }
64ee3120 359 if (channel->irq)
8ceee660
BH		 360 synchronize_irq(channel->irq);
361
362 /* Wait for any NAPI processing to complete */
363 napi_disable(&channel->napi_str);
364
365 /* Poll the channel */
ecc910f5 366 efx_process_channel(channel, channel->eventq_mask + 1);
8ceee660
BH		 367
368 /* Ack the eventq. This may cause an interrupt to be generated
369 * when they are reenabled */
370 efx_channel_processed(channel);
371
372 napi_enable(&channel->napi_str);
94dec6a2
BH		 373 if (efx->legacy_irq)
374 efx->legacy_irq_enabled = true;
152b6a62 375 efx_nic_enable_interrupts(efx);
8ceee660
BH		 376}
377
378/* Create event queue
379 * Event queue memory allocations are done only once. If the channel
380 * is reset, the memory buffer will be reused; this guards against
381 * errors during channel reset and also simplifies interrupt handling.
382 */
383static int efx_probe_eventq(struct efx_channel *channel)
384{
ecc910f5
SH		 385 struct efx_nic *efx = channel->efx;
386 unsigned long entries;
387
86ee5302 388 netif_dbg(efx, probe, efx->net_dev,
62776d03 389 "chan %d create event queue\n", channel->channel);
8ceee660 390
ecc910f5
SH		 391 /* Build an event queue with room for one event per tx and rx buffer,
392 * plus some extra for link state events and MCDI completions. */
393 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
394 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
395 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
396
152b6a62 397 return efx_nic_probe_eventq(channel);
8ceee660
BH		 398}
399
400/* Prepare channel's event queue */
bc3c90a2 401static void efx_init_eventq(struct efx_channel *channel)
8ceee660 402{
62776d03
BH		 403 netif_dbg(channel->efx, drv, channel->efx->net_dev,
404 "chan %d init event queue\n", channel->channel);
8ceee660
BH		 405
406 channel->eventq_read_ptr = 0;
407
152b6a62 408 efx_nic_init_eventq(channel);
8ceee660
BH		 409}
410
9f2cb71c
BH		 411/* Enable event queue processing and NAPI */
412static void efx_start_eventq(struct efx_channel *channel)
413{
414 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
415 "chan %d start event queue\n", channel->channel);
416
417 /* The interrupt handler for this channel may set work_pending
418 * as soon as we enable it. Make sure it's cleared before
419 * then. Similarly, make sure it sees the enabled flag set.
420 */
421 channel->work_pending = false;
422 channel->enabled = true;
423 smp_wmb();
424
425 napi_enable(&channel->napi_str);
426 efx_nic_eventq_read_ack(channel);
427}
428
429/* Disable event queue processing and NAPI */
430static void efx_stop_eventq(struct efx_channel *channel)
431{
432 if (!channel->enabled)
433 return;
434
435 napi_disable(&channel->napi_str);
436 channel->enabled = false;
437}
438
8ceee660
BH		 439static void efx_fini_eventq(struct efx_channel *channel)
440{
62776d03
BH		 441 netif_dbg(channel->efx, drv, channel->efx->net_dev,
442 "chan %d fini event queue\n", channel->channel);
8ceee660 443
152b6a62 444 efx_nic_fini_eventq(channel);
8ceee660
BH		 445}
446
447static void efx_remove_eventq(struct efx_channel *channel)
448{
62776d03
BH		 449 netif_dbg(channel->efx, drv, channel->efx->net_dev,
450 "chan %d remove event queue\n", channel->channel);
8ceee660 451
152b6a62 452 efx_nic_remove_eventq(channel);
8ceee660
BH		 453}
454
455/**************************************************************************
456 *
457 * Channel handling
458 *
459 *************************************************************************/
460
7f967c01 461/* Allocate and initialise a channel structure. */
4642610c
BH		 462static struct efx_channel *
463efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
464{
465 struct efx_channel *channel;
466 struct efx_rx_queue *rx_queue;
467 struct efx_tx_queue *tx_queue;
468 int j;
469
7f967c01
BH		 470 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
471 if (!channel)
472 return NULL;
4642610c 473
7f967c01
BH		 474 channel->efx = efx;
475 channel->channel = i;
476 channel->type = &efx_default_channel_type;
4642610c 477
7f967c01
BH		 478 for (j = 0; j < EFX_TXQ_TYPES; j++) {
479 tx_queue = &channel->tx_queue[j];
480 tx_queue->efx = efx;
481 tx_queue->queue = i * EFX_TXQ_TYPES + j;
482 tx_queue->channel = channel;
483 }
4642610c 484
7f967c01
BH		 485 rx_queue = &channel->rx_queue;
486 rx_queue->efx = efx;
487 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
488 (unsigned long)rx_queue);
4642610c 489
7f967c01
BH		 490 return channel;
491}
492
493/* Allocate and initialise a channel structure, copying parameters
494 * (but not resources) from an old channel structure.
495 */
496static struct efx_channel *
497efx_copy_channel(const struct efx_channel *old_channel)
498{
499 struct efx_channel *channel;
500 struct efx_rx_queue *rx_queue;
501 struct efx_tx_queue *tx_queue;
502 int j;
4642610c 503
7f967c01
BH		 504 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
505 if (!channel)
506 return NULL;
507
508 *channel = *old_channel;
509
510 channel->napi_dev = NULL;
511 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 512
7f967c01
BH		 513 for (j = 0; j < EFX_TXQ_TYPES; j++) {
514 tx_queue = &channel->tx_queue[j];
515 if (tx_queue->channel)
4642610c 516 tx_queue->channel = channel;
7f967c01
BH		 517 tx_queue->buffer = NULL;
518 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH		 519 }
520
4642610c 521 rx_queue = &channel->rx_queue;
7f967c01
BH		 522 rx_queue->buffer = NULL;
523 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH		 524 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
525 (unsigned long)rx_queue);
526
527 return channel;
528}
529
8ceee660
BH		 530static int efx_probe_channel(struct efx_channel *channel)
531{
532 struct efx_tx_queue *tx_queue;
533 struct efx_rx_queue *rx_queue;
534 int rc;
535
62776d03
BH		 536 netif_dbg(channel->efx, probe, channel->efx->net_dev,
537 "creating channel %d\n", channel->channel);
8ceee660 538
7f967c01
BH		 539 rc = channel->type->pre_probe(channel);
540 if (rc)
541 goto fail;
542
8ceee660
BH		 543 rc = efx_probe_eventq(channel);
544 if (rc)
7f967c01 545 goto fail;
8ceee660
BH		 546
547 efx_for_each_channel_tx_queue(tx_queue, channel) {
548 rc = efx_probe_tx_queue(tx_queue);
549 if (rc)
7f967c01 550 goto fail;
8ceee660
BH		 551 }
552
553 efx_for_each_channel_rx_queue(rx_queue, channel) {
554 rc = efx_probe_rx_queue(rx_queue);
555 if (rc)
7f967c01 556 goto fail;
8ceee660
BH		 557 }
558
559 channel->n_rx_frm_trunc = 0;
560
561 return 0;
562
7f967c01
BH		 563fail:
564 efx_remove_channel(channel);
8ceee660
BH		 565 return rc;
566}
567
7f967c01
BH		 568static void
569efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
570{
571 struct efx_nic *efx = channel->efx;
572 const char *type;
573 int number;
574
575 number = channel->channel;
576 if (efx->tx_channel_offset == 0) {
577 type = "";
578 } else if (channel->channel < efx->tx_channel_offset) {
579 type = "-rx";
580 } else {
581 type = "-tx";
582 number -= efx->tx_channel_offset;
583 }
584 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
585}
8ceee660 586
56536e9c
BH		 587static void efx_set_channel_names(struct efx_nic *efx)
588{
589 struct efx_channel *channel;
56536e9c 590
7f967c01
BH		 591 efx_for_each_channel(channel, efx)
592 channel->type->get_name(channel,
593 efx->channel_name[channel->channel],
594 sizeof(efx->channel_name[0]));
56536e9c
BH		 595}
596
4642610c
BH		 597static int efx_probe_channels(struct efx_nic *efx)
598{
599 struct efx_channel *channel;
600 int rc;
601
602 /* Restart special buffer allocation */
603 efx->next_buffer_table = 0;
604
c92aaff1
BH		 605 /* Probe channels in reverse, so that any 'extra' channels
606 * use the start of the buffer table. This allows the traffic
607 * channels to be resized without moving them or wasting the
608 * entries before them.
609 */
610 efx_for_each_channel_rev(channel, efx) {
4642610c
BH		 611 rc = efx_probe_channel(channel);
612 if (rc) {
613 netif_err(efx, probe, efx->net_dev,
614 "failed to create channel %d\n",
615 channel->channel);
616 goto fail;
617 }
618 }
619 efx_set_channel_names(efx);
620
621 return 0;
622
623fail:
624 efx_remove_channels(efx);
625 return rc;
626}
627
8ceee660
BH		 628/* Channels are shutdown and reinitialised whilst the NIC is running
629 * to propagate configuration changes (mtu, checksum offload), or
630 * to clear hardware error conditions
631 */
9f2cb71c 632static void efx_start_datapath(struct efx_nic *efx)
8ceee660
BH		 633{
634 struct efx_tx_queue *tx_queue;
635 struct efx_rx_queue *rx_queue;
636 struct efx_channel *channel;
8ceee660 637
f7f13b0b
BH		 638 /* Calculate the rx buffer allocation parameters required to
639 * support the current MTU, including padding for header
640 * alignment and overruns.
641 */
642 efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
643 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
39c9cf07 644 efx->type->rx_buffer_hash_size +
f7f13b0b 645 efx->type->rx_buffer_padding);
62b330ba
SH		 646 efx->rx_buffer_order = get_order(efx->rx_buffer_len +
647 sizeof(struct efx_rx_page_state));
8ceee660 648
14bf718f
BH		 649 /* We must keep at least one descriptor in a TX ring empty.
650 * We could avoid this when the queue size does not exactly
651 * match the hardware ring size, but it's not that important.
652 * Therefore we stop the queue when one more skb might fill
653 * the ring completely. We wake it when half way back to
654 * empty.
655 */
656 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
657 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
658
8ceee660
BH		 659 /* Initialise the channels */
660 efx_for_each_channel(channel, efx) {
bc3c90a2
BH		 661 efx_for_each_channel_tx_queue(tx_queue, channel)
662 efx_init_tx_queue(tx_queue);
8ceee660 663
9f2cb71c 664 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 665 efx_init_rx_queue(rx_queue);
9f2cb71c
BH		 666 efx_nic_generate_fill_event(rx_queue);
667 }
8ceee660
BH		 668
669 WARN_ON(channel->rx_pkt != NULL);
8ceee660 670 }
8ceee660 671
9f2cb71c
BH		 672 if (netif_device_present(efx->net_dev))
673 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH		 674}
675
9f2cb71c 676static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH		 677{
678 struct efx_channel *channel;
679 struct efx_tx_queue *tx_queue;
680 struct efx_rx_queue *rx_queue;
3dca9d2d 681 struct pci_dev *dev = efx->pci_dev;
6bc5d3a9 682 int rc;
8ceee660
BH		 683
684 EFX_ASSERT_RESET_SERIALISED(efx);
685 BUG_ON(efx->port_enabled);
686
3dca9d2d 687 /* Only perform flush if dma is enabled */
626950db 688 if (dev->is_busmaster && efx->state != STATE_RECOVERY) {
3dca9d2d
SH		 689 rc = efx_nic_flush_queues(efx);
690
691 if (rc && EFX_WORKAROUND_7803(efx)) {
692 /* Schedule a reset to recover from the flush failure. The
693 * descriptor caches reference memory we're about to free,
694 * but falcon_reconfigure_mac_wrapper() won't reconnect
695 * the MACs because of the pending reset. */
696 netif_err(efx, drv, efx->net_dev,
697 "Resetting to recover from flush failure\n");
698 efx_schedule_reset(efx, RESET_TYPE_ALL);
699 } else if (rc) {
700 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
701 } else {
702 netif_dbg(efx, drv, efx->net_dev,
703 "successfully flushed all queues\n");
704 }
fd371e32 705 }
6bc5d3a9 706
8ceee660 707 efx_for_each_channel(channel, efx) {
9f2cb71c
BH		 708 /* RX packet processing is pipelined, so wait for the
709 * NAPI handler to complete. At least event queue 0
710 * might be kept active by non-data events, so don't
711 * use napi_synchronize() but actually disable NAPI
712 * temporarily.
713 */
714 if (efx_channel_has_rx_queue(channel)) {
715 efx_stop_eventq(channel);
716 efx_start_eventq(channel);
717 }
8ceee660
BH		 718
719 efx_for_each_channel_rx_queue(rx_queue, channel)
720 efx_fini_rx_queue(rx_queue);
94b274bf 721 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 722 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 723 }
724}
725
726static void efx_remove_channel(struct efx_channel *channel)
727{
728 struct efx_tx_queue *tx_queue;
729 struct efx_rx_queue *rx_queue;
730
62776d03
BH		 731 netif_dbg(channel->efx, drv, channel->efx->net_dev,
732 "destroy chan %d\n", channel->channel);
8ceee660
BH		 733
734 efx_for_each_channel_rx_queue(rx_queue, channel)
735 efx_remove_rx_queue(rx_queue);
94b274bf 736 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH		 737 efx_remove_tx_queue(tx_queue);
738 efx_remove_eventq(channel);
c31e5f9f 739 channel->type->post_remove(channel);
8ceee660
BH		 740}
741
4642610c
BH		 742static void efx_remove_channels(struct efx_nic *efx)
743{
744 struct efx_channel *channel;
745
746 efx_for_each_channel(channel, efx)
747 efx_remove_channel(channel);
748}
749
750int
751efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
752{
753 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
754 u32 old_rxq_entries, old_txq_entries;
7f967c01 755 unsigned i, next_buffer_table = 0;
8b7325b4
BH		 756 int rc;
757
758 rc = efx_check_disabled(efx);
759 if (rc)
760 return rc;
7f967c01
BH		 761
762 /* Not all channels should be reallocated. We must avoid
763 * reallocating their buffer table entries.
764 */
765 efx_for_each_channel(channel, efx) {
766 struct efx_rx_queue *rx_queue;
767 struct efx_tx_queue *tx_queue;
768
769 if (channel->type->copy)
770 continue;
771 next_buffer_table = max(next_buffer_table,
772 channel->eventq.index +
773 channel->eventq.entries);
774 efx_for_each_channel_rx_queue(rx_queue, channel)
775 next_buffer_table = max(next_buffer_table,
776 rx_queue->rxd.index +
777 rx_queue->rxd.entries);
778 efx_for_each_channel_tx_queue(tx_queue, channel)
779 next_buffer_table = max(next_buffer_table,
780 tx_queue->txd.index +
781 tx_queue->txd.entries);
782 }
4642610c 783
29c69a48 784 efx_device_detach_sync(efx);
4642610c 785 efx_stop_all(efx);
7f967c01 786 efx_stop_interrupts(efx, true);
4642610c 787
7f967c01 788 /* Clone channels (where possible) */
4642610c
BH		 789 memset(other_channel, 0, sizeof(other_channel));
790 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 791 channel = efx->channel[i];
792 if (channel->type->copy)
793 channel = channel->type->copy(channel);
4642610c
BH		 794 if (!channel) {
795 rc = -ENOMEM;
796 goto out;
797 }
798 other_channel[i] = channel;
799 }
800
801 /* Swap entry counts and channel pointers */
802 old_rxq_entries = efx->rxq_entries;
803 old_txq_entries = efx->txq_entries;
804 efx->rxq_entries = rxq_entries;
805 efx->txq_entries = txq_entries;
806 for (i = 0; i < efx->n_channels; i++) {
807 channel = efx->channel[i];
808 efx->channel[i] = other_channel[i];
809 other_channel[i] = channel;
810 }
811
7f967c01
BH		 812 /* Restart buffer table allocation */
813 efx->next_buffer_table = next_buffer_table;
e8f14992 814
e8f14992 815 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 816 channel = efx->channel[i];
817 if (!channel->type->copy)
818 continue;
819 rc = efx_probe_channel(channel);
820 if (rc)
821 goto rollback;
822 efx_init_napi_channel(efx->channel[i]);
e8f14992 823 }
7f967c01 824
4642610c 825out:
7f967c01
BH		 826 /* Destroy unused channel structures */
827 for (i = 0; i < efx->n_channels; i++) {
828 channel = other_channel[i];
829 if (channel && channel->type->copy) {
830 efx_fini_napi_channel(channel);
831 efx_remove_channel(channel);
832 kfree(channel);
833 }
834 }
4642610c 835
7f967c01 836 efx_start_interrupts(efx, true);
4642610c 837 efx_start_all(efx);
29c69a48 838 netif_device_attach(efx->net_dev);
4642610c
BH		 839 return rc;
840
841rollback:
842 /* Swap back */
843 efx->rxq_entries = old_rxq_entries;
844 efx->txq_entries = old_txq_entries;
845 for (i = 0; i < efx->n_channels; i++) {
846 channel = efx->channel[i];
847 efx->channel[i] = other_channel[i];
848 other_channel[i] = channel;
849 }
850 goto out;
851}
852
90d683af 853void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 854{
90d683af 855 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH		 856}
857
7f967c01
BH		 858static const struct efx_channel_type efx_default_channel_type = {
859 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 860 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH		 861 .get_name = efx_get_channel_name,
862 .copy = efx_copy_channel,
863 .keep_eventq = false,
864};
865
866int efx_channel_dummy_op_int(struct efx_channel *channel)
867{
868 return 0;
869}
870
c31e5f9f
SH		 871void efx_channel_dummy_op_void(struct efx_channel *channel)
872{
873}
874
8ceee660
BH		 875/**************************************************************************
876 *
877 * Port handling
878 *
879 **************************************************************************/
880
881/* This ensures that the kernel is kept informed (via
882 * netif_carrier_on/off) of the link status, and also maintains the
883 * link status's stop on the port's TX queue.
884 */
fdaa9aed 885void efx_link_status_changed(struct efx_nic *efx)
8ceee660 886{
eb50c0d6
BH		 887 struct efx_link_state *link_state = &efx->link_state;
888
8ceee660
BH		 889 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
890 * that no events are triggered between unregister_netdev() and the
891 * driver unloading. A more general condition is that NETDEV_CHANGE
892 * can only be generated between NETDEV_UP and NETDEV_DOWN */
893 if (!netif_running(efx->net_dev))
894 return;
895
eb50c0d6 896 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 897 efx->n_link_state_changes++;
898
eb50c0d6 899 if (link_state->up)
8ceee660
BH		 900 netif_carrier_on(efx->net_dev);
901 else
902 netif_carrier_off(efx->net_dev);
903 }
904
905 /* Status message for kernel log */
2aa9ef11 906 if (link_state->up)
62776d03
BH		 907 netif_info(efx, link, efx->net_dev,
908 "link up at %uMbps %s-duplex (MTU %d)%s\n",
909 link_state->speed, link_state->fd ? "full" : "half",
910 efx->net_dev->mtu,
911 (efx->promiscuous ? " [PROMISC]" : ""));
2aa9ef11 912 else
62776d03 913 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH		 914}
915
d3245b28
BH		 916void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
917{
918 efx->link_advertising = advertising;
919 if (advertising) {
920 if (advertising & ADVERTISED_Pause)
921 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
922 else
923 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
924 if (advertising & ADVERTISED_Asym_Pause)
925 efx->wanted_fc ^= EFX_FC_TX;
926 }
927}
928
b5626946 929void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH		 930{
931 efx->wanted_fc = wanted_fc;
932 if (efx->link_advertising) {
933 if (wanted_fc & EFX_FC_RX)
934 efx->link_advertising |= (ADVERTISED_Pause |
935 ADVERTISED_Asym_Pause);
936 else
937 efx->link_advertising &= ~(ADVERTISED_Pause |
938 ADVERTISED_Asym_Pause);
939 if (wanted_fc & EFX_FC_TX)
940 efx->link_advertising ^= ADVERTISED_Asym_Pause;
941 }
942}
943
115122af
BH		 944static void efx_fini_port(struct efx_nic *efx);
945
d3245b28
BH		 946/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
947 * the MAC appropriately. All other PHY configuration changes are pushed
948 * through phy_op->set_settings(), and pushed asynchronously to the MAC
949 * through efx_monitor().
950 *
951 * Callers must hold the mac_lock
952 */
953int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 954{
d3245b28
BH		 955 enum efx_phy_mode phy_mode;
956 int rc;
8ceee660 957
d3245b28 958 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 959
0fca8c97 960 /* Serialise the promiscuous flag with efx_set_rx_mode. */
73ba7b68
BH		 961 netif_addr_lock_bh(efx->net_dev);
962 netif_addr_unlock_bh(efx->net_dev);
a816f75a 963
d3245b28
BH		 964 /* Disable PHY transmit in mac level loopbacks */
965 phy_mode = efx->phy_mode;
177dfcd8
BH		 966 if (LOOPBACK_INTERNAL(efx))
967 efx->phy_mode |= PHY_MODE_TX_DISABLED;
968 else
969 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 970
d3245b28 971 rc = efx->type->reconfigure_port(efx);
8ceee660 972
d3245b28
BH		 973 if (rc)
974 efx->phy_mode = phy_mode;
177dfcd8 975
d3245b28 976 return rc;
8ceee660
BH		 977}
978
979/* Reinitialise the MAC to pick up new PHY settings, even if the port is
980 * disabled. */
d3245b28 981int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 982{
d3245b28
BH		 983 int rc;
984
8ceee660
BH		 985 EFX_ASSERT_RESET_SERIALISED(efx);
986
987 mutex_lock(&efx->mac_lock);
d3245b28 988 rc = __efx_reconfigure_port(efx);
8ceee660 989 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 990
991 return rc;
8ceee660
BH		 992}
993
8be4f3e6
BH		 994/* Asynchronous work item for changing MAC promiscuity and multicast
995 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
996 * MAC directly. */
766ca0fa
BH		 997static void efx_mac_work(struct work_struct *data)
998{
999 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
1000
1001 mutex_lock(&efx->mac_lock);
30b81cda 1002 if (efx->port_enabled)
710b208d 1003 efx->type->reconfigure_mac(efx);
766ca0fa
BH		 1004 mutex_unlock(&efx->mac_lock);
1005}
1006
8ceee660
BH		 1007static int efx_probe_port(struct efx_nic *efx)
1008{
1009 int rc;
1010
62776d03 1011 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 1012
ff3b00a0
SH		 1013 if (phy_flash_cfg)
1014 efx->phy_mode = PHY_MODE_SPECIAL;
1015
ef2b90ee
BH		 1016 /* Connect up MAC/PHY operations table */
1017 rc = efx->type->probe_port(efx);
8ceee660 1018 if (rc)
e42de262 1019 return rc;
8ceee660 1020
e332bcb3
BH		 1021 /* Initialise MAC address to permanent address */
1022 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN);
8ceee660
BH		 1023
1024 return 0;
8ceee660
BH		 1025}
1026
1027static int efx_init_port(struct efx_nic *efx)
1028{
1029 int rc;
1030
62776d03 1031 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 1032
1dfc5cea
BH		 1033 mutex_lock(&efx->mac_lock);
1034
177dfcd8 1035 rc = efx->phy_op->init(efx);
8ceee660 1036 if (rc)
1dfc5cea 1037 goto fail1;
8ceee660 1038
dc8cfa55 1039 efx->port_initialized = true;
1dfc5cea 1040
d3245b28
BH		 1041 /* Reconfigure the MAC before creating dma queues (required for
1042 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
710b208d 1043 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1044
1045 /* Ensure the PHY advertises the correct flow control settings */
1046 rc = efx->phy_op->reconfigure(efx);
1047 if (rc)
1048 goto fail2;
1049
1dfc5cea 1050 mutex_unlock(&efx->mac_lock);
8ceee660 1051 return 0;
177dfcd8 1052
1dfc5cea 1053fail2:
177dfcd8 1054 efx->phy_op->fini(efx);
1dfc5cea
BH		 1055fail1:
1056 mutex_unlock(&efx->mac_lock);
177dfcd8 1057 return rc;
8ceee660
BH		 1058}
1059
8ceee660
BH		 1060static void efx_start_port(struct efx_nic *efx)
1061{
62776d03 1062 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH		 1063 BUG_ON(efx->port_enabled);
1064
1065 mutex_lock(&efx->mac_lock);
dc8cfa55 1066 efx->port_enabled = true;
8be4f3e6
BH		 1067
1068 /* efx_mac_work() might have been scheduled after efx_stop_port(),
1069 * and then cancelled by efx_flush_all() */
710b208d 1070 efx->type->reconfigure_mac(efx);
8be4f3e6 1071
8ceee660
BH		 1072 mutex_unlock(&efx->mac_lock);
1073}
1074
fdaa9aed 1075/* Prevent efx_mac_work() and efx_monitor() from working */
8ceee660
BH		 1076static void efx_stop_port(struct efx_nic *efx)
1077{
62776d03 1078 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660
BH		 1079
1080 mutex_lock(&efx->mac_lock);
dc8cfa55 1081 efx->port_enabled = false;
8ceee660
BH		 1082 mutex_unlock(&efx->mac_lock);
1083
1084 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH		 1085 netif_addr_lock_bh(efx->net_dev);
1086 netif_addr_unlock_bh(efx->net_dev);
8ceee660
BH		 1087}
1088
1089static void efx_fini_port(struct efx_nic *efx)
1090{
62776d03 1091 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH		 1092
1093 if (!efx->port_initialized)
1094 return;
1095
177dfcd8 1096 efx->phy_op->fini(efx);
dc8cfa55 1097 efx->port_initialized = false;
8ceee660 1098
eb50c0d6 1099 efx->link_state.up = false;
8ceee660
BH		 1100 efx_link_status_changed(efx);
1101}
1102
1103static void efx_remove_port(struct efx_nic *efx)
1104{
62776d03 1105 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1106
ef2b90ee 1107 efx->type->remove_port(efx);
8ceee660
BH		 1108}
1109
1110/**************************************************************************
1111 *
1112 * NIC handling
1113 *
1114 **************************************************************************/
1115
1116/* This configures the PCI device to enable I/O and DMA. */
1117static int efx_init_io(struct efx_nic *efx)
1118{
1119 struct pci_dev *pci_dev = efx->pci_dev;
1120 dma_addr_t dma_mask = efx->type->max_dma_mask;
1121 int rc;
1122
62776d03 1123 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660
BH		 1124
1125 rc = pci_enable_device(pci_dev);
1126 if (rc) {
62776d03
BH		 1127 netif_err(efx, probe, efx->net_dev,
1128 "failed to enable PCI device\n");
8ceee660
BH		 1129 goto fail1;
1130 }
1131
1132 pci_set_master(pci_dev);
1133
1134 /* Set the PCI DMA mask. Try all possibilities from our
1135 * genuine mask down to 32 bits, because some architectures
1136 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1137 * masks event though they reject 46 bit masks.
1138 */
1139 while (dma_mask > 0x7fffffffUL) {
0e33d870
BH		 1140 if (dma_supported(&pci_dev->dev, dma_mask)) {
1141 rc = dma_set_mask(&pci_dev->dev, dma_mask);
e9e01846
BH		 1142 if (rc == 0)
1143 break;
1144 }
8ceee660
BH		 1145 dma_mask >>= 1;
1146 }
1147 if (rc) {
62776d03
BH		 1148 netif_err(efx, probe, efx->net_dev,
1149 "could not find a suitable DMA mask\n");
8ceee660
BH		 1150 goto fail2;
1151 }
62776d03
BH		 1152 netif_dbg(efx, probe, efx->net_dev,
1153 "using DMA mask %llx\n", (unsigned long long) dma_mask);
0e33d870 1154 rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask);
8ceee660 1155 if (rc) {
0e33d870
BH		 1156 /* dma_set_coherent_mask() is not *allowed* to
1157 * fail with a mask that dma_set_mask() accepted,
8ceee660
BH		 1158 * but just in case...
1159 */
62776d03
BH		 1160 netif_err(efx, probe, efx->net_dev,
1161 "failed to set consistent DMA mask\n");
8ceee660
BH		 1162 goto fail2;
1163 }
1164
dc803df8
BH		 1165 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1166 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
8ceee660 1167 if (rc) {
62776d03
BH		 1168 netif_err(efx, probe, efx->net_dev,
1169 "request for memory BAR failed\n");
8ceee660
BH		 1170 rc = -EIO;
1171 goto fail3;
1172 }
86c432ca
BH		 1173 efx->membase = ioremap_nocache(efx->membase_phys,
1174 efx->type->mem_map_size);
8ceee660 1175 if (!efx->membase) {
62776d03
BH		 1176 netif_err(efx, probe, efx->net_dev,
1177 "could not map memory BAR at %llx+%x\n",
1178 (unsigned long long)efx->membase_phys,
1179 efx->type->mem_map_size);
8ceee660
BH		 1180 rc = -ENOMEM;
1181 goto fail4;
1182 }
62776d03
BH		 1183 netif_dbg(efx, probe, efx->net_dev,
1184 "memory BAR at %llx+%x (virtual %p)\n",
1185 (unsigned long long)efx->membase_phys,
1186 efx->type->mem_map_size, efx->membase);
8ceee660
BH		 1187
1188 return 0;
1189
1190 fail4:
dc803df8 1191 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
8ceee660 1192 fail3:
2c118e0f 1193 efx->membase_phys = 0;
8ceee660
BH		 1194 fail2:
1195 pci_disable_device(efx->pci_dev);
1196 fail1:
1197 return rc;
1198}
1199
1200static void efx_fini_io(struct efx_nic *efx)
1201{
62776d03 1202 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH		 1203
1204 if (efx->membase) {
1205 iounmap(efx->membase);
1206 efx->membase = NULL;
1207 }
1208
1209 if (efx->membase_phys) {
dc803df8 1210 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
2c118e0f 1211 efx->membase_phys = 0;
8ceee660
BH		 1212 }
1213
1214 pci_disable_device(efx->pci_dev);
1215}
1216
a9a52506 1217static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1218{
cdb08f8f 1219 cpumask_var_t thread_mask;
a16e5b24 1220 unsigned int count;
46123d04 1221 int cpu;
5b874e25 1222
cd2d5b52
BH		 1223 if (rss_cpus) {
1224 count = rss_cpus;
1225 } else {
1226 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1227 netif_warn(efx, probe, efx->net_dev,
1228 "RSS disabled due to allocation failure\n");
1229 return 1;
1230 }
46123d04 1231
cd2d5b52
BH		 1232 count = 0;
1233 for_each_online_cpu(cpu) {
1234 if (!cpumask_test_cpu(cpu, thread_mask)) {
1235 ++count;
1236 cpumask_or(thread_mask, thread_mask,
1237 topology_thread_cpumask(cpu));
1238 }
1239 }
1240
1241 free_cpumask_var(thread_mask);
2f8975fb
RR		 1242 }
1243
cd2d5b52
BH		 1244 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1245 * table entries that are inaccessible to VFs
1246 */
1247 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1248 count > efx_vf_size(efx)) {
1249 netif_warn(efx, probe, efx->net_dev,
1250 "Reducing number of RSS channels from %u to %u for "
1251 "VF support. Increase vf-msix-limit to use more "
1252 "channels on the PF.\n",
1253 count, efx_vf_size(efx));
1254 count = efx_vf_size(efx);
46123d04
BH		 1255 }
1256
1257 return count;
1258}
1259
64d8ad6d
BH		 1260static int
1261efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries)
1262{
1263#ifdef CONFIG_RFS_ACCEL
a16e5b24
BH		 1264 unsigned int i;
1265 int rc;
64d8ad6d
BH		 1266
1267 efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels);
1268 if (!efx->net_dev->rx_cpu_rmap)
1269 return -ENOMEM;
1270 for (i = 0; i < efx->n_rx_channels; i++) {
1271 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
1272 xentries[i].vector);
1273 if (rc) {
1274 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
1275 efx->net_dev->rx_cpu_rmap = NULL;
1276 return rc;
1277 }
1278 }
1279#endif
1280 return 0;
1281}
1282
46123d04
BH		 1283/* Probe the number and type of interrupts we are able to obtain, and
1284 * the resulting numbers of channels and RX queues.
1285 */
64d8ad6d 1286static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1287{
a16e5b24
BH		 1288 unsigned int max_channels =
1289 min(efx->type->phys_addr_channels, EFX_MAX_CHANNELS);
7f967c01
BH		 1290 unsigned int extra_channels = 0;
1291 unsigned int i, j;
a16e5b24 1292 int rc;
8ceee660 1293
7f967c01
BH		 1294 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1295 if (efx->extra_channel_type[i])
1296 ++extra_channels;
1297
8ceee660 1298 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1299 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1300 unsigned int n_channels;
aa6ef27e 1301
a9a52506 1302 n_channels = efx_wanted_parallelism(efx);
a4900ac9
BH		 1303 if (separate_tx_channels)
1304 n_channels *= 2;
7f967c01 1305 n_channels += extra_channels;
a4900ac9 1306 n_channels = min(n_channels, max_channels);
8ceee660 1307
a4900ac9 1308 for (i = 0; i < n_channels; i++)
8ceee660 1309 xentries[i].entry = i;
a4900ac9 1310 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
8ceee660 1311 if (rc > 0) {
62776d03
BH		 1312 netif_err(efx, drv, efx->net_dev,
1313 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1314 " available (%d < %u).\n", rc, n_channels);
62776d03
BH		 1315 netif_err(efx, drv, efx->net_dev,
1316 "WARNING: Performance may be reduced.\n");
a4900ac9
BH		 1317 EFX_BUG_ON_PARANOID(rc >= n_channels);
1318 n_channels = rc;
8ceee660 1319 rc = pci_enable_msix(efx->pci_dev, xentries,
a4900ac9 1320 n_channels);
8ceee660
BH		 1321 }
1322
1323 if (rc == 0) {
a4900ac9 1324 efx->n_channels = n_channels;
7f967c01
BH		 1325 if (n_channels > extra_channels)
1326 n_channels -= extra_channels;
a4900ac9 1327 if (separate_tx_channels) {
7f967c01
BH		 1328 efx->n_tx_channels = max(n_channels / 2, 1U);
1329 efx->n_rx_channels = max(n_channels -
1330 efx->n_tx_channels,
1331 1U);
a4900ac9 1332 } else {
7f967c01
BH		 1333 efx->n_tx_channels = n_channels;
1334 efx->n_rx_channels = n_channels;
a4900ac9 1335 }
64d8ad6d
BH		 1336 rc = efx_init_rx_cpu_rmap(efx, xentries);
1337 if (rc) {
1338 pci_disable_msix(efx->pci_dev);
1339 return rc;
1340 }
7f967c01 1341 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH		 1342 efx_get_channel(efx, i)->irq =
1343 xentries[i].vector;
8ceee660
BH		 1344 } else {
1345 /* Fall back to single channel MSI */
1346 efx->interrupt_mode = EFX_INT_MODE_MSI;
62776d03
BH		 1347 netif_err(efx, drv, efx->net_dev,
1348 "could not enable MSI-X\n");
8ceee660
BH		 1349 }
1350 }
1351
1352 /* Try single interrupt MSI */
1353 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1354 efx->n_channels = 1;
a4900ac9
BH		 1355 efx->n_rx_channels = 1;
1356 efx->n_tx_channels = 1;
8ceee660
BH		 1357 rc = pci_enable_msi(efx->pci_dev);
1358 if (rc == 0) {
f7d12cdc 1359 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1360 } else {
62776d03
BH		 1361 netif_err(efx, drv, efx->net_dev,
1362 "could not enable MSI\n");
8ceee660
BH		 1363 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1364 }
1365 }
1366
1367 /* Assume legacy interrupts */
1368 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
28b581ab 1369 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
a4900ac9
BH		 1370 efx->n_rx_channels = 1;
1371 efx->n_tx_channels = 1;
8ceee660
BH		 1372 efx->legacy_irq = efx->pci_dev->irq;
1373 }
64d8ad6d 1374
7f967c01
BH		 1375 /* Assign extra channels if possible */
1376 j = efx->n_channels;
1377 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1378 if (!efx->extra_channel_type[i])
1379 continue;
1380 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1381 efx->n_channels <= extra_channels) {
1382 efx->extra_channel_type[i]->handle_no_channel(efx);
1383 } else {
1384 --j;
1385 efx_get_channel(efx, j)->type =
1386 efx->extra_channel_type[i];
1387 }
1388 }
1389
cd2d5b52 1390 /* RSS might be usable on VFs even if it is disabled on the PF */
3132d282 1391 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ?
cd2d5b52
BH		 1392 efx->n_rx_channels : efx_vf_size(efx));
1393
64d8ad6d 1394 return 0;
8ceee660
BH		 1395}
1396
9f2cb71c 1397/* Enable interrupts, then probe and start the event queues */
7f967c01 1398static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq)
9f2cb71c
BH		 1399{
1400 struct efx_channel *channel;
1401
8b7325b4
BH		 1402 BUG_ON(efx->state == STATE_DISABLED);
1403
9f2cb71c
BH		 1404 if (efx->legacy_irq)
1405 efx->legacy_irq_enabled = true;
1406 efx_nic_enable_interrupts(efx);
1407
1408 efx_for_each_channel(channel, efx) {
7f967c01
BH		 1409 if (!channel->type->keep_eventq || !may_keep_eventq)
1410 efx_init_eventq(channel);
9f2cb71c
BH		 1411 efx_start_eventq(channel);
1412 }
1413
1414 efx_mcdi_mode_event(efx);
1415}
1416
7f967c01 1417static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq)
9f2cb71c
BH		 1418{
1419 struct efx_channel *channel;
1420
8b7325b4
BH		 1421 if (efx->state == STATE_DISABLED)
1422 return;
1423
9f2cb71c
BH		 1424 efx_mcdi_mode_poll(efx);
1425
1426 efx_nic_disable_interrupts(efx);
1427 if (efx->legacy_irq) {
1428 synchronize_irq(efx->legacy_irq);
1429 efx->legacy_irq_enabled = false;
1430 }
1431
1432 efx_for_each_channel(channel, efx) {
1433 if (channel->irq)
1434 synchronize_irq(channel->irq);
1435
1436 efx_stop_eventq(channel);
7f967c01
BH		 1437 if (!channel->type->keep_eventq || !may_keep_eventq)
1438 efx_fini_eventq(channel);
9f2cb71c
BH		 1439 }
1440}
1441
8ceee660
BH		 1442static void efx_remove_interrupts(struct efx_nic *efx)
1443{
1444 struct efx_channel *channel;
1445
1446 /* Remove MSI/MSI-X interrupts */
64ee3120 1447 efx_for_each_channel(channel, efx)
8ceee660
BH		 1448 channel->irq = 0;
1449 pci_disable_msi(efx->pci_dev);
1450 pci_disable_msix(efx->pci_dev);
1451
1452 /* Remove legacy interrupt */
1453 efx->legacy_irq = 0;
1454}
1455
8831da7b 1456static void efx_set_channels(struct efx_nic *efx)
8ceee660 1457{
602a5322
BH		 1458 struct efx_channel *channel;
1459 struct efx_tx_queue *tx_queue;
1460
97653431 1461 efx->tx_channel_offset =
a4900ac9 1462 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
602a5322 1463
79d68b37
SH		 1464 /* We need to mark which channels really have RX and TX
1465 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH		 1466 * RX-only and TX-only channels.
1467 */
1468 efx_for_each_channel(channel, efx) {
79d68b37
SH		 1469 if (channel->channel < efx->n_rx_channels)
1470 channel->rx_queue.core_index = channel->channel;
1471 else
1472 channel->rx_queue.core_index = -1;
1473
602a5322
BH		 1474 efx_for_each_channel_tx_queue(tx_queue, channel)
1475 tx_queue->queue -= (efx->tx_channel_offset *
1476 EFX_TXQ_TYPES);
1477 }
8ceee660
BH		 1478}
1479
1480static int efx_probe_nic(struct efx_nic *efx)
1481{
765c9f46 1482 size_t i;
8ceee660
BH		 1483 int rc;
1484
62776d03 1485 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH		 1486
1487 /* Carry out hardware-type specific initialisation */
ef2b90ee 1488 rc = efx->type->probe(efx);
8ceee660
BH		 1489 if (rc)
1490 return rc;
1491
a4900ac9 1492 /* Determine the number of channels and queues by trying to hook
8ceee660 1493 * in MSI-X interrupts. */
64d8ad6d
BH		 1494 rc = efx_probe_interrupts(efx);
1495 if (rc)
1496 goto fail;
8ceee660 1497
28e47c49
BH		 1498 efx->type->dimension_resources(efx);
1499
5d3a6fca
BH		 1500 if (efx->n_channels > 1)
1501 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
765c9f46 1502 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
278bc429 1503 efx->rx_indir_table[i] =
cd2d5b52 1504 ethtool_rxfh_indir_default(i, efx->rss_spread);
5d3a6fca 1505
8831da7b 1506 efx_set_channels(efx);
c4f4adc7
BH		 1507 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1508 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH		 1509
1510 /* Initialise the interrupt moderation settings */
9e393b30
BH		 1511 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1512 true);
8ceee660
BH		 1513
1514 return 0;
64d8ad6d
BH		 1515
1516fail:
1517 efx->type->remove(efx);
1518 return rc;
8ceee660
BH		 1519}
1520
1521static void efx_remove_nic(struct efx_nic *efx)
1522{
62776d03 1523 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH		 1524
1525 efx_remove_interrupts(efx);
ef2b90ee 1526 efx->type->remove(efx);
8ceee660
BH		 1527}
1528
1529/**************************************************************************
1530 *
1531 * NIC startup/shutdown
1532 *
1533 *************************************************************************/
1534
1535static int efx_probe_all(struct efx_nic *efx)
1536{
8ceee660
BH		 1537 int rc;
1538
8ceee660
BH		 1539 rc = efx_probe_nic(efx);
1540 if (rc) {
62776d03 1541 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH		 1542 goto fail1;
1543 }
1544
8ceee660
BH		 1545 rc = efx_probe_port(efx);
1546 if (rc) {
62776d03 1547 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH		 1548 goto fail2;
1549 }
1550
7e6d06f0
BH		 1551 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1552 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1553 rc = -EINVAL;
1554 goto fail3;
1555 }
ecc910f5 1556 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1557
64eebcfd
BH		 1558 rc = efx_probe_filters(efx);
1559 if (rc) {
1560 netif_err(efx, probe, efx->net_dev,
1561 "failed to create filter tables\n");
7f967c01 1562 goto fail3;
64eebcfd
BH		 1563 }
1564
7f967c01
BH		 1565 rc = efx_probe_channels(efx);
1566 if (rc)
1567 goto fail4;
1568
8ceee660
BH		 1569 return 0;
1570
64eebcfd 1571 fail4:
7f967c01 1572 efx_remove_filters(efx);
8ceee660 1573 fail3:
8ceee660
BH		 1574 efx_remove_port(efx);
1575 fail2:
1576 efx_remove_nic(efx);
1577 fail1:
1578 return rc;
1579}
1580
8b7325b4
BH		 1581/* If the interface is supposed to be running but is not, start
1582 * the hardware and software data path, regular activity for the port
1583 * (MAC statistics, link polling, etc.) and schedule the port to be
1584 * reconfigured. Interrupts must already be enabled. This function
1585 * is safe to call multiple times, so long as the NIC is not disabled.
1586 * Requires the RTNL lock.
9f2cb71c 1587 */
8ceee660
BH		 1588static void efx_start_all(struct efx_nic *efx)
1589{
8ceee660 1590 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1591 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH		 1592
1593 /* Check that it is appropriate to restart the interface. All
1594 * of these flags are safe to read under just the rtnl lock */
8b7325b4 1595 if (efx->port_enabled || !netif_running(efx->net_dev))
8ceee660
BH		 1596 return;
1597
8ceee660 1598 efx_start_port(efx);
9f2cb71c 1599 efx_start_datapath(efx);
8880f4ec 1600
626950db
AR		 1601 /* Start the hardware monitor if there is one */
1602 if (efx->type->monitor != NULL)
8ceee660
BH		 1603 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1604 efx_monitor_interval);
626950db
AR		 1605
1606 /* If link state detection is normally event-driven, we have
1607 * to poll now because we could have missed a change
1608 */
1609 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
78c1f0a0
SH		 1610 mutex_lock(&efx->mac_lock);
1611 if (efx->phy_op->poll(efx))
1612 efx_link_status_changed(efx);
1613 mutex_unlock(&efx->mac_lock);
1614 }
55edc6e6 1615
ef2b90ee 1616 efx->type->start_stats(efx);
8ceee660
BH		 1617}
1618
1619/* Flush all delayed work. Should only be called when no more delayed work
1620 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1621 * since we're holding the rtnl_lock at this point. */
1622static void efx_flush_all(struct efx_nic *efx)
1623{
dd40781e 1624 /* Make sure the hardware monitor and event self-test are stopped */
8ceee660 1625 cancel_delayed_work_sync(&efx->monitor_work);
dd40781e 1626 efx_selftest_async_cancel(efx);
8ceee660 1627 /* Stop scheduled port reconfigurations */
766ca0fa 1628 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1629}
1630
8b7325b4
BH		 1631/* Quiesce the hardware and software data path, and regular activity
1632 * for the port without bringing the link down. Safe to call multiple
1633 * times with the NIC in almost any state, but interrupts should be
1634 * enabled. Requires the RTNL lock.
1635 */
8ceee660
BH		 1636static void efx_stop_all(struct efx_nic *efx)
1637{
8ceee660
BH		 1638 EFX_ASSERT_RESET_SERIALISED(efx);
1639
1640 /* port_enabled can be read safely under the rtnl lock */
1641 if (!efx->port_enabled)
1642 return;
1643
ef2b90ee 1644 efx->type->stop_stats(efx);
8ceee660
BH		 1645 efx_stop_port(efx);
1646
fdaa9aed 1647 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
8ceee660
BH		 1648 efx_flush_all(efx);
1649
29c69a48
BH		 1650 /* Stop the kernel transmit interface. This is only valid if
1651 * the device is stopped or detached; otherwise the watchdog
1652 * may fire immediately.
1653 */
1654 WARN_ON(netif_running(efx->net_dev) &&
1655 netif_device_present(efx->net_dev));
9f2cb71c
BH		 1656 netif_tx_disable(efx->net_dev);
1657
1658 efx_stop_datapath(efx);
8ceee660
BH		 1659}
1660
1661static void efx_remove_all(struct efx_nic *efx)
1662{
4642610c 1663 efx_remove_channels(efx);
7f967c01 1664 efx_remove_filters(efx);
8ceee660
BH		 1665 efx_remove_port(efx);
1666 efx_remove_nic(efx);
1667}
1668
8ceee660
BH		 1669/**************************************************************************
1670 *
1671 * Interrupt moderation
1672 *
1673 **************************************************************************/
1674
cc180b69 1675static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
0d86ebd8 1676{
b548f976
BH		 1677 if (usecs == 0)
1678 return 0;
cc180b69 1679 if (usecs * 1000 < quantum_ns)
0d86ebd8 1680 return 1; /* never round down to 0 */
cc180b69 1681 return usecs * 1000 / quantum_ns;
0d86ebd8
BH		 1682}
1683
8ceee660 1684/* Set interrupt moderation parameters */
9e393b30
BH		 1685int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1686 unsigned int rx_usecs, bool rx_adaptive,
1687 bool rx_may_override_tx)
8ceee660 1688{
f7d12cdc 1689 struct efx_channel *channel;
cc180b69
BH		 1690 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1691 efx->timer_quantum_ns,
1692 1000);
1693 unsigned int tx_ticks;
1694 unsigned int rx_ticks;
8ceee660
BH		 1695
1696 EFX_ASSERT_RESET_SERIALISED(efx);
1697
cc180b69 1698 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
9e393b30
BH		 1699 return -EINVAL;
1700
cc180b69
BH		 1701 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1702 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1703
9e393b30
BH		 1704 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1705 !rx_may_override_tx) {
1706 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1707 "RX and TX IRQ moderation must be equal\n");
1708 return -EINVAL;
1709 }
1710
6fb70fd1 1711 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1712 efx->irq_rx_moderation = rx_ticks;
f7d12cdc 1713 efx_for_each_channel(channel, efx) {
525da907 1714 if (efx_channel_has_rx_queue(channel))
f7d12cdc 1715 channel->irq_moderation = rx_ticks;
525da907 1716 else if (efx_channel_has_tx_queues(channel))
f7d12cdc
BH		 1717 channel->irq_moderation = tx_ticks;
1718 }
9e393b30
BH		 1719
1720 return 0;
8ceee660
BH		 1721}
1722
a0c4faf5
BH		 1723void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
1724 unsigned int *rx_usecs, bool *rx_adaptive)
1725{
cc180b69
BH		 1726 /* We must round up when converting ticks to microseconds
1727 * because we round down when converting the other way.
1728 */
1729
a0c4faf5 1730 *rx_adaptive = efx->irq_rx_adaptive;
cc180b69
BH		 1731 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
1732 efx->timer_quantum_ns,
1733 1000);
a0c4faf5
BH		 1734
1735 /* If channels are shared between RX and TX, so is IRQ
1736 * moderation. Otherwise, IRQ moderation is the same for all
1737 * TX channels and is not adaptive.
1738 */
1739 if (efx->tx_channel_offset == 0)
1740 *tx_usecs = *rx_usecs;
1741 else
cc180b69 1742 *tx_usecs = DIV_ROUND_UP(
a0c4faf5 1743 efx->channel[efx->tx_channel_offset]->irq_moderation *
cc180b69
BH		 1744 efx->timer_quantum_ns,
1745 1000);
a0c4faf5
BH		 1746}
1747
8ceee660
BH		 1748/**************************************************************************
1749 *
1750 * Hardware monitor
1751 *
1752 **************************************************************************/
1753
e254c274 1754/* Run periodically off the general workqueue */
8ceee660
BH		 1755static void efx_monitor(struct work_struct *data)
1756{
1757 struct efx_nic *efx = container_of(data, struct efx_nic,
1758 monitor_work.work);
8ceee660 1759
62776d03
BH		 1760 netif_vdbg(efx, timer, efx->net_dev,
1761 "hardware monitor executing on CPU %d\n",
1762 raw_smp_processor_id());
ef2b90ee 1763 BUG_ON(efx->type->monitor == NULL);
8ceee660 1764
8ceee660
BH		 1765 /* If the mac_lock is already held then it is likely a port
1766 * reconfiguration is already in place, which will likely do
e254c274
BH		 1767 * most of the work of monitor() anyway. */
1768 if (mutex_trylock(&efx->mac_lock)) {
1769 if (efx->port_enabled)
1770 efx->type->monitor(efx);
1771 mutex_unlock(&efx->mac_lock);
1772 }
8ceee660 1773
8ceee660
BH		 1774 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1775 efx_monitor_interval);
1776}
1777
1778/**************************************************************************
1779 *
1780 * ioctls
1781 *
1782 *************************************************************************/
1783
1784/* Net device ioctl
1785 * Context: process, rtnl_lock() held.
1786 */
1787static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1788{
767e468c 1789 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 1790 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 1791
7c236c43
SH		 1792 if (cmd == SIOCSHWTSTAMP)
1793 return efx_ptp_ioctl(efx, ifr, cmd);
1794
68e7f45e
BH		 1795 /* Convert phy_id from older PRTAD/DEVAD format */
1796 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1797 (data->phy_id & 0xfc00) == 0x0400)
1798 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1799
1800 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 1801}
1802
1803/**************************************************************************
1804 *
1805 * NAPI interface
1806 *
1807 **************************************************************************/
1808
7f967c01
BH		 1809static void efx_init_napi_channel(struct efx_channel *channel)
1810{
1811 struct efx_nic *efx = channel->efx;
1812
1813 channel->napi_dev = efx->net_dev;
1814 netif_napi_add(channel->napi_dev, &channel->napi_str,
1815 efx_poll, napi_weight);
1816}
1817
e8f14992 1818static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH		 1819{
1820 struct efx_channel *channel;
8ceee660 1821
7f967c01
BH		 1822 efx_for_each_channel(channel, efx)
1823 efx_init_napi_channel(channel);
e8f14992
BH		 1824}
1825
1826static void efx_fini_napi_channel(struct efx_channel *channel)
1827{
1828 if (channel->napi_dev)
1829 netif_napi_del(&channel->napi_str);
1830 channel->napi_dev = NULL;
8ceee660
BH		 1831}
1832
1833static void efx_fini_napi(struct efx_nic *efx)
1834{
1835 struct efx_channel *channel;
1836
e8f14992
BH		 1837 efx_for_each_channel(channel, efx)
1838 efx_fini_napi_channel(channel);
8ceee660
BH		 1839}
1840
1841/**************************************************************************
1842 *
1843 * Kernel netpoll interface
1844 *
1845 *************************************************************************/
1846
1847#ifdef CONFIG_NET_POLL_CONTROLLER
1848
1849/* Although in the common case interrupts will be disabled, this is not
1850 * guaranteed. However, all our work happens inside the NAPI callback,
1851 * so no locking is required.
1852 */
1853static void efx_netpoll(struct net_device *net_dev)
1854{
767e468c 1855 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1856 struct efx_channel *channel;
1857
64ee3120 1858 efx_for_each_channel(channel, efx)
8ceee660
BH		 1859 efx_schedule_channel(channel);
1860}
1861
1862#endif
1863
1864/**************************************************************************
1865 *
1866 * Kernel net device interface
1867 *
1868 *************************************************************************/
1869
1870/* Context: process, rtnl_lock() held. */
1871static int efx_net_open(struct net_device *net_dev)
1872{
767e468c 1873 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH		 1874 int rc;
1875
62776d03
BH		 1876 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1877 raw_smp_processor_id());
8ceee660 1878
8b7325b4
BH		 1879 rc = efx_check_disabled(efx);
1880 if (rc)
1881 return rc;
f8b87c17
BH		 1882 if (efx->phy_mode & PHY_MODE_SPECIAL)
1883 return -EBUSY;
8880f4ec
BH		 1884 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1885 return -EIO;
f8b87c17 1886
78c1f0a0
SH		 1887 /* Notify the kernel of the link state polled during driver load,
1888 * before the monitor starts running */
1889 efx_link_status_changed(efx);
1890
8ceee660 1891 efx_start_all(efx);
dd40781e 1892 efx_selftest_async_start(efx);
8ceee660
BH		 1893 return 0;
1894}
1895
1896/* Context: process, rtnl_lock() held.
1897 * Note that the kernel will ignore our return code; this method
1898 * should really be a void.
1899 */
1900static int efx_net_stop(struct net_device *net_dev)
1901{
767e468c 1902 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1903
62776d03
BH		 1904 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1905 raw_smp_processor_id());
8ceee660 1906
8b7325b4
BH		 1907 /* Stop the device and flush all the channels */
1908 efx_stop_all(efx);
8ceee660
BH		 1909
1910 return 0;
1911}
1912
5b9e207c 1913/* Context: process, dev_base_lock or RTNL held, non-blocking. */
2aa9ef11
BH		 1914static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
1915 struct rtnl_link_stats64 *stats)
8ceee660 1916{
767e468c 1917 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1918 struct efx_mac_stats *mac_stats = &efx->mac_stats;
8ceee660 1919
55edc6e6 1920 spin_lock_bh(&efx->stats_lock);
1cb34522 1921
ef2b90ee 1922 efx->type->update_stats(efx);
8ceee660
BH		 1923
1924 stats->rx_packets = mac_stats->rx_packets;
1925 stats->tx_packets = mac_stats->tx_packets;
1926 stats->rx_bytes = mac_stats->rx_bytes;
1927 stats->tx_bytes = mac_stats->tx_bytes;
80485d34 1928 stats->rx_dropped = efx->n_rx_nodesc_drop_cnt;
8ceee660
BH		 1929 stats->multicast = mac_stats->rx_multicast;
1930 stats->collisions = mac_stats->tx_collision;
1931 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1932 mac_stats->rx_length_error);
8ceee660
BH		 1933 stats->rx_crc_errors = mac_stats->rx_bad;
1934 stats->rx_frame_errors = mac_stats->rx_align_error;
1935 stats->rx_fifo_errors = mac_stats->rx_overflow;
1936 stats->rx_missed_errors = mac_stats->rx_missed;
1937 stats->tx_window_errors = mac_stats->tx_late_collision;
1938
1939 stats->rx_errors = (stats->rx_length_errors +
8ceee660
BH		 1940 stats->rx_crc_errors +
1941 stats->rx_frame_errors +
8ceee660
BH		 1942 mac_stats->rx_symbol_error);
1943 stats->tx_errors = (stats->tx_window_errors +
1944 mac_stats->tx_bad);
1945
1cb34522
BH		 1946 spin_unlock_bh(&efx->stats_lock);
1947
8ceee660
BH		 1948 return stats;
1949}
1950
1951/* Context: netif_tx_lock held, BHs disabled. */
1952static void efx_watchdog(struct net_device *net_dev)
1953{
767e468c 1954 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1955
62776d03
BH		 1956 netif_err(efx, tx_err, efx->net_dev,
1957 "TX stuck with port_enabled=%d: resetting channels\n",
1958 efx->port_enabled);
8ceee660 1959
739bb23d 1960 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 1961}
1962
1963
1964/* Context: process, rtnl_lock() held. */
1965static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1966{
767e468c 1967 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 1968 int rc;
8ceee660 1969
8b7325b4
BH		 1970 rc = efx_check_disabled(efx);
1971 if (rc)
1972 return rc;
8ceee660
BH		 1973 if (new_mtu > EFX_MAX_MTU)
1974 return -EINVAL;
1975
62776d03 1976 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 1977
29c69a48
BH		 1978 efx_device_detach_sync(efx);
1979 efx_stop_all(efx);
1980
d3245b28 1981 mutex_lock(&efx->mac_lock);
8ceee660 1982 net_dev->mtu = new_mtu;
710b208d 1983 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1984 mutex_unlock(&efx->mac_lock);
1985
8ceee660 1986 efx_start_all(efx);
29c69a48 1987 netif_device_attach(efx->net_dev);
6c8eef4a 1988 return 0;
8ceee660
BH		 1989}
1990
1991static int efx_set_mac_address(struct net_device *net_dev, void *data)
1992{
767e468c 1993 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1994 struct sockaddr *addr = data;
1995 char *new_addr = addr->sa_data;
1996
8ceee660 1997 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH		 1998 netif_err(efx, drv, efx->net_dev,
1999 "invalid ethernet MAC address requested: %pM\n",
2000 new_addr);
504f9b5a 2001 return -EADDRNOTAVAIL;
8ceee660
BH		 2002 }
2003
2004 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
cd2d5b52 2005 efx_sriov_mac_address_changed(efx);
8ceee660
BH		 2006
2007 /* Reconfigure the MAC */
d3245b28 2008 mutex_lock(&efx->mac_lock);
710b208d 2009 efx->type->reconfigure_mac(efx);
d3245b28 2010 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 2011
2012 return 0;
2013}
2014
a816f75a 2015/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 2016static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 2017{
767e468c 2018 struct efx_nic *efx = netdev_priv(net_dev);
22bedad3 2019 struct netdev_hw_addr *ha;
8ceee660 2020 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
8ceee660
BH		 2021 u32 crc;
2022 int bit;
8ceee660 2023
8be4f3e6 2024 efx->promiscuous = !!(net_dev->flags & IFF_PROMISC);
8ceee660
BH		 2025
2026 /* Build multicast hash table */
8be4f3e6 2027 if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
8ceee660
BH		 2028 memset(mc_hash, 0xff, sizeof(*mc_hash));
2029 } else {
2030 memset(mc_hash, 0x00, sizeof(*mc_hash));
22bedad3
JP		 2031 netdev_for_each_mc_addr(ha, net_dev) {
2032 crc = ether_crc_le(ETH_ALEN, ha->addr);
8ceee660 2033 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
32766ec8 2034 __set_bit_le(bit, mc_hash);
8ceee660 2035 }
8ceee660 2036
8be4f3e6
BH		 2037 /* Broadcast packets go through the multicast hash filter.
2038 * ether_crc_le() of the broadcast address is 0xbe2612ff
2039 * so we always add bit 0xff to the mask.
2040 */
32766ec8 2041 __set_bit_le(0xff, mc_hash);
8be4f3e6 2042 }
a816f75a 2043
8be4f3e6
BH		 2044 if (efx->port_enabled)
2045 queue_work(efx->workqueue, &efx->mac_work);
2046 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 2047}
2048
c8f44aff 2049static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH		 2050{
2051 struct efx_nic *efx = netdev_priv(net_dev);
2052
2053 /* If disabling RX n-tuple filtering, clear existing filters */
2054 if (net_dev->features & ~data & NETIF_F_NTUPLE)
2055 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2056
2057 return 0;
2058}
2059
c3ecb9f3
SH		 2060static const struct net_device_ops efx_netdev_ops = {
2061 .ndo_open = efx_net_open,
2062 .ndo_stop = efx_net_stop,
4472702e 2063 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH		 2064 .ndo_tx_timeout = efx_watchdog,
2065 .ndo_start_xmit = efx_hard_start_xmit,
2066 .ndo_validate_addr = eth_validate_addr,
2067 .ndo_do_ioctl = efx_ioctl,
2068 .ndo_change_mtu = efx_change_mtu,
2069 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2070 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2071 .ndo_set_features = efx_set_features,
cd2d5b52
BH		 2072#ifdef CONFIG_SFC_SRIOV
2073 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2074 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2075 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2076 .ndo_get_vf_config = efx_sriov_get_vf_config,
2077#endif
c3ecb9f3
SH		 2078#ifdef CONFIG_NET_POLL_CONTROLLER
2079 .ndo_poll_controller = efx_netpoll,
2080#endif
94b274bf 2081 .ndo_setup_tc = efx_setup_tc,
64d8ad6d
BH		 2082#ifdef CONFIG_RFS_ACCEL
2083 .ndo_rx_flow_steer = efx_filter_rfs,
2084#endif
c3ecb9f3
SH		 2085};
2086
7dde596e
BH		 2087static void efx_update_name(struct efx_nic *efx)
2088{
2089 strcpy(efx->name, efx->net_dev->name);
2090 efx_mtd_rename(efx);
2091 efx_set_channel_names(efx);
2092}
2093
8ceee660
BH		 2094static int efx_netdev_event(struct notifier_block *this,
2095 unsigned long event, void *ptr)
2096{
d3208b5e 2097 struct net_device *net_dev = ptr;
8ceee660 2098
7dde596e
BH		 2099 if (net_dev->netdev_ops == &efx_netdev_ops &&
2100 event == NETDEV_CHANGENAME)
2101 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 2102
2103 return NOTIFY_DONE;
2104}
2105
2106static struct notifier_block efx_netdev_notifier = {
2107 .notifier_call = efx_netdev_event,
2108};
2109
06d5e193
BH		 2110static ssize_t
2111show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2112{
2113 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2114 return sprintf(buf, "%d\n", efx->phy_type);
2115}
2116static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL);
2117
8ceee660
BH		 2118static int efx_register_netdev(struct efx_nic *efx)
2119{
2120 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2121 struct efx_channel *channel;
8ceee660
BH		 2122 int rc;
2123
2124 net_dev->watchdog_timeo = 5 * HZ;
2125 net_dev->irq = efx->pci_dev->irq;
c3ecb9f3 2126 net_dev->netdev_ops = &efx_netdev_ops;
8ceee660 2127 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
7e6d06f0 2128 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
8ceee660 2129
7dde596e 2130 rtnl_lock();
aed0628d 2131
7153f623
BH		 2132 /* Enable resets to be scheduled and check whether any were
2133 * already requested. If so, the NIC is probably hosed so we
2134 * abort.
2135 */
2136 efx->state = STATE_READY;
2137 smp_mb(); /* ensure we change state before checking reset_pending */
2138 if (efx->reset_pending) {
2139 netif_err(efx, probe, efx->net_dev,
2140 "aborting probe due to scheduled reset\n");
2141 rc = -EIO;
2142 goto fail_locked;
2143 }
2144
aed0628d
BH		 2145 rc = dev_alloc_name(net_dev, net_dev->name);
2146 if (rc < 0)
2147 goto fail_locked;
7dde596e 2148 efx_update_name(efx);
aed0628d 2149
8f8b3d51
BH		 2150 /* Always start with carrier off; PHY events will detect the link */
2151 netif_carrier_off(net_dev);
2152
aed0628d
BH		 2153 rc = register_netdevice(net_dev);
2154 if (rc)
2155 goto fail_locked;
2156
c04bfc6b
BH		 2157 efx_for_each_channel(channel, efx) {
2158 struct efx_tx_queue *tx_queue;
60031fcc
BH		 2159 efx_for_each_channel_tx_queue(tx_queue, channel)
2160 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH		 2161 }
2162
7dde596e 2163 rtnl_unlock();
8ceee660 2164
06d5e193
BH		 2165 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2166 if (rc) {
62776d03
BH		 2167 netif_err(efx, drv, efx->net_dev,
2168 "failed to init net dev attributes\n");
06d5e193
BH		 2169 goto fail_registered;
2170 }
2171
8ceee660 2172 return 0;
06d5e193 2173
7153f623
BH		 2174fail_registered:
2175 rtnl_lock();
2176 unregister_netdevice(net_dev);
aed0628d 2177fail_locked:
7153f623 2178 efx->state = STATE_UNINIT;
aed0628d 2179 rtnl_unlock();
62776d03 2180 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2181 return rc;
8ceee660
BH		 2182}
2183
2184static void efx_unregister_netdev(struct efx_nic *efx)
2185{
f7d12cdc 2186 struct efx_channel *channel;
8ceee660
BH		 2187 struct efx_tx_queue *tx_queue;
2188
2189 if (!efx->net_dev)
2190 return;
2191
767e468c 2192 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660
BH		 2193
2194 /* Free up any skbs still remaining. This has to happen before
2195 * we try to unregister the netdev as running their destructors
2196 * may be needed to get the device ref. count to 0. */
f7d12cdc
BH		 2197 efx_for_each_channel(channel, efx) {
2198 efx_for_each_channel_tx_queue(tx_queue, channel)
2199 efx_release_tx_buffers(tx_queue);
2200 }
8ceee660 2201
73ba7b68
BH		 2202 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2203 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
7153f623
BH		 2204
2205 rtnl_lock();
2206 unregister_netdevice(efx->net_dev);
2207 efx->state = STATE_UNINIT;
2208 rtnl_unlock();
8ceee660
BH		 2209}
2210
2211/**************************************************************************
2212 *
2213 * Device reset and suspend
2214 *
2215 **************************************************************************/
2216
2467ca46
BH		 2217/* Tears down the entire software state and most of the hardware state
2218 * before reset. */
d3245b28 2219void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2220{
8ceee660
BH		 2221 EFX_ASSERT_RESET_SERIALISED(efx);
2222
2467ca46 2223 efx_stop_all(efx);
7f967c01 2224 efx_stop_interrupts(efx, false);
5642ceef
BH		 2225
2226 mutex_lock(&efx->mac_lock);
4b988280
SH		 2227 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2228 efx->phy_op->fini(efx);
ef2b90ee 2229 efx->type->fini(efx);
8ceee660
BH		 2230}
2231
2467ca46
BH		 2232/* This function will always ensure that the locks acquired in
2233 * efx_reset_down() are released. A failure return code indicates
2234 * that we were unable to reinitialise the hardware, and the
2235 * driver should be disabled. If ok is false, then the rx and tx
2236 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2237int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 2238{
2239 int rc;
2240
2467ca46 2241 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2242
ef2b90ee 2243 rc = efx->type->init(efx);
8ceee660 2244 if (rc) {
62776d03 2245 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2246 goto fail;
8ceee660
BH		 2247 }
2248
eb9f6744
BH		 2249 if (!ok)
2250 goto fail;
2251
4b988280 2252 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
eb9f6744
BH		 2253 rc = efx->phy_op->init(efx);
2254 if (rc)
2255 goto fail;
2256 if (efx->phy_op->reconfigure(efx))
62776d03
BH		 2257 netif_err(efx, drv, efx->net_dev,
2258 "could not restore PHY settings\n");
4b988280
SH		 2259 }
2260
710b208d 2261 efx->type->reconfigure_mac(efx);
8ceee660 2262
7f967c01 2263 efx_start_interrupts(efx, false);
64eebcfd 2264 efx_restore_filters(efx);
cd2d5b52 2265 efx_sriov_reset(efx);
eb9f6744 2266
eb9f6744
BH		 2267 mutex_unlock(&efx->mac_lock);
2268
2269 efx_start_all(efx);
2270
2271 return 0;
2272
2273fail:
2274 efx->port_initialized = false;
2467ca46
BH		 2275
2276 mutex_unlock(&efx->mac_lock);
2277
8ceee660
BH		 2278 return rc;
2279}
2280
eb9f6744
BH		 2281/* Reset the NIC using the specified method. Note that the reset may
2282 * fail, in which case the card will be left in an unusable state.
8ceee660 2283 *
eb9f6744 2284 * Caller must hold the rtnl_lock.
8ceee660 2285 */
eb9f6744 2286int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2287{
eb9f6744
BH		 2288 int rc, rc2;
2289 bool disabled;
8ceee660 2290
62776d03
BH		 2291 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2292 RESET_TYPE(method));
8ceee660 2293
c2f3b8e3 2294 efx_device_detach_sync(efx);
d3245b28 2295 efx_reset_down(efx, method);
8ceee660 2296
ef2b90ee 2297 rc = efx->type->reset(efx, method);
8ceee660 2298 if (rc) {
62776d03 2299 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2300 goto out;
8ceee660
BH		 2301 }
2302
a7d529ae
BH		 2303 /* Clear flags for the scopes we covered. We assume the NIC and
2304 * driver are now quiescent so that there is no race here.
2305 */
2306 efx->reset_pending &= -(1 << (method + 1));
8ceee660
BH		 2307
2308 /* Reinitialise bus-mastering, which may have been turned off before
2309 * the reset was scheduled. This is still appropriate, even in the
2310 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2311 * can respond to requests. */
2312 pci_set_master(efx->pci_dev);
2313
eb9f6744 2314out:
8ceee660 2315 /* Leave device stopped if necessary */
626950db
AR		 2316 disabled = rc ||
2317 method == RESET_TYPE_DISABLE ||
2318 method == RESET_TYPE_RECOVER_OR_DISABLE;
eb9f6744
BH		 2319 rc2 = efx_reset_up(efx, method, !disabled);
2320 if (rc2) {
2321 disabled = true;
2322 if (!rc)
2323 rc = rc2;
8ceee660
BH		 2324 }
2325
eb9f6744 2326 if (disabled) {
f49a4589 2327 dev_close(efx->net_dev);
62776d03 2328 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2329 efx->state = STATE_DISABLED;
f4bd954e 2330 } else {
62776d03 2331 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2332 netif_device_attach(efx->net_dev);
f4bd954e 2333 }
8ceee660
BH		 2334 return rc;
2335}
2336
626950db
AR		 2337/* Try recovery mechanisms.
2338 * For now only EEH is supported.
2339 * Returns 0 if the recovery mechanisms are unsuccessful.
2340 * Returns a non-zero value otherwise.
2341 */
2342static int efx_try_recovery(struct efx_nic *efx)
2343{
2344#ifdef CONFIG_EEH
2345 /* A PCI error can occur and not be seen by EEH because nothing
2346 * happens on the PCI bus. In this case the driver may fail and
2347 * schedule a 'recover or reset', leading to this recovery handler.
2348 * Manually call the eeh failure check function.
2349 */
2350 struct eeh_dev *eehdev =
2351 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
2352
2353 if (eeh_dev_check_failure(eehdev)) {
2354 /* The EEH mechanisms will handle the error and reset the
2355 * device if necessary.
2356 */
2357 return 1;
2358 }
2359#endif
2360 return 0;
2361}
2362
8ceee660
BH		 2363/* The worker thread exists so that code that cannot sleep can
2364 * schedule a reset for later.
2365 */
2366static void efx_reset_work(struct work_struct *data)
2367{
eb9f6744 2368 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
626950db
AR		 2369 unsigned long pending;
2370 enum reset_type method;
2371
2372 pending = ACCESS_ONCE(efx->reset_pending);
2373 method = fls(pending) - 1;
2374
2375 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2376 method == RESET_TYPE_RECOVER_OR_ALL) &&
2377 efx_try_recovery(efx))
2378 return;
8ceee660 2379
a7d529ae 2380 if (!pending)
319ba649
SH		 2381 return;
2382
eb9f6744 2383 rtnl_lock();
7153f623
BH		 2384
2385 /* We checked the state in efx_schedule_reset() but it may
2386 * have changed by now. Now that we have the RTNL lock,
2387 * it cannot change again.
2388 */
2389 if (efx->state == STATE_READY)
626950db 2390 (void)efx_reset(efx, method);
7153f623 2391
eb9f6744 2392 rtnl_unlock();
8ceee660
BH		 2393}
2394
2395void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2396{
2397 enum reset_type method;
2398
626950db
AR		 2399 if (efx->state == STATE_RECOVERY) {
2400 netif_dbg(efx, drv, efx->net_dev,
2401 "recovering: skip scheduling %s reset\n",
2402 RESET_TYPE(type));
2403 return;
2404 }
2405
8ceee660
BH		 2406 switch (type) {
2407 case RESET_TYPE_INVISIBLE:
2408 case RESET_TYPE_ALL:
626950db 2409 case RESET_TYPE_RECOVER_OR_ALL:
8ceee660
BH		 2410 case RESET_TYPE_WORLD:
2411 case RESET_TYPE_DISABLE:
626950db 2412 case RESET_TYPE_RECOVER_OR_DISABLE:
8ceee660 2413 method = type;
0e2a9c7c
BH		 2414 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2415 RESET_TYPE(method));
8ceee660 2416 break;
8ceee660 2417 default:
0e2a9c7c 2418 method = efx->type->map_reset_reason(type);
62776d03
BH		 2419 netif_dbg(efx, drv, efx->net_dev,
2420 "scheduling %s reset for %s\n",
2421 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH		 2422 break;
2423 }
8ceee660 2424
a7d529ae 2425 set_bit(method, &efx->reset_pending);
7153f623
BH		 2426 smp_mb(); /* ensure we change reset_pending before checking state */
2427
2428 /* If we're not READY then just leave the flags set as the cue
2429 * to abort probing or reschedule the reset later.
2430 */
2431 if (ACCESS_ONCE(efx->state) != STATE_READY)
2432 return;
8ceee660 2433
8880f4ec
BH		 2434 /* efx_process_channel() will no longer read events once a
2435 * reset is scheduled. So switch back to poll'd MCDI completions. */
2436 efx_mcdi_mode_poll(efx);
2437
1ab00629 2438 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 2439}
2440
2441/**************************************************************************
2442 *
2443 * List of NICs we support
2444 *
2445 **************************************************************************/
2446
2447/* PCI device ID table */
a3aa1884 2448static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
937383a5
BH		 2449 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2450 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
daeda630 2451 .driver_data = (unsigned long) &falcon_a1_nic_type},
937383a5
BH		 2452 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2453 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
daeda630 2454 .driver_data = (unsigned long) &falcon_b0_nic_type},
547c474f 2455 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2456 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2457 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2458 .driver_data = (unsigned long) &siena_a0_nic_type},
8ceee660
BH		 2459 {0} /* end of list */
2460};
2461
2462/**************************************************************************
2463 *
3759433d 2464 * Dummy PHY/MAC operations
8ceee660 2465 *
01aad7b6 2466 * Can be used for some unimplemented operations
8ceee660
BH		 2467 * Needed so all function pointers are valid and do not have to be tested
2468 * before use
2469 *
2470 **************************************************************************/
2471int efx_port_dummy_op_int(struct efx_nic *efx)
2472{
2473 return 0;
2474}
2475void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2476
2477static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH		 2478{
2479 return false;
2480}
8ceee660 2481
6c8c2513 2482static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2483 .init = efx_port_dummy_op_int,
d3245b28 2484 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2485 .poll = efx_port_dummy_op_poll,
8ceee660 2486 .fini = efx_port_dummy_op_void,
8ceee660
BH		 2487};
2488
8ceee660
BH		 2489/**************************************************************************
2490 *
2491 * Data housekeeping
2492 *
2493 **************************************************************************/
2494
2495/* This zeroes out and then fills in the invariants in a struct
2496 * efx_nic (including all sub-structures).
2497 */
adeb15aa 2498static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH		 2499 struct pci_dev *pci_dev, struct net_device *net_dev)
2500{
4642610c 2501 int i;
8ceee660
BH		 2502
2503 /* Initialise common structures */
8ceee660 2504 spin_lock_init(&efx->biu_lock);
76884835
BH		 2505#ifdef CONFIG_SFC_MTD
2506 INIT_LIST_HEAD(&efx->mtd_list);
2507#endif
8ceee660
BH		 2508 INIT_WORK(&efx->reset_work, efx_reset_work);
2509 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2510 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2511 efx->pci_dev = pci_dev;
62776d03 2512 efx->msg_enable = debug;
f16aeea0 2513 efx->state = STATE_UNINIT;
8ceee660 2514 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2515
2516 efx->net_dev = net_dev;
8ceee660
BH		 2517 spin_lock_init(&efx->stats_lock);
2518 mutex_init(&efx->mac_lock);
2519 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2520 efx->mdio.dev = net_dev;
766ca0fa 2521 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2522 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH		 2523
2524 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH		 2525 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2526 if (!efx->channel[i])
2527 goto fail;
8ceee660
BH		 2528 }
2529
8ceee660
BH		 2530 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
2531
2532 /* Higher numbered interrupt modes are less capable! */
2533 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2534 interrupt_mode);
2535
6977dc63
BH		 2536 /* Would be good to use the net_dev name, but we're too early */
2537 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2538 pci_name(pci_dev));
2539 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2540 if (!efx->workqueue)
4642610c 2541 goto fail;
8d9853d9 2542
8ceee660 2543 return 0;
4642610c
BH		 2544
2545fail:
2546 efx_fini_struct(efx);
2547 return -ENOMEM;
8ceee660
BH		 2548}
2549
2550static void efx_fini_struct(struct efx_nic *efx)
2551{
8313aca3
BH		 2552 int i;
2553
2554 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2555 kfree(efx->channel[i]);
2556
8ceee660
BH		 2557 if (efx->workqueue) {
2558 destroy_workqueue(efx->workqueue);
2559 efx->workqueue = NULL;
2560 }
2561}
2562
2563/**************************************************************************
2564 *
2565 * PCI interface
2566 *
2567 **************************************************************************/
2568
2569/* Main body of final NIC shutdown code
2570 * This is called only at module unload (or hotplug removal).
2571 */
2572static void efx_pci_remove_main(struct efx_nic *efx)
2573{
7153f623
BH		 2574 /* Flush reset_work. It can no longer be scheduled since we
2575 * are not READY.
2576 */
2577 BUG_ON(efx->state == STATE_READY);
2578 cancel_work_sync(&efx->reset_work);
2579
64d8ad6d
BH		 2580#ifdef CONFIG_RFS_ACCEL
2581 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
2582 efx->net_dev->rx_cpu_rmap = NULL;
2583#endif
7f967c01 2584 efx_stop_interrupts(efx, false);
152b6a62 2585 efx_nic_fini_interrupt(efx);
8ceee660 2586 efx_fini_port(efx);
ef2b90ee 2587 efx->type->fini(efx);
8ceee660
BH		 2588 efx_fini_napi(efx);
2589 efx_remove_all(efx);
2590}
2591
2592/* Final NIC shutdown
2593 * This is called only at module unload (or hotplug removal).
2594 */
2595static void efx_pci_remove(struct pci_dev *pci_dev)
2596{
2597 struct efx_nic *efx;
2598
2599 efx = pci_get_drvdata(pci_dev);
2600 if (!efx)
2601 return;
2602
2603 /* Mark the NIC as fini, then stop the interface */
2604 rtnl_lock();
8ceee660 2605 dev_close(efx->net_dev);
5642ceef 2606 efx_stop_interrupts(efx, false);
8ceee660
BH		 2607 rtnl_unlock();
2608
cd2d5b52 2609 efx_sriov_fini(efx);
8ceee660
BH		 2610 efx_unregister_netdev(efx);
2611
7dde596e
BH		 2612 efx_mtd_remove(efx);
2613
8ceee660
BH		 2614 efx_pci_remove_main(efx);
2615
8ceee660 2616 efx_fini_io(efx);
62776d03 2617 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 2618
8ceee660 2619 efx_fini_struct(efx);
3de4e301 2620 pci_set_drvdata(pci_dev, NULL);
8ceee660 2621 free_netdev(efx->net_dev);
626950db
AR		 2622
2623 pci_disable_pcie_error_reporting(pci_dev);
8ceee660
BH		 2624};
2625
460eeaa0
BH		 2626/* NIC VPD information
2627 * Called during probe to display the part number of the
2628 * installed NIC. VPD is potentially very large but this should
2629 * always appear within the first 512 bytes.
2630 */
2631#define SFC_VPD_LEN 512
2632static void efx_print_product_vpd(struct efx_nic *efx)
2633{
2634 struct pci_dev *dev = efx->pci_dev;
2635 char vpd_data[SFC_VPD_LEN];
2636 ssize_t vpd_size;
2637 int i, j;
2638
2639 /* Get the vpd data from the device */
2640 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
2641 if (vpd_size <= 0) {
2642 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
2643 return;
2644 }
2645
2646 /* Get the Read only section */
2647 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
2648 if (i < 0) {
2649 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
2650 return;
2651 }
2652
2653 j = pci_vpd_lrdt_size(&vpd_data[i]);
2654 i += PCI_VPD_LRDT_TAG_SIZE;
2655 if (i + j > vpd_size)
2656 j = vpd_size - i;
2657
2658 /* Get the Part number */
2659 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
2660 if (i < 0) {
2661 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
2662 return;
2663 }
2664
2665 j = pci_vpd_info_field_size(&vpd_data[i]);
2666 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2667 if (i + j > vpd_size) {
2668 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
2669 return;
2670 }
2671
2672 netif_info(efx, drv, efx->net_dev,
2673 "Part Number : %.*s\n", j, &vpd_data[i]);
2674}
2675
2676
8ceee660
BH		 2677/* Main body of NIC initialisation
2678 * This is called at module load (or hotplug insertion, theoretically).
2679 */
2680static int efx_pci_probe_main(struct efx_nic *efx)
2681{
2682 int rc;
2683
2684 /* Do start-of-day initialisation */
2685 rc = efx_probe_all(efx);
2686 if (rc)
2687 goto fail1;
2688
e8f14992 2689 efx_init_napi(efx);
8ceee660 2690
ef2b90ee 2691 rc = efx->type->init(efx);
8ceee660 2692 if (rc) {
62776d03
BH		 2693 netif_err(efx, probe, efx->net_dev,
2694 "failed to initialise NIC\n");
278c0621 2695 goto fail3;
8ceee660
BH		 2696 }
2697
2698 rc = efx_init_port(efx);
2699 if (rc) {
62776d03
BH		 2700 netif_err(efx, probe, efx->net_dev,
2701 "failed to initialise port\n");
278c0621 2702 goto fail4;
8ceee660
BH		 2703 }
2704
152b6a62 2705 rc = efx_nic_init_interrupt(efx);
8ceee660 2706 if (rc)
278c0621 2707 goto fail5;
7f967c01 2708 efx_start_interrupts(efx, false);
8ceee660
BH		 2709
2710 return 0;
2711
278c0621 2712 fail5:
8ceee660 2713 efx_fini_port(efx);
8ceee660 2714 fail4:
ef2b90ee 2715 efx->type->fini(efx);
8ceee660
BH		 2716 fail3:
2717 efx_fini_napi(efx);
8ceee660
BH		 2718 efx_remove_all(efx);
2719 fail1:
2720 return rc;
2721}
2722
2723/* NIC initialisation
2724 *
2725 * This is called at module load (or hotplug insertion,
73ba7b68 2726 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH		 2727 * sets up and registers the network devices with the kernel and hooks
2728 * the interrupt service routine. It does not prepare the device for
2729 * transmission; this is left to the first time one of the network
2730 * interfaces is brought up (i.e. efx_net_open).
2731 */
87d1fc11 2732static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 2733 const struct pci_device_id *entry)
8ceee660 2734{
8ceee660
BH		 2735 struct net_device *net_dev;
2736 struct efx_nic *efx;
fadac6aa 2737 int rc;
8ceee660
BH		 2738
2739 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH		 2740 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2741 EFX_MAX_RX_QUEUES);
8ceee660
BH		 2742 if (!net_dev)
2743 return -ENOMEM;
adeb15aa
BH		 2744 efx = netdev_priv(net_dev);
2745 efx->type = (const struct efx_nic_type *) entry->driver_data;
2746 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
97bc5415 2747 NETIF_F_HIGHDMA | NETIF_F_TSO |
abfe9039 2748 NETIF_F_RXCSUM);
adeb15aa 2749 if (efx->type->offload_features & NETIF_F_V6_CSUM)
738a8f4b 2750 net_dev->features |= NETIF_F_TSO6;
28506563
BH		 2751 /* Mask for features that also apply to VLAN devices */
2752 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
abfe9039
BH		 2753 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2754 NETIF_F_RXCSUM);
2755 /* All offloads can be toggled */
2756 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
8ceee660 2757 pci_set_drvdata(pci_dev, efx);
62776d03 2758 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 2759 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH		 2760 if (rc)
2761 goto fail1;
2762
62776d03 2763 netif_info(efx, probe, efx->net_dev,
ff79c8ac 2764 "Solarflare NIC detected\n");
8ceee660 2765
460eeaa0
BH		 2766 efx_print_product_vpd(efx);
2767
8ceee660
BH		 2768 /* Set up basic I/O (BAR mappings etc) */
2769 rc = efx_init_io(efx);
2770 if (rc)
2771 goto fail2;
2772
fadac6aa 2773 rc = efx_pci_probe_main(efx);
fadac6aa
BH		 2774 if (rc)
2775 goto fail3;
8ceee660 2776
8ceee660
BH		 2777 rc = efx_register_netdev(efx);
2778 if (rc)
fadac6aa 2779 goto fail4;
8ceee660 2780
cd2d5b52
BH		 2781 rc = efx_sriov_init(efx);
2782 if (rc)
2783 netif_err(efx, probe, efx->net_dev,
2784 "SR-IOV can't be enabled rc %d\n", rc);
2785
62776d03 2786 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 2787
7c43161c 2788 /* Try to create MTDs, but allow this to fail */
a5211bb5 2789 rtnl_lock();
7c43161c 2790 rc = efx_mtd_probe(efx);
a5211bb5 2791 rtnl_unlock();
7c43161c
BH		 2792 if (rc)
2793 netif_warn(efx, probe, efx->net_dev,
2794 "failed to create MTDs (%d)\n", rc);
2795
626950db
AR		 2796 rc = pci_enable_pcie_error_reporting(pci_dev);
2797 if (rc && rc != -EINVAL)
2798 netif_warn(efx, probe, efx->net_dev,
2799 "pci_enable_pcie_error_reporting failed (%d)\n", rc);
2800
8ceee660
BH		 2801 return 0;
2802
8ceee660 2803 fail4:
fadac6aa 2804 efx_pci_remove_main(efx);
8ceee660
BH		 2805 fail3:
2806 efx_fini_io(efx);
2807 fail2:
2808 efx_fini_struct(efx);
2809 fail1:
3de4e301 2810 pci_set_drvdata(pci_dev, NULL);
5e2a911c 2811 WARN_ON(rc > 0);
62776d03 2812 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH		 2813 free_netdev(net_dev);
2814 return rc;
2815}
2816
89c758fa
BH		 2817static int efx_pm_freeze(struct device *dev)
2818{
2819 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2820
61da026d
BH		 2821 rtnl_lock();
2822
6032fb56
BH		 2823 if (efx->state != STATE_DISABLED) {
2824 efx->state = STATE_UNINIT;
89c758fa 2825
c2f3b8e3 2826 efx_device_detach_sync(efx);
89c758fa 2827
6032fb56
BH		 2828 efx_stop_all(efx);
2829 efx_stop_interrupts(efx, false);
2830 }
89c758fa 2831
61da026d
BH		 2832 rtnl_unlock();
2833
89c758fa
BH		 2834 return 0;
2835}
2836
2837static int efx_pm_thaw(struct device *dev)
2838{
2839 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2840
61da026d
BH		 2841 rtnl_lock();
2842
6032fb56
BH		 2843 if (efx->state != STATE_DISABLED) {
2844 efx_start_interrupts(efx, false);
89c758fa 2845
6032fb56
BH		 2846 mutex_lock(&efx->mac_lock);
2847 efx->phy_op->reconfigure(efx);
2848 mutex_unlock(&efx->mac_lock);
89c758fa 2849
6032fb56 2850 efx_start_all(efx);
89c758fa 2851
6032fb56 2852 netif_device_attach(efx->net_dev);
89c758fa 2853
6032fb56 2854 efx->state = STATE_READY;
89c758fa 2855
6032fb56
BH		 2856 efx->type->resume_wol(efx);
2857 }
89c758fa 2858
61da026d
BH		 2859 rtnl_unlock();
2860
319ba649
SH		 2861 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2862 queue_work(reset_workqueue, &efx->reset_work);
2863
89c758fa
BH		 2864 return 0;
2865}
2866
2867static int efx_pm_poweroff(struct device *dev)
2868{
2869 struct pci_dev *pci_dev = to_pci_dev(dev);
2870 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2871
2872 efx->type->fini(efx);
2873
a7d529ae 2874 efx->reset_pending = 0;
89c758fa
BH		 2875
2876 pci_save_state(pci_dev);
2877 return pci_set_power_state(pci_dev, PCI_D3hot);
2878}
2879
2880/* Used for both resume and restore */
2881static int efx_pm_resume(struct device *dev)
2882{
2883 struct pci_dev *pci_dev = to_pci_dev(dev);
2884 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2885 int rc;
2886
2887 rc = pci_set_power_state(pci_dev, PCI_D0);
2888 if (rc)
2889 return rc;
2890 pci_restore_state(pci_dev);
2891 rc = pci_enable_device(pci_dev);
2892 if (rc)
2893 return rc;
2894 pci_set_master(efx->pci_dev);
2895 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2896 if (rc)
2897 return rc;
2898 rc = efx->type->init(efx);
2899 if (rc)
2900 return rc;
2901 efx_pm_thaw(dev);
2902 return 0;
2903}
2904
2905static int efx_pm_suspend(struct device *dev)
2906{
2907 int rc;
2908
2909 efx_pm_freeze(dev);
2910 rc = efx_pm_poweroff(dev);
2911 if (rc)
2912 efx_pm_resume(dev);
2913 return rc;
2914}
2915
18e83e4c 2916static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH		 2917 .suspend = efx_pm_suspend,
2918 .resume = efx_pm_resume,
2919 .freeze = efx_pm_freeze,
2920 .thaw = efx_pm_thaw,
2921 .poweroff = efx_pm_poweroff,
2922 .restore = efx_pm_resume,
2923};
2924
626950db
AR		 2925/* A PCI error affecting this device was detected.
2926 * At this point MMIO and DMA may be disabled.
2927 * Stop the software path and request a slot reset.
2928 */
2929pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
2930 enum pci_channel_state state)
2931{
2932 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2933 struct efx_nic *efx = pci_get_drvdata(pdev);
2934
2935 if (state == pci_channel_io_perm_failure)
2936 return PCI_ERS_RESULT_DISCONNECT;
2937
2938 rtnl_lock();
2939
2940 if (efx->state != STATE_DISABLED) {
2941 efx->state = STATE_RECOVERY;
2942 efx->reset_pending = 0;
2943
2944 efx_device_detach_sync(efx);
2945
2946 efx_stop_all(efx);
2947 efx_stop_interrupts(efx, false);
2948
2949 status = PCI_ERS_RESULT_NEED_RESET;
2950 } else {
2951 /* If the interface is disabled we don't want to do anything
2952 * with it.
2953 */
2954 status = PCI_ERS_RESULT_RECOVERED;
2955 }
2956
2957 rtnl_unlock();
2958
2959 pci_disable_device(pdev);
2960
2961 return status;
2962}
2963
2964/* Fake a successfull reset, which will be performed later in efx_io_resume. */
2965pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
2966{
2967 struct efx_nic *efx = pci_get_drvdata(pdev);
2968 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2969 int rc;
2970
2971 if (pci_enable_device(pdev)) {
2972 netif_err(efx, hw, efx->net_dev,
2973 "Cannot re-enable PCI device after reset.\n");
2974 status = PCI_ERS_RESULT_DISCONNECT;
2975 }
2976
2977 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
2978 if (rc) {
2979 netif_err(efx, hw, efx->net_dev,
2980 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
2981 /* Non-fatal error. Continue. */
2982 }
2983
2984 return status;
2985}
2986
2987/* Perform the actual reset and resume I/O operations. */
2988static void efx_io_resume(struct pci_dev *pdev)
2989{
2990 struct efx_nic *efx = pci_get_drvdata(pdev);
2991 int rc;
2992
2993 rtnl_lock();
2994
2995 if (efx->state == STATE_DISABLED)
2996 goto out;
2997
2998 rc = efx_reset(efx, RESET_TYPE_ALL);
2999 if (rc) {
3000 netif_err(efx, hw, efx->net_dev,
3001 "efx_reset failed after PCI error (%d)\n", rc);
3002 } else {
3003 efx->state = STATE_READY;
3004 netif_dbg(efx, hw, efx->net_dev,
3005 "Done resetting and resuming IO after PCI error.\n");
3006 }
3007
3008out:
3009 rtnl_unlock();
3010}
3011
3012/* For simplicity and reliability, we always require a slot reset and try to
3013 * reset the hardware when a pci error affecting the device is detected.
3014 * We leave both the link_reset and mmio_enabled callback unimplemented:
3015 * with our request for slot reset the mmio_enabled callback will never be
3016 * called, and the link_reset callback is not used by AER or EEH mechanisms.
3017 */
3018static struct pci_error_handlers efx_err_handlers = {
3019 .error_detected = efx_io_error_detected,
3020 .slot_reset = efx_io_slot_reset,
3021 .resume = efx_io_resume,
3022};
3023
8ceee660 3024static struct pci_driver efx_pci_driver = {
c5d5f5fd 3025 .name = KBUILD_MODNAME,
8ceee660
BH		 3026 .id_table = efx_pci_table,
3027 .probe = efx_pci_probe,
3028 .remove = efx_pci_remove,
89c758fa 3029 .driver.pm = &efx_pm_ops,
626950db 3030 .err_handler = &efx_err_handlers,
8ceee660
BH		 3031};
3032
3033/**************************************************************************
3034 *
3035 * Kernel module interface
3036 *
3037 *************************************************************************/
3038
3039module_param(interrupt_mode, uint, 0444);
3040MODULE_PARM_DESC(interrupt_mode,
3041 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
3042
3043static int __init efx_init_module(void)
3044{
3045 int rc;
3046
3047 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
3048
3049 rc = register_netdevice_notifier(&efx_netdev_notifier);
3050 if (rc)
3051 goto err_notifier;
3052
cd2d5b52
BH		 3053 rc = efx_init_sriov();
3054 if (rc)
3055 goto err_sriov;
3056
1ab00629
SH		 3057 reset_workqueue = create_singlethread_workqueue("sfc_reset");
3058 if (!reset_workqueue) {
3059 rc = -ENOMEM;
3060 goto err_reset;
3061 }
8ceee660
BH		 3062
3063 rc = pci_register_driver(&efx_pci_driver);
3064 if (rc < 0)
3065 goto err_pci;
3066
3067 return 0;
3068
3069 err_pci:
1ab00629
SH		 3070 destroy_workqueue(reset_workqueue);
3071 err_reset:
cd2d5b52
BH		 3072 efx_fini_sriov();
3073 err_sriov:
8ceee660
BH		 3074 unregister_netdevice_notifier(&efx_netdev_notifier);
3075 err_notifier:
3076 return rc;
3077}
3078
3079static void __exit efx_exit_module(void)
3080{
3081 printk(KERN_INFO "Solarflare NET driver unloading\n");
3082
3083 pci_unregister_driver(&efx_pci_driver);
1ab00629 3084 destroy_workqueue(reset_workqueue);
cd2d5b52 3085 efx_fini_sriov();
8ceee660
BH		 3086 unregister_netdevice_notifier(&efx_netdev_notifier);
3087
3088}
3089
3090module_init(efx_init_module);
3091module_exit(efx_exit_module);
3092
906bb26c
BH		 3093MODULE_AUTHOR("Solarflare Communications and "
3094 "Michael Brown <mbrown@fensystems.co.uk>");
8ceee660
BH		 3095MODULE_DESCRIPTION("Solarflare Communications network driver");
3096MODULE_LICENSE("GPL");
3097MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux kernel - Deliverables
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