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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
64d8ad6d | 24 | #include <linux/cpu_rmap.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
dd40781e | 28 | #include "selftest.h" |
8ceee660 | 29 | |
8880f4ec | 30 | #include "mcdi.h" |
fd371e32 | 31 | #include "workarounds.h" |
8880f4ec | 32 | |
c459302d BH |
33 | /************************************************************************** |
34 | * | |
35 | * Type name strings | |
36 | * | |
37 | ************************************************************************** | |
38 | */ | |
39 | ||
40 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
41 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 42 | const char *const efx_loopback_mode_names[] = { |
c459302d | 43 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 44 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
45 | [LOOPBACK_GMAC] = "GMAC", |
46 | [LOOPBACK_XGMII] = "XGMII", | |
47 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
48 | [LOOPBACK_XAUI] = "XAUI", |
49 | [LOOPBACK_GMII] = "GMII", | |
50 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
51 | [LOOPBACK_XGBR] = "XGBR", |
52 | [LOOPBACK_XFI] = "XFI", | |
53 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
54 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
55 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
56 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
57 | [LOOPBACK_GPHY] = "GPHY", |
58 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
59 | [LOOPBACK_PCS] = "PCS", |
60 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
61 | [LOOPBACK_XPORT] = "XPORT", |
62 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 63 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
64 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
65 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 66 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
67 | [LOOPBACK_XFI_WS] = "XFI_WS", |
68 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 69 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
70 | }; |
71 | ||
c459302d | 72 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 73 | const char *const efx_reset_type_names[] = { |
c459302d BH |
74 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
75 | [RESET_TYPE_ALL] = "ALL", | |
76 | [RESET_TYPE_WORLD] = "WORLD", | |
77 | [RESET_TYPE_DISABLE] = "DISABLE", | |
78 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
79 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
80 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
81 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
83 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 84 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
85 | }; |
86 | ||
8ceee660 BH |
87 | #define EFX_MAX_MTU (9 * 1024) |
88 | ||
1ab00629 SH |
89 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
90 | * queued onto this work queue. This is not a per-nic work queue, because | |
91 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
92 | */ | |
93 | static struct workqueue_struct *reset_workqueue; | |
94 | ||
8ceee660 BH |
95 | /************************************************************************** |
96 | * | |
97 | * Configurable values | |
98 | * | |
99 | *************************************************************************/ | |
100 | ||
8ceee660 BH |
101 | /* |
102 | * Use separate channels for TX and RX events | |
103 | * | |
28b581ab NT |
104 | * Set this to 1 to use separate channels for TX and RX. It allows us |
105 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 106 | * |
28b581ab | 107 | * This is only used in MSI-X interrupt mode |
8ceee660 | 108 | */ |
28b581ab | 109 | static unsigned int separate_tx_channels; |
8313aca3 | 110 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
111 | MODULE_PARM_DESC(separate_tx_channels, |
112 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
113 | |
114 | /* This is the weight assigned to each of the (per-channel) virtual | |
115 | * NAPI devices. | |
116 | */ | |
117 | static int napi_weight = 64; | |
118 | ||
119 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
120 | * monitor. On Falcon-based NICs, this will: |
121 | * - Check the on-board hardware monitor; | |
122 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 123 | */ |
d215697f | 124 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 125 | |
8ceee660 BH |
126 | /* Initial interrupt moderation settings. They can be modified after |
127 | * module load with ethtool. | |
128 | * | |
129 | * The default for RX should strike a balance between increasing the | |
130 | * round-trip latency and reducing overhead. | |
131 | */ | |
132 | static unsigned int rx_irq_mod_usec = 60; | |
133 | ||
134 | /* Initial interrupt moderation settings. They can be modified after | |
135 | * module load with ethtool. | |
136 | * | |
137 | * This default is chosen to ensure that a 10G link does not go idle | |
138 | * while a TX queue is stopped after it has become full. A queue is | |
139 | * restarted when it drops below half full. The time this takes (assuming | |
140 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
141 | * 512 / 3 * 1.2 = 205 usec. | |
142 | */ | |
143 | static unsigned int tx_irq_mod_usec = 150; | |
144 | ||
145 | /* This is the first interrupt mode to try out of: | |
146 | * 0 => MSI-X | |
147 | * 1 => MSI | |
148 | * 2 => legacy | |
149 | */ | |
150 | static unsigned int interrupt_mode; | |
151 | ||
152 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
153 | * i.e. the number of CPUs among which we may distribute simultaneous | |
154 | * interrupt handling. | |
155 | * | |
156 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 157 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
158 | */ |
159 | static unsigned int rss_cpus; | |
160 | module_param(rss_cpus, uint, 0444); | |
161 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
162 | ||
84ae48fe BH |
163 | static int phy_flash_cfg; |
164 | module_param(phy_flash_cfg, int, 0644); | |
165 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
166 | ||
e7bed9c8 | 167 | static unsigned irq_adapt_low_thresh = 8000; |
6fb70fd1 BH |
168 | module_param(irq_adapt_low_thresh, uint, 0644); |
169 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
170 | "Threshold score for reducing IRQ moderation"); | |
171 | ||
e7bed9c8 | 172 | static unsigned irq_adapt_high_thresh = 16000; |
6fb70fd1 BH |
173 | module_param(irq_adapt_high_thresh, uint, 0644); |
174 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
175 | "Threshold score for increasing IRQ moderation"); | |
176 | ||
62776d03 BH |
177 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
178 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
179 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
180 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
181 | module_param(debug, uint, 0); | |
182 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
183 | ||
8ceee660 BH |
184 | /************************************************************************** |
185 | * | |
186 | * Utility functions and prototypes | |
187 | * | |
188 | *************************************************************************/ | |
4642610c | 189 | |
7f967c01 BH |
190 | static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq); |
191 | static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq); | |
192 | static void efx_remove_channel(struct efx_channel *channel); | |
4642610c | 193 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 194 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 195 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 196 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 197 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 198 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
199 | static void efx_fini_struct(struct efx_nic *efx); |
200 | static void efx_start_all(struct efx_nic *efx); | |
201 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
202 | |
203 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
204 | do { \ | |
332c1ce9 BH |
205 | if ((efx->state == STATE_RUNNING) || \ |
206 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
207 | ASSERT_RTNL(); \ |
208 | } while (0) | |
209 | ||
210 | /************************************************************************** | |
211 | * | |
212 | * Event queue processing | |
213 | * | |
214 | *************************************************************************/ | |
215 | ||
216 | /* Process channel's event queue | |
217 | * | |
218 | * This function is responsible for processing the event queue of a | |
219 | * single channel. The caller must guarantee that this function will | |
220 | * never be concurrently called more than once on the same channel, | |
221 | * though different channels may be being processed concurrently. | |
222 | */ | |
fa236e18 | 223 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 224 | { |
fa236e18 | 225 | int spent; |
8ceee660 | 226 | |
9f2cb71c | 227 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 228 | return 0; |
8ceee660 | 229 | |
fa236e18 | 230 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
231 | if (spent && efx_channel_has_rx_queue(channel)) { |
232 | struct efx_rx_queue *rx_queue = | |
233 | efx_channel_get_rx_queue(channel); | |
234 | ||
235 | /* Deliver last RX packet. */ | |
236 | if (channel->rx_pkt) { | |
237 | __efx_rx_packet(channel, channel->rx_pkt); | |
238 | channel->rx_pkt = NULL; | |
239 | } | |
9f2cb71c BH |
240 | if (rx_queue->enabled) { |
241 | efx_rx_strategy(channel); | |
242 | efx_fast_push_rx_descriptors(rx_queue); | |
243 | } | |
8ceee660 BH |
244 | } |
245 | ||
fa236e18 | 246 | return spent; |
8ceee660 BH |
247 | } |
248 | ||
249 | /* Mark channel as finished processing | |
250 | * | |
251 | * Note that since we will not receive further interrupts for this | |
252 | * channel before we finish processing and call the eventq_read_ack() | |
253 | * method, there is no need to use the interrupt hold-off timers. | |
254 | */ | |
255 | static inline void efx_channel_processed(struct efx_channel *channel) | |
256 | { | |
5b9e207c BH |
257 | /* The interrupt handler for this channel may set work_pending |
258 | * as soon as we acknowledge the events we've seen. Make sure | |
259 | * it's cleared before then. */ | |
dc8cfa55 | 260 | channel->work_pending = false; |
5b9e207c BH |
261 | smp_wmb(); |
262 | ||
152b6a62 | 263 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
264 | } |
265 | ||
266 | /* NAPI poll handler | |
267 | * | |
268 | * NAPI guarantees serialisation of polls of the same device, which | |
269 | * provides the guarantee required by efx_process_channel(). | |
270 | */ | |
271 | static int efx_poll(struct napi_struct *napi, int budget) | |
272 | { | |
273 | struct efx_channel *channel = | |
274 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 275 | struct efx_nic *efx = channel->efx; |
fa236e18 | 276 | int spent; |
8ceee660 | 277 | |
62776d03 BH |
278 | netif_vdbg(efx, intr, efx->net_dev, |
279 | "channel %d NAPI poll executing on CPU %d\n", | |
280 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 281 | |
fa236e18 | 282 | spent = efx_process_channel(channel, budget); |
8ceee660 | 283 | |
fa236e18 | 284 | if (spent < budget) { |
9d9a6973 | 285 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
286 | efx->irq_rx_adaptive && |
287 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
288 | if (unlikely(channel->irq_mod_score < |
289 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
290 | if (channel->irq_moderation > 1) { |
291 | channel->irq_moderation -= 1; | |
ef2b90ee | 292 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 293 | } |
6fb70fd1 BH |
294 | } else if (unlikely(channel->irq_mod_score > |
295 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
296 | if (channel->irq_moderation < |
297 | efx->irq_rx_moderation) { | |
298 | channel->irq_moderation += 1; | |
ef2b90ee | 299 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 300 | } |
6fb70fd1 | 301 | } |
6fb70fd1 BH |
302 | channel->irq_count = 0; |
303 | channel->irq_mod_score = 0; | |
304 | } | |
305 | ||
64d8ad6d BH |
306 | efx_filter_rfs_expire(channel); |
307 | ||
8ceee660 | 308 | /* There is no race here; although napi_disable() will |
288379f0 | 309 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
310 | * since efx_channel_processed() will have no effect if |
311 | * interrupts have already been disabled. | |
312 | */ | |
288379f0 | 313 | napi_complete(napi); |
8ceee660 BH |
314 | efx_channel_processed(channel); |
315 | } | |
316 | ||
fa236e18 | 317 | return spent; |
8ceee660 BH |
318 | } |
319 | ||
320 | /* Process the eventq of the specified channel immediately on this CPU | |
321 | * | |
322 | * Disable hardware generated interrupts, wait for any existing | |
323 | * processing to finish, then directly poll (and ack ) the eventq. | |
324 | * Finally reenable NAPI and interrupts. | |
325 | * | |
d4fabcc8 BH |
326 | * This is for use only during a loopback self-test. It must not |
327 | * deliver any packets up the stack as this can result in deadlock. | |
8ceee660 BH |
328 | */ |
329 | void efx_process_channel_now(struct efx_channel *channel) | |
330 | { | |
331 | struct efx_nic *efx = channel->efx; | |
332 | ||
8313aca3 | 333 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 | 334 | BUG_ON(!channel->enabled); |
d4fabcc8 | 335 | BUG_ON(!efx->loopback_selftest); |
8ceee660 BH |
336 | |
337 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 338 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 339 | if (efx->legacy_irq) { |
8ceee660 | 340 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
341 | efx->legacy_irq_enabled = false; |
342 | } | |
64ee3120 | 343 | if (channel->irq) |
8ceee660 BH |
344 | synchronize_irq(channel->irq); |
345 | ||
346 | /* Wait for any NAPI processing to complete */ | |
347 | napi_disable(&channel->napi_str); | |
348 | ||
349 | /* Poll the channel */ | |
ecc910f5 | 350 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
351 | |
352 | /* Ack the eventq. This may cause an interrupt to be generated | |
353 | * when they are reenabled */ | |
354 | efx_channel_processed(channel); | |
355 | ||
356 | napi_enable(&channel->napi_str); | |
94dec6a2 BH |
357 | if (efx->legacy_irq) |
358 | efx->legacy_irq_enabled = true; | |
152b6a62 | 359 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
360 | } |
361 | ||
362 | /* Create event queue | |
363 | * Event queue memory allocations are done only once. If the channel | |
364 | * is reset, the memory buffer will be reused; this guards against | |
365 | * errors during channel reset and also simplifies interrupt handling. | |
366 | */ | |
367 | static int efx_probe_eventq(struct efx_channel *channel) | |
368 | { | |
ecc910f5 SH |
369 | struct efx_nic *efx = channel->efx; |
370 | unsigned long entries; | |
371 | ||
86ee5302 | 372 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 373 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 374 | |
ecc910f5 SH |
375 | /* Build an event queue with room for one event per tx and rx buffer, |
376 | * plus some extra for link state events and MCDI completions. */ | |
377 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
378 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
379 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
380 | ||
152b6a62 | 381 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
382 | } |
383 | ||
384 | /* Prepare channel's event queue */ | |
bc3c90a2 | 385 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 386 | { |
62776d03 BH |
387 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
388 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
389 | |
390 | channel->eventq_read_ptr = 0; | |
391 | ||
152b6a62 | 392 | efx_nic_init_eventq(channel); |
8ceee660 BH |
393 | } |
394 | ||
9f2cb71c BH |
395 | /* Enable event queue processing and NAPI */ |
396 | static void efx_start_eventq(struct efx_channel *channel) | |
397 | { | |
398 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
399 | "chan %d start event queue\n", channel->channel); | |
400 | ||
401 | /* The interrupt handler for this channel may set work_pending | |
402 | * as soon as we enable it. Make sure it's cleared before | |
403 | * then. Similarly, make sure it sees the enabled flag set. | |
404 | */ | |
405 | channel->work_pending = false; | |
406 | channel->enabled = true; | |
407 | smp_wmb(); | |
408 | ||
409 | napi_enable(&channel->napi_str); | |
410 | efx_nic_eventq_read_ack(channel); | |
411 | } | |
412 | ||
413 | /* Disable event queue processing and NAPI */ | |
414 | static void efx_stop_eventq(struct efx_channel *channel) | |
415 | { | |
416 | if (!channel->enabled) | |
417 | return; | |
418 | ||
419 | napi_disable(&channel->napi_str); | |
420 | channel->enabled = false; | |
421 | } | |
422 | ||
8ceee660 BH |
423 | static void efx_fini_eventq(struct efx_channel *channel) |
424 | { | |
62776d03 BH |
425 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
426 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 427 | |
152b6a62 | 428 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
429 | } |
430 | ||
431 | static void efx_remove_eventq(struct efx_channel *channel) | |
432 | { | |
62776d03 BH |
433 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
434 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 435 | |
152b6a62 | 436 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
437 | } |
438 | ||
439 | /************************************************************************** | |
440 | * | |
441 | * Channel handling | |
442 | * | |
443 | *************************************************************************/ | |
444 | ||
7f967c01 | 445 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
446 | static struct efx_channel * |
447 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
448 | { | |
449 | struct efx_channel *channel; | |
450 | struct efx_rx_queue *rx_queue; | |
451 | struct efx_tx_queue *tx_queue; | |
452 | int j; | |
453 | ||
7f967c01 BH |
454 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
455 | if (!channel) | |
456 | return NULL; | |
4642610c | 457 | |
7f967c01 BH |
458 | channel->efx = efx; |
459 | channel->channel = i; | |
460 | channel->type = &efx_default_channel_type; | |
4642610c | 461 | |
7f967c01 BH |
462 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
463 | tx_queue = &channel->tx_queue[j]; | |
464 | tx_queue->efx = efx; | |
465 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
466 | tx_queue->channel = channel; | |
467 | } | |
4642610c | 468 | |
7f967c01 BH |
469 | rx_queue = &channel->rx_queue; |
470 | rx_queue->efx = efx; | |
471 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
472 | (unsigned long)rx_queue); | |
4642610c | 473 | |
7f967c01 BH |
474 | return channel; |
475 | } | |
476 | ||
477 | /* Allocate and initialise a channel structure, copying parameters | |
478 | * (but not resources) from an old channel structure. | |
479 | */ | |
480 | static struct efx_channel * | |
481 | efx_copy_channel(const struct efx_channel *old_channel) | |
482 | { | |
483 | struct efx_channel *channel; | |
484 | struct efx_rx_queue *rx_queue; | |
485 | struct efx_tx_queue *tx_queue; | |
486 | int j; | |
4642610c | 487 | |
7f967c01 BH |
488 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
489 | if (!channel) | |
490 | return NULL; | |
491 | ||
492 | *channel = *old_channel; | |
493 | ||
494 | channel->napi_dev = NULL; | |
495 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 496 | |
7f967c01 BH |
497 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
498 | tx_queue = &channel->tx_queue[j]; | |
499 | if (tx_queue->channel) | |
4642610c | 500 | tx_queue->channel = channel; |
7f967c01 BH |
501 | tx_queue->buffer = NULL; |
502 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
503 | } |
504 | ||
4642610c | 505 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
506 | rx_queue->buffer = NULL; |
507 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
508 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
509 | (unsigned long)rx_queue); | |
510 | ||
511 | return channel; | |
512 | } | |
513 | ||
8ceee660 BH |
514 | static int efx_probe_channel(struct efx_channel *channel) |
515 | { | |
516 | struct efx_tx_queue *tx_queue; | |
517 | struct efx_rx_queue *rx_queue; | |
518 | int rc; | |
519 | ||
62776d03 BH |
520 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
521 | "creating channel %d\n", channel->channel); | |
8ceee660 | 522 | |
7f967c01 BH |
523 | rc = channel->type->pre_probe(channel); |
524 | if (rc) | |
525 | goto fail; | |
526 | ||
8ceee660 BH |
527 | rc = efx_probe_eventq(channel); |
528 | if (rc) | |
7f967c01 | 529 | goto fail; |
8ceee660 BH |
530 | |
531 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
532 | rc = efx_probe_tx_queue(tx_queue); | |
533 | if (rc) | |
7f967c01 | 534 | goto fail; |
8ceee660 BH |
535 | } |
536 | ||
537 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
538 | rc = efx_probe_rx_queue(rx_queue); | |
539 | if (rc) | |
7f967c01 | 540 | goto fail; |
8ceee660 BH |
541 | } |
542 | ||
543 | channel->n_rx_frm_trunc = 0; | |
544 | ||
545 | return 0; | |
546 | ||
7f967c01 BH |
547 | fail: |
548 | efx_remove_channel(channel); | |
8ceee660 BH |
549 | return rc; |
550 | } | |
551 | ||
7f967c01 BH |
552 | static void |
553 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
554 | { | |
555 | struct efx_nic *efx = channel->efx; | |
556 | const char *type; | |
557 | int number; | |
558 | ||
559 | number = channel->channel; | |
560 | if (efx->tx_channel_offset == 0) { | |
561 | type = ""; | |
562 | } else if (channel->channel < efx->tx_channel_offset) { | |
563 | type = "-rx"; | |
564 | } else { | |
565 | type = "-tx"; | |
566 | number -= efx->tx_channel_offset; | |
567 | } | |
568 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
569 | } | |
8ceee660 | 570 | |
56536e9c BH |
571 | static void efx_set_channel_names(struct efx_nic *efx) |
572 | { | |
573 | struct efx_channel *channel; | |
56536e9c | 574 | |
7f967c01 BH |
575 | efx_for_each_channel(channel, efx) |
576 | channel->type->get_name(channel, | |
577 | efx->channel_name[channel->channel], | |
578 | sizeof(efx->channel_name[0])); | |
56536e9c BH |
579 | } |
580 | ||
4642610c BH |
581 | static int efx_probe_channels(struct efx_nic *efx) |
582 | { | |
583 | struct efx_channel *channel; | |
584 | int rc; | |
585 | ||
586 | /* Restart special buffer allocation */ | |
587 | efx->next_buffer_table = 0; | |
588 | ||
c92aaff1 BH |
589 | /* Probe channels in reverse, so that any 'extra' channels |
590 | * use the start of the buffer table. This allows the traffic | |
591 | * channels to be resized without moving them or wasting the | |
592 | * entries before them. | |
593 | */ | |
594 | efx_for_each_channel_rev(channel, efx) { | |
4642610c BH |
595 | rc = efx_probe_channel(channel); |
596 | if (rc) { | |
597 | netif_err(efx, probe, efx->net_dev, | |
598 | "failed to create channel %d\n", | |
599 | channel->channel); | |
600 | goto fail; | |
601 | } | |
602 | } | |
603 | efx_set_channel_names(efx); | |
604 | ||
605 | return 0; | |
606 | ||
607 | fail: | |
608 | efx_remove_channels(efx); | |
609 | return rc; | |
610 | } | |
611 | ||
8ceee660 BH |
612 | /* Channels are shutdown and reinitialised whilst the NIC is running |
613 | * to propagate configuration changes (mtu, checksum offload), or | |
614 | * to clear hardware error conditions | |
615 | */ | |
9f2cb71c | 616 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 BH |
617 | { |
618 | struct efx_tx_queue *tx_queue; | |
619 | struct efx_rx_queue *rx_queue; | |
620 | struct efx_channel *channel; | |
8ceee660 | 621 | |
f7f13b0b BH |
622 | /* Calculate the rx buffer allocation parameters required to |
623 | * support the current MTU, including padding for header | |
624 | * alignment and overruns. | |
625 | */ | |
626 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
627 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 628 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 629 | efx->type->rx_buffer_padding); |
62b330ba SH |
630 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
631 | sizeof(struct efx_rx_page_state)); | |
8ceee660 | 632 | |
14bf718f BH |
633 | /* We must keep at least one descriptor in a TX ring empty. |
634 | * We could avoid this when the queue size does not exactly | |
635 | * match the hardware ring size, but it's not that important. | |
636 | * Therefore we stop the queue when one more skb might fill | |
637 | * the ring completely. We wake it when half way back to | |
638 | * empty. | |
639 | */ | |
640 | efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); | |
641 | efx->txq_wake_thresh = efx->txq_stop_thresh / 2; | |
642 | ||
8ceee660 BH |
643 | /* Initialise the channels */ |
644 | efx_for_each_channel(channel, efx) { | |
bc3c90a2 BH |
645 | efx_for_each_channel_tx_queue(tx_queue, channel) |
646 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
647 | |
648 | /* The rx buffer allocation strategy is MTU dependent */ | |
649 | efx_rx_strategy(channel); | |
650 | ||
9f2cb71c | 651 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 652 | efx_init_rx_queue(rx_queue); |
9f2cb71c BH |
653 | efx_nic_generate_fill_event(rx_queue); |
654 | } | |
8ceee660 BH |
655 | |
656 | WARN_ON(channel->rx_pkt != NULL); | |
657 | efx_rx_strategy(channel); | |
658 | } | |
8ceee660 | 659 | |
9f2cb71c BH |
660 | if (netif_device_present(efx->net_dev)) |
661 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
662 | } |
663 | ||
9f2cb71c | 664 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
665 | { |
666 | struct efx_channel *channel; | |
667 | struct efx_tx_queue *tx_queue; | |
668 | struct efx_rx_queue *rx_queue; | |
3dca9d2d | 669 | struct pci_dev *dev = efx->pci_dev; |
6bc5d3a9 | 670 | int rc; |
8ceee660 BH |
671 | |
672 | EFX_ASSERT_RESET_SERIALISED(efx); | |
673 | BUG_ON(efx->port_enabled); | |
674 | ||
3dca9d2d SH |
675 | /* Only perform flush if dma is enabled */ |
676 | if (dev->is_busmaster) { | |
677 | rc = efx_nic_flush_queues(efx); | |
678 | ||
679 | if (rc && EFX_WORKAROUND_7803(efx)) { | |
680 | /* Schedule a reset to recover from the flush failure. The | |
681 | * descriptor caches reference memory we're about to free, | |
682 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
683 | * the MACs because of the pending reset. */ | |
684 | netif_err(efx, drv, efx->net_dev, | |
685 | "Resetting to recover from flush failure\n"); | |
686 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
687 | } else if (rc) { | |
688 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); | |
689 | } else { | |
690 | netif_dbg(efx, drv, efx->net_dev, | |
691 | "successfully flushed all queues\n"); | |
692 | } | |
fd371e32 | 693 | } |
6bc5d3a9 | 694 | |
8ceee660 | 695 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
696 | /* RX packet processing is pipelined, so wait for the |
697 | * NAPI handler to complete. At least event queue 0 | |
698 | * might be kept active by non-data events, so don't | |
699 | * use napi_synchronize() but actually disable NAPI | |
700 | * temporarily. | |
701 | */ | |
702 | if (efx_channel_has_rx_queue(channel)) { | |
703 | efx_stop_eventq(channel); | |
704 | efx_start_eventq(channel); | |
705 | } | |
8ceee660 BH |
706 | |
707 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
708 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 709 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 710 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
711 | } |
712 | } | |
713 | ||
714 | static void efx_remove_channel(struct efx_channel *channel) | |
715 | { | |
716 | struct efx_tx_queue *tx_queue; | |
717 | struct efx_rx_queue *rx_queue; | |
718 | ||
62776d03 BH |
719 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
720 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
721 | |
722 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
723 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 724 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
725 | efx_remove_tx_queue(tx_queue); |
726 | efx_remove_eventq(channel); | |
8ceee660 BH |
727 | } |
728 | ||
4642610c BH |
729 | static void efx_remove_channels(struct efx_nic *efx) |
730 | { | |
731 | struct efx_channel *channel; | |
732 | ||
733 | efx_for_each_channel(channel, efx) | |
734 | efx_remove_channel(channel); | |
735 | } | |
736 | ||
737 | int | |
738 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
739 | { | |
740 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
741 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 BH |
742 | unsigned i, next_buffer_table = 0; |
743 | int rc = 0; | |
744 | ||
745 | /* Not all channels should be reallocated. We must avoid | |
746 | * reallocating their buffer table entries. | |
747 | */ | |
748 | efx_for_each_channel(channel, efx) { | |
749 | struct efx_rx_queue *rx_queue; | |
750 | struct efx_tx_queue *tx_queue; | |
751 | ||
752 | if (channel->type->copy) | |
753 | continue; | |
754 | next_buffer_table = max(next_buffer_table, | |
755 | channel->eventq.index + | |
756 | channel->eventq.entries); | |
757 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
758 | next_buffer_table = max(next_buffer_table, | |
759 | rx_queue->rxd.index + | |
760 | rx_queue->rxd.entries); | |
761 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
762 | next_buffer_table = max(next_buffer_table, | |
763 | tx_queue->txd.index + | |
764 | tx_queue->txd.entries); | |
765 | } | |
4642610c BH |
766 | |
767 | efx_stop_all(efx); | |
7f967c01 | 768 | efx_stop_interrupts(efx, true); |
4642610c | 769 | |
7f967c01 | 770 | /* Clone channels (where possible) */ |
4642610c BH |
771 | memset(other_channel, 0, sizeof(other_channel)); |
772 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
773 | channel = efx->channel[i]; |
774 | if (channel->type->copy) | |
775 | channel = channel->type->copy(channel); | |
4642610c BH |
776 | if (!channel) { |
777 | rc = -ENOMEM; | |
778 | goto out; | |
779 | } | |
780 | other_channel[i] = channel; | |
781 | } | |
782 | ||
783 | /* Swap entry counts and channel pointers */ | |
784 | old_rxq_entries = efx->rxq_entries; | |
785 | old_txq_entries = efx->txq_entries; | |
786 | efx->rxq_entries = rxq_entries; | |
787 | efx->txq_entries = txq_entries; | |
788 | for (i = 0; i < efx->n_channels; i++) { | |
789 | channel = efx->channel[i]; | |
790 | efx->channel[i] = other_channel[i]; | |
791 | other_channel[i] = channel; | |
792 | } | |
793 | ||
7f967c01 BH |
794 | /* Restart buffer table allocation */ |
795 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 796 | |
e8f14992 | 797 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
798 | channel = efx->channel[i]; |
799 | if (!channel->type->copy) | |
800 | continue; | |
801 | rc = efx_probe_channel(channel); | |
802 | if (rc) | |
803 | goto rollback; | |
804 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 805 | } |
7f967c01 | 806 | |
4642610c | 807 | out: |
7f967c01 BH |
808 | /* Destroy unused channel structures */ |
809 | for (i = 0; i < efx->n_channels; i++) { | |
810 | channel = other_channel[i]; | |
811 | if (channel && channel->type->copy) { | |
812 | efx_fini_napi_channel(channel); | |
813 | efx_remove_channel(channel); | |
814 | kfree(channel); | |
815 | } | |
816 | } | |
4642610c | 817 | |
7f967c01 | 818 | efx_start_interrupts(efx, true); |
4642610c BH |
819 | efx_start_all(efx); |
820 | return rc; | |
821 | ||
822 | rollback: | |
823 | /* Swap back */ | |
824 | efx->rxq_entries = old_rxq_entries; | |
825 | efx->txq_entries = old_txq_entries; | |
826 | for (i = 0; i < efx->n_channels; i++) { | |
827 | channel = efx->channel[i]; | |
828 | efx->channel[i] = other_channel[i]; | |
829 | other_channel[i] = channel; | |
830 | } | |
831 | goto out; | |
832 | } | |
833 | ||
90d683af | 834 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 835 | { |
90d683af | 836 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
837 | } |
838 | ||
7f967c01 BH |
839 | static const struct efx_channel_type efx_default_channel_type = { |
840 | .pre_probe = efx_channel_dummy_op_int, | |
841 | .get_name = efx_get_channel_name, | |
842 | .copy = efx_copy_channel, | |
843 | .keep_eventq = false, | |
844 | }; | |
845 | ||
846 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
847 | { | |
848 | return 0; | |
849 | } | |
850 | ||
8ceee660 BH |
851 | /************************************************************************** |
852 | * | |
853 | * Port handling | |
854 | * | |
855 | **************************************************************************/ | |
856 | ||
857 | /* This ensures that the kernel is kept informed (via | |
858 | * netif_carrier_on/off) of the link status, and also maintains the | |
859 | * link status's stop on the port's TX queue. | |
860 | */ | |
fdaa9aed | 861 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 862 | { |
eb50c0d6 BH |
863 | struct efx_link_state *link_state = &efx->link_state; |
864 | ||
8ceee660 BH |
865 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
866 | * that no events are triggered between unregister_netdev() and the | |
867 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
868 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
869 | if (!netif_running(efx->net_dev)) | |
870 | return; | |
871 | ||
eb50c0d6 | 872 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
873 | efx->n_link_state_changes++; |
874 | ||
eb50c0d6 | 875 | if (link_state->up) |
8ceee660 BH |
876 | netif_carrier_on(efx->net_dev); |
877 | else | |
878 | netif_carrier_off(efx->net_dev); | |
879 | } | |
880 | ||
881 | /* Status message for kernel log */ | |
2aa9ef11 | 882 | if (link_state->up) |
62776d03 BH |
883 | netif_info(efx, link, efx->net_dev, |
884 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
885 | link_state->speed, link_state->fd ? "full" : "half", | |
886 | efx->net_dev->mtu, | |
887 | (efx->promiscuous ? " [PROMISC]" : "")); | |
2aa9ef11 | 888 | else |
62776d03 | 889 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
890 | } |
891 | ||
d3245b28 BH |
892 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
893 | { | |
894 | efx->link_advertising = advertising; | |
895 | if (advertising) { | |
896 | if (advertising & ADVERTISED_Pause) | |
897 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
898 | else | |
899 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
900 | if (advertising & ADVERTISED_Asym_Pause) | |
901 | efx->wanted_fc ^= EFX_FC_TX; | |
902 | } | |
903 | } | |
904 | ||
b5626946 | 905 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
906 | { |
907 | efx->wanted_fc = wanted_fc; | |
908 | if (efx->link_advertising) { | |
909 | if (wanted_fc & EFX_FC_RX) | |
910 | efx->link_advertising |= (ADVERTISED_Pause | | |
911 | ADVERTISED_Asym_Pause); | |
912 | else | |
913 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
914 | ADVERTISED_Asym_Pause); | |
915 | if (wanted_fc & EFX_FC_TX) | |
916 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
917 | } | |
918 | } | |
919 | ||
115122af BH |
920 | static void efx_fini_port(struct efx_nic *efx); |
921 | ||
d3245b28 BH |
922 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
923 | * the MAC appropriately. All other PHY configuration changes are pushed | |
924 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
925 | * through efx_monitor(). | |
926 | * | |
927 | * Callers must hold the mac_lock | |
928 | */ | |
929 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 930 | { |
d3245b28 BH |
931 | enum efx_phy_mode phy_mode; |
932 | int rc; | |
8ceee660 | 933 | |
d3245b28 | 934 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 935 | |
0fca8c97 | 936 | /* Serialise the promiscuous flag with efx_set_rx_mode. */ |
73ba7b68 BH |
937 | netif_addr_lock_bh(efx->net_dev); |
938 | netif_addr_unlock_bh(efx->net_dev); | |
a816f75a | 939 | |
d3245b28 BH |
940 | /* Disable PHY transmit in mac level loopbacks */ |
941 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
942 | if (LOOPBACK_INTERNAL(efx)) |
943 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
944 | else | |
945 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 946 | |
d3245b28 | 947 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 948 | |
d3245b28 BH |
949 | if (rc) |
950 | efx->phy_mode = phy_mode; | |
177dfcd8 | 951 | |
d3245b28 | 952 | return rc; |
8ceee660 BH |
953 | } |
954 | ||
955 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
956 | * disabled. */ | |
d3245b28 | 957 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 958 | { |
d3245b28 BH |
959 | int rc; |
960 | ||
8ceee660 BH |
961 | EFX_ASSERT_RESET_SERIALISED(efx); |
962 | ||
963 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 964 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 965 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
966 | |
967 | return rc; | |
8ceee660 BH |
968 | } |
969 | ||
8be4f3e6 BH |
970 | /* Asynchronous work item for changing MAC promiscuity and multicast |
971 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
972 | * MAC directly. */ | |
766ca0fa BH |
973 | static void efx_mac_work(struct work_struct *data) |
974 | { | |
975 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
976 | ||
977 | mutex_lock(&efx->mac_lock); | |
30b81cda | 978 | if (efx->port_enabled) |
710b208d | 979 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
980 | mutex_unlock(&efx->mac_lock); |
981 | } | |
982 | ||
8ceee660 BH |
983 | static int efx_probe_port(struct efx_nic *efx) |
984 | { | |
985 | int rc; | |
986 | ||
62776d03 | 987 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 988 | |
ff3b00a0 SH |
989 | if (phy_flash_cfg) |
990 | efx->phy_mode = PHY_MODE_SPECIAL; | |
991 | ||
ef2b90ee BH |
992 | /* Connect up MAC/PHY operations table */ |
993 | rc = efx->type->probe_port(efx); | |
8ceee660 | 994 | if (rc) |
e42de262 | 995 | return rc; |
8ceee660 | 996 | |
e332bcb3 BH |
997 | /* Initialise MAC address to permanent address */ |
998 | memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); | |
8ceee660 BH |
999 | |
1000 | return 0; | |
8ceee660 BH |
1001 | } |
1002 | ||
1003 | static int efx_init_port(struct efx_nic *efx) | |
1004 | { | |
1005 | int rc; | |
1006 | ||
62776d03 | 1007 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 1008 | |
1dfc5cea BH |
1009 | mutex_lock(&efx->mac_lock); |
1010 | ||
177dfcd8 | 1011 | rc = efx->phy_op->init(efx); |
8ceee660 | 1012 | if (rc) |
1dfc5cea | 1013 | goto fail1; |
8ceee660 | 1014 | |
dc8cfa55 | 1015 | efx->port_initialized = true; |
1dfc5cea | 1016 | |
d3245b28 BH |
1017 | /* Reconfigure the MAC before creating dma queues (required for |
1018 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 1019 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1020 | |
1021 | /* Ensure the PHY advertises the correct flow control settings */ | |
1022 | rc = efx->phy_op->reconfigure(efx); | |
1023 | if (rc) | |
1024 | goto fail2; | |
1025 | ||
1dfc5cea | 1026 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1027 | return 0; |
177dfcd8 | 1028 | |
1dfc5cea | 1029 | fail2: |
177dfcd8 | 1030 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1031 | fail1: |
1032 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1033 | return rc; |
8ceee660 BH |
1034 | } |
1035 | ||
8ceee660 BH |
1036 | static void efx_start_port(struct efx_nic *efx) |
1037 | { | |
62776d03 | 1038 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1039 | BUG_ON(efx->port_enabled); |
1040 | ||
1041 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1042 | efx->port_enabled = true; |
8be4f3e6 BH |
1043 | |
1044 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
1045 | * and then cancelled by efx_flush_all() */ | |
710b208d | 1046 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 1047 | |
8ceee660 BH |
1048 | mutex_unlock(&efx->mac_lock); |
1049 | } | |
1050 | ||
fdaa9aed | 1051 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
1052 | static void efx_stop_port(struct efx_nic *efx) |
1053 | { | |
62776d03 | 1054 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
1055 | |
1056 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1057 | efx->port_enabled = false; |
8ceee660 BH |
1058 | mutex_unlock(&efx->mac_lock); |
1059 | ||
1060 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1061 | netif_addr_lock_bh(efx->net_dev); |
1062 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
1063 | } |
1064 | ||
1065 | static void efx_fini_port(struct efx_nic *efx) | |
1066 | { | |
62776d03 | 1067 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1068 | |
1069 | if (!efx->port_initialized) | |
1070 | return; | |
1071 | ||
177dfcd8 | 1072 | efx->phy_op->fini(efx); |
dc8cfa55 | 1073 | efx->port_initialized = false; |
8ceee660 | 1074 | |
eb50c0d6 | 1075 | efx->link_state.up = false; |
8ceee660 BH |
1076 | efx_link_status_changed(efx); |
1077 | } | |
1078 | ||
1079 | static void efx_remove_port(struct efx_nic *efx) | |
1080 | { | |
62776d03 | 1081 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1082 | |
ef2b90ee | 1083 | efx->type->remove_port(efx); |
8ceee660 BH |
1084 | } |
1085 | ||
1086 | /************************************************************************** | |
1087 | * | |
1088 | * NIC handling | |
1089 | * | |
1090 | **************************************************************************/ | |
1091 | ||
1092 | /* This configures the PCI device to enable I/O and DMA. */ | |
1093 | static int efx_init_io(struct efx_nic *efx) | |
1094 | { | |
1095 | struct pci_dev *pci_dev = efx->pci_dev; | |
1096 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
1097 | int rc; | |
1098 | ||
62776d03 | 1099 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1100 | |
1101 | rc = pci_enable_device(pci_dev); | |
1102 | if (rc) { | |
62776d03 BH |
1103 | netif_err(efx, probe, efx->net_dev, |
1104 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1105 | goto fail1; |
1106 | } | |
1107 | ||
1108 | pci_set_master(pci_dev); | |
1109 | ||
1110 | /* Set the PCI DMA mask. Try all possibilities from our | |
1111 | * genuine mask down to 32 bits, because some architectures | |
1112 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1113 | * masks event though they reject 46 bit masks. | |
1114 | */ | |
1115 | while (dma_mask > 0x7fffffffUL) { | |
0e33d870 BH |
1116 | if (dma_supported(&pci_dev->dev, dma_mask)) { |
1117 | rc = dma_set_mask(&pci_dev->dev, dma_mask); | |
e9e01846 BH |
1118 | if (rc == 0) |
1119 | break; | |
1120 | } | |
8ceee660 BH |
1121 | dma_mask >>= 1; |
1122 | } | |
1123 | if (rc) { | |
62776d03 BH |
1124 | netif_err(efx, probe, efx->net_dev, |
1125 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1126 | goto fail2; |
1127 | } | |
62776d03 BH |
1128 | netif_dbg(efx, probe, efx->net_dev, |
1129 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
0e33d870 | 1130 | rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask); |
8ceee660 | 1131 | if (rc) { |
0e33d870 BH |
1132 | /* dma_set_coherent_mask() is not *allowed* to |
1133 | * fail with a mask that dma_set_mask() accepted, | |
8ceee660 BH |
1134 | * but just in case... |
1135 | */ | |
62776d03 BH |
1136 | netif_err(efx, probe, efx->net_dev, |
1137 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1138 | goto fail2; |
1139 | } | |
1140 | ||
dc803df8 BH |
1141 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1142 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1143 | if (rc) { |
62776d03 BH |
1144 | netif_err(efx, probe, efx->net_dev, |
1145 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1146 | rc = -EIO; |
1147 | goto fail3; | |
1148 | } | |
86c432ca BH |
1149 | efx->membase = ioremap_nocache(efx->membase_phys, |
1150 | efx->type->mem_map_size); | |
8ceee660 | 1151 | if (!efx->membase) { |
62776d03 BH |
1152 | netif_err(efx, probe, efx->net_dev, |
1153 | "could not map memory BAR at %llx+%x\n", | |
1154 | (unsigned long long)efx->membase_phys, | |
1155 | efx->type->mem_map_size); | |
8ceee660 BH |
1156 | rc = -ENOMEM; |
1157 | goto fail4; | |
1158 | } | |
62776d03 BH |
1159 | netif_dbg(efx, probe, efx->net_dev, |
1160 | "memory BAR at %llx+%x (virtual %p)\n", | |
1161 | (unsigned long long)efx->membase_phys, | |
1162 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1163 | |
1164 | return 0; | |
1165 | ||
1166 | fail4: | |
dc803df8 | 1167 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1168 | fail3: |
2c118e0f | 1169 | efx->membase_phys = 0; |
8ceee660 BH |
1170 | fail2: |
1171 | pci_disable_device(efx->pci_dev); | |
1172 | fail1: | |
1173 | return rc; | |
1174 | } | |
1175 | ||
1176 | static void efx_fini_io(struct efx_nic *efx) | |
1177 | { | |
62776d03 | 1178 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1179 | |
1180 | if (efx->membase) { | |
1181 | iounmap(efx->membase); | |
1182 | efx->membase = NULL; | |
1183 | } | |
1184 | ||
1185 | if (efx->membase_phys) { | |
dc803df8 | 1186 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1187 | efx->membase_phys = 0; |
8ceee660 BH |
1188 | } |
1189 | ||
1190 | pci_disable_device(efx->pci_dev); | |
1191 | } | |
1192 | ||
a9a52506 | 1193 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1194 | { |
cdb08f8f | 1195 | cpumask_var_t thread_mask; |
a16e5b24 | 1196 | unsigned int count; |
46123d04 | 1197 | int cpu; |
5b874e25 | 1198 | |
cd2d5b52 BH |
1199 | if (rss_cpus) { |
1200 | count = rss_cpus; | |
1201 | } else { | |
1202 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1203 | netif_warn(efx, probe, efx->net_dev, | |
1204 | "RSS disabled due to allocation failure\n"); | |
1205 | return 1; | |
1206 | } | |
46123d04 | 1207 | |
cd2d5b52 BH |
1208 | count = 0; |
1209 | for_each_online_cpu(cpu) { | |
1210 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1211 | ++count; | |
1212 | cpumask_or(thread_mask, thread_mask, | |
1213 | topology_thread_cpumask(cpu)); | |
1214 | } | |
1215 | } | |
1216 | ||
1217 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1218 | } |
1219 | ||
cd2d5b52 BH |
1220 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1221 | * table entries that are inaccessible to VFs | |
1222 | */ | |
1223 | if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1224 | count > efx_vf_size(efx)) { | |
1225 | netif_warn(efx, probe, efx->net_dev, | |
1226 | "Reducing number of RSS channels from %u to %u for " | |
1227 | "VF support. Increase vf-msix-limit to use more " | |
1228 | "channels on the PF.\n", | |
1229 | count, efx_vf_size(efx)); | |
1230 | count = efx_vf_size(efx); | |
46123d04 BH |
1231 | } |
1232 | ||
1233 | return count; | |
1234 | } | |
1235 | ||
64d8ad6d BH |
1236 | static int |
1237 | efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) | |
1238 | { | |
1239 | #ifdef CONFIG_RFS_ACCEL | |
a16e5b24 BH |
1240 | unsigned int i; |
1241 | int rc; | |
64d8ad6d BH |
1242 | |
1243 | efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); | |
1244 | if (!efx->net_dev->rx_cpu_rmap) | |
1245 | return -ENOMEM; | |
1246 | for (i = 0; i < efx->n_rx_channels; i++) { | |
1247 | rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, | |
1248 | xentries[i].vector); | |
1249 | if (rc) { | |
1250 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
1251 | efx->net_dev->rx_cpu_rmap = NULL; | |
1252 | return rc; | |
1253 | } | |
1254 | } | |
1255 | #endif | |
1256 | return 0; | |
1257 | } | |
1258 | ||
46123d04 BH |
1259 | /* Probe the number and type of interrupts we are able to obtain, and |
1260 | * the resulting numbers of channels and RX queues. | |
1261 | */ | |
64d8ad6d | 1262 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1263 | { |
a16e5b24 BH |
1264 | unsigned int max_channels = |
1265 | min(efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
7f967c01 BH |
1266 | unsigned int extra_channels = 0; |
1267 | unsigned int i, j; | |
a16e5b24 | 1268 | int rc; |
8ceee660 | 1269 | |
7f967c01 BH |
1270 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1271 | if (efx->extra_channel_type[i]) | |
1272 | ++extra_channels; | |
1273 | ||
8ceee660 | 1274 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1275 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1276 | unsigned int n_channels; |
aa6ef27e | 1277 | |
a9a52506 | 1278 | n_channels = efx_wanted_parallelism(efx); |
a4900ac9 BH |
1279 | if (separate_tx_channels) |
1280 | n_channels *= 2; | |
7f967c01 | 1281 | n_channels += extra_channels; |
a4900ac9 | 1282 | n_channels = min(n_channels, max_channels); |
8ceee660 | 1283 | |
a4900ac9 | 1284 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1285 | xentries[i].entry = i; |
a4900ac9 | 1286 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1287 | if (rc > 0) { |
62776d03 BH |
1288 | netif_err(efx, drv, efx->net_dev, |
1289 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1290 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1291 | netif_err(efx, drv, efx->net_dev, |
1292 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1293 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1294 | n_channels = rc; | |
8ceee660 | 1295 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1296 | n_channels); |
8ceee660 BH |
1297 | } |
1298 | ||
1299 | if (rc == 0) { | |
a4900ac9 | 1300 | efx->n_channels = n_channels; |
7f967c01 BH |
1301 | if (n_channels > extra_channels) |
1302 | n_channels -= extra_channels; | |
a4900ac9 | 1303 | if (separate_tx_channels) { |
7f967c01 BH |
1304 | efx->n_tx_channels = max(n_channels / 2, 1U); |
1305 | efx->n_rx_channels = max(n_channels - | |
1306 | efx->n_tx_channels, | |
1307 | 1U); | |
a4900ac9 | 1308 | } else { |
7f967c01 BH |
1309 | efx->n_tx_channels = n_channels; |
1310 | efx->n_rx_channels = n_channels; | |
a4900ac9 | 1311 | } |
64d8ad6d BH |
1312 | rc = efx_init_rx_cpu_rmap(efx, xentries); |
1313 | if (rc) { | |
1314 | pci_disable_msix(efx->pci_dev); | |
1315 | return rc; | |
1316 | } | |
7f967c01 | 1317 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1318 | efx_get_channel(efx, i)->irq = |
1319 | xentries[i].vector; | |
8ceee660 BH |
1320 | } else { |
1321 | /* Fall back to single channel MSI */ | |
1322 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1323 | netif_err(efx, drv, efx->net_dev, |
1324 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1325 | } |
1326 | } | |
1327 | ||
1328 | /* Try single interrupt MSI */ | |
1329 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1330 | efx->n_channels = 1; |
a4900ac9 BH |
1331 | efx->n_rx_channels = 1; |
1332 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1333 | rc = pci_enable_msi(efx->pci_dev); |
1334 | if (rc == 0) { | |
f7d12cdc | 1335 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1336 | } else { |
62776d03 BH |
1337 | netif_err(efx, drv, efx->net_dev, |
1338 | "could not enable MSI\n"); | |
8ceee660 BH |
1339 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1340 | } | |
1341 | } | |
1342 | ||
1343 | /* Assume legacy interrupts */ | |
1344 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1345 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1346 | efx->n_rx_channels = 1; |
1347 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1348 | efx->legacy_irq = efx->pci_dev->irq; |
1349 | } | |
64d8ad6d | 1350 | |
7f967c01 BH |
1351 | /* Assign extra channels if possible */ |
1352 | j = efx->n_channels; | |
1353 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1354 | if (!efx->extra_channel_type[i]) | |
1355 | continue; | |
1356 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1357 | efx->n_channels <= extra_channels) { | |
1358 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1359 | } else { | |
1360 | --j; | |
1361 | efx_get_channel(efx, j)->type = | |
1362 | efx->extra_channel_type[i]; | |
1363 | } | |
1364 | } | |
1365 | ||
cd2d5b52 | 1366 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
3132d282 | 1367 | efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ? |
cd2d5b52 BH |
1368 | efx->n_rx_channels : efx_vf_size(efx)); |
1369 | ||
64d8ad6d | 1370 | return 0; |
8ceee660 BH |
1371 | } |
1372 | ||
9f2cb71c | 1373 | /* Enable interrupts, then probe and start the event queues */ |
7f967c01 | 1374 | static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq) |
9f2cb71c BH |
1375 | { |
1376 | struct efx_channel *channel; | |
1377 | ||
1378 | if (efx->legacy_irq) | |
1379 | efx->legacy_irq_enabled = true; | |
1380 | efx_nic_enable_interrupts(efx); | |
1381 | ||
1382 | efx_for_each_channel(channel, efx) { | |
7f967c01 BH |
1383 | if (!channel->type->keep_eventq || !may_keep_eventq) |
1384 | efx_init_eventq(channel); | |
9f2cb71c BH |
1385 | efx_start_eventq(channel); |
1386 | } | |
1387 | ||
1388 | efx_mcdi_mode_event(efx); | |
1389 | } | |
1390 | ||
7f967c01 | 1391 | static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq) |
9f2cb71c BH |
1392 | { |
1393 | struct efx_channel *channel; | |
1394 | ||
1395 | efx_mcdi_mode_poll(efx); | |
1396 | ||
1397 | efx_nic_disable_interrupts(efx); | |
1398 | if (efx->legacy_irq) { | |
1399 | synchronize_irq(efx->legacy_irq); | |
1400 | efx->legacy_irq_enabled = false; | |
1401 | } | |
1402 | ||
1403 | efx_for_each_channel(channel, efx) { | |
1404 | if (channel->irq) | |
1405 | synchronize_irq(channel->irq); | |
1406 | ||
1407 | efx_stop_eventq(channel); | |
7f967c01 BH |
1408 | if (!channel->type->keep_eventq || !may_keep_eventq) |
1409 | efx_fini_eventq(channel); | |
9f2cb71c BH |
1410 | } |
1411 | } | |
1412 | ||
8ceee660 BH |
1413 | static void efx_remove_interrupts(struct efx_nic *efx) |
1414 | { | |
1415 | struct efx_channel *channel; | |
1416 | ||
1417 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1418 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1419 | channel->irq = 0; |
1420 | pci_disable_msi(efx->pci_dev); | |
1421 | pci_disable_msix(efx->pci_dev); | |
1422 | ||
1423 | /* Remove legacy interrupt */ | |
1424 | efx->legacy_irq = 0; | |
1425 | } | |
1426 | ||
8831da7b | 1427 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1428 | { |
602a5322 BH |
1429 | struct efx_channel *channel; |
1430 | struct efx_tx_queue *tx_queue; | |
1431 | ||
97653431 | 1432 | efx->tx_channel_offset = |
a4900ac9 | 1433 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 BH |
1434 | |
1435 | /* We need to adjust the TX queue numbers if we have separate | |
1436 | * RX-only and TX-only channels. | |
1437 | */ | |
1438 | efx_for_each_channel(channel, efx) { | |
1439 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1440 | tx_queue->queue -= (efx->tx_channel_offset * | |
1441 | EFX_TXQ_TYPES); | |
1442 | } | |
8ceee660 BH |
1443 | } |
1444 | ||
1445 | static int efx_probe_nic(struct efx_nic *efx) | |
1446 | { | |
765c9f46 | 1447 | size_t i; |
8ceee660 BH |
1448 | int rc; |
1449 | ||
62776d03 | 1450 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1451 | |
1452 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1453 | rc = efx->type->probe(efx); |
8ceee660 BH |
1454 | if (rc) |
1455 | return rc; | |
1456 | ||
a4900ac9 | 1457 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1458 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1459 | rc = efx_probe_interrupts(efx); |
1460 | if (rc) | |
1461 | goto fail; | |
8ceee660 | 1462 | |
28e47c49 BH |
1463 | efx->type->dimension_resources(efx); |
1464 | ||
5d3a6fca BH |
1465 | if (efx->n_channels > 1) |
1466 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1467 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 | 1468 | efx->rx_indir_table[i] = |
cd2d5b52 | 1469 | ethtool_rxfh_indir_default(i, efx->rss_spread); |
5d3a6fca | 1470 | |
8831da7b | 1471 | efx_set_channels(efx); |
c4f4adc7 BH |
1472 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1473 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1474 | |
1475 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1476 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1477 | true); | |
8ceee660 BH |
1478 | |
1479 | return 0; | |
64d8ad6d BH |
1480 | |
1481 | fail: | |
1482 | efx->type->remove(efx); | |
1483 | return rc; | |
8ceee660 BH |
1484 | } |
1485 | ||
1486 | static void efx_remove_nic(struct efx_nic *efx) | |
1487 | { | |
62776d03 | 1488 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1489 | |
1490 | efx_remove_interrupts(efx); | |
ef2b90ee | 1491 | efx->type->remove(efx); |
8ceee660 BH |
1492 | } |
1493 | ||
1494 | /************************************************************************** | |
1495 | * | |
1496 | * NIC startup/shutdown | |
1497 | * | |
1498 | *************************************************************************/ | |
1499 | ||
1500 | static int efx_probe_all(struct efx_nic *efx) | |
1501 | { | |
8ceee660 BH |
1502 | int rc; |
1503 | ||
8ceee660 BH |
1504 | rc = efx_probe_nic(efx); |
1505 | if (rc) { | |
62776d03 | 1506 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1507 | goto fail1; |
1508 | } | |
1509 | ||
8ceee660 BH |
1510 | rc = efx_probe_port(efx); |
1511 | if (rc) { | |
62776d03 | 1512 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1513 | goto fail2; |
1514 | } | |
1515 | ||
7e6d06f0 BH |
1516 | BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); |
1517 | if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { | |
1518 | rc = -EINVAL; | |
1519 | goto fail3; | |
1520 | } | |
ecc910f5 | 1521 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1522 | |
64eebcfd BH |
1523 | rc = efx_probe_filters(efx); |
1524 | if (rc) { | |
1525 | netif_err(efx, probe, efx->net_dev, | |
1526 | "failed to create filter tables\n"); | |
7f967c01 | 1527 | goto fail3; |
64eebcfd BH |
1528 | } |
1529 | ||
7f967c01 BH |
1530 | rc = efx_probe_channels(efx); |
1531 | if (rc) | |
1532 | goto fail4; | |
1533 | ||
8ceee660 BH |
1534 | return 0; |
1535 | ||
64eebcfd | 1536 | fail4: |
7f967c01 | 1537 | efx_remove_filters(efx); |
8ceee660 | 1538 | fail3: |
8ceee660 BH |
1539 | efx_remove_port(efx); |
1540 | fail2: | |
1541 | efx_remove_nic(efx); | |
1542 | fail1: | |
1543 | return rc; | |
1544 | } | |
1545 | ||
9f2cb71c BH |
1546 | /* Called after previous invocation(s) of efx_stop_all, restarts the port, |
1547 | * kernel transmit queues and NAPI processing, and ensures that the port is | |
1548 | * scheduled to be reconfigured. This function is safe to call multiple | |
1549 | * times when the NIC is in any state. | |
1550 | */ | |
8ceee660 BH |
1551 | static void efx_start_all(struct efx_nic *efx) |
1552 | { | |
8ceee660 BH |
1553 | EFX_ASSERT_RESET_SERIALISED(efx); |
1554 | ||
1555 | /* Check that it is appropriate to restart the interface. All | |
1556 | * of these flags are safe to read under just the rtnl lock */ | |
1557 | if (efx->port_enabled) | |
1558 | return; | |
1559 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1560 | return; | |
73ba7b68 | 1561 | if (!netif_running(efx->net_dev)) |
8ceee660 BH |
1562 | return; |
1563 | ||
8ceee660 | 1564 | efx_start_port(efx); |
9f2cb71c | 1565 | efx_start_datapath(efx); |
8880f4ec | 1566 | |
78c1f0a0 SH |
1567 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1568 | * event driven), we have to poll the PHY because after an event queue | |
1569 | * flush, we could have a missed a link state change */ | |
1570 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1571 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1572 | efx_monitor_interval); | |
78c1f0a0 SH |
1573 | } else { |
1574 | mutex_lock(&efx->mac_lock); | |
1575 | if (efx->phy_op->poll(efx)) | |
1576 | efx_link_status_changed(efx); | |
1577 | mutex_unlock(&efx->mac_lock); | |
1578 | } | |
55edc6e6 | 1579 | |
ef2b90ee | 1580 | efx->type->start_stats(efx); |
8ceee660 BH |
1581 | } |
1582 | ||
1583 | /* Flush all delayed work. Should only be called when no more delayed work | |
1584 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1585 | * since we're holding the rtnl_lock at this point. */ | |
1586 | static void efx_flush_all(struct efx_nic *efx) | |
1587 | { | |
dd40781e | 1588 | /* Make sure the hardware monitor and event self-test are stopped */ |
8ceee660 | 1589 | cancel_delayed_work_sync(&efx->monitor_work); |
dd40781e | 1590 | efx_selftest_async_cancel(efx); |
8ceee660 | 1591 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1592 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1593 | } |
1594 | ||
1595 | /* Quiesce hardware and software without bringing the link down. | |
1596 | * Safe to call multiple times, when the nic and interface is in any | |
1597 | * state. The caller is guaranteed to subsequently be in a position | |
1598 | * to modify any hardware and software state they see fit without | |
1599 | * taking locks. */ | |
1600 | static void efx_stop_all(struct efx_nic *efx) | |
1601 | { | |
8ceee660 BH |
1602 | EFX_ASSERT_RESET_SERIALISED(efx); |
1603 | ||
1604 | /* port_enabled can be read safely under the rtnl lock */ | |
1605 | if (!efx->port_enabled) | |
1606 | return; | |
1607 | ||
ef2b90ee | 1608 | efx->type->stop_stats(efx); |
8ceee660 BH |
1609 | efx_stop_port(efx); |
1610 | ||
fdaa9aed | 1611 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1612 | efx_flush_all(efx); |
1613 | ||
8ceee660 BH |
1614 | /* Stop the kernel transmit interface late, so the watchdog |
1615 | * timer isn't ticking over the flush */ | |
9f2cb71c BH |
1616 | netif_tx_disable(efx->net_dev); |
1617 | ||
1618 | efx_stop_datapath(efx); | |
8ceee660 BH |
1619 | } |
1620 | ||
1621 | static void efx_remove_all(struct efx_nic *efx) | |
1622 | { | |
4642610c | 1623 | efx_remove_channels(efx); |
7f967c01 | 1624 | efx_remove_filters(efx); |
8ceee660 BH |
1625 | efx_remove_port(efx); |
1626 | efx_remove_nic(efx); | |
1627 | } | |
1628 | ||
8ceee660 BH |
1629 | /************************************************************************** |
1630 | * | |
1631 | * Interrupt moderation | |
1632 | * | |
1633 | **************************************************************************/ | |
1634 | ||
cc180b69 | 1635 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1636 | { |
b548f976 BH |
1637 | if (usecs == 0) |
1638 | return 0; | |
cc180b69 | 1639 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1640 | return 1; /* never round down to 0 */ |
cc180b69 | 1641 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1642 | } |
1643 | ||
8ceee660 | 1644 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1645 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1646 | unsigned int rx_usecs, bool rx_adaptive, | |
1647 | bool rx_may_override_tx) | |
8ceee660 | 1648 | { |
f7d12cdc | 1649 | struct efx_channel *channel; |
cc180b69 BH |
1650 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1651 | efx->timer_quantum_ns, | |
1652 | 1000); | |
1653 | unsigned int tx_ticks; | |
1654 | unsigned int rx_ticks; | |
8ceee660 BH |
1655 | |
1656 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1657 | ||
cc180b69 | 1658 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1659 | return -EINVAL; |
1660 | ||
cc180b69 BH |
1661 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1662 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1663 | ||
9e393b30 BH |
1664 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1665 | !rx_may_override_tx) { | |
1666 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1667 | "RX and TX IRQ moderation must be equal\n"); | |
1668 | return -EINVAL; | |
1669 | } | |
1670 | ||
6fb70fd1 | 1671 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1672 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1673 | efx_for_each_channel(channel, efx) { |
525da907 | 1674 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1675 | channel->irq_moderation = rx_ticks; |
525da907 | 1676 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1677 | channel->irq_moderation = tx_ticks; |
1678 | } | |
9e393b30 BH |
1679 | |
1680 | return 0; | |
8ceee660 BH |
1681 | } |
1682 | ||
a0c4faf5 BH |
1683 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1684 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1685 | { | |
cc180b69 BH |
1686 | /* We must round up when converting ticks to microseconds |
1687 | * because we round down when converting the other way. | |
1688 | */ | |
1689 | ||
a0c4faf5 | 1690 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1691 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1692 | efx->timer_quantum_ns, | |
1693 | 1000); | |
a0c4faf5 BH |
1694 | |
1695 | /* If channels are shared between RX and TX, so is IRQ | |
1696 | * moderation. Otherwise, IRQ moderation is the same for all | |
1697 | * TX channels and is not adaptive. | |
1698 | */ | |
1699 | if (efx->tx_channel_offset == 0) | |
1700 | *tx_usecs = *rx_usecs; | |
1701 | else | |
cc180b69 | 1702 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1703 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1704 | efx->timer_quantum_ns, |
1705 | 1000); | |
a0c4faf5 BH |
1706 | } |
1707 | ||
8ceee660 BH |
1708 | /************************************************************************** |
1709 | * | |
1710 | * Hardware monitor | |
1711 | * | |
1712 | **************************************************************************/ | |
1713 | ||
e254c274 | 1714 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1715 | static void efx_monitor(struct work_struct *data) |
1716 | { | |
1717 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1718 | monitor_work.work); | |
8ceee660 | 1719 | |
62776d03 BH |
1720 | netif_vdbg(efx, timer, efx->net_dev, |
1721 | "hardware monitor executing on CPU %d\n", | |
1722 | raw_smp_processor_id()); | |
ef2b90ee | 1723 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1724 | |
8ceee660 BH |
1725 | /* If the mac_lock is already held then it is likely a port |
1726 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1727 | * most of the work of monitor() anyway. */ |
1728 | if (mutex_trylock(&efx->mac_lock)) { | |
1729 | if (efx->port_enabled) | |
1730 | efx->type->monitor(efx); | |
1731 | mutex_unlock(&efx->mac_lock); | |
1732 | } | |
8ceee660 | 1733 | |
8ceee660 BH |
1734 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1735 | efx_monitor_interval); | |
1736 | } | |
1737 | ||
1738 | /************************************************************************** | |
1739 | * | |
1740 | * ioctls | |
1741 | * | |
1742 | *************************************************************************/ | |
1743 | ||
1744 | /* Net device ioctl | |
1745 | * Context: process, rtnl_lock() held. | |
1746 | */ | |
1747 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1748 | { | |
767e468c | 1749 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1750 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1751 | |
1752 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1753 | ||
68e7f45e BH |
1754 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1755 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1756 | (data->phy_id & 0xfc00) == 0x0400) | |
1757 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1758 | ||
1759 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1760 | } |
1761 | ||
1762 | /************************************************************************** | |
1763 | * | |
1764 | * NAPI interface | |
1765 | * | |
1766 | **************************************************************************/ | |
1767 | ||
7f967c01 BH |
1768 | static void efx_init_napi_channel(struct efx_channel *channel) |
1769 | { | |
1770 | struct efx_nic *efx = channel->efx; | |
1771 | ||
1772 | channel->napi_dev = efx->net_dev; | |
1773 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
1774 | efx_poll, napi_weight); | |
1775 | } | |
1776 | ||
e8f14992 | 1777 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1778 | { |
1779 | struct efx_channel *channel; | |
8ceee660 | 1780 | |
7f967c01 BH |
1781 | efx_for_each_channel(channel, efx) |
1782 | efx_init_napi_channel(channel); | |
e8f14992 BH |
1783 | } |
1784 | ||
1785 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1786 | { | |
1787 | if (channel->napi_dev) | |
1788 | netif_napi_del(&channel->napi_str); | |
1789 | channel->napi_dev = NULL; | |
8ceee660 BH |
1790 | } |
1791 | ||
1792 | static void efx_fini_napi(struct efx_nic *efx) | |
1793 | { | |
1794 | struct efx_channel *channel; | |
1795 | ||
e8f14992 BH |
1796 | efx_for_each_channel(channel, efx) |
1797 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1798 | } |
1799 | ||
1800 | /************************************************************************** | |
1801 | * | |
1802 | * Kernel netpoll interface | |
1803 | * | |
1804 | *************************************************************************/ | |
1805 | ||
1806 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1807 | ||
1808 | /* Although in the common case interrupts will be disabled, this is not | |
1809 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1810 | * so no locking is required. | |
1811 | */ | |
1812 | static void efx_netpoll(struct net_device *net_dev) | |
1813 | { | |
767e468c | 1814 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1815 | struct efx_channel *channel; |
1816 | ||
64ee3120 | 1817 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1818 | efx_schedule_channel(channel); |
1819 | } | |
1820 | ||
1821 | #endif | |
1822 | ||
1823 | /************************************************************************** | |
1824 | * | |
1825 | * Kernel net device interface | |
1826 | * | |
1827 | *************************************************************************/ | |
1828 | ||
1829 | /* Context: process, rtnl_lock() held. */ | |
1830 | static int efx_net_open(struct net_device *net_dev) | |
1831 | { | |
767e468c | 1832 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1833 | EFX_ASSERT_RESET_SERIALISED(efx); |
1834 | ||
62776d03 BH |
1835 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1836 | raw_smp_processor_id()); | |
8ceee660 | 1837 | |
f4bd954e BH |
1838 | if (efx->state == STATE_DISABLED) |
1839 | return -EIO; | |
f8b87c17 BH |
1840 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1841 | return -EBUSY; | |
8880f4ec BH |
1842 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1843 | return -EIO; | |
f8b87c17 | 1844 | |
78c1f0a0 SH |
1845 | /* Notify the kernel of the link state polled during driver load, |
1846 | * before the monitor starts running */ | |
1847 | efx_link_status_changed(efx); | |
1848 | ||
8ceee660 | 1849 | efx_start_all(efx); |
dd40781e | 1850 | efx_selftest_async_start(efx); |
8ceee660 BH |
1851 | return 0; |
1852 | } | |
1853 | ||
1854 | /* Context: process, rtnl_lock() held. | |
1855 | * Note that the kernel will ignore our return code; this method | |
1856 | * should really be a void. | |
1857 | */ | |
1858 | static int efx_net_stop(struct net_device *net_dev) | |
1859 | { | |
767e468c | 1860 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1861 | |
62776d03 BH |
1862 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1863 | raw_smp_processor_id()); | |
8ceee660 | 1864 | |
f4bd954e BH |
1865 | if (efx->state != STATE_DISABLED) { |
1866 | /* Stop the device and flush all the channels */ | |
1867 | efx_stop_all(efx); | |
f4bd954e | 1868 | } |
8ceee660 BH |
1869 | |
1870 | return 0; | |
1871 | } | |
1872 | ||
5b9e207c | 1873 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
1874 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
1875 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 1876 | { |
767e468c | 1877 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1878 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1879 | |
55edc6e6 | 1880 | spin_lock_bh(&efx->stats_lock); |
1cb34522 | 1881 | |
ef2b90ee | 1882 | efx->type->update_stats(efx); |
8ceee660 BH |
1883 | |
1884 | stats->rx_packets = mac_stats->rx_packets; | |
1885 | stats->tx_packets = mac_stats->tx_packets; | |
1886 | stats->rx_bytes = mac_stats->rx_bytes; | |
1887 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1888 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1889 | stats->multicast = mac_stats->rx_multicast; |
1890 | stats->collisions = mac_stats->tx_collision; | |
1891 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1892 | mac_stats->rx_length_error); | |
8ceee660 BH |
1893 | stats->rx_crc_errors = mac_stats->rx_bad; |
1894 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1895 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1896 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1897 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1898 | ||
1899 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1900 | stats->rx_crc_errors + |
1901 | stats->rx_frame_errors + | |
8ceee660 BH |
1902 | mac_stats->rx_symbol_error); |
1903 | stats->tx_errors = (stats->tx_window_errors + | |
1904 | mac_stats->tx_bad); | |
1905 | ||
1cb34522 BH |
1906 | spin_unlock_bh(&efx->stats_lock); |
1907 | ||
8ceee660 BH |
1908 | return stats; |
1909 | } | |
1910 | ||
1911 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1912 | static void efx_watchdog(struct net_device *net_dev) | |
1913 | { | |
767e468c | 1914 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1915 | |
62776d03 BH |
1916 | netif_err(efx, tx_err, efx->net_dev, |
1917 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1918 | efx->port_enabled); | |
8ceee660 | 1919 | |
739bb23d | 1920 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1921 | } |
1922 | ||
1923 | ||
1924 | /* Context: process, rtnl_lock() held. */ | |
1925 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1926 | { | |
767e468c | 1927 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1928 | |
1929 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1930 | ||
1931 | if (new_mtu > EFX_MAX_MTU) | |
1932 | return -EINVAL; | |
1933 | ||
1934 | efx_stop_all(efx); | |
1935 | ||
62776d03 | 1936 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 1937 | |
d3245b28 BH |
1938 | mutex_lock(&efx->mac_lock); |
1939 | /* Reconfigure the MAC before enabling the dma queues so that | |
1940 | * the RX buffers don't overflow */ | |
8ceee660 | 1941 | net_dev->mtu = new_mtu; |
710b208d | 1942 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1943 | mutex_unlock(&efx->mac_lock); |
1944 | ||
8ceee660 | 1945 | efx_start_all(efx); |
6c8eef4a | 1946 | return 0; |
8ceee660 BH |
1947 | } |
1948 | ||
1949 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1950 | { | |
767e468c | 1951 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1952 | struct sockaddr *addr = data; |
1953 | char *new_addr = addr->sa_data; | |
1954 | ||
1955 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1956 | ||
1957 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1958 | netif_err(efx, drv, efx->net_dev, |
1959 | "invalid ethernet MAC address requested: %pM\n", | |
1960 | new_addr); | |
504f9b5a | 1961 | return -EADDRNOTAVAIL; |
8ceee660 BH |
1962 | } |
1963 | ||
1964 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
cd2d5b52 | 1965 | efx_sriov_mac_address_changed(efx); |
8ceee660 BH |
1966 | |
1967 | /* Reconfigure the MAC */ | |
d3245b28 | 1968 | mutex_lock(&efx->mac_lock); |
710b208d | 1969 | efx->type->reconfigure_mac(efx); |
d3245b28 | 1970 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
1971 | |
1972 | return 0; | |
1973 | } | |
1974 | ||
a816f75a | 1975 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 1976 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 1977 | { |
767e468c | 1978 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1979 | struct netdev_hw_addr *ha; |
8ceee660 | 1980 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1981 | u32 crc; |
1982 | int bit; | |
8ceee660 | 1983 | |
8be4f3e6 | 1984 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1985 | |
1986 | /* Build multicast hash table */ | |
8be4f3e6 | 1987 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1988 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1989 | } else { | |
1990 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1991 | netdev_for_each_mc_addr(ha, net_dev) { |
1992 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1993 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1994 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1995 | } |
8ceee660 | 1996 | |
8be4f3e6 BH |
1997 | /* Broadcast packets go through the multicast hash filter. |
1998 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1999 | * so we always add bit 0xff to the mask. | |
2000 | */ | |
2001 | set_bit_le(0xff, mc_hash->byte); | |
2002 | } | |
a816f75a | 2003 | |
8be4f3e6 BH |
2004 | if (efx->port_enabled) |
2005 | queue_work(efx->workqueue, &efx->mac_work); | |
2006 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
2007 | } |
2008 | ||
c8f44aff | 2009 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
2010 | { |
2011 | struct efx_nic *efx = netdev_priv(net_dev); | |
2012 | ||
2013 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
2014 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
2015 | efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
2016 | ||
2017 | return 0; | |
2018 | } | |
2019 | ||
c3ecb9f3 SH |
2020 | static const struct net_device_ops efx_netdev_ops = { |
2021 | .ndo_open = efx_net_open, | |
2022 | .ndo_stop = efx_net_stop, | |
4472702e | 2023 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
2024 | .ndo_tx_timeout = efx_watchdog, |
2025 | .ndo_start_xmit = efx_hard_start_xmit, | |
2026 | .ndo_validate_addr = eth_validate_addr, | |
2027 | .ndo_do_ioctl = efx_ioctl, | |
2028 | .ndo_change_mtu = efx_change_mtu, | |
2029 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2030 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2031 | .ndo_set_features = efx_set_features, |
cd2d5b52 BH |
2032 | #ifdef CONFIG_SFC_SRIOV |
2033 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, | |
2034 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2035 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2036 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
2037 | #endif | |
c3ecb9f3 SH |
2038 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2039 | .ndo_poll_controller = efx_netpoll, | |
2040 | #endif | |
94b274bf | 2041 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
2042 | #ifdef CONFIG_RFS_ACCEL |
2043 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2044 | #endif | |
c3ecb9f3 SH |
2045 | }; |
2046 | ||
7dde596e BH |
2047 | static void efx_update_name(struct efx_nic *efx) |
2048 | { | |
2049 | strcpy(efx->name, efx->net_dev->name); | |
2050 | efx_mtd_rename(efx); | |
2051 | efx_set_channel_names(efx); | |
2052 | } | |
2053 | ||
8ceee660 BH |
2054 | static int efx_netdev_event(struct notifier_block *this, |
2055 | unsigned long event, void *ptr) | |
2056 | { | |
d3208b5e | 2057 | struct net_device *net_dev = ptr; |
8ceee660 | 2058 | |
7dde596e BH |
2059 | if (net_dev->netdev_ops == &efx_netdev_ops && |
2060 | event == NETDEV_CHANGENAME) | |
2061 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2062 | |
2063 | return NOTIFY_DONE; | |
2064 | } | |
2065 | ||
2066 | static struct notifier_block efx_netdev_notifier = { | |
2067 | .notifier_call = efx_netdev_event, | |
2068 | }; | |
2069 | ||
06d5e193 BH |
2070 | static ssize_t |
2071 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2072 | { | |
2073 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2074 | return sprintf(buf, "%d\n", efx->phy_type); | |
2075 | } | |
2076 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
2077 | ||
8ceee660 BH |
2078 | static int efx_register_netdev(struct efx_nic *efx) |
2079 | { | |
2080 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2081 | struct efx_channel *channel; |
8ceee660 BH |
2082 | int rc; |
2083 | ||
2084 | net_dev->watchdog_timeo = 5 * HZ; | |
2085 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 2086 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 | 2087 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
7e6d06f0 | 2088 | net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; |
8ceee660 | 2089 | |
7dde596e | 2090 | rtnl_lock(); |
aed0628d BH |
2091 | |
2092 | rc = dev_alloc_name(net_dev, net_dev->name); | |
2093 | if (rc < 0) | |
2094 | goto fail_locked; | |
7dde596e | 2095 | efx_update_name(efx); |
aed0628d BH |
2096 | |
2097 | rc = register_netdevice(net_dev); | |
2098 | if (rc) | |
2099 | goto fail_locked; | |
2100 | ||
c04bfc6b BH |
2101 | efx_for_each_channel(channel, efx) { |
2102 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2103 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2104 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2105 | } |
2106 | ||
aed0628d | 2107 | /* Always start with carrier off; PHY events will detect the link */ |
86ee5302 | 2108 | netif_carrier_off(net_dev); |
aed0628d | 2109 | |
7dde596e | 2110 | rtnl_unlock(); |
8ceee660 | 2111 | |
06d5e193 BH |
2112 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2113 | if (rc) { | |
62776d03 BH |
2114 | netif_err(efx, drv, efx->net_dev, |
2115 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2116 | goto fail_registered; |
2117 | } | |
2118 | ||
8ceee660 | 2119 | return 0; |
06d5e193 | 2120 | |
aed0628d BH |
2121 | fail_locked: |
2122 | rtnl_unlock(); | |
62776d03 | 2123 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
2124 | return rc; |
2125 | ||
06d5e193 BH |
2126 | fail_registered: |
2127 | unregister_netdev(net_dev); | |
2128 | return rc; | |
8ceee660 BH |
2129 | } |
2130 | ||
2131 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2132 | { | |
f7d12cdc | 2133 | struct efx_channel *channel; |
8ceee660 BH |
2134 | struct efx_tx_queue *tx_queue; |
2135 | ||
2136 | if (!efx->net_dev) | |
2137 | return; | |
2138 | ||
767e468c | 2139 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
2140 | |
2141 | /* Free up any skbs still remaining. This has to happen before | |
2142 | * we try to unregister the netdev as running their destructors | |
2143 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
2144 | efx_for_each_channel(channel, efx) { |
2145 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
2146 | efx_release_tx_buffers(tx_queue); | |
2147 | } | |
8ceee660 | 2148 | |
73ba7b68 BH |
2149 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
2150 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
2151 | unregister_netdev(efx->net_dev); | |
8ceee660 BH |
2152 | } |
2153 | ||
2154 | /************************************************************************** | |
2155 | * | |
2156 | * Device reset and suspend | |
2157 | * | |
2158 | **************************************************************************/ | |
2159 | ||
2467ca46 BH |
2160 | /* Tears down the entire software state and most of the hardware state |
2161 | * before reset. */ | |
d3245b28 | 2162 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2163 | { |
8ceee660 BH |
2164 | EFX_ASSERT_RESET_SERIALISED(efx); |
2165 | ||
2467ca46 BH |
2166 | efx_stop_all(efx); |
2167 | mutex_lock(&efx->mac_lock); | |
2168 | ||
7f967c01 | 2169 | efx_stop_interrupts(efx, false); |
4b988280 SH |
2170 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2171 | efx->phy_op->fini(efx); | |
ef2b90ee | 2172 | efx->type->fini(efx); |
8ceee660 BH |
2173 | } |
2174 | ||
2467ca46 BH |
2175 | /* This function will always ensure that the locks acquired in |
2176 | * efx_reset_down() are released. A failure return code indicates | |
2177 | * that we were unable to reinitialise the hardware, and the | |
2178 | * driver should be disabled. If ok is false, then the rx and tx | |
2179 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2180 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2181 | { |
2182 | int rc; | |
2183 | ||
2467ca46 | 2184 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2185 | |
ef2b90ee | 2186 | rc = efx->type->init(efx); |
8ceee660 | 2187 | if (rc) { |
62776d03 | 2188 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2189 | goto fail; |
8ceee660 BH |
2190 | } |
2191 | ||
eb9f6744 BH |
2192 | if (!ok) |
2193 | goto fail; | |
2194 | ||
4b988280 | 2195 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2196 | rc = efx->phy_op->init(efx); |
2197 | if (rc) | |
2198 | goto fail; | |
2199 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2200 | netif_err(efx, drv, efx->net_dev, |
2201 | "could not restore PHY settings\n"); | |
4b988280 SH |
2202 | } |
2203 | ||
710b208d | 2204 | efx->type->reconfigure_mac(efx); |
8ceee660 | 2205 | |
7f967c01 | 2206 | efx_start_interrupts(efx, false); |
64eebcfd | 2207 | efx_restore_filters(efx); |
cd2d5b52 | 2208 | efx_sriov_reset(efx); |
eb9f6744 | 2209 | |
eb9f6744 BH |
2210 | mutex_unlock(&efx->mac_lock); |
2211 | ||
2212 | efx_start_all(efx); | |
2213 | ||
2214 | return 0; | |
2215 | ||
2216 | fail: | |
2217 | efx->port_initialized = false; | |
2467ca46 BH |
2218 | |
2219 | mutex_unlock(&efx->mac_lock); | |
2220 | ||
8ceee660 BH |
2221 | return rc; |
2222 | } | |
2223 | ||
eb9f6744 BH |
2224 | /* Reset the NIC using the specified method. Note that the reset may |
2225 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2226 | * |
eb9f6744 | 2227 | * Caller must hold the rtnl_lock. |
8ceee660 | 2228 | */ |
eb9f6744 | 2229 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2230 | { |
eb9f6744 BH |
2231 | int rc, rc2; |
2232 | bool disabled; | |
8ceee660 | 2233 | |
62776d03 BH |
2234 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2235 | RESET_TYPE(method)); | |
8ceee660 | 2236 | |
e4abce85 | 2237 | netif_device_detach(efx->net_dev); |
d3245b28 | 2238 | efx_reset_down(efx, method); |
8ceee660 | 2239 | |
ef2b90ee | 2240 | rc = efx->type->reset(efx, method); |
8ceee660 | 2241 | if (rc) { |
62776d03 | 2242 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2243 | goto out; |
8ceee660 BH |
2244 | } |
2245 | ||
a7d529ae BH |
2246 | /* Clear flags for the scopes we covered. We assume the NIC and |
2247 | * driver are now quiescent so that there is no race here. | |
2248 | */ | |
2249 | efx->reset_pending &= -(1 << (method + 1)); | |
8ceee660 BH |
2250 | |
2251 | /* Reinitialise bus-mastering, which may have been turned off before | |
2252 | * the reset was scheduled. This is still appropriate, even in the | |
2253 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2254 | * can respond to requests. */ | |
2255 | pci_set_master(efx->pci_dev); | |
2256 | ||
eb9f6744 | 2257 | out: |
8ceee660 | 2258 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2259 | disabled = rc || method == RESET_TYPE_DISABLE; |
2260 | rc2 = efx_reset_up(efx, method, !disabled); | |
2261 | if (rc2) { | |
2262 | disabled = true; | |
2263 | if (!rc) | |
2264 | rc = rc2; | |
8ceee660 BH |
2265 | } |
2266 | ||
eb9f6744 | 2267 | if (disabled) { |
f49a4589 | 2268 | dev_close(efx->net_dev); |
62776d03 | 2269 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2270 | efx->state = STATE_DISABLED; |
f4bd954e | 2271 | } else { |
62776d03 | 2272 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2273 | netif_device_attach(efx->net_dev); |
f4bd954e | 2274 | } |
8ceee660 BH |
2275 | return rc; |
2276 | } | |
2277 | ||
2278 | /* The worker thread exists so that code that cannot sleep can | |
2279 | * schedule a reset for later. | |
2280 | */ | |
2281 | static void efx_reset_work(struct work_struct *data) | |
2282 | { | |
eb9f6744 | 2283 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
a7d529ae | 2284 | unsigned long pending = ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 2285 | |
a7d529ae | 2286 | if (!pending) |
319ba649 SH |
2287 | return; |
2288 | ||
eb9f6744 | 2289 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
a7d529ae | 2290 | * flags set so that efx_pci_probe_main will be retried */ |
eb9f6744 | 2291 | if (efx->state != STATE_RUNNING) { |
62776d03 BH |
2292 | netif_info(efx, drv, efx->net_dev, |
2293 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
2294 | return; |
2295 | } | |
2296 | ||
2297 | rtnl_lock(); | |
a7d529ae | 2298 | (void)efx_reset(efx, fls(pending) - 1); |
eb9f6744 | 2299 | rtnl_unlock(); |
8ceee660 BH |
2300 | } |
2301 | ||
2302 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2303 | { | |
2304 | enum reset_type method; | |
2305 | ||
8ceee660 BH |
2306 | switch (type) { |
2307 | case RESET_TYPE_INVISIBLE: | |
2308 | case RESET_TYPE_ALL: | |
2309 | case RESET_TYPE_WORLD: | |
2310 | case RESET_TYPE_DISABLE: | |
2311 | method = type; | |
0e2a9c7c BH |
2312 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2313 | RESET_TYPE(method)); | |
8ceee660 | 2314 | break; |
8ceee660 | 2315 | default: |
0e2a9c7c | 2316 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2317 | netif_dbg(efx, drv, efx->net_dev, |
2318 | "scheduling %s reset for %s\n", | |
2319 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2320 | break; |
2321 | } | |
8ceee660 | 2322 | |
a7d529ae | 2323 | set_bit(method, &efx->reset_pending); |
8ceee660 | 2324 | |
8880f4ec BH |
2325 | /* efx_process_channel() will no longer read events once a |
2326 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2327 | efx_mcdi_mode_poll(efx); | |
2328 | ||
1ab00629 | 2329 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2330 | } |
2331 | ||
2332 | /************************************************************************** | |
2333 | * | |
2334 | * List of NICs we support | |
2335 | * | |
2336 | **************************************************************************/ | |
2337 | ||
2338 | /* PCI device ID table */ | |
a3aa1884 | 2339 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2340 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2341 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2342 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2343 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2344 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2345 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2346 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2347 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2348 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2349 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8ceee660 BH |
2350 | {0} /* end of list */ |
2351 | }; | |
2352 | ||
2353 | /************************************************************************** | |
2354 | * | |
3759433d | 2355 | * Dummy PHY/MAC operations |
8ceee660 | 2356 | * |
01aad7b6 | 2357 | * Can be used for some unimplemented operations |
8ceee660 BH |
2358 | * Needed so all function pointers are valid and do not have to be tested |
2359 | * before use | |
2360 | * | |
2361 | **************************************************************************/ | |
2362 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2363 | { | |
2364 | return 0; | |
2365 | } | |
2366 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2367 | |
2368 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2369 | { |
2370 | return false; | |
2371 | } | |
8ceee660 | 2372 | |
6c8c2513 | 2373 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2374 | .init = efx_port_dummy_op_int, |
d3245b28 | 2375 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2376 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2377 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2378 | }; |
2379 | ||
8ceee660 BH |
2380 | /************************************************************************** |
2381 | * | |
2382 | * Data housekeeping | |
2383 | * | |
2384 | **************************************************************************/ | |
2385 | ||
2386 | /* This zeroes out and then fills in the invariants in a struct | |
2387 | * efx_nic (including all sub-structures). | |
2388 | */ | |
6c8c2513 | 2389 | static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type, |
8ceee660 BH |
2390 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2391 | { | |
4642610c | 2392 | int i; |
8ceee660 BH |
2393 | |
2394 | /* Initialise common structures */ | |
2395 | memset(efx, 0, sizeof(*efx)); | |
2396 | spin_lock_init(&efx->biu_lock); | |
76884835 BH |
2397 | #ifdef CONFIG_SFC_MTD |
2398 | INIT_LIST_HEAD(&efx->mtd_list); | |
2399 | #endif | |
8ceee660 BH |
2400 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2401 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
dd40781e | 2402 | INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); |
8ceee660 | 2403 | efx->pci_dev = pci_dev; |
62776d03 | 2404 | efx->msg_enable = debug; |
8ceee660 | 2405 | efx->state = STATE_INIT; |
8ceee660 | 2406 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2407 | |
2408 | efx->net_dev = net_dev; | |
8ceee660 BH |
2409 | spin_lock_init(&efx->stats_lock); |
2410 | mutex_init(&efx->mac_lock); | |
2411 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2412 | efx->mdio.dev = net_dev; |
766ca0fa | 2413 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2414 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2415 | |
2416 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2417 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2418 | if (!efx->channel[i]) | |
2419 | goto fail; | |
8ceee660 BH |
2420 | } |
2421 | ||
2422 | efx->type = type; | |
2423 | ||
8ceee660 BH |
2424 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2425 | ||
2426 | /* Higher numbered interrupt modes are less capable! */ | |
2427 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2428 | interrupt_mode); | |
2429 | ||
6977dc63 BH |
2430 | /* Would be good to use the net_dev name, but we're too early */ |
2431 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2432 | pci_name(pci_dev)); | |
2433 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2434 | if (!efx->workqueue) |
4642610c | 2435 | goto fail; |
8d9853d9 | 2436 | |
8ceee660 | 2437 | return 0; |
4642610c BH |
2438 | |
2439 | fail: | |
2440 | efx_fini_struct(efx); | |
2441 | return -ENOMEM; | |
8ceee660 BH |
2442 | } |
2443 | ||
2444 | static void efx_fini_struct(struct efx_nic *efx) | |
2445 | { | |
8313aca3 BH |
2446 | int i; |
2447 | ||
2448 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2449 | kfree(efx->channel[i]); | |
2450 | ||
8ceee660 BH |
2451 | if (efx->workqueue) { |
2452 | destroy_workqueue(efx->workqueue); | |
2453 | efx->workqueue = NULL; | |
2454 | } | |
2455 | } | |
2456 | ||
2457 | /************************************************************************** | |
2458 | * | |
2459 | * PCI interface | |
2460 | * | |
2461 | **************************************************************************/ | |
2462 | ||
2463 | /* Main body of final NIC shutdown code | |
2464 | * This is called only at module unload (or hotplug removal). | |
2465 | */ | |
2466 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2467 | { | |
64d8ad6d BH |
2468 | #ifdef CONFIG_RFS_ACCEL |
2469 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
2470 | efx->net_dev->rx_cpu_rmap = NULL; | |
2471 | #endif | |
7f967c01 | 2472 | efx_stop_interrupts(efx, false); |
152b6a62 | 2473 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2474 | efx_fini_port(efx); |
ef2b90ee | 2475 | efx->type->fini(efx); |
8ceee660 BH |
2476 | efx_fini_napi(efx); |
2477 | efx_remove_all(efx); | |
2478 | } | |
2479 | ||
2480 | /* Final NIC shutdown | |
2481 | * This is called only at module unload (or hotplug removal). | |
2482 | */ | |
2483 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2484 | { | |
2485 | struct efx_nic *efx; | |
2486 | ||
2487 | efx = pci_get_drvdata(pci_dev); | |
2488 | if (!efx) | |
2489 | return; | |
2490 | ||
2491 | /* Mark the NIC as fini, then stop the interface */ | |
2492 | rtnl_lock(); | |
2493 | efx->state = STATE_FINI; | |
2494 | dev_close(efx->net_dev); | |
2495 | ||
2496 | /* Allow any queued efx_resets() to complete */ | |
2497 | rtnl_unlock(); | |
2498 | ||
7f967c01 | 2499 | efx_stop_interrupts(efx, false); |
cd2d5b52 | 2500 | efx_sriov_fini(efx); |
8ceee660 BH |
2501 | efx_unregister_netdev(efx); |
2502 | ||
7dde596e BH |
2503 | efx_mtd_remove(efx); |
2504 | ||
8ceee660 BH |
2505 | /* Wait for any scheduled resets to complete. No more will be |
2506 | * scheduled from this point because efx_stop_all() has been | |
2507 | * called, we are no longer registered with driverlink, and | |
2508 | * the net_device's have been removed. */ | |
1ab00629 | 2509 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2510 | |
2511 | efx_pci_remove_main(efx); | |
2512 | ||
8ceee660 | 2513 | efx_fini_io(efx); |
62776d03 | 2514 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 | 2515 | |
8ceee660 | 2516 | efx_fini_struct(efx); |
3de4e301 | 2517 | pci_set_drvdata(pci_dev, NULL); |
8ceee660 BH |
2518 | free_netdev(efx->net_dev); |
2519 | }; | |
2520 | ||
460eeaa0 BH |
2521 | /* NIC VPD information |
2522 | * Called during probe to display the part number of the | |
2523 | * installed NIC. VPD is potentially very large but this should | |
2524 | * always appear within the first 512 bytes. | |
2525 | */ | |
2526 | #define SFC_VPD_LEN 512 | |
2527 | static void efx_print_product_vpd(struct efx_nic *efx) | |
2528 | { | |
2529 | struct pci_dev *dev = efx->pci_dev; | |
2530 | char vpd_data[SFC_VPD_LEN]; | |
2531 | ssize_t vpd_size; | |
2532 | int i, j; | |
2533 | ||
2534 | /* Get the vpd data from the device */ | |
2535 | vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); | |
2536 | if (vpd_size <= 0) { | |
2537 | netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); | |
2538 | return; | |
2539 | } | |
2540 | ||
2541 | /* Get the Read only section */ | |
2542 | i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); | |
2543 | if (i < 0) { | |
2544 | netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); | |
2545 | return; | |
2546 | } | |
2547 | ||
2548 | j = pci_vpd_lrdt_size(&vpd_data[i]); | |
2549 | i += PCI_VPD_LRDT_TAG_SIZE; | |
2550 | if (i + j > vpd_size) | |
2551 | j = vpd_size - i; | |
2552 | ||
2553 | /* Get the Part number */ | |
2554 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); | |
2555 | if (i < 0) { | |
2556 | netif_err(efx, drv, efx->net_dev, "Part number not found\n"); | |
2557 | return; | |
2558 | } | |
2559 | ||
2560 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2561 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2562 | if (i + j > vpd_size) { | |
2563 | netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); | |
2564 | return; | |
2565 | } | |
2566 | ||
2567 | netif_info(efx, drv, efx->net_dev, | |
2568 | "Part Number : %.*s\n", j, &vpd_data[i]); | |
2569 | } | |
2570 | ||
2571 | ||
8ceee660 BH |
2572 | /* Main body of NIC initialisation |
2573 | * This is called at module load (or hotplug insertion, theoretically). | |
2574 | */ | |
2575 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2576 | { | |
2577 | int rc; | |
2578 | ||
2579 | /* Do start-of-day initialisation */ | |
2580 | rc = efx_probe_all(efx); | |
2581 | if (rc) | |
2582 | goto fail1; | |
2583 | ||
e8f14992 | 2584 | efx_init_napi(efx); |
8ceee660 | 2585 | |
ef2b90ee | 2586 | rc = efx->type->init(efx); |
8ceee660 | 2587 | if (rc) { |
62776d03 BH |
2588 | netif_err(efx, probe, efx->net_dev, |
2589 | "failed to initialise NIC\n"); | |
278c0621 | 2590 | goto fail3; |
8ceee660 BH |
2591 | } |
2592 | ||
2593 | rc = efx_init_port(efx); | |
2594 | if (rc) { | |
62776d03 BH |
2595 | netif_err(efx, probe, efx->net_dev, |
2596 | "failed to initialise port\n"); | |
278c0621 | 2597 | goto fail4; |
8ceee660 BH |
2598 | } |
2599 | ||
152b6a62 | 2600 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2601 | if (rc) |
278c0621 | 2602 | goto fail5; |
7f967c01 | 2603 | efx_start_interrupts(efx, false); |
8ceee660 BH |
2604 | |
2605 | return 0; | |
2606 | ||
278c0621 | 2607 | fail5: |
8ceee660 | 2608 | efx_fini_port(efx); |
8ceee660 | 2609 | fail4: |
ef2b90ee | 2610 | efx->type->fini(efx); |
8ceee660 BH |
2611 | fail3: |
2612 | efx_fini_napi(efx); | |
8ceee660 BH |
2613 | efx_remove_all(efx); |
2614 | fail1: | |
2615 | return rc; | |
2616 | } | |
2617 | ||
2618 | /* NIC initialisation | |
2619 | * | |
2620 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2621 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2622 | * sets up and registers the network devices with the kernel and hooks |
2623 | * the interrupt service routine. It does not prepare the device for | |
2624 | * transmission; this is left to the first time one of the network | |
2625 | * interfaces is brought up (i.e. efx_net_open). | |
2626 | */ | |
2627 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2628 | const struct pci_device_id *entry) | |
2629 | { | |
6c8c2513 | 2630 | const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data; |
8ceee660 BH |
2631 | struct net_device *net_dev; |
2632 | struct efx_nic *efx; | |
fadac6aa | 2633 | int rc; |
8ceee660 BH |
2634 | |
2635 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2636 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2637 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2638 | if (!net_dev) |
2639 | return -ENOMEM; | |
c383b537 | 2640 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 | 2641 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2642 | NETIF_F_RXCSUM); |
738a8f4b BH |
2643 | if (type->offload_features & NETIF_F_V6_CSUM) |
2644 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2645 | /* Mask for features that also apply to VLAN devices */ |
2646 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2647 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2648 | NETIF_F_RXCSUM); | |
2649 | /* All offloads can be toggled */ | |
2650 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
767e468c | 2651 | efx = netdev_priv(net_dev); |
8ceee660 | 2652 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2653 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2654 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2655 | if (rc) | |
2656 | goto fail1; | |
2657 | ||
62776d03 | 2658 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2659 | "Solarflare NIC detected\n"); |
8ceee660 | 2660 | |
460eeaa0 BH |
2661 | efx_print_product_vpd(efx); |
2662 | ||
8ceee660 BH |
2663 | /* Set up basic I/O (BAR mappings etc) */ |
2664 | rc = efx_init_io(efx); | |
2665 | if (rc) | |
2666 | goto fail2; | |
2667 | ||
fadac6aa | 2668 | rc = efx_pci_probe_main(efx); |
fa402b2e | 2669 | |
fadac6aa BH |
2670 | /* Serialise against efx_reset(). No more resets will be |
2671 | * scheduled since efx_stop_all() has been called, and we have | |
2672 | * not and never have been registered. | |
2673 | */ | |
2674 | cancel_work_sync(&efx->reset_work); | |
8ceee660 | 2675 | |
fadac6aa BH |
2676 | if (rc) |
2677 | goto fail3; | |
8ceee660 | 2678 | |
fadac6aa BH |
2679 | /* If there was a scheduled reset during probe, the NIC is |
2680 | * probably hosed anyway. | |
2681 | */ | |
2682 | if (efx->reset_pending) { | |
2683 | rc = -EIO; | |
8ceee660 BH |
2684 | goto fail4; |
2685 | } | |
2686 | ||
55edc6e6 BH |
2687 | /* Switch to the running state before we expose the device to the OS, |
2688 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2689 | efx->state = STATE_RUNNING; |
7dde596e | 2690 | |
8ceee660 BH |
2691 | rc = efx_register_netdev(efx); |
2692 | if (rc) | |
fadac6aa | 2693 | goto fail4; |
8ceee660 | 2694 | |
cd2d5b52 BH |
2695 | rc = efx_sriov_init(efx); |
2696 | if (rc) | |
2697 | netif_err(efx, probe, efx->net_dev, | |
2698 | "SR-IOV can't be enabled rc %d\n", rc); | |
2699 | ||
62776d03 | 2700 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 2701 | |
7c43161c | 2702 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 2703 | rtnl_lock(); |
7c43161c | 2704 | rc = efx_mtd_probe(efx); |
a5211bb5 | 2705 | rtnl_unlock(); |
7c43161c BH |
2706 | if (rc) |
2707 | netif_warn(efx, probe, efx->net_dev, | |
2708 | "failed to create MTDs (%d)\n", rc); | |
2709 | ||
8ceee660 BH |
2710 | return 0; |
2711 | ||
8ceee660 | 2712 | fail4: |
fadac6aa | 2713 | efx_pci_remove_main(efx); |
8ceee660 BH |
2714 | fail3: |
2715 | efx_fini_io(efx); | |
2716 | fail2: | |
2717 | efx_fini_struct(efx); | |
2718 | fail1: | |
3de4e301 | 2719 | pci_set_drvdata(pci_dev, NULL); |
5e2a911c | 2720 | WARN_ON(rc > 0); |
62776d03 | 2721 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2722 | free_netdev(net_dev); |
2723 | return rc; | |
2724 | } | |
2725 | ||
89c758fa BH |
2726 | static int efx_pm_freeze(struct device *dev) |
2727 | { | |
2728 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2729 | ||
2730 | efx->state = STATE_FINI; | |
2731 | ||
2732 | netif_device_detach(efx->net_dev); | |
2733 | ||
2734 | efx_stop_all(efx); | |
7f967c01 | 2735 | efx_stop_interrupts(efx, false); |
89c758fa BH |
2736 | |
2737 | return 0; | |
2738 | } | |
2739 | ||
2740 | static int efx_pm_thaw(struct device *dev) | |
2741 | { | |
2742 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2743 | ||
2744 | efx->state = STATE_INIT; | |
2745 | ||
7f967c01 | 2746 | efx_start_interrupts(efx, false); |
89c758fa BH |
2747 | |
2748 | mutex_lock(&efx->mac_lock); | |
2749 | efx->phy_op->reconfigure(efx); | |
2750 | mutex_unlock(&efx->mac_lock); | |
2751 | ||
2752 | efx_start_all(efx); | |
2753 | ||
2754 | netif_device_attach(efx->net_dev); | |
2755 | ||
2756 | efx->state = STATE_RUNNING; | |
2757 | ||
2758 | efx->type->resume_wol(efx); | |
2759 | ||
319ba649 SH |
2760 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2761 | queue_work(reset_workqueue, &efx->reset_work); | |
2762 | ||
89c758fa BH |
2763 | return 0; |
2764 | } | |
2765 | ||
2766 | static int efx_pm_poweroff(struct device *dev) | |
2767 | { | |
2768 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2769 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2770 | ||
2771 | efx->type->fini(efx); | |
2772 | ||
a7d529ae | 2773 | efx->reset_pending = 0; |
89c758fa BH |
2774 | |
2775 | pci_save_state(pci_dev); | |
2776 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2777 | } | |
2778 | ||
2779 | /* Used for both resume and restore */ | |
2780 | static int efx_pm_resume(struct device *dev) | |
2781 | { | |
2782 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2783 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2784 | int rc; | |
2785 | ||
2786 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2787 | if (rc) | |
2788 | return rc; | |
2789 | pci_restore_state(pci_dev); | |
2790 | rc = pci_enable_device(pci_dev); | |
2791 | if (rc) | |
2792 | return rc; | |
2793 | pci_set_master(efx->pci_dev); | |
2794 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2795 | if (rc) | |
2796 | return rc; | |
2797 | rc = efx->type->init(efx); | |
2798 | if (rc) | |
2799 | return rc; | |
2800 | efx_pm_thaw(dev); | |
2801 | return 0; | |
2802 | } | |
2803 | ||
2804 | static int efx_pm_suspend(struct device *dev) | |
2805 | { | |
2806 | int rc; | |
2807 | ||
2808 | efx_pm_freeze(dev); | |
2809 | rc = efx_pm_poweroff(dev); | |
2810 | if (rc) | |
2811 | efx_pm_resume(dev); | |
2812 | return rc; | |
2813 | } | |
2814 | ||
18e83e4c | 2815 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
2816 | .suspend = efx_pm_suspend, |
2817 | .resume = efx_pm_resume, | |
2818 | .freeze = efx_pm_freeze, | |
2819 | .thaw = efx_pm_thaw, | |
2820 | .poweroff = efx_pm_poweroff, | |
2821 | .restore = efx_pm_resume, | |
2822 | }; | |
2823 | ||
8ceee660 | 2824 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2825 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2826 | .id_table = efx_pci_table, |
2827 | .probe = efx_pci_probe, | |
2828 | .remove = efx_pci_remove, | |
89c758fa | 2829 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2830 | }; |
2831 | ||
2832 | /************************************************************************** | |
2833 | * | |
2834 | * Kernel module interface | |
2835 | * | |
2836 | *************************************************************************/ | |
2837 | ||
2838 | module_param(interrupt_mode, uint, 0444); | |
2839 | MODULE_PARM_DESC(interrupt_mode, | |
2840 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2841 | ||
2842 | static int __init efx_init_module(void) | |
2843 | { | |
2844 | int rc; | |
2845 | ||
2846 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2847 | ||
2848 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2849 | if (rc) | |
2850 | goto err_notifier; | |
2851 | ||
cd2d5b52 BH |
2852 | rc = efx_init_sriov(); |
2853 | if (rc) | |
2854 | goto err_sriov; | |
2855 | ||
1ab00629 SH |
2856 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2857 | if (!reset_workqueue) { | |
2858 | rc = -ENOMEM; | |
2859 | goto err_reset; | |
2860 | } | |
8ceee660 BH |
2861 | |
2862 | rc = pci_register_driver(&efx_pci_driver); | |
2863 | if (rc < 0) | |
2864 | goto err_pci; | |
2865 | ||
2866 | return 0; | |
2867 | ||
2868 | err_pci: | |
1ab00629 SH |
2869 | destroy_workqueue(reset_workqueue); |
2870 | err_reset: | |
cd2d5b52 BH |
2871 | efx_fini_sriov(); |
2872 | err_sriov: | |
8ceee660 BH |
2873 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2874 | err_notifier: | |
2875 | return rc; | |
2876 | } | |
2877 | ||
2878 | static void __exit efx_exit_module(void) | |
2879 | { | |
2880 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2881 | ||
2882 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2883 | destroy_workqueue(reset_workqueue); |
cd2d5b52 | 2884 | efx_fini_sriov(); |
8ceee660 BH |
2885 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2886 | ||
2887 | } | |
2888 | ||
2889 | module_init(efx_init_module); | |
2890 | module_exit(efx_exit_module); | |
2891 | ||
906bb26c BH |
2892 | MODULE_AUTHOR("Solarflare Communications and " |
2893 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2894 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2895 | MODULE_LICENSE("GPL"); | |
2896 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |