Commit | Line | Data |
---|---|---|
8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
64d8ad6d | 24 | #include <linux/cpu_rmap.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 41 | const char *const efx_loopback_mode_names[] = { |
c459302d | 42 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
47 | [LOOPBACK_XAUI] = "XAUI", |
48 | [LOOPBACK_GMII] = "GMII", | |
49 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
50 | [LOOPBACK_XGBR] = "XGBR", |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
58 | [LOOPBACK_PCS] = "PCS", |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 65 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
69 | }; |
70 | ||
c459302d | 71 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 72 | const char *const efx_reset_type_names[] = { |
c459302d BH |
73 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
74 | [RESET_TYPE_ALL] = "ALL", | |
75 | [RESET_TYPE_WORLD] = "WORLD", | |
76 | [RESET_TYPE_DISABLE] = "DISABLE", | |
77 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
78 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
79 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
80 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
81 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 83 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
84 | }; |
85 | ||
8ceee660 BH |
86 | #define EFX_MAX_MTU (9 * 1024) |
87 | ||
1ab00629 SH |
88 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
89 | * queued onto this work queue. This is not a per-nic work queue, because | |
90 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
91 | */ | |
92 | static struct workqueue_struct *reset_workqueue; | |
93 | ||
8ceee660 BH |
94 | /************************************************************************** |
95 | * | |
96 | * Configurable values | |
97 | * | |
98 | *************************************************************************/ | |
99 | ||
8ceee660 BH |
100 | /* |
101 | * Use separate channels for TX and RX events | |
102 | * | |
28b581ab NT |
103 | * Set this to 1 to use separate channels for TX and RX. It allows us |
104 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 105 | * |
28b581ab | 106 | * This is only used in MSI-X interrupt mode |
8ceee660 | 107 | */ |
28b581ab | 108 | static unsigned int separate_tx_channels; |
8313aca3 | 109 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
110 | MODULE_PARM_DESC(separate_tx_channels, |
111 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
112 | |
113 | /* This is the weight assigned to each of the (per-channel) virtual | |
114 | * NAPI devices. | |
115 | */ | |
116 | static int napi_weight = 64; | |
117 | ||
118 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
119 | * monitor. On Falcon-based NICs, this will: |
120 | * - Check the on-board hardware monitor; | |
121 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 122 | */ |
d215697f | 123 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 124 | |
8ceee660 BH |
125 | /* Initial interrupt moderation settings. They can be modified after |
126 | * module load with ethtool. | |
127 | * | |
128 | * The default for RX should strike a balance between increasing the | |
129 | * round-trip latency and reducing overhead. | |
130 | */ | |
131 | static unsigned int rx_irq_mod_usec = 60; | |
132 | ||
133 | /* Initial interrupt moderation settings. They can be modified after | |
134 | * module load with ethtool. | |
135 | * | |
136 | * This default is chosen to ensure that a 10G link does not go idle | |
137 | * while a TX queue is stopped after it has become full. A queue is | |
138 | * restarted when it drops below half full. The time this takes (assuming | |
139 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
140 | * 512 / 3 * 1.2 = 205 usec. | |
141 | */ | |
142 | static unsigned int tx_irq_mod_usec = 150; | |
143 | ||
144 | /* This is the first interrupt mode to try out of: | |
145 | * 0 => MSI-X | |
146 | * 1 => MSI | |
147 | * 2 => legacy | |
148 | */ | |
149 | static unsigned int interrupt_mode; | |
150 | ||
151 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
152 | * i.e. the number of CPUs among which we may distribute simultaneous | |
153 | * interrupt handling. | |
154 | * | |
155 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 156 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
157 | */ |
158 | static unsigned int rss_cpus; | |
159 | module_param(rss_cpus, uint, 0444); | |
160 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
161 | ||
84ae48fe BH |
162 | static int phy_flash_cfg; |
163 | module_param(phy_flash_cfg, int, 0644); | |
164 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
165 | ||
6fb70fd1 BH |
166 | static unsigned irq_adapt_low_thresh = 10000; |
167 | module_param(irq_adapt_low_thresh, uint, 0644); | |
168 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
169 | "Threshold score for reducing IRQ moderation"); | |
170 | ||
171 | static unsigned irq_adapt_high_thresh = 20000; | |
172 | module_param(irq_adapt_high_thresh, uint, 0644); | |
173 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
174 | "Threshold score for increasing IRQ moderation"); | |
175 | ||
62776d03 BH |
176 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
177 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
178 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
179 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
180 | module_param(debug, uint, 0); | |
181 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
182 | ||
8ceee660 BH |
183 | /************************************************************************** |
184 | * | |
185 | * Utility functions and prototypes | |
186 | * | |
187 | *************************************************************************/ | |
4642610c | 188 | |
9f2cb71c BH |
189 | static void efx_start_interrupts(struct efx_nic *efx); |
190 | static void efx_stop_interrupts(struct efx_nic *efx); | |
4642610c | 191 | static void efx_remove_channels(struct efx_nic *efx); |
8ceee660 | 192 | static void efx_remove_port(struct efx_nic *efx); |
e8f14992 | 193 | static void efx_init_napi(struct efx_nic *efx); |
8ceee660 | 194 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 195 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
196 | static void efx_fini_struct(struct efx_nic *efx); |
197 | static void efx_start_all(struct efx_nic *efx); | |
198 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
199 | |
200 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
201 | do { \ | |
332c1ce9 BH |
202 | if ((efx->state == STATE_RUNNING) || \ |
203 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
204 | ASSERT_RTNL(); \ |
205 | } while (0) | |
206 | ||
207 | /************************************************************************** | |
208 | * | |
209 | * Event queue processing | |
210 | * | |
211 | *************************************************************************/ | |
212 | ||
213 | /* Process channel's event queue | |
214 | * | |
215 | * This function is responsible for processing the event queue of a | |
216 | * single channel. The caller must guarantee that this function will | |
217 | * never be concurrently called more than once on the same channel, | |
218 | * though different channels may be being processed concurrently. | |
219 | */ | |
fa236e18 | 220 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 221 | { |
fa236e18 | 222 | int spent; |
8ceee660 | 223 | |
9f2cb71c | 224 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 225 | return 0; |
8ceee660 | 226 | |
fa236e18 | 227 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
228 | if (spent && efx_channel_has_rx_queue(channel)) { |
229 | struct efx_rx_queue *rx_queue = | |
230 | efx_channel_get_rx_queue(channel); | |
231 | ||
232 | /* Deliver last RX packet. */ | |
233 | if (channel->rx_pkt) { | |
234 | __efx_rx_packet(channel, channel->rx_pkt); | |
235 | channel->rx_pkt = NULL; | |
236 | } | |
9f2cb71c BH |
237 | if (rx_queue->enabled) { |
238 | efx_rx_strategy(channel); | |
239 | efx_fast_push_rx_descriptors(rx_queue); | |
240 | } | |
8ceee660 BH |
241 | } |
242 | ||
fa236e18 | 243 | return spent; |
8ceee660 BH |
244 | } |
245 | ||
246 | /* Mark channel as finished processing | |
247 | * | |
248 | * Note that since we will not receive further interrupts for this | |
249 | * channel before we finish processing and call the eventq_read_ack() | |
250 | * method, there is no need to use the interrupt hold-off timers. | |
251 | */ | |
252 | static inline void efx_channel_processed(struct efx_channel *channel) | |
253 | { | |
5b9e207c BH |
254 | /* The interrupt handler for this channel may set work_pending |
255 | * as soon as we acknowledge the events we've seen. Make sure | |
256 | * it's cleared before then. */ | |
dc8cfa55 | 257 | channel->work_pending = false; |
5b9e207c BH |
258 | smp_wmb(); |
259 | ||
152b6a62 | 260 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
261 | } |
262 | ||
263 | /* NAPI poll handler | |
264 | * | |
265 | * NAPI guarantees serialisation of polls of the same device, which | |
266 | * provides the guarantee required by efx_process_channel(). | |
267 | */ | |
268 | static int efx_poll(struct napi_struct *napi, int budget) | |
269 | { | |
270 | struct efx_channel *channel = | |
271 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 272 | struct efx_nic *efx = channel->efx; |
fa236e18 | 273 | int spent; |
8ceee660 | 274 | |
62776d03 BH |
275 | netif_vdbg(efx, intr, efx->net_dev, |
276 | "channel %d NAPI poll executing on CPU %d\n", | |
277 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 278 | |
fa236e18 | 279 | spent = efx_process_channel(channel, budget); |
8ceee660 | 280 | |
fa236e18 | 281 | if (spent < budget) { |
9d9a6973 | 282 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
283 | efx->irq_rx_adaptive && |
284 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
285 | if (unlikely(channel->irq_mod_score < |
286 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
287 | if (channel->irq_moderation > 1) { |
288 | channel->irq_moderation -= 1; | |
ef2b90ee | 289 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 290 | } |
6fb70fd1 BH |
291 | } else if (unlikely(channel->irq_mod_score > |
292 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
293 | if (channel->irq_moderation < |
294 | efx->irq_rx_moderation) { | |
295 | channel->irq_moderation += 1; | |
ef2b90ee | 296 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 297 | } |
6fb70fd1 | 298 | } |
6fb70fd1 BH |
299 | channel->irq_count = 0; |
300 | channel->irq_mod_score = 0; | |
301 | } | |
302 | ||
64d8ad6d BH |
303 | efx_filter_rfs_expire(channel); |
304 | ||
8ceee660 | 305 | /* There is no race here; although napi_disable() will |
288379f0 | 306 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
307 | * since efx_channel_processed() will have no effect if |
308 | * interrupts have already been disabled. | |
309 | */ | |
288379f0 | 310 | napi_complete(napi); |
8ceee660 BH |
311 | efx_channel_processed(channel); |
312 | } | |
313 | ||
fa236e18 | 314 | return spent; |
8ceee660 BH |
315 | } |
316 | ||
317 | /* Process the eventq of the specified channel immediately on this CPU | |
318 | * | |
319 | * Disable hardware generated interrupts, wait for any existing | |
320 | * processing to finish, then directly poll (and ack ) the eventq. | |
321 | * Finally reenable NAPI and interrupts. | |
322 | * | |
d4fabcc8 BH |
323 | * This is for use only during a loopback self-test. It must not |
324 | * deliver any packets up the stack as this can result in deadlock. | |
8ceee660 BH |
325 | */ |
326 | void efx_process_channel_now(struct efx_channel *channel) | |
327 | { | |
328 | struct efx_nic *efx = channel->efx; | |
329 | ||
8313aca3 | 330 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 | 331 | BUG_ON(!channel->enabled); |
d4fabcc8 | 332 | BUG_ON(!efx->loopback_selftest); |
8ceee660 BH |
333 | |
334 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 335 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 336 | if (efx->legacy_irq) { |
8ceee660 | 337 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
338 | efx->legacy_irq_enabled = false; |
339 | } | |
64ee3120 | 340 | if (channel->irq) |
8ceee660 BH |
341 | synchronize_irq(channel->irq); |
342 | ||
343 | /* Wait for any NAPI processing to complete */ | |
344 | napi_disable(&channel->napi_str); | |
345 | ||
346 | /* Poll the channel */ | |
ecc910f5 | 347 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
348 | |
349 | /* Ack the eventq. This may cause an interrupt to be generated | |
350 | * when they are reenabled */ | |
351 | efx_channel_processed(channel); | |
352 | ||
353 | napi_enable(&channel->napi_str); | |
94dec6a2 BH |
354 | if (efx->legacy_irq) |
355 | efx->legacy_irq_enabled = true; | |
152b6a62 | 356 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
357 | } |
358 | ||
359 | /* Create event queue | |
360 | * Event queue memory allocations are done only once. If the channel | |
361 | * is reset, the memory buffer will be reused; this guards against | |
362 | * errors during channel reset and also simplifies interrupt handling. | |
363 | */ | |
364 | static int efx_probe_eventq(struct efx_channel *channel) | |
365 | { | |
ecc910f5 SH |
366 | struct efx_nic *efx = channel->efx; |
367 | unsigned long entries; | |
368 | ||
86ee5302 | 369 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 370 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 371 | |
ecc910f5 SH |
372 | /* Build an event queue with room for one event per tx and rx buffer, |
373 | * plus some extra for link state events and MCDI completions. */ | |
374 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
375 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
376 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
377 | ||
152b6a62 | 378 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
379 | } |
380 | ||
381 | /* Prepare channel's event queue */ | |
bc3c90a2 | 382 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 383 | { |
62776d03 BH |
384 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
385 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
386 | |
387 | channel->eventq_read_ptr = 0; | |
388 | ||
152b6a62 | 389 | efx_nic_init_eventq(channel); |
8ceee660 BH |
390 | } |
391 | ||
9f2cb71c BH |
392 | /* Enable event queue processing and NAPI */ |
393 | static void efx_start_eventq(struct efx_channel *channel) | |
394 | { | |
395 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
396 | "chan %d start event queue\n", channel->channel); | |
397 | ||
398 | /* The interrupt handler for this channel may set work_pending | |
399 | * as soon as we enable it. Make sure it's cleared before | |
400 | * then. Similarly, make sure it sees the enabled flag set. | |
401 | */ | |
402 | channel->work_pending = false; | |
403 | channel->enabled = true; | |
404 | smp_wmb(); | |
405 | ||
406 | napi_enable(&channel->napi_str); | |
407 | efx_nic_eventq_read_ack(channel); | |
408 | } | |
409 | ||
410 | /* Disable event queue processing and NAPI */ | |
411 | static void efx_stop_eventq(struct efx_channel *channel) | |
412 | { | |
413 | if (!channel->enabled) | |
414 | return; | |
415 | ||
416 | napi_disable(&channel->napi_str); | |
417 | channel->enabled = false; | |
418 | } | |
419 | ||
8ceee660 BH |
420 | static void efx_fini_eventq(struct efx_channel *channel) |
421 | { | |
62776d03 BH |
422 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
423 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 424 | |
152b6a62 | 425 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
426 | } |
427 | ||
428 | static void efx_remove_eventq(struct efx_channel *channel) | |
429 | { | |
62776d03 BH |
430 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
431 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 432 | |
152b6a62 | 433 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
434 | } |
435 | ||
436 | /************************************************************************** | |
437 | * | |
438 | * Channel handling | |
439 | * | |
440 | *************************************************************************/ | |
441 | ||
4642610c BH |
442 | /* Allocate and initialise a channel structure, optionally copying |
443 | * parameters (but not resources) from an old channel structure. */ | |
444 | static struct efx_channel * | |
445 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
446 | { | |
447 | struct efx_channel *channel; | |
448 | struct efx_rx_queue *rx_queue; | |
449 | struct efx_tx_queue *tx_queue; | |
450 | int j; | |
451 | ||
452 | if (old_channel) { | |
453 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); | |
454 | if (!channel) | |
455 | return NULL; | |
456 | ||
457 | *channel = *old_channel; | |
458 | ||
e8f14992 | 459 | channel->napi_dev = NULL; |
4642610c BH |
460 | memset(&channel->eventq, 0, sizeof(channel->eventq)); |
461 | ||
462 | rx_queue = &channel->rx_queue; | |
463 | rx_queue->buffer = NULL; | |
464 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
465 | ||
466 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
467 | tx_queue = &channel->tx_queue[j]; | |
468 | if (tx_queue->channel) | |
469 | tx_queue->channel = channel; | |
470 | tx_queue->buffer = NULL; | |
471 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
472 | } | |
473 | } else { | |
474 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); | |
475 | if (!channel) | |
476 | return NULL; | |
477 | ||
478 | channel->efx = efx; | |
479 | channel->channel = i; | |
480 | ||
481 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
482 | tx_queue = &channel->tx_queue[j]; | |
483 | tx_queue->efx = efx; | |
484 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
485 | tx_queue->channel = channel; | |
486 | } | |
487 | } | |
488 | ||
4642610c BH |
489 | rx_queue = &channel->rx_queue; |
490 | rx_queue->efx = efx; | |
491 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
492 | (unsigned long)rx_queue); | |
493 | ||
494 | return channel; | |
495 | } | |
496 | ||
8ceee660 BH |
497 | static int efx_probe_channel(struct efx_channel *channel) |
498 | { | |
499 | struct efx_tx_queue *tx_queue; | |
500 | struct efx_rx_queue *rx_queue; | |
501 | int rc; | |
502 | ||
62776d03 BH |
503 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
504 | "creating channel %d\n", channel->channel); | |
8ceee660 BH |
505 | |
506 | rc = efx_probe_eventq(channel); | |
507 | if (rc) | |
508 | goto fail1; | |
509 | ||
510 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
511 | rc = efx_probe_tx_queue(tx_queue); | |
512 | if (rc) | |
513 | goto fail2; | |
514 | } | |
515 | ||
516 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
517 | rc = efx_probe_rx_queue(rx_queue); | |
518 | if (rc) | |
519 | goto fail3; | |
520 | } | |
521 | ||
522 | channel->n_rx_frm_trunc = 0; | |
523 | ||
524 | return 0; | |
525 | ||
526 | fail3: | |
527 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
528 | efx_remove_rx_queue(rx_queue); | |
529 | fail2: | |
530 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
531 | efx_remove_tx_queue(tx_queue); | |
532 | fail1: | |
533 | return rc; | |
534 | } | |
535 | ||
536 | ||
56536e9c BH |
537 | static void efx_set_channel_names(struct efx_nic *efx) |
538 | { | |
539 | struct efx_channel *channel; | |
540 | const char *type = ""; | |
541 | int number; | |
542 | ||
543 | efx_for_each_channel(channel, efx) { | |
544 | number = channel->channel; | |
a4900ac9 BH |
545 | if (efx->n_channels > efx->n_rx_channels) { |
546 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
547 | type = "-rx"; |
548 | } else { | |
549 | type = "-tx"; | |
a4900ac9 | 550 | number -= efx->n_rx_channels; |
56536e9c BH |
551 | } |
552 | } | |
4642610c BH |
553 | snprintf(efx->channel_name[channel->channel], |
554 | sizeof(efx->channel_name[0]), | |
56536e9c BH |
555 | "%s%s-%d", efx->name, type, number); |
556 | } | |
557 | } | |
558 | ||
4642610c BH |
559 | static int efx_probe_channels(struct efx_nic *efx) |
560 | { | |
561 | struct efx_channel *channel; | |
562 | int rc; | |
563 | ||
564 | /* Restart special buffer allocation */ | |
565 | efx->next_buffer_table = 0; | |
566 | ||
567 | efx_for_each_channel(channel, efx) { | |
568 | rc = efx_probe_channel(channel); | |
569 | if (rc) { | |
570 | netif_err(efx, probe, efx->net_dev, | |
571 | "failed to create channel %d\n", | |
572 | channel->channel); | |
573 | goto fail; | |
574 | } | |
575 | } | |
576 | efx_set_channel_names(efx); | |
577 | ||
578 | return 0; | |
579 | ||
580 | fail: | |
581 | efx_remove_channels(efx); | |
582 | return rc; | |
583 | } | |
584 | ||
8ceee660 BH |
585 | /* Channels are shutdown and reinitialised whilst the NIC is running |
586 | * to propagate configuration changes (mtu, checksum offload), or | |
587 | * to clear hardware error conditions | |
588 | */ | |
9f2cb71c | 589 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 BH |
590 | { |
591 | struct efx_tx_queue *tx_queue; | |
592 | struct efx_rx_queue *rx_queue; | |
593 | struct efx_channel *channel; | |
8ceee660 | 594 | |
f7f13b0b BH |
595 | /* Calculate the rx buffer allocation parameters required to |
596 | * support the current MTU, including padding for header | |
597 | * alignment and overruns. | |
598 | */ | |
599 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
600 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 601 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 602 | efx->type->rx_buffer_padding); |
62b330ba SH |
603 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
604 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
605 | |
606 | /* Initialise the channels */ | |
607 | efx_for_each_channel(channel, efx) { | |
bc3c90a2 BH |
608 | efx_for_each_channel_tx_queue(tx_queue, channel) |
609 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
610 | |
611 | /* The rx buffer allocation strategy is MTU dependent */ | |
612 | efx_rx_strategy(channel); | |
613 | ||
9f2cb71c | 614 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 615 | efx_init_rx_queue(rx_queue); |
9f2cb71c BH |
616 | efx_nic_generate_fill_event(rx_queue); |
617 | } | |
8ceee660 BH |
618 | |
619 | WARN_ON(channel->rx_pkt != NULL); | |
620 | efx_rx_strategy(channel); | |
621 | } | |
8ceee660 | 622 | |
9f2cb71c BH |
623 | if (netif_device_present(efx->net_dev)) |
624 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
625 | } |
626 | ||
9f2cb71c | 627 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
628 | { |
629 | struct efx_channel *channel; | |
630 | struct efx_tx_queue *tx_queue; | |
631 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 632 | int rc; |
8ceee660 BH |
633 | |
634 | EFX_ASSERT_RESET_SERIALISED(efx); | |
635 | BUG_ON(efx->port_enabled); | |
636 | ||
152b6a62 | 637 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
638 | if (rc && EFX_WORKAROUND_7803(efx)) { |
639 | /* Schedule a reset to recover from the flush failure. The | |
640 | * descriptor caches reference memory we're about to free, | |
641 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
642 | * the MACs because of the pending reset. */ | |
62776d03 BH |
643 | netif_err(efx, drv, efx->net_dev, |
644 | "Resetting to recover from flush failure\n"); | |
fd371e32 SH |
645 | efx_schedule_reset(efx, RESET_TYPE_ALL); |
646 | } else if (rc) { | |
62776d03 | 647 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); |
fd371e32 | 648 | } else { |
62776d03 BH |
649 | netif_dbg(efx, drv, efx->net_dev, |
650 | "successfully flushed all queues\n"); | |
fd371e32 | 651 | } |
6bc5d3a9 | 652 | |
8ceee660 | 653 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
654 | /* RX packet processing is pipelined, so wait for the |
655 | * NAPI handler to complete. At least event queue 0 | |
656 | * might be kept active by non-data events, so don't | |
657 | * use napi_synchronize() but actually disable NAPI | |
658 | * temporarily. | |
659 | */ | |
660 | if (efx_channel_has_rx_queue(channel)) { | |
661 | efx_stop_eventq(channel); | |
662 | efx_start_eventq(channel); | |
663 | } | |
8ceee660 BH |
664 | |
665 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
666 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 667 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 668 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
669 | } |
670 | } | |
671 | ||
672 | static void efx_remove_channel(struct efx_channel *channel) | |
673 | { | |
674 | struct efx_tx_queue *tx_queue; | |
675 | struct efx_rx_queue *rx_queue; | |
676 | ||
62776d03 BH |
677 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
678 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
679 | |
680 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
681 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 682 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
683 | efx_remove_tx_queue(tx_queue); |
684 | efx_remove_eventq(channel); | |
8ceee660 BH |
685 | } |
686 | ||
4642610c BH |
687 | static void efx_remove_channels(struct efx_nic *efx) |
688 | { | |
689 | struct efx_channel *channel; | |
690 | ||
691 | efx_for_each_channel(channel, efx) | |
692 | efx_remove_channel(channel); | |
693 | } | |
694 | ||
695 | int | |
696 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
697 | { | |
698 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
699 | u32 old_rxq_entries, old_txq_entries; | |
700 | unsigned i; | |
701 | int rc; | |
702 | ||
703 | efx_stop_all(efx); | |
9f2cb71c | 704 | efx_stop_interrupts(efx); |
4642610c BH |
705 | |
706 | /* Clone channels */ | |
707 | memset(other_channel, 0, sizeof(other_channel)); | |
708 | for (i = 0; i < efx->n_channels; i++) { | |
709 | channel = efx_alloc_channel(efx, i, efx->channel[i]); | |
710 | if (!channel) { | |
711 | rc = -ENOMEM; | |
712 | goto out; | |
713 | } | |
714 | other_channel[i] = channel; | |
715 | } | |
716 | ||
717 | /* Swap entry counts and channel pointers */ | |
718 | old_rxq_entries = efx->rxq_entries; | |
719 | old_txq_entries = efx->txq_entries; | |
720 | efx->rxq_entries = rxq_entries; | |
721 | efx->txq_entries = txq_entries; | |
722 | for (i = 0; i < efx->n_channels; i++) { | |
723 | channel = efx->channel[i]; | |
724 | efx->channel[i] = other_channel[i]; | |
725 | other_channel[i] = channel; | |
726 | } | |
727 | ||
728 | rc = efx_probe_channels(efx); | |
729 | if (rc) | |
730 | goto rollback; | |
731 | ||
e8f14992 BH |
732 | efx_init_napi(efx); |
733 | ||
4642610c | 734 | /* Destroy old channels */ |
e8f14992 BH |
735 | for (i = 0; i < efx->n_channels; i++) { |
736 | efx_fini_napi_channel(other_channel[i]); | |
4642610c | 737 | efx_remove_channel(other_channel[i]); |
e8f14992 | 738 | } |
4642610c BH |
739 | out: |
740 | /* Free unused channel structures */ | |
741 | for (i = 0; i < efx->n_channels; i++) | |
742 | kfree(other_channel[i]); | |
743 | ||
9f2cb71c | 744 | efx_start_interrupts(efx); |
4642610c BH |
745 | efx_start_all(efx); |
746 | return rc; | |
747 | ||
748 | rollback: | |
749 | /* Swap back */ | |
750 | efx->rxq_entries = old_rxq_entries; | |
751 | efx->txq_entries = old_txq_entries; | |
752 | for (i = 0; i < efx->n_channels; i++) { | |
753 | channel = efx->channel[i]; | |
754 | efx->channel[i] = other_channel[i]; | |
755 | other_channel[i] = channel; | |
756 | } | |
757 | goto out; | |
758 | } | |
759 | ||
90d683af | 760 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 761 | { |
90d683af | 762 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
763 | } |
764 | ||
765 | /************************************************************************** | |
766 | * | |
767 | * Port handling | |
768 | * | |
769 | **************************************************************************/ | |
770 | ||
771 | /* This ensures that the kernel is kept informed (via | |
772 | * netif_carrier_on/off) of the link status, and also maintains the | |
773 | * link status's stop on the port's TX queue. | |
774 | */ | |
fdaa9aed | 775 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 776 | { |
eb50c0d6 BH |
777 | struct efx_link_state *link_state = &efx->link_state; |
778 | ||
8ceee660 BH |
779 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
780 | * that no events are triggered between unregister_netdev() and the | |
781 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
782 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
783 | if (!netif_running(efx->net_dev)) | |
784 | return; | |
785 | ||
eb50c0d6 | 786 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
787 | efx->n_link_state_changes++; |
788 | ||
eb50c0d6 | 789 | if (link_state->up) |
8ceee660 BH |
790 | netif_carrier_on(efx->net_dev); |
791 | else | |
792 | netif_carrier_off(efx->net_dev); | |
793 | } | |
794 | ||
795 | /* Status message for kernel log */ | |
2aa9ef11 | 796 | if (link_state->up) |
62776d03 BH |
797 | netif_info(efx, link, efx->net_dev, |
798 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
799 | link_state->speed, link_state->fd ? "full" : "half", | |
800 | efx->net_dev->mtu, | |
801 | (efx->promiscuous ? " [PROMISC]" : "")); | |
2aa9ef11 | 802 | else |
62776d03 | 803 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
804 | } |
805 | ||
d3245b28 BH |
806 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
807 | { | |
808 | efx->link_advertising = advertising; | |
809 | if (advertising) { | |
810 | if (advertising & ADVERTISED_Pause) | |
811 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
812 | else | |
813 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
814 | if (advertising & ADVERTISED_Asym_Pause) | |
815 | efx->wanted_fc ^= EFX_FC_TX; | |
816 | } | |
817 | } | |
818 | ||
b5626946 | 819 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
820 | { |
821 | efx->wanted_fc = wanted_fc; | |
822 | if (efx->link_advertising) { | |
823 | if (wanted_fc & EFX_FC_RX) | |
824 | efx->link_advertising |= (ADVERTISED_Pause | | |
825 | ADVERTISED_Asym_Pause); | |
826 | else | |
827 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
828 | ADVERTISED_Asym_Pause); | |
829 | if (wanted_fc & EFX_FC_TX) | |
830 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
831 | } | |
832 | } | |
833 | ||
115122af BH |
834 | static void efx_fini_port(struct efx_nic *efx); |
835 | ||
d3245b28 BH |
836 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
837 | * the MAC appropriately. All other PHY configuration changes are pushed | |
838 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
839 | * through efx_monitor(). | |
840 | * | |
841 | * Callers must hold the mac_lock | |
842 | */ | |
843 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 844 | { |
d3245b28 BH |
845 | enum efx_phy_mode phy_mode; |
846 | int rc; | |
8ceee660 | 847 | |
d3245b28 | 848 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 849 | |
0fca8c97 | 850 | /* Serialise the promiscuous flag with efx_set_rx_mode. */ |
73ba7b68 BH |
851 | netif_addr_lock_bh(efx->net_dev); |
852 | netif_addr_unlock_bh(efx->net_dev); | |
a816f75a | 853 | |
d3245b28 BH |
854 | /* Disable PHY transmit in mac level loopbacks */ |
855 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
856 | if (LOOPBACK_INTERNAL(efx)) |
857 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
858 | else | |
859 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 860 | |
d3245b28 | 861 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 862 | |
d3245b28 BH |
863 | if (rc) |
864 | efx->phy_mode = phy_mode; | |
177dfcd8 | 865 | |
d3245b28 | 866 | return rc; |
8ceee660 BH |
867 | } |
868 | ||
869 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
870 | * disabled. */ | |
d3245b28 | 871 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 872 | { |
d3245b28 BH |
873 | int rc; |
874 | ||
8ceee660 BH |
875 | EFX_ASSERT_RESET_SERIALISED(efx); |
876 | ||
877 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 878 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 879 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
880 | |
881 | return rc; | |
8ceee660 BH |
882 | } |
883 | ||
8be4f3e6 BH |
884 | /* Asynchronous work item for changing MAC promiscuity and multicast |
885 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
886 | * MAC directly. */ | |
766ca0fa BH |
887 | static void efx_mac_work(struct work_struct *data) |
888 | { | |
889 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
890 | ||
891 | mutex_lock(&efx->mac_lock); | |
30b81cda | 892 | if (efx->port_enabled) |
710b208d | 893 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
894 | mutex_unlock(&efx->mac_lock); |
895 | } | |
896 | ||
8ceee660 BH |
897 | static int efx_probe_port(struct efx_nic *efx) |
898 | { | |
899 | int rc; | |
900 | ||
62776d03 | 901 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 902 | |
ff3b00a0 SH |
903 | if (phy_flash_cfg) |
904 | efx->phy_mode = PHY_MODE_SPECIAL; | |
905 | ||
ef2b90ee BH |
906 | /* Connect up MAC/PHY operations table */ |
907 | rc = efx->type->probe_port(efx); | |
8ceee660 | 908 | if (rc) |
e42de262 | 909 | return rc; |
8ceee660 | 910 | |
e332bcb3 BH |
911 | /* Initialise MAC address to permanent address */ |
912 | memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); | |
8ceee660 BH |
913 | |
914 | return 0; | |
8ceee660 BH |
915 | } |
916 | ||
917 | static int efx_init_port(struct efx_nic *efx) | |
918 | { | |
919 | int rc; | |
920 | ||
62776d03 | 921 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 922 | |
1dfc5cea BH |
923 | mutex_lock(&efx->mac_lock); |
924 | ||
177dfcd8 | 925 | rc = efx->phy_op->init(efx); |
8ceee660 | 926 | if (rc) |
1dfc5cea | 927 | goto fail1; |
8ceee660 | 928 | |
dc8cfa55 | 929 | efx->port_initialized = true; |
1dfc5cea | 930 | |
d3245b28 BH |
931 | /* Reconfigure the MAC before creating dma queues (required for |
932 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 933 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
934 | |
935 | /* Ensure the PHY advertises the correct flow control settings */ | |
936 | rc = efx->phy_op->reconfigure(efx); | |
937 | if (rc) | |
938 | goto fail2; | |
939 | ||
1dfc5cea | 940 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 941 | return 0; |
177dfcd8 | 942 | |
1dfc5cea | 943 | fail2: |
177dfcd8 | 944 | efx->phy_op->fini(efx); |
1dfc5cea BH |
945 | fail1: |
946 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 947 | return rc; |
8ceee660 BH |
948 | } |
949 | ||
8ceee660 BH |
950 | static void efx_start_port(struct efx_nic *efx) |
951 | { | |
62776d03 | 952 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
953 | BUG_ON(efx->port_enabled); |
954 | ||
955 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 956 | efx->port_enabled = true; |
8be4f3e6 BH |
957 | |
958 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
959 | * and then cancelled by efx_flush_all() */ | |
710b208d | 960 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 961 | |
8ceee660 BH |
962 | mutex_unlock(&efx->mac_lock); |
963 | } | |
964 | ||
fdaa9aed | 965 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
966 | static void efx_stop_port(struct efx_nic *efx) |
967 | { | |
62776d03 | 968 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
969 | |
970 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 971 | efx->port_enabled = false; |
8ceee660 BH |
972 | mutex_unlock(&efx->mac_lock); |
973 | ||
974 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
975 | netif_addr_lock_bh(efx->net_dev); |
976 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
977 | } |
978 | ||
979 | static void efx_fini_port(struct efx_nic *efx) | |
980 | { | |
62776d03 | 981 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
982 | |
983 | if (!efx->port_initialized) | |
984 | return; | |
985 | ||
177dfcd8 | 986 | efx->phy_op->fini(efx); |
dc8cfa55 | 987 | efx->port_initialized = false; |
8ceee660 | 988 | |
eb50c0d6 | 989 | efx->link_state.up = false; |
8ceee660 BH |
990 | efx_link_status_changed(efx); |
991 | } | |
992 | ||
993 | static void efx_remove_port(struct efx_nic *efx) | |
994 | { | |
62776d03 | 995 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 996 | |
ef2b90ee | 997 | efx->type->remove_port(efx); |
8ceee660 BH |
998 | } |
999 | ||
1000 | /************************************************************************** | |
1001 | * | |
1002 | * NIC handling | |
1003 | * | |
1004 | **************************************************************************/ | |
1005 | ||
1006 | /* This configures the PCI device to enable I/O and DMA. */ | |
1007 | static int efx_init_io(struct efx_nic *efx) | |
1008 | { | |
1009 | struct pci_dev *pci_dev = efx->pci_dev; | |
1010 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
1011 | int rc; | |
1012 | ||
62776d03 | 1013 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1014 | |
1015 | rc = pci_enable_device(pci_dev); | |
1016 | if (rc) { | |
62776d03 BH |
1017 | netif_err(efx, probe, efx->net_dev, |
1018 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1019 | goto fail1; |
1020 | } | |
1021 | ||
1022 | pci_set_master(pci_dev); | |
1023 | ||
1024 | /* Set the PCI DMA mask. Try all possibilities from our | |
1025 | * genuine mask down to 32 bits, because some architectures | |
1026 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1027 | * masks event though they reject 46 bit masks. | |
1028 | */ | |
1029 | while (dma_mask > 0x7fffffffUL) { | |
e9e01846 BH |
1030 | if (pci_dma_supported(pci_dev, dma_mask)) { |
1031 | rc = pci_set_dma_mask(pci_dev, dma_mask); | |
1032 | if (rc == 0) | |
1033 | break; | |
1034 | } | |
8ceee660 BH |
1035 | dma_mask >>= 1; |
1036 | } | |
1037 | if (rc) { | |
62776d03 BH |
1038 | netif_err(efx, probe, efx->net_dev, |
1039 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1040 | goto fail2; |
1041 | } | |
62776d03 BH |
1042 | netif_dbg(efx, probe, efx->net_dev, |
1043 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 BH |
1044 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); |
1045 | if (rc) { | |
1046 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
1047 | * fail with a mask that pci_set_dma_mask() accepted, | |
1048 | * but just in case... | |
1049 | */ | |
62776d03 BH |
1050 | netif_err(efx, probe, efx->net_dev, |
1051 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1052 | goto fail2; |
1053 | } | |
1054 | ||
dc803df8 BH |
1055 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1056 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1057 | if (rc) { |
62776d03 BH |
1058 | netif_err(efx, probe, efx->net_dev, |
1059 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1060 | rc = -EIO; |
1061 | goto fail3; | |
1062 | } | |
86c432ca BH |
1063 | efx->membase = ioremap_nocache(efx->membase_phys, |
1064 | efx->type->mem_map_size); | |
8ceee660 | 1065 | if (!efx->membase) { |
62776d03 BH |
1066 | netif_err(efx, probe, efx->net_dev, |
1067 | "could not map memory BAR at %llx+%x\n", | |
1068 | (unsigned long long)efx->membase_phys, | |
1069 | efx->type->mem_map_size); | |
8ceee660 BH |
1070 | rc = -ENOMEM; |
1071 | goto fail4; | |
1072 | } | |
62776d03 BH |
1073 | netif_dbg(efx, probe, efx->net_dev, |
1074 | "memory BAR at %llx+%x (virtual %p)\n", | |
1075 | (unsigned long long)efx->membase_phys, | |
1076 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1077 | |
1078 | return 0; | |
1079 | ||
1080 | fail4: | |
dc803df8 | 1081 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1082 | fail3: |
2c118e0f | 1083 | efx->membase_phys = 0; |
8ceee660 BH |
1084 | fail2: |
1085 | pci_disable_device(efx->pci_dev); | |
1086 | fail1: | |
1087 | return rc; | |
1088 | } | |
1089 | ||
1090 | static void efx_fini_io(struct efx_nic *efx) | |
1091 | { | |
62776d03 | 1092 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1093 | |
1094 | if (efx->membase) { | |
1095 | iounmap(efx->membase); | |
1096 | efx->membase = NULL; | |
1097 | } | |
1098 | ||
1099 | if (efx->membase_phys) { | |
dc803df8 | 1100 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1101 | efx->membase_phys = 0; |
8ceee660 BH |
1102 | } |
1103 | ||
1104 | pci_disable_device(efx->pci_dev); | |
1105 | } | |
1106 | ||
a16e5b24 | 1107 | static unsigned int efx_wanted_parallelism(void) |
46123d04 | 1108 | { |
cdb08f8f | 1109 | cpumask_var_t thread_mask; |
a16e5b24 | 1110 | unsigned int count; |
46123d04 | 1111 | int cpu; |
5b874e25 BH |
1112 | |
1113 | if (rss_cpus) | |
1114 | return rss_cpus; | |
46123d04 | 1115 | |
cdb08f8f | 1116 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { |
2f8975fb | 1117 | printk(KERN_WARNING |
3977d033 | 1118 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
1119 | return 1; |
1120 | } | |
1121 | ||
46123d04 BH |
1122 | count = 0; |
1123 | for_each_online_cpu(cpu) { | |
cdb08f8f | 1124 | if (!cpumask_test_cpu(cpu, thread_mask)) { |
46123d04 | 1125 | ++count; |
cdb08f8f BH |
1126 | cpumask_or(thread_mask, thread_mask, |
1127 | topology_thread_cpumask(cpu)); | |
46123d04 BH |
1128 | } |
1129 | } | |
1130 | ||
cdb08f8f | 1131 | free_cpumask_var(thread_mask); |
46123d04 BH |
1132 | return count; |
1133 | } | |
1134 | ||
64d8ad6d BH |
1135 | static int |
1136 | efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) | |
1137 | { | |
1138 | #ifdef CONFIG_RFS_ACCEL | |
a16e5b24 BH |
1139 | unsigned int i; |
1140 | int rc; | |
64d8ad6d BH |
1141 | |
1142 | efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); | |
1143 | if (!efx->net_dev->rx_cpu_rmap) | |
1144 | return -ENOMEM; | |
1145 | for (i = 0; i < efx->n_rx_channels; i++) { | |
1146 | rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, | |
1147 | xentries[i].vector); | |
1148 | if (rc) { | |
1149 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
1150 | efx->net_dev->rx_cpu_rmap = NULL; | |
1151 | return rc; | |
1152 | } | |
1153 | } | |
1154 | #endif | |
1155 | return 0; | |
1156 | } | |
1157 | ||
46123d04 BH |
1158 | /* Probe the number and type of interrupts we are able to obtain, and |
1159 | * the resulting numbers of channels and RX queues. | |
1160 | */ | |
64d8ad6d | 1161 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1162 | { |
a16e5b24 BH |
1163 | unsigned int max_channels = |
1164 | min(efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
1165 | unsigned int i; | |
1166 | int rc; | |
8ceee660 BH |
1167 | |
1168 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 1169 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1170 | unsigned int n_channels; |
aa6ef27e | 1171 | |
fa142b9d | 1172 | n_channels = efx_wanted_parallelism(); |
a4900ac9 BH |
1173 | if (separate_tx_channels) |
1174 | n_channels *= 2; | |
1175 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 1176 | |
a4900ac9 | 1177 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1178 | xentries[i].entry = i; |
a4900ac9 | 1179 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1180 | if (rc > 0) { |
62776d03 BH |
1181 | netif_err(efx, drv, efx->net_dev, |
1182 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1183 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1184 | netif_err(efx, drv, efx->net_dev, |
1185 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1186 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1187 | n_channels = rc; | |
8ceee660 | 1188 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1189 | n_channels); |
8ceee660 BH |
1190 | } |
1191 | ||
1192 | if (rc == 0) { | |
a4900ac9 BH |
1193 | efx->n_channels = n_channels; |
1194 | if (separate_tx_channels) { | |
1195 | efx->n_tx_channels = | |
1196 | max(efx->n_channels / 2, 1U); | |
1197 | efx->n_rx_channels = | |
1198 | max(efx->n_channels - | |
1199 | efx->n_tx_channels, 1U); | |
1200 | } else { | |
1201 | efx->n_tx_channels = efx->n_channels; | |
1202 | efx->n_rx_channels = efx->n_channels; | |
1203 | } | |
64d8ad6d BH |
1204 | rc = efx_init_rx_cpu_rmap(efx, xentries); |
1205 | if (rc) { | |
1206 | pci_disable_msix(efx->pci_dev); | |
1207 | return rc; | |
1208 | } | |
a4900ac9 | 1209 | for (i = 0; i < n_channels; i++) |
f7d12cdc BH |
1210 | efx_get_channel(efx, i)->irq = |
1211 | xentries[i].vector; | |
8ceee660 BH |
1212 | } else { |
1213 | /* Fall back to single channel MSI */ | |
1214 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1215 | netif_err(efx, drv, efx->net_dev, |
1216 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1217 | } |
1218 | } | |
1219 | ||
1220 | /* Try single interrupt MSI */ | |
1221 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1222 | efx->n_channels = 1; |
a4900ac9 BH |
1223 | efx->n_rx_channels = 1; |
1224 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1225 | rc = pci_enable_msi(efx->pci_dev); |
1226 | if (rc == 0) { | |
f7d12cdc | 1227 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1228 | } else { |
62776d03 BH |
1229 | netif_err(efx, drv, efx->net_dev, |
1230 | "could not enable MSI\n"); | |
8ceee660 BH |
1231 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1232 | } | |
1233 | } | |
1234 | ||
1235 | /* Assume legacy interrupts */ | |
1236 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1237 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1238 | efx->n_rx_channels = 1; |
1239 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1240 | efx->legacy_irq = efx->pci_dev->irq; |
1241 | } | |
64d8ad6d BH |
1242 | |
1243 | return 0; | |
8ceee660 BH |
1244 | } |
1245 | ||
9f2cb71c BH |
1246 | /* Enable interrupts, then probe and start the event queues */ |
1247 | static void efx_start_interrupts(struct efx_nic *efx) | |
1248 | { | |
1249 | struct efx_channel *channel; | |
1250 | ||
1251 | if (efx->legacy_irq) | |
1252 | efx->legacy_irq_enabled = true; | |
1253 | efx_nic_enable_interrupts(efx); | |
1254 | ||
1255 | efx_for_each_channel(channel, efx) { | |
1256 | efx_init_eventq(channel); | |
1257 | efx_start_eventq(channel); | |
1258 | } | |
1259 | ||
1260 | efx_mcdi_mode_event(efx); | |
1261 | } | |
1262 | ||
1263 | static void efx_stop_interrupts(struct efx_nic *efx) | |
1264 | { | |
1265 | struct efx_channel *channel; | |
1266 | ||
1267 | efx_mcdi_mode_poll(efx); | |
1268 | ||
1269 | efx_nic_disable_interrupts(efx); | |
1270 | if (efx->legacy_irq) { | |
1271 | synchronize_irq(efx->legacy_irq); | |
1272 | efx->legacy_irq_enabled = false; | |
1273 | } | |
1274 | ||
1275 | efx_for_each_channel(channel, efx) { | |
1276 | if (channel->irq) | |
1277 | synchronize_irq(channel->irq); | |
1278 | ||
1279 | efx_stop_eventq(channel); | |
1280 | efx_fini_eventq(channel); | |
1281 | } | |
1282 | } | |
1283 | ||
8ceee660 BH |
1284 | static void efx_remove_interrupts(struct efx_nic *efx) |
1285 | { | |
1286 | struct efx_channel *channel; | |
1287 | ||
1288 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1289 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1290 | channel->irq = 0; |
1291 | pci_disable_msi(efx->pci_dev); | |
1292 | pci_disable_msix(efx->pci_dev); | |
1293 | ||
1294 | /* Remove legacy interrupt */ | |
1295 | efx->legacy_irq = 0; | |
1296 | } | |
1297 | ||
8831da7b | 1298 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1299 | { |
602a5322 BH |
1300 | struct efx_channel *channel; |
1301 | struct efx_tx_queue *tx_queue; | |
1302 | ||
97653431 | 1303 | efx->tx_channel_offset = |
a4900ac9 | 1304 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 BH |
1305 | |
1306 | /* We need to adjust the TX queue numbers if we have separate | |
1307 | * RX-only and TX-only channels. | |
1308 | */ | |
1309 | efx_for_each_channel(channel, efx) { | |
1310 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1311 | tx_queue->queue -= (efx->tx_channel_offset * | |
1312 | EFX_TXQ_TYPES); | |
1313 | } | |
8ceee660 BH |
1314 | } |
1315 | ||
1316 | static int efx_probe_nic(struct efx_nic *efx) | |
1317 | { | |
765c9f46 | 1318 | size_t i; |
8ceee660 BH |
1319 | int rc; |
1320 | ||
62776d03 | 1321 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1322 | |
1323 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1324 | rc = efx->type->probe(efx); |
8ceee660 BH |
1325 | if (rc) |
1326 | return rc; | |
1327 | ||
a4900ac9 | 1328 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1329 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1330 | rc = efx_probe_interrupts(efx); |
1331 | if (rc) | |
1332 | goto fail; | |
8ceee660 | 1333 | |
5d3a6fca BH |
1334 | if (efx->n_channels > 1) |
1335 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1336 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 BH |
1337 | efx->rx_indir_table[i] = |
1338 | ethtool_rxfh_indir_default(i, efx->n_rx_channels); | |
5d3a6fca | 1339 | |
8831da7b | 1340 | efx_set_channels(efx); |
c4f4adc7 BH |
1341 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1342 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1343 | |
1344 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1345 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1346 | true); | |
8ceee660 BH |
1347 | |
1348 | return 0; | |
64d8ad6d BH |
1349 | |
1350 | fail: | |
1351 | efx->type->remove(efx); | |
1352 | return rc; | |
8ceee660 BH |
1353 | } |
1354 | ||
1355 | static void efx_remove_nic(struct efx_nic *efx) | |
1356 | { | |
62776d03 | 1357 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1358 | |
1359 | efx_remove_interrupts(efx); | |
ef2b90ee | 1360 | efx->type->remove(efx); |
8ceee660 BH |
1361 | } |
1362 | ||
1363 | /************************************************************************** | |
1364 | * | |
1365 | * NIC startup/shutdown | |
1366 | * | |
1367 | *************************************************************************/ | |
1368 | ||
1369 | static int efx_probe_all(struct efx_nic *efx) | |
1370 | { | |
8ceee660 BH |
1371 | int rc; |
1372 | ||
8ceee660 BH |
1373 | rc = efx_probe_nic(efx); |
1374 | if (rc) { | |
62776d03 | 1375 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1376 | goto fail1; |
1377 | } | |
1378 | ||
8ceee660 BH |
1379 | rc = efx_probe_port(efx); |
1380 | if (rc) { | |
62776d03 | 1381 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1382 | goto fail2; |
1383 | } | |
1384 | ||
ecc910f5 | 1385 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
4642610c BH |
1386 | rc = efx_probe_channels(efx); |
1387 | if (rc) | |
1388 | goto fail3; | |
8ceee660 | 1389 | |
64eebcfd BH |
1390 | rc = efx_probe_filters(efx); |
1391 | if (rc) { | |
1392 | netif_err(efx, probe, efx->net_dev, | |
1393 | "failed to create filter tables\n"); | |
1394 | goto fail4; | |
1395 | } | |
1396 | ||
8ceee660 BH |
1397 | return 0; |
1398 | ||
64eebcfd BH |
1399 | fail4: |
1400 | efx_remove_channels(efx); | |
8ceee660 | 1401 | fail3: |
8ceee660 BH |
1402 | efx_remove_port(efx); |
1403 | fail2: | |
1404 | efx_remove_nic(efx); | |
1405 | fail1: | |
1406 | return rc; | |
1407 | } | |
1408 | ||
9f2cb71c BH |
1409 | /* Called after previous invocation(s) of efx_stop_all, restarts the port, |
1410 | * kernel transmit queues and NAPI processing, and ensures that the port is | |
1411 | * scheduled to be reconfigured. This function is safe to call multiple | |
1412 | * times when the NIC is in any state. | |
1413 | */ | |
8ceee660 BH |
1414 | static void efx_start_all(struct efx_nic *efx) |
1415 | { | |
8ceee660 BH |
1416 | EFX_ASSERT_RESET_SERIALISED(efx); |
1417 | ||
1418 | /* Check that it is appropriate to restart the interface. All | |
1419 | * of these flags are safe to read under just the rtnl lock */ | |
1420 | if (efx->port_enabled) | |
1421 | return; | |
1422 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1423 | return; | |
73ba7b68 | 1424 | if (!netif_running(efx->net_dev)) |
8ceee660 BH |
1425 | return; |
1426 | ||
8ceee660 | 1427 | efx_start_port(efx); |
9f2cb71c | 1428 | efx_start_datapath(efx); |
8880f4ec | 1429 | |
78c1f0a0 SH |
1430 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1431 | * event driven), we have to poll the PHY because after an event queue | |
1432 | * flush, we could have a missed a link state change */ | |
1433 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1434 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1435 | efx_monitor_interval); | |
78c1f0a0 SH |
1436 | } else { |
1437 | mutex_lock(&efx->mac_lock); | |
1438 | if (efx->phy_op->poll(efx)) | |
1439 | efx_link_status_changed(efx); | |
1440 | mutex_unlock(&efx->mac_lock); | |
1441 | } | |
55edc6e6 | 1442 | |
ef2b90ee | 1443 | efx->type->start_stats(efx); |
8ceee660 BH |
1444 | } |
1445 | ||
1446 | /* Flush all delayed work. Should only be called when no more delayed work | |
1447 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1448 | * since we're holding the rtnl_lock at this point. */ | |
1449 | static void efx_flush_all(struct efx_nic *efx) | |
1450 | { | |
8ceee660 BH |
1451 | /* Make sure the hardware monitor is stopped */ |
1452 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1453 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1454 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1455 | } |
1456 | ||
1457 | /* Quiesce hardware and software without bringing the link down. | |
1458 | * Safe to call multiple times, when the nic and interface is in any | |
1459 | * state. The caller is guaranteed to subsequently be in a position | |
1460 | * to modify any hardware and software state they see fit without | |
1461 | * taking locks. */ | |
1462 | static void efx_stop_all(struct efx_nic *efx) | |
1463 | { | |
8ceee660 BH |
1464 | EFX_ASSERT_RESET_SERIALISED(efx); |
1465 | ||
1466 | /* port_enabled can be read safely under the rtnl lock */ | |
1467 | if (!efx->port_enabled) | |
1468 | return; | |
1469 | ||
ef2b90ee | 1470 | efx->type->stop_stats(efx); |
8ceee660 BH |
1471 | efx_stop_port(efx); |
1472 | ||
fdaa9aed | 1473 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1474 | efx_flush_all(efx); |
1475 | ||
8ceee660 BH |
1476 | /* Stop the kernel transmit interface late, so the watchdog |
1477 | * timer isn't ticking over the flush */ | |
9f2cb71c BH |
1478 | netif_tx_disable(efx->net_dev); |
1479 | ||
1480 | efx_stop_datapath(efx); | |
8ceee660 BH |
1481 | } |
1482 | ||
1483 | static void efx_remove_all(struct efx_nic *efx) | |
1484 | { | |
64eebcfd | 1485 | efx_remove_filters(efx); |
4642610c | 1486 | efx_remove_channels(efx); |
8ceee660 BH |
1487 | efx_remove_port(efx); |
1488 | efx_remove_nic(efx); | |
1489 | } | |
1490 | ||
8ceee660 BH |
1491 | /************************************************************************** |
1492 | * | |
1493 | * Interrupt moderation | |
1494 | * | |
1495 | **************************************************************************/ | |
1496 | ||
cc180b69 | 1497 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1498 | { |
b548f976 BH |
1499 | if (usecs == 0) |
1500 | return 0; | |
cc180b69 | 1501 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1502 | return 1; /* never round down to 0 */ |
cc180b69 | 1503 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1504 | } |
1505 | ||
8ceee660 | 1506 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1507 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1508 | unsigned int rx_usecs, bool rx_adaptive, | |
1509 | bool rx_may_override_tx) | |
8ceee660 | 1510 | { |
f7d12cdc | 1511 | struct efx_channel *channel; |
cc180b69 BH |
1512 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1513 | efx->timer_quantum_ns, | |
1514 | 1000); | |
1515 | unsigned int tx_ticks; | |
1516 | unsigned int rx_ticks; | |
8ceee660 BH |
1517 | |
1518 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1519 | ||
cc180b69 | 1520 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1521 | return -EINVAL; |
1522 | ||
cc180b69 BH |
1523 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1524 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1525 | ||
9e393b30 BH |
1526 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1527 | !rx_may_override_tx) { | |
1528 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1529 | "RX and TX IRQ moderation must be equal\n"); | |
1530 | return -EINVAL; | |
1531 | } | |
1532 | ||
6fb70fd1 | 1533 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1534 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1535 | efx_for_each_channel(channel, efx) { |
525da907 | 1536 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1537 | channel->irq_moderation = rx_ticks; |
525da907 | 1538 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1539 | channel->irq_moderation = tx_ticks; |
1540 | } | |
9e393b30 BH |
1541 | |
1542 | return 0; | |
8ceee660 BH |
1543 | } |
1544 | ||
a0c4faf5 BH |
1545 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1546 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1547 | { | |
cc180b69 BH |
1548 | /* We must round up when converting ticks to microseconds |
1549 | * because we round down when converting the other way. | |
1550 | */ | |
1551 | ||
a0c4faf5 | 1552 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1553 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1554 | efx->timer_quantum_ns, | |
1555 | 1000); | |
a0c4faf5 BH |
1556 | |
1557 | /* If channels are shared between RX and TX, so is IRQ | |
1558 | * moderation. Otherwise, IRQ moderation is the same for all | |
1559 | * TX channels and is not adaptive. | |
1560 | */ | |
1561 | if (efx->tx_channel_offset == 0) | |
1562 | *tx_usecs = *rx_usecs; | |
1563 | else | |
cc180b69 | 1564 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1565 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1566 | efx->timer_quantum_ns, |
1567 | 1000); | |
a0c4faf5 BH |
1568 | } |
1569 | ||
8ceee660 BH |
1570 | /************************************************************************** |
1571 | * | |
1572 | * Hardware monitor | |
1573 | * | |
1574 | **************************************************************************/ | |
1575 | ||
e254c274 | 1576 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1577 | static void efx_monitor(struct work_struct *data) |
1578 | { | |
1579 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1580 | monitor_work.work); | |
8ceee660 | 1581 | |
62776d03 BH |
1582 | netif_vdbg(efx, timer, efx->net_dev, |
1583 | "hardware monitor executing on CPU %d\n", | |
1584 | raw_smp_processor_id()); | |
ef2b90ee | 1585 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1586 | |
8ceee660 BH |
1587 | /* If the mac_lock is already held then it is likely a port |
1588 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1589 | * most of the work of monitor() anyway. */ |
1590 | if (mutex_trylock(&efx->mac_lock)) { | |
1591 | if (efx->port_enabled) | |
1592 | efx->type->monitor(efx); | |
1593 | mutex_unlock(&efx->mac_lock); | |
1594 | } | |
8ceee660 | 1595 | |
8ceee660 BH |
1596 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1597 | efx_monitor_interval); | |
1598 | } | |
1599 | ||
1600 | /************************************************************************** | |
1601 | * | |
1602 | * ioctls | |
1603 | * | |
1604 | *************************************************************************/ | |
1605 | ||
1606 | /* Net device ioctl | |
1607 | * Context: process, rtnl_lock() held. | |
1608 | */ | |
1609 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1610 | { | |
767e468c | 1611 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1612 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1613 | |
1614 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1615 | ||
68e7f45e BH |
1616 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1617 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1618 | (data->phy_id & 0xfc00) == 0x0400) | |
1619 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1620 | ||
1621 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1622 | } |
1623 | ||
1624 | /************************************************************************** | |
1625 | * | |
1626 | * NAPI interface | |
1627 | * | |
1628 | **************************************************************************/ | |
1629 | ||
e8f14992 | 1630 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1631 | { |
1632 | struct efx_channel *channel; | |
8ceee660 BH |
1633 | |
1634 | efx_for_each_channel(channel, efx) { | |
1635 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1636 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1637 | efx_poll, napi_weight); | |
8ceee660 | 1638 | } |
e8f14992 BH |
1639 | } |
1640 | ||
1641 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1642 | { | |
1643 | if (channel->napi_dev) | |
1644 | netif_napi_del(&channel->napi_str); | |
1645 | channel->napi_dev = NULL; | |
8ceee660 BH |
1646 | } |
1647 | ||
1648 | static void efx_fini_napi(struct efx_nic *efx) | |
1649 | { | |
1650 | struct efx_channel *channel; | |
1651 | ||
e8f14992 BH |
1652 | efx_for_each_channel(channel, efx) |
1653 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1654 | } |
1655 | ||
1656 | /************************************************************************** | |
1657 | * | |
1658 | * Kernel netpoll interface | |
1659 | * | |
1660 | *************************************************************************/ | |
1661 | ||
1662 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1663 | ||
1664 | /* Although in the common case interrupts will be disabled, this is not | |
1665 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1666 | * so no locking is required. | |
1667 | */ | |
1668 | static void efx_netpoll(struct net_device *net_dev) | |
1669 | { | |
767e468c | 1670 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1671 | struct efx_channel *channel; |
1672 | ||
64ee3120 | 1673 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1674 | efx_schedule_channel(channel); |
1675 | } | |
1676 | ||
1677 | #endif | |
1678 | ||
1679 | /************************************************************************** | |
1680 | * | |
1681 | * Kernel net device interface | |
1682 | * | |
1683 | *************************************************************************/ | |
1684 | ||
1685 | /* Context: process, rtnl_lock() held. */ | |
1686 | static int efx_net_open(struct net_device *net_dev) | |
1687 | { | |
767e468c | 1688 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1689 | EFX_ASSERT_RESET_SERIALISED(efx); |
1690 | ||
62776d03 BH |
1691 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1692 | raw_smp_processor_id()); | |
8ceee660 | 1693 | |
f4bd954e BH |
1694 | if (efx->state == STATE_DISABLED) |
1695 | return -EIO; | |
f8b87c17 BH |
1696 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1697 | return -EBUSY; | |
8880f4ec BH |
1698 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1699 | return -EIO; | |
f8b87c17 | 1700 | |
78c1f0a0 SH |
1701 | /* Notify the kernel of the link state polled during driver load, |
1702 | * before the monitor starts running */ | |
1703 | efx_link_status_changed(efx); | |
1704 | ||
8ceee660 BH |
1705 | efx_start_all(efx); |
1706 | return 0; | |
1707 | } | |
1708 | ||
1709 | /* Context: process, rtnl_lock() held. | |
1710 | * Note that the kernel will ignore our return code; this method | |
1711 | * should really be a void. | |
1712 | */ | |
1713 | static int efx_net_stop(struct net_device *net_dev) | |
1714 | { | |
767e468c | 1715 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1716 | |
62776d03 BH |
1717 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1718 | raw_smp_processor_id()); | |
8ceee660 | 1719 | |
f4bd954e BH |
1720 | if (efx->state != STATE_DISABLED) { |
1721 | /* Stop the device and flush all the channels */ | |
1722 | efx_stop_all(efx); | |
f4bd954e | 1723 | } |
8ceee660 BH |
1724 | |
1725 | return 0; | |
1726 | } | |
1727 | ||
5b9e207c | 1728 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
1729 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
1730 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 1731 | { |
767e468c | 1732 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1733 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1734 | |
55edc6e6 | 1735 | spin_lock_bh(&efx->stats_lock); |
1cb34522 | 1736 | |
ef2b90ee | 1737 | efx->type->update_stats(efx); |
8ceee660 BH |
1738 | |
1739 | stats->rx_packets = mac_stats->rx_packets; | |
1740 | stats->tx_packets = mac_stats->tx_packets; | |
1741 | stats->rx_bytes = mac_stats->rx_bytes; | |
1742 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1743 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1744 | stats->multicast = mac_stats->rx_multicast; |
1745 | stats->collisions = mac_stats->tx_collision; | |
1746 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1747 | mac_stats->rx_length_error); | |
8ceee660 BH |
1748 | stats->rx_crc_errors = mac_stats->rx_bad; |
1749 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1750 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1751 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1752 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1753 | ||
1754 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1755 | stats->rx_crc_errors + |
1756 | stats->rx_frame_errors + | |
8ceee660 BH |
1757 | mac_stats->rx_symbol_error); |
1758 | stats->tx_errors = (stats->tx_window_errors + | |
1759 | mac_stats->tx_bad); | |
1760 | ||
1cb34522 BH |
1761 | spin_unlock_bh(&efx->stats_lock); |
1762 | ||
8ceee660 BH |
1763 | return stats; |
1764 | } | |
1765 | ||
1766 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1767 | static void efx_watchdog(struct net_device *net_dev) | |
1768 | { | |
767e468c | 1769 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1770 | |
62776d03 BH |
1771 | netif_err(efx, tx_err, efx->net_dev, |
1772 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1773 | efx->port_enabled); | |
8ceee660 | 1774 | |
739bb23d | 1775 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1776 | } |
1777 | ||
1778 | ||
1779 | /* Context: process, rtnl_lock() held. */ | |
1780 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1781 | { | |
767e468c | 1782 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1783 | |
1784 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1785 | ||
1786 | if (new_mtu > EFX_MAX_MTU) | |
1787 | return -EINVAL; | |
1788 | ||
1789 | efx_stop_all(efx); | |
1790 | ||
62776d03 | 1791 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 1792 | |
d3245b28 BH |
1793 | mutex_lock(&efx->mac_lock); |
1794 | /* Reconfigure the MAC before enabling the dma queues so that | |
1795 | * the RX buffers don't overflow */ | |
8ceee660 | 1796 | net_dev->mtu = new_mtu; |
710b208d | 1797 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1798 | mutex_unlock(&efx->mac_lock); |
1799 | ||
8ceee660 | 1800 | efx_start_all(efx); |
6c8eef4a | 1801 | return 0; |
8ceee660 BH |
1802 | } |
1803 | ||
1804 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1805 | { | |
767e468c | 1806 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1807 | struct sockaddr *addr = data; |
1808 | char *new_addr = addr->sa_data; | |
1809 | ||
1810 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1811 | ||
1812 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1813 | netif_err(efx, drv, efx->net_dev, |
1814 | "invalid ethernet MAC address requested: %pM\n", | |
1815 | new_addr); | |
8ceee660 BH |
1816 | return -EINVAL; |
1817 | } | |
1818 | ||
1819 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1820 | ||
1821 | /* Reconfigure the MAC */ | |
d3245b28 | 1822 | mutex_lock(&efx->mac_lock); |
710b208d | 1823 | efx->type->reconfigure_mac(efx); |
d3245b28 | 1824 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
1825 | |
1826 | return 0; | |
1827 | } | |
1828 | ||
a816f75a | 1829 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 1830 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 1831 | { |
767e468c | 1832 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1833 | struct netdev_hw_addr *ha; |
8ceee660 | 1834 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1835 | u32 crc; |
1836 | int bit; | |
8ceee660 | 1837 | |
8be4f3e6 | 1838 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1839 | |
1840 | /* Build multicast hash table */ | |
8be4f3e6 | 1841 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1842 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1843 | } else { | |
1844 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1845 | netdev_for_each_mc_addr(ha, net_dev) { |
1846 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1847 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1848 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1849 | } |
8ceee660 | 1850 | |
8be4f3e6 BH |
1851 | /* Broadcast packets go through the multicast hash filter. |
1852 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1853 | * so we always add bit 0xff to the mask. | |
1854 | */ | |
1855 | set_bit_le(0xff, mc_hash->byte); | |
1856 | } | |
a816f75a | 1857 | |
8be4f3e6 BH |
1858 | if (efx->port_enabled) |
1859 | queue_work(efx->workqueue, &efx->mac_work); | |
1860 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1861 | } |
1862 | ||
c8f44aff | 1863 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
1864 | { |
1865 | struct efx_nic *efx = netdev_priv(net_dev); | |
1866 | ||
1867 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
1868 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
1869 | efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
1870 | ||
1871 | return 0; | |
1872 | } | |
1873 | ||
c3ecb9f3 SH |
1874 | static const struct net_device_ops efx_netdev_ops = { |
1875 | .ndo_open = efx_net_open, | |
1876 | .ndo_stop = efx_net_stop, | |
4472702e | 1877 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
1878 | .ndo_tx_timeout = efx_watchdog, |
1879 | .ndo_start_xmit = efx_hard_start_xmit, | |
1880 | .ndo_validate_addr = eth_validate_addr, | |
1881 | .ndo_do_ioctl = efx_ioctl, | |
1882 | .ndo_change_mtu = efx_change_mtu, | |
1883 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 1884 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 1885 | .ndo_set_features = efx_set_features, |
c3ecb9f3 SH |
1886 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1887 | .ndo_poll_controller = efx_netpoll, | |
1888 | #endif | |
94b274bf | 1889 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
1890 | #ifdef CONFIG_RFS_ACCEL |
1891 | .ndo_rx_flow_steer = efx_filter_rfs, | |
1892 | #endif | |
c3ecb9f3 SH |
1893 | }; |
1894 | ||
7dde596e BH |
1895 | static void efx_update_name(struct efx_nic *efx) |
1896 | { | |
1897 | strcpy(efx->name, efx->net_dev->name); | |
1898 | efx_mtd_rename(efx); | |
1899 | efx_set_channel_names(efx); | |
1900 | } | |
1901 | ||
8ceee660 BH |
1902 | static int efx_netdev_event(struct notifier_block *this, |
1903 | unsigned long event, void *ptr) | |
1904 | { | |
d3208b5e | 1905 | struct net_device *net_dev = ptr; |
8ceee660 | 1906 | |
7dde596e BH |
1907 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1908 | event == NETDEV_CHANGENAME) | |
1909 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1910 | |
1911 | return NOTIFY_DONE; | |
1912 | } | |
1913 | ||
1914 | static struct notifier_block efx_netdev_notifier = { | |
1915 | .notifier_call = efx_netdev_event, | |
1916 | }; | |
1917 | ||
06d5e193 BH |
1918 | static ssize_t |
1919 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1920 | { | |
1921 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1922 | return sprintf(buf, "%d\n", efx->phy_type); | |
1923 | } | |
1924 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1925 | ||
8ceee660 BH |
1926 | static int efx_register_netdev(struct efx_nic *efx) |
1927 | { | |
1928 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 1929 | struct efx_channel *channel; |
8ceee660 BH |
1930 | int rc; |
1931 | ||
1932 | net_dev->watchdog_timeo = 5 * HZ; | |
1933 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1934 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1935 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
1936 | ||
7dde596e | 1937 | rtnl_lock(); |
aed0628d BH |
1938 | |
1939 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1940 | if (rc < 0) | |
1941 | goto fail_locked; | |
7dde596e | 1942 | efx_update_name(efx); |
aed0628d BH |
1943 | |
1944 | rc = register_netdevice(net_dev); | |
1945 | if (rc) | |
1946 | goto fail_locked; | |
1947 | ||
c04bfc6b BH |
1948 | efx_for_each_channel(channel, efx) { |
1949 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
1950 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1951 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
1952 | } |
1953 | ||
aed0628d | 1954 | /* Always start with carrier off; PHY events will detect the link */ |
86ee5302 | 1955 | netif_carrier_off(net_dev); |
aed0628d | 1956 | |
7dde596e | 1957 | rtnl_unlock(); |
8ceee660 | 1958 | |
06d5e193 BH |
1959 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1960 | if (rc) { | |
62776d03 BH |
1961 | netif_err(efx, drv, efx->net_dev, |
1962 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
1963 | goto fail_registered; |
1964 | } | |
1965 | ||
8ceee660 | 1966 | return 0; |
06d5e193 | 1967 | |
aed0628d BH |
1968 | fail_locked: |
1969 | rtnl_unlock(); | |
62776d03 | 1970 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
1971 | return rc; |
1972 | ||
06d5e193 BH |
1973 | fail_registered: |
1974 | unregister_netdev(net_dev); | |
1975 | return rc; | |
8ceee660 BH |
1976 | } |
1977 | ||
1978 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1979 | { | |
f7d12cdc | 1980 | struct efx_channel *channel; |
8ceee660 BH |
1981 | struct efx_tx_queue *tx_queue; |
1982 | ||
1983 | if (!efx->net_dev) | |
1984 | return; | |
1985 | ||
767e468c | 1986 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1987 | |
1988 | /* Free up any skbs still remaining. This has to happen before | |
1989 | * we try to unregister the netdev as running their destructors | |
1990 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
1991 | efx_for_each_channel(channel, efx) { |
1992 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1993 | efx_release_tx_buffers(tx_queue); | |
1994 | } | |
8ceee660 | 1995 | |
73ba7b68 BH |
1996 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
1997 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
1998 | unregister_netdev(efx->net_dev); | |
8ceee660 BH |
1999 | } |
2000 | ||
2001 | /************************************************************************** | |
2002 | * | |
2003 | * Device reset and suspend | |
2004 | * | |
2005 | **************************************************************************/ | |
2006 | ||
2467ca46 BH |
2007 | /* Tears down the entire software state and most of the hardware state |
2008 | * before reset. */ | |
d3245b28 | 2009 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2010 | { |
8ceee660 BH |
2011 | EFX_ASSERT_RESET_SERIALISED(efx); |
2012 | ||
2467ca46 BH |
2013 | efx_stop_all(efx); |
2014 | mutex_lock(&efx->mac_lock); | |
2015 | ||
9f2cb71c | 2016 | efx_stop_interrupts(efx); |
4b988280 SH |
2017 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2018 | efx->phy_op->fini(efx); | |
ef2b90ee | 2019 | efx->type->fini(efx); |
8ceee660 BH |
2020 | } |
2021 | ||
2467ca46 BH |
2022 | /* This function will always ensure that the locks acquired in |
2023 | * efx_reset_down() are released. A failure return code indicates | |
2024 | * that we were unable to reinitialise the hardware, and the | |
2025 | * driver should be disabled. If ok is false, then the rx and tx | |
2026 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2027 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2028 | { |
2029 | int rc; | |
2030 | ||
2467ca46 | 2031 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2032 | |
ef2b90ee | 2033 | rc = efx->type->init(efx); |
8ceee660 | 2034 | if (rc) { |
62776d03 | 2035 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2036 | goto fail; |
8ceee660 BH |
2037 | } |
2038 | ||
eb9f6744 BH |
2039 | if (!ok) |
2040 | goto fail; | |
2041 | ||
4b988280 | 2042 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2043 | rc = efx->phy_op->init(efx); |
2044 | if (rc) | |
2045 | goto fail; | |
2046 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2047 | netif_err(efx, drv, efx->net_dev, |
2048 | "could not restore PHY settings\n"); | |
4b988280 SH |
2049 | } |
2050 | ||
710b208d | 2051 | efx->type->reconfigure_mac(efx); |
8ceee660 | 2052 | |
9f2cb71c | 2053 | efx_start_interrupts(efx); |
64eebcfd | 2054 | efx_restore_filters(efx); |
eb9f6744 | 2055 | |
eb9f6744 BH |
2056 | mutex_unlock(&efx->mac_lock); |
2057 | ||
2058 | efx_start_all(efx); | |
2059 | ||
2060 | return 0; | |
2061 | ||
2062 | fail: | |
2063 | efx->port_initialized = false; | |
2467ca46 BH |
2064 | |
2065 | mutex_unlock(&efx->mac_lock); | |
2066 | ||
8ceee660 BH |
2067 | return rc; |
2068 | } | |
2069 | ||
eb9f6744 BH |
2070 | /* Reset the NIC using the specified method. Note that the reset may |
2071 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2072 | * |
eb9f6744 | 2073 | * Caller must hold the rtnl_lock. |
8ceee660 | 2074 | */ |
eb9f6744 | 2075 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2076 | { |
eb9f6744 BH |
2077 | int rc, rc2; |
2078 | bool disabled; | |
8ceee660 | 2079 | |
62776d03 BH |
2080 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2081 | RESET_TYPE(method)); | |
8ceee660 | 2082 | |
e4abce85 | 2083 | netif_device_detach(efx->net_dev); |
d3245b28 | 2084 | efx_reset_down(efx, method); |
8ceee660 | 2085 | |
ef2b90ee | 2086 | rc = efx->type->reset(efx, method); |
8ceee660 | 2087 | if (rc) { |
62776d03 | 2088 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2089 | goto out; |
8ceee660 BH |
2090 | } |
2091 | ||
a7d529ae BH |
2092 | /* Clear flags for the scopes we covered. We assume the NIC and |
2093 | * driver are now quiescent so that there is no race here. | |
2094 | */ | |
2095 | efx->reset_pending &= -(1 << (method + 1)); | |
8ceee660 BH |
2096 | |
2097 | /* Reinitialise bus-mastering, which may have been turned off before | |
2098 | * the reset was scheduled. This is still appropriate, even in the | |
2099 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2100 | * can respond to requests. */ | |
2101 | pci_set_master(efx->pci_dev); | |
2102 | ||
eb9f6744 | 2103 | out: |
8ceee660 | 2104 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2105 | disabled = rc || method == RESET_TYPE_DISABLE; |
2106 | rc2 = efx_reset_up(efx, method, !disabled); | |
2107 | if (rc2) { | |
2108 | disabled = true; | |
2109 | if (!rc) | |
2110 | rc = rc2; | |
8ceee660 BH |
2111 | } |
2112 | ||
eb9f6744 | 2113 | if (disabled) { |
f49a4589 | 2114 | dev_close(efx->net_dev); |
62776d03 | 2115 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2116 | efx->state = STATE_DISABLED; |
f4bd954e | 2117 | } else { |
62776d03 | 2118 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2119 | netif_device_attach(efx->net_dev); |
f4bd954e | 2120 | } |
8ceee660 BH |
2121 | return rc; |
2122 | } | |
2123 | ||
2124 | /* The worker thread exists so that code that cannot sleep can | |
2125 | * schedule a reset for later. | |
2126 | */ | |
2127 | static void efx_reset_work(struct work_struct *data) | |
2128 | { | |
eb9f6744 | 2129 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
a7d529ae | 2130 | unsigned long pending = ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 2131 | |
a7d529ae | 2132 | if (!pending) |
319ba649 SH |
2133 | return; |
2134 | ||
eb9f6744 | 2135 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
a7d529ae | 2136 | * flags set so that efx_pci_probe_main will be retried */ |
eb9f6744 | 2137 | if (efx->state != STATE_RUNNING) { |
62776d03 BH |
2138 | netif_info(efx, drv, efx->net_dev, |
2139 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
2140 | return; |
2141 | } | |
2142 | ||
2143 | rtnl_lock(); | |
a7d529ae | 2144 | (void)efx_reset(efx, fls(pending) - 1); |
eb9f6744 | 2145 | rtnl_unlock(); |
8ceee660 BH |
2146 | } |
2147 | ||
2148 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2149 | { | |
2150 | enum reset_type method; | |
2151 | ||
8ceee660 BH |
2152 | switch (type) { |
2153 | case RESET_TYPE_INVISIBLE: | |
2154 | case RESET_TYPE_ALL: | |
2155 | case RESET_TYPE_WORLD: | |
2156 | case RESET_TYPE_DISABLE: | |
2157 | method = type; | |
0e2a9c7c BH |
2158 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2159 | RESET_TYPE(method)); | |
8ceee660 | 2160 | break; |
8ceee660 | 2161 | default: |
0e2a9c7c | 2162 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2163 | netif_dbg(efx, drv, efx->net_dev, |
2164 | "scheduling %s reset for %s\n", | |
2165 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2166 | break; |
2167 | } | |
8ceee660 | 2168 | |
a7d529ae | 2169 | set_bit(method, &efx->reset_pending); |
8ceee660 | 2170 | |
8880f4ec BH |
2171 | /* efx_process_channel() will no longer read events once a |
2172 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2173 | efx_mcdi_mode_poll(efx); | |
2174 | ||
1ab00629 | 2175 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2176 | } |
2177 | ||
2178 | /************************************************************************** | |
2179 | * | |
2180 | * List of NICs we support | |
2181 | * | |
2182 | **************************************************************************/ | |
2183 | ||
2184 | /* PCI device ID table */ | |
a3aa1884 | 2185 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2186 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2187 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2188 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2189 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2190 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2191 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2192 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2193 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2194 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2195 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8ceee660 BH |
2196 | {0} /* end of list */ |
2197 | }; | |
2198 | ||
2199 | /************************************************************************** | |
2200 | * | |
3759433d | 2201 | * Dummy PHY/MAC operations |
8ceee660 | 2202 | * |
01aad7b6 | 2203 | * Can be used for some unimplemented operations |
8ceee660 BH |
2204 | * Needed so all function pointers are valid and do not have to be tested |
2205 | * before use | |
2206 | * | |
2207 | **************************************************************************/ | |
2208 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2209 | { | |
2210 | return 0; | |
2211 | } | |
2212 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2213 | |
2214 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2215 | { |
2216 | return false; | |
2217 | } | |
8ceee660 | 2218 | |
6c8c2513 | 2219 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2220 | .init = efx_port_dummy_op_int, |
d3245b28 | 2221 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2222 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2223 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2224 | }; |
2225 | ||
8ceee660 BH |
2226 | /************************************************************************** |
2227 | * | |
2228 | * Data housekeeping | |
2229 | * | |
2230 | **************************************************************************/ | |
2231 | ||
2232 | /* This zeroes out and then fills in the invariants in a struct | |
2233 | * efx_nic (including all sub-structures). | |
2234 | */ | |
6c8c2513 | 2235 | static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type, |
8ceee660 BH |
2236 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2237 | { | |
4642610c | 2238 | int i; |
8ceee660 BH |
2239 | |
2240 | /* Initialise common structures */ | |
2241 | memset(efx, 0, sizeof(*efx)); | |
2242 | spin_lock_init(&efx->biu_lock); | |
76884835 BH |
2243 | #ifdef CONFIG_SFC_MTD |
2244 | INIT_LIST_HEAD(&efx->mtd_list); | |
2245 | #endif | |
8ceee660 BH |
2246 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2247 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2248 | efx->pci_dev = pci_dev; | |
62776d03 | 2249 | efx->msg_enable = debug; |
8ceee660 | 2250 | efx->state = STATE_INIT; |
8ceee660 | 2251 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2252 | |
2253 | efx->net_dev = net_dev; | |
8ceee660 BH |
2254 | spin_lock_init(&efx->stats_lock); |
2255 | mutex_init(&efx->mac_lock); | |
2256 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2257 | efx->mdio.dev = net_dev; |
766ca0fa | 2258 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2259 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2260 | |
2261 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2262 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2263 | if (!efx->channel[i]) | |
2264 | goto fail; | |
8ceee660 BH |
2265 | } |
2266 | ||
2267 | efx->type = type; | |
2268 | ||
8ceee660 BH |
2269 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2270 | ||
2271 | /* Higher numbered interrupt modes are less capable! */ | |
2272 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2273 | interrupt_mode); | |
2274 | ||
6977dc63 BH |
2275 | /* Would be good to use the net_dev name, but we're too early */ |
2276 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2277 | pci_name(pci_dev)); | |
2278 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2279 | if (!efx->workqueue) |
4642610c | 2280 | goto fail; |
8d9853d9 | 2281 | |
8ceee660 | 2282 | return 0; |
4642610c BH |
2283 | |
2284 | fail: | |
2285 | efx_fini_struct(efx); | |
2286 | return -ENOMEM; | |
8ceee660 BH |
2287 | } |
2288 | ||
2289 | static void efx_fini_struct(struct efx_nic *efx) | |
2290 | { | |
8313aca3 BH |
2291 | int i; |
2292 | ||
2293 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2294 | kfree(efx->channel[i]); | |
2295 | ||
8ceee660 BH |
2296 | if (efx->workqueue) { |
2297 | destroy_workqueue(efx->workqueue); | |
2298 | efx->workqueue = NULL; | |
2299 | } | |
2300 | } | |
2301 | ||
2302 | /************************************************************************** | |
2303 | * | |
2304 | * PCI interface | |
2305 | * | |
2306 | **************************************************************************/ | |
2307 | ||
2308 | /* Main body of final NIC shutdown code | |
2309 | * This is called only at module unload (or hotplug removal). | |
2310 | */ | |
2311 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2312 | { | |
64d8ad6d BH |
2313 | #ifdef CONFIG_RFS_ACCEL |
2314 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
2315 | efx->net_dev->rx_cpu_rmap = NULL; | |
2316 | #endif | |
9f2cb71c | 2317 | efx_stop_interrupts(efx); |
152b6a62 | 2318 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2319 | efx_fini_port(efx); |
ef2b90ee | 2320 | efx->type->fini(efx); |
8ceee660 BH |
2321 | efx_fini_napi(efx); |
2322 | efx_remove_all(efx); | |
2323 | } | |
2324 | ||
2325 | /* Final NIC shutdown | |
2326 | * This is called only at module unload (or hotplug removal). | |
2327 | */ | |
2328 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2329 | { | |
2330 | struct efx_nic *efx; | |
2331 | ||
2332 | efx = pci_get_drvdata(pci_dev); | |
2333 | if (!efx) | |
2334 | return; | |
2335 | ||
2336 | /* Mark the NIC as fini, then stop the interface */ | |
2337 | rtnl_lock(); | |
2338 | efx->state = STATE_FINI; | |
2339 | dev_close(efx->net_dev); | |
2340 | ||
2341 | /* Allow any queued efx_resets() to complete */ | |
2342 | rtnl_unlock(); | |
2343 | ||
9f2cb71c | 2344 | efx_stop_interrupts(efx); |
8ceee660 BH |
2345 | efx_unregister_netdev(efx); |
2346 | ||
7dde596e BH |
2347 | efx_mtd_remove(efx); |
2348 | ||
8ceee660 BH |
2349 | /* Wait for any scheduled resets to complete. No more will be |
2350 | * scheduled from this point because efx_stop_all() has been | |
2351 | * called, we are no longer registered with driverlink, and | |
2352 | * the net_device's have been removed. */ | |
1ab00629 | 2353 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2354 | |
2355 | efx_pci_remove_main(efx); | |
2356 | ||
8ceee660 | 2357 | efx_fini_io(efx); |
62776d03 | 2358 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 BH |
2359 | |
2360 | pci_set_drvdata(pci_dev, NULL); | |
2361 | efx_fini_struct(efx); | |
2362 | free_netdev(efx->net_dev); | |
2363 | }; | |
2364 | ||
2365 | /* Main body of NIC initialisation | |
2366 | * This is called at module load (or hotplug insertion, theoretically). | |
2367 | */ | |
2368 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2369 | { | |
2370 | int rc; | |
2371 | ||
2372 | /* Do start-of-day initialisation */ | |
2373 | rc = efx_probe_all(efx); | |
2374 | if (rc) | |
2375 | goto fail1; | |
2376 | ||
e8f14992 | 2377 | efx_init_napi(efx); |
8ceee660 | 2378 | |
ef2b90ee | 2379 | rc = efx->type->init(efx); |
8ceee660 | 2380 | if (rc) { |
62776d03 BH |
2381 | netif_err(efx, probe, efx->net_dev, |
2382 | "failed to initialise NIC\n"); | |
278c0621 | 2383 | goto fail3; |
8ceee660 BH |
2384 | } |
2385 | ||
2386 | rc = efx_init_port(efx); | |
2387 | if (rc) { | |
62776d03 BH |
2388 | netif_err(efx, probe, efx->net_dev, |
2389 | "failed to initialise port\n"); | |
278c0621 | 2390 | goto fail4; |
8ceee660 BH |
2391 | } |
2392 | ||
152b6a62 | 2393 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2394 | if (rc) |
278c0621 | 2395 | goto fail5; |
9f2cb71c | 2396 | efx_start_interrupts(efx); |
8ceee660 BH |
2397 | |
2398 | return 0; | |
2399 | ||
278c0621 | 2400 | fail5: |
8ceee660 | 2401 | efx_fini_port(efx); |
8ceee660 | 2402 | fail4: |
ef2b90ee | 2403 | efx->type->fini(efx); |
8ceee660 BH |
2404 | fail3: |
2405 | efx_fini_napi(efx); | |
8ceee660 BH |
2406 | efx_remove_all(efx); |
2407 | fail1: | |
2408 | return rc; | |
2409 | } | |
2410 | ||
2411 | /* NIC initialisation | |
2412 | * | |
2413 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2414 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2415 | * sets up and registers the network devices with the kernel and hooks |
2416 | * the interrupt service routine. It does not prepare the device for | |
2417 | * transmission; this is left to the first time one of the network | |
2418 | * interfaces is brought up (i.e. efx_net_open). | |
2419 | */ | |
2420 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2421 | const struct pci_device_id *entry) | |
2422 | { | |
6c8c2513 | 2423 | const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data; |
8ceee660 BH |
2424 | struct net_device *net_dev; |
2425 | struct efx_nic *efx; | |
fadac6aa | 2426 | int rc; |
8ceee660 BH |
2427 | |
2428 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2429 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2430 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2431 | if (!net_dev) |
2432 | return -ENOMEM; | |
c383b537 | 2433 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 | 2434 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2435 | NETIF_F_RXCSUM); |
738a8f4b BH |
2436 | if (type->offload_features & NETIF_F_V6_CSUM) |
2437 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2438 | /* Mask for features that also apply to VLAN devices */ |
2439 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2440 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2441 | NETIF_F_RXCSUM); | |
2442 | /* All offloads can be toggled */ | |
2443 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
767e468c | 2444 | efx = netdev_priv(net_dev); |
8ceee660 | 2445 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2446 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2447 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2448 | if (rc) | |
2449 | goto fail1; | |
2450 | ||
62776d03 | 2451 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2452 | "Solarflare NIC detected\n"); |
8ceee660 BH |
2453 | |
2454 | /* Set up basic I/O (BAR mappings etc) */ | |
2455 | rc = efx_init_io(efx); | |
2456 | if (rc) | |
2457 | goto fail2; | |
2458 | ||
fadac6aa | 2459 | rc = efx_pci_probe_main(efx); |
fa402b2e | 2460 | |
fadac6aa BH |
2461 | /* Serialise against efx_reset(). No more resets will be |
2462 | * scheduled since efx_stop_all() has been called, and we have | |
2463 | * not and never have been registered. | |
2464 | */ | |
2465 | cancel_work_sync(&efx->reset_work); | |
8ceee660 | 2466 | |
fadac6aa BH |
2467 | if (rc) |
2468 | goto fail3; | |
8ceee660 | 2469 | |
fadac6aa BH |
2470 | /* If there was a scheduled reset during probe, the NIC is |
2471 | * probably hosed anyway. | |
2472 | */ | |
2473 | if (efx->reset_pending) { | |
2474 | rc = -EIO; | |
8ceee660 BH |
2475 | goto fail4; |
2476 | } | |
2477 | ||
55edc6e6 BH |
2478 | /* Switch to the running state before we expose the device to the OS, |
2479 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2480 | efx->state = STATE_RUNNING; |
7dde596e | 2481 | |
8ceee660 BH |
2482 | rc = efx_register_netdev(efx); |
2483 | if (rc) | |
fadac6aa | 2484 | goto fail4; |
8ceee660 | 2485 | |
62776d03 | 2486 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 2487 | |
7c43161c | 2488 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 2489 | rtnl_lock(); |
7c43161c | 2490 | rc = efx_mtd_probe(efx); |
a5211bb5 | 2491 | rtnl_unlock(); |
7c43161c BH |
2492 | if (rc) |
2493 | netif_warn(efx, probe, efx->net_dev, | |
2494 | "failed to create MTDs (%d)\n", rc); | |
2495 | ||
8ceee660 BH |
2496 | return 0; |
2497 | ||
8ceee660 | 2498 | fail4: |
fadac6aa | 2499 | efx_pci_remove_main(efx); |
8ceee660 BH |
2500 | fail3: |
2501 | efx_fini_io(efx); | |
2502 | fail2: | |
2503 | efx_fini_struct(efx); | |
2504 | fail1: | |
5e2a911c | 2505 | WARN_ON(rc > 0); |
62776d03 | 2506 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2507 | free_netdev(net_dev); |
2508 | return rc; | |
2509 | } | |
2510 | ||
89c758fa BH |
2511 | static int efx_pm_freeze(struct device *dev) |
2512 | { | |
2513 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2514 | ||
2515 | efx->state = STATE_FINI; | |
2516 | ||
2517 | netif_device_detach(efx->net_dev); | |
2518 | ||
2519 | efx_stop_all(efx); | |
9f2cb71c | 2520 | efx_stop_interrupts(efx); |
89c758fa BH |
2521 | |
2522 | return 0; | |
2523 | } | |
2524 | ||
2525 | static int efx_pm_thaw(struct device *dev) | |
2526 | { | |
2527 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2528 | ||
2529 | efx->state = STATE_INIT; | |
2530 | ||
9f2cb71c | 2531 | efx_start_interrupts(efx); |
89c758fa BH |
2532 | |
2533 | mutex_lock(&efx->mac_lock); | |
2534 | efx->phy_op->reconfigure(efx); | |
2535 | mutex_unlock(&efx->mac_lock); | |
2536 | ||
2537 | efx_start_all(efx); | |
2538 | ||
2539 | netif_device_attach(efx->net_dev); | |
2540 | ||
2541 | efx->state = STATE_RUNNING; | |
2542 | ||
2543 | efx->type->resume_wol(efx); | |
2544 | ||
319ba649 SH |
2545 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2546 | queue_work(reset_workqueue, &efx->reset_work); | |
2547 | ||
89c758fa BH |
2548 | return 0; |
2549 | } | |
2550 | ||
2551 | static int efx_pm_poweroff(struct device *dev) | |
2552 | { | |
2553 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2554 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2555 | ||
2556 | efx->type->fini(efx); | |
2557 | ||
a7d529ae | 2558 | efx->reset_pending = 0; |
89c758fa BH |
2559 | |
2560 | pci_save_state(pci_dev); | |
2561 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2562 | } | |
2563 | ||
2564 | /* Used for both resume and restore */ | |
2565 | static int efx_pm_resume(struct device *dev) | |
2566 | { | |
2567 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2568 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2569 | int rc; | |
2570 | ||
2571 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2572 | if (rc) | |
2573 | return rc; | |
2574 | pci_restore_state(pci_dev); | |
2575 | rc = pci_enable_device(pci_dev); | |
2576 | if (rc) | |
2577 | return rc; | |
2578 | pci_set_master(efx->pci_dev); | |
2579 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2580 | if (rc) | |
2581 | return rc; | |
2582 | rc = efx->type->init(efx); | |
2583 | if (rc) | |
2584 | return rc; | |
2585 | efx_pm_thaw(dev); | |
2586 | return 0; | |
2587 | } | |
2588 | ||
2589 | static int efx_pm_suspend(struct device *dev) | |
2590 | { | |
2591 | int rc; | |
2592 | ||
2593 | efx_pm_freeze(dev); | |
2594 | rc = efx_pm_poweroff(dev); | |
2595 | if (rc) | |
2596 | efx_pm_resume(dev); | |
2597 | return rc; | |
2598 | } | |
2599 | ||
18e83e4c | 2600 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
2601 | .suspend = efx_pm_suspend, |
2602 | .resume = efx_pm_resume, | |
2603 | .freeze = efx_pm_freeze, | |
2604 | .thaw = efx_pm_thaw, | |
2605 | .poweroff = efx_pm_poweroff, | |
2606 | .restore = efx_pm_resume, | |
2607 | }; | |
2608 | ||
8ceee660 | 2609 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2610 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2611 | .id_table = efx_pci_table, |
2612 | .probe = efx_pci_probe, | |
2613 | .remove = efx_pci_remove, | |
89c758fa | 2614 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2615 | }; |
2616 | ||
2617 | /************************************************************************** | |
2618 | * | |
2619 | * Kernel module interface | |
2620 | * | |
2621 | *************************************************************************/ | |
2622 | ||
2623 | module_param(interrupt_mode, uint, 0444); | |
2624 | MODULE_PARM_DESC(interrupt_mode, | |
2625 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2626 | ||
2627 | static int __init efx_init_module(void) | |
2628 | { | |
2629 | int rc; | |
2630 | ||
2631 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2632 | ||
2633 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2634 | if (rc) | |
2635 | goto err_notifier; | |
2636 | ||
1ab00629 SH |
2637 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2638 | if (!reset_workqueue) { | |
2639 | rc = -ENOMEM; | |
2640 | goto err_reset; | |
2641 | } | |
8ceee660 BH |
2642 | |
2643 | rc = pci_register_driver(&efx_pci_driver); | |
2644 | if (rc < 0) | |
2645 | goto err_pci; | |
2646 | ||
2647 | return 0; | |
2648 | ||
2649 | err_pci: | |
1ab00629 SH |
2650 | destroy_workqueue(reset_workqueue); |
2651 | err_reset: | |
8ceee660 BH |
2652 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2653 | err_notifier: | |
2654 | return rc; | |
2655 | } | |
2656 | ||
2657 | static void __exit efx_exit_module(void) | |
2658 | { | |
2659 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2660 | ||
2661 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2662 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2663 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2664 | ||
2665 | } | |
2666 | ||
2667 | module_init(efx_init_module); | |
2668 | module_exit(efx_exit_module); | |
2669 | ||
906bb26c BH |
2670 | MODULE_AUTHOR("Solarflare Communications and " |
2671 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2672 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2673 | MODULE_LICENSE("GPL"); | |
2674 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |