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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
64d8ad6d | 24 | #include <linux/cpu_rmap.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
41 | const char *efx_loopback_mode_names[] = { | |
42 | [LOOPBACK_NONE] = "NONE", | |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
47 | [LOOPBACK_XAUI] = "XAUI", | |
e58f69f4 BH |
48 | [LOOPBACK_GMII] = "GMII", |
49 | [LOOPBACK_SGMII] = "SGMII", | |
50 | [LOOPBACK_XGBR] = "XGBR", | |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
58 | [LOOPBACK_PCS] = "PCS", | |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", | |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", | |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
65 | [LOOPBACK_GMII_WS] = "GMII_WS", | |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", | |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", | |
c459302d BH |
69 | }; |
70 | ||
c459302d BH |
71 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
72 | const char *efx_reset_type_names[] = { | |
73 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", | |
74 | [RESET_TYPE_ALL] = "ALL", | |
75 | [RESET_TYPE_WORLD] = "WORLD", | |
76 | [RESET_TYPE_DISABLE] = "DISABLE", | |
77 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
78 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
79 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
80 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
81 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 83 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
84 | }; |
85 | ||
8ceee660 BH |
86 | #define EFX_MAX_MTU (9 * 1024) |
87 | ||
1ab00629 SH |
88 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
89 | * queued onto this work queue. This is not a per-nic work queue, because | |
90 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
91 | */ | |
92 | static struct workqueue_struct *reset_workqueue; | |
93 | ||
8ceee660 BH |
94 | /************************************************************************** |
95 | * | |
96 | * Configurable values | |
97 | * | |
98 | *************************************************************************/ | |
99 | ||
8ceee660 BH |
100 | /* |
101 | * Use separate channels for TX and RX events | |
102 | * | |
28b581ab NT |
103 | * Set this to 1 to use separate channels for TX and RX. It allows us |
104 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 105 | * |
28b581ab | 106 | * This is only used in MSI-X interrupt mode |
8ceee660 | 107 | */ |
28b581ab | 108 | static unsigned int separate_tx_channels; |
8313aca3 | 109 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
110 | MODULE_PARM_DESC(separate_tx_channels, |
111 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
112 | |
113 | /* This is the weight assigned to each of the (per-channel) virtual | |
114 | * NAPI devices. | |
115 | */ | |
116 | static int napi_weight = 64; | |
117 | ||
118 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
119 | * monitor. On Falcon-based NICs, this will: |
120 | * - Check the on-board hardware monitor; | |
121 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 122 | */ |
d215697f | 123 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 124 | |
8ceee660 BH |
125 | /* This controls whether or not the driver will initialise devices |
126 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
127 | * such devices will be initialised with a random locally-generated | |
128 | * MAC address. This allows for loading the sfc_mtd driver to | |
129 | * reprogram the flash, even if the flash contents (including the MAC | |
130 | * address) have previously been erased. | |
131 | */ | |
132 | static unsigned int allow_bad_hwaddr; | |
133 | ||
134 | /* Initial interrupt moderation settings. They can be modified after | |
135 | * module load with ethtool. | |
136 | * | |
137 | * The default for RX should strike a balance between increasing the | |
138 | * round-trip latency and reducing overhead. | |
139 | */ | |
140 | static unsigned int rx_irq_mod_usec = 60; | |
141 | ||
142 | /* Initial interrupt moderation settings. They can be modified after | |
143 | * module load with ethtool. | |
144 | * | |
145 | * This default is chosen to ensure that a 10G link does not go idle | |
146 | * while a TX queue is stopped after it has become full. A queue is | |
147 | * restarted when it drops below half full. The time this takes (assuming | |
148 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
149 | * 512 / 3 * 1.2 = 205 usec. | |
150 | */ | |
151 | static unsigned int tx_irq_mod_usec = 150; | |
152 | ||
153 | /* This is the first interrupt mode to try out of: | |
154 | * 0 => MSI-X | |
155 | * 1 => MSI | |
156 | * 2 => legacy | |
157 | */ | |
158 | static unsigned int interrupt_mode; | |
159 | ||
160 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
161 | * i.e. the number of CPUs among which we may distribute simultaneous | |
162 | * interrupt handling. | |
163 | * | |
164 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
165 | * The default (0) means to assign an interrupt to each package (level II cache) | |
166 | */ | |
167 | static unsigned int rss_cpus; | |
168 | module_param(rss_cpus, uint, 0444); | |
169 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
170 | ||
84ae48fe BH |
171 | static int phy_flash_cfg; |
172 | module_param(phy_flash_cfg, int, 0644); | |
173 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
174 | ||
6fb70fd1 BH |
175 | static unsigned irq_adapt_low_thresh = 10000; |
176 | module_param(irq_adapt_low_thresh, uint, 0644); | |
177 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
178 | "Threshold score for reducing IRQ moderation"); | |
179 | ||
180 | static unsigned irq_adapt_high_thresh = 20000; | |
181 | module_param(irq_adapt_high_thresh, uint, 0644); | |
182 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
183 | "Threshold score for increasing IRQ moderation"); | |
184 | ||
62776d03 BH |
185 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
186 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
187 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
188 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
189 | module_param(debug, uint, 0); | |
190 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
191 | ||
8ceee660 BH |
192 | /************************************************************************** |
193 | * | |
194 | * Utility functions and prototypes | |
195 | * | |
196 | *************************************************************************/ | |
4642610c BH |
197 | |
198 | static void efx_remove_channels(struct efx_nic *efx); | |
8ceee660 | 199 | static void efx_remove_port(struct efx_nic *efx); |
e8f14992 | 200 | static void efx_init_napi(struct efx_nic *efx); |
8ceee660 | 201 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 202 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
203 | static void efx_fini_struct(struct efx_nic *efx); |
204 | static void efx_start_all(struct efx_nic *efx); | |
205 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
206 | |
207 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
208 | do { \ | |
332c1ce9 BH |
209 | if ((efx->state == STATE_RUNNING) || \ |
210 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
211 | ASSERT_RTNL(); \ |
212 | } while (0) | |
213 | ||
214 | /************************************************************************** | |
215 | * | |
216 | * Event queue processing | |
217 | * | |
218 | *************************************************************************/ | |
219 | ||
220 | /* Process channel's event queue | |
221 | * | |
222 | * This function is responsible for processing the event queue of a | |
223 | * single channel. The caller must guarantee that this function will | |
224 | * never be concurrently called more than once on the same channel, | |
225 | * though different channels may be being processed concurrently. | |
226 | */ | |
fa236e18 | 227 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 228 | { |
42cbe2d7 | 229 | struct efx_nic *efx = channel->efx; |
fa236e18 | 230 | int spent; |
8ceee660 | 231 | |
a7d529ae | 232 | if (unlikely(efx->reset_pending || !channel->enabled)) |
42cbe2d7 | 233 | return 0; |
8ceee660 | 234 | |
fa236e18 BH |
235 | spent = efx_nic_process_eventq(channel, budget); |
236 | if (spent == 0) | |
42cbe2d7 | 237 | return 0; |
8ceee660 BH |
238 | |
239 | /* Deliver last RX packet. */ | |
240 | if (channel->rx_pkt) { | |
241 | __efx_rx_packet(channel, channel->rx_pkt, | |
242 | channel->rx_pkt_csummed); | |
243 | channel->rx_pkt = NULL; | |
244 | } | |
245 | ||
8ceee660 BH |
246 | efx_rx_strategy(channel); |
247 | ||
f7d12cdc | 248 | efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel)); |
8ceee660 | 249 | |
fa236e18 | 250 | return spent; |
8ceee660 BH |
251 | } |
252 | ||
253 | /* Mark channel as finished processing | |
254 | * | |
255 | * Note that since we will not receive further interrupts for this | |
256 | * channel before we finish processing and call the eventq_read_ack() | |
257 | * method, there is no need to use the interrupt hold-off timers. | |
258 | */ | |
259 | static inline void efx_channel_processed(struct efx_channel *channel) | |
260 | { | |
5b9e207c BH |
261 | /* The interrupt handler for this channel may set work_pending |
262 | * as soon as we acknowledge the events we've seen. Make sure | |
263 | * it's cleared before then. */ | |
dc8cfa55 | 264 | channel->work_pending = false; |
5b9e207c BH |
265 | smp_wmb(); |
266 | ||
152b6a62 | 267 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
268 | } |
269 | ||
270 | /* NAPI poll handler | |
271 | * | |
272 | * NAPI guarantees serialisation of polls of the same device, which | |
273 | * provides the guarantee required by efx_process_channel(). | |
274 | */ | |
275 | static int efx_poll(struct napi_struct *napi, int budget) | |
276 | { | |
277 | struct efx_channel *channel = | |
278 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 279 | struct efx_nic *efx = channel->efx; |
fa236e18 | 280 | int spent; |
8ceee660 | 281 | |
62776d03 BH |
282 | netif_vdbg(efx, intr, efx->net_dev, |
283 | "channel %d NAPI poll executing on CPU %d\n", | |
284 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 285 | |
fa236e18 | 286 | spent = efx_process_channel(channel, budget); |
8ceee660 | 287 | |
fa236e18 | 288 | if (spent < budget) { |
a4900ac9 | 289 | if (channel->channel < efx->n_rx_channels && |
6fb70fd1 BH |
290 | efx->irq_rx_adaptive && |
291 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
292 | if (unlikely(channel->irq_mod_score < |
293 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
294 | if (channel->irq_moderation > 1) { |
295 | channel->irq_moderation -= 1; | |
ef2b90ee | 296 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 297 | } |
6fb70fd1 BH |
298 | } else if (unlikely(channel->irq_mod_score > |
299 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
300 | if (channel->irq_moderation < |
301 | efx->irq_rx_moderation) { | |
302 | channel->irq_moderation += 1; | |
ef2b90ee | 303 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 304 | } |
6fb70fd1 | 305 | } |
6fb70fd1 BH |
306 | channel->irq_count = 0; |
307 | channel->irq_mod_score = 0; | |
308 | } | |
309 | ||
64d8ad6d BH |
310 | efx_filter_rfs_expire(channel); |
311 | ||
8ceee660 | 312 | /* There is no race here; although napi_disable() will |
288379f0 | 313 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
314 | * since efx_channel_processed() will have no effect if |
315 | * interrupts have already been disabled. | |
316 | */ | |
288379f0 | 317 | napi_complete(napi); |
8ceee660 BH |
318 | efx_channel_processed(channel); |
319 | } | |
320 | ||
fa236e18 | 321 | return spent; |
8ceee660 BH |
322 | } |
323 | ||
324 | /* Process the eventq of the specified channel immediately on this CPU | |
325 | * | |
326 | * Disable hardware generated interrupts, wait for any existing | |
327 | * processing to finish, then directly poll (and ack ) the eventq. | |
328 | * Finally reenable NAPI and interrupts. | |
329 | * | |
d4fabcc8 BH |
330 | * This is for use only during a loopback self-test. It must not |
331 | * deliver any packets up the stack as this can result in deadlock. | |
8ceee660 BH |
332 | */ |
333 | void efx_process_channel_now(struct efx_channel *channel) | |
334 | { | |
335 | struct efx_nic *efx = channel->efx; | |
336 | ||
8313aca3 | 337 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 | 338 | BUG_ON(!channel->enabled); |
d4fabcc8 | 339 | BUG_ON(!efx->loopback_selftest); |
8ceee660 BH |
340 | |
341 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 342 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 343 | if (efx->legacy_irq) { |
8ceee660 | 344 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
345 | efx->legacy_irq_enabled = false; |
346 | } | |
64ee3120 | 347 | if (channel->irq) |
8ceee660 BH |
348 | synchronize_irq(channel->irq); |
349 | ||
350 | /* Wait for any NAPI processing to complete */ | |
351 | napi_disable(&channel->napi_str); | |
352 | ||
353 | /* Poll the channel */ | |
ecc910f5 | 354 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
355 | |
356 | /* Ack the eventq. This may cause an interrupt to be generated | |
357 | * when they are reenabled */ | |
358 | efx_channel_processed(channel); | |
359 | ||
360 | napi_enable(&channel->napi_str); | |
94dec6a2 BH |
361 | if (efx->legacy_irq) |
362 | efx->legacy_irq_enabled = true; | |
152b6a62 | 363 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
364 | } |
365 | ||
366 | /* Create event queue | |
367 | * Event queue memory allocations are done only once. If the channel | |
368 | * is reset, the memory buffer will be reused; this guards against | |
369 | * errors during channel reset and also simplifies interrupt handling. | |
370 | */ | |
371 | static int efx_probe_eventq(struct efx_channel *channel) | |
372 | { | |
ecc910f5 SH |
373 | struct efx_nic *efx = channel->efx; |
374 | unsigned long entries; | |
375 | ||
62776d03 BH |
376 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
377 | "chan %d create event queue\n", channel->channel); | |
8ceee660 | 378 | |
ecc910f5 SH |
379 | /* Build an event queue with room for one event per tx and rx buffer, |
380 | * plus some extra for link state events and MCDI completions. */ | |
381 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
382 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
383 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
384 | ||
152b6a62 | 385 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
386 | } |
387 | ||
388 | /* Prepare channel's event queue */ | |
bc3c90a2 | 389 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 390 | { |
62776d03 BH |
391 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
392 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
393 | |
394 | channel->eventq_read_ptr = 0; | |
395 | ||
152b6a62 | 396 | efx_nic_init_eventq(channel); |
8ceee660 BH |
397 | } |
398 | ||
399 | static void efx_fini_eventq(struct efx_channel *channel) | |
400 | { | |
62776d03 BH |
401 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
402 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 403 | |
152b6a62 | 404 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
405 | } |
406 | ||
407 | static void efx_remove_eventq(struct efx_channel *channel) | |
408 | { | |
62776d03 BH |
409 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
410 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 411 | |
152b6a62 | 412 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
413 | } |
414 | ||
415 | /************************************************************************** | |
416 | * | |
417 | * Channel handling | |
418 | * | |
419 | *************************************************************************/ | |
420 | ||
4642610c BH |
421 | /* Allocate and initialise a channel structure, optionally copying |
422 | * parameters (but not resources) from an old channel structure. */ | |
423 | static struct efx_channel * | |
424 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
425 | { | |
426 | struct efx_channel *channel; | |
427 | struct efx_rx_queue *rx_queue; | |
428 | struct efx_tx_queue *tx_queue; | |
429 | int j; | |
430 | ||
431 | if (old_channel) { | |
432 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); | |
433 | if (!channel) | |
434 | return NULL; | |
435 | ||
436 | *channel = *old_channel; | |
437 | ||
e8f14992 | 438 | channel->napi_dev = NULL; |
4642610c BH |
439 | memset(&channel->eventq, 0, sizeof(channel->eventq)); |
440 | ||
441 | rx_queue = &channel->rx_queue; | |
442 | rx_queue->buffer = NULL; | |
443 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
444 | ||
445 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
446 | tx_queue = &channel->tx_queue[j]; | |
447 | if (tx_queue->channel) | |
448 | tx_queue->channel = channel; | |
449 | tx_queue->buffer = NULL; | |
450 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
451 | } | |
452 | } else { | |
453 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); | |
454 | if (!channel) | |
455 | return NULL; | |
456 | ||
457 | channel->efx = efx; | |
458 | channel->channel = i; | |
459 | ||
460 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
461 | tx_queue = &channel->tx_queue[j]; | |
462 | tx_queue->efx = efx; | |
463 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
464 | tx_queue->channel = channel; | |
465 | } | |
466 | } | |
467 | ||
4642610c BH |
468 | rx_queue = &channel->rx_queue; |
469 | rx_queue->efx = efx; | |
470 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
471 | (unsigned long)rx_queue); | |
472 | ||
473 | return channel; | |
474 | } | |
475 | ||
8ceee660 BH |
476 | static int efx_probe_channel(struct efx_channel *channel) |
477 | { | |
478 | struct efx_tx_queue *tx_queue; | |
479 | struct efx_rx_queue *rx_queue; | |
480 | int rc; | |
481 | ||
62776d03 BH |
482 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
483 | "creating channel %d\n", channel->channel); | |
8ceee660 BH |
484 | |
485 | rc = efx_probe_eventq(channel); | |
486 | if (rc) | |
487 | goto fail1; | |
488 | ||
489 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
490 | rc = efx_probe_tx_queue(tx_queue); | |
491 | if (rc) | |
492 | goto fail2; | |
493 | } | |
494 | ||
495 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
496 | rc = efx_probe_rx_queue(rx_queue); | |
497 | if (rc) | |
498 | goto fail3; | |
499 | } | |
500 | ||
501 | channel->n_rx_frm_trunc = 0; | |
502 | ||
503 | return 0; | |
504 | ||
505 | fail3: | |
506 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
507 | efx_remove_rx_queue(rx_queue); | |
508 | fail2: | |
509 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
510 | efx_remove_tx_queue(tx_queue); | |
511 | fail1: | |
512 | return rc; | |
513 | } | |
514 | ||
515 | ||
56536e9c BH |
516 | static void efx_set_channel_names(struct efx_nic *efx) |
517 | { | |
518 | struct efx_channel *channel; | |
519 | const char *type = ""; | |
520 | int number; | |
521 | ||
522 | efx_for_each_channel(channel, efx) { | |
523 | number = channel->channel; | |
a4900ac9 BH |
524 | if (efx->n_channels > efx->n_rx_channels) { |
525 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
526 | type = "-rx"; |
527 | } else { | |
528 | type = "-tx"; | |
a4900ac9 | 529 | number -= efx->n_rx_channels; |
56536e9c BH |
530 | } |
531 | } | |
4642610c BH |
532 | snprintf(efx->channel_name[channel->channel], |
533 | sizeof(efx->channel_name[0]), | |
56536e9c BH |
534 | "%s%s-%d", efx->name, type, number); |
535 | } | |
536 | } | |
537 | ||
4642610c BH |
538 | static int efx_probe_channels(struct efx_nic *efx) |
539 | { | |
540 | struct efx_channel *channel; | |
541 | int rc; | |
542 | ||
543 | /* Restart special buffer allocation */ | |
544 | efx->next_buffer_table = 0; | |
545 | ||
546 | efx_for_each_channel(channel, efx) { | |
547 | rc = efx_probe_channel(channel); | |
548 | if (rc) { | |
549 | netif_err(efx, probe, efx->net_dev, | |
550 | "failed to create channel %d\n", | |
551 | channel->channel); | |
552 | goto fail; | |
553 | } | |
554 | } | |
555 | efx_set_channel_names(efx); | |
556 | ||
557 | return 0; | |
558 | ||
559 | fail: | |
560 | efx_remove_channels(efx); | |
561 | return rc; | |
562 | } | |
563 | ||
8ceee660 BH |
564 | /* Channels are shutdown and reinitialised whilst the NIC is running |
565 | * to propagate configuration changes (mtu, checksum offload), or | |
566 | * to clear hardware error conditions | |
567 | */ | |
bc3c90a2 | 568 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
569 | { |
570 | struct efx_tx_queue *tx_queue; | |
571 | struct efx_rx_queue *rx_queue; | |
572 | struct efx_channel *channel; | |
8ceee660 | 573 | |
f7f13b0b BH |
574 | /* Calculate the rx buffer allocation parameters required to |
575 | * support the current MTU, including padding for header | |
576 | * alignment and overruns. | |
577 | */ | |
578 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
579 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 580 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 581 | efx->type->rx_buffer_padding); |
62b330ba SH |
582 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
583 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
584 | |
585 | /* Initialise the channels */ | |
586 | efx_for_each_channel(channel, efx) { | |
62776d03 BH |
587 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
588 | "init chan %d\n", channel->channel); | |
8ceee660 | 589 | |
bc3c90a2 | 590 | efx_init_eventq(channel); |
8ceee660 | 591 | |
bc3c90a2 BH |
592 | efx_for_each_channel_tx_queue(tx_queue, channel) |
593 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
594 | |
595 | /* The rx buffer allocation strategy is MTU dependent */ | |
596 | efx_rx_strategy(channel); | |
597 | ||
bc3c90a2 BH |
598 | efx_for_each_channel_rx_queue(rx_queue, channel) |
599 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
600 | |
601 | WARN_ON(channel->rx_pkt != NULL); | |
602 | efx_rx_strategy(channel); | |
603 | } | |
8ceee660 BH |
604 | } |
605 | ||
606 | /* This enables event queue processing and packet transmission. | |
607 | * | |
608 | * Note that this function is not allowed to fail, since that would | |
609 | * introduce too much complexity into the suspend/resume path. | |
610 | */ | |
611 | static void efx_start_channel(struct efx_channel *channel) | |
612 | { | |
613 | struct efx_rx_queue *rx_queue; | |
614 | ||
62776d03 BH |
615 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, |
616 | "starting chan %d\n", channel->channel); | |
8ceee660 | 617 | |
5b9e207c BH |
618 | /* The interrupt handler for this channel may set work_pending |
619 | * as soon as we enable it. Make sure it's cleared before | |
620 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
621 | channel->work_pending = false; |
622 | channel->enabled = true; | |
5b9e207c | 623 | smp_wmb(); |
8ceee660 | 624 | |
90d683af | 625 | /* Fill the queues before enabling NAPI */ |
8ceee660 BH |
626 | efx_for_each_channel_rx_queue(rx_queue, channel) |
627 | efx_fast_push_rx_descriptors(rx_queue); | |
90d683af SH |
628 | |
629 | napi_enable(&channel->napi_str); | |
8ceee660 BH |
630 | } |
631 | ||
632 | /* This disables event queue processing and packet transmission. | |
633 | * This function does not guarantee that all queue processing | |
634 | * (e.g. RX refill) is complete. | |
635 | */ | |
636 | static void efx_stop_channel(struct efx_channel *channel) | |
637 | { | |
8ceee660 BH |
638 | if (!channel->enabled) |
639 | return; | |
640 | ||
62776d03 BH |
641 | netif_dbg(channel->efx, ifdown, channel->efx->net_dev, |
642 | "stop chan %d\n", channel->channel); | |
8ceee660 | 643 | |
dc8cfa55 | 644 | channel->enabled = false; |
8ceee660 | 645 | napi_disable(&channel->napi_str); |
8ceee660 BH |
646 | } |
647 | ||
648 | static void efx_fini_channels(struct efx_nic *efx) | |
649 | { | |
650 | struct efx_channel *channel; | |
651 | struct efx_tx_queue *tx_queue; | |
652 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 653 | int rc; |
8ceee660 BH |
654 | |
655 | EFX_ASSERT_RESET_SERIALISED(efx); | |
656 | BUG_ON(efx->port_enabled); | |
657 | ||
152b6a62 | 658 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
659 | if (rc && EFX_WORKAROUND_7803(efx)) { |
660 | /* Schedule a reset to recover from the flush failure. The | |
661 | * descriptor caches reference memory we're about to free, | |
662 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
663 | * the MACs because of the pending reset. */ | |
62776d03 BH |
664 | netif_err(efx, drv, efx->net_dev, |
665 | "Resetting to recover from flush failure\n"); | |
fd371e32 SH |
666 | efx_schedule_reset(efx, RESET_TYPE_ALL); |
667 | } else if (rc) { | |
62776d03 | 668 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); |
fd371e32 | 669 | } else { |
62776d03 BH |
670 | netif_dbg(efx, drv, efx->net_dev, |
671 | "successfully flushed all queues\n"); | |
fd371e32 | 672 | } |
6bc5d3a9 | 673 | |
8ceee660 | 674 | efx_for_each_channel(channel, efx) { |
62776d03 BH |
675 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
676 | "shut down chan %d\n", channel->channel); | |
8ceee660 BH |
677 | |
678 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
679 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 680 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 681 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
682 | efx_fini_eventq(channel); |
683 | } | |
684 | } | |
685 | ||
686 | static void efx_remove_channel(struct efx_channel *channel) | |
687 | { | |
688 | struct efx_tx_queue *tx_queue; | |
689 | struct efx_rx_queue *rx_queue; | |
690 | ||
62776d03 BH |
691 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
692 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
693 | |
694 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
695 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 696 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
697 | efx_remove_tx_queue(tx_queue); |
698 | efx_remove_eventq(channel); | |
8ceee660 BH |
699 | } |
700 | ||
4642610c BH |
701 | static void efx_remove_channels(struct efx_nic *efx) |
702 | { | |
703 | struct efx_channel *channel; | |
704 | ||
705 | efx_for_each_channel(channel, efx) | |
706 | efx_remove_channel(channel); | |
707 | } | |
708 | ||
709 | int | |
710 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
711 | { | |
712 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
713 | u32 old_rxq_entries, old_txq_entries; | |
714 | unsigned i; | |
715 | int rc; | |
716 | ||
717 | efx_stop_all(efx); | |
718 | efx_fini_channels(efx); | |
719 | ||
720 | /* Clone channels */ | |
721 | memset(other_channel, 0, sizeof(other_channel)); | |
722 | for (i = 0; i < efx->n_channels; i++) { | |
723 | channel = efx_alloc_channel(efx, i, efx->channel[i]); | |
724 | if (!channel) { | |
725 | rc = -ENOMEM; | |
726 | goto out; | |
727 | } | |
728 | other_channel[i] = channel; | |
729 | } | |
730 | ||
731 | /* Swap entry counts and channel pointers */ | |
732 | old_rxq_entries = efx->rxq_entries; | |
733 | old_txq_entries = efx->txq_entries; | |
734 | efx->rxq_entries = rxq_entries; | |
735 | efx->txq_entries = txq_entries; | |
736 | for (i = 0; i < efx->n_channels; i++) { | |
737 | channel = efx->channel[i]; | |
738 | efx->channel[i] = other_channel[i]; | |
739 | other_channel[i] = channel; | |
740 | } | |
741 | ||
742 | rc = efx_probe_channels(efx); | |
743 | if (rc) | |
744 | goto rollback; | |
745 | ||
e8f14992 BH |
746 | efx_init_napi(efx); |
747 | ||
4642610c | 748 | /* Destroy old channels */ |
e8f14992 BH |
749 | for (i = 0; i < efx->n_channels; i++) { |
750 | efx_fini_napi_channel(other_channel[i]); | |
4642610c | 751 | efx_remove_channel(other_channel[i]); |
e8f14992 | 752 | } |
4642610c BH |
753 | out: |
754 | /* Free unused channel structures */ | |
755 | for (i = 0; i < efx->n_channels; i++) | |
756 | kfree(other_channel[i]); | |
757 | ||
758 | efx_init_channels(efx); | |
759 | efx_start_all(efx); | |
760 | return rc; | |
761 | ||
762 | rollback: | |
763 | /* Swap back */ | |
764 | efx->rxq_entries = old_rxq_entries; | |
765 | efx->txq_entries = old_txq_entries; | |
766 | for (i = 0; i < efx->n_channels; i++) { | |
767 | channel = efx->channel[i]; | |
768 | efx->channel[i] = other_channel[i]; | |
769 | other_channel[i] = channel; | |
770 | } | |
771 | goto out; | |
772 | } | |
773 | ||
90d683af | 774 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 775 | { |
90d683af | 776 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
777 | } |
778 | ||
779 | /************************************************************************** | |
780 | * | |
781 | * Port handling | |
782 | * | |
783 | **************************************************************************/ | |
784 | ||
785 | /* This ensures that the kernel is kept informed (via | |
786 | * netif_carrier_on/off) of the link status, and also maintains the | |
787 | * link status's stop on the port's TX queue. | |
788 | */ | |
fdaa9aed | 789 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 790 | { |
eb50c0d6 BH |
791 | struct efx_link_state *link_state = &efx->link_state; |
792 | ||
8ceee660 BH |
793 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
794 | * that no events are triggered between unregister_netdev() and the | |
795 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
796 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
797 | if (!netif_running(efx->net_dev)) | |
798 | return; | |
799 | ||
eb50c0d6 | 800 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
801 | efx->n_link_state_changes++; |
802 | ||
eb50c0d6 | 803 | if (link_state->up) |
8ceee660 BH |
804 | netif_carrier_on(efx->net_dev); |
805 | else | |
806 | netif_carrier_off(efx->net_dev); | |
807 | } | |
808 | ||
809 | /* Status message for kernel log */ | |
eb50c0d6 | 810 | if (link_state->up) { |
62776d03 BH |
811 | netif_info(efx, link, efx->net_dev, |
812 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
813 | link_state->speed, link_state->fd ? "full" : "half", | |
814 | efx->net_dev->mtu, | |
815 | (efx->promiscuous ? " [PROMISC]" : "")); | |
8ceee660 | 816 | } else { |
62776d03 | 817 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
818 | } |
819 | ||
820 | } | |
821 | ||
d3245b28 BH |
822 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
823 | { | |
824 | efx->link_advertising = advertising; | |
825 | if (advertising) { | |
826 | if (advertising & ADVERTISED_Pause) | |
827 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
828 | else | |
829 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
830 | if (advertising & ADVERTISED_Asym_Pause) | |
831 | efx->wanted_fc ^= EFX_FC_TX; | |
832 | } | |
833 | } | |
834 | ||
b5626946 | 835 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
836 | { |
837 | efx->wanted_fc = wanted_fc; | |
838 | if (efx->link_advertising) { | |
839 | if (wanted_fc & EFX_FC_RX) | |
840 | efx->link_advertising |= (ADVERTISED_Pause | | |
841 | ADVERTISED_Asym_Pause); | |
842 | else | |
843 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
844 | ADVERTISED_Asym_Pause); | |
845 | if (wanted_fc & EFX_FC_TX) | |
846 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
847 | } | |
848 | } | |
849 | ||
115122af BH |
850 | static void efx_fini_port(struct efx_nic *efx); |
851 | ||
d3245b28 BH |
852 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
853 | * the MAC appropriately. All other PHY configuration changes are pushed | |
854 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
855 | * through efx_monitor(). | |
856 | * | |
857 | * Callers must hold the mac_lock | |
858 | */ | |
859 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 860 | { |
d3245b28 BH |
861 | enum efx_phy_mode phy_mode; |
862 | int rc; | |
8ceee660 | 863 | |
d3245b28 | 864 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 865 | |
a816f75a BH |
866 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
867 | if (efx_dev_registered(efx)) { | |
868 | netif_addr_lock_bh(efx->net_dev); | |
869 | netif_addr_unlock_bh(efx->net_dev); | |
870 | } | |
871 | ||
d3245b28 BH |
872 | /* Disable PHY transmit in mac level loopbacks */ |
873 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
874 | if (LOOPBACK_INTERNAL(efx)) |
875 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
876 | else | |
877 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 878 | |
d3245b28 | 879 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 880 | |
d3245b28 BH |
881 | if (rc) |
882 | efx->phy_mode = phy_mode; | |
177dfcd8 | 883 | |
d3245b28 | 884 | return rc; |
8ceee660 BH |
885 | } |
886 | ||
887 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
888 | * disabled. */ | |
d3245b28 | 889 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 890 | { |
d3245b28 BH |
891 | int rc; |
892 | ||
8ceee660 BH |
893 | EFX_ASSERT_RESET_SERIALISED(efx); |
894 | ||
895 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 896 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 897 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
898 | |
899 | return rc; | |
8ceee660 BH |
900 | } |
901 | ||
8be4f3e6 BH |
902 | /* Asynchronous work item for changing MAC promiscuity and multicast |
903 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
904 | * MAC directly. */ | |
766ca0fa BH |
905 | static void efx_mac_work(struct work_struct *data) |
906 | { | |
907 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
908 | ||
909 | mutex_lock(&efx->mac_lock); | |
8be4f3e6 | 910 | if (efx->port_enabled) { |
ef2b90ee | 911 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
912 | efx->mac_op->reconfigure(efx); |
913 | } | |
766ca0fa BH |
914 | mutex_unlock(&efx->mac_lock); |
915 | } | |
916 | ||
8ceee660 BH |
917 | static int efx_probe_port(struct efx_nic *efx) |
918 | { | |
7e300bc8 | 919 | unsigned char *perm_addr; |
8ceee660 BH |
920 | int rc; |
921 | ||
62776d03 | 922 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 923 | |
ff3b00a0 SH |
924 | if (phy_flash_cfg) |
925 | efx->phy_mode = PHY_MODE_SPECIAL; | |
926 | ||
ef2b90ee BH |
927 | /* Connect up MAC/PHY operations table */ |
928 | rc = efx->type->probe_port(efx); | |
8ceee660 | 929 | if (rc) |
e42de262 | 930 | return rc; |
8ceee660 BH |
931 | |
932 | /* Sanity check MAC address */ | |
7e300bc8 BH |
933 | perm_addr = efx->net_dev->perm_addr; |
934 | if (is_valid_ether_addr(perm_addr)) { | |
935 | memcpy(efx->net_dev->dev_addr, perm_addr, ETH_ALEN); | |
8ceee660 | 936 | } else { |
62776d03 | 937 | netif_err(efx, probe, efx->net_dev, "invalid MAC address %pM\n", |
7e300bc8 | 938 | perm_addr); |
8ceee660 BH |
939 | if (!allow_bad_hwaddr) { |
940 | rc = -EINVAL; | |
941 | goto err; | |
942 | } | |
943 | random_ether_addr(efx->net_dev->dev_addr); | |
62776d03 BH |
944 | netif_info(efx, probe, efx->net_dev, |
945 | "using locally-generated MAC %pM\n", | |
946 | efx->net_dev->dev_addr); | |
8ceee660 BH |
947 | } |
948 | ||
949 | return 0; | |
950 | ||
951 | err: | |
e42de262 | 952 | efx->type->remove_port(efx); |
8ceee660 BH |
953 | return rc; |
954 | } | |
955 | ||
956 | static int efx_init_port(struct efx_nic *efx) | |
957 | { | |
958 | int rc; | |
959 | ||
62776d03 | 960 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 961 | |
1dfc5cea BH |
962 | mutex_lock(&efx->mac_lock); |
963 | ||
177dfcd8 | 964 | rc = efx->phy_op->init(efx); |
8ceee660 | 965 | if (rc) |
1dfc5cea | 966 | goto fail1; |
8ceee660 | 967 | |
dc8cfa55 | 968 | efx->port_initialized = true; |
1dfc5cea | 969 | |
d3245b28 BH |
970 | /* Reconfigure the MAC before creating dma queues (required for |
971 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
972 | efx->mac_op->reconfigure(efx); | |
973 | ||
974 | /* Ensure the PHY advertises the correct flow control settings */ | |
975 | rc = efx->phy_op->reconfigure(efx); | |
976 | if (rc) | |
977 | goto fail2; | |
978 | ||
1dfc5cea | 979 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 980 | return 0; |
177dfcd8 | 981 | |
1dfc5cea | 982 | fail2: |
177dfcd8 | 983 | efx->phy_op->fini(efx); |
1dfc5cea BH |
984 | fail1: |
985 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 986 | return rc; |
8ceee660 BH |
987 | } |
988 | ||
8ceee660 BH |
989 | static void efx_start_port(struct efx_nic *efx) |
990 | { | |
62776d03 | 991 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
992 | BUG_ON(efx->port_enabled); |
993 | ||
994 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 995 | efx->port_enabled = true; |
8be4f3e6 BH |
996 | |
997 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
998 | * and then cancelled by efx_flush_all() */ | |
ef2b90ee | 999 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
1000 | efx->mac_op->reconfigure(efx); |
1001 | ||
8ceee660 BH |
1002 | mutex_unlock(&efx->mac_lock); |
1003 | } | |
1004 | ||
fdaa9aed | 1005 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
1006 | static void efx_stop_port(struct efx_nic *efx) |
1007 | { | |
62776d03 | 1008 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
1009 | |
1010 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1011 | efx->port_enabled = false; |
8ceee660 BH |
1012 | mutex_unlock(&efx->mac_lock); |
1013 | ||
1014 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 1015 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
1016 | netif_addr_lock_bh(efx->net_dev); |
1017 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
1018 | } |
1019 | } | |
1020 | ||
1021 | static void efx_fini_port(struct efx_nic *efx) | |
1022 | { | |
62776d03 | 1023 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1024 | |
1025 | if (!efx->port_initialized) | |
1026 | return; | |
1027 | ||
177dfcd8 | 1028 | efx->phy_op->fini(efx); |
dc8cfa55 | 1029 | efx->port_initialized = false; |
8ceee660 | 1030 | |
eb50c0d6 | 1031 | efx->link_state.up = false; |
8ceee660 BH |
1032 | efx_link_status_changed(efx); |
1033 | } | |
1034 | ||
1035 | static void efx_remove_port(struct efx_nic *efx) | |
1036 | { | |
62776d03 | 1037 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1038 | |
ef2b90ee | 1039 | efx->type->remove_port(efx); |
8ceee660 BH |
1040 | } |
1041 | ||
1042 | /************************************************************************** | |
1043 | * | |
1044 | * NIC handling | |
1045 | * | |
1046 | **************************************************************************/ | |
1047 | ||
1048 | /* This configures the PCI device to enable I/O and DMA. */ | |
1049 | static int efx_init_io(struct efx_nic *efx) | |
1050 | { | |
1051 | struct pci_dev *pci_dev = efx->pci_dev; | |
1052 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
1053 | int rc; | |
1054 | ||
62776d03 | 1055 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1056 | |
1057 | rc = pci_enable_device(pci_dev); | |
1058 | if (rc) { | |
62776d03 BH |
1059 | netif_err(efx, probe, efx->net_dev, |
1060 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1061 | goto fail1; |
1062 | } | |
1063 | ||
1064 | pci_set_master(pci_dev); | |
1065 | ||
1066 | /* Set the PCI DMA mask. Try all possibilities from our | |
1067 | * genuine mask down to 32 bits, because some architectures | |
1068 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1069 | * masks event though they reject 46 bit masks. | |
1070 | */ | |
1071 | while (dma_mask > 0x7fffffffUL) { | |
1072 | if (pci_dma_supported(pci_dev, dma_mask) && | |
1073 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
1074 | break; | |
1075 | dma_mask >>= 1; | |
1076 | } | |
1077 | if (rc) { | |
62776d03 BH |
1078 | netif_err(efx, probe, efx->net_dev, |
1079 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1080 | goto fail2; |
1081 | } | |
62776d03 BH |
1082 | netif_dbg(efx, probe, efx->net_dev, |
1083 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 BH |
1084 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); |
1085 | if (rc) { | |
1086 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
1087 | * fail with a mask that pci_set_dma_mask() accepted, | |
1088 | * but just in case... | |
1089 | */ | |
62776d03 BH |
1090 | netif_err(efx, probe, efx->net_dev, |
1091 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1092 | goto fail2; |
1093 | } | |
1094 | ||
dc803df8 BH |
1095 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1096 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1097 | if (rc) { |
62776d03 BH |
1098 | netif_err(efx, probe, efx->net_dev, |
1099 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1100 | rc = -EIO; |
1101 | goto fail3; | |
1102 | } | |
86c432ca BH |
1103 | efx->membase = ioremap_nocache(efx->membase_phys, |
1104 | efx->type->mem_map_size); | |
8ceee660 | 1105 | if (!efx->membase) { |
62776d03 BH |
1106 | netif_err(efx, probe, efx->net_dev, |
1107 | "could not map memory BAR at %llx+%x\n", | |
1108 | (unsigned long long)efx->membase_phys, | |
1109 | efx->type->mem_map_size); | |
8ceee660 BH |
1110 | rc = -ENOMEM; |
1111 | goto fail4; | |
1112 | } | |
62776d03 BH |
1113 | netif_dbg(efx, probe, efx->net_dev, |
1114 | "memory BAR at %llx+%x (virtual %p)\n", | |
1115 | (unsigned long long)efx->membase_phys, | |
1116 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1117 | |
1118 | return 0; | |
1119 | ||
1120 | fail4: | |
dc803df8 | 1121 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1122 | fail3: |
2c118e0f | 1123 | efx->membase_phys = 0; |
8ceee660 BH |
1124 | fail2: |
1125 | pci_disable_device(efx->pci_dev); | |
1126 | fail1: | |
1127 | return rc; | |
1128 | } | |
1129 | ||
1130 | static void efx_fini_io(struct efx_nic *efx) | |
1131 | { | |
62776d03 | 1132 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1133 | |
1134 | if (efx->membase) { | |
1135 | iounmap(efx->membase); | |
1136 | efx->membase = NULL; | |
1137 | } | |
1138 | ||
1139 | if (efx->membase_phys) { | |
dc803df8 | 1140 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1141 | efx->membase_phys = 0; |
8ceee660 BH |
1142 | } |
1143 | ||
1144 | pci_disable_device(efx->pci_dev); | |
1145 | } | |
1146 | ||
a4900ac9 BH |
1147 | /* Get number of channels wanted. Each channel will have its own IRQ, |
1148 | * 1 RX queue and/or 2 TX queues. */ | |
1149 | static int efx_wanted_channels(void) | |
46123d04 | 1150 | { |
2f8975fb | 1151 | cpumask_var_t core_mask; |
46123d04 BH |
1152 | int count; |
1153 | int cpu; | |
5b874e25 BH |
1154 | |
1155 | if (rss_cpus) | |
1156 | return rss_cpus; | |
46123d04 | 1157 | |
79f55997 | 1158 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 1159 | printk(KERN_WARNING |
3977d033 | 1160 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
1161 | return 1; |
1162 | } | |
1163 | ||
46123d04 BH |
1164 | count = 0; |
1165 | for_each_online_cpu(cpu) { | |
2f8975fb | 1166 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 1167 | ++count; |
2f8975fb | 1168 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 1169 | topology_core_cpumask(cpu)); |
46123d04 BH |
1170 | } |
1171 | } | |
1172 | ||
2f8975fb | 1173 | free_cpumask_var(core_mask); |
46123d04 BH |
1174 | return count; |
1175 | } | |
1176 | ||
64d8ad6d BH |
1177 | static int |
1178 | efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) | |
1179 | { | |
1180 | #ifdef CONFIG_RFS_ACCEL | |
1181 | int i, rc; | |
1182 | ||
1183 | efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); | |
1184 | if (!efx->net_dev->rx_cpu_rmap) | |
1185 | return -ENOMEM; | |
1186 | for (i = 0; i < efx->n_rx_channels; i++) { | |
1187 | rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, | |
1188 | xentries[i].vector); | |
1189 | if (rc) { | |
1190 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
1191 | efx->net_dev->rx_cpu_rmap = NULL; | |
1192 | return rc; | |
1193 | } | |
1194 | } | |
1195 | #endif | |
1196 | return 0; | |
1197 | } | |
1198 | ||
46123d04 BH |
1199 | /* Probe the number and type of interrupts we are able to obtain, and |
1200 | * the resulting numbers of channels and RX queues. | |
1201 | */ | |
64d8ad6d | 1202 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1203 | { |
46123d04 BH |
1204 | int max_channels = |
1205 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
1206 | int rc, i; |
1207 | ||
1208 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 1209 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a4900ac9 | 1210 | int n_channels; |
aa6ef27e | 1211 | |
a4900ac9 BH |
1212 | n_channels = efx_wanted_channels(); |
1213 | if (separate_tx_channels) | |
1214 | n_channels *= 2; | |
1215 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 1216 | |
a4900ac9 | 1217 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1218 | xentries[i].entry = i; |
a4900ac9 | 1219 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1220 | if (rc > 0) { |
62776d03 BH |
1221 | netif_err(efx, drv, efx->net_dev, |
1222 | "WARNING: Insufficient MSI-X vectors" | |
1223 | " available (%d < %d).\n", rc, n_channels); | |
1224 | netif_err(efx, drv, efx->net_dev, | |
1225 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1226 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1227 | n_channels = rc; | |
8ceee660 | 1228 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1229 | n_channels); |
8ceee660 BH |
1230 | } |
1231 | ||
1232 | if (rc == 0) { | |
a4900ac9 BH |
1233 | efx->n_channels = n_channels; |
1234 | if (separate_tx_channels) { | |
1235 | efx->n_tx_channels = | |
1236 | max(efx->n_channels / 2, 1U); | |
1237 | efx->n_rx_channels = | |
1238 | max(efx->n_channels - | |
1239 | efx->n_tx_channels, 1U); | |
1240 | } else { | |
1241 | efx->n_tx_channels = efx->n_channels; | |
1242 | efx->n_rx_channels = efx->n_channels; | |
1243 | } | |
64d8ad6d BH |
1244 | rc = efx_init_rx_cpu_rmap(efx, xentries); |
1245 | if (rc) { | |
1246 | pci_disable_msix(efx->pci_dev); | |
1247 | return rc; | |
1248 | } | |
a4900ac9 | 1249 | for (i = 0; i < n_channels; i++) |
f7d12cdc BH |
1250 | efx_get_channel(efx, i)->irq = |
1251 | xentries[i].vector; | |
8ceee660 BH |
1252 | } else { |
1253 | /* Fall back to single channel MSI */ | |
1254 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1255 | netif_err(efx, drv, efx->net_dev, |
1256 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1257 | } |
1258 | } | |
1259 | ||
1260 | /* Try single interrupt MSI */ | |
1261 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1262 | efx->n_channels = 1; |
a4900ac9 BH |
1263 | efx->n_rx_channels = 1; |
1264 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1265 | rc = pci_enable_msi(efx->pci_dev); |
1266 | if (rc == 0) { | |
f7d12cdc | 1267 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1268 | } else { |
62776d03 BH |
1269 | netif_err(efx, drv, efx->net_dev, |
1270 | "could not enable MSI\n"); | |
8ceee660 BH |
1271 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1272 | } | |
1273 | } | |
1274 | ||
1275 | /* Assume legacy interrupts */ | |
1276 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1277 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1278 | efx->n_rx_channels = 1; |
1279 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1280 | efx->legacy_irq = efx->pci_dev->irq; |
1281 | } | |
64d8ad6d BH |
1282 | |
1283 | return 0; | |
8ceee660 BH |
1284 | } |
1285 | ||
1286 | static void efx_remove_interrupts(struct efx_nic *efx) | |
1287 | { | |
1288 | struct efx_channel *channel; | |
1289 | ||
1290 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1291 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1292 | channel->irq = 0; |
1293 | pci_disable_msi(efx->pci_dev); | |
1294 | pci_disable_msix(efx->pci_dev); | |
1295 | ||
1296 | /* Remove legacy interrupt */ | |
1297 | efx->legacy_irq = 0; | |
1298 | } | |
1299 | ||
8831da7b | 1300 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1301 | { |
602a5322 BH |
1302 | struct efx_channel *channel; |
1303 | struct efx_tx_queue *tx_queue; | |
1304 | ||
97653431 | 1305 | efx->tx_channel_offset = |
a4900ac9 | 1306 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 BH |
1307 | |
1308 | /* We need to adjust the TX queue numbers if we have separate | |
1309 | * RX-only and TX-only channels. | |
1310 | */ | |
1311 | efx_for_each_channel(channel, efx) { | |
1312 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1313 | tx_queue->queue -= (efx->tx_channel_offset * | |
1314 | EFX_TXQ_TYPES); | |
1315 | } | |
8ceee660 BH |
1316 | } |
1317 | ||
1318 | static int efx_probe_nic(struct efx_nic *efx) | |
1319 | { | |
765c9f46 | 1320 | size_t i; |
8ceee660 BH |
1321 | int rc; |
1322 | ||
62776d03 | 1323 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1324 | |
1325 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1326 | rc = efx->type->probe(efx); |
8ceee660 BH |
1327 | if (rc) |
1328 | return rc; | |
1329 | ||
a4900ac9 | 1330 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1331 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1332 | rc = efx_probe_interrupts(efx); |
1333 | if (rc) | |
1334 | goto fail; | |
8ceee660 | 1335 | |
5d3a6fca BH |
1336 | if (efx->n_channels > 1) |
1337 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 BH |
1338 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
1339 | efx->rx_indir_table[i] = i % efx->n_rx_channels; | |
5d3a6fca | 1340 | |
8831da7b | 1341 | efx_set_channels(efx); |
c4f4adc7 BH |
1342 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1343 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1344 | |
1345 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1346 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1347 | true); | |
8ceee660 BH |
1348 | |
1349 | return 0; | |
64d8ad6d BH |
1350 | |
1351 | fail: | |
1352 | efx->type->remove(efx); | |
1353 | return rc; | |
8ceee660 BH |
1354 | } |
1355 | ||
1356 | static void efx_remove_nic(struct efx_nic *efx) | |
1357 | { | |
62776d03 | 1358 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1359 | |
1360 | efx_remove_interrupts(efx); | |
ef2b90ee | 1361 | efx->type->remove(efx); |
8ceee660 BH |
1362 | } |
1363 | ||
1364 | /************************************************************************** | |
1365 | * | |
1366 | * NIC startup/shutdown | |
1367 | * | |
1368 | *************************************************************************/ | |
1369 | ||
1370 | static int efx_probe_all(struct efx_nic *efx) | |
1371 | { | |
8ceee660 BH |
1372 | int rc; |
1373 | ||
8ceee660 BH |
1374 | rc = efx_probe_nic(efx); |
1375 | if (rc) { | |
62776d03 | 1376 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1377 | goto fail1; |
1378 | } | |
1379 | ||
8ceee660 BH |
1380 | rc = efx_probe_port(efx); |
1381 | if (rc) { | |
62776d03 | 1382 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1383 | goto fail2; |
1384 | } | |
1385 | ||
ecc910f5 | 1386 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
4642610c BH |
1387 | rc = efx_probe_channels(efx); |
1388 | if (rc) | |
1389 | goto fail3; | |
8ceee660 | 1390 | |
64eebcfd BH |
1391 | rc = efx_probe_filters(efx); |
1392 | if (rc) { | |
1393 | netif_err(efx, probe, efx->net_dev, | |
1394 | "failed to create filter tables\n"); | |
1395 | goto fail4; | |
1396 | } | |
1397 | ||
8ceee660 BH |
1398 | return 0; |
1399 | ||
64eebcfd BH |
1400 | fail4: |
1401 | efx_remove_channels(efx); | |
8ceee660 | 1402 | fail3: |
8ceee660 BH |
1403 | efx_remove_port(efx); |
1404 | fail2: | |
1405 | efx_remove_nic(efx); | |
1406 | fail1: | |
1407 | return rc; | |
1408 | } | |
1409 | ||
1410 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1411 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1412 | * and ensures that the port is scheduled to be reconfigured. | |
1413 | * This function is safe to call multiple times when the NIC is in any | |
1414 | * state. */ | |
1415 | static void efx_start_all(struct efx_nic *efx) | |
1416 | { | |
1417 | struct efx_channel *channel; | |
1418 | ||
1419 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1420 | ||
1421 | /* Check that it is appropriate to restart the interface. All | |
1422 | * of these flags are safe to read under just the rtnl lock */ | |
1423 | if (efx->port_enabled) | |
1424 | return; | |
1425 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1426 | return; | |
55668611 | 1427 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1428 | return; |
1429 | ||
1430 | /* Mark the port as enabled so port reconfigurations can start, then | |
1431 | * restart the transmit interface early so the watchdog timer stops */ | |
1432 | efx_start_port(efx); | |
8ceee660 | 1433 | |
e4abce85 | 1434 | if (efx_dev_registered(efx) && netif_device_present(efx->net_dev)) |
c04bfc6b BH |
1435 | netif_tx_wake_all_queues(efx->net_dev); |
1436 | ||
1437 | efx_for_each_channel(channel, efx) | |
8ceee660 BH |
1438 | efx_start_channel(channel); |
1439 | ||
94dec6a2 BH |
1440 | if (efx->legacy_irq) |
1441 | efx->legacy_irq_enabled = true; | |
152b6a62 | 1442 | efx_nic_enable_interrupts(efx); |
8ceee660 | 1443 | |
8880f4ec BH |
1444 | /* Switch to event based MCDI completions after enabling interrupts. |
1445 | * If a reset has been scheduled, then we need to stay in polled mode. | |
1446 | * Rather than serialising efx_mcdi_mode_event() [which sleeps] and | |
1447 | * reset_pending [modified from an atomic context], we instead guarantee | |
1448 | * that efx_mcdi_mode_poll() isn't reverted erroneously */ | |
1449 | efx_mcdi_mode_event(efx); | |
a7d529ae | 1450 | if (efx->reset_pending) |
8880f4ec BH |
1451 | efx_mcdi_mode_poll(efx); |
1452 | ||
78c1f0a0 SH |
1453 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1454 | * event driven), we have to poll the PHY because after an event queue | |
1455 | * flush, we could have a missed a link state change */ | |
1456 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1457 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1458 | efx_monitor_interval); | |
78c1f0a0 SH |
1459 | } else { |
1460 | mutex_lock(&efx->mac_lock); | |
1461 | if (efx->phy_op->poll(efx)) | |
1462 | efx_link_status_changed(efx); | |
1463 | mutex_unlock(&efx->mac_lock); | |
1464 | } | |
55edc6e6 | 1465 | |
ef2b90ee | 1466 | efx->type->start_stats(efx); |
8ceee660 BH |
1467 | } |
1468 | ||
1469 | /* Flush all delayed work. Should only be called when no more delayed work | |
1470 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1471 | * since we're holding the rtnl_lock at this point. */ | |
1472 | static void efx_flush_all(struct efx_nic *efx) | |
1473 | { | |
8ceee660 BH |
1474 | /* Make sure the hardware monitor is stopped */ |
1475 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1476 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1477 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1478 | } |
1479 | ||
1480 | /* Quiesce hardware and software without bringing the link down. | |
1481 | * Safe to call multiple times, when the nic and interface is in any | |
1482 | * state. The caller is guaranteed to subsequently be in a position | |
1483 | * to modify any hardware and software state they see fit without | |
1484 | * taking locks. */ | |
1485 | static void efx_stop_all(struct efx_nic *efx) | |
1486 | { | |
1487 | struct efx_channel *channel; | |
1488 | ||
1489 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1490 | ||
1491 | /* port_enabled can be read safely under the rtnl lock */ | |
1492 | if (!efx->port_enabled) | |
1493 | return; | |
1494 | ||
ef2b90ee | 1495 | efx->type->stop_stats(efx); |
55edc6e6 | 1496 | |
8880f4ec BH |
1497 | /* Switch to MCDI polling on Siena before disabling interrupts */ |
1498 | efx_mcdi_mode_poll(efx); | |
1499 | ||
8ceee660 | 1500 | /* Disable interrupts and wait for ISR to complete */ |
152b6a62 | 1501 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 1502 | if (efx->legacy_irq) { |
8ceee660 | 1503 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
1504 | efx->legacy_irq_enabled = false; |
1505 | } | |
64ee3120 | 1506 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1507 | if (channel->irq) |
1508 | synchronize_irq(channel->irq); | |
b3475645 | 1509 | } |
8ceee660 BH |
1510 | |
1511 | /* Stop all NAPI processing and synchronous rx refills */ | |
1512 | efx_for_each_channel(channel, efx) | |
1513 | efx_stop_channel(channel); | |
1514 | ||
1515 | /* Stop all asynchronous port reconfigurations. Since all | |
1516 | * event processing has already been stopped, there is no | |
1517 | * window to loose phy events */ | |
1518 | efx_stop_port(efx); | |
1519 | ||
fdaa9aed | 1520 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1521 | efx_flush_all(efx); |
1522 | ||
8ceee660 BH |
1523 | /* Stop the kernel transmit interface late, so the watchdog |
1524 | * timer isn't ticking over the flush */ | |
55668611 | 1525 | if (efx_dev_registered(efx)) { |
c04bfc6b | 1526 | netif_tx_stop_all_queues(efx->net_dev); |
8ceee660 BH |
1527 | netif_tx_lock_bh(efx->net_dev); |
1528 | netif_tx_unlock_bh(efx->net_dev); | |
1529 | } | |
1530 | } | |
1531 | ||
1532 | static void efx_remove_all(struct efx_nic *efx) | |
1533 | { | |
64eebcfd | 1534 | efx_remove_filters(efx); |
4642610c | 1535 | efx_remove_channels(efx); |
8ceee660 BH |
1536 | efx_remove_port(efx); |
1537 | efx_remove_nic(efx); | |
1538 | } | |
1539 | ||
8ceee660 BH |
1540 | /************************************************************************** |
1541 | * | |
1542 | * Interrupt moderation | |
1543 | * | |
1544 | **************************************************************************/ | |
1545 | ||
b548f976 | 1546 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int resolution) |
0d86ebd8 | 1547 | { |
b548f976 BH |
1548 | if (usecs == 0) |
1549 | return 0; | |
0d86ebd8 BH |
1550 | if (usecs < resolution) |
1551 | return 1; /* never round down to 0 */ | |
1552 | return usecs / resolution; | |
1553 | } | |
1554 | ||
8ceee660 | 1555 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1556 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1557 | unsigned int rx_usecs, bool rx_adaptive, | |
1558 | bool rx_may_override_tx) | |
8ceee660 | 1559 | { |
f7d12cdc | 1560 | struct efx_channel *channel; |
152b6a62 BH |
1561 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION); |
1562 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1563 | |
1564 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1565 | ||
9e393b30 BH |
1566 | if (tx_ticks > EFX_IRQ_MOD_MAX || rx_ticks > EFX_IRQ_MOD_MAX) |
1567 | return -EINVAL; | |
1568 | ||
1569 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && | |
1570 | !rx_may_override_tx) { | |
1571 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1572 | "RX and TX IRQ moderation must be equal\n"); | |
1573 | return -EINVAL; | |
1574 | } | |
1575 | ||
6fb70fd1 | 1576 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1577 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1578 | efx_for_each_channel(channel, efx) { |
525da907 | 1579 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1580 | channel->irq_moderation = rx_ticks; |
525da907 | 1581 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1582 | channel->irq_moderation = tx_ticks; |
1583 | } | |
9e393b30 BH |
1584 | |
1585 | return 0; | |
8ceee660 BH |
1586 | } |
1587 | ||
a0c4faf5 BH |
1588 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1589 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1590 | { | |
1591 | *rx_adaptive = efx->irq_rx_adaptive; | |
1592 | *rx_usecs = efx->irq_rx_moderation * EFX_IRQ_MOD_RESOLUTION; | |
1593 | ||
1594 | /* If channels are shared between RX and TX, so is IRQ | |
1595 | * moderation. Otherwise, IRQ moderation is the same for all | |
1596 | * TX channels and is not adaptive. | |
1597 | */ | |
1598 | if (efx->tx_channel_offset == 0) | |
1599 | *tx_usecs = *rx_usecs; | |
1600 | else | |
1601 | *tx_usecs = | |
1602 | efx->channel[efx->tx_channel_offset]->irq_moderation * | |
1603 | EFX_IRQ_MOD_RESOLUTION; | |
1604 | } | |
1605 | ||
8ceee660 BH |
1606 | /************************************************************************** |
1607 | * | |
1608 | * Hardware monitor | |
1609 | * | |
1610 | **************************************************************************/ | |
1611 | ||
e254c274 | 1612 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1613 | static void efx_monitor(struct work_struct *data) |
1614 | { | |
1615 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1616 | monitor_work.work); | |
8ceee660 | 1617 | |
62776d03 BH |
1618 | netif_vdbg(efx, timer, efx->net_dev, |
1619 | "hardware monitor executing on CPU %d\n", | |
1620 | raw_smp_processor_id()); | |
ef2b90ee | 1621 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1622 | |
8ceee660 BH |
1623 | /* If the mac_lock is already held then it is likely a port |
1624 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1625 | * most of the work of monitor() anyway. */ |
1626 | if (mutex_trylock(&efx->mac_lock)) { | |
1627 | if (efx->port_enabled) | |
1628 | efx->type->monitor(efx); | |
1629 | mutex_unlock(&efx->mac_lock); | |
1630 | } | |
8ceee660 | 1631 | |
8ceee660 BH |
1632 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1633 | efx_monitor_interval); | |
1634 | } | |
1635 | ||
1636 | /************************************************************************** | |
1637 | * | |
1638 | * ioctls | |
1639 | * | |
1640 | *************************************************************************/ | |
1641 | ||
1642 | /* Net device ioctl | |
1643 | * Context: process, rtnl_lock() held. | |
1644 | */ | |
1645 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1646 | { | |
767e468c | 1647 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1648 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1649 | |
1650 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1651 | ||
68e7f45e BH |
1652 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1653 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1654 | (data->phy_id & 0xfc00) == 0x0400) | |
1655 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1656 | ||
1657 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1658 | } |
1659 | ||
1660 | /************************************************************************** | |
1661 | * | |
1662 | * NAPI interface | |
1663 | * | |
1664 | **************************************************************************/ | |
1665 | ||
e8f14992 | 1666 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1667 | { |
1668 | struct efx_channel *channel; | |
8ceee660 BH |
1669 | |
1670 | efx_for_each_channel(channel, efx) { | |
1671 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1672 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1673 | efx_poll, napi_weight); | |
8ceee660 | 1674 | } |
e8f14992 BH |
1675 | } |
1676 | ||
1677 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1678 | { | |
1679 | if (channel->napi_dev) | |
1680 | netif_napi_del(&channel->napi_str); | |
1681 | channel->napi_dev = NULL; | |
8ceee660 BH |
1682 | } |
1683 | ||
1684 | static void efx_fini_napi(struct efx_nic *efx) | |
1685 | { | |
1686 | struct efx_channel *channel; | |
1687 | ||
e8f14992 BH |
1688 | efx_for_each_channel(channel, efx) |
1689 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1690 | } |
1691 | ||
1692 | /************************************************************************** | |
1693 | * | |
1694 | * Kernel netpoll interface | |
1695 | * | |
1696 | *************************************************************************/ | |
1697 | ||
1698 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1699 | ||
1700 | /* Although in the common case interrupts will be disabled, this is not | |
1701 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1702 | * so no locking is required. | |
1703 | */ | |
1704 | static void efx_netpoll(struct net_device *net_dev) | |
1705 | { | |
767e468c | 1706 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1707 | struct efx_channel *channel; |
1708 | ||
64ee3120 | 1709 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1710 | efx_schedule_channel(channel); |
1711 | } | |
1712 | ||
1713 | #endif | |
1714 | ||
1715 | /************************************************************************** | |
1716 | * | |
1717 | * Kernel net device interface | |
1718 | * | |
1719 | *************************************************************************/ | |
1720 | ||
1721 | /* Context: process, rtnl_lock() held. */ | |
1722 | static int efx_net_open(struct net_device *net_dev) | |
1723 | { | |
767e468c | 1724 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1725 | EFX_ASSERT_RESET_SERIALISED(efx); |
1726 | ||
62776d03 BH |
1727 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1728 | raw_smp_processor_id()); | |
8ceee660 | 1729 | |
f4bd954e BH |
1730 | if (efx->state == STATE_DISABLED) |
1731 | return -EIO; | |
f8b87c17 BH |
1732 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1733 | return -EBUSY; | |
8880f4ec BH |
1734 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1735 | return -EIO; | |
f8b87c17 | 1736 | |
78c1f0a0 SH |
1737 | /* Notify the kernel of the link state polled during driver load, |
1738 | * before the monitor starts running */ | |
1739 | efx_link_status_changed(efx); | |
1740 | ||
8ceee660 BH |
1741 | efx_start_all(efx); |
1742 | return 0; | |
1743 | } | |
1744 | ||
1745 | /* Context: process, rtnl_lock() held. | |
1746 | * Note that the kernel will ignore our return code; this method | |
1747 | * should really be a void. | |
1748 | */ | |
1749 | static int efx_net_stop(struct net_device *net_dev) | |
1750 | { | |
767e468c | 1751 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1752 | |
62776d03 BH |
1753 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1754 | raw_smp_processor_id()); | |
8ceee660 | 1755 | |
f4bd954e BH |
1756 | if (efx->state != STATE_DISABLED) { |
1757 | /* Stop the device and flush all the channels */ | |
1758 | efx_stop_all(efx); | |
1759 | efx_fini_channels(efx); | |
1760 | efx_init_channels(efx); | |
1761 | } | |
8ceee660 BH |
1762 | |
1763 | return 0; | |
1764 | } | |
1765 | ||
5b9e207c | 1766 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
28172739 | 1767 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, struct rtnl_link_stats64 *stats) |
8ceee660 | 1768 | { |
767e468c | 1769 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1770 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1771 | |
55edc6e6 | 1772 | spin_lock_bh(&efx->stats_lock); |
ef2b90ee | 1773 | efx->type->update_stats(efx); |
55edc6e6 | 1774 | spin_unlock_bh(&efx->stats_lock); |
8ceee660 BH |
1775 | |
1776 | stats->rx_packets = mac_stats->rx_packets; | |
1777 | stats->tx_packets = mac_stats->tx_packets; | |
1778 | stats->rx_bytes = mac_stats->rx_bytes; | |
1779 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1780 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1781 | stats->multicast = mac_stats->rx_multicast; |
1782 | stats->collisions = mac_stats->tx_collision; | |
1783 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1784 | mac_stats->rx_length_error); | |
8ceee660 BH |
1785 | stats->rx_crc_errors = mac_stats->rx_bad; |
1786 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1787 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1788 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1789 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1790 | ||
1791 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1792 | stats->rx_crc_errors + |
1793 | stats->rx_frame_errors + | |
8ceee660 BH |
1794 | mac_stats->rx_symbol_error); |
1795 | stats->tx_errors = (stats->tx_window_errors + | |
1796 | mac_stats->tx_bad); | |
1797 | ||
1798 | return stats; | |
1799 | } | |
1800 | ||
1801 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1802 | static void efx_watchdog(struct net_device *net_dev) | |
1803 | { | |
767e468c | 1804 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1805 | |
62776d03 BH |
1806 | netif_err(efx, tx_err, efx->net_dev, |
1807 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1808 | efx->port_enabled); | |
8ceee660 | 1809 | |
739bb23d | 1810 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1811 | } |
1812 | ||
1813 | ||
1814 | /* Context: process, rtnl_lock() held. */ | |
1815 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1816 | { | |
767e468c | 1817 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1818 | int rc = 0; |
1819 | ||
1820 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1821 | ||
1822 | if (new_mtu > EFX_MAX_MTU) | |
1823 | return -EINVAL; | |
1824 | ||
1825 | efx_stop_all(efx); | |
1826 | ||
62776d03 | 1827 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 BH |
1828 | |
1829 | efx_fini_channels(efx); | |
d3245b28 BH |
1830 | |
1831 | mutex_lock(&efx->mac_lock); | |
1832 | /* Reconfigure the MAC before enabling the dma queues so that | |
1833 | * the RX buffers don't overflow */ | |
8ceee660 | 1834 | net_dev->mtu = new_mtu; |
d3245b28 BH |
1835 | efx->mac_op->reconfigure(efx); |
1836 | mutex_unlock(&efx->mac_lock); | |
1837 | ||
bc3c90a2 | 1838 | efx_init_channels(efx); |
8ceee660 BH |
1839 | |
1840 | efx_start_all(efx); | |
1841 | return rc; | |
8ceee660 BH |
1842 | } |
1843 | ||
1844 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1845 | { | |
767e468c | 1846 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1847 | struct sockaddr *addr = data; |
1848 | char *new_addr = addr->sa_data; | |
1849 | ||
1850 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1851 | ||
1852 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1853 | netif_err(efx, drv, efx->net_dev, |
1854 | "invalid ethernet MAC address requested: %pM\n", | |
1855 | new_addr); | |
8ceee660 BH |
1856 | return -EINVAL; |
1857 | } | |
1858 | ||
1859 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1860 | ||
1861 | /* Reconfigure the MAC */ | |
d3245b28 BH |
1862 | mutex_lock(&efx->mac_lock); |
1863 | efx->mac_op->reconfigure(efx); | |
1864 | mutex_unlock(&efx->mac_lock); | |
8ceee660 BH |
1865 | |
1866 | return 0; | |
1867 | } | |
1868 | ||
a816f75a | 1869 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1870 | static void efx_set_multicast_list(struct net_device *net_dev) |
1871 | { | |
767e468c | 1872 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1873 | struct netdev_hw_addr *ha; |
8ceee660 | 1874 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1875 | u32 crc; |
1876 | int bit; | |
8ceee660 | 1877 | |
8be4f3e6 | 1878 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1879 | |
1880 | /* Build multicast hash table */ | |
8be4f3e6 | 1881 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1882 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1883 | } else { | |
1884 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1885 | netdev_for_each_mc_addr(ha, net_dev) { |
1886 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1887 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1888 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1889 | } |
8ceee660 | 1890 | |
8be4f3e6 BH |
1891 | /* Broadcast packets go through the multicast hash filter. |
1892 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1893 | * so we always add bit 0xff to the mask. | |
1894 | */ | |
1895 | set_bit_le(0xff, mc_hash->byte); | |
1896 | } | |
a816f75a | 1897 | |
8be4f3e6 BH |
1898 | if (efx->port_enabled) |
1899 | queue_work(efx->workqueue, &efx->mac_work); | |
1900 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1901 | } |
1902 | ||
abfe9039 BH |
1903 | static int efx_set_features(struct net_device *net_dev, u32 data) |
1904 | { | |
1905 | struct efx_nic *efx = netdev_priv(net_dev); | |
1906 | ||
1907 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
1908 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
1909 | efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
1910 | ||
1911 | return 0; | |
1912 | } | |
1913 | ||
c3ecb9f3 SH |
1914 | static const struct net_device_ops efx_netdev_ops = { |
1915 | .ndo_open = efx_net_open, | |
1916 | .ndo_stop = efx_net_stop, | |
4472702e | 1917 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
1918 | .ndo_tx_timeout = efx_watchdog, |
1919 | .ndo_start_xmit = efx_hard_start_xmit, | |
1920 | .ndo_validate_addr = eth_validate_addr, | |
1921 | .ndo_do_ioctl = efx_ioctl, | |
1922 | .ndo_change_mtu = efx_change_mtu, | |
1923 | .ndo_set_mac_address = efx_set_mac_address, | |
afc4b13d | 1924 | .ndo_set_rx_mode = efx_set_multicast_list, |
abfe9039 | 1925 | .ndo_set_features = efx_set_features, |
c3ecb9f3 SH |
1926 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1927 | .ndo_poll_controller = efx_netpoll, | |
1928 | #endif | |
94b274bf | 1929 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
1930 | #ifdef CONFIG_RFS_ACCEL |
1931 | .ndo_rx_flow_steer = efx_filter_rfs, | |
1932 | #endif | |
c3ecb9f3 SH |
1933 | }; |
1934 | ||
7dde596e BH |
1935 | static void efx_update_name(struct efx_nic *efx) |
1936 | { | |
1937 | strcpy(efx->name, efx->net_dev->name); | |
1938 | efx_mtd_rename(efx); | |
1939 | efx_set_channel_names(efx); | |
1940 | } | |
1941 | ||
8ceee660 BH |
1942 | static int efx_netdev_event(struct notifier_block *this, |
1943 | unsigned long event, void *ptr) | |
1944 | { | |
d3208b5e | 1945 | struct net_device *net_dev = ptr; |
8ceee660 | 1946 | |
7dde596e BH |
1947 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1948 | event == NETDEV_CHANGENAME) | |
1949 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1950 | |
1951 | return NOTIFY_DONE; | |
1952 | } | |
1953 | ||
1954 | static struct notifier_block efx_netdev_notifier = { | |
1955 | .notifier_call = efx_netdev_event, | |
1956 | }; | |
1957 | ||
06d5e193 BH |
1958 | static ssize_t |
1959 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1960 | { | |
1961 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1962 | return sprintf(buf, "%d\n", efx->phy_type); | |
1963 | } | |
1964 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1965 | ||
8ceee660 BH |
1966 | static int efx_register_netdev(struct efx_nic *efx) |
1967 | { | |
1968 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 1969 | struct efx_channel *channel; |
8ceee660 BH |
1970 | int rc; |
1971 | ||
1972 | net_dev->watchdog_timeo = 5 * HZ; | |
1973 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1974 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1975 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
1976 | ||
8ceee660 | 1977 | /* Clear MAC statistics */ |
177dfcd8 | 1978 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1979 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1980 | ||
7dde596e | 1981 | rtnl_lock(); |
aed0628d BH |
1982 | |
1983 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1984 | if (rc < 0) | |
1985 | goto fail_locked; | |
7dde596e | 1986 | efx_update_name(efx); |
aed0628d BH |
1987 | |
1988 | rc = register_netdevice(net_dev); | |
1989 | if (rc) | |
1990 | goto fail_locked; | |
1991 | ||
c04bfc6b BH |
1992 | efx_for_each_channel(channel, efx) { |
1993 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
1994 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1995 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
1996 | } |
1997 | ||
aed0628d BH |
1998 | /* Always start with carrier off; PHY events will detect the link */ |
1999 | netif_carrier_off(efx->net_dev); | |
2000 | ||
7dde596e | 2001 | rtnl_unlock(); |
8ceee660 | 2002 | |
06d5e193 BH |
2003 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2004 | if (rc) { | |
62776d03 BH |
2005 | netif_err(efx, drv, efx->net_dev, |
2006 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2007 | goto fail_registered; |
2008 | } | |
2009 | ||
8ceee660 | 2010 | return 0; |
06d5e193 | 2011 | |
aed0628d BH |
2012 | fail_locked: |
2013 | rtnl_unlock(); | |
62776d03 | 2014 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
2015 | return rc; |
2016 | ||
06d5e193 BH |
2017 | fail_registered: |
2018 | unregister_netdev(net_dev); | |
2019 | return rc; | |
8ceee660 BH |
2020 | } |
2021 | ||
2022 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2023 | { | |
f7d12cdc | 2024 | struct efx_channel *channel; |
8ceee660 BH |
2025 | struct efx_tx_queue *tx_queue; |
2026 | ||
2027 | if (!efx->net_dev) | |
2028 | return; | |
2029 | ||
767e468c | 2030 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
2031 | |
2032 | /* Free up any skbs still remaining. This has to happen before | |
2033 | * we try to unregister the netdev as running their destructors | |
2034 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
2035 | efx_for_each_channel(channel, efx) { |
2036 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
2037 | efx_release_tx_buffers(tx_queue); | |
2038 | } | |
8ceee660 | 2039 | |
55668611 | 2040 | if (efx_dev_registered(efx)) { |
8ceee660 | 2041 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 2042 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
2043 | unregister_netdev(efx->net_dev); |
2044 | } | |
2045 | } | |
2046 | ||
2047 | /************************************************************************** | |
2048 | * | |
2049 | * Device reset and suspend | |
2050 | * | |
2051 | **************************************************************************/ | |
2052 | ||
2467ca46 BH |
2053 | /* Tears down the entire software state and most of the hardware state |
2054 | * before reset. */ | |
d3245b28 | 2055 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2056 | { |
8ceee660 BH |
2057 | EFX_ASSERT_RESET_SERIALISED(efx); |
2058 | ||
2467ca46 BH |
2059 | efx_stop_all(efx); |
2060 | mutex_lock(&efx->mac_lock); | |
2061 | ||
8ceee660 | 2062 | efx_fini_channels(efx); |
4b988280 SH |
2063 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2064 | efx->phy_op->fini(efx); | |
ef2b90ee | 2065 | efx->type->fini(efx); |
8ceee660 BH |
2066 | } |
2067 | ||
2467ca46 BH |
2068 | /* This function will always ensure that the locks acquired in |
2069 | * efx_reset_down() are released. A failure return code indicates | |
2070 | * that we were unable to reinitialise the hardware, and the | |
2071 | * driver should be disabled. If ok is false, then the rx and tx | |
2072 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2073 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2074 | { |
2075 | int rc; | |
2076 | ||
2467ca46 | 2077 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2078 | |
ef2b90ee | 2079 | rc = efx->type->init(efx); |
8ceee660 | 2080 | if (rc) { |
62776d03 | 2081 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2082 | goto fail; |
8ceee660 BH |
2083 | } |
2084 | ||
eb9f6744 BH |
2085 | if (!ok) |
2086 | goto fail; | |
2087 | ||
4b988280 | 2088 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2089 | rc = efx->phy_op->init(efx); |
2090 | if (rc) | |
2091 | goto fail; | |
2092 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2093 | netif_err(efx, drv, efx->net_dev, |
2094 | "could not restore PHY settings\n"); | |
4b988280 SH |
2095 | } |
2096 | ||
eb9f6744 | 2097 | efx->mac_op->reconfigure(efx); |
8ceee660 | 2098 | |
eb9f6744 | 2099 | efx_init_channels(efx); |
64eebcfd | 2100 | efx_restore_filters(efx); |
eb9f6744 | 2101 | |
eb9f6744 BH |
2102 | mutex_unlock(&efx->mac_lock); |
2103 | ||
2104 | efx_start_all(efx); | |
2105 | ||
2106 | return 0; | |
2107 | ||
2108 | fail: | |
2109 | efx->port_initialized = false; | |
2467ca46 BH |
2110 | |
2111 | mutex_unlock(&efx->mac_lock); | |
2112 | ||
8ceee660 BH |
2113 | return rc; |
2114 | } | |
2115 | ||
eb9f6744 BH |
2116 | /* Reset the NIC using the specified method. Note that the reset may |
2117 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2118 | * |
eb9f6744 | 2119 | * Caller must hold the rtnl_lock. |
8ceee660 | 2120 | */ |
eb9f6744 | 2121 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2122 | { |
eb9f6744 BH |
2123 | int rc, rc2; |
2124 | bool disabled; | |
8ceee660 | 2125 | |
62776d03 BH |
2126 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2127 | RESET_TYPE(method)); | |
8ceee660 | 2128 | |
e4abce85 | 2129 | netif_device_detach(efx->net_dev); |
d3245b28 | 2130 | efx_reset_down(efx, method); |
8ceee660 | 2131 | |
ef2b90ee | 2132 | rc = efx->type->reset(efx, method); |
8ceee660 | 2133 | if (rc) { |
62776d03 | 2134 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2135 | goto out; |
8ceee660 BH |
2136 | } |
2137 | ||
a7d529ae BH |
2138 | /* Clear flags for the scopes we covered. We assume the NIC and |
2139 | * driver are now quiescent so that there is no race here. | |
2140 | */ | |
2141 | efx->reset_pending &= -(1 << (method + 1)); | |
8ceee660 BH |
2142 | |
2143 | /* Reinitialise bus-mastering, which may have been turned off before | |
2144 | * the reset was scheduled. This is still appropriate, even in the | |
2145 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2146 | * can respond to requests. */ | |
2147 | pci_set_master(efx->pci_dev); | |
2148 | ||
eb9f6744 | 2149 | out: |
8ceee660 | 2150 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2151 | disabled = rc || method == RESET_TYPE_DISABLE; |
2152 | rc2 = efx_reset_up(efx, method, !disabled); | |
2153 | if (rc2) { | |
2154 | disabled = true; | |
2155 | if (!rc) | |
2156 | rc = rc2; | |
8ceee660 BH |
2157 | } |
2158 | ||
eb9f6744 | 2159 | if (disabled) { |
f49a4589 | 2160 | dev_close(efx->net_dev); |
62776d03 | 2161 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2162 | efx->state = STATE_DISABLED; |
f4bd954e | 2163 | } else { |
62776d03 | 2164 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2165 | netif_device_attach(efx->net_dev); |
f4bd954e | 2166 | } |
8ceee660 BH |
2167 | return rc; |
2168 | } | |
2169 | ||
2170 | /* The worker thread exists so that code that cannot sleep can | |
2171 | * schedule a reset for later. | |
2172 | */ | |
2173 | static void efx_reset_work(struct work_struct *data) | |
2174 | { | |
eb9f6744 | 2175 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
a7d529ae | 2176 | unsigned long pending = ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 2177 | |
a7d529ae | 2178 | if (!pending) |
319ba649 SH |
2179 | return; |
2180 | ||
eb9f6744 | 2181 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
a7d529ae | 2182 | * flags set so that efx_pci_probe_main will be retried */ |
eb9f6744 | 2183 | if (efx->state != STATE_RUNNING) { |
62776d03 BH |
2184 | netif_info(efx, drv, efx->net_dev, |
2185 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
2186 | return; |
2187 | } | |
2188 | ||
2189 | rtnl_lock(); | |
a7d529ae | 2190 | (void)efx_reset(efx, fls(pending) - 1); |
eb9f6744 | 2191 | rtnl_unlock(); |
8ceee660 BH |
2192 | } |
2193 | ||
2194 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2195 | { | |
2196 | enum reset_type method; | |
2197 | ||
8ceee660 BH |
2198 | switch (type) { |
2199 | case RESET_TYPE_INVISIBLE: | |
2200 | case RESET_TYPE_ALL: | |
2201 | case RESET_TYPE_WORLD: | |
2202 | case RESET_TYPE_DISABLE: | |
2203 | method = type; | |
0e2a9c7c BH |
2204 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2205 | RESET_TYPE(method)); | |
8ceee660 | 2206 | break; |
8ceee660 | 2207 | default: |
0e2a9c7c | 2208 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2209 | netif_dbg(efx, drv, efx->net_dev, |
2210 | "scheduling %s reset for %s\n", | |
2211 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2212 | break; |
2213 | } | |
8ceee660 | 2214 | |
a7d529ae | 2215 | set_bit(method, &efx->reset_pending); |
8ceee660 | 2216 | |
8880f4ec BH |
2217 | /* efx_process_channel() will no longer read events once a |
2218 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2219 | efx_mcdi_mode_poll(efx); | |
2220 | ||
1ab00629 | 2221 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2222 | } |
2223 | ||
2224 | /************************************************************************** | |
2225 | * | |
2226 | * List of NICs we support | |
2227 | * | |
2228 | **************************************************************************/ | |
2229 | ||
2230 | /* PCI device ID table */ | |
a3aa1884 | 2231 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2232 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2233 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2234 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2235 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2236 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2237 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
937383a5 | 2238 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, BETHPAGE_A_P_DEVID), |
8880f4ec | 2239 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
937383a5 | 2240 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, SIENA_A_P_DEVID), |
8880f4ec | 2241 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8ceee660 BH |
2242 | {0} /* end of list */ |
2243 | }; | |
2244 | ||
2245 | /************************************************************************** | |
2246 | * | |
3759433d | 2247 | * Dummy PHY/MAC operations |
8ceee660 | 2248 | * |
01aad7b6 | 2249 | * Can be used for some unimplemented operations |
8ceee660 BH |
2250 | * Needed so all function pointers are valid and do not have to be tested |
2251 | * before use | |
2252 | * | |
2253 | **************************************************************************/ | |
2254 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2255 | { | |
2256 | return 0; | |
2257 | } | |
2258 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2259 | |
2260 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2261 | { |
2262 | return false; | |
2263 | } | |
8ceee660 | 2264 | |
6c8c2513 | 2265 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2266 | .init = efx_port_dummy_op_int, |
d3245b28 | 2267 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2268 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2269 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2270 | }; |
2271 | ||
8ceee660 BH |
2272 | /************************************************************************** |
2273 | * | |
2274 | * Data housekeeping | |
2275 | * | |
2276 | **************************************************************************/ | |
2277 | ||
2278 | /* This zeroes out and then fills in the invariants in a struct | |
2279 | * efx_nic (including all sub-structures). | |
2280 | */ | |
6c8c2513 | 2281 | static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type, |
8ceee660 BH |
2282 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2283 | { | |
4642610c | 2284 | int i; |
8ceee660 BH |
2285 | |
2286 | /* Initialise common structures */ | |
2287 | memset(efx, 0, sizeof(*efx)); | |
2288 | spin_lock_init(&efx->biu_lock); | |
76884835 BH |
2289 | #ifdef CONFIG_SFC_MTD |
2290 | INIT_LIST_HEAD(&efx->mtd_list); | |
2291 | #endif | |
8ceee660 BH |
2292 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2293 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2294 | efx->pci_dev = pci_dev; | |
62776d03 | 2295 | efx->msg_enable = debug; |
8ceee660 | 2296 | efx->state = STATE_INIT; |
8ceee660 | 2297 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2298 | |
2299 | efx->net_dev = net_dev; | |
8ceee660 BH |
2300 | spin_lock_init(&efx->stats_lock); |
2301 | mutex_init(&efx->mac_lock); | |
b895d73e | 2302 | efx->mac_op = type->default_mac_ops; |
8ceee660 | 2303 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 2304 | efx->mdio.dev = net_dev; |
766ca0fa | 2305 | INIT_WORK(&efx->mac_work, efx_mac_work); |
8ceee660 BH |
2306 | |
2307 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2308 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2309 | if (!efx->channel[i]) | |
2310 | goto fail; | |
8ceee660 BH |
2311 | } |
2312 | ||
2313 | efx->type = type; | |
2314 | ||
8ceee660 BH |
2315 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2316 | ||
2317 | /* Higher numbered interrupt modes are less capable! */ | |
2318 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2319 | interrupt_mode); | |
2320 | ||
6977dc63 BH |
2321 | /* Would be good to use the net_dev name, but we're too early */ |
2322 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2323 | pci_name(pci_dev)); | |
2324 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2325 | if (!efx->workqueue) |
4642610c | 2326 | goto fail; |
8d9853d9 | 2327 | |
8ceee660 | 2328 | return 0; |
4642610c BH |
2329 | |
2330 | fail: | |
2331 | efx_fini_struct(efx); | |
2332 | return -ENOMEM; | |
8ceee660 BH |
2333 | } |
2334 | ||
2335 | static void efx_fini_struct(struct efx_nic *efx) | |
2336 | { | |
8313aca3 BH |
2337 | int i; |
2338 | ||
2339 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2340 | kfree(efx->channel[i]); | |
2341 | ||
8ceee660 BH |
2342 | if (efx->workqueue) { |
2343 | destroy_workqueue(efx->workqueue); | |
2344 | efx->workqueue = NULL; | |
2345 | } | |
2346 | } | |
2347 | ||
2348 | /************************************************************************** | |
2349 | * | |
2350 | * PCI interface | |
2351 | * | |
2352 | **************************************************************************/ | |
2353 | ||
2354 | /* Main body of final NIC shutdown code | |
2355 | * This is called only at module unload (or hotplug removal). | |
2356 | */ | |
2357 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2358 | { | |
64d8ad6d BH |
2359 | #ifdef CONFIG_RFS_ACCEL |
2360 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
2361 | efx->net_dev->rx_cpu_rmap = NULL; | |
2362 | #endif | |
152b6a62 | 2363 | efx_nic_fini_interrupt(efx); |
8ceee660 BH |
2364 | efx_fini_channels(efx); |
2365 | efx_fini_port(efx); | |
ef2b90ee | 2366 | efx->type->fini(efx); |
8ceee660 BH |
2367 | efx_fini_napi(efx); |
2368 | efx_remove_all(efx); | |
2369 | } | |
2370 | ||
2371 | /* Final NIC shutdown | |
2372 | * This is called only at module unload (or hotplug removal). | |
2373 | */ | |
2374 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2375 | { | |
2376 | struct efx_nic *efx; | |
2377 | ||
2378 | efx = pci_get_drvdata(pci_dev); | |
2379 | if (!efx) | |
2380 | return; | |
2381 | ||
2382 | /* Mark the NIC as fini, then stop the interface */ | |
2383 | rtnl_lock(); | |
2384 | efx->state = STATE_FINI; | |
2385 | dev_close(efx->net_dev); | |
2386 | ||
2387 | /* Allow any queued efx_resets() to complete */ | |
2388 | rtnl_unlock(); | |
2389 | ||
8ceee660 BH |
2390 | efx_unregister_netdev(efx); |
2391 | ||
7dde596e BH |
2392 | efx_mtd_remove(efx); |
2393 | ||
8ceee660 BH |
2394 | /* Wait for any scheduled resets to complete. No more will be |
2395 | * scheduled from this point because efx_stop_all() has been | |
2396 | * called, we are no longer registered with driverlink, and | |
2397 | * the net_device's have been removed. */ | |
1ab00629 | 2398 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2399 | |
2400 | efx_pci_remove_main(efx); | |
2401 | ||
8ceee660 | 2402 | efx_fini_io(efx); |
62776d03 | 2403 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 BH |
2404 | |
2405 | pci_set_drvdata(pci_dev, NULL); | |
2406 | efx_fini_struct(efx); | |
2407 | free_netdev(efx->net_dev); | |
2408 | }; | |
2409 | ||
2410 | /* Main body of NIC initialisation | |
2411 | * This is called at module load (or hotplug insertion, theoretically). | |
2412 | */ | |
2413 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2414 | { | |
2415 | int rc; | |
2416 | ||
2417 | /* Do start-of-day initialisation */ | |
2418 | rc = efx_probe_all(efx); | |
2419 | if (rc) | |
2420 | goto fail1; | |
2421 | ||
e8f14992 | 2422 | efx_init_napi(efx); |
8ceee660 | 2423 | |
ef2b90ee | 2424 | rc = efx->type->init(efx); |
8ceee660 | 2425 | if (rc) { |
62776d03 BH |
2426 | netif_err(efx, probe, efx->net_dev, |
2427 | "failed to initialise NIC\n"); | |
278c0621 | 2428 | goto fail3; |
8ceee660 BH |
2429 | } |
2430 | ||
2431 | rc = efx_init_port(efx); | |
2432 | if (rc) { | |
62776d03 BH |
2433 | netif_err(efx, probe, efx->net_dev, |
2434 | "failed to initialise port\n"); | |
278c0621 | 2435 | goto fail4; |
8ceee660 BH |
2436 | } |
2437 | ||
bc3c90a2 | 2438 | efx_init_channels(efx); |
8ceee660 | 2439 | |
152b6a62 | 2440 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2441 | if (rc) |
278c0621 | 2442 | goto fail5; |
8ceee660 BH |
2443 | |
2444 | return 0; | |
2445 | ||
278c0621 | 2446 | fail5: |
bc3c90a2 | 2447 | efx_fini_channels(efx); |
8ceee660 | 2448 | efx_fini_port(efx); |
8ceee660 | 2449 | fail4: |
ef2b90ee | 2450 | efx->type->fini(efx); |
8ceee660 BH |
2451 | fail3: |
2452 | efx_fini_napi(efx); | |
8ceee660 BH |
2453 | efx_remove_all(efx); |
2454 | fail1: | |
2455 | return rc; | |
2456 | } | |
2457 | ||
2458 | /* NIC initialisation | |
2459 | * | |
2460 | * This is called at module load (or hotplug insertion, | |
2461 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2462 | * sets up and registers the network devices with the kernel and hooks | |
2463 | * the interrupt service routine. It does not prepare the device for | |
2464 | * transmission; this is left to the first time one of the network | |
2465 | * interfaces is brought up (i.e. efx_net_open). | |
2466 | */ | |
2467 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2468 | const struct pci_device_id *entry) | |
2469 | { | |
6c8c2513 | 2470 | const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data; |
8ceee660 BH |
2471 | struct net_device *net_dev; |
2472 | struct efx_nic *efx; | |
2473 | int i, rc; | |
2474 | ||
2475 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2476 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2477 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2478 | if (!net_dev) |
2479 | return -ENOMEM; | |
c383b537 | 2480 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 | 2481 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2482 | NETIF_F_RXCSUM); |
738a8f4b BH |
2483 | if (type->offload_features & NETIF_F_V6_CSUM) |
2484 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2485 | /* Mask for features that also apply to VLAN devices */ |
2486 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2487 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2488 | NETIF_F_RXCSUM); | |
2489 | /* All offloads can be toggled */ | |
2490 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
767e468c | 2491 | efx = netdev_priv(net_dev); |
8ceee660 | 2492 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2493 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2494 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2495 | if (rc) | |
2496 | goto fail1; | |
2497 | ||
62776d03 | 2498 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2499 | "Solarflare NIC detected\n"); |
8ceee660 BH |
2500 | |
2501 | /* Set up basic I/O (BAR mappings etc) */ | |
2502 | rc = efx_init_io(efx); | |
2503 | if (rc) | |
2504 | goto fail2; | |
2505 | ||
2506 | /* No serialisation is required with the reset path because | |
2507 | * we're in STATE_INIT. */ | |
2508 | for (i = 0; i < 5; i++) { | |
2509 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2510 | |
2511 | /* Serialise against efx_reset(). No more resets will be | |
2512 | * scheduled since efx_stop_all() has been called, and we | |
2513 | * have not and never have been registered with either | |
2514 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2515 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2516 | |
fa402b2e | 2517 | if (rc == 0) { |
a7d529ae | 2518 | if (efx->reset_pending) { |
fa402b2e SH |
2519 | /* If there was a scheduled reset during |
2520 | * probe, the NIC is probably hosed anyway */ | |
2521 | efx_pci_remove_main(efx); | |
2522 | rc = -EIO; | |
2523 | } else { | |
2524 | break; | |
2525 | } | |
2526 | } | |
2527 | ||
8ceee660 | 2528 | /* Retry if a recoverably reset event has been scheduled */ |
a7d529ae BH |
2529 | if (efx->reset_pending & |
2530 | ~(1 << RESET_TYPE_INVISIBLE | 1 << RESET_TYPE_ALL) || | |
2531 | !efx->reset_pending) | |
8ceee660 BH |
2532 | goto fail3; |
2533 | ||
a7d529ae | 2534 | efx->reset_pending = 0; |
8ceee660 BH |
2535 | } |
2536 | ||
2537 | if (rc) { | |
62776d03 | 2538 | netif_err(efx, probe, efx->net_dev, "Could not reset NIC\n"); |
8ceee660 BH |
2539 | goto fail4; |
2540 | } | |
2541 | ||
55edc6e6 BH |
2542 | /* Switch to the running state before we expose the device to the OS, |
2543 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2544 | efx->state = STATE_RUNNING; |
7dde596e | 2545 | |
8ceee660 BH |
2546 | rc = efx_register_netdev(efx); |
2547 | if (rc) | |
2548 | goto fail5; | |
2549 | ||
62776d03 | 2550 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 BH |
2551 | |
2552 | rtnl_lock(); | |
2553 | efx_mtd_probe(efx); /* allowed to fail */ | |
2554 | rtnl_unlock(); | |
8ceee660 BH |
2555 | return 0; |
2556 | ||
2557 | fail5: | |
2558 | efx_pci_remove_main(efx); | |
2559 | fail4: | |
2560 | fail3: | |
2561 | efx_fini_io(efx); | |
2562 | fail2: | |
2563 | efx_fini_struct(efx); | |
2564 | fail1: | |
5e2a911c | 2565 | WARN_ON(rc > 0); |
62776d03 | 2566 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2567 | free_netdev(net_dev); |
2568 | return rc; | |
2569 | } | |
2570 | ||
89c758fa BH |
2571 | static int efx_pm_freeze(struct device *dev) |
2572 | { | |
2573 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2574 | ||
2575 | efx->state = STATE_FINI; | |
2576 | ||
2577 | netif_device_detach(efx->net_dev); | |
2578 | ||
2579 | efx_stop_all(efx); | |
2580 | efx_fini_channels(efx); | |
2581 | ||
2582 | return 0; | |
2583 | } | |
2584 | ||
2585 | static int efx_pm_thaw(struct device *dev) | |
2586 | { | |
2587 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2588 | ||
2589 | efx->state = STATE_INIT; | |
2590 | ||
2591 | efx_init_channels(efx); | |
2592 | ||
2593 | mutex_lock(&efx->mac_lock); | |
2594 | efx->phy_op->reconfigure(efx); | |
2595 | mutex_unlock(&efx->mac_lock); | |
2596 | ||
2597 | efx_start_all(efx); | |
2598 | ||
2599 | netif_device_attach(efx->net_dev); | |
2600 | ||
2601 | efx->state = STATE_RUNNING; | |
2602 | ||
2603 | efx->type->resume_wol(efx); | |
2604 | ||
319ba649 SH |
2605 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2606 | queue_work(reset_workqueue, &efx->reset_work); | |
2607 | ||
89c758fa BH |
2608 | return 0; |
2609 | } | |
2610 | ||
2611 | static int efx_pm_poweroff(struct device *dev) | |
2612 | { | |
2613 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2614 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2615 | ||
2616 | efx->type->fini(efx); | |
2617 | ||
a7d529ae | 2618 | efx->reset_pending = 0; |
89c758fa BH |
2619 | |
2620 | pci_save_state(pci_dev); | |
2621 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2622 | } | |
2623 | ||
2624 | /* Used for both resume and restore */ | |
2625 | static int efx_pm_resume(struct device *dev) | |
2626 | { | |
2627 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2628 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2629 | int rc; | |
2630 | ||
2631 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2632 | if (rc) | |
2633 | return rc; | |
2634 | pci_restore_state(pci_dev); | |
2635 | rc = pci_enable_device(pci_dev); | |
2636 | if (rc) | |
2637 | return rc; | |
2638 | pci_set_master(efx->pci_dev); | |
2639 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2640 | if (rc) | |
2641 | return rc; | |
2642 | rc = efx->type->init(efx); | |
2643 | if (rc) | |
2644 | return rc; | |
2645 | efx_pm_thaw(dev); | |
2646 | return 0; | |
2647 | } | |
2648 | ||
2649 | static int efx_pm_suspend(struct device *dev) | |
2650 | { | |
2651 | int rc; | |
2652 | ||
2653 | efx_pm_freeze(dev); | |
2654 | rc = efx_pm_poweroff(dev); | |
2655 | if (rc) | |
2656 | efx_pm_resume(dev); | |
2657 | return rc; | |
2658 | } | |
2659 | ||
2660 | static struct dev_pm_ops efx_pm_ops = { | |
2661 | .suspend = efx_pm_suspend, | |
2662 | .resume = efx_pm_resume, | |
2663 | .freeze = efx_pm_freeze, | |
2664 | .thaw = efx_pm_thaw, | |
2665 | .poweroff = efx_pm_poweroff, | |
2666 | .restore = efx_pm_resume, | |
2667 | }; | |
2668 | ||
8ceee660 | 2669 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2670 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2671 | .id_table = efx_pci_table, |
2672 | .probe = efx_pci_probe, | |
2673 | .remove = efx_pci_remove, | |
89c758fa | 2674 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2675 | }; |
2676 | ||
2677 | /************************************************************************** | |
2678 | * | |
2679 | * Kernel module interface | |
2680 | * | |
2681 | *************************************************************************/ | |
2682 | ||
2683 | module_param(interrupt_mode, uint, 0444); | |
2684 | MODULE_PARM_DESC(interrupt_mode, | |
2685 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2686 | ||
2687 | static int __init efx_init_module(void) | |
2688 | { | |
2689 | int rc; | |
2690 | ||
2691 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2692 | ||
2693 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2694 | if (rc) | |
2695 | goto err_notifier; | |
2696 | ||
1ab00629 SH |
2697 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2698 | if (!reset_workqueue) { | |
2699 | rc = -ENOMEM; | |
2700 | goto err_reset; | |
2701 | } | |
8ceee660 BH |
2702 | |
2703 | rc = pci_register_driver(&efx_pci_driver); | |
2704 | if (rc < 0) | |
2705 | goto err_pci; | |
2706 | ||
2707 | return 0; | |
2708 | ||
2709 | err_pci: | |
1ab00629 SH |
2710 | destroy_workqueue(reset_workqueue); |
2711 | err_reset: | |
8ceee660 BH |
2712 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2713 | err_notifier: | |
2714 | return rc; | |
2715 | } | |
2716 | ||
2717 | static void __exit efx_exit_module(void) | |
2718 | { | |
2719 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2720 | ||
2721 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2722 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2723 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2724 | ||
2725 | } | |
2726 | ||
2727 | module_init(efx_init_module); | |
2728 | module_exit(efx_exit_module); | |
2729 | ||
906bb26c BH |
2730 | MODULE_AUTHOR("Solarflare Communications and " |
2731 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2732 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2733 | MODULE_LICENSE("GPL"); | |
2734 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |