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sfc: Do not assume efx_nic_type::ev_fini is idempotent
[deliverable/linux.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6 4 * Copyright 2005-2011 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
20#include <linux/crc32.h>
21#include <linux/ethtool.h>
aa6ef27e 22#include <linux/topology.h>
5a0e3ad6 23#include <linux/gfp.h>
626950db 24#include <linux/aer.h>
b28405b0 25#include <linux/interrupt.h>
8ceee660 26#include "net_driver.h"
8ceee660 27#include "efx.h"
744093c9 28#include "nic.h"
dd40781e 29#include "selftest.h"
8ceee660 30
8880f4ec 31#include "mcdi.h"
fd371e32 32#include "workarounds.h"
8880f4ec 33
c459302d
BH		 34/**************************************************************************
35 *
36 * Type name strings
37 *
38 **************************************************************************
39 */
40
41/* Loopback mode names (see LOOPBACK_MODE()) */
42const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 43const char *const efx_loopback_mode_names[] = {
c459302d 44 [LOOPBACK_NONE] = "NONE",
e58f69f4 45 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 46 [LOOPBACK_GMAC] = "GMAC",
47 [LOOPBACK_XGMII] = "XGMII",
48 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH		 49 [LOOPBACK_XAUI] = "XAUI",
50 [LOOPBACK_GMII] = "GMII",
51 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH		 52 [LOOPBACK_XGBR] = "XGBR",
53 [LOOPBACK_XFI] = "XFI",
54 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
55 [LOOPBACK_GMII_FAR] = "GMII_FAR",
56 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
57 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 58 [LOOPBACK_GPHY] = "GPHY",
59 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH		 60 [LOOPBACK_PCS] = "PCS",
61 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 62 [LOOPBACK_XPORT] = "XPORT",
63 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 64 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH		 65 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
66 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 67 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH		 68 [LOOPBACK_XFI_WS] = "XFI_WS",
69 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 70 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 71};
72
c459302d 73const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 74const char *const efx_reset_type_names[] = {
626950db
AR		 75 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
76 [RESET_TYPE_ALL] = "ALL",
77 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
78 [RESET_TYPE_WORLD] = "WORLD",
79 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
80 [RESET_TYPE_DISABLE] = "DISABLE",
81 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
82 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
83 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
84 [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH",
85 [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH",
86 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
87 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
c459302d
BH		 88};
89
1ab00629
SH		 90/* Reset workqueue. If any NIC has a hardware failure then a reset will be
91 * queued onto this work queue. This is not a per-nic work queue, because
92 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
93 */
94static struct workqueue_struct *reset_workqueue;
95
8ceee660
BH		 96/**************************************************************************
97 *
98 * Configurable values
99 *
100 *************************************************************************/
101
8ceee660
BH		 102/*
103 * Use separate channels for TX and RX events
104 *
28b581ab
NT		 105 * Set this to 1 to use separate channels for TX and RX. It allows us
106 * to control interrupt affinity separately for TX and RX.
8ceee660 107 *
28b581ab 108 * This is only used in MSI-X interrupt mode
8ceee660 109 */
b9cc977d
BH		 110static bool separate_tx_channels;
111module_param(separate_tx_channels, bool, 0444);
28b581ab
NT		 112MODULE_PARM_DESC(separate_tx_channels,
113 "Use separate channels for TX and RX");
8ceee660
BH		 114
115/* This is the weight assigned to each of the (per-channel) virtual
116 * NAPI devices.
117 */
118static int napi_weight = 64;
119
120/* This is the time (in jiffies) between invocations of the hardware
626950db
AR		 121 * monitor.
122 * On Falcon-based NICs, this will:
e254c274
BH		 123 * - Check the on-board hardware monitor;
124 * - Poll the link state and reconfigure the hardware as necessary.
626950db
AR		 125 * On Siena-based NICs for power systems with EEH support, this will give EEH a
126 * chance to start.
8ceee660 127 */
d215697f 128static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 129
8ceee660
BH		 130/* Initial interrupt moderation settings. They can be modified after
131 * module load with ethtool.
132 *
133 * The default for RX should strike a balance between increasing the
134 * round-trip latency and reducing overhead.
135 */
136static unsigned int rx_irq_mod_usec = 60;
137
138/* Initial interrupt moderation settings. They can be modified after
139 * module load with ethtool.
140 *
141 * This default is chosen to ensure that a 10G link does not go idle
142 * while a TX queue is stopped after it has become full. A queue is
143 * restarted when it drops below half full. The time this takes (assuming
144 * worst case 3 descriptors per packet and 1024 descriptors) is
145 * 512 / 3 * 1.2 = 205 usec.
146 */
147static unsigned int tx_irq_mod_usec = 150;
148
149/* This is the first interrupt mode to try out of:
150 * 0 => MSI-X
151 * 1 => MSI
152 * 2 => legacy
153 */
154static unsigned int interrupt_mode;
155
156/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
157 * i.e. the number of CPUs among which we may distribute simultaneous
158 * interrupt handling.
159 *
160 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 161 * The default (0) means to assign an interrupt to each core.
8ceee660
BH		 162 */
163static unsigned int rss_cpus;
164module_param(rss_cpus, uint, 0444);
165MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
166
b9cc977d
BH		 167static bool phy_flash_cfg;
168module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH		 169MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
170
e7bed9c8 171static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH		 172module_param(irq_adapt_low_thresh, uint, 0644);
173MODULE_PARM_DESC(irq_adapt_low_thresh,
174 "Threshold score for reducing IRQ moderation");
175
e7bed9c8 176static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH		 177module_param(irq_adapt_high_thresh, uint, 0644);
178MODULE_PARM_DESC(irq_adapt_high_thresh,
179 "Threshold score for increasing IRQ moderation");
180
62776d03
BH		 181static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
182 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
183 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
184 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
185module_param(debug, uint, 0);
186MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
187
8ceee660
BH		 188/**************************************************************************
189 *
190 * Utility functions and prototypes
191 *
192 *************************************************************************/
4642610c 193
d8291187
BH		 194static void efx_soft_enable_interrupts(struct efx_nic *efx);
195static void efx_soft_disable_interrupts(struct efx_nic *efx);
7f967c01 196static void efx_remove_channel(struct efx_channel *channel);
4642610c 197static void efx_remove_channels(struct efx_nic *efx);
7f967c01 198static const struct efx_channel_type efx_default_channel_type;
8ceee660 199static void efx_remove_port(struct efx_nic *efx);
7f967c01 200static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 201static void efx_fini_napi(struct efx_nic *efx);
e8f14992 202static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH		 203static void efx_fini_struct(struct efx_nic *efx);
204static void efx_start_all(struct efx_nic *efx);
205static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH		 206
207#define EFX_ASSERT_RESET_SERIALISED(efx) \
208 do { \
f16aeea0 209 if ((efx->state == STATE_READY) || \
626950db 210 (efx->state == STATE_RECOVERY) || \
332c1ce9 211 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 212 ASSERT_RTNL(); \
213 } while (0)
214
8b7325b4
BH		 215static int efx_check_disabled(struct efx_nic *efx)
216{
626950db 217 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
8b7325b4
BH		 218 netif_err(efx, drv, efx->net_dev,
219 "device is disabled due to earlier errors\n");
220 return -EIO;
221 }
222 return 0;
223}
224
8ceee660
BH		 225/**************************************************************************
226 *
227 * Event queue processing
228 *
229 *************************************************************************/
230
231/* Process channel's event queue
232 *
233 * This function is responsible for processing the event queue of a
234 * single channel. The caller must guarantee that this function will
235 * never be concurrently called more than once on the same channel,
236 * though different channels may be being processed concurrently.
237 */
fa236e18 238static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 239{
fa236e18 240 int spent;
8ceee660 241
9f2cb71c 242 if (unlikely(!channel->enabled))
42cbe2d7 243 return 0;
8ceee660 244
fa236e18 245 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH		 246 if (spent && efx_channel_has_rx_queue(channel)) {
247 struct efx_rx_queue *rx_queue =
248 efx_channel_get_rx_queue(channel);
249
ff734ef4 250 efx_rx_flush_packet(channel);
d8aec745 251 efx_fast_push_rx_descriptors(rx_queue);
8ceee660
BH		 252 }
253
fa236e18 254 return spent;
8ceee660
BH		 255}
256
8ceee660
BH		 257/* NAPI poll handler
258 *
259 * NAPI guarantees serialisation of polls of the same device, which
260 * provides the guarantee required by efx_process_channel().
261 */
262static int efx_poll(struct napi_struct *napi, int budget)
263{
264 struct efx_channel *channel =
265 container_of(napi, struct efx_channel, napi_str);
62776d03 266 struct efx_nic *efx = channel->efx;
fa236e18 267 int spent;
8ceee660 268
62776d03
BH		 269 netif_vdbg(efx, intr, efx->net_dev,
270 "channel %d NAPI poll executing on CPU %d\n",
271 channel->channel, raw_smp_processor_id());
8ceee660 272
fa236e18 273 spent = efx_process_channel(channel, budget);
8ceee660 274
fa236e18 275 if (spent < budget) {
9d9a6973 276 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH		 277 efx->irq_rx_adaptive &&
278 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH		 279 if (unlikely(channel->irq_mod_score <
280 irq_adapt_low_thresh)) {
0d86ebd8
BH		 281 if (channel->irq_moderation > 1) {
282 channel->irq_moderation -= 1;
ef2b90ee 283 efx->type->push_irq_moderation(channel);
0d86ebd8 284 }
6fb70fd1
BH		 285 } else if (unlikely(channel->irq_mod_score >
286 irq_adapt_high_thresh)) {
0d86ebd8
BH		 287 if (channel->irq_moderation <
288 efx->irq_rx_moderation) {
289 channel->irq_moderation += 1;
ef2b90ee 290 efx->type->push_irq_moderation(channel);
0d86ebd8 291 }
6fb70fd1 292 }
6fb70fd1
BH		 293 channel->irq_count = 0;
294 channel->irq_mod_score = 0;
295 }
296
64d8ad6d
BH		 297 efx_filter_rfs_expire(channel);
298
8ceee660 299 /* There is no race here; although napi_disable() will
288379f0 300 * only wait for napi_complete(), this isn't a problem
514bedbc 301 * since efx_nic_eventq_read_ack() will have no effect if
8ceee660
BH		 302 * interrupts have already been disabled.
303 */
288379f0 304 napi_complete(napi);
514bedbc 305 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 306 }
307
fa236e18 308 return spent;
8ceee660
BH		 309}
310
8ceee660
BH		 311/* Create event queue
312 * Event queue memory allocations are done only once. If the channel
313 * is reset, the memory buffer will be reused; this guards against
314 * errors during channel reset and also simplifies interrupt handling.
315 */
316static int efx_probe_eventq(struct efx_channel *channel)
317{
ecc910f5
SH		 318 struct efx_nic *efx = channel->efx;
319 unsigned long entries;
320
86ee5302 321 netif_dbg(efx, probe, efx->net_dev,
62776d03 322 "chan %d create event queue\n", channel->channel);
8ceee660 323
ecc910f5
SH		 324 /* Build an event queue with room for one event per tx and rx buffer,
325 * plus some extra for link state events and MCDI completions. */
326 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
327 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
328 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
329
152b6a62 330 return efx_nic_probe_eventq(channel);
8ceee660
BH		 331}
332
333/* Prepare channel's event queue */
bc3c90a2 334static void efx_init_eventq(struct efx_channel *channel)
8ceee660 335{
62776d03
BH		 336 netif_dbg(channel->efx, drv, channel->efx->net_dev,
337 "chan %d init event queue\n", channel->channel);
8ceee660
BH		 338
339 channel->eventq_read_ptr = 0;
340
152b6a62 341 efx_nic_init_eventq(channel);
be3fc09c 342 channel->eventq_init = true;
8ceee660
BH		 343}
344
9f2cb71c
BH		 345/* Enable event queue processing and NAPI */
346static void efx_start_eventq(struct efx_channel *channel)
347{
348 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
349 "chan %d start event queue\n", channel->channel);
350
514bedbc 351 /* Make sure the NAPI handler sees the enabled flag set */
9f2cb71c
BH		 352 channel->enabled = true;
353 smp_wmb();
354
355 napi_enable(&channel->napi_str);
356 efx_nic_eventq_read_ack(channel);
357}
358
359/* Disable event queue processing and NAPI */
360static void efx_stop_eventq(struct efx_channel *channel)
361{
362 if (!channel->enabled)
363 return;
364
365 napi_disable(&channel->napi_str);
366 channel->enabled = false;
367}
368
8ceee660
BH		 369static void efx_fini_eventq(struct efx_channel *channel)
370{
be3fc09c
BH		 371 if (!channel->eventq_init)
372 return;
373
62776d03
BH		 374 netif_dbg(channel->efx, drv, channel->efx->net_dev,
375 "chan %d fini event queue\n", channel->channel);
8ceee660 376
152b6a62 377 efx_nic_fini_eventq(channel);
be3fc09c 378 channel->eventq_init = false;
8ceee660
BH		 379}
380
381static void efx_remove_eventq(struct efx_channel *channel)
382{
62776d03
BH		 383 netif_dbg(channel->efx, drv, channel->efx->net_dev,
384 "chan %d remove event queue\n", channel->channel);
8ceee660 385
152b6a62 386 efx_nic_remove_eventq(channel);
8ceee660
BH		 387}
388
389/**************************************************************************
390 *
391 * Channel handling
392 *
393 *************************************************************************/
394
7f967c01 395/* Allocate and initialise a channel structure. */
4642610c
BH		 396static struct efx_channel *
397efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
398{
399 struct efx_channel *channel;
400 struct efx_rx_queue *rx_queue;
401 struct efx_tx_queue *tx_queue;
402 int j;
403
7f967c01
BH		 404 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
405 if (!channel)
406 return NULL;
4642610c 407
7f967c01
BH		 408 channel->efx = efx;
409 channel->channel = i;
410 channel->type = &efx_default_channel_type;
4642610c 411
7f967c01
BH		 412 for (j = 0; j < EFX_TXQ_TYPES; j++) {
413 tx_queue = &channel->tx_queue[j];
414 tx_queue->efx = efx;
415 tx_queue->queue = i * EFX_TXQ_TYPES + j;
416 tx_queue->channel = channel;
417 }
4642610c 418
7f967c01
BH		 419 rx_queue = &channel->rx_queue;
420 rx_queue->efx = efx;
421 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
422 (unsigned long)rx_queue);
4642610c 423
7f967c01
BH		 424 return channel;
425}
426
427/* Allocate and initialise a channel structure, copying parameters
428 * (but not resources) from an old channel structure.
429 */
430static struct efx_channel *
431efx_copy_channel(const struct efx_channel *old_channel)
432{
433 struct efx_channel *channel;
434 struct efx_rx_queue *rx_queue;
435 struct efx_tx_queue *tx_queue;
436 int j;
4642610c 437
7f967c01
BH		 438 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
439 if (!channel)
440 return NULL;
441
442 *channel = *old_channel;
443
444 channel->napi_dev = NULL;
445 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 446
7f967c01
BH		 447 for (j = 0; j < EFX_TXQ_TYPES; j++) {
448 tx_queue = &channel->tx_queue[j];
449 if (tx_queue->channel)
4642610c 450 tx_queue->channel = channel;
7f967c01
BH		 451 tx_queue->buffer = NULL;
452 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH		 453 }
454
4642610c 455 rx_queue = &channel->rx_queue;
7f967c01
BH		 456 rx_queue->buffer = NULL;
457 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH		 458 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
459 (unsigned long)rx_queue);
460
461 return channel;
462}
463
8ceee660
BH		 464static int efx_probe_channel(struct efx_channel *channel)
465{
466 struct efx_tx_queue *tx_queue;
467 struct efx_rx_queue *rx_queue;
468 int rc;
469
62776d03
BH		 470 netif_dbg(channel->efx, probe, channel->efx->net_dev,
471 "creating channel %d\n", channel->channel);
8ceee660 472
7f967c01
BH		 473 rc = channel->type->pre_probe(channel);
474 if (rc)
475 goto fail;
476
8ceee660
BH		 477 rc = efx_probe_eventq(channel);
478 if (rc)
7f967c01 479 goto fail;
8ceee660
BH		 480
481 efx_for_each_channel_tx_queue(tx_queue, channel) {
482 rc = efx_probe_tx_queue(tx_queue);
483 if (rc)
7f967c01 484 goto fail;
8ceee660
BH		 485 }
486
487 efx_for_each_channel_rx_queue(rx_queue, channel) {
488 rc = efx_probe_rx_queue(rx_queue);
489 if (rc)
7f967c01 490 goto fail;
8ceee660
BH		 491 }
492
493 channel->n_rx_frm_trunc = 0;
494
495 return 0;
496
7f967c01
BH		 497fail:
498 efx_remove_channel(channel);
8ceee660
BH		 499 return rc;
500}
501
7f967c01
BH		 502static void
503efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
504{
505 struct efx_nic *efx = channel->efx;
506 const char *type;
507 int number;
508
509 number = channel->channel;
510 if (efx->tx_channel_offset == 0) {
511 type = "";
512 } else if (channel->channel < efx->tx_channel_offset) {
513 type = "-rx";
514 } else {
515 type = "-tx";
516 number -= efx->tx_channel_offset;
517 }
518 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
519}
8ceee660 520
56536e9c
BH		 521static void efx_set_channel_names(struct efx_nic *efx)
522{
523 struct efx_channel *channel;
56536e9c 524
7f967c01
BH		 525 efx_for_each_channel(channel, efx)
526 channel->type->get_name(channel,
d8291187
BH		 527 efx->msi_context[channel->channel].name,
528 sizeof(efx->msi_context[0].name));
56536e9c
BH		 529}
530
4642610c
BH		 531static int efx_probe_channels(struct efx_nic *efx)
532{
533 struct efx_channel *channel;
534 int rc;
535
536 /* Restart special buffer allocation */
537 efx->next_buffer_table = 0;
538
c92aaff1
BH		 539 /* Probe channels in reverse, so that any 'extra' channels
540 * use the start of the buffer table. This allows the traffic
541 * channels to be resized without moving them or wasting the
542 * entries before them.
543 */
544 efx_for_each_channel_rev(channel, efx) {
4642610c
BH		 545 rc = efx_probe_channel(channel);
546 if (rc) {
547 netif_err(efx, probe, efx->net_dev,
548 "failed to create channel %d\n",
549 channel->channel);
550 goto fail;
551 }
552 }
553 efx_set_channel_names(efx);
554
555 return 0;
556
557fail:
558 efx_remove_channels(efx);
559 return rc;
560}
561
8ceee660
BH		 562/* Channels are shutdown and reinitialised whilst the NIC is running
563 * to propagate configuration changes (mtu, checksum offload), or
564 * to clear hardware error conditions
565 */
9f2cb71c 566static void efx_start_datapath(struct efx_nic *efx)
8ceee660 567{
85740cdf 568 bool old_rx_scatter = efx->rx_scatter;
8ceee660
BH		 569 struct efx_tx_queue *tx_queue;
570 struct efx_rx_queue *rx_queue;
571 struct efx_channel *channel;
85740cdf 572 size_t rx_buf_len;
8ceee660 573
f7f13b0b
BH		 574 /* Calculate the rx buffer allocation parameters required to
575 * support the current MTU, including padding for header
576 * alignment and overruns.
577 */
272baeeb
BH		 578 efx->rx_dma_len = (efx->type->rx_buffer_hash_size +
579 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
580 efx->type->rx_buffer_padding);
85740cdf 581 rx_buf_len = (sizeof(struct efx_rx_page_state) +
c14ff2ea 582 NET_IP_ALIGN + efx->rx_dma_len);
85740cdf
BH		 583 if (rx_buf_len <= PAGE_SIZE) {
584 efx->rx_scatter = false;
585 efx->rx_buffer_order = 0;
85740cdf 586 } else if (efx->type->can_rx_scatter) {
950c54df 587 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
85740cdf 588 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
950c54df
BH		 589 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
590 EFX_RX_BUF_ALIGNMENT) >
591 PAGE_SIZE);
85740cdf
BH		 592 efx->rx_scatter = true;
593 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
594 efx->rx_buffer_order = 0;
85740cdf
BH		 595 } else {
596 efx->rx_scatter = false;
597 efx->rx_buffer_order = get_order(rx_buf_len);
85740cdf
BH		 598 }
599
1648a23f
DP		 600 efx_rx_config_page_split(efx);
601 if (efx->rx_buffer_order)
602 netif_dbg(efx, drv, efx->net_dev,
603 "RX buf len=%u; page order=%u batch=%u\n",
604 efx->rx_dma_len, efx->rx_buffer_order,
605 efx->rx_pages_per_batch);
606 else
607 netif_dbg(efx, drv, efx->net_dev,
608 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
609 efx->rx_dma_len, efx->rx_page_buf_step,
610 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
2768935a 611
85740cdf
BH		 612 /* RX filters also have scatter-enabled flags */
613 if (efx->rx_scatter != old_rx_scatter)
614 efx_filter_update_rx_scatter(efx);
8ceee660 615
14bf718f
BH		 616 /* We must keep at least one descriptor in a TX ring empty.
617 * We could avoid this when the queue size does not exactly
618 * match the hardware ring size, but it's not that important.
619 * Therefore we stop the queue when one more skb might fill
620 * the ring completely. We wake it when half way back to
621 * empty.
622 */
623 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
624 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
625
8ceee660
BH		 626 /* Initialise the channels */
627 efx_for_each_channel(channel, efx) {
bc3c90a2
BH		 628 efx_for_each_channel_tx_queue(tx_queue, channel)
629 efx_init_tx_queue(tx_queue);
8ceee660 630
9f2cb71c 631 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 632 efx_init_rx_queue(rx_queue);
9f2cb71c
BH		 633 efx_nic_generate_fill_event(rx_queue);
634 }
8ceee660 635
85740cdf 636 WARN_ON(channel->rx_pkt_n_frags);
8ceee660 637 }
8ceee660 638
9f2cb71c
BH		 639 if (netif_device_present(efx->net_dev))
640 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH		 641}
642
9f2cb71c 643static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH		 644{
645 struct efx_channel *channel;
646 struct efx_tx_queue *tx_queue;
647 struct efx_rx_queue *rx_queue;
6bc5d3a9 648 int rc;
8ceee660
BH		 649
650 EFX_ASSERT_RESET_SERIALISED(efx);
651 BUG_ON(efx->port_enabled);
652
d8aec745
BH		 653 /* Stop RX refill */
654 efx_for_each_channel(channel, efx) {
655 efx_for_each_channel_rx_queue(rx_queue, channel)
656 rx_queue->refill_enabled = false;
657 }
658
8ceee660 659 efx_for_each_channel(channel, efx) {
9f2cb71c
BH		 660 /* RX packet processing is pipelined, so wait for the
661 * NAPI handler to complete. At least event queue 0
662 * might be kept active by non-data events, so don't
663 * use napi_synchronize() but actually disable NAPI
664 * temporarily.
665 */
666 if (efx_channel_has_rx_queue(channel)) {
667 efx_stop_eventq(channel);
668 efx_start_eventq(channel);
669 }
e42c3d85 670 }
8ceee660 671
e42c3d85
BH		 672 rc = efx->type->fini_dmaq(efx);
673 if (rc && EFX_WORKAROUND_7803(efx)) {
674 /* Schedule a reset to recover from the flush failure. The
675 * descriptor caches reference memory we're about to free,
676 * but falcon_reconfigure_mac_wrapper() won't reconnect
677 * the MACs because of the pending reset.
678 */
679 netif_err(efx, drv, efx->net_dev,
680 "Resetting to recover from flush failure\n");
681 efx_schedule_reset(efx, RESET_TYPE_ALL);
682 } else if (rc) {
683 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
684 } else {
685 netif_dbg(efx, drv, efx->net_dev,
686 "successfully flushed all queues\n");
687 }
688
689 efx_for_each_channel(channel, efx) {
8ceee660
BH		 690 efx_for_each_channel_rx_queue(rx_queue, channel)
691 efx_fini_rx_queue(rx_queue);
94b274bf 692 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 693 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 694 }
695}
696
697static void efx_remove_channel(struct efx_channel *channel)
698{
699 struct efx_tx_queue *tx_queue;
700 struct efx_rx_queue *rx_queue;
701
62776d03
BH		 702 netif_dbg(channel->efx, drv, channel->efx->net_dev,
703 "destroy chan %d\n", channel->channel);
8ceee660
BH		 704
705 efx_for_each_channel_rx_queue(rx_queue, channel)
706 efx_remove_rx_queue(rx_queue);
94b274bf 707 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH		 708 efx_remove_tx_queue(tx_queue);
709 efx_remove_eventq(channel);
c31e5f9f 710 channel->type->post_remove(channel);
8ceee660
BH		 711}
712
4642610c
BH		 713static void efx_remove_channels(struct efx_nic *efx)
714{
715 struct efx_channel *channel;
716
717 efx_for_each_channel(channel, efx)
718 efx_remove_channel(channel);
719}
720
721int
722efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
723{
724 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
725 u32 old_rxq_entries, old_txq_entries;
7f967c01 726 unsigned i, next_buffer_table = 0;
8b7325b4
BH		 727 int rc;
728
729 rc = efx_check_disabled(efx);
730 if (rc)
731 return rc;
7f967c01
BH		 732
733 /* Not all channels should be reallocated. We must avoid
734 * reallocating their buffer table entries.
735 */
736 efx_for_each_channel(channel, efx) {
737 struct efx_rx_queue *rx_queue;
738 struct efx_tx_queue *tx_queue;
739
740 if (channel->type->copy)
741 continue;
742 next_buffer_table = max(next_buffer_table,
743 channel->eventq.index +
744 channel->eventq.entries);
745 efx_for_each_channel_rx_queue(rx_queue, channel)
746 next_buffer_table = max(next_buffer_table,
747 rx_queue->rxd.index +
748 rx_queue->rxd.entries);
749 efx_for_each_channel_tx_queue(tx_queue, channel)
750 next_buffer_table = max(next_buffer_table,
751 tx_queue->txd.index +
752 tx_queue->txd.entries);
753 }
4642610c 754
29c69a48 755 efx_device_detach_sync(efx);
4642610c 756 efx_stop_all(efx);
d8291187 757 efx_soft_disable_interrupts(efx);
4642610c 758
7f967c01 759 /* Clone channels (where possible) */
4642610c
BH		 760 memset(other_channel, 0, sizeof(other_channel));
761 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 762 channel = efx->channel[i];
763 if (channel->type->copy)
764 channel = channel->type->copy(channel);
4642610c
BH		 765 if (!channel) {
766 rc = -ENOMEM;
767 goto out;
768 }
769 other_channel[i] = channel;
770 }
771
772 /* Swap entry counts and channel pointers */
773 old_rxq_entries = efx->rxq_entries;
774 old_txq_entries = efx->txq_entries;
775 efx->rxq_entries = rxq_entries;
776 efx->txq_entries = txq_entries;
777 for (i = 0; i < efx->n_channels; i++) {
778 channel = efx->channel[i];
779 efx->channel[i] = other_channel[i];
780 other_channel[i] = channel;
781 }
782
7f967c01
BH		 783 /* Restart buffer table allocation */
784 efx->next_buffer_table = next_buffer_table;
e8f14992 785
e8f14992 786 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 787 channel = efx->channel[i];
788 if (!channel->type->copy)
789 continue;
790 rc = efx_probe_channel(channel);
791 if (rc)
792 goto rollback;
793 efx_init_napi_channel(efx->channel[i]);
e8f14992 794 }
7f967c01 795
4642610c 796out:
7f967c01
BH		 797 /* Destroy unused channel structures */
798 for (i = 0; i < efx->n_channels; i++) {
799 channel = other_channel[i];
800 if (channel && channel->type->copy) {
801 efx_fini_napi_channel(channel);
802 efx_remove_channel(channel);
803 kfree(channel);
804 }
805 }
4642610c 806
d8291187 807 efx_soft_enable_interrupts(efx);
4642610c 808 efx_start_all(efx);
29c69a48 809 netif_device_attach(efx->net_dev);
4642610c
BH		 810 return rc;
811
812rollback:
813 /* Swap back */
814 efx->rxq_entries = old_rxq_entries;
815 efx->txq_entries = old_txq_entries;
816 for (i = 0; i < efx->n_channels; i++) {
817 channel = efx->channel[i];
818 efx->channel[i] = other_channel[i];
819 other_channel[i] = channel;
820 }
821 goto out;
822}
823
90d683af 824void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 825{
90d683af 826 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH		 827}
828
7f967c01
BH		 829static const struct efx_channel_type efx_default_channel_type = {
830 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 831 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH		 832 .get_name = efx_get_channel_name,
833 .copy = efx_copy_channel,
834 .keep_eventq = false,
835};
836
837int efx_channel_dummy_op_int(struct efx_channel *channel)
838{
839 return 0;
840}
841
c31e5f9f
SH		 842void efx_channel_dummy_op_void(struct efx_channel *channel)
843{
844}
845
8ceee660
BH		 846/**************************************************************************
847 *
848 * Port handling
849 *
850 **************************************************************************/
851
852/* This ensures that the kernel is kept informed (via
853 * netif_carrier_on/off) of the link status, and also maintains the
854 * link status's stop on the port's TX queue.
855 */
fdaa9aed 856void efx_link_status_changed(struct efx_nic *efx)
8ceee660 857{
eb50c0d6
BH		 858 struct efx_link_state *link_state = &efx->link_state;
859
8ceee660
BH		 860 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
861 * that no events are triggered between unregister_netdev() and the
862 * driver unloading. A more general condition is that NETDEV_CHANGE
863 * can only be generated between NETDEV_UP and NETDEV_DOWN */
864 if (!netif_running(efx->net_dev))
865 return;
866
eb50c0d6 867 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 868 efx->n_link_state_changes++;
869
eb50c0d6 870 if (link_state->up)
8ceee660
BH		 871 netif_carrier_on(efx->net_dev);
872 else
873 netif_carrier_off(efx->net_dev);
874 }
875
876 /* Status message for kernel log */
2aa9ef11 877 if (link_state->up)
62776d03
BH		 878 netif_info(efx, link, efx->net_dev,
879 "link up at %uMbps %s-duplex (MTU %d)%s\n",
880 link_state->speed, link_state->fd ? "full" : "half",
881 efx->net_dev->mtu,
882 (efx->promiscuous ? " [PROMISC]" : ""));
2aa9ef11 883 else
62776d03 884 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH		 885}
886
d3245b28
BH		 887void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
888{
889 efx->link_advertising = advertising;
890 if (advertising) {
891 if (advertising & ADVERTISED_Pause)
892 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
893 else
894 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
895 if (advertising & ADVERTISED_Asym_Pause)
896 efx->wanted_fc ^= EFX_FC_TX;
897 }
898}
899
b5626946 900void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH		 901{
902 efx->wanted_fc = wanted_fc;
903 if (efx->link_advertising) {
904 if (wanted_fc & EFX_FC_RX)
905 efx->link_advertising |= (ADVERTISED_Pause |
906 ADVERTISED_Asym_Pause);
907 else
908 efx->link_advertising &= ~(ADVERTISED_Pause |
909 ADVERTISED_Asym_Pause);
910 if (wanted_fc & EFX_FC_TX)
911 efx->link_advertising ^= ADVERTISED_Asym_Pause;
912 }
913}
914
115122af
BH		 915static void efx_fini_port(struct efx_nic *efx);
916
d3245b28
BH		 917/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
918 * the MAC appropriately. All other PHY configuration changes are pushed
919 * through phy_op->set_settings(), and pushed asynchronously to the MAC
920 * through efx_monitor().
921 *
922 * Callers must hold the mac_lock
923 */
924int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 925{
d3245b28
BH		 926 enum efx_phy_mode phy_mode;
927 int rc;
8ceee660 928
d3245b28 929 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 930
0fca8c97 931 /* Serialise the promiscuous flag with efx_set_rx_mode. */
73ba7b68
BH		 932 netif_addr_lock_bh(efx->net_dev);
933 netif_addr_unlock_bh(efx->net_dev);
a816f75a 934
d3245b28
BH		 935 /* Disable PHY transmit in mac level loopbacks */
936 phy_mode = efx->phy_mode;
177dfcd8
BH		 937 if (LOOPBACK_INTERNAL(efx))
938 efx->phy_mode |= PHY_MODE_TX_DISABLED;
939 else
940 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 941
d3245b28 942 rc = efx->type->reconfigure_port(efx);
8ceee660 943
d3245b28
BH		 944 if (rc)
945 efx->phy_mode = phy_mode;
177dfcd8 946
d3245b28 947 return rc;
8ceee660
BH		 948}
949
950/* Reinitialise the MAC to pick up new PHY settings, even if the port is
951 * disabled. */
d3245b28 952int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 953{
d3245b28
BH		 954 int rc;
955
8ceee660
BH		 956 EFX_ASSERT_RESET_SERIALISED(efx);
957
958 mutex_lock(&efx->mac_lock);
d3245b28 959 rc = __efx_reconfigure_port(efx);
8ceee660 960 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 961
962 return rc;
8ceee660
BH		 963}
964
8be4f3e6
BH		 965/* Asynchronous work item for changing MAC promiscuity and multicast
966 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
967 * MAC directly. */
766ca0fa
BH		 968static void efx_mac_work(struct work_struct *data)
969{
970 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
971
972 mutex_lock(&efx->mac_lock);
30b81cda 973 if (efx->port_enabled)
710b208d 974 efx->type->reconfigure_mac(efx);
766ca0fa
BH		 975 mutex_unlock(&efx->mac_lock);
976}
977
8ceee660
BH		 978static int efx_probe_port(struct efx_nic *efx)
979{
980 int rc;
981
62776d03 982 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 983
ff3b00a0
SH		 984 if (phy_flash_cfg)
985 efx->phy_mode = PHY_MODE_SPECIAL;
986
ef2b90ee
BH		 987 /* Connect up MAC/PHY operations table */
988 rc = efx->type->probe_port(efx);
8ceee660 989 if (rc)
e42de262 990 return rc;
8ceee660 991
e332bcb3
BH		 992 /* Initialise MAC address to permanent address */
993 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN);
8ceee660
BH		 994
995 return 0;
8ceee660
BH		 996}
997
998static int efx_init_port(struct efx_nic *efx)
999{
1000 int rc;
1001
62776d03 1002 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 1003
1dfc5cea
BH		 1004 mutex_lock(&efx->mac_lock);
1005
177dfcd8 1006 rc = efx->phy_op->init(efx);
8ceee660 1007 if (rc)
1dfc5cea 1008 goto fail1;
8ceee660 1009
dc8cfa55 1010 efx->port_initialized = true;
1dfc5cea 1011
d3245b28
BH		 1012 /* Reconfigure the MAC before creating dma queues (required for
1013 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
710b208d 1014 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1015
1016 /* Ensure the PHY advertises the correct flow control settings */
1017 rc = efx->phy_op->reconfigure(efx);
1018 if (rc)
1019 goto fail2;
1020
1dfc5cea 1021 mutex_unlock(&efx->mac_lock);
8ceee660 1022 return 0;
177dfcd8 1023
1dfc5cea 1024fail2:
177dfcd8 1025 efx->phy_op->fini(efx);
1dfc5cea
BH		 1026fail1:
1027 mutex_unlock(&efx->mac_lock);
177dfcd8 1028 return rc;
8ceee660
BH		 1029}
1030
8ceee660
BH		 1031static void efx_start_port(struct efx_nic *efx)
1032{
62776d03 1033 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH		 1034 BUG_ON(efx->port_enabled);
1035
1036 mutex_lock(&efx->mac_lock);
dc8cfa55 1037 efx->port_enabled = true;
8be4f3e6
BH		 1038
1039 /* efx_mac_work() might have been scheduled after efx_stop_port(),
1040 * and then cancelled by efx_flush_all() */
710b208d 1041 efx->type->reconfigure_mac(efx);
8be4f3e6 1042
8ceee660
BH		 1043 mutex_unlock(&efx->mac_lock);
1044}
1045
fdaa9aed 1046/* Prevent efx_mac_work() and efx_monitor() from working */
8ceee660
BH		 1047static void efx_stop_port(struct efx_nic *efx)
1048{
62776d03 1049 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660
BH		 1050
1051 mutex_lock(&efx->mac_lock);
dc8cfa55 1052 efx->port_enabled = false;
8ceee660
BH		 1053 mutex_unlock(&efx->mac_lock);
1054
1055 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH		 1056 netif_addr_lock_bh(efx->net_dev);
1057 netif_addr_unlock_bh(efx->net_dev);
8ceee660
BH		 1058}
1059
1060static void efx_fini_port(struct efx_nic *efx)
1061{
62776d03 1062 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH		 1063
1064 if (!efx->port_initialized)
1065 return;
1066
177dfcd8 1067 efx->phy_op->fini(efx);
dc8cfa55 1068 efx->port_initialized = false;
8ceee660 1069
eb50c0d6 1070 efx->link_state.up = false;
8ceee660
BH		 1071 efx_link_status_changed(efx);
1072}
1073
1074static void efx_remove_port(struct efx_nic *efx)
1075{
62776d03 1076 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1077
ef2b90ee 1078 efx->type->remove_port(efx);
8ceee660
BH		 1079}
1080
1081/**************************************************************************
1082 *
1083 * NIC handling
1084 *
1085 **************************************************************************/
1086
1087/* This configures the PCI device to enable I/O and DMA. */
1088static int efx_init_io(struct efx_nic *efx)
1089{
1090 struct pci_dev *pci_dev = efx->pci_dev;
1091 dma_addr_t dma_mask = efx->type->max_dma_mask;
b105798f 1092 unsigned int mem_map_size = efx->type->mem_map_size(efx);
8ceee660
BH		 1093 int rc;
1094
62776d03 1095 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660
BH		 1096
1097 rc = pci_enable_device(pci_dev);
1098 if (rc) {
62776d03
BH		 1099 netif_err(efx, probe, efx->net_dev,
1100 "failed to enable PCI device\n");
8ceee660
BH		 1101 goto fail1;
1102 }
1103
1104 pci_set_master(pci_dev);
1105
1106 /* Set the PCI DMA mask. Try all possibilities from our
1107 * genuine mask down to 32 bits, because some architectures
1108 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1109 * masks event though they reject 46 bit masks.
1110 */
1111 while (dma_mask > 0x7fffffffUL) {
0e33d870
BH		 1112 if (dma_supported(&pci_dev->dev, dma_mask)) {
1113 rc = dma_set_mask(&pci_dev->dev, dma_mask);
e9e01846
BH		 1114 if (rc == 0)
1115 break;
1116 }
8ceee660
BH		 1117 dma_mask >>= 1;
1118 }
1119 if (rc) {
62776d03
BH		 1120 netif_err(efx, probe, efx->net_dev,
1121 "could not find a suitable DMA mask\n");
8ceee660
BH		 1122 goto fail2;
1123 }
62776d03
BH		 1124 netif_dbg(efx, probe, efx->net_dev,
1125 "using DMA mask %llx\n", (unsigned long long) dma_mask);
0e33d870 1126 rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask);
8ceee660 1127 if (rc) {
0e33d870
BH		 1128 /* dma_set_coherent_mask() is not *allowed* to
1129 * fail with a mask that dma_set_mask() accepted,
8ceee660
BH		 1130 * but just in case...
1131 */
62776d03
BH		 1132 netif_err(efx, probe, efx->net_dev,
1133 "failed to set consistent DMA mask\n");
8ceee660
BH		 1134 goto fail2;
1135 }
1136
dc803df8
BH		 1137 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1138 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
8ceee660 1139 if (rc) {
62776d03
BH		 1140 netif_err(efx, probe, efx->net_dev,
1141 "request for memory BAR failed\n");
8ceee660
BH		 1142 rc = -EIO;
1143 goto fail3;
1144 }
b105798f 1145 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
8ceee660 1146 if (!efx->membase) {
62776d03
BH		 1147 netif_err(efx, probe, efx->net_dev,
1148 "could not map memory BAR at %llx+%x\n",
b105798f 1149 (unsigned long long)efx->membase_phys, mem_map_size);
8ceee660
BH		 1150 rc = -ENOMEM;
1151 goto fail4;
1152 }
62776d03
BH		 1153 netif_dbg(efx, probe, efx->net_dev,
1154 "memory BAR at %llx+%x (virtual %p)\n",
b105798f
BH		 1155 (unsigned long long)efx->membase_phys, mem_map_size,
1156 efx->membase);
8ceee660
BH		 1157
1158 return 0;
1159
1160 fail4:
dc803df8 1161 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
8ceee660 1162 fail3:
2c118e0f 1163 efx->membase_phys = 0;
8ceee660
BH		 1164 fail2:
1165 pci_disable_device(efx->pci_dev);
1166 fail1:
1167 return rc;
1168}
1169
1170static void efx_fini_io(struct efx_nic *efx)
1171{
62776d03 1172 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH		 1173
1174 if (efx->membase) {
1175 iounmap(efx->membase);
1176 efx->membase = NULL;
1177 }
1178
1179 if (efx->membase_phys) {
dc803df8 1180 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
2c118e0f 1181 efx->membase_phys = 0;
8ceee660
BH		 1182 }
1183
1184 pci_disable_device(efx->pci_dev);
1185}
1186
a9a52506 1187static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1188{
cdb08f8f 1189 cpumask_var_t thread_mask;
a16e5b24 1190 unsigned int count;
46123d04 1191 int cpu;
5b874e25 1192
cd2d5b52
BH		 1193 if (rss_cpus) {
1194 count = rss_cpus;
1195 } else {
1196 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1197 netif_warn(efx, probe, efx->net_dev,
1198 "RSS disabled due to allocation failure\n");
1199 return 1;
1200 }
46123d04 1201
cd2d5b52
BH		 1202 count = 0;
1203 for_each_online_cpu(cpu) {
1204 if (!cpumask_test_cpu(cpu, thread_mask)) {
1205 ++count;
1206 cpumask_or(thread_mask, thread_mask,
1207 topology_thread_cpumask(cpu));
1208 }
1209 }
1210
1211 free_cpumask_var(thread_mask);
2f8975fb
RR		 1212 }
1213
cd2d5b52
BH		 1214 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1215 * table entries that are inaccessible to VFs
1216 */
1217 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1218 count > efx_vf_size(efx)) {
1219 netif_warn(efx, probe, efx->net_dev,
1220 "Reducing number of RSS channels from %u to %u for "
1221 "VF support. Increase vf-msix-limit to use more "
1222 "channels on the PF.\n",
1223 count, efx_vf_size(efx));
1224 count = efx_vf_size(efx);
46123d04
BH		 1225 }
1226
1227 return count;
1228}
1229
1230/* Probe the number and type of interrupts we are able to obtain, and
1231 * the resulting numbers of channels and RX queues.
1232 */
64d8ad6d 1233static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1234{
7f967c01
BH		 1235 unsigned int extra_channels = 0;
1236 unsigned int i, j;
a16e5b24 1237 int rc;
8ceee660 1238
7f967c01
BH		 1239 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1240 if (efx->extra_channel_type[i])
1241 ++extra_channels;
1242
8ceee660 1243 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1244 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1245 unsigned int n_channels;
aa6ef27e 1246
a9a52506 1247 n_channels = efx_wanted_parallelism(efx);
a4900ac9
BH		 1248 if (separate_tx_channels)
1249 n_channels *= 2;
7f967c01 1250 n_channels += extra_channels;
b105798f 1251 n_channels = min(n_channels, efx->max_channels);
8ceee660 1252
a4900ac9 1253 for (i = 0; i < n_channels; i++)
8ceee660 1254 xentries[i].entry = i;
a4900ac9 1255 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
8ceee660 1256 if (rc > 0) {
62776d03
BH		 1257 netif_err(efx, drv, efx->net_dev,
1258 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1259 " available (%d < %u).\n", rc, n_channels);
62776d03
BH		 1260 netif_err(efx, drv, efx->net_dev,
1261 "WARNING: Performance may be reduced.\n");
a4900ac9
BH		 1262 EFX_BUG_ON_PARANOID(rc >= n_channels);
1263 n_channels = rc;
8ceee660 1264 rc = pci_enable_msix(efx->pci_dev, xentries,
a4900ac9 1265 n_channels);
8ceee660
BH		 1266 }
1267
1268 if (rc == 0) {
a4900ac9 1269 efx->n_channels = n_channels;
7f967c01
BH		 1270 if (n_channels > extra_channels)
1271 n_channels -= extra_channels;
a4900ac9 1272 if (separate_tx_channels) {
7f967c01
BH		 1273 efx->n_tx_channels = max(n_channels / 2, 1U);
1274 efx->n_rx_channels = max(n_channels -
1275 efx->n_tx_channels,
1276 1U);
a4900ac9 1277 } else {
7f967c01
BH		 1278 efx->n_tx_channels = n_channels;
1279 efx->n_rx_channels = n_channels;
a4900ac9 1280 }
7f967c01 1281 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH		 1282 efx_get_channel(efx, i)->irq =
1283 xentries[i].vector;
8ceee660
BH		 1284 } else {
1285 /* Fall back to single channel MSI */
1286 efx->interrupt_mode = EFX_INT_MODE_MSI;
62776d03
BH		 1287 netif_err(efx, drv, efx->net_dev,
1288 "could not enable MSI-X\n");
8ceee660
BH		 1289 }
1290 }
1291
1292 /* Try single interrupt MSI */
1293 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1294 efx->n_channels = 1;
a4900ac9
BH		 1295 efx->n_rx_channels = 1;
1296 efx->n_tx_channels = 1;
8ceee660
BH		 1297 rc = pci_enable_msi(efx->pci_dev);
1298 if (rc == 0) {
f7d12cdc 1299 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1300 } else {
62776d03
BH		 1301 netif_err(efx, drv, efx->net_dev,
1302 "could not enable MSI\n");
8ceee660
BH		 1303 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1304 }
1305 }
1306
1307 /* Assume legacy interrupts */
1308 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
28b581ab 1309 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
a4900ac9
BH		 1310 efx->n_rx_channels = 1;
1311 efx->n_tx_channels = 1;
8ceee660
BH		 1312 efx->legacy_irq = efx->pci_dev->irq;
1313 }
64d8ad6d 1314
7f967c01
BH		 1315 /* Assign extra channels if possible */
1316 j = efx->n_channels;
1317 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1318 if (!efx->extra_channel_type[i])
1319 continue;
1320 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1321 efx->n_channels <= extra_channels) {
1322 efx->extra_channel_type[i]->handle_no_channel(efx);
1323 } else {
1324 --j;
1325 efx_get_channel(efx, j)->type =
1326 efx->extra_channel_type[i];
1327 }
1328 }
1329
cd2d5b52 1330 /* RSS might be usable on VFs even if it is disabled on the PF */
3132d282 1331 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ?
cd2d5b52
BH		 1332 efx->n_rx_channels : efx_vf_size(efx));
1333
64d8ad6d 1334 return 0;
8ceee660
BH		 1335}
1336
d8291187 1337static void efx_soft_enable_interrupts(struct efx_nic *efx)
9f2cb71c
BH		 1338{
1339 struct efx_channel *channel;
1340
8b7325b4
BH		 1341 BUG_ON(efx->state == STATE_DISABLED);
1342
d8291187
BH		 1343 efx->irq_soft_enabled = true;
1344 smp_wmb();
9f2cb71c
BH		 1345
1346 efx_for_each_channel(channel, efx) {
d8291187 1347 if (!channel->type->keep_eventq)
7f967c01 1348 efx_init_eventq(channel);
9f2cb71c
BH		 1349 efx_start_eventq(channel);
1350 }
1351
1352 efx_mcdi_mode_event(efx);
1353}
1354
d8291187 1355static void efx_soft_disable_interrupts(struct efx_nic *efx)
9f2cb71c
BH		 1356{
1357 struct efx_channel *channel;
1358
8b7325b4
BH		 1359 if (efx->state == STATE_DISABLED)
1360 return;
1361
9f2cb71c
BH		 1362 efx_mcdi_mode_poll(efx);
1363
d8291187
BH		 1364 efx->irq_soft_enabled = false;
1365 smp_wmb();
1366
1367 if (efx->legacy_irq)
9f2cb71c 1368 synchronize_irq(efx->legacy_irq);
9f2cb71c
BH		 1369
1370 efx_for_each_channel(channel, efx) {
1371 if (channel->irq)
1372 synchronize_irq(channel->irq);
1373
1374 efx_stop_eventq(channel);
d8291187 1375 if (!channel->type->keep_eventq)
7f967c01 1376 efx_fini_eventq(channel);
9f2cb71c
BH		 1377 }
1378}
1379
d8291187
BH		 1380static void efx_enable_interrupts(struct efx_nic *efx)
1381{
1382 struct efx_channel *channel;
1383
1384 BUG_ON(efx->state == STATE_DISABLED);
1385
1386 if (efx->eeh_disabled_legacy_irq) {
1387 enable_irq(efx->legacy_irq);
1388 efx->eeh_disabled_legacy_irq = false;
1389 }
1390
86094f7f 1391 efx->type->irq_enable_master(efx);
d8291187
BH		 1392
1393 efx_for_each_channel(channel, efx) {
1394 if (channel->type->keep_eventq)
1395 efx_init_eventq(channel);
1396 }
1397
1398 efx_soft_enable_interrupts(efx);
1399}
1400
1401static void efx_disable_interrupts(struct efx_nic *efx)
1402{
1403 struct efx_channel *channel;
1404
1405 efx_soft_disable_interrupts(efx);
1406
1407 efx_for_each_channel(channel, efx) {
1408 if (channel->type->keep_eventq)
1409 efx_fini_eventq(channel);
1410 }
1411
86094f7f 1412 efx->type->irq_disable_non_ev(efx);
d8291187
BH		 1413}
1414
8ceee660
BH		 1415static void efx_remove_interrupts(struct efx_nic *efx)
1416{
1417 struct efx_channel *channel;
1418
1419 /* Remove MSI/MSI-X interrupts */
64ee3120 1420 efx_for_each_channel(channel, efx)
8ceee660
BH		 1421 channel->irq = 0;
1422 pci_disable_msi(efx->pci_dev);
1423 pci_disable_msix(efx->pci_dev);
1424
1425 /* Remove legacy interrupt */
1426 efx->legacy_irq = 0;
1427}
1428
8831da7b 1429static void efx_set_channels(struct efx_nic *efx)
8ceee660 1430{
602a5322
BH		 1431 struct efx_channel *channel;
1432 struct efx_tx_queue *tx_queue;
1433
97653431 1434 efx->tx_channel_offset =
a4900ac9 1435 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
602a5322 1436
79d68b37
SH		 1437 /* We need to mark which channels really have RX and TX
1438 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH		 1439 * RX-only and TX-only channels.
1440 */
1441 efx_for_each_channel(channel, efx) {
79d68b37
SH		 1442 if (channel->channel < efx->n_rx_channels)
1443 channel->rx_queue.core_index = channel->channel;
1444 else
1445 channel->rx_queue.core_index = -1;
1446
602a5322
BH		 1447 efx_for_each_channel_tx_queue(tx_queue, channel)
1448 tx_queue->queue -= (efx->tx_channel_offset *
1449 EFX_TXQ_TYPES);
1450 }
8ceee660
BH		 1451}
1452
1453static int efx_probe_nic(struct efx_nic *efx)
1454{
765c9f46 1455 size_t i;
8ceee660
BH		 1456 int rc;
1457
62776d03 1458 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH		 1459
1460 /* Carry out hardware-type specific initialisation */
ef2b90ee 1461 rc = efx->type->probe(efx);
8ceee660
BH		 1462 if (rc)
1463 return rc;
1464
a4900ac9 1465 /* Determine the number of channels and queues by trying to hook
8ceee660 1466 * in MSI-X interrupts. */
64d8ad6d
BH		 1467 rc = efx_probe_interrupts(efx);
1468 if (rc)
1469 goto fail;
8ceee660 1470
28e47c49
BH		 1471 efx->type->dimension_resources(efx);
1472
5d3a6fca
BH		 1473 if (efx->n_channels > 1)
1474 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
765c9f46 1475 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
278bc429 1476 efx->rx_indir_table[i] =
cd2d5b52 1477 ethtool_rxfh_indir_default(i, efx->rss_spread);
5d3a6fca 1478
8831da7b 1479 efx_set_channels(efx);
c4f4adc7
BH		 1480 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1481 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH		 1482
1483 /* Initialise the interrupt moderation settings */
9e393b30
BH		 1484 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1485 true);
8ceee660
BH		 1486
1487 return 0;
64d8ad6d
BH		 1488
1489fail:
1490 efx->type->remove(efx);
1491 return rc;
8ceee660
BH		 1492}
1493
1494static void efx_remove_nic(struct efx_nic *efx)
1495{
62776d03 1496 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH		 1497
1498 efx_remove_interrupts(efx);
ef2b90ee 1499 efx->type->remove(efx);
8ceee660
BH		 1500}
1501
1502/**************************************************************************
1503 *
1504 * NIC startup/shutdown
1505 *
1506 *************************************************************************/
1507
1508static int efx_probe_all(struct efx_nic *efx)
1509{
8ceee660
BH		 1510 int rc;
1511
8ceee660
BH		 1512 rc = efx_probe_nic(efx);
1513 if (rc) {
62776d03 1514 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH		 1515 goto fail1;
1516 }
1517
8ceee660
BH		 1518 rc = efx_probe_port(efx);
1519 if (rc) {
62776d03 1520 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH		 1521 goto fail2;
1522 }
1523
7e6d06f0
BH		 1524 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1525 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1526 rc = -EINVAL;
1527 goto fail3;
1528 }
ecc910f5 1529 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1530
64eebcfd
BH		 1531 rc = efx_probe_filters(efx);
1532 if (rc) {
1533 netif_err(efx, probe, efx->net_dev,
1534 "failed to create filter tables\n");
7f967c01 1535 goto fail3;
64eebcfd
BH		 1536 }
1537
7f967c01
BH		 1538 rc = efx_probe_channels(efx);
1539 if (rc)
1540 goto fail4;
1541
8ceee660
BH		 1542 return 0;
1543
64eebcfd 1544 fail4:
7f967c01 1545 efx_remove_filters(efx);
8ceee660 1546 fail3:
8ceee660
BH		 1547 efx_remove_port(efx);
1548 fail2:
1549 efx_remove_nic(efx);
1550 fail1:
1551 return rc;
1552}
1553
8b7325b4
BH		 1554/* If the interface is supposed to be running but is not, start
1555 * the hardware and software data path, regular activity for the port
1556 * (MAC statistics, link polling, etc.) and schedule the port to be
1557 * reconfigured. Interrupts must already be enabled. This function
1558 * is safe to call multiple times, so long as the NIC is not disabled.
1559 * Requires the RTNL lock.
9f2cb71c 1560 */
8ceee660
BH		 1561static void efx_start_all(struct efx_nic *efx)
1562{
8ceee660 1563 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1564 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH		 1565
1566 /* Check that it is appropriate to restart the interface. All
1567 * of these flags are safe to read under just the rtnl lock */
8b7325b4 1568 if (efx->port_enabled || !netif_running(efx->net_dev))
8ceee660
BH		 1569 return;
1570
8ceee660 1571 efx_start_port(efx);
9f2cb71c 1572 efx_start_datapath(efx);
8880f4ec 1573
626950db
AR		 1574 /* Start the hardware monitor if there is one */
1575 if (efx->type->monitor != NULL)
8ceee660
BH		 1576 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1577 efx_monitor_interval);
626950db
AR		 1578
1579 /* If link state detection is normally event-driven, we have
1580 * to poll now because we could have missed a change
1581 */
1582 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
78c1f0a0
SH		 1583 mutex_lock(&efx->mac_lock);
1584 if (efx->phy_op->poll(efx))
1585 efx_link_status_changed(efx);
1586 mutex_unlock(&efx->mac_lock);
1587 }
55edc6e6 1588
ef2b90ee 1589 efx->type->start_stats(efx);
8ceee660
BH		 1590}
1591
1592/* Flush all delayed work. Should only be called when no more delayed work
1593 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1594 * since we're holding the rtnl_lock at this point. */
1595static void efx_flush_all(struct efx_nic *efx)
1596{
dd40781e 1597 /* Make sure the hardware monitor and event self-test are stopped */
8ceee660 1598 cancel_delayed_work_sync(&efx->monitor_work);
dd40781e 1599 efx_selftest_async_cancel(efx);
8ceee660 1600 /* Stop scheduled port reconfigurations */
766ca0fa 1601 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1602}
1603
8b7325b4
BH		 1604/* Quiesce the hardware and software data path, and regular activity
1605 * for the port without bringing the link down. Safe to call multiple
1606 * times with the NIC in almost any state, but interrupts should be
1607 * enabled. Requires the RTNL lock.
1608 */
8ceee660
BH		 1609static void efx_stop_all(struct efx_nic *efx)
1610{
8ceee660
BH		 1611 EFX_ASSERT_RESET_SERIALISED(efx);
1612
1613 /* port_enabled can be read safely under the rtnl lock */
1614 if (!efx->port_enabled)
1615 return;
1616
ef2b90ee 1617 efx->type->stop_stats(efx);
8ceee660
BH		 1618 efx_stop_port(efx);
1619
fdaa9aed 1620 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
8ceee660
BH		 1621 efx_flush_all(efx);
1622
29c69a48
BH		 1623 /* Stop the kernel transmit interface. This is only valid if
1624 * the device is stopped or detached; otherwise the watchdog
1625 * may fire immediately.
1626 */
1627 WARN_ON(netif_running(efx->net_dev) &&
1628 netif_device_present(efx->net_dev));
9f2cb71c
BH		 1629 netif_tx_disable(efx->net_dev);
1630
1631 efx_stop_datapath(efx);
8ceee660
BH		 1632}
1633
1634static void efx_remove_all(struct efx_nic *efx)
1635{
4642610c 1636 efx_remove_channels(efx);
7f967c01 1637 efx_remove_filters(efx);
8ceee660
BH		 1638 efx_remove_port(efx);
1639 efx_remove_nic(efx);
1640}
1641
8ceee660
BH		 1642/**************************************************************************
1643 *
1644 * Interrupt moderation
1645 *
1646 **************************************************************************/
1647
cc180b69 1648static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
0d86ebd8 1649{
b548f976
BH		 1650 if (usecs == 0)
1651 return 0;
cc180b69 1652 if (usecs * 1000 < quantum_ns)
0d86ebd8 1653 return 1; /* never round down to 0 */
cc180b69 1654 return usecs * 1000 / quantum_ns;
0d86ebd8
BH		 1655}
1656
8ceee660 1657/* Set interrupt moderation parameters */
9e393b30
BH		 1658int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1659 unsigned int rx_usecs, bool rx_adaptive,
1660 bool rx_may_override_tx)
8ceee660 1661{
f7d12cdc 1662 struct efx_channel *channel;
cc180b69
BH		 1663 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1664 efx->timer_quantum_ns,
1665 1000);
1666 unsigned int tx_ticks;
1667 unsigned int rx_ticks;
8ceee660
BH		 1668
1669 EFX_ASSERT_RESET_SERIALISED(efx);
1670
cc180b69 1671 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
9e393b30
BH		 1672 return -EINVAL;
1673
cc180b69
BH		 1674 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1675 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1676
9e393b30
BH		 1677 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1678 !rx_may_override_tx) {
1679 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1680 "RX and TX IRQ moderation must be equal\n");
1681 return -EINVAL;
1682 }
1683
6fb70fd1 1684 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1685 efx->irq_rx_moderation = rx_ticks;
f7d12cdc 1686 efx_for_each_channel(channel, efx) {
525da907 1687 if (efx_channel_has_rx_queue(channel))
f7d12cdc 1688 channel->irq_moderation = rx_ticks;
525da907 1689 else if (efx_channel_has_tx_queues(channel))
f7d12cdc
BH		 1690 channel->irq_moderation = tx_ticks;
1691 }
9e393b30
BH		 1692
1693 return 0;
8ceee660
BH		 1694}
1695
a0c4faf5
BH		 1696void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
1697 unsigned int *rx_usecs, bool *rx_adaptive)
1698{
cc180b69
BH		 1699 /* We must round up when converting ticks to microseconds
1700 * because we round down when converting the other way.
1701 */
1702
a0c4faf5 1703 *rx_adaptive = efx->irq_rx_adaptive;
cc180b69
BH		 1704 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
1705 efx->timer_quantum_ns,
1706 1000);
a0c4faf5
BH		 1707
1708 /* If channels are shared between RX and TX, so is IRQ
1709 * moderation. Otherwise, IRQ moderation is the same for all
1710 * TX channels and is not adaptive.
1711 */
1712 if (efx->tx_channel_offset == 0)
1713 *tx_usecs = *rx_usecs;
1714 else
cc180b69 1715 *tx_usecs = DIV_ROUND_UP(
a0c4faf5 1716 efx->channel[efx->tx_channel_offset]->irq_moderation *
cc180b69
BH		 1717 efx->timer_quantum_ns,
1718 1000);
a0c4faf5
BH		 1719}
1720
8ceee660
BH		 1721/**************************************************************************
1722 *
1723 * Hardware monitor
1724 *
1725 **************************************************************************/
1726
e254c274 1727/* Run periodically off the general workqueue */
8ceee660
BH		 1728static void efx_monitor(struct work_struct *data)
1729{
1730 struct efx_nic *efx = container_of(data, struct efx_nic,
1731 monitor_work.work);
8ceee660 1732
62776d03
BH		 1733 netif_vdbg(efx, timer, efx->net_dev,
1734 "hardware monitor executing on CPU %d\n",
1735 raw_smp_processor_id());
ef2b90ee 1736 BUG_ON(efx->type->monitor == NULL);
8ceee660 1737
8ceee660
BH		 1738 /* If the mac_lock is already held then it is likely a port
1739 * reconfiguration is already in place, which will likely do
e254c274
BH		 1740 * most of the work of monitor() anyway. */
1741 if (mutex_trylock(&efx->mac_lock)) {
1742 if (efx->port_enabled)
1743 efx->type->monitor(efx);
1744 mutex_unlock(&efx->mac_lock);
1745 }
8ceee660 1746
8ceee660
BH		 1747 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1748 efx_monitor_interval);
1749}
1750
1751/**************************************************************************
1752 *
1753 * ioctls
1754 *
1755 *************************************************************************/
1756
1757/* Net device ioctl
1758 * Context: process, rtnl_lock() held.
1759 */
1760static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1761{
767e468c 1762 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 1763 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 1764
7c236c43
SH		 1765 if (cmd == SIOCSHWTSTAMP)
1766 return efx_ptp_ioctl(efx, ifr, cmd);
1767
68e7f45e
BH		 1768 /* Convert phy_id from older PRTAD/DEVAD format */
1769 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1770 (data->phy_id & 0xfc00) == 0x0400)
1771 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1772
1773 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 1774}
1775
1776/**************************************************************************
1777 *
1778 * NAPI interface
1779 *
1780 **************************************************************************/
1781
7f967c01
BH		 1782static void efx_init_napi_channel(struct efx_channel *channel)
1783{
1784 struct efx_nic *efx = channel->efx;
1785
1786 channel->napi_dev = efx->net_dev;
1787 netif_napi_add(channel->napi_dev, &channel->napi_str,
1788 efx_poll, napi_weight);
1789}
1790
e8f14992 1791static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH		 1792{
1793 struct efx_channel *channel;
8ceee660 1794
7f967c01
BH		 1795 efx_for_each_channel(channel, efx)
1796 efx_init_napi_channel(channel);
e8f14992
BH		 1797}
1798
1799static void efx_fini_napi_channel(struct efx_channel *channel)
1800{
1801 if (channel->napi_dev)
1802 netif_napi_del(&channel->napi_str);
1803 channel->napi_dev = NULL;
8ceee660
BH		 1804}
1805
1806static void efx_fini_napi(struct efx_nic *efx)
1807{
1808 struct efx_channel *channel;
1809
e8f14992
BH		 1810 efx_for_each_channel(channel, efx)
1811 efx_fini_napi_channel(channel);
8ceee660
BH		 1812}
1813
1814/**************************************************************************
1815 *
1816 * Kernel netpoll interface
1817 *
1818 *************************************************************************/
1819
1820#ifdef CONFIG_NET_POLL_CONTROLLER
1821
1822/* Although in the common case interrupts will be disabled, this is not
1823 * guaranteed. However, all our work happens inside the NAPI callback,
1824 * so no locking is required.
1825 */
1826static void efx_netpoll(struct net_device *net_dev)
1827{
767e468c 1828 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1829 struct efx_channel *channel;
1830
64ee3120 1831 efx_for_each_channel(channel, efx)
8ceee660
BH		 1832 efx_schedule_channel(channel);
1833}
1834
1835#endif
1836
1837/**************************************************************************
1838 *
1839 * Kernel net device interface
1840 *
1841 *************************************************************************/
1842
1843/* Context: process, rtnl_lock() held. */
1844static int efx_net_open(struct net_device *net_dev)
1845{
767e468c 1846 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH		 1847 int rc;
1848
62776d03
BH		 1849 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1850 raw_smp_processor_id());
8ceee660 1851
8b7325b4
BH		 1852 rc = efx_check_disabled(efx);
1853 if (rc)
1854 return rc;
f8b87c17
BH		 1855 if (efx->phy_mode & PHY_MODE_SPECIAL)
1856 return -EBUSY;
8880f4ec
BH		 1857 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1858 return -EIO;
f8b87c17 1859
78c1f0a0
SH		 1860 /* Notify the kernel of the link state polled during driver load,
1861 * before the monitor starts running */
1862 efx_link_status_changed(efx);
1863
8ceee660 1864 efx_start_all(efx);
dd40781e 1865 efx_selftest_async_start(efx);
8ceee660
BH		 1866 return 0;
1867}
1868
1869/* Context: process, rtnl_lock() held.
1870 * Note that the kernel will ignore our return code; this method
1871 * should really be a void.
1872 */
1873static int efx_net_stop(struct net_device *net_dev)
1874{
767e468c 1875 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1876
62776d03
BH		 1877 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1878 raw_smp_processor_id());
8ceee660 1879
8b7325b4
BH		 1880 /* Stop the device and flush all the channels */
1881 efx_stop_all(efx);
8ceee660
BH		 1882
1883 return 0;
1884}
1885
5b9e207c 1886/* Context: process, dev_base_lock or RTNL held, non-blocking. */
2aa9ef11
BH		 1887static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
1888 struct rtnl_link_stats64 *stats)
8ceee660 1889{
767e468c 1890 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1891 struct efx_mac_stats *mac_stats = &efx->mac_stats;
8ceee660 1892
55edc6e6 1893 spin_lock_bh(&efx->stats_lock);
1cb34522 1894
ef2b90ee 1895 efx->type->update_stats(efx);
8ceee660
BH		 1896
1897 stats->rx_packets = mac_stats->rx_packets;
1898 stats->tx_packets = mac_stats->tx_packets;
1899 stats->rx_bytes = mac_stats->rx_bytes;
1900 stats->tx_bytes = mac_stats->tx_bytes;
80485d34 1901 stats->rx_dropped = efx->n_rx_nodesc_drop_cnt;
8ceee660
BH		 1902 stats->multicast = mac_stats->rx_multicast;
1903 stats->collisions = mac_stats->tx_collision;
1904 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1905 mac_stats->rx_length_error);
8ceee660
BH		 1906 stats->rx_crc_errors = mac_stats->rx_bad;
1907 stats->rx_frame_errors = mac_stats->rx_align_error;
1908 stats->rx_fifo_errors = mac_stats->rx_overflow;
1909 stats->rx_missed_errors = mac_stats->rx_missed;
1910 stats->tx_window_errors = mac_stats->tx_late_collision;
1911
1912 stats->rx_errors = (stats->rx_length_errors +
8ceee660
BH		 1913 stats->rx_crc_errors +
1914 stats->rx_frame_errors +
8ceee660
BH		 1915 mac_stats->rx_symbol_error);
1916 stats->tx_errors = (stats->tx_window_errors +
1917 mac_stats->tx_bad);
1918
1cb34522
BH		 1919 spin_unlock_bh(&efx->stats_lock);
1920
8ceee660
BH		 1921 return stats;
1922}
1923
1924/* Context: netif_tx_lock held, BHs disabled. */
1925static void efx_watchdog(struct net_device *net_dev)
1926{
767e468c 1927 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1928
62776d03
BH		 1929 netif_err(efx, tx_err, efx->net_dev,
1930 "TX stuck with port_enabled=%d: resetting channels\n",
1931 efx->port_enabled);
8ceee660 1932
739bb23d 1933 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 1934}
1935
1936
1937/* Context: process, rtnl_lock() held. */
1938static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1939{
767e468c 1940 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 1941 int rc;
8ceee660 1942
8b7325b4
BH		 1943 rc = efx_check_disabled(efx);
1944 if (rc)
1945 return rc;
8ceee660
BH		 1946 if (new_mtu > EFX_MAX_MTU)
1947 return -EINVAL;
1948
62776d03 1949 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 1950
29c69a48
BH		 1951 efx_device_detach_sync(efx);
1952 efx_stop_all(efx);
1953
d3245b28 1954 mutex_lock(&efx->mac_lock);
8ceee660 1955 net_dev->mtu = new_mtu;
710b208d 1956 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1957 mutex_unlock(&efx->mac_lock);
1958
8ceee660 1959 efx_start_all(efx);
29c69a48 1960 netif_device_attach(efx->net_dev);
6c8eef4a 1961 return 0;
8ceee660
BH		 1962}
1963
1964static int efx_set_mac_address(struct net_device *net_dev, void *data)
1965{
767e468c 1966 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1967 struct sockaddr *addr = data;
1968 char *new_addr = addr->sa_data;
1969
8ceee660 1970 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH		 1971 netif_err(efx, drv, efx->net_dev,
1972 "invalid ethernet MAC address requested: %pM\n",
1973 new_addr);
504f9b5a 1974 return -EADDRNOTAVAIL;
8ceee660
BH		 1975 }
1976
1977 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
cd2d5b52 1978 efx_sriov_mac_address_changed(efx);
8ceee660
BH		 1979
1980 /* Reconfigure the MAC */
d3245b28 1981 mutex_lock(&efx->mac_lock);
710b208d 1982 efx->type->reconfigure_mac(efx);
d3245b28 1983 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 1984
1985 return 0;
1986}
1987
a816f75a 1988/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 1989static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 1990{
767e468c 1991 struct efx_nic *efx = netdev_priv(net_dev);
22bedad3 1992 struct netdev_hw_addr *ha;
8ceee660 1993 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
8ceee660
BH		 1994 u32 crc;
1995 int bit;
8ceee660 1996
8be4f3e6 1997 efx->promiscuous = !!(net_dev->flags & IFF_PROMISC);
8ceee660
BH		 1998
1999 /* Build multicast hash table */
8be4f3e6 2000 if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
8ceee660
BH		 2001 memset(mc_hash, 0xff, sizeof(*mc_hash));
2002 } else {
2003 memset(mc_hash, 0x00, sizeof(*mc_hash));
22bedad3
JP		 2004 netdev_for_each_mc_addr(ha, net_dev) {
2005 crc = ether_crc_le(ETH_ALEN, ha->addr);
8ceee660 2006 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
32766ec8 2007 __set_bit_le(bit, mc_hash);
8ceee660 2008 }
8ceee660 2009
8be4f3e6
BH		 2010 /* Broadcast packets go through the multicast hash filter.
2011 * ether_crc_le() of the broadcast address is 0xbe2612ff
2012 * so we always add bit 0xff to the mask.
2013 */
32766ec8 2014 __set_bit_le(0xff, mc_hash);
8be4f3e6 2015 }
a816f75a 2016
8be4f3e6
BH		 2017 if (efx->port_enabled)
2018 queue_work(efx->workqueue, &efx->mac_work);
2019 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 2020}
2021
c8f44aff 2022static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH		 2023{
2024 struct efx_nic *efx = netdev_priv(net_dev);
2025
2026 /* If disabling RX n-tuple filtering, clear existing filters */
2027 if (net_dev->features & ~data & NETIF_F_NTUPLE)
2028 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2029
2030 return 0;
2031}
2032
c3ecb9f3
SH		 2033static const struct net_device_ops efx_netdev_ops = {
2034 .ndo_open = efx_net_open,
2035 .ndo_stop = efx_net_stop,
4472702e 2036 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH		 2037 .ndo_tx_timeout = efx_watchdog,
2038 .ndo_start_xmit = efx_hard_start_xmit,
2039 .ndo_validate_addr = eth_validate_addr,
2040 .ndo_do_ioctl = efx_ioctl,
2041 .ndo_change_mtu = efx_change_mtu,
2042 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2043 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2044 .ndo_set_features = efx_set_features,
cd2d5b52
BH		 2045#ifdef CONFIG_SFC_SRIOV
2046 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2047 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2048 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2049 .ndo_get_vf_config = efx_sriov_get_vf_config,
2050#endif
c3ecb9f3
SH		 2051#ifdef CONFIG_NET_POLL_CONTROLLER
2052 .ndo_poll_controller = efx_netpoll,
2053#endif
94b274bf 2054 .ndo_setup_tc = efx_setup_tc,
64d8ad6d
BH		 2055#ifdef CONFIG_RFS_ACCEL
2056 .ndo_rx_flow_steer = efx_filter_rfs,
2057#endif
c3ecb9f3
SH		 2058};
2059
7dde596e
BH		 2060static void efx_update_name(struct efx_nic *efx)
2061{
2062 strcpy(efx->name, efx->net_dev->name);
2063 efx_mtd_rename(efx);
2064 efx_set_channel_names(efx);
2065}
2066
8ceee660
BH		 2067static int efx_netdev_event(struct notifier_block *this,
2068 unsigned long event, void *ptr)
2069{
351638e7 2070 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
8ceee660 2071
7dde596e
BH		 2072 if (net_dev->netdev_ops == &efx_netdev_ops &&
2073 event == NETDEV_CHANGENAME)
2074 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 2075
2076 return NOTIFY_DONE;
2077}
2078
2079static struct notifier_block efx_netdev_notifier = {
2080 .notifier_call = efx_netdev_event,
2081};
2082
06d5e193
BH		 2083static ssize_t
2084show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2085{
2086 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2087 return sprintf(buf, "%d\n", efx->phy_type);
2088}
776fbcc9 2089static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
06d5e193 2090
8ceee660
BH		 2091static int efx_register_netdev(struct efx_nic *efx)
2092{
2093 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2094 struct efx_channel *channel;
8ceee660
BH		 2095 int rc;
2096
2097 net_dev->watchdog_timeo = 5 * HZ;
2098 net_dev->irq = efx->pci_dev->irq;
c3ecb9f3 2099 net_dev->netdev_ops = &efx_netdev_ops;
8ceee660 2100 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
7e6d06f0 2101 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
8ceee660 2102
7dde596e 2103 rtnl_lock();
aed0628d 2104
7153f623
BH		 2105 /* Enable resets to be scheduled and check whether any were
2106 * already requested. If so, the NIC is probably hosed so we
2107 * abort.
2108 */
2109 efx->state = STATE_READY;
2110 smp_mb(); /* ensure we change state before checking reset_pending */
2111 if (efx->reset_pending) {
2112 netif_err(efx, probe, efx->net_dev,
2113 "aborting probe due to scheduled reset\n");
2114 rc = -EIO;
2115 goto fail_locked;
2116 }
2117
aed0628d
BH		 2118 rc = dev_alloc_name(net_dev, net_dev->name);
2119 if (rc < 0)
2120 goto fail_locked;
7dde596e 2121 efx_update_name(efx);
aed0628d 2122
8f8b3d51
BH		 2123 /* Always start with carrier off; PHY events will detect the link */
2124 netif_carrier_off(net_dev);
2125
aed0628d
BH		 2126 rc = register_netdevice(net_dev);
2127 if (rc)
2128 goto fail_locked;
2129
c04bfc6b
BH		 2130 efx_for_each_channel(channel, efx) {
2131 struct efx_tx_queue *tx_queue;
60031fcc
BH		 2132 efx_for_each_channel_tx_queue(tx_queue, channel)
2133 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH		 2134 }
2135
7dde596e 2136 rtnl_unlock();
8ceee660 2137
06d5e193
BH		 2138 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2139 if (rc) {
62776d03
BH		 2140 netif_err(efx, drv, efx->net_dev,
2141 "failed to init net dev attributes\n");
06d5e193
BH		 2142 goto fail_registered;
2143 }
2144
8ceee660 2145 return 0;
06d5e193 2146
7153f623
BH		 2147fail_registered:
2148 rtnl_lock();
2149 unregister_netdevice(net_dev);
aed0628d 2150fail_locked:
7153f623 2151 efx->state = STATE_UNINIT;
aed0628d 2152 rtnl_unlock();
62776d03 2153 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2154 return rc;
8ceee660
BH		 2155}
2156
2157static void efx_unregister_netdev(struct efx_nic *efx)
2158{
8ceee660
BH		 2159 if (!efx->net_dev)
2160 return;
2161
767e468c 2162 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660 2163
73ba7b68
BH		 2164 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2165 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
7153f623
BH		 2166
2167 rtnl_lock();
2168 unregister_netdevice(efx->net_dev);
2169 efx->state = STATE_UNINIT;
2170 rtnl_unlock();
8ceee660
BH		 2171}
2172
2173/**************************************************************************
2174 *
2175 * Device reset and suspend
2176 *
2177 **************************************************************************/
2178
2467ca46
BH		 2179/* Tears down the entire software state and most of the hardware state
2180 * before reset. */
d3245b28 2181void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2182{
8ceee660
BH		 2183 EFX_ASSERT_RESET_SERIALISED(efx);
2184
2467ca46 2185 efx_stop_all(efx);
d8291187 2186 efx_disable_interrupts(efx);
5642ceef
BH		 2187
2188 mutex_lock(&efx->mac_lock);
4b988280
SH		 2189 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2190 efx->phy_op->fini(efx);
ef2b90ee 2191 efx->type->fini(efx);
8ceee660
BH		 2192}
2193
2467ca46
BH		 2194/* This function will always ensure that the locks acquired in
2195 * efx_reset_down() are released. A failure return code indicates
2196 * that we were unable to reinitialise the hardware, and the
2197 * driver should be disabled. If ok is false, then the rx and tx
2198 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2199int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 2200{
2201 int rc;
2202
2467ca46 2203 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2204
ef2b90ee 2205 rc = efx->type->init(efx);
8ceee660 2206 if (rc) {
62776d03 2207 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2208 goto fail;
8ceee660
BH		 2209 }
2210
eb9f6744
BH		 2211 if (!ok)
2212 goto fail;
2213
4b988280 2214 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
eb9f6744
BH		 2215 rc = efx->phy_op->init(efx);
2216 if (rc)
2217 goto fail;
2218 if (efx->phy_op->reconfigure(efx))
62776d03
BH		 2219 netif_err(efx, drv, efx->net_dev,
2220 "could not restore PHY settings\n");
4b988280
SH		 2221 }
2222
710b208d 2223 efx->type->reconfigure_mac(efx);
8ceee660 2224
d8291187 2225 efx_enable_interrupts(efx);
64eebcfd 2226 efx_restore_filters(efx);
cd2d5b52 2227 efx_sriov_reset(efx);
eb9f6744 2228
eb9f6744
BH		 2229 mutex_unlock(&efx->mac_lock);
2230
2231 efx_start_all(efx);
2232
2233 return 0;
2234
2235fail:
2236 efx->port_initialized = false;
2467ca46
BH		 2237
2238 mutex_unlock(&efx->mac_lock);
2239
8ceee660
BH		 2240 return rc;
2241}
2242
eb9f6744
BH		 2243/* Reset the NIC using the specified method. Note that the reset may
2244 * fail, in which case the card will be left in an unusable state.
8ceee660 2245 *
eb9f6744 2246 * Caller must hold the rtnl_lock.
8ceee660 2247 */
eb9f6744 2248int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2249{
eb9f6744
BH		 2250 int rc, rc2;
2251 bool disabled;
8ceee660 2252
62776d03
BH		 2253 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2254 RESET_TYPE(method));
8ceee660 2255
c2f3b8e3 2256 efx_device_detach_sync(efx);
d3245b28 2257 efx_reset_down(efx, method);
8ceee660 2258
ef2b90ee 2259 rc = efx->type->reset(efx, method);
8ceee660 2260 if (rc) {
62776d03 2261 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2262 goto out;
8ceee660
BH		 2263 }
2264
a7d529ae
BH		 2265 /* Clear flags for the scopes we covered. We assume the NIC and
2266 * driver are now quiescent so that there is no race here.
2267 */
2268 efx->reset_pending &= -(1 << (method + 1));
8ceee660
BH		 2269
2270 /* Reinitialise bus-mastering, which may have been turned off before
2271 * the reset was scheduled. This is still appropriate, even in the
2272 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2273 * can respond to requests. */
2274 pci_set_master(efx->pci_dev);
2275
eb9f6744 2276out:
8ceee660 2277 /* Leave device stopped if necessary */
626950db
AR		 2278 disabled = rc ||
2279 method == RESET_TYPE_DISABLE ||
2280 method == RESET_TYPE_RECOVER_OR_DISABLE;
eb9f6744
BH		 2281 rc2 = efx_reset_up(efx, method, !disabled);
2282 if (rc2) {
2283 disabled = true;
2284 if (!rc)
2285 rc = rc2;
8ceee660
BH		 2286 }
2287
eb9f6744 2288 if (disabled) {
f49a4589 2289 dev_close(efx->net_dev);
62776d03 2290 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2291 efx->state = STATE_DISABLED;
f4bd954e 2292 } else {
62776d03 2293 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2294 netif_device_attach(efx->net_dev);
f4bd954e 2295 }
8ceee660
BH		 2296 return rc;
2297}
2298
626950db
AR		 2299/* Try recovery mechanisms.
2300 * For now only EEH is supported.
2301 * Returns 0 if the recovery mechanisms are unsuccessful.
2302 * Returns a non-zero value otherwise.
2303 */
b28405b0 2304int efx_try_recovery(struct efx_nic *efx)
626950db
AR		 2305{
2306#ifdef CONFIG_EEH
2307 /* A PCI error can occur and not be seen by EEH because nothing
2308 * happens on the PCI bus. In this case the driver may fail and
2309 * schedule a 'recover or reset', leading to this recovery handler.
2310 * Manually call the eeh failure check function.
2311 */
2312 struct eeh_dev *eehdev =
2313 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
2314
2315 if (eeh_dev_check_failure(eehdev)) {
2316 /* The EEH mechanisms will handle the error and reset the
2317 * device if necessary.
2318 */
2319 return 1;
2320 }
2321#endif
2322 return 0;
2323}
2324
8ceee660
BH		 2325/* The worker thread exists so that code that cannot sleep can
2326 * schedule a reset for later.
2327 */
2328static void efx_reset_work(struct work_struct *data)
2329{
eb9f6744 2330 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
626950db
AR		 2331 unsigned long pending;
2332 enum reset_type method;
2333
2334 pending = ACCESS_ONCE(efx->reset_pending);
2335 method = fls(pending) - 1;
2336
2337 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2338 method == RESET_TYPE_RECOVER_OR_ALL) &&
2339 efx_try_recovery(efx))
2340 return;
8ceee660 2341
a7d529ae 2342 if (!pending)
319ba649
SH		 2343 return;
2344
eb9f6744 2345 rtnl_lock();
7153f623
BH		 2346
2347 /* We checked the state in efx_schedule_reset() but it may
2348 * have changed by now. Now that we have the RTNL lock,
2349 * it cannot change again.
2350 */
2351 if (efx->state == STATE_READY)
626950db 2352 (void)efx_reset(efx, method);
7153f623 2353
eb9f6744 2354 rtnl_unlock();
8ceee660
BH		 2355}
2356
2357void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2358{
2359 enum reset_type method;
2360
626950db
AR		 2361 if (efx->state == STATE_RECOVERY) {
2362 netif_dbg(efx, drv, efx->net_dev,
2363 "recovering: skip scheduling %s reset\n",
2364 RESET_TYPE(type));
2365 return;
2366 }
2367
8ceee660
BH		 2368 switch (type) {
2369 case RESET_TYPE_INVISIBLE:
2370 case RESET_TYPE_ALL:
626950db 2371 case RESET_TYPE_RECOVER_OR_ALL:
8ceee660
BH		 2372 case RESET_TYPE_WORLD:
2373 case RESET_TYPE_DISABLE:
626950db 2374 case RESET_TYPE_RECOVER_OR_DISABLE:
8ceee660 2375 method = type;
0e2a9c7c
BH		 2376 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2377 RESET_TYPE(method));
8ceee660 2378 break;
8ceee660 2379 default:
0e2a9c7c 2380 method = efx->type->map_reset_reason(type);
62776d03
BH		 2381 netif_dbg(efx, drv, efx->net_dev,
2382 "scheduling %s reset for %s\n",
2383 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH		 2384 break;
2385 }
8ceee660 2386
a7d529ae 2387 set_bit(method, &efx->reset_pending);
7153f623
BH		 2388 smp_mb(); /* ensure we change reset_pending before checking state */
2389
2390 /* If we're not READY then just leave the flags set as the cue
2391 * to abort probing or reschedule the reset later.
2392 */
2393 if (ACCESS_ONCE(efx->state) != STATE_READY)
2394 return;
8ceee660 2395
8880f4ec
BH		 2396 /* efx_process_channel() will no longer read events once a
2397 * reset is scheduled. So switch back to poll'd MCDI completions. */
2398 efx_mcdi_mode_poll(efx);
2399
1ab00629 2400 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 2401}
2402
2403/**************************************************************************
2404 *
2405 * List of NICs we support
2406 *
2407 **************************************************************************/
2408
2409/* PCI device ID table */
a3aa1884 2410static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
937383a5
BH		 2411 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2412 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
daeda630 2413 .driver_data = (unsigned long) &falcon_a1_nic_type},
937383a5
BH		 2414 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2415 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
daeda630 2416 .driver_data = (unsigned long) &falcon_b0_nic_type},
547c474f 2417 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2418 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2419 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2420 .driver_data = (unsigned long) &siena_a0_nic_type},
8ceee660
BH		 2421 {0} /* end of list */
2422};
2423
2424/**************************************************************************
2425 *
3759433d 2426 * Dummy PHY/MAC operations
8ceee660 2427 *
01aad7b6 2428 * Can be used for some unimplemented operations
8ceee660
BH		 2429 * Needed so all function pointers are valid and do not have to be tested
2430 * before use
2431 *
2432 **************************************************************************/
2433int efx_port_dummy_op_int(struct efx_nic *efx)
2434{
2435 return 0;
2436}
2437void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2438
2439static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH		 2440{
2441 return false;
2442}
8ceee660 2443
6c8c2513 2444static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2445 .init = efx_port_dummy_op_int,
d3245b28 2446 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2447 .poll = efx_port_dummy_op_poll,
8ceee660 2448 .fini = efx_port_dummy_op_void,
8ceee660
BH		 2449};
2450
8ceee660
BH		 2451/**************************************************************************
2452 *
2453 * Data housekeeping
2454 *
2455 **************************************************************************/
2456
2457/* This zeroes out and then fills in the invariants in a struct
2458 * efx_nic (including all sub-structures).
2459 */
adeb15aa 2460static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH		 2461 struct pci_dev *pci_dev, struct net_device *net_dev)
2462{
4642610c 2463 int i;
8ceee660
BH		 2464
2465 /* Initialise common structures */
8ceee660 2466 spin_lock_init(&efx->biu_lock);
76884835
BH		 2467#ifdef CONFIG_SFC_MTD
2468 INIT_LIST_HEAD(&efx->mtd_list);
2469#endif
8ceee660
BH		 2470 INIT_WORK(&efx->reset_work, efx_reset_work);
2471 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2472 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2473 efx->pci_dev = pci_dev;
62776d03 2474 efx->msg_enable = debug;
f16aeea0 2475 efx->state = STATE_UNINIT;
8ceee660 2476 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2477
2478 efx->net_dev = net_dev;
8ceee660
BH		 2479 spin_lock_init(&efx->stats_lock);
2480 mutex_init(&efx->mac_lock);
2481 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2482 efx->mdio.dev = net_dev;
766ca0fa 2483 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2484 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH		 2485
2486 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH		 2487 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2488 if (!efx->channel[i])
2489 goto fail;
d8291187
BH		 2490 efx->msi_context[i].efx = efx;
2491 efx->msi_context[i].index = i;
8ceee660
BH		 2492 }
2493
8ceee660
BH		 2494 /* Higher numbered interrupt modes are less capable! */
2495 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2496 interrupt_mode);
2497
6977dc63
BH		 2498 /* Would be good to use the net_dev name, but we're too early */
2499 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2500 pci_name(pci_dev));
2501 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2502 if (!efx->workqueue)
4642610c 2503 goto fail;
8d9853d9 2504
8ceee660 2505 return 0;
4642610c
BH		 2506
2507fail:
2508 efx_fini_struct(efx);
2509 return -ENOMEM;
8ceee660
BH		 2510}
2511
2512static void efx_fini_struct(struct efx_nic *efx)
2513{
8313aca3
BH		 2514 int i;
2515
2516 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2517 kfree(efx->channel[i]);
2518
8ceee660
BH		 2519 if (efx->workqueue) {
2520 destroy_workqueue(efx->workqueue);
2521 efx->workqueue = NULL;
2522 }
2523}
2524
2525/**************************************************************************
2526 *
2527 * PCI interface
2528 *
2529 **************************************************************************/
2530
2531/* Main body of final NIC shutdown code
2532 * This is called only at module unload (or hotplug removal).
2533 */
2534static void efx_pci_remove_main(struct efx_nic *efx)
2535{
7153f623
BH		 2536 /* Flush reset_work. It can no longer be scheduled since we
2537 * are not READY.
2538 */
2539 BUG_ON(efx->state == STATE_READY);
2540 cancel_work_sync(&efx->reset_work);
2541
d8291187 2542 efx_disable_interrupts(efx);
152b6a62 2543 efx_nic_fini_interrupt(efx);
8ceee660 2544 efx_fini_port(efx);
ef2b90ee 2545 efx->type->fini(efx);
8ceee660
BH		 2546 efx_fini_napi(efx);
2547 efx_remove_all(efx);
2548}
2549
2550/* Final NIC shutdown
2551 * This is called only at module unload (or hotplug removal).
2552 */
2553static void efx_pci_remove(struct pci_dev *pci_dev)
2554{
2555 struct efx_nic *efx;
2556
2557 efx = pci_get_drvdata(pci_dev);
2558 if (!efx)
2559 return;
2560
2561 /* Mark the NIC as fini, then stop the interface */
2562 rtnl_lock();
8ceee660 2563 dev_close(efx->net_dev);
d8291187 2564 efx_disable_interrupts(efx);
8ceee660
BH		 2565 rtnl_unlock();
2566
cd2d5b52 2567 efx_sriov_fini(efx);
8ceee660
BH		 2568 efx_unregister_netdev(efx);
2569
7dde596e
BH		 2570 efx_mtd_remove(efx);
2571
8ceee660
BH		 2572 efx_pci_remove_main(efx);
2573
8ceee660 2574 efx_fini_io(efx);
62776d03 2575 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 2576
8ceee660 2577 efx_fini_struct(efx);
3de4e301 2578 pci_set_drvdata(pci_dev, NULL);
8ceee660 2579 free_netdev(efx->net_dev);
626950db
AR		 2580
2581 pci_disable_pcie_error_reporting(pci_dev);
8ceee660
BH		 2582};
2583
460eeaa0
BH		 2584/* NIC VPD information
2585 * Called during probe to display the part number of the
2586 * installed NIC. VPD is potentially very large but this should
2587 * always appear within the first 512 bytes.
2588 */
2589#define SFC_VPD_LEN 512
2590static void efx_print_product_vpd(struct efx_nic *efx)
2591{
2592 struct pci_dev *dev = efx->pci_dev;
2593 char vpd_data[SFC_VPD_LEN];
2594 ssize_t vpd_size;
2595 int i, j;
2596
2597 /* Get the vpd data from the device */
2598 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
2599 if (vpd_size <= 0) {
2600 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
2601 return;
2602 }
2603
2604 /* Get the Read only section */
2605 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
2606 if (i < 0) {
2607 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
2608 return;
2609 }
2610
2611 j = pci_vpd_lrdt_size(&vpd_data[i]);
2612 i += PCI_VPD_LRDT_TAG_SIZE;
2613 if (i + j > vpd_size)
2614 j = vpd_size - i;
2615
2616 /* Get the Part number */
2617 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
2618 if (i < 0) {
2619 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
2620 return;
2621 }
2622
2623 j = pci_vpd_info_field_size(&vpd_data[i]);
2624 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2625 if (i + j > vpd_size) {
2626 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
2627 return;
2628 }
2629
2630 netif_info(efx, drv, efx->net_dev,
2631 "Part Number : %.*s\n", j, &vpd_data[i]);
2632}
2633
2634
8ceee660
BH		 2635/* Main body of NIC initialisation
2636 * This is called at module load (or hotplug insertion, theoretically).
2637 */
2638static int efx_pci_probe_main(struct efx_nic *efx)
2639{
2640 int rc;
2641
2642 /* Do start-of-day initialisation */
2643 rc = efx_probe_all(efx);
2644 if (rc)
2645 goto fail1;
2646
e8f14992 2647 efx_init_napi(efx);
8ceee660 2648
ef2b90ee 2649 rc = efx->type->init(efx);
8ceee660 2650 if (rc) {
62776d03
BH		 2651 netif_err(efx, probe, efx->net_dev,
2652 "failed to initialise NIC\n");
278c0621 2653 goto fail3;
8ceee660
BH		 2654 }
2655
2656 rc = efx_init_port(efx);
2657 if (rc) {
62776d03
BH		 2658 netif_err(efx, probe, efx->net_dev,
2659 "failed to initialise port\n");
278c0621 2660 goto fail4;
8ceee660
BH		 2661 }
2662
152b6a62 2663 rc = efx_nic_init_interrupt(efx);
8ceee660 2664 if (rc)
278c0621 2665 goto fail5;
d8291187 2666 efx_enable_interrupts(efx);
8ceee660
BH		 2667
2668 return 0;
2669
278c0621 2670 fail5:
8ceee660 2671 efx_fini_port(efx);
8ceee660 2672 fail4:
ef2b90ee 2673 efx->type->fini(efx);
8ceee660
BH		 2674 fail3:
2675 efx_fini_napi(efx);
8ceee660
BH		 2676 efx_remove_all(efx);
2677 fail1:
2678 return rc;
2679}
2680
2681/* NIC initialisation
2682 *
2683 * This is called at module load (or hotplug insertion,
73ba7b68 2684 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH		 2685 * sets up and registers the network devices with the kernel and hooks
2686 * the interrupt service routine. It does not prepare the device for
2687 * transmission; this is left to the first time one of the network
2688 * interfaces is brought up (i.e. efx_net_open).
2689 */
87d1fc11 2690static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 2691 const struct pci_device_id *entry)
8ceee660 2692{
8ceee660
BH		 2693 struct net_device *net_dev;
2694 struct efx_nic *efx;
fadac6aa 2695 int rc;
8ceee660
BH		 2696
2697 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH		 2698 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2699 EFX_MAX_RX_QUEUES);
8ceee660
BH		 2700 if (!net_dev)
2701 return -ENOMEM;
adeb15aa
BH		 2702 efx = netdev_priv(net_dev);
2703 efx->type = (const struct efx_nic_type *) entry->driver_data;
2704 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
97bc5415 2705 NETIF_F_HIGHDMA | NETIF_F_TSO |
abfe9039 2706 NETIF_F_RXCSUM);
adeb15aa 2707 if (efx->type->offload_features & NETIF_F_V6_CSUM)
738a8f4b 2708 net_dev->features |= NETIF_F_TSO6;
28506563
BH		 2709 /* Mask for features that also apply to VLAN devices */
2710 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
abfe9039
BH		 2711 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2712 NETIF_F_RXCSUM);
2713 /* All offloads can be toggled */
2714 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
8ceee660 2715 pci_set_drvdata(pci_dev, efx);
62776d03 2716 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 2717 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH		 2718 if (rc)
2719 goto fail1;
2720
62776d03 2721 netif_info(efx, probe, efx->net_dev,
ff79c8ac 2722 "Solarflare NIC detected\n");
8ceee660 2723
460eeaa0
BH		 2724 efx_print_product_vpd(efx);
2725
8ceee660
BH		 2726 /* Set up basic I/O (BAR mappings etc) */
2727 rc = efx_init_io(efx);
2728 if (rc)
2729 goto fail2;
2730
fadac6aa 2731 rc = efx_pci_probe_main(efx);
fadac6aa
BH		 2732 if (rc)
2733 goto fail3;
8ceee660 2734
8ceee660
BH		 2735 rc = efx_register_netdev(efx);
2736 if (rc)
fadac6aa 2737 goto fail4;
8ceee660 2738
cd2d5b52
BH		 2739 rc = efx_sriov_init(efx);
2740 if (rc)
2741 netif_err(efx, probe, efx->net_dev,
2742 "SR-IOV can't be enabled rc %d\n", rc);
2743
62776d03 2744 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 2745
7c43161c 2746 /* Try to create MTDs, but allow this to fail */
a5211bb5 2747 rtnl_lock();
7c43161c 2748 rc = efx_mtd_probe(efx);
a5211bb5 2749 rtnl_unlock();
7c43161c
BH		 2750 if (rc)
2751 netif_warn(efx, probe, efx->net_dev,
2752 "failed to create MTDs (%d)\n", rc);
2753
626950db
AR		 2754 rc = pci_enable_pcie_error_reporting(pci_dev);
2755 if (rc && rc != -EINVAL)
2756 netif_warn(efx, probe, efx->net_dev,
2757 "pci_enable_pcie_error_reporting failed (%d)\n", rc);
2758
8ceee660
BH		 2759 return 0;
2760
8ceee660 2761 fail4:
fadac6aa 2762 efx_pci_remove_main(efx);
8ceee660
BH		 2763 fail3:
2764 efx_fini_io(efx);
2765 fail2:
2766 efx_fini_struct(efx);
2767 fail1:
3de4e301 2768 pci_set_drvdata(pci_dev, NULL);
5e2a911c 2769 WARN_ON(rc > 0);
62776d03 2770 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH		 2771 free_netdev(net_dev);
2772 return rc;
2773}
2774
89c758fa
BH		 2775static int efx_pm_freeze(struct device *dev)
2776{
2777 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2778
61da026d
BH		 2779 rtnl_lock();
2780
6032fb56
BH		 2781 if (efx->state != STATE_DISABLED) {
2782 efx->state = STATE_UNINIT;
89c758fa 2783
c2f3b8e3 2784 efx_device_detach_sync(efx);
89c758fa 2785
6032fb56 2786 efx_stop_all(efx);
d8291187 2787 efx_disable_interrupts(efx);
6032fb56 2788 }
89c758fa 2789
61da026d
BH		 2790 rtnl_unlock();
2791
89c758fa
BH		 2792 return 0;
2793}
2794
2795static int efx_pm_thaw(struct device *dev)
2796{
2797 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2798
61da026d
BH		 2799 rtnl_lock();
2800
6032fb56 2801 if (efx->state != STATE_DISABLED) {
d8291187 2802 efx_enable_interrupts(efx);
89c758fa 2803
6032fb56
BH		 2804 mutex_lock(&efx->mac_lock);
2805 efx->phy_op->reconfigure(efx);
2806 mutex_unlock(&efx->mac_lock);
89c758fa 2807
6032fb56 2808 efx_start_all(efx);
89c758fa 2809
6032fb56 2810 netif_device_attach(efx->net_dev);
89c758fa 2811
6032fb56 2812 efx->state = STATE_READY;
89c758fa 2813
6032fb56
BH		 2814 efx->type->resume_wol(efx);
2815 }
89c758fa 2816
61da026d
BH		 2817 rtnl_unlock();
2818
319ba649
SH		 2819 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2820 queue_work(reset_workqueue, &efx->reset_work);
2821
89c758fa
BH		 2822 return 0;
2823}
2824
2825static int efx_pm_poweroff(struct device *dev)
2826{
2827 struct pci_dev *pci_dev = to_pci_dev(dev);
2828 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2829
2830 efx->type->fini(efx);
2831
a7d529ae 2832 efx->reset_pending = 0;
89c758fa
BH		 2833
2834 pci_save_state(pci_dev);
2835 return pci_set_power_state(pci_dev, PCI_D3hot);
2836}
2837
2838/* Used for both resume and restore */
2839static int efx_pm_resume(struct device *dev)
2840{
2841 struct pci_dev *pci_dev = to_pci_dev(dev);
2842 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2843 int rc;
2844
2845 rc = pci_set_power_state(pci_dev, PCI_D0);
2846 if (rc)
2847 return rc;
2848 pci_restore_state(pci_dev);
2849 rc = pci_enable_device(pci_dev);
2850 if (rc)
2851 return rc;
2852 pci_set_master(efx->pci_dev);
2853 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2854 if (rc)
2855 return rc;
2856 rc = efx->type->init(efx);
2857 if (rc)
2858 return rc;
2859 efx_pm_thaw(dev);
2860 return 0;
2861}
2862
2863static int efx_pm_suspend(struct device *dev)
2864{
2865 int rc;
2866
2867 efx_pm_freeze(dev);
2868 rc = efx_pm_poweroff(dev);
2869 if (rc)
2870 efx_pm_resume(dev);
2871 return rc;
2872}
2873
18e83e4c 2874static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH		 2875 .suspend = efx_pm_suspend,
2876 .resume = efx_pm_resume,
2877 .freeze = efx_pm_freeze,
2878 .thaw = efx_pm_thaw,
2879 .poweroff = efx_pm_poweroff,
2880 .restore = efx_pm_resume,
2881};
2882
626950db
AR		 2883/* A PCI error affecting this device was detected.
2884 * At this point MMIO and DMA may be disabled.
2885 * Stop the software path and request a slot reset.
2886 */
debd0034 2887static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
2888 enum pci_channel_state state)
626950db
AR		 2889{
2890 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2891 struct efx_nic *efx = pci_get_drvdata(pdev);
2892
2893 if (state == pci_channel_io_perm_failure)
2894 return PCI_ERS_RESULT_DISCONNECT;
2895
2896 rtnl_lock();
2897
2898 if (efx->state != STATE_DISABLED) {
2899 efx->state = STATE_RECOVERY;
2900 efx->reset_pending = 0;
2901
2902 efx_device_detach_sync(efx);
2903
2904 efx_stop_all(efx);
d8291187 2905 efx_disable_interrupts(efx);
626950db
AR		 2906
2907 status = PCI_ERS_RESULT_NEED_RESET;
2908 } else {
2909 /* If the interface is disabled we don't want to do anything
2910 * with it.
2911 */
2912 status = PCI_ERS_RESULT_RECOVERED;
2913 }
2914
2915 rtnl_unlock();
2916
2917 pci_disable_device(pdev);
2918
2919 return status;
2920}
2921
2922/* Fake a successfull reset, which will be performed later in efx_io_resume. */
debd0034 2923static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
626950db
AR		 2924{
2925 struct efx_nic *efx = pci_get_drvdata(pdev);
2926 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2927 int rc;
2928
2929 if (pci_enable_device(pdev)) {
2930 netif_err(efx, hw, efx->net_dev,
2931 "Cannot re-enable PCI device after reset.\n");
2932 status = PCI_ERS_RESULT_DISCONNECT;
2933 }
2934
2935 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
2936 if (rc) {
2937 netif_err(efx, hw, efx->net_dev,
2938 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
2939 /* Non-fatal error. Continue. */
2940 }
2941
2942 return status;
2943}
2944
2945/* Perform the actual reset and resume I/O operations. */
2946static void efx_io_resume(struct pci_dev *pdev)
2947{
2948 struct efx_nic *efx = pci_get_drvdata(pdev);
2949 int rc;
2950
2951 rtnl_lock();
2952
2953 if (efx->state == STATE_DISABLED)
2954 goto out;
2955
2956 rc = efx_reset(efx, RESET_TYPE_ALL);
2957 if (rc) {
2958 netif_err(efx, hw, efx->net_dev,
2959 "efx_reset failed after PCI error (%d)\n", rc);
2960 } else {
2961 efx->state = STATE_READY;
2962 netif_dbg(efx, hw, efx->net_dev,
2963 "Done resetting and resuming IO after PCI error.\n");
2964 }
2965
2966out:
2967 rtnl_unlock();
2968}
2969
2970/* For simplicity and reliability, we always require a slot reset and try to
2971 * reset the hardware when a pci error affecting the device is detected.
2972 * We leave both the link_reset and mmio_enabled callback unimplemented:
2973 * with our request for slot reset the mmio_enabled callback will never be
2974 * called, and the link_reset callback is not used by AER or EEH mechanisms.
2975 */
2976static struct pci_error_handlers efx_err_handlers = {
2977 .error_detected = efx_io_error_detected,
2978 .slot_reset = efx_io_slot_reset,
2979 .resume = efx_io_resume,
2980};
2981
8ceee660 2982static struct pci_driver efx_pci_driver = {
c5d5f5fd 2983 .name = KBUILD_MODNAME,
8ceee660
BH		 2984 .id_table = efx_pci_table,
2985 .probe = efx_pci_probe,
2986 .remove = efx_pci_remove,
89c758fa 2987 .driver.pm = &efx_pm_ops,
626950db 2988 .err_handler = &efx_err_handlers,
8ceee660
BH		 2989};
2990
2991/**************************************************************************
2992 *
2993 * Kernel module interface
2994 *
2995 *************************************************************************/
2996
2997module_param(interrupt_mode, uint, 0444);
2998MODULE_PARM_DESC(interrupt_mode,
2999 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
3000
3001static int __init efx_init_module(void)
3002{
3003 int rc;
3004
3005 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
3006
3007 rc = register_netdevice_notifier(&efx_netdev_notifier);
3008 if (rc)
3009 goto err_notifier;
3010
cd2d5b52
BH		 3011 rc = efx_init_sriov();
3012 if (rc)
3013 goto err_sriov;
3014
1ab00629
SH		 3015 reset_workqueue = create_singlethread_workqueue("sfc_reset");
3016 if (!reset_workqueue) {
3017 rc = -ENOMEM;
3018 goto err_reset;
3019 }
8ceee660
BH		 3020
3021 rc = pci_register_driver(&efx_pci_driver);
3022 if (rc < 0)
3023 goto err_pci;
3024
3025 return 0;
3026
3027 err_pci:
1ab00629
SH		 3028 destroy_workqueue(reset_workqueue);
3029 err_reset:
cd2d5b52
BH		 3030 efx_fini_sriov();
3031 err_sriov:
8ceee660
BH		 3032 unregister_netdevice_notifier(&efx_netdev_notifier);
3033 err_notifier:
3034 return rc;
3035}
3036
3037static void __exit efx_exit_module(void)
3038{
3039 printk(KERN_INFO "Solarflare NET driver unloading\n");
3040
3041 pci_unregister_driver(&efx_pci_driver);
1ab00629 3042 destroy_workqueue(reset_workqueue);
cd2d5b52 3043 efx_fini_sriov();
8ceee660
BH		 3044 unregister_netdevice_notifier(&efx_netdev_notifier);
3045
3046}
3047
3048module_init(efx_init_module);
3049module_exit(efx_exit_module);
3050
906bb26c
BH		 3051MODULE_AUTHOR("Solarflare Communications and "
3052 "Michael Brown <mbrown@fensystems.co.uk>");
8ceee660
BH		 3053MODULE_DESCRIPTION("Solarflare Communications network driver");
3054MODULE_LICENSE("GPL");
3055MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux kernel - Deliverables
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