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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2005-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
8ceee660 | 20 | #include <linux/ethtool.h> |
aa6ef27e | 21 | #include <linux/topology.h> |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
626950db | 23 | #include <linux/aer.h> |
b28405b0 | 24 | #include <linux/interrupt.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
dd40781e | 28 | #include "selftest.h" |
7fa8d547 | 29 | #include "sriov.h" |
8ceee660 | 30 | |
8880f4ec | 31 | #include "mcdi.h" |
fd371e32 | 32 | #include "workarounds.h" |
8880f4ec | 33 | |
c459302d BH |
34 | /************************************************************************** |
35 | * | |
36 | * Type name strings | |
37 | * | |
38 | ************************************************************************** | |
39 | */ | |
40 | ||
41 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
42 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 43 | const char *const efx_loopback_mode_names[] = { |
c459302d | 44 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 45 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
46 | [LOOPBACK_GMAC] = "GMAC", |
47 | [LOOPBACK_XGMII] = "XGMII", | |
48 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
49 | [LOOPBACK_XAUI] = "XAUI", |
50 | [LOOPBACK_GMII] = "GMII", | |
51 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
52 | [LOOPBACK_XGBR] = "XGBR", |
53 | [LOOPBACK_XFI] = "XFI", | |
54 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
55 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
56 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
57 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
58 | [LOOPBACK_GPHY] = "GPHY", |
59 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
60 | [LOOPBACK_PCS] = "PCS", |
61 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
62 | [LOOPBACK_XPORT] = "XPORT", |
63 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 64 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
65 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
66 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 67 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
68 | [LOOPBACK_XFI_WS] = "XFI_WS", |
69 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 70 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
71 | }; |
72 | ||
c459302d | 73 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 74 | const char *const efx_reset_type_names[] = { |
626950db AR |
75 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
76 | [RESET_TYPE_ALL] = "ALL", | |
77 | [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", | |
78 | [RESET_TYPE_WORLD] = "WORLD", | |
79 | [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", | |
e283546c | 80 | [RESET_TYPE_MC_BIST] = "MC_BIST", |
626950db AR |
81 | [RESET_TYPE_DISABLE] = "DISABLE", |
82 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
83 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
84 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
3de82b91 | 85 | [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", |
626950db AR |
86 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", |
87 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", | |
e283546c | 88 | [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)", |
c459302d BH |
89 | }; |
90 | ||
1ab00629 SH |
91 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
92 | * queued onto this work queue. This is not a per-nic work queue, because | |
93 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
94 | */ | |
95 | static struct workqueue_struct *reset_workqueue; | |
96 | ||
74cd60a4 JC |
97 | /* How often and how many times to poll for a reset while waiting for a |
98 | * BIST that another function started to complete. | |
99 | */ | |
100 | #define BIST_WAIT_DELAY_MS 100 | |
101 | #define BIST_WAIT_DELAY_COUNT 100 | |
102 | ||
8ceee660 BH |
103 | /************************************************************************** |
104 | * | |
105 | * Configurable values | |
106 | * | |
107 | *************************************************************************/ | |
108 | ||
8ceee660 BH |
109 | /* |
110 | * Use separate channels for TX and RX events | |
111 | * | |
28b581ab NT |
112 | * Set this to 1 to use separate channels for TX and RX. It allows us |
113 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 114 | * |
28b581ab | 115 | * This is only used in MSI-X interrupt mode |
8ceee660 | 116 | */ |
b9cc977d BH |
117 | static bool separate_tx_channels; |
118 | module_param(separate_tx_channels, bool, 0444); | |
28b581ab NT |
119 | MODULE_PARM_DESC(separate_tx_channels, |
120 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
121 | |
122 | /* This is the weight assigned to each of the (per-channel) virtual | |
123 | * NAPI devices. | |
124 | */ | |
125 | static int napi_weight = 64; | |
126 | ||
127 | /* This is the time (in jiffies) between invocations of the hardware | |
626950db AR |
128 | * monitor. |
129 | * On Falcon-based NICs, this will: | |
e254c274 BH |
130 | * - Check the on-board hardware monitor; |
131 | * - Poll the link state and reconfigure the hardware as necessary. | |
626950db AR |
132 | * On Siena-based NICs for power systems with EEH support, this will give EEH a |
133 | * chance to start. | |
8ceee660 | 134 | */ |
d215697f | 135 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 136 | |
8ceee660 BH |
137 | /* Initial interrupt moderation settings. They can be modified after |
138 | * module load with ethtool. | |
139 | * | |
140 | * The default for RX should strike a balance between increasing the | |
141 | * round-trip latency and reducing overhead. | |
142 | */ | |
143 | static unsigned int rx_irq_mod_usec = 60; | |
144 | ||
145 | /* Initial interrupt moderation settings. They can be modified after | |
146 | * module load with ethtool. | |
147 | * | |
148 | * This default is chosen to ensure that a 10G link does not go idle | |
149 | * while a TX queue is stopped after it has become full. A queue is | |
150 | * restarted when it drops below half full. The time this takes (assuming | |
151 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
152 | * 512 / 3 * 1.2 = 205 usec. | |
153 | */ | |
154 | static unsigned int tx_irq_mod_usec = 150; | |
155 | ||
156 | /* This is the first interrupt mode to try out of: | |
157 | * 0 => MSI-X | |
158 | * 1 => MSI | |
159 | * 2 => legacy | |
160 | */ | |
161 | static unsigned int interrupt_mode; | |
162 | ||
163 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
164 | * i.e. the number of CPUs among which we may distribute simultaneous | |
165 | * interrupt handling. | |
166 | * | |
167 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 168 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
169 | */ |
170 | static unsigned int rss_cpus; | |
171 | module_param(rss_cpus, uint, 0444); | |
172 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
173 | ||
b9cc977d BH |
174 | static bool phy_flash_cfg; |
175 | module_param(phy_flash_cfg, bool, 0644); | |
84ae48fe BH |
176 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); |
177 | ||
e7bed9c8 | 178 | static unsigned irq_adapt_low_thresh = 8000; |
6fb70fd1 BH |
179 | module_param(irq_adapt_low_thresh, uint, 0644); |
180 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
181 | "Threshold score for reducing IRQ moderation"); | |
182 | ||
e7bed9c8 | 183 | static unsigned irq_adapt_high_thresh = 16000; |
6fb70fd1 BH |
184 | module_param(irq_adapt_high_thresh, uint, 0644); |
185 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
186 | "Threshold score for increasing IRQ moderation"); | |
187 | ||
62776d03 BH |
188 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
189 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
190 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
191 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
192 | module_param(debug, uint, 0); | |
193 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
194 | ||
8ceee660 BH |
195 | /************************************************************************** |
196 | * | |
197 | * Utility functions and prototypes | |
198 | * | |
199 | *************************************************************************/ | |
4642610c | 200 | |
261e4d96 | 201 | static int efx_soft_enable_interrupts(struct efx_nic *efx); |
d8291187 | 202 | static void efx_soft_disable_interrupts(struct efx_nic *efx); |
7f967c01 | 203 | static void efx_remove_channel(struct efx_channel *channel); |
4642610c | 204 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 205 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 206 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 207 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 208 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 209 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
210 | static void efx_fini_struct(struct efx_nic *efx); |
211 | static void efx_start_all(struct efx_nic *efx); | |
212 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
213 | |
214 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
215 | do { \ | |
f16aeea0 | 216 | if ((efx->state == STATE_READY) || \ |
626950db | 217 | (efx->state == STATE_RECOVERY) || \ |
332c1ce9 | 218 | (efx->state == STATE_DISABLED)) \ |
8ceee660 BH |
219 | ASSERT_RTNL(); \ |
220 | } while (0) | |
221 | ||
8b7325b4 BH |
222 | static int efx_check_disabled(struct efx_nic *efx) |
223 | { | |
626950db | 224 | if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { |
8b7325b4 BH |
225 | netif_err(efx, drv, efx->net_dev, |
226 | "device is disabled due to earlier errors\n"); | |
227 | return -EIO; | |
228 | } | |
229 | return 0; | |
230 | } | |
231 | ||
8ceee660 BH |
232 | /************************************************************************** |
233 | * | |
234 | * Event queue processing | |
235 | * | |
236 | *************************************************************************/ | |
237 | ||
238 | /* Process channel's event queue | |
239 | * | |
240 | * This function is responsible for processing the event queue of a | |
241 | * single channel. The caller must guarantee that this function will | |
242 | * never be concurrently called more than once on the same channel, | |
243 | * though different channels may be being processed concurrently. | |
244 | */ | |
fa236e18 | 245 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 246 | { |
fa236e18 | 247 | int spent; |
8ceee660 | 248 | |
9f2cb71c | 249 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 250 | return 0; |
8ceee660 | 251 | |
fa236e18 | 252 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
253 | if (spent && efx_channel_has_rx_queue(channel)) { |
254 | struct efx_rx_queue *rx_queue = | |
255 | efx_channel_get_rx_queue(channel); | |
256 | ||
ff734ef4 | 257 | efx_rx_flush_packet(channel); |
cce28794 | 258 | efx_fast_push_rx_descriptors(rx_queue, true); |
8ceee660 BH |
259 | } |
260 | ||
fa236e18 | 261 | return spent; |
8ceee660 BH |
262 | } |
263 | ||
8ceee660 BH |
264 | /* NAPI poll handler |
265 | * | |
266 | * NAPI guarantees serialisation of polls of the same device, which | |
267 | * provides the guarantee required by efx_process_channel(). | |
268 | */ | |
269 | static int efx_poll(struct napi_struct *napi, int budget) | |
270 | { | |
271 | struct efx_channel *channel = | |
272 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 273 | struct efx_nic *efx = channel->efx; |
fa236e18 | 274 | int spent; |
8ceee660 | 275 | |
36763266 AR |
276 | if (!efx_channel_lock_napi(channel)) |
277 | return budget; | |
278 | ||
62776d03 BH |
279 | netif_vdbg(efx, intr, efx->net_dev, |
280 | "channel %d NAPI poll executing on CPU %d\n", | |
281 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 282 | |
fa236e18 | 283 | spent = efx_process_channel(channel, budget); |
8ceee660 | 284 | |
fa236e18 | 285 | if (spent < budget) { |
9d9a6973 | 286 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
287 | efx->irq_rx_adaptive && |
288 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
289 | if (unlikely(channel->irq_mod_score < |
290 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
291 | if (channel->irq_moderation > 1) { |
292 | channel->irq_moderation -= 1; | |
ef2b90ee | 293 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 294 | } |
6fb70fd1 BH |
295 | } else if (unlikely(channel->irq_mod_score > |
296 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
297 | if (channel->irq_moderation < |
298 | efx->irq_rx_moderation) { | |
299 | channel->irq_moderation += 1; | |
ef2b90ee | 300 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 301 | } |
6fb70fd1 | 302 | } |
6fb70fd1 BH |
303 | channel->irq_count = 0; |
304 | channel->irq_mod_score = 0; | |
305 | } | |
306 | ||
64d8ad6d BH |
307 | efx_filter_rfs_expire(channel); |
308 | ||
8ceee660 | 309 | /* There is no race here; although napi_disable() will |
288379f0 | 310 | * only wait for napi_complete(), this isn't a problem |
514bedbc | 311 | * since efx_nic_eventq_read_ack() will have no effect if |
8ceee660 BH |
312 | * interrupts have already been disabled. |
313 | */ | |
288379f0 | 314 | napi_complete(napi); |
514bedbc | 315 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
316 | } |
317 | ||
36763266 | 318 | efx_channel_unlock_napi(channel); |
fa236e18 | 319 | return spent; |
8ceee660 BH |
320 | } |
321 | ||
8ceee660 BH |
322 | /* Create event queue |
323 | * Event queue memory allocations are done only once. If the channel | |
324 | * is reset, the memory buffer will be reused; this guards against | |
325 | * errors during channel reset and also simplifies interrupt handling. | |
326 | */ | |
327 | static int efx_probe_eventq(struct efx_channel *channel) | |
328 | { | |
ecc910f5 SH |
329 | struct efx_nic *efx = channel->efx; |
330 | unsigned long entries; | |
331 | ||
86ee5302 | 332 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 333 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 334 | |
ecc910f5 SH |
335 | /* Build an event queue with room for one event per tx and rx buffer, |
336 | * plus some extra for link state events and MCDI completions. */ | |
337 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
338 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
339 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
340 | ||
152b6a62 | 341 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
342 | } |
343 | ||
344 | /* Prepare channel's event queue */ | |
261e4d96 | 345 | static int efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 346 | { |
15acb1ce | 347 | struct efx_nic *efx = channel->efx; |
261e4d96 JC |
348 | int rc; |
349 | ||
350 | EFX_WARN_ON_PARANOID(channel->eventq_init); | |
351 | ||
15acb1ce | 352 | netif_dbg(efx, drv, efx->net_dev, |
62776d03 | 353 | "chan %d init event queue\n", channel->channel); |
8ceee660 | 354 | |
261e4d96 JC |
355 | rc = efx_nic_init_eventq(channel); |
356 | if (rc == 0) { | |
15acb1ce | 357 | efx->type->push_irq_moderation(channel); |
261e4d96 JC |
358 | channel->eventq_read_ptr = 0; |
359 | channel->eventq_init = true; | |
360 | } | |
361 | return rc; | |
8ceee660 BH |
362 | } |
363 | ||
9f2cb71c | 364 | /* Enable event queue processing and NAPI */ |
36763266 | 365 | void efx_start_eventq(struct efx_channel *channel) |
9f2cb71c BH |
366 | { |
367 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
368 | "chan %d start event queue\n", channel->channel); | |
369 | ||
514bedbc | 370 | /* Make sure the NAPI handler sees the enabled flag set */ |
9f2cb71c BH |
371 | channel->enabled = true; |
372 | smp_wmb(); | |
373 | ||
36763266 | 374 | efx_channel_enable(channel); |
9f2cb71c BH |
375 | napi_enable(&channel->napi_str); |
376 | efx_nic_eventq_read_ack(channel); | |
377 | } | |
378 | ||
379 | /* Disable event queue processing and NAPI */ | |
36763266 | 380 | void efx_stop_eventq(struct efx_channel *channel) |
9f2cb71c BH |
381 | { |
382 | if (!channel->enabled) | |
383 | return; | |
384 | ||
385 | napi_disable(&channel->napi_str); | |
36763266 AR |
386 | while (!efx_channel_disable(channel)) |
387 | usleep_range(1000, 20000); | |
9f2cb71c BH |
388 | channel->enabled = false; |
389 | } | |
390 | ||
8ceee660 BH |
391 | static void efx_fini_eventq(struct efx_channel *channel) |
392 | { | |
be3fc09c BH |
393 | if (!channel->eventq_init) |
394 | return; | |
395 | ||
62776d03 BH |
396 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
397 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 398 | |
152b6a62 | 399 | efx_nic_fini_eventq(channel); |
be3fc09c | 400 | channel->eventq_init = false; |
8ceee660 BH |
401 | } |
402 | ||
403 | static void efx_remove_eventq(struct efx_channel *channel) | |
404 | { | |
62776d03 BH |
405 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
406 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 407 | |
152b6a62 | 408 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
409 | } |
410 | ||
411 | /************************************************************************** | |
412 | * | |
413 | * Channel handling | |
414 | * | |
415 | *************************************************************************/ | |
416 | ||
7f967c01 | 417 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
418 | static struct efx_channel * |
419 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
420 | { | |
421 | struct efx_channel *channel; | |
422 | struct efx_rx_queue *rx_queue; | |
423 | struct efx_tx_queue *tx_queue; | |
424 | int j; | |
425 | ||
7f967c01 BH |
426 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
427 | if (!channel) | |
428 | return NULL; | |
4642610c | 429 | |
7f967c01 BH |
430 | channel->efx = efx; |
431 | channel->channel = i; | |
432 | channel->type = &efx_default_channel_type; | |
4642610c | 433 | |
7f967c01 BH |
434 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
435 | tx_queue = &channel->tx_queue[j]; | |
436 | tx_queue->efx = efx; | |
437 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
438 | tx_queue->channel = channel; | |
439 | } | |
4642610c | 440 | |
7f967c01 BH |
441 | rx_queue = &channel->rx_queue; |
442 | rx_queue->efx = efx; | |
443 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
444 | (unsigned long)rx_queue); | |
4642610c | 445 | |
7f967c01 BH |
446 | return channel; |
447 | } | |
448 | ||
449 | /* Allocate and initialise a channel structure, copying parameters | |
450 | * (but not resources) from an old channel structure. | |
451 | */ | |
452 | static struct efx_channel * | |
453 | efx_copy_channel(const struct efx_channel *old_channel) | |
454 | { | |
455 | struct efx_channel *channel; | |
456 | struct efx_rx_queue *rx_queue; | |
457 | struct efx_tx_queue *tx_queue; | |
458 | int j; | |
4642610c | 459 | |
7f967c01 BH |
460 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
461 | if (!channel) | |
462 | return NULL; | |
463 | ||
464 | *channel = *old_channel; | |
465 | ||
466 | channel->napi_dev = NULL; | |
467 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 468 | |
7f967c01 BH |
469 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
470 | tx_queue = &channel->tx_queue[j]; | |
471 | if (tx_queue->channel) | |
4642610c | 472 | tx_queue->channel = channel; |
7f967c01 BH |
473 | tx_queue->buffer = NULL; |
474 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
475 | } |
476 | ||
4642610c | 477 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
478 | rx_queue->buffer = NULL; |
479 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
480 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
481 | (unsigned long)rx_queue); | |
482 | ||
483 | return channel; | |
484 | } | |
485 | ||
8ceee660 BH |
486 | static int efx_probe_channel(struct efx_channel *channel) |
487 | { | |
488 | struct efx_tx_queue *tx_queue; | |
489 | struct efx_rx_queue *rx_queue; | |
490 | int rc; | |
491 | ||
62776d03 BH |
492 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
493 | "creating channel %d\n", channel->channel); | |
8ceee660 | 494 | |
7f967c01 BH |
495 | rc = channel->type->pre_probe(channel); |
496 | if (rc) | |
497 | goto fail; | |
498 | ||
8ceee660 BH |
499 | rc = efx_probe_eventq(channel); |
500 | if (rc) | |
7f967c01 | 501 | goto fail; |
8ceee660 BH |
502 | |
503 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
504 | rc = efx_probe_tx_queue(tx_queue); | |
505 | if (rc) | |
7f967c01 | 506 | goto fail; |
8ceee660 BH |
507 | } |
508 | ||
509 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
510 | rc = efx_probe_rx_queue(rx_queue); | |
511 | if (rc) | |
7f967c01 | 512 | goto fail; |
8ceee660 BH |
513 | } |
514 | ||
8ceee660 BH |
515 | return 0; |
516 | ||
7f967c01 BH |
517 | fail: |
518 | efx_remove_channel(channel); | |
8ceee660 BH |
519 | return rc; |
520 | } | |
521 | ||
7f967c01 BH |
522 | static void |
523 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
524 | { | |
525 | struct efx_nic *efx = channel->efx; | |
526 | const char *type; | |
527 | int number; | |
528 | ||
529 | number = channel->channel; | |
530 | if (efx->tx_channel_offset == 0) { | |
531 | type = ""; | |
532 | } else if (channel->channel < efx->tx_channel_offset) { | |
533 | type = "-rx"; | |
534 | } else { | |
535 | type = "-tx"; | |
536 | number -= efx->tx_channel_offset; | |
537 | } | |
538 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
539 | } | |
8ceee660 | 540 | |
56536e9c BH |
541 | static void efx_set_channel_names(struct efx_nic *efx) |
542 | { | |
543 | struct efx_channel *channel; | |
56536e9c | 544 | |
7f967c01 BH |
545 | efx_for_each_channel(channel, efx) |
546 | channel->type->get_name(channel, | |
d8291187 BH |
547 | efx->msi_context[channel->channel].name, |
548 | sizeof(efx->msi_context[0].name)); | |
56536e9c BH |
549 | } |
550 | ||
4642610c BH |
551 | static int efx_probe_channels(struct efx_nic *efx) |
552 | { | |
553 | struct efx_channel *channel; | |
554 | int rc; | |
555 | ||
556 | /* Restart special buffer allocation */ | |
557 | efx->next_buffer_table = 0; | |
558 | ||
c92aaff1 BH |
559 | /* Probe channels in reverse, so that any 'extra' channels |
560 | * use the start of the buffer table. This allows the traffic | |
561 | * channels to be resized without moving them or wasting the | |
562 | * entries before them. | |
563 | */ | |
564 | efx_for_each_channel_rev(channel, efx) { | |
4642610c BH |
565 | rc = efx_probe_channel(channel); |
566 | if (rc) { | |
567 | netif_err(efx, probe, efx->net_dev, | |
568 | "failed to create channel %d\n", | |
569 | channel->channel); | |
570 | goto fail; | |
571 | } | |
572 | } | |
573 | efx_set_channel_names(efx); | |
574 | ||
575 | return 0; | |
576 | ||
577 | fail: | |
578 | efx_remove_channels(efx); | |
579 | return rc; | |
580 | } | |
581 | ||
8ceee660 BH |
582 | /* Channels are shutdown and reinitialised whilst the NIC is running |
583 | * to propagate configuration changes (mtu, checksum offload), or | |
584 | * to clear hardware error conditions | |
585 | */ | |
9f2cb71c | 586 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 | 587 | { |
85740cdf | 588 | bool old_rx_scatter = efx->rx_scatter; |
8ceee660 BH |
589 | struct efx_tx_queue *tx_queue; |
590 | struct efx_rx_queue *rx_queue; | |
591 | struct efx_channel *channel; | |
85740cdf | 592 | size_t rx_buf_len; |
8ceee660 | 593 | |
f7f13b0b BH |
594 | /* Calculate the rx buffer allocation parameters required to |
595 | * support the current MTU, including padding for header | |
596 | * alignment and overruns. | |
597 | */ | |
43a3739d | 598 | efx->rx_dma_len = (efx->rx_prefix_size + |
272baeeb BH |
599 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + |
600 | efx->type->rx_buffer_padding); | |
85740cdf | 601 | rx_buf_len = (sizeof(struct efx_rx_page_state) + |
2ec03014 | 602 | efx->rx_ip_align + efx->rx_dma_len); |
85740cdf | 603 | if (rx_buf_len <= PAGE_SIZE) { |
e8c68c0a | 604 | efx->rx_scatter = efx->type->always_rx_scatter; |
85740cdf | 605 | efx->rx_buffer_order = 0; |
85740cdf | 606 | } else if (efx->type->can_rx_scatter) { |
950c54df | 607 | BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES); |
85740cdf | 608 | BUILD_BUG_ON(sizeof(struct efx_rx_page_state) + |
950c54df BH |
609 | 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE, |
610 | EFX_RX_BUF_ALIGNMENT) > | |
611 | PAGE_SIZE); | |
85740cdf BH |
612 | efx->rx_scatter = true; |
613 | efx->rx_dma_len = EFX_RX_USR_BUF_SIZE; | |
614 | efx->rx_buffer_order = 0; | |
85740cdf BH |
615 | } else { |
616 | efx->rx_scatter = false; | |
617 | efx->rx_buffer_order = get_order(rx_buf_len); | |
85740cdf BH |
618 | } |
619 | ||
1648a23f DP |
620 | efx_rx_config_page_split(efx); |
621 | if (efx->rx_buffer_order) | |
622 | netif_dbg(efx, drv, efx->net_dev, | |
623 | "RX buf len=%u; page order=%u batch=%u\n", | |
624 | efx->rx_dma_len, efx->rx_buffer_order, | |
625 | efx->rx_pages_per_batch); | |
626 | else | |
627 | netif_dbg(efx, drv, efx->net_dev, | |
628 | "RX buf len=%u step=%u bpp=%u; page batch=%u\n", | |
629 | efx->rx_dma_len, efx->rx_page_buf_step, | |
630 | efx->rx_bufs_per_page, efx->rx_pages_per_batch); | |
2768935a | 631 | |
e8c68c0a | 632 | /* RX filters may also have scatter-enabled flags */ |
85740cdf | 633 | if (efx->rx_scatter != old_rx_scatter) |
add72477 | 634 | efx->type->filter_update_rx_scatter(efx); |
8ceee660 | 635 | |
14bf718f BH |
636 | /* We must keep at least one descriptor in a TX ring empty. |
637 | * We could avoid this when the queue size does not exactly | |
638 | * match the hardware ring size, but it's not that important. | |
639 | * Therefore we stop the queue when one more skb might fill | |
640 | * the ring completely. We wake it when half way back to | |
641 | * empty. | |
642 | */ | |
643 | efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); | |
644 | efx->txq_wake_thresh = efx->txq_stop_thresh / 2; | |
645 | ||
8ceee660 BH |
646 | /* Initialise the channels */ |
647 | efx_for_each_channel(channel, efx) { | |
3881d8ab | 648 | efx_for_each_channel_tx_queue(tx_queue, channel) { |
bc3c90a2 | 649 | efx_init_tx_queue(tx_queue); |
3881d8ab AR |
650 | atomic_inc(&efx->active_queues); |
651 | } | |
8ceee660 | 652 | |
9f2cb71c | 653 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 654 | efx_init_rx_queue(rx_queue); |
3881d8ab | 655 | atomic_inc(&efx->active_queues); |
cce28794 JC |
656 | efx_stop_eventq(channel); |
657 | efx_fast_push_rx_descriptors(rx_queue, false); | |
658 | efx_start_eventq(channel); | |
9f2cb71c | 659 | } |
8ceee660 | 660 | |
85740cdf | 661 | WARN_ON(channel->rx_pkt_n_frags); |
8ceee660 | 662 | } |
8ceee660 | 663 | |
2ea4dc28 AR |
664 | efx_ptp_start_datapath(efx); |
665 | ||
9f2cb71c BH |
666 | if (netif_device_present(efx->net_dev)) |
667 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
668 | } |
669 | ||
9f2cb71c | 670 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
671 | { |
672 | struct efx_channel *channel; | |
673 | struct efx_tx_queue *tx_queue; | |
674 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 675 | int rc; |
8ceee660 BH |
676 | |
677 | EFX_ASSERT_RESET_SERIALISED(efx); | |
678 | BUG_ON(efx->port_enabled); | |
679 | ||
2ea4dc28 AR |
680 | efx_ptp_stop_datapath(efx); |
681 | ||
d8aec745 BH |
682 | /* Stop RX refill */ |
683 | efx_for_each_channel(channel, efx) { | |
684 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
685 | rx_queue->refill_enabled = false; | |
686 | } | |
687 | ||
8ceee660 | 688 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
689 | /* RX packet processing is pipelined, so wait for the |
690 | * NAPI handler to complete. At least event queue 0 | |
691 | * might be kept active by non-data events, so don't | |
692 | * use napi_synchronize() but actually disable NAPI | |
693 | * temporarily. | |
694 | */ | |
695 | if (efx_channel_has_rx_queue(channel)) { | |
696 | efx_stop_eventq(channel); | |
697 | efx_start_eventq(channel); | |
698 | } | |
e42c3d85 | 699 | } |
8ceee660 | 700 | |
e42c3d85 BH |
701 | rc = efx->type->fini_dmaq(efx); |
702 | if (rc && EFX_WORKAROUND_7803(efx)) { | |
703 | /* Schedule a reset to recover from the flush failure. The | |
704 | * descriptor caches reference memory we're about to free, | |
705 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
706 | * the MACs because of the pending reset. | |
707 | */ | |
708 | netif_err(efx, drv, efx->net_dev, | |
709 | "Resetting to recover from flush failure\n"); | |
710 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
711 | } else if (rc) { | |
712 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); | |
713 | } else { | |
714 | netif_dbg(efx, drv, efx->net_dev, | |
715 | "successfully flushed all queues\n"); | |
716 | } | |
717 | ||
718 | efx_for_each_channel(channel, efx) { | |
8ceee660 BH |
719 | efx_for_each_channel_rx_queue(rx_queue, channel) |
720 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 721 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 722 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
723 | } |
724 | } | |
725 | ||
726 | static void efx_remove_channel(struct efx_channel *channel) | |
727 | { | |
728 | struct efx_tx_queue *tx_queue; | |
729 | struct efx_rx_queue *rx_queue; | |
730 | ||
62776d03 BH |
731 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
732 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
733 | |
734 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
735 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 736 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
737 | efx_remove_tx_queue(tx_queue); |
738 | efx_remove_eventq(channel); | |
c31e5f9f | 739 | channel->type->post_remove(channel); |
8ceee660 BH |
740 | } |
741 | ||
4642610c BH |
742 | static void efx_remove_channels(struct efx_nic *efx) |
743 | { | |
744 | struct efx_channel *channel; | |
745 | ||
746 | efx_for_each_channel(channel, efx) | |
747 | efx_remove_channel(channel); | |
748 | } | |
749 | ||
750 | int | |
751 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
752 | { | |
753 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
754 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 | 755 | unsigned i, next_buffer_table = 0; |
261e4d96 | 756 | int rc, rc2; |
8b7325b4 BH |
757 | |
758 | rc = efx_check_disabled(efx); | |
759 | if (rc) | |
760 | return rc; | |
7f967c01 BH |
761 | |
762 | /* Not all channels should be reallocated. We must avoid | |
763 | * reallocating their buffer table entries. | |
764 | */ | |
765 | efx_for_each_channel(channel, efx) { | |
766 | struct efx_rx_queue *rx_queue; | |
767 | struct efx_tx_queue *tx_queue; | |
768 | ||
769 | if (channel->type->copy) | |
770 | continue; | |
771 | next_buffer_table = max(next_buffer_table, | |
772 | channel->eventq.index + | |
773 | channel->eventq.entries); | |
774 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
775 | next_buffer_table = max(next_buffer_table, | |
776 | rx_queue->rxd.index + | |
777 | rx_queue->rxd.entries); | |
778 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
779 | next_buffer_table = max(next_buffer_table, | |
780 | tx_queue->txd.index + | |
781 | tx_queue->txd.entries); | |
782 | } | |
4642610c | 783 | |
29c69a48 | 784 | efx_device_detach_sync(efx); |
4642610c | 785 | efx_stop_all(efx); |
d8291187 | 786 | efx_soft_disable_interrupts(efx); |
4642610c | 787 | |
7f967c01 | 788 | /* Clone channels (where possible) */ |
4642610c BH |
789 | memset(other_channel, 0, sizeof(other_channel)); |
790 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
791 | channel = efx->channel[i]; |
792 | if (channel->type->copy) | |
793 | channel = channel->type->copy(channel); | |
4642610c BH |
794 | if (!channel) { |
795 | rc = -ENOMEM; | |
796 | goto out; | |
797 | } | |
798 | other_channel[i] = channel; | |
799 | } | |
800 | ||
801 | /* Swap entry counts and channel pointers */ | |
802 | old_rxq_entries = efx->rxq_entries; | |
803 | old_txq_entries = efx->txq_entries; | |
804 | efx->rxq_entries = rxq_entries; | |
805 | efx->txq_entries = txq_entries; | |
806 | for (i = 0; i < efx->n_channels; i++) { | |
807 | channel = efx->channel[i]; | |
808 | efx->channel[i] = other_channel[i]; | |
809 | other_channel[i] = channel; | |
810 | } | |
811 | ||
7f967c01 BH |
812 | /* Restart buffer table allocation */ |
813 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 814 | |
e8f14992 | 815 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
816 | channel = efx->channel[i]; |
817 | if (!channel->type->copy) | |
818 | continue; | |
819 | rc = efx_probe_channel(channel); | |
820 | if (rc) | |
821 | goto rollback; | |
822 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 823 | } |
7f967c01 | 824 | |
4642610c | 825 | out: |
7f967c01 BH |
826 | /* Destroy unused channel structures */ |
827 | for (i = 0; i < efx->n_channels; i++) { | |
828 | channel = other_channel[i]; | |
829 | if (channel && channel->type->copy) { | |
830 | efx_fini_napi_channel(channel); | |
831 | efx_remove_channel(channel); | |
832 | kfree(channel); | |
833 | } | |
834 | } | |
4642610c | 835 | |
261e4d96 JC |
836 | rc2 = efx_soft_enable_interrupts(efx); |
837 | if (rc2) { | |
838 | rc = rc ? rc : rc2; | |
839 | netif_err(efx, drv, efx->net_dev, | |
840 | "unable to restart interrupts on channel reallocation\n"); | |
841 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
842 | } else { | |
843 | efx_start_all(efx); | |
844 | netif_device_attach(efx->net_dev); | |
845 | } | |
4642610c BH |
846 | return rc; |
847 | ||
848 | rollback: | |
849 | /* Swap back */ | |
850 | efx->rxq_entries = old_rxq_entries; | |
851 | efx->txq_entries = old_txq_entries; | |
852 | for (i = 0; i < efx->n_channels; i++) { | |
853 | channel = efx->channel[i]; | |
854 | efx->channel[i] = other_channel[i]; | |
855 | other_channel[i] = channel; | |
856 | } | |
857 | goto out; | |
858 | } | |
859 | ||
90d683af | 860 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 861 | { |
90d683af | 862 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
863 | } |
864 | ||
7f967c01 BH |
865 | static const struct efx_channel_type efx_default_channel_type = { |
866 | .pre_probe = efx_channel_dummy_op_int, | |
c31e5f9f | 867 | .post_remove = efx_channel_dummy_op_void, |
7f967c01 BH |
868 | .get_name = efx_get_channel_name, |
869 | .copy = efx_copy_channel, | |
870 | .keep_eventq = false, | |
871 | }; | |
872 | ||
873 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
874 | { | |
875 | return 0; | |
876 | } | |
877 | ||
c31e5f9f SH |
878 | void efx_channel_dummy_op_void(struct efx_channel *channel) |
879 | { | |
880 | } | |
881 | ||
8ceee660 BH |
882 | /************************************************************************** |
883 | * | |
884 | * Port handling | |
885 | * | |
886 | **************************************************************************/ | |
887 | ||
888 | /* This ensures that the kernel is kept informed (via | |
889 | * netif_carrier_on/off) of the link status, and also maintains the | |
890 | * link status's stop on the port's TX queue. | |
891 | */ | |
fdaa9aed | 892 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 893 | { |
eb50c0d6 BH |
894 | struct efx_link_state *link_state = &efx->link_state; |
895 | ||
8ceee660 BH |
896 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
897 | * that no events are triggered between unregister_netdev() and the | |
898 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
899 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
900 | if (!netif_running(efx->net_dev)) | |
901 | return; | |
902 | ||
eb50c0d6 | 903 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
904 | efx->n_link_state_changes++; |
905 | ||
eb50c0d6 | 906 | if (link_state->up) |
8ceee660 BH |
907 | netif_carrier_on(efx->net_dev); |
908 | else | |
909 | netif_carrier_off(efx->net_dev); | |
910 | } | |
911 | ||
912 | /* Status message for kernel log */ | |
2aa9ef11 | 913 | if (link_state->up) |
62776d03 | 914 | netif_info(efx, link, efx->net_dev, |
964e6135 | 915 | "link up at %uMbps %s-duplex (MTU %d)\n", |
62776d03 | 916 | link_state->speed, link_state->fd ? "full" : "half", |
964e6135 | 917 | efx->net_dev->mtu); |
2aa9ef11 | 918 | else |
62776d03 | 919 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
920 | } |
921 | ||
d3245b28 BH |
922 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
923 | { | |
924 | efx->link_advertising = advertising; | |
925 | if (advertising) { | |
926 | if (advertising & ADVERTISED_Pause) | |
927 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
928 | else | |
929 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
930 | if (advertising & ADVERTISED_Asym_Pause) | |
931 | efx->wanted_fc ^= EFX_FC_TX; | |
932 | } | |
933 | } | |
934 | ||
b5626946 | 935 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
936 | { |
937 | efx->wanted_fc = wanted_fc; | |
938 | if (efx->link_advertising) { | |
939 | if (wanted_fc & EFX_FC_RX) | |
940 | efx->link_advertising |= (ADVERTISED_Pause | | |
941 | ADVERTISED_Asym_Pause); | |
942 | else | |
943 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
944 | ADVERTISED_Asym_Pause); | |
945 | if (wanted_fc & EFX_FC_TX) | |
946 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
947 | } | |
948 | } | |
949 | ||
115122af BH |
950 | static void efx_fini_port(struct efx_nic *efx); |
951 | ||
d3245b28 BH |
952 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
953 | * the MAC appropriately. All other PHY configuration changes are pushed | |
954 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
955 | * through efx_monitor(). | |
956 | * | |
957 | * Callers must hold the mac_lock | |
958 | */ | |
959 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 960 | { |
d3245b28 BH |
961 | enum efx_phy_mode phy_mode; |
962 | int rc; | |
8ceee660 | 963 | |
d3245b28 | 964 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 965 | |
d3245b28 BH |
966 | /* Disable PHY transmit in mac level loopbacks */ |
967 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
968 | if (LOOPBACK_INTERNAL(efx)) |
969 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
970 | else | |
971 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 972 | |
d3245b28 | 973 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 974 | |
d3245b28 BH |
975 | if (rc) |
976 | efx->phy_mode = phy_mode; | |
177dfcd8 | 977 | |
d3245b28 | 978 | return rc; |
8ceee660 BH |
979 | } |
980 | ||
981 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
982 | * disabled. */ | |
d3245b28 | 983 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 984 | { |
d3245b28 BH |
985 | int rc; |
986 | ||
8ceee660 BH |
987 | EFX_ASSERT_RESET_SERIALISED(efx); |
988 | ||
989 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 990 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 991 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
992 | |
993 | return rc; | |
8ceee660 BH |
994 | } |
995 | ||
8be4f3e6 BH |
996 | /* Asynchronous work item for changing MAC promiscuity and multicast |
997 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
998 | * MAC directly. */ | |
766ca0fa BH |
999 | static void efx_mac_work(struct work_struct *data) |
1000 | { | |
1001 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
1002 | ||
1003 | mutex_lock(&efx->mac_lock); | |
30b81cda | 1004 | if (efx->port_enabled) |
710b208d | 1005 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
1006 | mutex_unlock(&efx->mac_lock); |
1007 | } | |
1008 | ||
8ceee660 BH |
1009 | static int efx_probe_port(struct efx_nic *efx) |
1010 | { | |
1011 | int rc; | |
1012 | ||
62776d03 | 1013 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 1014 | |
ff3b00a0 SH |
1015 | if (phy_flash_cfg) |
1016 | efx->phy_mode = PHY_MODE_SPECIAL; | |
1017 | ||
ef2b90ee BH |
1018 | /* Connect up MAC/PHY operations table */ |
1019 | rc = efx->type->probe_port(efx); | |
8ceee660 | 1020 | if (rc) |
e42de262 | 1021 | return rc; |
8ceee660 | 1022 | |
e332bcb3 | 1023 | /* Initialise MAC address to permanent address */ |
cd84ff4d | 1024 | ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr); |
8ceee660 BH |
1025 | |
1026 | return 0; | |
8ceee660 BH |
1027 | } |
1028 | ||
1029 | static int efx_init_port(struct efx_nic *efx) | |
1030 | { | |
1031 | int rc; | |
1032 | ||
62776d03 | 1033 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 1034 | |
1dfc5cea BH |
1035 | mutex_lock(&efx->mac_lock); |
1036 | ||
177dfcd8 | 1037 | rc = efx->phy_op->init(efx); |
8ceee660 | 1038 | if (rc) |
1dfc5cea | 1039 | goto fail1; |
8ceee660 | 1040 | |
dc8cfa55 | 1041 | efx->port_initialized = true; |
1dfc5cea | 1042 | |
d3245b28 BH |
1043 | /* Reconfigure the MAC before creating dma queues (required for |
1044 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 1045 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1046 | |
1047 | /* Ensure the PHY advertises the correct flow control settings */ | |
1048 | rc = efx->phy_op->reconfigure(efx); | |
1049 | if (rc) | |
1050 | goto fail2; | |
1051 | ||
1dfc5cea | 1052 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1053 | return 0; |
177dfcd8 | 1054 | |
1dfc5cea | 1055 | fail2: |
177dfcd8 | 1056 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1057 | fail1: |
1058 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1059 | return rc; |
8ceee660 BH |
1060 | } |
1061 | ||
8ceee660 BH |
1062 | static void efx_start_port(struct efx_nic *efx) |
1063 | { | |
62776d03 | 1064 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1065 | BUG_ON(efx->port_enabled); |
1066 | ||
1067 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1068 | efx->port_enabled = true; |
8be4f3e6 | 1069 | |
d615c039 | 1070 | /* Ensure MAC ingress/egress is enabled */ |
710b208d | 1071 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 1072 | |
8ceee660 BH |
1073 | mutex_unlock(&efx->mac_lock); |
1074 | } | |
1075 | ||
d615c039 BH |
1076 | /* Cancel work for MAC reconfiguration, periodic hardware monitoring |
1077 | * and the async self-test, wait for them to finish and prevent them | |
1078 | * being scheduled again. This doesn't cover online resets, which | |
1079 | * should only be cancelled when removing the device. | |
1080 | */ | |
8ceee660 BH |
1081 | static void efx_stop_port(struct efx_nic *efx) |
1082 | { | |
62776d03 | 1083 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 | 1084 | |
d615c039 BH |
1085 | EFX_ASSERT_RESET_SERIALISED(efx); |
1086 | ||
8ceee660 | 1087 | mutex_lock(&efx->mac_lock); |
dc8cfa55 | 1088 | efx->port_enabled = false; |
8ceee660 BH |
1089 | mutex_unlock(&efx->mac_lock); |
1090 | ||
1091 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1092 | netif_addr_lock_bh(efx->net_dev); |
1093 | netif_addr_unlock_bh(efx->net_dev); | |
d615c039 BH |
1094 | |
1095 | cancel_delayed_work_sync(&efx->monitor_work); | |
1096 | efx_selftest_async_cancel(efx); | |
1097 | cancel_work_sync(&efx->mac_work); | |
8ceee660 BH |
1098 | } |
1099 | ||
1100 | static void efx_fini_port(struct efx_nic *efx) | |
1101 | { | |
62776d03 | 1102 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1103 | |
1104 | if (!efx->port_initialized) | |
1105 | return; | |
1106 | ||
177dfcd8 | 1107 | efx->phy_op->fini(efx); |
dc8cfa55 | 1108 | efx->port_initialized = false; |
8ceee660 | 1109 | |
eb50c0d6 | 1110 | efx->link_state.up = false; |
8ceee660 BH |
1111 | efx_link_status_changed(efx); |
1112 | } | |
1113 | ||
1114 | static void efx_remove_port(struct efx_nic *efx) | |
1115 | { | |
62776d03 | 1116 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1117 | |
ef2b90ee | 1118 | efx->type->remove_port(efx); |
8ceee660 BH |
1119 | } |
1120 | ||
1121 | /************************************************************************** | |
1122 | * | |
1123 | * NIC handling | |
1124 | * | |
1125 | **************************************************************************/ | |
1126 | ||
0bcf4a64 BH |
1127 | static LIST_HEAD(efx_primary_list); |
1128 | static LIST_HEAD(efx_unassociated_list); | |
1129 | ||
1130 | static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right) | |
1131 | { | |
1132 | return left->type == right->type && | |
1133 | left->vpd_sn && right->vpd_sn && | |
1134 | !strcmp(left->vpd_sn, right->vpd_sn); | |
1135 | } | |
1136 | ||
1137 | static void efx_associate(struct efx_nic *efx) | |
1138 | { | |
1139 | struct efx_nic *other, *next; | |
1140 | ||
1141 | if (efx->primary == efx) { | |
1142 | /* Adding primary function; look for secondaries */ | |
1143 | ||
1144 | netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n"); | |
1145 | list_add_tail(&efx->node, &efx_primary_list); | |
1146 | ||
1147 | list_for_each_entry_safe(other, next, &efx_unassociated_list, | |
1148 | node) { | |
1149 | if (efx_same_controller(efx, other)) { | |
1150 | list_del(&other->node); | |
1151 | netif_dbg(other, probe, other->net_dev, | |
1152 | "moving to secondary list of %s %s\n", | |
1153 | pci_name(efx->pci_dev), | |
1154 | efx->net_dev->name); | |
1155 | list_add_tail(&other->node, | |
1156 | &efx->secondary_list); | |
1157 | other->primary = efx; | |
1158 | } | |
1159 | } | |
1160 | } else { | |
1161 | /* Adding secondary function; look for primary */ | |
1162 | ||
1163 | list_for_each_entry(other, &efx_primary_list, node) { | |
1164 | if (efx_same_controller(efx, other)) { | |
1165 | netif_dbg(efx, probe, efx->net_dev, | |
1166 | "adding to secondary list of %s %s\n", | |
1167 | pci_name(other->pci_dev), | |
1168 | other->net_dev->name); | |
1169 | list_add_tail(&efx->node, | |
1170 | &other->secondary_list); | |
1171 | efx->primary = other; | |
1172 | return; | |
1173 | } | |
1174 | } | |
1175 | ||
1176 | netif_dbg(efx, probe, efx->net_dev, | |
1177 | "adding to unassociated list\n"); | |
1178 | list_add_tail(&efx->node, &efx_unassociated_list); | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | static void efx_dissociate(struct efx_nic *efx) | |
1183 | { | |
1184 | struct efx_nic *other, *next; | |
1185 | ||
1186 | list_del(&efx->node); | |
1187 | efx->primary = NULL; | |
1188 | ||
1189 | list_for_each_entry_safe(other, next, &efx->secondary_list, node) { | |
1190 | list_del(&other->node); | |
1191 | netif_dbg(other, probe, other->net_dev, | |
1192 | "moving to unassociated list\n"); | |
1193 | list_add_tail(&other->node, &efx_unassociated_list); | |
1194 | other->primary = NULL; | |
1195 | } | |
1196 | } | |
1197 | ||
8ceee660 BH |
1198 | /* This configures the PCI device to enable I/O and DMA. */ |
1199 | static int efx_init_io(struct efx_nic *efx) | |
1200 | { | |
1201 | struct pci_dev *pci_dev = efx->pci_dev; | |
1202 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
b105798f | 1203 | unsigned int mem_map_size = efx->type->mem_map_size(efx); |
8ceee660 BH |
1204 | int rc; |
1205 | ||
62776d03 | 1206 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1207 | |
1208 | rc = pci_enable_device(pci_dev); | |
1209 | if (rc) { | |
62776d03 BH |
1210 | netif_err(efx, probe, efx->net_dev, |
1211 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1212 | goto fail1; |
1213 | } | |
1214 | ||
1215 | pci_set_master(pci_dev); | |
1216 | ||
1217 | /* Set the PCI DMA mask. Try all possibilities from our | |
1218 | * genuine mask down to 32 bits, because some architectures | |
1219 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1220 | * masks event though they reject 46 bit masks. | |
1221 | */ | |
1222 | while (dma_mask > 0x7fffffffUL) { | |
0e33d870 | 1223 | if (dma_supported(&pci_dev->dev, dma_mask)) { |
9663deda | 1224 | rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask); |
e9e01846 BH |
1225 | if (rc == 0) |
1226 | break; | |
1227 | } | |
8ceee660 BH |
1228 | dma_mask >>= 1; |
1229 | } | |
1230 | if (rc) { | |
62776d03 BH |
1231 | netif_err(efx, probe, efx->net_dev, |
1232 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1233 | goto fail2; |
1234 | } | |
62776d03 BH |
1235 | netif_dbg(efx, probe, efx->net_dev, |
1236 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 | 1237 | |
dc803df8 BH |
1238 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1239 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1240 | if (rc) { |
62776d03 BH |
1241 | netif_err(efx, probe, efx->net_dev, |
1242 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1243 | rc = -EIO; |
1244 | goto fail3; | |
1245 | } | |
b105798f | 1246 | efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); |
8ceee660 | 1247 | if (!efx->membase) { |
62776d03 BH |
1248 | netif_err(efx, probe, efx->net_dev, |
1249 | "could not map memory BAR at %llx+%x\n", | |
b105798f | 1250 | (unsigned long long)efx->membase_phys, mem_map_size); |
8ceee660 BH |
1251 | rc = -ENOMEM; |
1252 | goto fail4; | |
1253 | } | |
62776d03 BH |
1254 | netif_dbg(efx, probe, efx->net_dev, |
1255 | "memory BAR at %llx+%x (virtual %p)\n", | |
b105798f BH |
1256 | (unsigned long long)efx->membase_phys, mem_map_size, |
1257 | efx->membase); | |
8ceee660 BH |
1258 | |
1259 | return 0; | |
1260 | ||
1261 | fail4: | |
dc803df8 | 1262 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1263 | fail3: |
2c118e0f | 1264 | efx->membase_phys = 0; |
8ceee660 BH |
1265 | fail2: |
1266 | pci_disable_device(efx->pci_dev); | |
1267 | fail1: | |
1268 | return rc; | |
1269 | } | |
1270 | ||
1271 | static void efx_fini_io(struct efx_nic *efx) | |
1272 | { | |
62776d03 | 1273 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1274 | |
1275 | if (efx->membase) { | |
1276 | iounmap(efx->membase); | |
1277 | efx->membase = NULL; | |
1278 | } | |
1279 | ||
1280 | if (efx->membase_phys) { | |
dc803df8 | 1281 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1282 | efx->membase_phys = 0; |
8ceee660 BH |
1283 | } |
1284 | ||
1285 | pci_disable_device(efx->pci_dev); | |
1286 | } | |
1287 | ||
a9a52506 | 1288 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1289 | { |
cdb08f8f | 1290 | cpumask_var_t thread_mask; |
a16e5b24 | 1291 | unsigned int count; |
46123d04 | 1292 | int cpu; |
5b874e25 | 1293 | |
cd2d5b52 BH |
1294 | if (rss_cpus) { |
1295 | count = rss_cpus; | |
1296 | } else { | |
1297 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1298 | netif_warn(efx, probe, efx->net_dev, | |
1299 | "RSS disabled due to allocation failure\n"); | |
1300 | return 1; | |
1301 | } | |
46123d04 | 1302 | |
cd2d5b52 BH |
1303 | count = 0; |
1304 | for_each_online_cpu(cpu) { | |
1305 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1306 | ++count; | |
1307 | cpumask_or(thread_mask, thread_mask, | |
1308 | topology_thread_cpumask(cpu)); | |
1309 | } | |
1310 | } | |
1311 | ||
1312 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1313 | } |
1314 | ||
cd2d5b52 BH |
1315 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1316 | * table entries that are inaccessible to VFs | |
1317 | */ | |
7fa8d547 SS |
1318 | #ifdef CONFIG_SFC_SRIOV |
1319 | if (efx->type->sriov_wanted) { | |
1320 | if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1321 | count > efx_vf_size(efx)) { | |
1322 | netif_warn(efx, probe, efx->net_dev, | |
1323 | "Reducing number of RSS channels from %u to %u for " | |
1324 | "VF support. Increase vf-msix-limit to use more " | |
1325 | "channels on the PF.\n", | |
1326 | count, efx_vf_size(efx)); | |
1327 | count = efx_vf_size(efx); | |
1328 | } | |
46123d04 | 1329 | } |
7fa8d547 | 1330 | #endif |
46123d04 BH |
1331 | |
1332 | return count; | |
1333 | } | |
1334 | ||
1335 | /* Probe the number and type of interrupts we are able to obtain, and | |
1336 | * the resulting numbers of channels and RX queues. | |
1337 | */ | |
64d8ad6d | 1338 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1339 | { |
7f967c01 BH |
1340 | unsigned int extra_channels = 0; |
1341 | unsigned int i, j; | |
a16e5b24 | 1342 | int rc; |
8ceee660 | 1343 | |
7f967c01 BH |
1344 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1345 | if (efx->extra_channel_type[i]) | |
1346 | ++extra_channels; | |
1347 | ||
8ceee660 | 1348 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1349 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1350 | unsigned int n_channels; |
aa6ef27e | 1351 | |
a9a52506 | 1352 | n_channels = efx_wanted_parallelism(efx); |
a4900ac9 BH |
1353 | if (separate_tx_channels) |
1354 | n_channels *= 2; | |
7f967c01 | 1355 | n_channels += extra_channels; |
b105798f | 1356 | n_channels = min(n_channels, efx->max_channels); |
8ceee660 | 1357 | |
a4900ac9 | 1358 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1359 | xentries[i].entry = i; |
184603d8 AG |
1360 | rc = pci_enable_msix_range(efx->pci_dev, |
1361 | xentries, 1, n_channels); | |
1362 | if (rc < 0) { | |
1363 | /* Fall back to single channel MSI */ | |
1364 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
1365 | netif_err(efx, drv, efx->net_dev, | |
1366 | "could not enable MSI-X\n"); | |
1367 | } else if (rc < n_channels) { | |
62776d03 BH |
1368 | netif_err(efx, drv, efx->net_dev, |
1369 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1370 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1371 | netif_err(efx, drv, efx->net_dev, |
1372 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 | 1373 | n_channels = rc; |
8ceee660 BH |
1374 | } |
1375 | ||
184603d8 | 1376 | if (rc > 0) { |
a4900ac9 | 1377 | efx->n_channels = n_channels; |
7f967c01 BH |
1378 | if (n_channels > extra_channels) |
1379 | n_channels -= extra_channels; | |
a4900ac9 | 1380 | if (separate_tx_channels) { |
7f967c01 BH |
1381 | efx->n_tx_channels = max(n_channels / 2, 1U); |
1382 | efx->n_rx_channels = max(n_channels - | |
1383 | efx->n_tx_channels, | |
1384 | 1U); | |
a4900ac9 | 1385 | } else { |
7f967c01 BH |
1386 | efx->n_tx_channels = n_channels; |
1387 | efx->n_rx_channels = n_channels; | |
a4900ac9 | 1388 | } |
7f967c01 | 1389 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1390 | efx_get_channel(efx, i)->irq = |
1391 | xentries[i].vector; | |
8ceee660 BH |
1392 | } |
1393 | } | |
1394 | ||
1395 | /* Try single interrupt MSI */ | |
1396 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1397 | efx->n_channels = 1; |
a4900ac9 BH |
1398 | efx->n_rx_channels = 1; |
1399 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1400 | rc = pci_enable_msi(efx->pci_dev); |
1401 | if (rc == 0) { | |
f7d12cdc | 1402 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1403 | } else { |
62776d03 BH |
1404 | netif_err(efx, drv, efx->net_dev, |
1405 | "could not enable MSI\n"); | |
8ceee660 BH |
1406 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1407 | } | |
1408 | } | |
1409 | ||
1410 | /* Assume legacy interrupts */ | |
1411 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1412 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1413 | efx->n_rx_channels = 1; |
1414 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1415 | efx->legacy_irq = efx->pci_dev->irq; |
1416 | } | |
64d8ad6d | 1417 | |
7f967c01 BH |
1418 | /* Assign extra channels if possible */ |
1419 | j = efx->n_channels; | |
1420 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1421 | if (!efx->extra_channel_type[i]) | |
1422 | continue; | |
1423 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1424 | efx->n_channels <= extra_channels) { | |
1425 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1426 | } else { | |
1427 | --j; | |
1428 | efx_get_channel(efx, j)->type = | |
1429 | efx->extra_channel_type[i]; | |
1430 | } | |
1431 | } | |
1432 | ||
cd2d5b52 | 1433 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
7fa8d547 SS |
1434 | #ifdef CONFIG_SFC_SRIOV |
1435 | if (efx->type->sriov_wanted) { | |
1436 | efx->rss_spread = ((efx->n_rx_channels > 1 || | |
1437 | !efx->type->sriov_wanted(efx)) ? | |
1438 | efx->n_rx_channels : efx_vf_size(efx)); | |
1439 | return 0; | |
1440 | } | |
1441 | #endif | |
1442 | efx->rss_spread = efx->n_rx_channels; | |
64d8ad6d | 1443 | return 0; |
8ceee660 BH |
1444 | } |
1445 | ||
261e4d96 | 1446 | static int efx_soft_enable_interrupts(struct efx_nic *efx) |
9f2cb71c | 1447 | { |
261e4d96 JC |
1448 | struct efx_channel *channel, *end_channel; |
1449 | int rc; | |
9f2cb71c | 1450 | |
8b7325b4 BH |
1451 | BUG_ON(efx->state == STATE_DISABLED); |
1452 | ||
d8291187 BH |
1453 | efx->irq_soft_enabled = true; |
1454 | smp_wmb(); | |
9f2cb71c BH |
1455 | |
1456 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1457 | if (!channel->type->keep_eventq) { |
1458 | rc = efx_init_eventq(channel); | |
1459 | if (rc) | |
1460 | goto fail; | |
1461 | } | |
9f2cb71c BH |
1462 | efx_start_eventq(channel); |
1463 | } | |
1464 | ||
1465 | efx_mcdi_mode_event(efx); | |
261e4d96 JC |
1466 | |
1467 | return 0; | |
1468 | fail: | |
1469 | end_channel = channel; | |
1470 | efx_for_each_channel(channel, efx) { | |
1471 | if (channel == end_channel) | |
1472 | break; | |
1473 | efx_stop_eventq(channel); | |
1474 | if (!channel->type->keep_eventq) | |
1475 | efx_fini_eventq(channel); | |
1476 | } | |
1477 | ||
1478 | return rc; | |
9f2cb71c BH |
1479 | } |
1480 | ||
d8291187 | 1481 | static void efx_soft_disable_interrupts(struct efx_nic *efx) |
9f2cb71c BH |
1482 | { |
1483 | struct efx_channel *channel; | |
1484 | ||
8b7325b4 BH |
1485 | if (efx->state == STATE_DISABLED) |
1486 | return; | |
1487 | ||
9f2cb71c BH |
1488 | efx_mcdi_mode_poll(efx); |
1489 | ||
d8291187 BH |
1490 | efx->irq_soft_enabled = false; |
1491 | smp_wmb(); | |
1492 | ||
1493 | if (efx->legacy_irq) | |
9f2cb71c | 1494 | synchronize_irq(efx->legacy_irq); |
9f2cb71c BH |
1495 | |
1496 | efx_for_each_channel(channel, efx) { | |
1497 | if (channel->irq) | |
1498 | synchronize_irq(channel->irq); | |
1499 | ||
1500 | efx_stop_eventq(channel); | |
d8291187 | 1501 | if (!channel->type->keep_eventq) |
7f967c01 | 1502 | efx_fini_eventq(channel); |
9f2cb71c | 1503 | } |
cade715f BH |
1504 | |
1505 | /* Flush the asynchronous MCDI request queue */ | |
1506 | efx_mcdi_flush_async(efx); | |
9f2cb71c BH |
1507 | } |
1508 | ||
261e4d96 | 1509 | static int efx_enable_interrupts(struct efx_nic *efx) |
d8291187 | 1510 | { |
261e4d96 JC |
1511 | struct efx_channel *channel, *end_channel; |
1512 | int rc; | |
d8291187 BH |
1513 | |
1514 | BUG_ON(efx->state == STATE_DISABLED); | |
1515 | ||
1516 | if (efx->eeh_disabled_legacy_irq) { | |
1517 | enable_irq(efx->legacy_irq); | |
1518 | efx->eeh_disabled_legacy_irq = false; | |
1519 | } | |
1520 | ||
86094f7f | 1521 | efx->type->irq_enable_master(efx); |
d8291187 BH |
1522 | |
1523 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1524 | if (channel->type->keep_eventq) { |
1525 | rc = efx_init_eventq(channel); | |
1526 | if (rc) | |
1527 | goto fail; | |
1528 | } | |
1529 | } | |
1530 | ||
1531 | rc = efx_soft_enable_interrupts(efx); | |
1532 | if (rc) | |
1533 | goto fail; | |
1534 | ||
1535 | return 0; | |
1536 | ||
1537 | fail: | |
1538 | end_channel = channel; | |
1539 | efx_for_each_channel(channel, efx) { | |
1540 | if (channel == end_channel) | |
1541 | break; | |
d8291187 | 1542 | if (channel->type->keep_eventq) |
261e4d96 | 1543 | efx_fini_eventq(channel); |
d8291187 BH |
1544 | } |
1545 | ||
261e4d96 JC |
1546 | efx->type->irq_disable_non_ev(efx); |
1547 | ||
1548 | return rc; | |
d8291187 BH |
1549 | } |
1550 | ||
1551 | static void efx_disable_interrupts(struct efx_nic *efx) | |
1552 | { | |
1553 | struct efx_channel *channel; | |
1554 | ||
1555 | efx_soft_disable_interrupts(efx); | |
1556 | ||
1557 | efx_for_each_channel(channel, efx) { | |
1558 | if (channel->type->keep_eventq) | |
1559 | efx_fini_eventq(channel); | |
1560 | } | |
1561 | ||
86094f7f | 1562 | efx->type->irq_disable_non_ev(efx); |
d8291187 BH |
1563 | } |
1564 | ||
8ceee660 BH |
1565 | static void efx_remove_interrupts(struct efx_nic *efx) |
1566 | { | |
1567 | struct efx_channel *channel; | |
1568 | ||
1569 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1570 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1571 | channel->irq = 0; |
1572 | pci_disable_msi(efx->pci_dev); | |
1573 | pci_disable_msix(efx->pci_dev); | |
1574 | ||
1575 | /* Remove legacy interrupt */ | |
1576 | efx->legacy_irq = 0; | |
1577 | } | |
1578 | ||
8831da7b | 1579 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1580 | { |
602a5322 BH |
1581 | struct efx_channel *channel; |
1582 | struct efx_tx_queue *tx_queue; | |
1583 | ||
97653431 | 1584 | efx->tx_channel_offset = |
a4900ac9 | 1585 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 | 1586 | |
79d68b37 SH |
1587 | /* We need to mark which channels really have RX and TX |
1588 | * queues, and adjust the TX queue numbers if we have separate | |
602a5322 BH |
1589 | * RX-only and TX-only channels. |
1590 | */ | |
1591 | efx_for_each_channel(channel, efx) { | |
79d68b37 SH |
1592 | if (channel->channel < efx->n_rx_channels) |
1593 | channel->rx_queue.core_index = channel->channel; | |
1594 | else | |
1595 | channel->rx_queue.core_index = -1; | |
1596 | ||
602a5322 BH |
1597 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1598 | tx_queue->queue -= (efx->tx_channel_offset * | |
1599 | EFX_TXQ_TYPES); | |
1600 | } | |
8ceee660 BH |
1601 | } |
1602 | ||
1603 | static int efx_probe_nic(struct efx_nic *efx) | |
1604 | { | |
765c9f46 | 1605 | size_t i; |
8ceee660 BH |
1606 | int rc; |
1607 | ||
62776d03 | 1608 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1609 | |
1610 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1611 | rc = efx->type->probe(efx); |
8ceee660 BH |
1612 | if (rc) |
1613 | return rc; | |
1614 | ||
a4900ac9 | 1615 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1616 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1617 | rc = efx_probe_interrupts(efx); |
1618 | if (rc) | |
c15eed22 | 1619 | goto fail1; |
8ceee660 | 1620 | |
52ad762b DP |
1621 | efx_set_channels(efx); |
1622 | ||
c15eed22 BH |
1623 | rc = efx->type->dimension_resources(efx); |
1624 | if (rc) | |
1625 | goto fail2; | |
28e47c49 | 1626 | |
5d3a6fca | 1627 | if (efx->n_channels > 1) |
7a20db37 | 1628 | netdev_rss_key_fill(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); |
765c9f46 | 1629 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 | 1630 | efx->rx_indir_table[i] = |
cd2d5b52 | 1631 | ethtool_rxfh_indir_default(i, efx->rss_spread); |
5d3a6fca | 1632 | |
c4f4adc7 BH |
1633 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1634 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1635 | |
1636 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1637 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1638 | true); | |
8ceee660 BH |
1639 | |
1640 | return 0; | |
64d8ad6d | 1641 | |
c15eed22 BH |
1642 | fail2: |
1643 | efx_remove_interrupts(efx); | |
1644 | fail1: | |
64d8ad6d BH |
1645 | efx->type->remove(efx); |
1646 | return rc; | |
8ceee660 BH |
1647 | } |
1648 | ||
1649 | static void efx_remove_nic(struct efx_nic *efx) | |
1650 | { | |
62776d03 | 1651 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1652 | |
1653 | efx_remove_interrupts(efx); | |
ef2b90ee | 1654 | efx->type->remove(efx); |
8ceee660 BH |
1655 | } |
1656 | ||
add72477 BH |
1657 | static int efx_probe_filters(struct efx_nic *efx) |
1658 | { | |
1659 | int rc; | |
1660 | ||
1661 | spin_lock_init(&efx->filter_lock); | |
1662 | ||
1663 | rc = efx->type->filter_table_probe(efx); | |
1664 | if (rc) | |
1665 | return rc; | |
1666 | ||
1667 | #ifdef CONFIG_RFS_ACCEL | |
1668 | if (efx->type->offload_features & NETIF_F_NTUPLE) { | |
1669 | efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters, | |
1670 | sizeof(*efx->rps_flow_id), | |
1671 | GFP_KERNEL); | |
1672 | if (!efx->rps_flow_id) { | |
1673 | efx->type->filter_table_remove(efx); | |
1674 | return -ENOMEM; | |
1675 | } | |
1676 | } | |
1677 | #endif | |
1678 | ||
1679 | return 0; | |
1680 | } | |
1681 | ||
1682 | static void efx_remove_filters(struct efx_nic *efx) | |
1683 | { | |
1684 | #ifdef CONFIG_RFS_ACCEL | |
1685 | kfree(efx->rps_flow_id); | |
1686 | #endif | |
1687 | efx->type->filter_table_remove(efx); | |
1688 | } | |
1689 | ||
1690 | static void efx_restore_filters(struct efx_nic *efx) | |
1691 | { | |
1692 | efx->type->filter_table_restore(efx); | |
1693 | } | |
1694 | ||
8ceee660 BH |
1695 | /************************************************************************** |
1696 | * | |
1697 | * NIC startup/shutdown | |
1698 | * | |
1699 | *************************************************************************/ | |
1700 | ||
1701 | static int efx_probe_all(struct efx_nic *efx) | |
1702 | { | |
8ceee660 BH |
1703 | int rc; |
1704 | ||
8ceee660 BH |
1705 | rc = efx_probe_nic(efx); |
1706 | if (rc) { | |
62776d03 | 1707 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1708 | goto fail1; |
1709 | } | |
1710 | ||
8ceee660 BH |
1711 | rc = efx_probe_port(efx); |
1712 | if (rc) { | |
62776d03 | 1713 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1714 | goto fail2; |
1715 | } | |
1716 | ||
7e6d06f0 BH |
1717 | BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); |
1718 | if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { | |
1719 | rc = -EINVAL; | |
1720 | goto fail3; | |
1721 | } | |
ecc910f5 | 1722 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1723 | |
64eebcfd BH |
1724 | rc = efx_probe_filters(efx); |
1725 | if (rc) { | |
1726 | netif_err(efx, probe, efx->net_dev, | |
1727 | "failed to create filter tables\n"); | |
7f967c01 | 1728 | goto fail3; |
64eebcfd BH |
1729 | } |
1730 | ||
7f967c01 BH |
1731 | rc = efx_probe_channels(efx); |
1732 | if (rc) | |
1733 | goto fail4; | |
1734 | ||
8ceee660 BH |
1735 | return 0; |
1736 | ||
64eebcfd | 1737 | fail4: |
7f967c01 | 1738 | efx_remove_filters(efx); |
8ceee660 | 1739 | fail3: |
8ceee660 BH |
1740 | efx_remove_port(efx); |
1741 | fail2: | |
1742 | efx_remove_nic(efx); | |
1743 | fail1: | |
1744 | return rc; | |
1745 | } | |
1746 | ||
8b7325b4 BH |
1747 | /* If the interface is supposed to be running but is not, start |
1748 | * the hardware and software data path, regular activity for the port | |
1749 | * (MAC statistics, link polling, etc.) and schedule the port to be | |
1750 | * reconfigured. Interrupts must already be enabled. This function | |
1751 | * is safe to call multiple times, so long as the NIC is not disabled. | |
1752 | * Requires the RTNL lock. | |
9f2cb71c | 1753 | */ |
8ceee660 BH |
1754 | static void efx_start_all(struct efx_nic *efx) |
1755 | { | |
8ceee660 | 1756 | EFX_ASSERT_RESET_SERIALISED(efx); |
8b7325b4 | 1757 | BUG_ON(efx->state == STATE_DISABLED); |
8ceee660 BH |
1758 | |
1759 | /* Check that it is appropriate to restart the interface. All | |
1760 | * of these flags are safe to read under just the rtnl lock */ | |
e283546c EC |
1761 | if (efx->port_enabled || !netif_running(efx->net_dev) || |
1762 | efx->reset_pending) | |
8ceee660 BH |
1763 | return; |
1764 | ||
8ceee660 | 1765 | efx_start_port(efx); |
9f2cb71c | 1766 | efx_start_datapath(efx); |
8880f4ec | 1767 | |
626950db AR |
1768 | /* Start the hardware monitor if there is one */ |
1769 | if (efx->type->monitor != NULL) | |
8ceee660 BH |
1770 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1771 | efx_monitor_interval); | |
626950db AR |
1772 | |
1773 | /* If link state detection is normally event-driven, we have | |
1774 | * to poll now because we could have missed a change | |
1775 | */ | |
1776 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { | |
78c1f0a0 SH |
1777 | mutex_lock(&efx->mac_lock); |
1778 | if (efx->phy_op->poll(efx)) | |
1779 | efx_link_status_changed(efx); | |
1780 | mutex_unlock(&efx->mac_lock); | |
1781 | } | |
55edc6e6 | 1782 | |
ef2b90ee | 1783 | efx->type->start_stats(efx); |
f8f3b5ae JC |
1784 | efx->type->pull_stats(efx); |
1785 | spin_lock_bh(&efx->stats_lock); | |
1786 | efx->type->update_stats(efx, NULL, NULL); | |
1787 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
1788 | } |
1789 | ||
8b7325b4 BH |
1790 | /* Quiesce the hardware and software data path, and regular activity |
1791 | * for the port without bringing the link down. Safe to call multiple | |
1792 | * times with the NIC in almost any state, but interrupts should be | |
1793 | * enabled. Requires the RTNL lock. | |
1794 | */ | |
8ceee660 BH |
1795 | static void efx_stop_all(struct efx_nic *efx) |
1796 | { | |
8ceee660 BH |
1797 | EFX_ASSERT_RESET_SERIALISED(efx); |
1798 | ||
1799 | /* port_enabled can be read safely under the rtnl lock */ | |
1800 | if (!efx->port_enabled) | |
1801 | return; | |
1802 | ||
f8f3b5ae JC |
1803 | /* update stats before we go down so we can accurately count |
1804 | * rx_nodesc_drops | |
1805 | */ | |
1806 | efx->type->pull_stats(efx); | |
1807 | spin_lock_bh(&efx->stats_lock); | |
1808 | efx->type->update_stats(efx, NULL, NULL); | |
1809 | spin_unlock_bh(&efx->stats_lock); | |
ef2b90ee | 1810 | efx->type->stop_stats(efx); |
8ceee660 BH |
1811 | efx_stop_port(efx); |
1812 | ||
29c69a48 BH |
1813 | /* Stop the kernel transmit interface. This is only valid if |
1814 | * the device is stopped or detached; otherwise the watchdog | |
1815 | * may fire immediately. | |
1816 | */ | |
1817 | WARN_ON(netif_running(efx->net_dev) && | |
1818 | netif_device_present(efx->net_dev)); | |
9f2cb71c BH |
1819 | netif_tx_disable(efx->net_dev); |
1820 | ||
1821 | efx_stop_datapath(efx); | |
8ceee660 BH |
1822 | } |
1823 | ||
1824 | static void efx_remove_all(struct efx_nic *efx) | |
1825 | { | |
4642610c | 1826 | efx_remove_channels(efx); |
7f967c01 | 1827 | efx_remove_filters(efx); |
8ceee660 BH |
1828 | efx_remove_port(efx); |
1829 | efx_remove_nic(efx); | |
1830 | } | |
1831 | ||
8ceee660 BH |
1832 | /************************************************************************** |
1833 | * | |
1834 | * Interrupt moderation | |
1835 | * | |
1836 | **************************************************************************/ | |
1837 | ||
cc180b69 | 1838 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1839 | { |
b548f976 BH |
1840 | if (usecs == 0) |
1841 | return 0; | |
cc180b69 | 1842 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1843 | return 1; /* never round down to 0 */ |
cc180b69 | 1844 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1845 | } |
1846 | ||
8ceee660 | 1847 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1848 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1849 | unsigned int rx_usecs, bool rx_adaptive, | |
1850 | bool rx_may_override_tx) | |
8ceee660 | 1851 | { |
f7d12cdc | 1852 | struct efx_channel *channel; |
cc180b69 BH |
1853 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1854 | efx->timer_quantum_ns, | |
1855 | 1000); | |
1856 | unsigned int tx_ticks; | |
1857 | unsigned int rx_ticks; | |
8ceee660 BH |
1858 | |
1859 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1860 | ||
cc180b69 | 1861 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1862 | return -EINVAL; |
1863 | ||
cc180b69 BH |
1864 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1865 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1866 | ||
9e393b30 BH |
1867 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1868 | !rx_may_override_tx) { | |
1869 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1870 | "RX and TX IRQ moderation must be equal\n"); | |
1871 | return -EINVAL; | |
1872 | } | |
1873 | ||
6fb70fd1 | 1874 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1875 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1876 | efx_for_each_channel(channel, efx) { |
525da907 | 1877 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1878 | channel->irq_moderation = rx_ticks; |
525da907 | 1879 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1880 | channel->irq_moderation = tx_ticks; |
1881 | } | |
9e393b30 BH |
1882 | |
1883 | return 0; | |
8ceee660 BH |
1884 | } |
1885 | ||
a0c4faf5 BH |
1886 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1887 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1888 | { | |
cc180b69 BH |
1889 | /* We must round up when converting ticks to microseconds |
1890 | * because we round down when converting the other way. | |
1891 | */ | |
1892 | ||
a0c4faf5 | 1893 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1894 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1895 | efx->timer_quantum_ns, | |
1896 | 1000); | |
a0c4faf5 BH |
1897 | |
1898 | /* If channels are shared between RX and TX, so is IRQ | |
1899 | * moderation. Otherwise, IRQ moderation is the same for all | |
1900 | * TX channels and is not adaptive. | |
1901 | */ | |
1902 | if (efx->tx_channel_offset == 0) | |
1903 | *tx_usecs = *rx_usecs; | |
1904 | else | |
cc180b69 | 1905 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1906 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1907 | efx->timer_quantum_ns, |
1908 | 1000); | |
a0c4faf5 BH |
1909 | } |
1910 | ||
8ceee660 BH |
1911 | /************************************************************************** |
1912 | * | |
1913 | * Hardware monitor | |
1914 | * | |
1915 | **************************************************************************/ | |
1916 | ||
e254c274 | 1917 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1918 | static void efx_monitor(struct work_struct *data) |
1919 | { | |
1920 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1921 | monitor_work.work); | |
8ceee660 | 1922 | |
62776d03 BH |
1923 | netif_vdbg(efx, timer, efx->net_dev, |
1924 | "hardware monitor executing on CPU %d\n", | |
1925 | raw_smp_processor_id()); | |
ef2b90ee | 1926 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1927 | |
8ceee660 BH |
1928 | /* If the mac_lock is already held then it is likely a port |
1929 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1930 | * most of the work of monitor() anyway. */ |
1931 | if (mutex_trylock(&efx->mac_lock)) { | |
1932 | if (efx->port_enabled) | |
1933 | efx->type->monitor(efx); | |
1934 | mutex_unlock(&efx->mac_lock); | |
1935 | } | |
8ceee660 | 1936 | |
8ceee660 BH |
1937 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1938 | efx_monitor_interval); | |
1939 | } | |
1940 | ||
1941 | /************************************************************************** | |
1942 | * | |
1943 | * ioctls | |
1944 | * | |
1945 | *************************************************************************/ | |
1946 | ||
1947 | /* Net device ioctl | |
1948 | * Context: process, rtnl_lock() held. | |
1949 | */ | |
1950 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1951 | { | |
767e468c | 1952 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1953 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 | 1954 | |
7c236c43 | 1955 | if (cmd == SIOCSHWTSTAMP) |
433dc9b3 BH |
1956 | return efx_ptp_set_ts_config(efx, ifr); |
1957 | if (cmd == SIOCGHWTSTAMP) | |
1958 | return efx_ptp_get_ts_config(efx, ifr); | |
7c236c43 | 1959 | |
68e7f45e BH |
1960 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1961 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1962 | (data->phy_id & 0xfc00) == 0x0400) | |
1963 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1964 | ||
1965 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1966 | } |
1967 | ||
1968 | /************************************************************************** | |
1969 | * | |
1970 | * NAPI interface | |
1971 | * | |
1972 | **************************************************************************/ | |
1973 | ||
7f967c01 BH |
1974 | static void efx_init_napi_channel(struct efx_channel *channel) |
1975 | { | |
1976 | struct efx_nic *efx = channel->efx; | |
1977 | ||
1978 | channel->napi_dev = efx->net_dev; | |
1979 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
1980 | efx_poll, napi_weight); | |
36763266 AR |
1981 | napi_hash_add(&channel->napi_str); |
1982 | efx_channel_init_lock(channel); | |
7f967c01 BH |
1983 | } |
1984 | ||
e8f14992 | 1985 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1986 | { |
1987 | struct efx_channel *channel; | |
8ceee660 | 1988 | |
7f967c01 BH |
1989 | efx_for_each_channel(channel, efx) |
1990 | efx_init_napi_channel(channel); | |
e8f14992 BH |
1991 | } |
1992 | ||
1993 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1994 | { | |
36763266 | 1995 | if (channel->napi_dev) { |
e8f14992 | 1996 | netif_napi_del(&channel->napi_str); |
36763266 AR |
1997 | napi_hash_del(&channel->napi_str); |
1998 | } | |
e8f14992 | 1999 | channel->napi_dev = NULL; |
8ceee660 BH |
2000 | } |
2001 | ||
2002 | static void efx_fini_napi(struct efx_nic *efx) | |
2003 | { | |
2004 | struct efx_channel *channel; | |
2005 | ||
e8f14992 BH |
2006 | efx_for_each_channel(channel, efx) |
2007 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
2008 | } |
2009 | ||
2010 | /************************************************************************** | |
2011 | * | |
2012 | * Kernel netpoll interface | |
2013 | * | |
2014 | *************************************************************************/ | |
2015 | ||
2016 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2017 | ||
2018 | /* Although in the common case interrupts will be disabled, this is not | |
2019 | * guaranteed. However, all our work happens inside the NAPI callback, | |
2020 | * so no locking is required. | |
2021 | */ | |
2022 | static void efx_netpoll(struct net_device *net_dev) | |
2023 | { | |
767e468c | 2024 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
2025 | struct efx_channel *channel; |
2026 | ||
64ee3120 | 2027 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
2028 | efx_schedule_channel(channel); |
2029 | } | |
2030 | ||
2031 | #endif | |
2032 | ||
36763266 AR |
2033 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2034 | static int efx_busy_poll(struct napi_struct *napi) | |
2035 | { | |
2036 | struct efx_channel *channel = | |
2037 | container_of(napi, struct efx_channel, napi_str); | |
2038 | struct efx_nic *efx = channel->efx; | |
2039 | int budget = 4; | |
2040 | int old_rx_packets, rx_packets; | |
2041 | ||
2042 | if (!netif_running(efx->net_dev)) | |
2043 | return LL_FLUSH_FAILED; | |
2044 | ||
2045 | if (!efx_channel_lock_poll(channel)) | |
2046 | return LL_FLUSH_BUSY; | |
2047 | ||
2048 | old_rx_packets = channel->rx_queue.rx_packets; | |
2049 | efx_process_channel(channel, budget); | |
2050 | ||
2051 | rx_packets = channel->rx_queue.rx_packets - old_rx_packets; | |
2052 | ||
2053 | /* There is no race condition with NAPI here. | |
2054 | * NAPI will automatically be rescheduled if it yielded during busy | |
2055 | * polling, because it was not able to take the lock and thus returned | |
2056 | * the full budget. | |
2057 | */ | |
2058 | efx_channel_unlock_poll(channel); | |
2059 | ||
2060 | return rx_packets; | |
2061 | } | |
2062 | #endif | |
2063 | ||
8ceee660 BH |
2064 | /************************************************************************** |
2065 | * | |
2066 | * Kernel net device interface | |
2067 | * | |
2068 | *************************************************************************/ | |
2069 | ||
2070 | /* Context: process, rtnl_lock() held. */ | |
2071 | static int efx_net_open(struct net_device *net_dev) | |
2072 | { | |
767e468c | 2073 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 BH |
2074 | int rc; |
2075 | ||
62776d03 BH |
2076 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
2077 | raw_smp_processor_id()); | |
8ceee660 | 2078 | |
8b7325b4 BH |
2079 | rc = efx_check_disabled(efx); |
2080 | if (rc) | |
2081 | return rc; | |
f8b87c17 BH |
2082 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
2083 | return -EBUSY; | |
8880f4ec BH |
2084 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
2085 | return -EIO; | |
f8b87c17 | 2086 | |
78c1f0a0 SH |
2087 | /* Notify the kernel of the link state polled during driver load, |
2088 | * before the monitor starts running */ | |
2089 | efx_link_status_changed(efx); | |
2090 | ||
8ceee660 | 2091 | efx_start_all(efx); |
dd40781e | 2092 | efx_selftest_async_start(efx); |
8ceee660 BH |
2093 | return 0; |
2094 | } | |
2095 | ||
2096 | /* Context: process, rtnl_lock() held. | |
2097 | * Note that the kernel will ignore our return code; this method | |
2098 | * should really be a void. | |
2099 | */ | |
2100 | static int efx_net_stop(struct net_device *net_dev) | |
2101 | { | |
767e468c | 2102 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2103 | |
62776d03 BH |
2104 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
2105 | raw_smp_processor_id()); | |
8ceee660 | 2106 | |
8b7325b4 BH |
2107 | /* Stop the device and flush all the channels */ |
2108 | efx_stop_all(efx); | |
8ceee660 BH |
2109 | |
2110 | return 0; | |
2111 | } | |
2112 | ||
5b9e207c | 2113 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
2114 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
2115 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 2116 | { |
767e468c | 2117 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2118 | |
55edc6e6 | 2119 | spin_lock_bh(&efx->stats_lock); |
cd0ecc9a | 2120 | efx->type->update_stats(efx, NULL, stats); |
1cb34522 BH |
2121 | spin_unlock_bh(&efx->stats_lock); |
2122 | ||
8ceee660 BH |
2123 | return stats; |
2124 | } | |
2125 | ||
2126 | /* Context: netif_tx_lock held, BHs disabled. */ | |
2127 | static void efx_watchdog(struct net_device *net_dev) | |
2128 | { | |
767e468c | 2129 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2130 | |
62776d03 BH |
2131 | netif_err(efx, tx_err, efx->net_dev, |
2132 | "TX stuck with port_enabled=%d: resetting channels\n", | |
2133 | efx->port_enabled); | |
8ceee660 | 2134 | |
739bb23d | 2135 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
2136 | } |
2137 | ||
2138 | ||
2139 | /* Context: process, rtnl_lock() held. */ | |
2140 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
2141 | { | |
767e468c | 2142 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 | 2143 | int rc; |
8ceee660 | 2144 | |
8b7325b4 BH |
2145 | rc = efx_check_disabled(efx); |
2146 | if (rc) | |
2147 | return rc; | |
8ceee660 BH |
2148 | if (new_mtu > EFX_MAX_MTU) |
2149 | return -EINVAL; | |
2150 | ||
62776d03 | 2151 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 2152 | |
29c69a48 BH |
2153 | efx_device_detach_sync(efx); |
2154 | efx_stop_all(efx); | |
2155 | ||
d3245b28 | 2156 | mutex_lock(&efx->mac_lock); |
8ceee660 | 2157 | net_dev->mtu = new_mtu; |
710b208d | 2158 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
2159 | mutex_unlock(&efx->mac_lock); |
2160 | ||
8ceee660 | 2161 | efx_start_all(efx); |
29c69a48 | 2162 | netif_device_attach(efx->net_dev); |
6c8eef4a | 2163 | return 0; |
8ceee660 BH |
2164 | } |
2165 | ||
2166 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
2167 | { | |
767e468c | 2168 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2169 | struct sockaddr *addr = data; |
e0b3ae30 | 2170 | u8 *new_addr = addr->sa_data; |
8ceee660 | 2171 | |
8ceee660 | 2172 | if (!is_valid_ether_addr(new_addr)) { |
62776d03 BH |
2173 | netif_err(efx, drv, efx->net_dev, |
2174 | "invalid ethernet MAC address requested: %pM\n", | |
2175 | new_addr); | |
504f9b5a | 2176 | return -EADDRNOTAVAIL; |
8ceee660 BH |
2177 | } |
2178 | ||
cd84ff4d | 2179 | ether_addr_copy(net_dev->dev_addr, new_addr); |
7fa8d547 SS |
2180 | if (efx->type->sriov_mac_address_changed) |
2181 | efx->type->sriov_mac_address_changed(efx); | |
8ceee660 BH |
2182 | |
2183 | /* Reconfigure the MAC */ | |
d3245b28 | 2184 | mutex_lock(&efx->mac_lock); |
710b208d | 2185 | efx->type->reconfigure_mac(efx); |
d3245b28 | 2186 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
2187 | |
2188 | return 0; | |
2189 | } | |
2190 | ||
a816f75a | 2191 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 2192 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 2193 | { |
767e468c | 2194 | struct efx_nic *efx = netdev_priv(net_dev); |
a816f75a | 2195 | |
8be4f3e6 BH |
2196 | if (efx->port_enabled) |
2197 | queue_work(efx->workqueue, &efx->mac_work); | |
2198 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
2199 | } |
2200 | ||
c8f44aff | 2201 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
2202 | { |
2203 | struct efx_nic *efx = netdev_priv(net_dev); | |
2204 | ||
2205 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
2206 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
fbd79120 | 2207 | return efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); |
abfe9039 BH |
2208 | |
2209 | return 0; | |
2210 | } | |
2211 | ||
7fa8d547 | 2212 | static const struct net_device_ops efx_netdev_ops = { |
c3ecb9f3 SH |
2213 | .ndo_open = efx_net_open, |
2214 | .ndo_stop = efx_net_stop, | |
4472702e | 2215 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
2216 | .ndo_tx_timeout = efx_watchdog, |
2217 | .ndo_start_xmit = efx_hard_start_xmit, | |
2218 | .ndo_validate_addr = eth_validate_addr, | |
2219 | .ndo_do_ioctl = efx_ioctl, | |
2220 | .ndo_change_mtu = efx_change_mtu, | |
2221 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2222 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2223 | .ndo_set_features = efx_set_features, |
cd2d5b52 | 2224 | #ifdef CONFIG_SFC_SRIOV |
7fa8d547 SS |
2225 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, |
2226 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2227 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2228 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
cd2d5b52 | 2229 | #endif |
c3ecb9f3 SH |
2230 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2231 | .ndo_poll_controller = efx_netpoll, | |
2232 | #endif | |
94b274bf | 2233 | .ndo_setup_tc = efx_setup_tc, |
36763266 AR |
2234 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2235 | .ndo_busy_poll = efx_busy_poll, | |
2236 | #endif | |
64d8ad6d BH |
2237 | #ifdef CONFIG_RFS_ACCEL |
2238 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2239 | #endif | |
c3ecb9f3 SH |
2240 | }; |
2241 | ||
7dde596e BH |
2242 | static void efx_update_name(struct efx_nic *efx) |
2243 | { | |
2244 | strcpy(efx->name, efx->net_dev->name); | |
2245 | efx_mtd_rename(efx); | |
2246 | efx_set_channel_names(efx); | |
2247 | } | |
2248 | ||
8ceee660 BH |
2249 | static int efx_netdev_event(struct notifier_block *this, |
2250 | unsigned long event, void *ptr) | |
2251 | { | |
351638e7 | 2252 | struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); |
8ceee660 | 2253 | |
7fa8d547 | 2254 | if ((net_dev->netdev_ops == &efx_netdev_ops) && |
7dde596e BH |
2255 | event == NETDEV_CHANGENAME) |
2256 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2257 | |
2258 | return NOTIFY_DONE; | |
2259 | } | |
2260 | ||
2261 | static struct notifier_block efx_netdev_notifier = { | |
2262 | .notifier_call = efx_netdev_event, | |
2263 | }; | |
2264 | ||
06d5e193 BH |
2265 | static ssize_t |
2266 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2267 | { | |
2268 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2269 | return sprintf(buf, "%d\n", efx->phy_type); | |
2270 | } | |
776fbcc9 | 2271 | static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); |
06d5e193 | 2272 | |
8ceee660 BH |
2273 | static int efx_register_netdev(struct efx_nic *efx) |
2274 | { | |
2275 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2276 | struct efx_channel *channel; |
8ceee660 BH |
2277 | int rc; |
2278 | ||
2279 | net_dev->watchdog_timeo = 5 * HZ; | |
2280 | net_dev->irq = efx->pci_dev->irq; | |
7fa8d547 SS |
2281 | net_dev->netdev_ops = &efx_netdev_ops; |
2282 | if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) | |
8127d661 | 2283 | net_dev->priv_flags |= IFF_UNICAST_FLT; |
7ad24ea4 | 2284 | net_dev->ethtool_ops = &efx_ethtool_ops; |
7e6d06f0 | 2285 | net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; |
8ceee660 | 2286 | |
7dde596e | 2287 | rtnl_lock(); |
aed0628d | 2288 | |
7153f623 BH |
2289 | /* Enable resets to be scheduled and check whether any were |
2290 | * already requested. If so, the NIC is probably hosed so we | |
2291 | * abort. | |
2292 | */ | |
2293 | efx->state = STATE_READY; | |
2294 | smp_mb(); /* ensure we change state before checking reset_pending */ | |
2295 | if (efx->reset_pending) { | |
2296 | netif_err(efx, probe, efx->net_dev, | |
2297 | "aborting probe due to scheduled reset\n"); | |
2298 | rc = -EIO; | |
2299 | goto fail_locked; | |
2300 | } | |
2301 | ||
aed0628d BH |
2302 | rc = dev_alloc_name(net_dev, net_dev->name); |
2303 | if (rc < 0) | |
2304 | goto fail_locked; | |
7dde596e | 2305 | efx_update_name(efx); |
aed0628d | 2306 | |
8f8b3d51 BH |
2307 | /* Always start with carrier off; PHY events will detect the link */ |
2308 | netif_carrier_off(net_dev); | |
2309 | ||
aed0628d BH |
2310 | rc = register_netdevice(net_dev); |
2311 | if (rc) | |
2312 | goto fail_locked; | |
2313 | ||
c04bfc6b BH |
2314 | efx_for_each_channel(channel, efx) { |
2315 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2316 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2317 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2318 | } |
2319 | ||
0bcf4a64 BH |
2320 | efx_associate(efx); |
2321 | ||
7dde596e | 2322 | rtnl_unlock(); |
8ceee660 | 2323 | |
06d5e193 BH |
2324 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2325 | if (rc) { | |
62776d03 BH |
2326 | netif_err(efx, drv, efx->net_dev, |
2327 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2328 | goto fail_registered; |
2329 | } | |
2330 | ||
8ceee660 | 2331 | return 0; |
06d5e193 | 2332 | |
7153f623 BH |
2333 | fail_registered: |
2334 | rtnl_lock(); | |
0bcf4a64 | 2335 | efx_dissociate(efx); |
7153f623 | 2336 | unregister_netdevice(net_dev); |
aed0628d | 2337 | fail_locked: |
7153f623 | 2338 | efx->state = STATE_UNINIT; |
aed0628d | 2339 | rtnl_unlock(); |
62776d03 | 2340 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d | 2341 | return rc; |
8ceee660 BH |
2342 | } |
2343 | ||
2344 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2345 | { | |
8ceee660 BH |
2346 | if (!efx->net_dev) |
2347 | return; | |
2348 | ||
767e468c | 2349 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 | 2350 | |
73ba7b68 BH |
2351 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
2352 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
7153f623 BH |
2353 | |
2354 | rtnl_lock(); | |
2355 | unregister_netdevice(efx->net_dev); | |
2356 | efx->state = STATE_UNINIT; | |
2357 | rtnl_unlock(); | |
8ceee660 BH |
2358 | } |
2359 | ||
2360 | /************************************************************************** | |
2361 | * | |
2362 | * Device reset and suspend | |
2363 | * | |
2364 | **************************************************************************/ | |
2365 | ||
2467ca46 BH |
2366 | /* Tears down the entire software state and most of the hardware state |
2367 | * before reset. */ | |
d3245b28 | 2368 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2369 | { |
8ceee660 BH |
2370 | EFX_ASSERT_RESET_SERIALISED(efx); |
2371 | ||
e283546c EC |
2372 | if (method == RESET_TYPE_MCDI_TIMEOUT) |
2373 | efx->type->prepare_flr(efx); | |
2374 | ||
2467ca46 | 2375 | efx_stop_all(efx); |
d8291187 | 2376 | efx_disable_interrupts(efx); |
5642ceef BH |
2377 | |
2378 | mutex_lock(&efx->mac_lock); | |
4b988280 SH |
2379 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2380 | efx->phy_op->fini(efx); | |
ef2b90ee | 2381 | efx->type->fini(efx); |
8ceee660 BH |
2382 | } |
2383 | ||
2467ca46 BH |
2384 | /* This function will always ensure that the locks acquired in |
2385 | * efx_reset_down() are released. A failure return code indicates | |
2386 | * that we were unable to reinitialise the hardware, and the | |
2387 | * driver should be disabled. If ok is false, then the rx and tx | |
2388 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2389 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2390 | { |
2391 | int rc; | |
2392 | ||
2467ca46 | 2393 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2394 | |
e283546c EC |
2395 | if (method == RESET_TYPE_MCDI_TIMEOUT) |
2396 | efx->type->finish_flr(efx); | |
2397 | ||
2398 | /* Ensure that SRAM is initialised even if we're disabling the device */ | |
ef2b90ee | 2399 | rc = efx->type->init(efx); |
8ceee660 | 2400 | if (rc) { |
62776d03 | 2401 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2402 | goto fail; |
8ceee660 BH |
2403 | } |
2404 | ||
eb9f6744 BH |
2405 | if (!ok) |
2406 | goto fail; | |
2407 | ||
4b988280 | 2408 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2409 | rc = efx->phy_op->init(efx); |
2410 | if (rc) | |
2411 | goto fail; | |
2412 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2413 | netif_err(efx, drv, efx->net_dev, |
2414 | "could not restore PHY settings\n"); | |
4b988280 SH |
2415 | } |
2416 | ||
261e4d96 JC |
2417 | rc = efx_enable_interrupts(efx); |
2418 | if (rc) | |
2419 | goto fail; | |
64eebcfd | 2420 | efx_restore_filters(efx); |
7fa8d547 SS |
2421 | if (efx->type->sriov_reset) |
2422 | efx->type->sriov_reset(efx); | |
eb9f6744 | 2423 | |
eb9f6744 BH |
2424 | mutex_unlock(&efx->mac_lock); |
2425 | ||
2426 | efx_start_all(efx); | |
2427 | ||
2428 | return 0; | |
2429 | ||
2430 | fail: | |
2431 | efx->port_initialized = false; | |
2467ca46 BH |
2432 | |
2433 | mutex_unlock(&efx->mac_lock); | |
2434 | ||
8ceee660 BH |
2435 | return rc; |
2436 | } | |
2437 | ||
eb9f6744 BH |
2438 | /* Reset the NIC using the specified method. Note that the reset may |
2439 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2440 | * |
eb9f6744 | 2441 | * Caller must hold the rtnl_lock. |
8ceee660 | 2442 | */ |
eb9f6744 | 2443 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2444 | { |
eb9f6744 BH |
2445 | int rc, rc2; |
2446 | bool disabled; | |
8ceee660 | 2447 | |
62776d03 BH |
2448 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2449 | RESET_TYPE(method)); | |
8ceee660 | 2450 | |
c2f3b8e3 | 2451 | efx_device_detach_sync(efx); |
d3245b28 | 2452 | efx_reset_down(efx, method); |
8ceee660 | 2453 | |
ef2b90ee | 2454 | rc = efx->type->reset(efx, method); |
8ceee660 | 2455 | if (rc) { |
62776d03 | 2456 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2457 | goto out; |
8ceee660 BH |
2458 | } |
2459 | ||
a7d529ae BH |
2460 | /* Clear flags for the scopes we covered. We assume the NIC and |
2461 | * driver are now quiescent so that there is no race here. | |
2462 | */ | |
e283546c EC |
2463 | if (method < RESET_TYPE_MAX_METHOD) |
2464 | efx->reset_pending &= -(1 << (method + 1)); | |
2465 | else /* it doesn't fit into the well-ordered scope hierarchy */ | |
2466 | __clear_bit(method, &efx->reset_pending); | |
8ceee660 BH |
2467 | |
2468 | /* Reinitialise bus-mastering, which may have been turned off before | |
2469 | * the reset was scheduled. This is still appropriate, even in the | |
2470 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2471 | * can respond to requests. */ | |
2472 | pci_set_master(efx->pci_dev); | |
2473 | ||
eb9f6744 | 2474 | out: |
8ceee660 | 2475 | /* Leave device stopped if necessary */ |
626950db AR |
2476 | disabled = rc || |
2477 | method == RESET_TYPE_DISABLE || | |
2478 | method == RESET_TYPE_RECOVER_OR_DISABLE; | |
eb9f6744 BH |
2479 | rc2 = efx_reset_up(efx, method, !disabled); |
2480 | if (rc2) { | |
2481 | disabled = true; | |
2482 | if (!rc) | |
2483 | rc = rc2; | |
8ceee660 BH |
2484 | } |
2485 | ||
eb9f6744 | 2486 | if (disabled) { |
f49a4589 | 2487 | dev_close(efx->net_dev); |
62776d03 | 2488 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2489 | efx->state = STATE_DISABLED; |
f4bd954e | 2490 | } else { |
62776d03 | 2491 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2492 | netif_device_attach(efx->net_dev); |
f4bd954e | 2493 | } |
8ceee660 BH |
2494 | return rc; |
2495 | } | |
2496 | ||
626950db AR |
2497 | /* Try recovery mechanisms. |
2498 | * For now only EEH is supported. | |
2499 | * Returns 0 if the recovery mechanisms are unsuccessful. | |
2500 | * Returns a non-zero value otherwise. | |
2501 | */ | |
b28405b0 | 2502 | int efx_try_recovery(struct efx_nic *efx) |
626950db AR |
2503 | { |
2504 | #ifdef CONFIG_EEH | |
2505 | /* A PCI error can occur and not be seen by EEH because nothing | |
2506 | * happens on the PCI bus. In this case the driver may fail and | |
2507 | * schedule a 'recover or reset', leading to this recovery handler. | |
2508 | * Manually call the eeh failure check function. | |
2509 | */ | |
12a89dba | 2510 | struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev); |
626950db AR |
2511 | if (eeh_dev_check_failure(eehdev)) { |
2512 | /* The EEH mechanisms will handle the error and reset the | |
2513 | * device if necessary. | |
2514 | */ | |
2515 | return 1; | |
2516 | } | |
2517 | #endif | |
2518 | return 0; | |
2519 | } | |
2520 | ||
74cd60a4 JC |
2521 | static void efx_wait_for_bist_end(struct efx_nic *efx) |
2522 | { | |
2523 | int i; | |
2524 | ||
2525 | for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) { | |
2526 | if (efx_mcdi_poll_reboot(efx)) | |
2527 | goto out; | |
2528 | msleep(BIST_WAIT_DELAY_MS); | |
2529 | } | |
2530 | ||
2531 | netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n"); | |
2532 | out: | |
2533 | /* Either way unset the BIST flag. If we found no reboot we probably | |
2534 | * won't recover, but we should try. | |
2535 | */ | |
2536 | efx->mc_bist_for_other_fn = false; | |
2537 | } | |
2538 | ||
8ceee660 BH |
2539 | /* The worker thread exists so that code that cannot sleep can |
2540 | * schedule a reset for later. | |
2541 | */ | |
2542 | static void efx_reset_work(struct work_struct *data) | |
2543 | { | |
eb9f6744 | 2544 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
626950db AR |
2545 | unsigned long pending; |
2546 | enum reset_type method; | |
2547 | ||
2548 | pending = ACCESS_ONCE(efx->reset_pending); | |
2549 | method = fls(pending) - 1; | |
2550 | ||
74cd60a4 JC |
2551 | if (method == RESET_TYPE_MC_BIST) |
2552 | efx_wait_for_bist_end(efx); | |
2553 | ||
626950db AR |
2554 | if ((method == RESET_TYPE_RECOVER_OR_DISABLE || |
2555 | method == RESET_TYPE_RECOVER_OR_ALL) && | |
2556 | efx_try_recovery(efx)) | |
2557 | return; | |
8ceee660 | 2558 | |
a7d529ae | 2559 | if (!pending) |
319ba649 SH |
2560 | return; |
2561 | ||
eb9f6744 | 2562 | rtnl_lock(); |
7153f623 BH |
2563 | |
2564 | /* We checked the state in efx_schedule_reset() but it may | |
2565 | * have changed by now. Now that we have the RTNL lock, | |
2566 | * it cannot change again. | |
2567 | */ | |
2568 | if (efx->state == STATE_READY) | |
626950db | 2569 | (void)efx_reset(efx, method); |
7153f623 | 2570 | |
eb9f6744 | 2571 | rtnl_unlock(); |
8ceee660 BH |
2572 | } |
2573 | ||
2574 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2575 | { | |
2576 | enum reset_type method; | |
2577 | ||
626950db AR |
2578 | if (efx->state == STATE_RECOVERY) { |
2579 | netif_dbg(efx, drv, efx->net_dev, | |
2580 | "recovering: skip scheduling %s reset\n", | |
2581 | RESET_TYPE(type)); | |
2582 | return; | |
2583 | } | |
2584 | ||
8ceee660 BH |
2585 | switch (type) { |
2586 | case RESET_TYPE_INVISIBLE: | |
2587 | case RESET_TYPE_ALL: | |
626950db | 2588 | case RESET_TYPE_RECOVER_OR_ALL: |
8ceee660 BH |
2589 | case RESET_TYPE_WORLD: |
2590 | case RESET_TYPE_DISABLE: | |
626950db | 2591 | case RESET_TYPE_RECOVER_OR_DISABLE: |
74cd60a4 | 2592 | case RESET_TYPE_MC_BIST: |
e283546c | 2593 | case RESET_TYPE_MCDI_TIMEOUT: |
8ceee660 | 2594 | method = type; |
0e2a9c7c BH |
2595 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2596 | RESET_TYPE(method)); | |
8ceee660 | 2597 | break; |
8ceee660 | 2598 | default: |
0e2a9c7c | 2599 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2600 | netif_dbg(efx, drv, efx->net_dev, |
2601 | "scheduling %s reset for %s\n", | |
2602 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2603 | break; |
2604 | } | |
8ceee660 | 2605 | |
a7d529ae | 2606 | set_bit(method, &efx->reset_pending); |
7153f623 BH |
2607 | smp_mb(); /* ensure we change reset_pending before checking state */ |
2608 | ||
2609 | /* If we're not READY then just leave the flags set as the cue | |
2610 | * to abort probing or reschedule the reset later. | |
2611 | */ | |
2612 | if (ACCESS_ONCE(efx->state) != STATE_READY) | |
2613 | return; | |
8ceee660 | 2614 | |
8880f4ec BH |
2615 | /* efx_process_channel() will no longer read events once a |
2616 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2617 | efx_mcdi_mode_poll(efx); | |
2618 | ||
1ab00629 | 2619 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2620 | } |
2621 | ||
2622 | /************************************************************************** | |
2623 | * | |
2624 | * List of NICs we support | |
2625 | * | |
2626 | **************************************************************************/ | |
2627 | ||
2628 | /* PCI device ID table */ | |
9baa3c34 | 2629 | static const struct pci_device_id efx_pci_table[] = { |
937383a5 BH |
2630 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2631 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2632 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2633 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2634 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2635 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2636 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2637 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2638 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2639 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8127d661 BH |
2640 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */ |
2641 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
3b06a00e MW |
2642 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0923), /* SFC9140 PF */ |
2643 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
8ceee660 BH |
2644 | {0} /* end of list */ |
2645 | }; | |
2646 | ||
2647 | /************************************************************************** | |
2648 | * | |
3759433d | 2649 | * Dummy PHY/MAC operations |
8ceee660 | 2650 | * |
01aad7b6 | 2651 | * Can be used for some unimplemented operations |
8ceee660 BH |
2652 | * Needed so all function pointers are valid and do not have to be tested |
2653 | * before use | |
2654 | * | |
2655 | **************************************************************************/ | |
2656 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2657 | { | |
2658 | return 0; | |
2659 | } | |
2660 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2661 | |
2662 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2663 | { |
2664 | return false; | |
2665 | } | |
8ceee660 | 2666 | |
6c8c2513 | 2667 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2668 | .init = efx_port_dummy_op_int, |
d3245b28 | 2669 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2670 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2671 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2672 | }; |
2673 | ||
8ceee660 BH |
2674 | /************************************************************************** |
2675 | * | |
2676 | * Data housekeeping | |
2677 | * | |
2678 | **************************************************************************/ | |
2679 | ||
2680 | /* This zeroes out and then fills in the invariants in a struct | |
2681 | * efx_nic (including all sub-structures). | |
2682 | */ | |
adeb15aa | 2683 | static int efx_init_struct(struct efx_nic *efx, |
8ceee660 BH |
2684 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2685 | { | |
4642610c | 2686 | int i; |
8ceee660 BH |
2687 | |
2688 | /* Initialise common structures */ | |
0bcf4a64 BH |
2689 | INIT_LIST_HEAD(&efx->node); |
2690 | INIT_LIST_HEAD(&efx->secondary_list); | |
8ceee660 | 2691 | spin_lock_init(&efx->biu_lock); |
76884835 BH |
2692 | #ifdef CONFIG_SFC_MTD |
2693 | INIT_LIST_HEAD(&efx->mtd_list); | |
2694 | #endif | |
8ceee660 BH |
2695 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2696 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
dd40781e | 2697 | INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); |
8ceee660 | 2698 | efx->pci_dev = pci_dev; |
62776d03 | 2699 | efx->msg_enable = debug; |
f16aeea0 | 2700 | efx->state = STATE_UNINIT; |
8ceee660 | 2701 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2702 | |
2703 | efx->net_dev = net_dev; | |
43a3739d | 2704 | efx->rx_prefix_size = efx->type->rx_prefix_size; |
2ec03014 AR |
2705 | efx->rx_ip_align = |
2706 | NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0; | |
43a3739d JC |
2707 | efx->rx_packet_hash_offset = |
2708 | efx->type->rx_hash_offset - efx->type->rx_prefix_size; | |
bd9a265d JC |
2709 | efx->rx_packet_ts_offset = |
2710 | efx->type->rx_ts_offset - efx->type->rx_prefix_size; | |
8ceee660 BH |
2711 | spin_lock_init(&efx->stats_lock); |
2712 | mutex_init(&efx->mac_lock); | |
2713 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2714 | efx->mdio.dev = net_dev; |
766ca0fa | 2715 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2716 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2717 | |
2718 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2719 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2720 | if (!efx->channel[i]) | |
2721 | goto fail; | |
d8291187 BH |
2722 | efx->msi_context[i].efx = efx; |
2723 | efx->msi_context[i].index = i; | |
8ceee660 BH |
2724 | } |
2725 | ||
8ceee660 BH |
2726 | /* Higher numbered interrupt modes are less capable! */ |
2727 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2728 | interrupt_mode); | |
2729 | ||
6977dc63 BH |
2730 | /* Would be good to use the net_dev name, but we're too early */ |
2731 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2732 | pci_name(pci_dev)); | |
2733 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2734 | if (!efx->workqueue) |
4642610c | 2735 | goto fail; |
8d9853d9 | 2736 | |
8ceee660 | 2737 | return 0; |
4642610c BH |
2738 | |
2739 | fail: | |
2740 | efx_fini_struct(efx); | |
2741 | return -ENOMEM; | |
8ceee660 BH |
2742 | } |
2743 | ||
2744 | static void efx_fini_struct(struct efx_nic *efx) | |
2745 | { | |
8313aca3 BH |
2746 | int i; |
2747 | ||
2748 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2749 | kfree(efx->channel[i]); | |
2750 | ||
ef215e64 BH |
2751 | kfree(efx->vpd_sn); |
2752 | ||
8ceee660 BH |
2753 | if (efx->workqueue) { |
2754 | destroy_workqueue(efx->workqueue); | |
2755 | efx->workqueue = NULL; | |
2756 | } | |
2757 | } | |
2758 | ||
e4d112e4 EC |
2759 | void efx_update_sw_stats(struct efx_nic *efx, u64 *stats) |
2760 | { | |
2761 | u64 n_rx_nodesc_trunc = 0; | |
2762 | struct efx_channel *channel; | |
2763 | ||
2764 | efx_for_each_channel(channel, efx) | |
2765 | n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc; | |
2766 | stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc; | |
2767 | stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops); | |
2768 | } | |
2769 | ||
8ceee660 BH |
2770 | /************************************************************************** |
2771 | * | |
2772 | * PCI interface | |
2773 | * | |
2774 | **************************************************************************/ | |
2775 | ||
2776 | /* Main body of final NIC shutdown code | |
2777 | * This is called only at module unload (or hotplug removal). | |
2778 | */ | |
2779 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2780 | { | |
7153f623 BH |
2781 | /* Flush reset_work. It can no longer be scheduled since we |
2782 | * are not READY. | |
2783 | */ | |
2784 | BUG_ON(efx->state == STATE_READY); | |
2785 | cancel_work_sync(&efx->reset_work); | |
2786 | ||
d8291187 | 2787 | efx_disable_interrupts(efx); |
152b6a62 | 2788 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2789 | efx_fini_port(efx); |
ef2b90ee | 2790 | efx->type->fini(efx); |
8ceee660 BH |
2791 | efx_fini_napi(efx); |
2792 | efx_remove_all(efx); | |
2793 | } | |
2794 | ||
2795 | /* Final NIC shutdown | |
2796 | * This is called only at module unload (or hotplug removal). | |
2797 | */ | |
2798 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2799 | { | |
2800 | struct efx_nic *efx; | |
2801 | ||
2802 | efx = pci_get_drvdata(pci_dev); | |
2803 | if (!efx) | |
2804 | return; | |
2805 | ||
2806 | /* Mark the NIC as fini, then stop the interface */ | |
2807 | rtnl_lock(); | |
0bcf4a64 | 2808 | efx_dissociate(efx); |
8ceee660 | 2809 | dev_close(efx->net_dev); |
d8291187 | 2810 | efx_disable_interrupts(efx); |
8ceee660 BH |
2811 | rtnl_unlock(); |
2812 | ||
7fa8d547 SS |
2813 | if (efx->type->sriov_fini) |
2814 | efx->type->sriov_fini(efx); | |
2815 | ||
8ceee660 BH |
2816 | efx_unregister_netdev(efx); |
2817 | ||
7dde596e BH |
2818 | efx_mtd_remove(efx); |
2819 | ||
8ceee660 BH |
2820 | efx_pci_remove_main(efx); |
2821 | ||
8ceee660 | 2822 | efx_fini_io(efx); |
62776d03 | 2823 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 | 2824 | |
8ceee660 BH |
2825 | efx_fini_struct(efx); |
2826 | free_netdev(efx->net_dev); | |
626950db AR |
2827 | |
2828 | pci_disable_pcie_error_reporting(pci_dev); | |
8ceee660 BH |
2829 | }; |
2830 | ||
460eeaa0 BH |
2831 | /* NIC VPD information |
2832 | * Called during probe to display the part number of the | |
2833 | * installed NIC. VPD is potentially very large but this should | |
2834 | * always appear within the first 512 bytes. | |
2835 | */ | |
2836 | #define SFC_VPD_LEN 512 | |
ef215e64 | 2837 | static void efx_probe_vpd_strings(struct efx_nic *efx) |
460eeaa0 BH |
2838 | { |
2839 | struct pci_dev *dev = efx->pci_dev; | |
2840 | char vpd_data[SFC_VPD_LEN]; | |
2841 | ssize_t vpd_size; | |
ef215e64 | 2842 | int ro_start, ro_size, i, j; |
460eeaa0 BH |
2843 | |
2844 | /* Get the vpd data from the device */ | |
2845 | vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); | |
2846 | if (vpd_size <= 0) { | |
2847 | netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); | |
2848 | return; | |
2849 | } | |
2850 | ||
2851 | /* Get the Read only section */ | |
ef215e64 BH |
2852 | ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); |
2853 | if (ro_start < 0) { | |
460eeaa0 BH |
2854 | netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); |
2855 | return; | |
2856 | } | |
2857 | ||
ef215e64 BH |
2858 | ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); |
2859 | j = ro_size; | |
2860 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
460eeaa0 BH |
2861 | if (i + j > vpd_size) |
2862 | j = vpd_size - i; | |
2863 | ||
2864 | /* Get the Part number */ | |
2865 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); | |
2866 | if (i < 0) { | |
2867 | netif_err(efx, drv, efx->net_dev, "Part number not found\n"); | |
2868 | return; | |
2869 | } | |
2870 | ||
2871 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2872 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2873 | if (i + j > vpd_size) { | |
2874 | netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); | |
2875 | return; | |
2876 | } | |
2877 | ||
2878 | netif_info(efx, drv, efx->net_dev, | |
2879 | "Part Number : %.*s\n", j, &vpd_data[i]); | |
ef215e64 BH |
2880 | |
2881 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
2882 | j = ro_size; | |
2883 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN"); | |
2884 | if (i < 0) { | |
2885 | netif_err(efx, drv, efx->net_dev, "Serial number not found\n"); | |
2886 | return; | |
2887 | } | |
2888 | ||
2889 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2890 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2891 | if (i + j > vpd_size) { | |
2892 | netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n"); | |
2893 | return; | |
2894 | } | |
2895 | ||
2896 | efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL); | |
2897 | if (!efx->vpd_sn) | |
2898 | return; | |
2899 | ||
2900 | snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]); | |
460eeaa0 BH |
2901 | } |
2902 | ||
2903 | ||
8ceee660 BH |
2904 | /* Main body of NIC initialisation |
2905 | * This is called at module load (or hotplug insertion, theoretically). | |
2906 | */ | |
2907 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2908 | { | |
2909 | int rc; | |
2910 | ||
2911 | /* Do start-of-day initialisation */ | |
2912 | rc = efx_probe_all(efx); | |
2913 | if (rc) | |
2914 | goto fail1; | |
2915 | ||
e8f14992 | 2916 | efx_init_napi(efx); |
8ceee660 | 2917 | |
ef2b90ee | 2918 | rc = efx->type->init(efx); |
8ceee660 | 2919 | if (rc) { |
62776d03 BH |
2920 | netif_err(efx, probe, efx->net_dev, |
2921 | "failed to initialise NIC\n"); | |
278c0621 | 2922 | goto fail3; |
8ceee660 BH |
2923 | } |
2924 | ||
2925 | rc = efx_init_port(efx); | |
2926 | if (rc) { | |
62776d03 BH |
2927 | netif_err(efx, probe, efx->net_dev, |
2928 | "failed to initialise port\n"); | |
278c0621 | 2929 | goto fail4; |
8ceee660 BH |
2930 | } |
2931 | ||
152b6a62 | 2932 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2933 | if (rc) |
278c0621 | 2934 | goto fail5; |
261e4d96 JC |
2935 | rc = efx_enable_interrupts(efx); |
2936 | if (rc) | |
2937 | goto fail6; | |
8ceee660 BH |
2938 | |
2939 | return 0; | |
2940 | ||
261e4d96 JC |
2941 | fail6: |
2942 | efx_nic_fini_interrupt(efx); | |
278c0621 | 2943 | fail5: |
8ceee660 | 2944 | efx_fini_port(efx); |
8ceee660 | 2945 | fail4: |
ef2b90ee | 2946 | efx->type->fini(efx); |
8ceee660 BH |
2947 | fail3: |
2948 | efx_fini_napi(efx); | |
8ceee660 BH |
2949 | efx_remove_all(efx); |
2950 | fail1: | |
2951 | return rc; | |
2952 | } | |
2953 | ||
2954 | /* NIC initialisation | |
2955 | * | |
2956 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2957 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2958 | * sets up and registers the network devices with the kernel and hooks |
2959 | * the interrupt service routine. It does not prepare the device for | |
2960 | * transmission; this is left to the first time one of the network | |
2961 | * interfaces is brought up (i.e. efx_net_open). | |
2962 | */ | |
87d1fc11 | 2963 | static int efx_pci_probe(struct pci_dev *pci_dev, |
1dd06ae8 | 2964 | const struct pci_device_id *entry) |
8ceee660 | 2965 | { |
8ceee660 BH |
2966 | struct net_device *net_dev; |
2967 | struct efx_nic *efx; | |
fadac6aa | 2968 | int rc; |
8ceee660 BH |
2969 | |
2970 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2971 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2972 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2973 | if (!net_dev) |
2974 | return -ENOMEM; | |
adeb15aa BH |
2975 | efx = netdev_priv(net_dev); |
2976 | efx->type = (const struct efx_nic_type *) entry->driver_data; | |
2977 | net_dev->features |= (efx->type->offload_features | NETIF_F_SG | | |
97bc5415 | 2978 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2979 | NETIF_F_RXCSUM); |
adeb15aa | 2980 | if (efx->type->offload_features & NETIF_F_V6_CSUM) |
738a8f4b | 2981 | net_dev->features |= NETIF_F_TSO6; |
28506563 BH |
2982 | /* Mask for features that also apply to VLAN devices */ |
2983 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2984 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2985 | NETIF_F_RXCSUM); | |
2986 | /* All offloads can be toggled */ | |
2987 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
8ceee660 | 2988 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2989 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
adeb15aa | 2990 | rc = efx_init_struct(efx, pci_dev, net_dev); |
8ceee660 BH |
2991 | if (rc) |
2992 | goto fail1; | |
2993 | ||
62776d03 | 2994 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2995 | "Solarflare NIC detected\n"); |
8ceee660 | 2996 | |
ef215e64 | 2997 | efx_probe_vpd_strings(efx); |
460eeaa0 | 2998 | |
8ceee660 BH |
2999 | /* Set up basic I/O (BAR mappings etc) */ |
3000 | rc = efx_init_io(efx); | |
3001 | if (rc) | |
3002 | goto fail2; | |
3003 | ||
fadac6aa | 3004 | rc = efx_pci_probe_main(efx); |
fadac6aa BH |
3005 | if (rc) |
3006 | goto fail3; | |
8ceee660 | 3007 | |
8ceee660 BH |
3008 | rc = efx_register_netdev(efx); |
3009 | if (rc) | |
fadac6aa | 3010 | goto fail4; |
8ceee660 | 3011 | |
7fa8d547 SS |
3012 | if (efx->type->sriov_init) { |
3013 | rc = efx->type->sriov_init(efx); | |
3014 | if (rc) | |
3015 | netif_err(efx, probe, efx->net_dev, | |
3016 | "SR-IOV can't be enabled rc %d\n", rc); | |
3017 | } | |
cd2d5b52 | 3018 | |
62776d03 | 3019 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 3020 | |
7c43161c | 3021 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 3022 | rtnl_lock(); |
7c43161c | 3023 | rc = efx_mtd_probe(efx); |
a5211bb5 | 3024 | rtnl_unlock(); |
7c43161c BH |
3025 | if (rc) |
3026 | netif_warn(efx, probe, efx->net_dev, | |
3027 | "failed to create MTDs (%d)\n", rc); | |
3028 | ||
626950db AR |
3029 | rc = pci_enable_pcie_error_reporting(pci_dev); |
3030 | if (rc && rc != -EINVAL) | |
3031 | netif_warn(efx, probe, efx->net_dev, | |
3032 | "pci_enable_pcie_error_reporting failed (%d)\n", rc); | |
3033 | ||
8ceee660 BH |
3034 | return 0; |
3035 | ||
8ceee660 | 3036 | fail4: |
fadac6aa | 3037 | efx_pci_remove_main(efx); |
8ceee660 BH |
3038 | fail3: |
3039 | efx_fini_io(efx); | |
3040 | fail2: | |
3041 | efx_fini_struct(efx); | |
3042 | fail1: | |
5e2a911c | 3043 | WARN_ON(rc > 0); |
62776d03 | 3044 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
3045 | free_netdev(net_dev); |
3046 | return rc; | |
3047 | } | |
3048 | ||
89c758fa BH |
3049 | static int efx_pm_freeze(struct device *dev) |
3050 | { | |
3051 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
3052 | ||
61da026d BH |
3053 | rtnl_lock(); |
3054 | ||
6032fb56 BH |
3055 | if (efx->state != STATE_DISABLED) { |
3056 | efx->state = STATE_UNINIT; | |
89c758fa | 3057 | |
c2f3b8e3 | 3058 | efx_device_detach_sync(efx); |
89c758fa | 3059 | |
6032fb56 | 3060 | efx_stop_all(efx); |
d8291187 | 3061 | efx_disable_interrupts(efx); |
6032fb56 | 3062 | } |
89c758fa | 3063 | |
61da026d BH |
3064 | rtnl_unlock(); |
3065 | ||
89c758fa BH |
3066 | return 0; |
3067 | } | |
3068 | ||
3069 | static int efx_pm_thaw(struct device *dev) | |
3070 | { | |
261e4d96 | 3071 | int rc; |
89c758fa BH |
3072 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); |
3073 | ||
61da026d BH |
3074 | rtnl_lock(); |
3075 | ||
6032fb56 | 3076 | if (efx->state != STATE_DISABLED) { |
261e4d96 JC |
3077 | rc = efx_enable_interrupts(efx); |
3078 | if (rc) | |
3079 | goto fail; | |
89c758fa | 3080 | |
6032fb56 BH |
3081 | mutex_lock(&efx->mac_lock); |
3082 | efx->phy_op->reconfigure(efx); | |
3083 | mutex_unlock(&efx->mac_lock); | |
89c758fa | 3084 | |
6032fb56 | 3085 | efx_start_all(efx); |
89c758fa | 3086 | |
6032fb56 | 3087 | netif_device_attach(efx->net_dev); |
89c758fa | 3088 | |
6032fb56 | 3089 | efx->state = STATE_READY; |
89c758fa | 3090 | |
6032fb56 BH |
3091 | efx->type->resume_wol(efx); |
3092 | } | |
89c758fa | 3093 | |
61da026d BH |
3094 | rtnl_unlock(); |
3095 | ||
319ba649 SH |
3096 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
3097 | queue_work(reset_workqueue, &efx->reset_work); | |
3098 | ||
89c758fa | 3099 | return 0; |
261e4d96 JC |
3100 | |
3101 | fail: | |
3102 | rtnl_unlock(); | |
3103 | ||
3104 | return rc; | |
89c758fa BH |
3105 | } |
3106 | ||
3107 | static int efx_pm_poweroff(struct device *dev) | |
3108 | { | |
3109 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
3110 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
3111 | ||
3112 | efx->type->fini(efx); | |
3113 | ||
a7d529ae | 3114 | efx->reset_pending = 0; |
89c758fa BH |
3115 | |
3116 | pci_save_state(pci_dev); | |
3117 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
3118 | } | |
3119 | ||
3120 | /* Used for both resume and restore */ | |
3121 | static int efx_pm_resume(struct device *dev) | |
3122 | { | |
3123 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
3124 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
3125 | int rc; | |
3126 | ||
3127 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
3128 | if (rc) | |
3129 | return rc; | |
3130 | pci_restore_state(pci_dev); | |
3131 | rc = pci_enable_device(pci_dev); | |
3132 | if (rc) | |
3133 | return rc; | |
3134 | pci_set_master(efx->pci_dev); | |
3135 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
3136 | if (rc) | |
3137 | return rc; | |
3138 | rc = efx->type->init(efx); | |
3139 | if (rc) | |
3140 | return rc; | |
261e4d96 JC |
3141 | rc = efx_pm_thaw(dev); |
3142 | return rc; | |
89c758fa BH |
3143 | } |
3144 | ||
3145 | static int efx_pm_suspend(struct device *dev) | |
3146 | { | |
3147 | int rc; | |
3148 | ||
3149 | efx_pm_freeze(dev); | |
3150 | rc = efx_pm_poweroff(dev); | |
3151 | if (rc) | |
3152 | efx_pm_resume(dev); | |
3153 | return rc; | |
3154 | } | |
3155 | ||
18e83e4c | 3156 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
3157 | .suspend = efx_pm_suspend, |
3158 | .resume = efx_pm_resume, | |
3159 | .freeze = efx_pm_freeze, | |
3160 | .thaw = efx_pm_thaw, | |
3161 | .poweroff = efx_pm_poweroff, | |
3162 | .restore = efx_pm_resume, | |
3163 | }; | |
3164 | ||
626950db AR |
3165 | /* A PCI error affecting this device was detected. |
3166 | * At this point MMIO and DMA may be disabled. | |
3167 | * Stop the software path and request a slot reset. | |
3168 | */ | |
debd0034 | 3169 | static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev, |
3170 | enum pci_channel_state state) | |
626950db AR |
3171 | { |
3172 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3173 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3174 | ||
3175 | if (state == pci_channel_io_perm_failure) | |
3176 | return PCI_ERS_RESULT_DISCONNECT; | |
3177 | ||
3178 | rtnl_lock(); | |
3179 | ||
3180 | if (efx->state != STATE_DISABLED) { | |
3181 | efx->state = STATE_RECOVERY; | |
3182 | efx->reset_pending = 0; | |
3183 | ||
3184 | efx_device_detach_sync(efx); | |
3185 | ||
3186 | efx_stop_all(efx); | |
d8291187 | 3187 | efx_disable_interrupts(efx); |
626950db AR |
3188 | |
3189 | status = PCI_ERS_RESULT_NEED_RESET; | |
3190 | } else { | |
3191 | /* If the interface is disabled we don't want to do anything | |
3192 | * with it. | |
3193 | */ | |
3194 | status = PCI_ERS_RESULT_RECOVERED; | |
3195 | } | |
3196 | ||
3197 | rtnl_unlock(); | |
3198 | ||
3199 | pci_disable_device(pdev); | |
3200 | ||
3201 | return status; | |
3202 | } | |
3203 | ||
dbedd44e | 3204 | /* Fake a successful reset, which will be performed later in efx_io_resume. */ |
debd0034 | 3205 | static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev) |
626950db AR |
3206 | { |
3207 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3208 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3209 | int rc; | |
3210 | ||
3211 | if (pci_enable_device(pdev)) { | |
3212 | netif_err(efx, hw, efx->net_dev, | |
3213 | "Cannot re-enable PCI device after reset.\n"); | |
3214 | status = PCI_ERS_RESULT_DISCONNECT; | |
3215 | } | |
3216 | ||
3217 | rc = pci_cleanup_aer_uncorrect_error_status(pdev); | |
3218 | if (rc) { | |
3219 | netif_err(efx, hw, efx->net_dev, | |
3220 | "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc); | |
3221 | /* Non-fatal error. Continue. */ | |
3222 | } | |
3223 | ||
3224 | return status; | |
3225 | } | |
3226 | ||
3227 | /* Perform the actual reset and resume I/O operations. */ | |
3228 | static void efx_io_resume(struct pci_dev *pdev) | |
3229 | { | |
3230 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3231 | int rc; | |
3232 | ||
3233 | rtnl_lock(); | |
3234 | ||
3235 | if (efx->state == STATE_DISABLED) | |
3236 | goto out; | |
3237 | ||
3238 | rc = efx_reset(efx, RESET_TYPE_ALL); | |
3239 | if (rc) { | |
3240 | netif_err(efx, hw, efx->net_dev, | |
3241 | "efx_reset failed after PCI error (%d)\n", rc); | |
3242 | } else { | |
3243 | efx->state = STATE_READY; | |
3244 | netif_dbg(efx, hw, efx->net_dev, | |
3245 | "Done resetting and resuming IO after PCI error.\n"); | |
3246 | } | |
3247 | ||
3248 | out: | |
3249 | rtnl_unlock(); | |
3250 | } | |
3251 | ||
3252 | /* For simplicity and reliability, we always require a slot reset and try to | |
3253 | * reset the hardware when a pci error affecting the device is detected. | |
3254 | * We leave both the link_reset and mmio_enabled callback unimplemented: | |
3255 | * with our request for slot reset the mmio_enabled callback will never be | |
3256 | * called, and the link_reset callback is not used by AER or EEH mechanisms. | |
3257 | */ | |
3258 | static struct pci_error_handlers efx_err_handlers = { | |
3259 | .error_detected = efx_io_error_detected, | |
3260 | .slot_reset = efx_io_slot_reset, | |
3261 | .resume = efx_io_resume, | |
3262 | }; | |
3263 | ||
8ceee660 | 3264 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 3265 | .name = KBUILD_MODNAME, |
8ceee660 BH |
3266 | .id_table = efx_pci_table, |
3267 | .probe = efx_pci_probe, | |
3268 | .remove = efx_pci_remove, | |
89c758fa | 3269 | .driver.pm = &efx_pm_ops, |
626950db | 3270 | .err_handler = &efx_err_handlers, |
8ceee660 BH |
3271 | }; |
3272 | ||
3273 | /************************************************************************** | |
3274 | * | |
3275 | * Kernel module interface | |
3276 | * | |
3277 | *************************************************************************/ | |
3278 | ||
3279 | module_param(interrupt_mode, uint, 0444); | |
3280 | MODULE_PARM_DESC(interrupt_mode, | |
3281 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
3282 | ||
3283 | static int __init efx_init_module(void) | |
3284 | { | |
3285 | int rc; | |
3286 | ||
3287 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
3288 | ||
3289 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
3290 | if (rc) | |
3291 | goto err_notifier; | |
3292 | ||
7fa8d547 | 3293 | #ifdef CONFIG_SFC_SRIOV |
cd2d5b52 BH |
3294 | rc = efx_init_sriov(); |
3295 | if (rc) | |
3296 | goto err_sriov; | |
7fa8d547 | 3297 | #endif |
cd2d5b52 | 3298 | |
1ab00629 SH |
3299 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
3300 | if (!reset_workqueue) { | |
3301 | rc = -ENOMEM; | |
3302 | goto err_reset; | |
3303 | } | |
8ceee660 BH |
3304 | |
3305 | rc = pci_register_driver(&efx_pci_driver); | |
3306 | if (rc < 0) | |
3307 | goto err_pci; | |
3308 | ||
3309 | return 0; | |
3310 | ||
3311 | err_pci: | |
1ab00629 SH |
3312 | destroy_workqueue(reset_workqueue); |
3313 | err_reset: | |
7fa8d547 | 3314 | #ifdef CONFIG_SFC_SRIOV |
cd2d5b52 BH |
3315 | efx_fini_sriov(); |
3316 | err_sriov: | |
7fa8d547 | 3317 | #endif |
8ceee660 BH |
3318 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3319 | err_notifier: | |
3320 | return rc; | |
3321 | } | |
3322 | ||
3323 | static void __exit efx_exit_module(void) | |
3324 | { | |
3325 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
3326 | ||
3327 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 3328 | destroy_workqueue(reset_workqueue); |
7fa8d547 | 3329 | #ifdef CONFIG_SFC_SRIOV |
cd2d5b52 | 3330 | efx_fini_sriov(); |
7fa8d547 | 3331 | #endif |
8ceee660 BH |
3332 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3333 | ||
3334 | } | |
3335 | ||
3336 | module_init(efx_init_module); | |
3337 | module_exit(efx_exit_module); | |
3338 | ||
906bb26c BH |
3339 | MODULE_AUTHOR("Solarflare Communications and " |
3340 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
6a350fdb | 3341 | MODULE_DESCRIPTION("Solarflare network driver"); |
8ceee660 BH |
3342 | MODULE_LICENSE("GPL"); |
3343 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |