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sfc: Maintain current frequency adjustment when applying a time offset
[deliverable/linux.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660 1/****************************************************************************
f7a6d2c4 2 * Driver for Solarflare network controllers and boards
8ceee660 3 * Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4 4 * Copyright 2005-2013 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
8ceee660 20#include <linux/ethtool.h>
aa6ef27e 21#include <linux/topology.h>
5a0e3ad6 22#include <linux/gfp.h>
626950db 23#include <linux/aer.h>
b28405b0 24#include <linux/interrupt.h>
8ceee660 25#include "net_driver.h"
8ceee660 26#include "efx.h"
744093c9 27#include "nic.h"
dd40781e 28#include "selftest.h"
8ceee660 29
8880f4ec 30#include "mcdi.h"
fd371e32 31#include "workarounds.h"
8880f4ec 32
c459302d
BH		 33/**************************************************************************
34 *
35 * Type name strings
36 *
37 **************************************************************************
38 */
39
40/* Loopback mode names (see LOOPBACK_MODE()) */
41const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 42const char *const efx_loopback_mode_names[] = {
c459302d 43 [LOOPBACK_NONE] = "NONE",
e58f69f4 44 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 45 [LOOPBACK_GMAC] = "GMAC",
46 [LOOPBACK_XGMII] = "XGMII",
47 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH		 48 [LOOPBACK_XAUI] = "XAUI",
49 [LOOPBACK_GMII] = "GMII",
50 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH		 51 [LOOPBACK_XGBR] = "XGBR",
52 [LOOPBACK_XFI] = "XFI",
53 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
54 [LOOPBACK_GMII_FAR] = "GMII_FAR",
55 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
56 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 57 [LOOPBACK_GPHY] = "GPHY",
58 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH		 59 [LOOPBACK_PCS] = "PCS",
60 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 61 [LOOPBACK_XPORT] = "XPORT",
62 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 63 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH		 64 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
65 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 66 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH		 67 [LOOPBACK_XFI_WS] = "XFI_WS",
68 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 69 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 70};
71
c459302d 72const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 73const char *const efx_reset_type_names[] = {
626950db
AR		 74 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
75 [RESET_TYPE_ALL] = "ALL",
76 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
77 [RESET_TYPE_WORLD] = "WORLD",
78 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
79 [RESET_TYPE_DISABLE] = "DISABLE",
80 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
81 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
82 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
3de82b91 83 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
626950db
AR		 84 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
85 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
c459302d
BH		 86};
87
1ab00629
SH		 88/* Reset workqueue. If any NIC has a hardware failure then a reset will be
89 * queued onto this work queue. This is not a per-nic work queue, because
90 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
91 */
92static struct workqueue_struct *reset_workqueue;
93
8ceee660
BH		 94/**************************************************************************
95 *
96 * Configurable values
97 *
98 *************************************************************************/
99
8ceee660
BH		 100/*
101 * Use separate channels for TX and RX events
102 *
28b581ab
NT		 103 * Set this to 1 to use separate channels for TX and RX. It allows us
104 * to control interrupt affinity separately for TX and RX.
8ceee660 105 *
28b581ab 106 * This is only used in MSI-X interrupt mode
8ceee660 107 */
b9cc977d
BH		 108static bool separate_tx_channels;
109module_param(separate_tx_channels, bool, 0444);
28b581ab
NT		 110MODULE_PARM_DESC(separate_tx_channels,
111 "Use separate channels for TX and RX");
8ceee660
BH		 112
113/* This is the weight assigned to each of the (per-channel) virtual
114 * NAPI devices.
115 */
116static int napi_weight = 64;
117
118/* This is the time (in jiffies) between invocations of the hardware
626950db
AR		 119 * monitor.
120 * On Falcon-based NICs, this will:
e254c274
BH		 121 * - Check the on-board hardware monitor;
122 * - Poll the link state and reconfigure the hardware as necessary.
626950db
AR		 123 * On Siena-based NICs for power systems with EEH support, this will give EEH a
124 * chance to start.
8ceee660 125 */
d215697f 126static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 127
8ceee660
BH		 128/* Initial interrupt moderation settings. They can be modified after
129 * module load with ethtool.
130 *
131 * The default for RX should strike a balance between increasing the
132 * round-trip latency and reducing overhead.
133 */
134static unsigned int rx_irq_mod_usec = 60;
135
136/* Initial interrupt moderation settings. They can be modified after
137 * module load with ethtool.
138 *
139 * This default is chosen to ensure that a 10G link does not go idle
140 * while a TX queue is stopped after it has become full. A queue is
141 * restarted when it drops below half full. The time this takes (assuming
142 * worst case 3 descriptors per packet and 1024 descriptors) is
143 * 512 / 3 * 1.2 = 205 usec.
144 */
145static unsigned int tx_irq_mod_usec = 150;
146
147/* This is the first interrupt mode to try out of:
148 * 0 => MSI-X
149 * 1 => MSI
150 * 2 => legacy
151 */
152static unsigned int interrupt_mode;
153
154/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
155 * i.e. the number of CPUs among which we may distribute simultaneous
156 * interrupt handling.
157 *
158 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 159 * The default (0) means to assign an interrupt to each core.
8ceee660
BH		 160 */
161static unsigned int rss_cpus;
162module_param(rss_cpus, uint, 0444);
163MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
164
b9cc977d
BH		 165static bool phy_flash_cfg;
166module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH		 167MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
168
e7bed9c8 169static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH		 170module_param(irq_adapt_low_thresh, uint, 0644);
171MODULE_PARM_DESC(irq_adapt_low_thresh,
172 "Threshold score for reducing IRQ moderation");
173
e7bed9c8 174static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH		 175module_param(irq_adapt_high_thresh, uint, 0644);
176MODULE_PARM_DESC(irq_adapt_high_thresh,
177 "Threshold score for increasing IRQ moderation");
178
62776d03
BH		 179static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
180 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
181 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
182 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
183module_param(debug, uint, 0);
184MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
185
8ceee660
BH		 186/**************************************************************************
187 *
188 * Utility functions and prototypes
189 *
190 *************************************************************************/
4642610c 191
261e4d96 192static int efx_soft_enable_interrupts(struct efx_nic *efx);
d8291187 193static void efx_soft_disable_interrupts(struct efx_nic *efx);
7f967c01 194static void efx_remove_channel(struct efx_channel *channel);
4642610c 195static void efx_remove_channels(struct efx_nic *efx);
7f967c01 196static const struct efx_channel_type efx_default_channel_type;
8ceee660 197static void efx_remove_port(struct efx_nic *efx);
7f967c01 198static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 199static void efx_fini_napi(struct efx_nic *efx);
e8f14992 200static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH		 201static void efx_fini_struct(struct efx_nic *efx);
202static void efx_start_all(struct efx_nic *efx);
203static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH		 204
205#define EFX_ASSERT_RESET_SERIALISED(efx) \
206 do { \
f16aeea0 207 if ((efx->state == STATE_READY) || \
626950db 208 (efx->state == STATE_RECOVERY) || \
332c1ce9 209 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 210 ASSERT_RTNL(); \
211 } while (0)
212
8b7325b4
BH		 213static int efx_check_disabled(struct efx_nic *efx)
214{
626950db 215 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
8b7325b4
BH		 216 netif_err(efx, drv, efx->net_dev,
217 "device is disabled due to earlier errors\n");
218 return -EIO;
219 }
220 return 0;
221}
222
8ceee660
BH		 223/**************************************************************************
224 *
225 * Event queue processing
226 *
227 *************************************************************************/
228
229/* Process channel's event queue
230 *
231 * This function is responsible for processing the event queue of a
232 * single channel. The caller must guarantee that this function will
233 * never be concurrently called more than once on the same channel,
234 * though different channels may be being processed concurrently.
235 */
fa236e18 236static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 237{
fa236e18 238 int spent;
8ceee660 239
9f2cb71c 240 if (unlikely(!channel->enabled))
42cbe2d7 241 return 0;
8ceee660 242
fa236e18 243 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH		 244 if (spent && efx_channel_has_rx_queue(channel)) {
245 struct efx_rx_queue *rx_queue =
246 efx_channel_get_rx_queue(channel);
247
ff734ef4 248 efx_rx_flush_packet(channel);
d8aec745 249 efx_fast_push_rx_descriptors(rx_queue);
8ceee660
BH		 250 }
251
fa236e18 252 return spent;
8ceee660
BH		 253}
254
8ceee660
BH		 255/* NAPI poll handler
256 *
257 * NAPI guarantees serialisation of polls of the same device, which
258 * provides the guarantee required by efx_process_channel().
259 */
260static int efx_poll(struct napi_struct *napi, int budget)
261{
262 struct efx_channel *channel =
263 container_of(napi, struct efx_channel, napi_str);
62776d03 264 struct efx_nic *efx = channel->efx;
fa236e18 265 int spent;
8ceee660 266
62776d03
BH		 267 netif_vdbg(efx, intr, efx->net_dev,
268 "channel %d NAPI poll executing on CPU %d\n",
269 channel->channel, raw_smp_processor_id());
8ceee660 270
fa236e18 271 spent = efx_process_channel(channel, budget);
8ceee660 272
fa236e18 273 if (spent < budget) {
9d9a6973 274 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH		 275 efx->irq_rx_adaptive &&
276 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH		 277 if (unlikely(channel->irq_mod_score <
278 irq_adapt_low_thresh)) {
0d86ebd8
BH		 279 if (channel->irq_moderation > 1) {
280 channel->irq_moderation -= 1;
ef2b90ee 281 efx->type->push_irq_moderation(channel);
0d86ebd8 282 }
6fb70fd1
BH		 283 } else if (unlikely(channel->irq_mod_score >
284 irq_adapt_high_thresh)) {
0d86ebd8
BH		 285 if (channel->irq_moderation <
286 efx->irq_rx_moderation) {
287 channel->irq_moderation += 1;
ef2b90ee 288 efx->type->push_irq_moderation(channel);
0d86ebd8 289 }
6fb70fd1 290 }
6fb70fd1
BH		 291 channel->irq_count = 0;
292 channel->irq_mod_score = 0;
293 }
294
64d8ad6d
BH		 295 efx_filter_rfs_expire(channel);
296
8ceee660 297 /* There is no race here; although napi_disable() will
288379f0 298 * only wait for napi_complete(), this isn't a problem
514bedbc 299 * since efx_nic_eventq_read_ack() will have no effect if
8ceee660
BH		 300 * interrupts have already been disabled.
301 */
288379f0 302 napi_complete(napi);
514bedbc 303 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 304 }
305
fa236e18 306 return spent;
8ceee660
BH		 307}
308
8ceee660
BH		 309/* Create event queue
310 * Event queue memory allocations are done only once. If the channel
311 * is reset, the memory buffer will be reused; this guards against
312 * errors during channel reset and also simplifies interrupt handling.
313 */
314static int efx_probe_eventq(struct efx_channel *channel)
315{
ecc910f5
SH		 316 struct efx_nic *efx = channel->efx;
317 unsigned long entries;
318
86ee5302 319 netif_dbg(efx, probe, efx->net_dev,
62776d03 320 "chan %d create event queue\n", channel->channel);
8ceee660 321
ecc910f5
SH		 322 /* Build an event queue with room for one event per tx and rx buffer,
323 * plus some extra for link state events and MCDI completions. */
324 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
325 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
326 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
327
152b6a62 328 return efx_nic_probe_eventq(channel);
8ceee660
BH		 329}
330
331/* Prepare channel's event queue */
261e4d96 332static int efx_init_eventq(struct efx_channel *channel)
8ceee660 333{
15acb1ce 334 struct efx_nic *efx = channel->efx;
261e4d96
JC		 335 int rc;
336
337 EFX_WARN_ON_PARANOID(channel->eventq_init);
338
15acb1ce 339 netif_dbg(efx, drv, efx->net_dev,
62776d03 340 "chan %d init event queue\n", channel->channel);
8ceee660 341
261e4d96
JC		 342 rc = efx_nic_init_eventq(channel);
343 if (rc == 0) {
15acb1ce 344 efx->type->push_irq_moderation(channel);
261e4d96
JC		 345 channel->eventq_read_ptr = 0;
346 channel->eventq_init = true;
347 }
348 return rc;
8ceee660
BH		 349}
350
9f2cb71c
BH		 351/* Enable event queue processing and NAPI */
352static void efx_start_eventq(struct efx_channel *channel)
353{
354 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
355 "chan %d start event queue\n", channel->channel);
356
514bedbc 357 /* Make sure the NAPI handler sees the enabled flag set */
9f2cb71c
BH		 358 channel->enabled = true;
359 smp_wmb();
360
361 napi_enable(&channel->napi_str);
362 efx_nic_eventq_read_ack(channel);
363}
364
365/* Disable event queue processing and NAPI */
366static void efx_stop_eventq(struct efx_channel *channel)
367{
368 if (!channel->enabled)
369 return;
370
371 napi_disable(&channel->napi_str);
372 channel->enabled = false;
373}
374
8ceee660
BH		 375static void efx_fini_eventq(struct efx_channel *channel)
376{
be3fc09c
BH		 377 if (!channel->eventq_init)
378 return;
379
62776d03
BH		 380 netif_dbg(channel->efx, drv, channel->efx->net_dev,
381 "chan %d fini event queue\n", channel->channel);
8ceee660 382
152b6a62 383 efx_nic_fini_eventq(channel);
be3fc09c 384 channel->eventq_init = false;
8ceee660
BH		 385}
386
387static void efx_remove_eventq(struct efx_channel *channel)
388{
62776d03
BH		 389 netif_dbg(channel->efx, drv, channel->efx->net_dev,
390 "chan %d remove event queue\n", channel->channel);
8ceee660 391
152b6a62 392 efx_nic_remove_eventq(channel);
8ceee660
BH		 393}
394
395/**************************************************************************
396 *
397 * Channel handling
398 *
399 *************************************************************************/
400
7f967c01 401/* Allocate and initialise a channel structure. */
4642610c
BH		 402static struct efx_channel *
403efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
404{
405 struct efx_channel *channel;
406 struct efx_rx_queue *rx_queue;
407 struct efx_tx_queue *tx_queue;
408 int j;
409
7f967c01
BH		 410 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
411 if (!channel)
412 return NULL;
4642610c 413
7f967c01
BH		 414 channel->efx = efx;
415 channel->channel = i;
416 channel->type = &efx_default_channel_type;
4642610c 417
7f967c01
BH		 418 for (j = 0; j < EFX_TXQ_TYPES; j++) {
419 tx_queue = &channel->tx_queue[j];
420 tx_queue->efx = efx;
421 tx_queue->queue = i * EFX_TXQ_TYPES + j;
422 tx_queue->channel = channel;
423 }
4642610c 424
7f967c01
BH		 425 rx_queue = &channel->rx_queue;
426 rx_queue->efx = efx;
427 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
428 (unsigned long)rx_queue);
4642610c 429
7f967c01
BH		 430 return channel;
431}
432
433/* Allocate and initialise a channel structure, copying parameters
434 * (but not resources) from an old channel structure.
435 */
436static struct efx_channel *
437efx_copy_channel(const struct efx_channel *old_channel)
438{
439 struct efx_channel *channel;
440 struct efx_rx_queue *rx_queue;
441 struct efx_tx_queue *tx_queue;
442 int j;
4642610c 443
7f967c01
BH		 444 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
445 if (!channel)
446 return NULL;
447
448 *channel = *old_channel;
449
450 channel->napi_dev = NULL;
451 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 452
7f967c01
BH		 453 for (j = 0; j < EFX_TXQ_TYPES; j++) {
454 tx_queue = &channel->tx_queue[j];
455 if (tx_queue->channel)
4642610c 456 tx_queue->channel = channel;
7f967c01
BH		 457 tx_queue->buffer = NULL;
458 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH		 459 }
460
4642610c 461 rx_queue = &channel->rx_queue;
7f967c01
BH		 462 rx_queue->buffer = NULL;
463 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH		 464 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
465 (unsigned long)rx_queue);
466
467 return channel;
468}
469
8ceee660
BH		 470static int efx_probe_channel(struct efx_channel *channel)
471{
472 struct efx_tx_queue *tx_queue;
473 struct efx_rx_queue *rx_queue;
474 int rc;
475
62776d03
BH		 476 netif_dbg(channel->efx, probe, channel->efx->net_dev,
477 "creating channel %d\n", channel->channel);
8ceee660 478
7f967c01
BH		 479 rc = channel->type->pre_probe(channel);
480 if (rc)
481 goto fail;
482
8ceee660
BH		 483 rc = efx_probe_eventq(channel);
484 if (rc)
7f967c01 485 goto fail;
8ceee660
BH		 486
487 efx_for_each_channel_tx_queue(tx_queue, channel) {
488 rc = efx_probe_tx_queue(tx_queue);
489 if (rc)
7f967c01 490 goto fail;
8ceee660
BH		 491 }
492
493 efx_for_each_channel_rx_queue(rx_queue, channel) {
494 rc = efx_probe_rx_queue(rx_queue);
495 if (rc)
7f967c01 496 goto fail;
8ceee660
BH		 497 }
498
499 channel->n_rx_frm_trunc = 0;
500
501 return 0;
502
7f967c01
BH		 503fail:
504 efx_remove_channel(channel);
8ceee660
BH		 505 return rc;
506}
507
7f967c01
BH		 508static void
509efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
510{
511 struct efx_nic *efx = channel->efx;
512 const char *type;
513 int number;
514
515 number = channel->channel;
516 if (efx->tx_channel_offset == 0) {
517 type = "";
518 } else if (channel->channel < efx->tx_channel_offset) {
519 type = "-rx";
520 } else {
521 type = "-tx";
522 number -= efx->tx_channel_offset;
523 }
524 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
525}
8ceee660 526
56536e9c
BH		 527static void efx_set_channel_names(struct efx_nic *efx)
528{
529 struct efx_channel *channel;
56536e9c 530
7f967c01
BH		 531 efx_for_each_channel(channel, efx)
532 channel->type->get_name(channel,
d8291187
BH		 533 efx->msi_context[channel->channel].name,
534 sizeof(efx->msi_context[0].name));
56536e9c
BH		 535}
536
4642610c
BH		 537static int efx_probe_channels(struct efx_nic *efx)
538{
539 struct efx_channel *channel;
540 int rc;
541
542 /* Restart special buffer allocation */
543 efx->next_buffer_table = 0;
544
c92aaff1
BH		 545 /* Probe channels in reverse, so that any 'extra' channels
546 * use the start of the buffer table. This allows the traffic
547 * channels to be resized without moving them or wasting the
548 * entries before them.
549 */
550 efx_for_each_channel_rev(channel, efx) {
4642610c
BH		 551 rc = efx_probe_channel(channel);
552 if (rc) {
553 netif_err(efx, probe, efx->net_dev,
554 "failed to create channel %d\n",
555 channel->channel);
556 goto fail;
557 }
558 }
559 efx_set_channel_names(efx);
560
561 return 0;
562
563fail:
564 efx_remove_channels(efx);
565 return rc;
566}
567
8ceee660
BH		 568/* Channels are shutdown and reinitialised whilst the NIC is running
569 * to propagate configuration changes (mtu, checksum offload), or
570 * to clear hardware error conditions
571 */
9f2cb71c 572static void efx_start_datapath(struct efx_nic *efx)
8ceee660 573{
85740cdf 574 bool old_rx_scatter = efx->rx_scatter;
8ceee660
BH		 575 struct efx_tx_queue *tx_queue;
576 struct efx_rx_queue *rx_queue;
577 struct efx_channel *channel;
85740cdf 578 size_t rx_buf_len;
8ceee660 579
f7f13b0b
BH		 580 /* Calculate the rx buffer allocation parameters required to
581 * support the current MTU, including padding for header
582 * alignment and overruns.
583 */
43a3739d 584 efx->rx_dma_len = (efx->rx_prefix_size +
272baeeb
BH		 585 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
586 efx->type->rx_buffer_padding);
85740cdf 587 rx_buf_len = (sizeof(struct efx_rx_page_state) +
c14ff2ea 588 NET_IP_ALIGN + efx->rx_dma_len);
85740cdf 589 if (rx_buf_len <= PAGE_SIZE) {
e8c68c0a 590 efx->rx_scatter = efx->type->always_rx_scatter;
85740cdf 591 efx->rx_buffer_order = 0;
85740cdf 592 } else if (efx->type->can_rx_scatter) {
950c54df 593 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
85740cdf 594 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
950c54df
BH		 595 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
596 EFX_RX_BUF_ALIGNMENT) >
597 PAGE_SIZE);
85740cdf
BH		 598 efx->rx_scatter = true;
599 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
600 efx->rx_buffer_order = 0;
85740cdf
BH		 601 } else {
602 efx->rx_scatter = false;
603 efx->rx_buffer_order = get_order(rx_buf_len);
85740cdf
BH		 604 }
605
1648a23f
DP		 606 efx_rx_config_page_split(efx);
607 if (efx->rx_buffer_order)
608 netif_dbg(efx, drv, efx->net_dev,
609 "RX buf len=%u; page order=%u batch=%u\n",
610 efx->rx_dma_len, efx->rx_buffer_order,
611 efx->rx_pages_per_batch);
612 else
613 netif_dbg(efx, drv, efx->net_dev,
614 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
615 efx->rx_dma_len, efx->rx_page_buf_step,
616 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
2768935a 617
e8c68c0a 618 /* RX filters may also have scatter-enabled flags */
85740cdf 619 if (efx->rx_scatter != old_rx_scatter)
add72477 620 efx->type->filter_update_rx_scatter(efx);
8ceee660 621
14bf718f
BH		 622 /* We must keep at least one descriptor in a TX ring empty.
623 * We could avoid this when the queue size does not exactly
624 * match the hardware ring size, but it's not that important.
625 * Therefore we stop the queue when one more skb might fill
626 * the ring completely. We wake it when half way back to
627 * empty.
628 */
629 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
630 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
631
8ceee660
BH		 632 /* Initialise the channels */
633 efx_for_each_channel(channel, efx) {
3881d8ab 634 efx_for_each_channel_tx_queue(tx_queue, channel) {
bc3c90a2 635 efx_init_tx_queue(tx_queue);
3881d8ab
AR		 636 atomic_inc(&efx->active_queues);
637 }
8ceee660 638
9f2cb71c 639 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 640 efx_init_rx_queue(rx_queue);
3881d8ab 641 atomic_inc(&efx->active_queues);
9f2cb71c
BH		 642 efx_nic_generate_fill_event(rx_queue);
643 }
8ceee660 644
85740cdf 645 WARN_ON(channel->rx_pkt_n_frags);
8ceee660 646 }
8ceee660 647
2ea4dc28
AR		 648 efx_ptp_start_datapath(efx);
649
9f2cb71c
BH		 650 if (netif_device_present(efx->net_dev))
651 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH		 652}
653
9f2cb71c 654static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH		 655{
656 struct efx_channel *channel;
657 struct efx_tx_queue *tx_queue;
658 struct efx_rx_queue *rx_queue;
6bc5d3a9 659 int rc;
8ceee660
BH		 660
661 EFX_ASSERT_RESET_SERIALISED(efx);
662 BUG_ON(efx->port_enabled);
663
2ea4dc28
AR		 664 efx_ptp_stop_datapath(efx);
665
d8aec745
BH		 666 /* Stop RX refill */
667 efx_for_each_channel(channel, efx) {
668 efx_for_each_channel_rx_queue(rx_queue, channel)
669 rx_queue->refill_enabled = false;
670 }
671
8ceee660 672 efx_for_each_channel(channel, efx) {
9f2cb71c
BH		 673 /* RX packet processing is pipelined, so wait for the
674 * NAPI handler to complete. At least event queue 0
675 * might be kept active by non-data events, so don't
676 * use napi_synchronize() but actually disable NAPI
677 * temporarily.
678 */
679 if (efx_channel_has_rx_queue(channel)) {
680 efx_stop_eventq(channel);
681 efx_start_eventq(channel);
682 }
e42c3d85 683 }
8ceee660 684
e42c3d85
BH		 685 rc = efx->type->fini_dmaq(efx);
686 if (rc && EFX_WORKAROUND_7803(efx)) {
687 /* Schedule a reset to recover from the flush failure. The
688 * descriptor caches reference memory we're about to free,
689 * but falcon_reconfigure_mac_wrapper() won't reconnect
690 * the MACs because of the pending reset.
691 */
692 netif_err(efx, drv, efx->net_dev,
693 "Resetting to recover from flush failure\n");
694 efx_schedule_reset(efx, RESET_TYPE_ALL);
695 } else if (rc) {
696 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
697 } else {
698 netif_dbg(efx, drv, efx->net_dev,
699 "successfully flushed all queues\n");
700 }
701
702 efx_for_each_channel(channel, efx) {
8ceee660
BH		 703 efx_for_each_channel_rx_queue(rx_queue, channel)
704 efx_fini_rx_queue(rx_queue);
94b274bf 705 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 706 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 707 }
708}
709
710static void efx_remove_channel(struct efx_channel *channel)
711{
712 struct efx_tx_queue *tx_queue;
713 struct efx_rx_queue *rx_queue;
714
62776d03
BH		 715 netif_dbg(channel->efx, drv, channel->efx->net_dev,
716 "destroy chan %d\n", channel->channel);
8ceee660
BH		 717
718 efx_for_each_channel_rx_queue(rx_queue, channel)
719 efx_remove_rx_queue(rx_queue);
94b274bf 720 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH		 721 efx_remove_tx_queue(tx_queue);
722 efx_remove_eventq(channel);
c31e5f9f 723 channel->type->post_remove(channel);
8ceee660
BH		 724}
725
4642610c
BH		 726static void efx_remove_channels(struct efx_nic *efx)
727{
728 struct efx_channel *channel;
729
730 efx_for_each_channel(channel, efx)
731 efx_remove_channel(channel);
732}
733
734int
735efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
736{
737 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
738 u32 old_rxq_entries, old_txq_entries;
7f967c01 739 unsigned i, next_buffer_table = 0;
261e4d96 740 int rc, rc2;
8b7325b4
BH		 741
742 rc = efx_check_disabled(efx);
743 if (rc)
744 return rc;
7f967c01
BH		 745
746 /* Not all channels should be reallocated. We must avoid
747 * reallocating their buffer table entries.
748 */
749 efx_for_each_channel(channel, efx) {
750 struct efx_rx_queue *rx_queue;
751 struct efx_tx_queue *tx_queue;
752
753 if (channel->type->copy)
754 continue;
755 next_buffer_table = max(next_buffer_table,
756 channel->eventq.index +
757 channel->eventq.entries);
758 efx_for_each_channel_rx_queue(rx_queue, channel)
759 next_buffer_table = max(next_buffer_table,
760 rx_queue->rxd.index +
761 rx_queue->rxd.entries);
762 efx_for_each_channel_tx_queue(tx_queue, channel)
763 next_buffer_table = max(next_buffer_table,
764 tx_queue->txd.index +
765 tx_queue->txd.entries);
766 }
4642610c 767
29c69a48 768 efx_device_detach_sync(efx);
4642610c 769 efx_stop_all(efx);
d8291187 770 efx_soft_disable_interrupts(efx);
4642610c 771
7f967c01 772 /* Clone channels (where possible) */
4642610c
BH		 773 memset(other_channel, 0, sizeof(other_channel));
774 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 775 channel = efx->channel[i];
776 if (channel->type->copy)
777 channel = channel->type->copy(channel);
4642610c
BH		 778 if (!channel) {
779 rc = -ENOMEM;
780 goto out;
781 }
782 other_channel[i] = channel;
783 }
784
785 /* Swap entry counts and channel pointers */
786 old_rxq_entries = efx->rxq_entries;
787 old_txq_entries = efx->txq_entries;
788 efx->rxq_entries = rxq_entries;
789 efx->txq_entries = txq_entries;
790 for (i = 0; i < efx->n_channels; i++) {
791 channel = efx->channel[i];
792 efx->channel[i] = other_channel[i];
793 other_channel[i] = channel;
794 }
795
7f967c01
BH		 796 /* Restart buffer table allocation */
797 efx->next_buffer_table = next_buffer_table;
e8f14992 798
e8f14992 799 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 800 channel = efx->channel[i];
801 if (!channel->type->copy)
802 continue;
803 rc = efx_probe_channel(channel);
804 if (rc)
805 goto rollback;
806 efx_init_napi_channel(efx->channel[i]);
e8f14992 807 }
7f967c01 808
4642610c 809out:
7f967c01
BH		 810 /* Destroy unused channel structures */
811 for (i = 0; i < efx->n_channels; i++) {
812 channel = other_channel[i];
813 if (channel && channel->type->copy) {
814 efx_fini_napi_channel(channel);
815 efx_remove_channel(channel);
816 kfree(channel);
817 }
818 }
4642610c 819
261e4d96
JC		 820 rc2 = efx_soft_enable_interrupts(efx);
821 if (rc2) {
822 rc = rc ? rc : rc2;
823 netif_err(efx, drv, efx->net_dev,
824 "unable to restart interrupts on channel reallocation\n");
825 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
826 } else {
827 efx_start_all(efx);
828 netif_device_attach(efx->net_dev);
829 }
4642610c
BH		 830 return rc;
831
832rollback:
833 /* Swap back */
834 efx->rxq_entries = old_rxq_entries;
835 efx->txq_entries = old_txq_entries;
836 for (i = 0; i < efx->n_channels; i++) {
837 channel = efx->channel[i];
838 efx->channel[i] = other_channel[i];
839 other_channel[i] = channel;
840 }
841 goto out;
842}
843
90d683af 844void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 845{
90d683af 846 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH		 847}
848
7f967c01
BH		 849static const struct efx_channel_type efx_default_channel_type = {
850 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 851 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH		 852 .get_name = efx_get_channel_name,
853 .copy = efx_copy_channel,
854 .keep_eventq = false,
855};
856
857int efx_channel_dummy_op_int(struct efx_channel *channel)
858{
859 return 0;
860}
861
c31e5f9f
SH		 862void efx_channel_dummy_op_void(struct efx_channel *channel)
863{
864}
865
8ceee660
BH		 866/**************************************************************************
867 *
868 * Port handling
869 *
870 **************************************************************************/
871
872/* This ensures that the kernel is kept informed (via
873 * netif_carrier_on/off) of the link status, and also maintains the
874 * link status's stop on the port's TX queue.
875 */
fdaa9aed 876void efx_link_status_changed(struct efx_nic *efx)
8ceee660 877{
eb50c0d6
BH		 878 struct efx_link_state *link_state = &efx->link_state;
879
8ceee660
BH		 880 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
881 * that no events are triggered between unregister_netdev() and the
882 * driver unloading. A more general condition is that NETDEV_CHANGE
883 * can only be generated between NETDEV_UP and NETDEV_DOWN */
884 if (!netif_running(efx->net_dev))
885 return;
886
eb50c0d6 887 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 888 efx->n_link_state_changes++;
889
eb50c0d6 890 if (link_state->up)
8ceee660
BH		 891 netif_carrier_on(efx->net_dev);
892 else
893 netif_carrier_off(efx->net_dev);
894 }
895
896 /* Status message for kernel log */
2aa9ef11 897 if (link_state->up)
62776d03 898 netif_info(efx, link, efx->net_dev,
964e6135 899 "link up at %uMbps %s-duplex (MTU %d)\n",
62776d03 900 link_state->speed, link_state->fd ? "full" : "half",
964e6135 901 efx->net_dev->mtu);
2aa9ef11 902 else
62776d03 903 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH		 904}
905
d3245b28
BH		 906void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
907{
908 efx->link_advertising = advertising;
909 if (advertising) {
910 if (advertising & ADVERTISED_Pause)
911 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
912 else
913 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
914 if (advertising & ADVERTISED_Asym_Pause)
915 efx->wanted_fc ^= EFX_FC_TX;
916 }
917}
918
b5626946 919void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH		 920{
921 efx->wanted_fc = wanted_fc;
922 if (efx->link_advertising) {
923 if (wanted_fc & EFX_FC_RX)
924 efx->link_advertising |= (ADVERTISED_Pause |
925 ADVERTISED_Asym_Pause);
926 else
927 efx->link_advertising &= ~(ADVERTISED_Pause |
928 ADVERTISED_Asym_Pause);
929 if (wanted_fc & EFX_FC_TX)
930 efx->link_advertising ^= ADVERTISED_Asym_Pause;
931 }
932}
933
115122af
BH		 934static void efx_fini_port(struct efx_nic *efx);
935
d3245b28
BH		 936/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
937 * the MAC appropriately. All other PHY configuration changes are pushed
938 * through phy_op->set_settings(), and pushed asynchronously to the MAC
939 * through efx_monitor().
940 *
941 * Callers must hold the mac_lock
942 */
943int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 944{
d3245b28
BH		 945 enum efx_phy_mode phy_mode;
946 int rc;
8ceee660 947
d3245b28 948 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 949
d3245b28
BH		 950 /* Disable PHY transmit in mac level loopbacks */
951 phy_mode = efx->phy_mode;
177dfcd8
BH		 952 if (LOOPBACK_INTERNAL(efx))
953 efx->phy_mode |= PHY_MODE_TX_DISABLED;
954 else
955 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 956
d3245b28 957 rc = efx->type->reconfigure_port(efx);
8ceee660 958
d3245b28
BH		 959 if (rc)
960 efx->phy_mode = phy_mode;
177dfcd8 961
d3245b28 962 return rc;
8ceee660
BH		 963}
964
965/* Reinitialise the MAC to pick up new PHY settings, even if the port is
966 * disabled. */
d3245b28 967int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 968{
d3245b28
BH		 969 int rc;
970
8ceee660
BH		 971 EFX_ASSERT_RESET_SERIALISED(efx);
972
973 mutex_lock(&efx->mac_lock);
d3245b28 974 rc = __efx_reconfigure_port(efx);
8ceee660 975 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 976
977 return rc;
8ceee660
BH		 978}
979
8be4f3e6
BH		 980/* Asynchronous work item for changing MAC promiscuity and multicast
981 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
982 * MAC directly. */
766ca0fa
BH		 983static void efx_mac_work(struct work_struct *data)
984{
985 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
986
987 mutex_lock(&efx->mac_lock);
30b81cda 988 if (efx->port_enabled)
710b208d 989 efx->type->reconfigure_mac(efx);
766ca0fa
BH		 990 mutex_unlock(&efx->mac_lock);
991}
992
8ceee660
BH		 993static int efx_probe_port(struct efx_nic *efx)
994{
995 int rc;
996
62776d03 997 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 998
ff3b00a0
SH		 999 if (phy_flash_cfg)
1000 efx->phy_mode = PHY_MODE_SPECIAL;
1001
ef2b90ee
BH		 1002 /* Connect up MAC/PHY operations table */
1003 rc = efx->type->probe_port(efx);
8ceee660 1004 if (rc)
e42de262 1005 return rc;
8ceee660 1006
e332bcb3
BH		 1007 /* Initialise MAC address to permanent address */
1008 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN);
8ceee660
BH		 1009
1010 return 0;
8ceee660
BH		 1011}
1012
1013static int efx_init_port(struct efx_nic *efx)
1014{
1015 int rc;
1016
62776d03 1017 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 1018
1dfc5cea
BH		 1019 mutex_lock(&efx->mac_lock);
1020
177dfcd8 1021 rc = efx->phy_op->init(efx);
8ceee660 1022 if (rc)
1dfc5cea 1023 goto fail1;
8ceee660 1024
dc8cfa55 1025 efx->port_initialized = true;
1dfc5cea 1026
d3245b28
BH		 1027 /* Reconfigure the MAC before creating dma queues (required for
1028 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
710b208d 1029 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1030
1031 /* Ensure the PHY advertises the correct flow control settings */
1032 rc = efx->phy_op->reconfigure(efx);
1033 if (rc)
1034 goto fail2;
1035
1dfc5cea 1036 mutex_unlock(&efx->mac_lock);
8ceee660 1037 return 0;
177dfcd8 1038
1dfc5cea 1039fail2:
177dfcd8 1040 efx->phy_op->fini(efx);
1dfc5cea
BH		 1041fail1:
1042 mutex_unlock(&efx->mac_lock);
177dfcd8 1043 return rc;
8ceee660
BH		 1044}
1045
8ceee660
BH		 1046static void efx_start_port(struct efx_nic *efx)
1047{
62776d03 1048 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH		 1049 BUG_ON(efx->port_enabled);
1050
1051 mutex_lock(&efx->mac_lock);
dc8cfa55 1052 efx->port_enabled = true;
8be4f3e6
BH		 1053
1054 /* efx_mac_work() might have been scheduled after efx_stop_port(),
1055 * and then cancelled by efx_flush_all() */
710b208d 1056 efx->type->reconfigure_mac(efx);
8be4f3e6 1057
8ceee660
BH		 1058 mutex_unlock(&efx->mac_lock);
1059}
1060
fdaa9aed 1061/* Prevent efx_mac_work() and efx_monitor() from working */
8ceee660
BH		 1062static void efx_stop_port(struct efx_nic *efx)
1063{
62776d03 1064 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660
BH		 1065
1066 mutex_lock(&efx->mac_lock);
dc8cfa55 1067 efx->port_enabled = false;
8ceee660
BH		 1068 mutex_unlock(&efx->mac_lock);
1069
1070 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH		 1071 netif_addr_lock_bh(efx->net_dev);
1072 netif_addr_unlock_bh(efx->net_dev);
8ceee660
BH		 1073}
1074
1075static void efx_fini_port(struct efx_nic *efx)
1076{
62776d03 1077 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH		 1078
1079 if (!efx->port_initialized)
1080 return;
1081
177dfcd8 1082 efx->phy_op->fini(efx);
dc8cfa55 1083 efx->port_initialized = false;
8ceee660 1084
eb50c0d6 1085 efx->link_state.up = false;
8ceee660
BH		 1086 efx_link_status_changed(efx);
1087}
1088
1089static void efx_remove_port(struct efx_nic *efx)
1090{
62776d03 1091 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1092
ef2b90ee 1093 efx->type->remove_port(efx);
8ceee660
BH		 1094}
1095
1096/**************************************************************************
1097 *
1098 * NIC handling
1099 *
1100 **************************************************************************/
1101
1102/* This configures the PCI device to enable I/O and DMA. */
1103static int efx_init_io(struct efx_nic *efx)
1104{
1105 struct pci_dev *pci_dev = efx->pci_dev;
1106 dma_addr_t dma_mask = efx->type->max_dma_mask;
b105798f 1107 unsigned int mem_map_size = efx->type->mem_map_size(efx);
8ceee660
BH		 1108 int rc;
1109
62776d03 1110 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660
BH		 1111
1112 rc = pci_enable_device(pci_dev);
1113 if (rc) {
62776d03
BH		 1114 netif_err(efx, probe, efx->net_dev,
1115 "failed to enable PCI device\n");
8ceee660
BH		 1116 goto fail1;
1117 }
1118
1119 pci_set_master(pci_dev);
1120
1121 /* Set the PCI DMA mask. Try all possibilities from our
1122 * genuine mask down to 32 bits, because some architectures
1123 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1124 * masks event though they reject 46 bit masks.
1125 */
1126 while (dma_mask > 0x7fffffffUL) {
0e33d870 1127 if (dma_supported(&pci_dev->dev, dma_mask)) {
9663deda 1128 rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask);
e9e01846
BH		 1129 if (rc == 0)
1130 break;
1131 }
8ceee660
BH		 1132 dma_mask >>= 1;
1133 }
1134 if (rc) {
62776d03
BH		 1135 netif_err(efx, probe, efx->net_dev,
1136 "could not find a suitable DMA mask\n");
8ceee660
BH		 1137 goto fail2;
1138 }
62776d03
BH		 1139 netif_dbg(efx, probe, efx->net_dev,
1140 "using DMA mask %llx\n", (unsigned long long) dma_mask);
8ceee660 1141
dc803df8
BH		 1142 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1143 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
8ceee660 1144 if (rc) {
62776d03
BH		 1145 netif_err(efx, probe, efx->net_dev,
1146 "request for memory BAR failed\n");
8ceee660
BH		 1147 rc = -EIO;
1148 goto fail3;
1149 }
b105798f 1150 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
8ceee660 1151 if (!efx->membase) {
62776d03
BH		 1152 netif_err(efx, probe, efx->net_dev,
1153 "could not map memory BAR at %llx+%x\n",
b105798f 1154 (unsigned long long)efx->membase_phys, mem_map_size);
8ceee660
BH		 1155 rc = -ENOMEM;
1156 goto fail4;
1157 }
62776d03
BH		 1158 netif_dbg(efx, probe, efx->net_dev,
1159 "memory BAR at %llx+%x (virtual %p)\n",
b105798f
BH		 1160 (unsigned long long)efx->membase_phys, mem_map_size,
1161 efx->membase);
8ceee660
BH		 1162
1163 return 0;
1164
1165 fail4:
dc803df8 1166 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
8ceee660 1167 fail3:
2c118e0f 1168 efx->membase_phys = 0;
8ceee660
BH		 1169 fail2:
1170 pci_disable_device(efx->pci_dev);
1171 fail1:
1172 return rc;
1173}
1174
1175static void efx_fini_io(struct efx_nic *efx)
1176{
62776d03 1177 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH		 1178
1179 if (efx->membase) {
1180 iounmap(efx->membase);
1181 efx->membase = NULL;
1182 }
1183
1184 if (efx->membase_phys) {
dc803df8 1185 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
2c118e0f 1186 efx->membase_phys = 0;
8ceee660
BH		 1187 }
1188
1189 pci_disable_device(efx->pci_dev);
1190}
1191
a9a52506 1192static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1193{
cdb08f8f 1194 cpumask_var_t thread_mask;
a16e5b24 1195 unsigned int count;
46123d04 1196 int cpu;
5b874e25 1197
cd2d5b52
BH		 1198 if (rss_cpus) {
1199 count = rss_cpus;
1200 } else {
1201 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1202 netif_warn(efx, probe, efx->net_dev,
1203 "RSS disabled due to allocation failure\n");
1204 return 1;
1205 }
46123d04 1206
cd2d5b52
BH		 1207 count = 0;
1208 for_each_online_cpu(cpu) {
1209 if (!cpumask_test_cpu(cpu, thread_mask)) {
1210 ++count;
1211 cpumask_or(thread_mask, thread_mask,
1212 topology_thread_cpumask(cpu));
1213 }
1214 }
1215
1216 free_cpumask_var(thread_mask);
2f8975fb
RR		 1217 }
1218
cd2d5b52
BH		 1219 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1220 * table entries that are inaccessible to VFs
1221 */
1222 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1223 count > efx_vf_size(efx)) {
1224 netif_warn(efx, probe, efx->net_dev,
1225 "Reducing number of RSS channels from %u to %u for "
1226 "VF support. Increase vf-msix-limit to use more "
1227 "channels on the PF.\n",
1228 count, efx_vf_size(efx));
1229 count = efx_vf_size(efx);
46123d04
BH		 1230 }
1231
1232 return count;
1233}
1234
1235/* Probe the number and type of interrupts we are able to obtain, and
1236 * the resulting numbers of channels and RX queues.
1237 */
64d8ad6d 1238static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1239{
7f967c01
BH		 1240 unsigned int extra_channels = 0;
1241 unsigned int i, j;
a16e5b24 1242 int rc;
8ceee660 1243
7f967c01
BH		 1244 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1245 if (efx->extra_channel_type[i])
1246 ++extra_channels;
1247
8ceee660 1248 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1249 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1250 unsigned int n_channels;
aa6ef27e 1251
a9a52506 1252 n_channels = efx_wanted_parallelism(efx);
a4900ac9
BH		 1253 if (separate_tx_channels)
1254 n_channels *= 2;
7f967c01 1255 n_channels += extra_channels;
b105798f 1256 n_channels = min(n_channels, efx->max_channels);
8ceee660 1257
a4900ac9 1258 for (i = 0; i < n_channels; i++)
8ceee660 1259 xentries[i].entry = i;
a4900ac9 1260 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
8ceee660 1261 if (rc > 0) {
62776d03
BH		 1262 netif_err(efx, drv, efx->net_dev,
1263 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1264 " available (%d < %u).\n", rc, n_channels);
62776d03
BH		 1265 netif_err(efx, drv, efx->net_dev,
1266 "WARNING: Performance may be reduced.\n");
a4900ac9
BH		 1267 EFX_BUG_ON_PARANOID(rc >= n_channels);
1268 n_channels = rc;
8ceee660 1269 rc = pci_enable_msix(efx->pci_dev, xentries,
a4900ac9 1270 n_channels);
8ceee660
BH		 1271 }
1272
1273 if (rc == 0) {
a4900ac9 1274 efx->n_channels = n_channels;
7f967c01
BH		 1275 if (n_channels > extra_channels)
1276 n_channels -= extra_channels;
a4900ac9 1277 if (separate_tx_channels) {
7f967c01
BH		 1278 efx->n_tx_channels = max(n_channels / 2, 1U);
1279 efx->n_rx_channels = max(n_channels -
1280 efx->n_tx_channels,
1281 1U);
a4900ac9 1282 } else {
7f967c01
BH		 1283 efx->n_tx_channels = n_channels;
1284 efx->n_rx_channels = n_channels;
a4900ac9 1285 }
7f967c01 1286 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH		 1287 efx_get_channel(efx, i)->irq =
1288 xentries[i].vector;
8ceee660
BH		 1289 } else {
1290 /* Fall back to single channel MSI */
1291 efx->interrupt_mode = EFX_INT_MODE_MSI;
62776d03
BH		 1292 netif_err(efx, drv, efx->net_dev,
1293 "could not enable MSI-X\n");
8ceee660
BH		 1294 }
1295 }
1296
1297 /* Try single interrupt MSI */
1298 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1299 efx->n_channels = 1;
a4900ac9
BH		 1300 efx->n_rx_channels = 1;
1301 efx->n_tx_channels = 1;
8ceee660
BH		 1302 rc = pci_enable_msi(efx->pci_dev);
1303 if (rc == 0) {
f7d12cdc 1304 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1305 } else {
62776d03
BH		 1306 netif_err(efx, drv, efx->net_dev,
1307 "could not enable MSI\n");
8ceee660
BH		 1308 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1309 }
1310 }
1311
1312 /* Assume legacy interrupts */
1313 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
28b581ab 1314 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
a4900ac9
BH		 1315 efx->n_rx_channels = 1;
1316 efx->n_tx_channels = 1;
8ceee660
BH		 1317 efx->legacy_irq = efx->pci_dev->irq;
1318 }
64d8ad6d 1319
7f967c01
BH		 1320 /* Assign extra channels if possible */
1321 j = efx->n_channels;
1322 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1323 if (!efx->extra_channel_type[i])
1324 continue;
1325 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1326 efx->n_channels <= extra_channels) {
1327 efx->extra_channel_type[i]->handle_no_channel(efx);
1328 } else {
1329 --j;
1330 efx_get_channel(efx, j)->type =
1331 efx->extra_channel_type[i];
1332 }
1333 }
1334
cd2d5b52 1335 /* RSS might be usable on VFs even if it is disabled on the PF */
3132d282 1336 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ?
cd2d5b52
BH		 1337 efx->n_rx_channels : efx_vf_size(efx));
1338
64d8ad6d 1339 return 0;
8ceee660
BH		 1340}
1341
261e4d96 1342static int efx_soft_enable_interrupts(struct efx_nic *efx)
9f2cb71c 1343{
261e4d96
JC		 1344 struct efx_channel *channel, *end_channel;
1345 int rc;
9f2cb71c 1346
8b7325b4
BH		 1347 BUG_ON(efx->state == STATE_DISABLED);
1348
d8291187
BH		 1349 efx->irq_soft_enabled = true;
1350 smp_wmb();
9f2cb71c
BH		 1351
1352 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1353 if (!channel->type->keep_eventq) {
1354 rc = efx_init_eventq(channel);
1355 if (rc)
1356 goto fail;
1357 }
9f2cb71c
BH		 1358 efx_start_eventq(channel);
1359 }
1360
1361 efx_mcdi_mode_event(efx);
261e4d96
JC		 1362
1363 return 0;
1364fail:
1365 end_channel = channel;
1366 efx_for_each_channel(channel, efx) {
1367 if (channel == end_channel)
1368 break;
1369 efx_stop_eventq(channel);
1370 if (!channel->type->keep_eventq)
1371 efx_fini_eventq(channel);
1372 }
1373
1374 return rc;
9f2cb71c
BH		 1375}
1376
d8291187 1377static void efx_soft_disable_interrupts(struct efx_nic *efx)
9f2cb71c
BH		 1378{
1379 struct efx_channel *channel;
1380
8b7325b4
BH		 1381 if (efx->state == STATE_DISABLED)
1382 return;
1383
9f2cb71c
BH		 1384 efx_mcdi_mode_poll(efx);
1385
d8291187
BH		 1386 efx->irq_soft_enabled = false;
1387 smp_wmb();
1388
1389 if (efx->legacy_irq)
9f2cb71c 1390 synchronize_irq(efx->legacy_irq);
9f2cb71c
BH		 1391
1392 efx_for_each_channel(channel, efx) {
1393 if (channel->irq)
1394 synchronize_irq(channel->irq);
1395
1396 efx_stop_eventq(channel);
d8291187 1397 if (!channel->type->keep_eventq)
7f967c01 1398 efx_fini_eventq(channel);
9f2cb71c 1399 }
cade715f
BH		 1400
1401 /* Flush the asynchronous MCDI request queue */
1402 efx_mcdi_flush_async(efx);
9f2cb71c
BH		 1403}
1404
261e4d96 1405static int efx_enable_interrupts(struct efx_nic *efx)
d8291187 1406{
261e4d96
JC		 1407 struct efx_channel *channel, *end_channel;
1408 int rc;
d8291187
BH		 1409
1410 BUG_ON(efx->state == STATE_DISABLED);
1411
1412 if (efx->eeh_disabled_legacy_irq) {
1413 enable_irq(efx->legacy_irq);
1414 efx->eeh_disabled_legacy_irq = false;
1415 }
1416
86094f7f 1417 efx->type->irq_enable_master(efx);
d8291187
BH		 1418
1419 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1420 if (channel->type->keep_eventq) {
1421 rc = efx_init_eventq(channel);
1422 if (rc)
1423 goto fail;
1424 }
1425 }
1426
1427 rc = efx_soft_enable_interrupts(efx);
1428 if (rc)
1429 goto fail;
1430
1431 return 0;
1432
1433fail:
1434 end_channel = channel;
1435 efx_for_each_channel(channel, efx) {
1436 if (channel == end_channel)
1437 break;
d8291187 1438 if (channel->type->keep_eventq)
261e4d96 1439 efx_fini_eventq(channel);
d8291187
BH		 1440 }
1441
261e4d96
JC		 1442 efx->type->irq_disable_non_ev(efx);
1443
1444 return rc;
d8291187
BH		 1445}
1446
1447static void efx_disable_interrupts(struct efx_nic *efx)
1448{
1449 struct efx_channel *channel;
1450
1451 efx_soft_disable_interrupts(efx);
1452
1453 efx_for_each_channel(channel, efx) {
1454 if (channel->type->keep_eventq)
1455 efx_fini_eventq(channel);
1456 }
1457
86094f7f 1458 efx->type->irq_disable_non_ev(efx);
d8291187
BH		 1459}
1460
8ceee660
BH		 1461static void efx_remove_interrupts(struct efx_nic *efx)
1462{
1463 struct efx_channel *channel;
1464
1465 /* Remove MSI/MSI-X interrupts */
64ee3120 1466 efx_for_each_channel(channel, efx)
8ceee660
BH		 1467 channel->irq = 0;
1468 pci_disable_msi(efx->pci_dev);
1469 pci_disable_msix(efx->pci_dev);
1470
1471 /* Remove legacy interrupt */
1472 efx->legacy_irq = 0;
1473}
1474
8831da7b 1475static void efx_set_channels(struct efx_nic *efx)
8ceee660 1476{
602a5322
BH		 1477 struct efx_channel *channel;
1478 struct efx_tx_queue *tx_queue;
1479
97653431 1480 efx->tx_channel_offset =
a4900ac9 1481 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
602a5322 1482
79d68b37
SH		 1483 /* We need to mark which channels really have RX and TX
1484 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH		 1485 * RX-only and TX-only channels.
1486 */
1487 efx_for_each_channel(channel, efx) {
79d68b37
SH		 1488 if (channel->channel < efx->n_rx_channels)
1489 channel->rx_queue.core_index = channel->channel;
1490 else
1491 channel->rx_queue.core_index = -1;
1492
602a5322
BH		 1493 efx_for_each_channel_tx_queue(tx_queue, channel)
1494 tx_queue->queue -= (efx->tx_channel_offset *
1495 EFX_TXQ_TYPES);
1496 }
8ceee660
BH		 1497}
1498
1499static int efx_probe_nic(struct efx_nic *efx)
1500{
765c9f46 1501 size_t i;
8ceee660
BH		 1502 int rc;
1503
62776d03 1504 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH		 1505
1506 /* Carry out hardware-type specific initialisation */
ef2b90ee 1507 rc = efx->type->probe(efx);
8ceee660
BH		 1508 if (rc)
1509 return rc;
1510
a4900ac9 1511 /* Determine the number of channels and queues by trying to hook
8ceee660 1512 * in MSI-X interrupts. */
64d8ad6d
BH		 1513 rc = efx_probe_interrupts(efx);
1514 if (rc)
c15eed22 1515 goto fail1;
8ceee660 1516
c15eed22
BH		 1517 rc = efx->type->dimension_resources(efx);
1518 if (rc)
1519 goto fail2;
28e47c49 1520
5d3a6fca
BH		 1521 if (efx->n_channels > 1)
1522 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
765c9f46 1523 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
278bc429 1524 efx->rx_indir_table[i] =
cd2d5b52 1525 ethtool_rxfh_indir_default(i, efx->rss_spread);
5d3a6fca 1526
8831da7b 1527 efx_set_channels(efx);
c4f4adc7
BH		 1528 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1529 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH		 1530
1531 /* Initialise the interrupt moderation settings */
9e393b30
BH		 1532 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1533 true);
8ceee660
BH		 1534
1535 return 0;
64d8ad6d 1536
c15eed22
BH		 1537fail2:
1538 efx_remove_interrupts(efx);
1539fail1:
64d8ad6d
BH		 1540 efx->type->remove(efx);
1541 return rc;
8ceee660
BH		 1542}
1543
1544static void efx_remove_nic(struct efx_nic *efx)
1545{
62776d03 1546 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH		 1547
1548 efx_remove_interrupts(efx);
ef2b90ee 1549 efx->type->remove(efx);
8ceee660
BH		 1550}
1551
add72477
BH		 1552static int efx_probe_filters(struct efx_nic *efx)
1553{
1554 int rc;
1555
1556 spin_lock_init(&efx->filter_lock);
1557
1558 rc = efx->type->filter_table_probe(efx);
1559 if (rc)
1560 return rc;
1561
1562#ifdef CONFIG_RFS_ACCEL
1563 if (efx->type->offload_features & NETIF_F_NTUPLE) {
1564 efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters,
1565 sizeof(*efx->rps_flow_id),
1566 GFP_KERNEL);
1567 if (!efx->rps_flow_id) {
1568 efx->type->filter_table_remove(efx);
1569 return -ENOMEM;
1570 }
1571 }
1572#endif
1573
1574 return 0;
1575}
1576
1577static void efx_remove_filters(struct efx_nic *efx)
1578{
1579#ifdef CONFIG_RFS_ACCEL
1580 kfree(efx->rps_flow_id);
1581#endif
1582 efx->type->filter_table_remove(efx);
1583}
1584
1585static void efx_restore_filters(struct efx_nic *efx)
1586{
1587 efx->type->filter_table_restore(efx);
1588}
1589
8ceee660
BH		 1590/**************************************************************************
1591 *
1592 * NIC startup/shutdown
1593 *
1594 *************************************************************************/
1595
1596static int efx_probe_all(struct efx_nic *efx)
1597{
8ceee660
BH		 1598 int rc;
1599
8ceee660
BH		 1600 rc = efx_probe_nic(efx);
1601 if (rc) {
62776d03 1602 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH		 1603 goto fail1;
1604 }
1605
8ceee660
BH		 1606 rc = efx_probe_port(efx);
1607 if (rc) {
62776d03 1608 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH		 1609 goto fail2;
1610 }
1611
7e6d06f0
BH		 1612 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1613 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1614 rc = -EINVAL;
1615 goto fail3;
1616 }
ecc910f5 1617 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1618
64eebcfd
BH		 1619 rc = efx_probe_filters(efx);
1620 if (rc) {
1621 netif_err(efx, probe, efx->net_dev,
1622 "failed to create filter tables\n");
7f967c01 1623 goto fail3;
64eebcfd
BH		 1624 }
1625
7f967c01
BH		 1626 rc = efx_probe_channels(efx);
1627 if (rc)
1628 goto fail4;
1629
8ceee660
BH		 1630 return 0;
1631
64eebcfd 1632 fail4:
7f967c01 1633 efx_remove_filters(efx);
8ceee660 1634 fail3:
8ceee660
BH		 1635 efx_remove_port(efx);
1636 fail2:
1637 efx_remove_nic(efx);
1638 fail1:
1639 return rc;
1640}
1641
8b7325b4
BH		 1642/* If the interface is supposed to be running but is not, start
1643 * the hardware and software data path, regular activity for the port
1644 * (MAC statistics, link polling, etc.) and schedule the port to be
1645 * reconfigured. Interrupts must already be enabled. This function
1646 * is safe to call multiple times, so long as the NIC is not disabled.
1647 * Requires the RTNL lock.
9f2cb71c 1648 */
8ceee660
BH		 1649static void efx_start_all(struct efx_nic *efx)
1650{
8ceee660 1651 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1652 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH		 1653
1654 /* Check that it is appropriate to restart the interface. All
1655 * of these flags are safe to read under just the rtnl lock */
8b7325b4 1656 if (efx->port_enabled || !netif_running(efx->net_dev))
8ceee660
BH		 1657 return;
1658
8ceee660 1659 efx_start_port(efx);
9f2cb71c 1660 efx_start_datapath(efx);
8880f4ec 1661
626950db
AR		 1662 /* Start the hardware monitor if there is one */
1663 if (efx->type->monitor != NULL)
8ceee660
BH		 1664 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1665 efx_monitor_interval);
626950db
AR		 1666
1667 /* If link state detection is normally event-driven, we have
1668 * to poll now because we could have missed a change
1669 */
1670 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
78c1f0a0
SH		 1671 mutex_lock(&efx->mac_lock);
1672 if (efx->phy_op->poll(efx))
1673 efx_link_status_changed(efx);
1674 mutex_unlock(&efx->mac_lock);
1675 }
55edc6e6 1676
ef2b90ee 1677 efx->type->start_stats(efx);
8ceee660
BH		 1678}
1679
1680/* Flush all delayed work. Should only be called when no more delayed work
1681 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1682 * since we're holding the rtnl_lock at this point. */
1683static void efx_flush_all(struct efx_nic *efx)
1684{
dd40781e 1685 /* Make sure the hardware monitor and event self-test are stopped */
8ceee660 1686 cancel_delayed_work_sync(&efx->monitor_work);
dd40781e 1687 efx_selftest_async_cancel(efx);
8ceee660 1688 /* Stop scheduled port reconfigurations */
766ca0fa 1689 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1690}
1691
8b7325b4
BH		 1692/* Quiesce the hardware and software data path, and regular activity
1693 * for the port without bringing the link down. Safe to call multiple
1694 * times with the NIC in almost any state, but interrupts should be
1695 * enabled. Requires the RTNL lock.
1696 */
8ceee660
BH		 1697static void efx_stop_all(struct efx_nic *efx)
1698{
8ceee660
BH		 1699 EFX_ASSERT_RESET_SERIALISED(efx);
1700
1701 /* port_enabled can be read safely under the rtnl lock */
1702 if (!efx->port_enabled)
1703 return;
1704
ef2b90ee 1705 efx->type->stop_stats(efx);
8ceee660
BH		 1706 efx_stop_port(efx);
1707
fdaa9aed 1708 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
8ceee660
BH		 1709 efx_flush_all(efx);
1710
29c69a48
BH		 1711 /* Stop the kernel transmit interface. This is only valid if
1712 * the device is stopped or detached; otherwise the watchdog
1713 * may fire immediately.
1714 */
1715 WARN_ON(netif_running(efx->net_dev) &&
1716 netif_device_present(efx->net_dev));
9f2cb71c
BH		 1717 netif_tx_disable(efx->net_dev);
1718
1719 efx_stop_datapath(efx);
8ceee660
BH		 1720}
1721
1722static void efx_remove_all(struct efx_nic *efx)
1723{
4642610c 1724 efx_remove_channels(efx);
7f967c01 1725 efx_remove_filters(efx);
8ceee660
BH		 1726 efx_remove_port(efx);
1727 efx_remove_nic(efx);
1728}
1729
8ceee660
BH		 1730/**************************************************************************
1731 *
1732 * Interrupt moderation
1733 *
1734 **************************************************************************/
1735
cc180b69 1736static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
0d86ebd8 1737{
b548f976
BH		 1738 if (usecs == 0)
1739 return 0;
cc180b69 1740 if (usecs * 1000 < quantum_ns)
0d86ebd8 1741 return 1; /* never round down to 0 */
cc180b69 1742 return usecs * 1000 / quantum_ns;
0d86ebd8
BH		 1743}
1744
8ceee660 1745/* Set interrupt moderation parameters */
9e393b30
BH		 1746int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1747 unsigned int rx_usecs, bool rx_adaptive,
1748 bool rx_may_override_tx)
8ceee660 1749{
f7d12cdc 1750 struct efx_channel *channel;
cc180b69
BH		 1751 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1752 efx->timer_quantum_ns,
1753 1000);
1754 unsigned int tx_ticks;
1755 unsigned int rx_ticks;
8ceee660
BH		 1756
1757 EFX_ASSERT_RESET_SERIALISED(efx);
1758
cc180b69 1759 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
9e393b30
BH		 1760 return -EINVAL;
1761
cc180b69
BH		 1762 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1763 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1764
9e393b30
BH		 1765 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1766 !rx_may_override_tx) {
1767 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1768 "RX and TX IRQ moderation must be equal\n");
1769 return -EINVAL;
1770 }
1771
6fb70fd1 1772 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1773 efx->irq_rx_moderation = rx_ticks;
f7d12cdc 1774 efx_for_each_channel(channel, efx) {
525da907 1775 if (efx_channel_has_rx_queue(channel))
f7d12cdc 1776 channel->irq_moderation = rx_ticks;
525da907 1777 else if (efx_channel_has_tx_queues(channel))
f7d12cdc
BH		 1778 channel->irq_moderation = tx_ticks;
1779 }
9e393b30
BH		 1780
1781 return 0;
8ceee660
BH		 1782}
1783
a0c4faf5
BH		 1784void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
1785 unsigned int *rx_usecs, bool *rx_adaptive)
1786{
cc180b69
BH		 1787 /* We must round up when converting ticks to microseconds
1788 * because we round down when converting the other way.
1789 */
1790
a0c4faf5 1791 *rx_adaptive = efx->irq_rx_adaptive;
cc180b69
BH		 1792 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
1793 efx->timer_quantum_ns,
1794 1000);
a0c4faf5
BH		 1795
1796 /* If channels are shared between RX and TX, so is IRQ
1797 * moderation. Otherwise, IRQ moderation is the same for all
1798 * TX channels and is not adaptive.
1799 */
1800 if (efx->tx_channel_offset == 0)
1801 *tx_usecs = *rx_usecs;
1802 else
cc180b69 1803 *tx_usecs = DIV_ROUND_UP(
a0c4faf5 1804 efx->channel[efx->tx_channel_offset]->irq_moderation *
cc180b69
BH		 1805 efx->timer_quantum_ns,
1806 1000);
a0c4faf5
BH		 1807}
1808
8ceee660
BH		 1809/**************************************************************************
1810 *
1811 * Hardware monitor
1812 *
1813 **************************************************************************/
1814
e254c274 1815/* Run periodically off the general workqueue */
8ceee660
BH		 1816static void efx_monitor(struct work_struct *data)
1817{
1818 struct efx_nic *efx = container_of(data, struct efx_nic,
1819 monitor_work.work);
8ceee660 1820
62776d03
BH		 1821 netif_vdbg(efx, timer, efx->net_dev,
1822 "hardware monitor executing on CPU %d\n",
1823 raw_smp_processor_id());
ef2b90ee 1824 BUG_ON(efx->type->monitor == NULL);
8ceee660 1825
8ceee660
BH		 1826 /* If the mac_lock is already held then it is likely a port
1827 * reconfiguration is already in place, which will likely do
e254c274
BH		 1828 * most of the work of monitor() anyway. */
1829 if (mutex_trylock(&efx->mac_lock)) {
1830 if (efx->port_enabled)
1831 efx->type->monitor(efx);
1832 mutex_unlock(&efx->mac_lock);
1833 }
8ceee660 1834
8ceee660
BH		 1835 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1836 efx_monitor_interval);
1837}
1838
1839/**************************************************************************
1840 *
1841 * ioctls
1842 *
1843 *************************************************************************/
1844
1845/* Net device ioctl
1846 * Context: process, rtnl_lock() held.
1847 */
1848static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1849{
767e468c 1850 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 1851 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 1852
7c236c43
SH		 1853 if (cmd == SIOCSHWTSTAMP)
1854 return efx_ptp_ioctl(efx, ifr, cmd);
1855
68e7f45e
BH		 1856 /* Convert phy_id from older PRTAD/DEVAD format */
1857 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1858 (data->phy_id & 0xfc00) == 0x0400)
1859 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1860
1861 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 1862}
1863
1864/**************************************************************************
1865 *
1866 * NAPI interface
1867 *
1868 **************************************************************************/
1869
7f967c01
BH		 1870static void efx_init_napi_channel(struct efx_channel *channel)
1871{
1872 struct efx_nic *efx = channel->efx;
1873
1874 channel->napi_dev = efx->net_dev;
1875 netif_napi_add(channel->napi_dev, &channel->napi_str,
1876 efx_poll, napi_weight);
1877}
1878
e8f14992 1879static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH		 1880{
1881 struct efx_channel *channel;
8ceee660 1882
7f967c01
BH		 1883 efx_for_each_channel(channel, efx)
1884 efx_init_napi_channel(channel);
e8f14992
BH		 1885}
1886
1887static void efx_fini_napi_channel(struct efx_channel *channel)
1888{
1889 if (channel->napi_dev)
1890 netif_napi_del(&channel->napi_str);
1891 channel->napi_dev = NULL;
8ceee660
BH		 1892}
1893
1894static void efx_fini_napi(struct efx_nic *efx)
1895{
1896 struct efx_channel *channel;
1897
e8f14992
BH		 1898 efx_for_each_channel(channel, efx)
1899 efx_fini_napi_channel(channel);
8ceee660
BH		 1900}
1901
1902/**************************************************************************
1903 *
1904 * Kernel netpoll interface
1905 *
1906 *************************************************************************/
1907
1908#ifdef CONFIG_NET_POLL_CONTROLLER
1909
1910/* Although in the common case interrupts will be disabled, this is not
1911 * guaranteed. However, all our work happens inside the NAPI callback,
1912 * so no locking is required.
1913 */
1914static void efx_netpoll(struct net_device *net_dev)
1915{
767e468c 1916 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1917 struct efx_channel *channel;
1918
64ee3120 1919 efx_for_each_channel(channel, efx)
8ceee660
BH		 1920 efx_schedule_channel(channel);
1921}
1922
1923#endif
1924
1925/**************************************************************************
1926 *
1927 * Kernel net device interface
1928 *
1929 *************************************************************************/
1930
1931/* Context: process, rtnl_lock() held. */
1932static int efx_net_open(struct net_device *net_dev)
1933{
767e468c 1934 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH		 1935 int rc;
1936
62776d03
BH		 1937 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1938 raw_smp_processor_id());
8ceee660 1939
8b7325b4
BH		 1940 rc = efx_check_disabled(efx);
1941 if (rc)
1942 return rc;
f8b87c17
BH		 1943 if (efx->phy_mode & PHY_MODE_SPECIAL)
1944 return -EBUSY;
8880f4ec
BH		 1945 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1946 return -EIO;
f8b87c17 1947
78c1f0a0
SH		 1948 /* Notify the kernel of the link state polled during driver load,
1949 * before the monitor starts running */
1950 efx_link_status_changed(efx);
1951
8ceee660 1952 efx_start_all(efx);
dd40781e 1953 efx_selftest_async_start(efx);
8ceee660
BH		 1954 return 0;
1955}
1956
1957/* Context: process, rtnl_lock() held.
1958 * Note that the kernel will ignore our return code; this method
1959 * should really be a void.
1960 */
1961static int efx_net_stop(struct net_device *net_dev)
1962{
767e468c 1963 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1964
62776d03
BH		 1965 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1966 raw_smp_processor_id());
8ceee660 1967
8b7325b4
BH		 1968 /* Stop the device and flush all the channels */
1969 efx_stop_all(efx);
8ceee660
BH		 1970
1971 return 0;
1972}
1973
5b9e207c 1974/* Context: process, dev_base_lock or RTNL held, non-blocking. */
2aa9ef11
BH		 1975static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
1976 struct rtnl_link_stats64 *stats)
8ceee660 1977{
767e468c 1978 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1979
55edc6e6 1980 spin_lock_bh(&efx->stats_lock);
cd0ecc9a 1981 efx->type->update_stats(efx, NULL, stats);
1cb34522
BH		 1982 spin_unlock_bh(&efx->stats_lock);
1983
8ceee660
BH		 1984 return stats;
1985}
1986
1987/* Context: netif_tx_lock held, BHs disabled. */
1988static void efx_watchdog(struct net_device *net_dev)
1989{
767e468c 1990 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1991
62776d03
BH		 1992 netif_err(efx, tx_err, efx->net_dev,
1993 "TX stuck with port_enabled=%d: resetting channels\n",
1994 efx->port_enabled);
8ceee660 1995
739bb23d 1996 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 1997}
1998
1999
2000/* Context: process, rtnl_lock() held. */
2001static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
2002{
767e468c 2003 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 2004 int rc;
8ceee660 2005
8b7325b4
BH		 2006 rc = efx_check_disabled(efx);
2007 if (rc)
2008 return rc;
8ceee660
BH		 2009 if (new_mtu > EFX_MAX_MTU)
2010 return -EINVAL;
2011
62776d03 2012 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 2013
29c69a48
BH		 2014 efx_device_detach_sync(efx);
2015 efx_stop_all(efx);
2016
d3245b28 2017 mutex_lock(&efx->mac_lock);
8ceee660 2018 net_dev->mtu = new_mtu;
710b208d 2019 efx->type->reconfigure_mac(efx);
d3245b28
BH		 2020 mutex_unlock(&efx->mac_lock);
2021
8ceee660 2022 efx_start_all(efx);
29c69a48 2023 netif_device_attach(efx->net_dev);
6c8eef4a 2024 return 0;
8ceee660
BH		 2025}
2026
2027static int efx_set_mac_address(struct net_device *net_dev, void *data)
2028{
767e468c 2029 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 2030 struct sockaddr *addr = data;
2031 char *new_addr = addr->sa_data;
2032
8ceee660 2033 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH		 2034 netif_err(efx, drv, efx->net_dev,
2035 "invalid ethernet MAC address requested: %pM\n",
2036 new_addr);
504f9b5a 2037 return -EADDRNOTAVAIL;
8ceee660
BH		 2038 }
2039
2040 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
cd2d5b52 2041 efx_sriov_mac_address_changed(efx);
8ceee660
BH		 2042
2043 /* Reconfigure the MAC */
d3245b28 2044 mutex_lock(&efx->mac_lock);
710b208d 2045 efx->type->reconfigure_mac(efx);
d3245b28 2046 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 2047
2048 return 0;
2049}
2050
a816f75a 2051/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 2052static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 2053{
767e468c 2054 struct efx_nic *efx = netdev_priv(net_dev);
a816f75a 2055
8be4f3e6
BH		 2056 if (efx->port_enabled)
2057 queue_work(efx->workqueue, &efx->mac_work);
2058 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 2059}
2060
c8f44aff 2061static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH		 2062{
2063 struct efx_nic *efx = netdev_priv(net_dev);
2064
2065 /* If disabling RX n-tuple filtering, clear existing filters */
2066 if (net_dev->features & ~data & NETIF_F_NTUPLE)
2067 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2068
2069 return 0;
2070}
2071
8127d661 2072static const struct net_device_ops efx_farch_netdev_ops = {
c3ecb9f3
SH		 2073 .ndo_open = efx_net_open,
2074 .ndo_stop = efx_net_stop,
4472702e 2075 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH		 2076 .ndo_tx_timeout = efx_watchdog,
2077 .ndo_start_xmit = efx_hard_start_xmit,
2078 .ndo_validate_addr = eth_validate_addr,
2079 .ndo_do_ioctl = efx_ioctl,
2080 .ndo_change_mtu = efx_change_mtu,
2081 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2082 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2083 .ndo_set_features = efx_set_features,
cd2d5b52
BH		 2084#ifdef CONFIG_SFC_SRIOV
2085 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2086 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2087 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2088 .ndo_get_vf_config = efx_sriov_get_vf_config,
2089#endif
c3ecb9f3
SH		 2090#ifdef CONFIG_NET_POLL_CONTROLLER
2091 .ndo_poll_controller = efx_netpoll,
2092#endif
94b274bf 2093 .ndo_setup_tc = efx_setup_tc,
64d8ad6d
BH		 2094#ifdef CONFIG_RFS_ACCEL
2095 .ndo_rx_flow_steer = efx_filter_rfs,
2096#endif
c3ecb9f3
SH		 2097};
2098
8127d661
BH		 2099static const struct net_device_ops efx_ef10_netdev_ops = {
2100 .ndo_open = efx_net_open,
2101 .ndo_stop = efx_net_stop,
2102 .ndo_get_stats64 = efx_net_stats,
2103 .ndo_tx_timeout = efx_watchdog,
2104 .ndo_start_xmit = efx_hard_start_xmit,
2105 .ndo_validate_addr = eth_validate_addr,
2106 .ndo_do_ioctl = efx_ioctl,
2107 .ndo_change_mtu = efx_change_mtu,
2108 .ndo_set_mac_address = efx_set_mac_address,
2109 .ndo_set_rx_mode = efx_set_rx_mode,
2110 .ndo_set_features = efx_set_features,
2111#ifdef CONFIG_NET_POLL_CONTROLLER
2112 .ndo_poll_controller = efx_netpoll,
2113#endif
2114#ifdef CONFIG_RFS_ACCEL
2115 .ndo_rx_flow_steer = efx_filter_rfs,
2116#endif
2117};
2118
7dde596e
BH		 2119static void efx_update_name(struct efx_nic *efx)
2120{
2121 strcpy(efx->name, efx->net_dev->name);
2122 efx_mtd_rename(efx);
2123 efx_set_channel_names(efx);
2124}
2125
8ceee660
BH		 2126static int efx_netdev_event(struct notifier_block *this,
2127 unsigned long event, void *ptr)
2128{
351638e7 2129 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
8ceee660 2130
8127d661
BH		 2131 if ((net_dev->netdev_ops == &efx_farch_netdev_ops ||
2132 net_dev->netdev_ops == &efx_ef10_netdev_ops) &&
7dde596e
BH		 2133 event == NETDEV_CHANGENAME)
2134 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 2135
2136 return NOTIFY_DONE;
2137}
2138
2139static struct notifier_block efx_netdev_notifier = {
2140 .notifier_call = efx_netdev_event,
2141};
2142
06d5e193
BH		 2143static ssize_t
2144show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2145{
2146 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2147 return sprintf(buf, "%d\n", efx->phy_type);
2148}
776fbcc9 2149static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
06d5e193 2150
8ceee660
BH		 2151static int efx_register_netdev(struct efx_nic *efx)
2152{
2153 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2154 struct efx_channel *channel;
8ceee660
BH		 2155 int rc;
2156
2157 net_dev->watchdog_timeo = 5 * HZ;
2158 net_dev->irq = efx->pci_dev->irq;
8127d661
BH		 2159 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) {
2160 net_dev->netdev_ops = &efx_ef10_netdev_ops;
2161 net_dev->priv_flags |= IFF_UNICAST_FLT;
2162 } else {
2163 net_dev->netdev_ops = &efx_farch_netdev_ops;
2164 }
8ceee660 2165 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
7e6d06f0 2166 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
8ceee660 2167
7dde596e 2168 rtnl_lock();
aed0628d 2169
7153f623
BH		 2170 /* Enable resets to be scheduled and check whether any were
2171 * already requested. If so, the NIC is probably hosed so we
2172 * abort.
2173 */
2174 efx->state = STATE_READY;
2175 smp_mb(); /* ensure we change state before checking reset_pending */
2176 if (efx->reset_pending) {
2177 netif_err(efx, probe, efx->net_dev,
2178 "aborting probe due to scheduled reset\n");
2179 rc = -EIO;
2180 goto fail_locked;
2181 }
2182
aed0628d
BH		 2183 rc = dev_alloc_name(net_dev, net_dev->name);
2184 if (rc < 0)
2185 goto fail_locked;
7dde596e 2186 efx_update_name(efx);
aed0628d 2187
8f8b3d51
BH		 2188 /* Always start with carrier off; PHY events will detect the link */
2189 netif_carrier_off(net_dev);
2190
aed0628d
BH		 2191 rc = register_netdevice(net_dev);
2192 if (rc)
2193 goto fail_locked;
2194
c04bfc6b
BH		 2195 efx_for_each_channel(channel, efx) {
2196 struct efx_tx_queue *tx_queue;
60031fcc
BH		 2197 efx_for_each_channel_tx_queue(tx_queue, channel)
2198 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH		 2199 }
2200
7dde596e 2201 rtnl_unlock();
8ceee660 2202
06d5e193
BH		 2203 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2204 if (rc) {
62776d03
BH		 2205 netif_err(efx, drv, efx->net_dev,
2206 "failed to init net dev attributes\n");
06d5e193
BH		 2207 goto fail_registered;
2208 }
2209
8ceee660 2210 return 0;
06d5e193 2211
7153f623
BH		 2212fail_registered:
2213 rtnl_lock();
2214 unregister_netdevice(net_dev);
aed0628d 2215fail_locked:
7153f623 2216 efx->state = STATE_UNINIT;
aed0628d 2217 rtnl_unlock();
62776d03 2218 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2219 return rc;
8ceee660
BH		 2220}
2221
2222static void efx_unregister_netdev(struct efx_nic *efx)
2223{
8ceee660
BH		 2224 if (!efx->net_dev)
2225 return;
2226
767e468c 2227 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660 2228
73ba7b68
BH		 2229 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2230 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
7153f623
BH		 2231
2232 rtnl_lock();
2233 unregister_netdevice(efx->net_dev);
2234 efx->state = STATE_UNINIT;
2235 rtnl_unlock();
8ceee660
BH		 2236}
2237
2238/**************************************************************************
2239 *
2240 * Device reset and suspend
2241 *
2242 **************************************************************************/
2243
2467ca46
BH		 2244/* Tears down the entire software state and most of the hardware state
2245 * before reset. */
d3245b28 2246void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2247{
8ceee660
BH		 2248 EFX_ASSERT_RESET_SERIALISED(efx);
2249
2467ca46 2250 efx_stop_all(efx);
d8291187 2251 efx_disable_interrupts(efx);
5642ceef
BH		 2252
2253 mutex_lock(&efx->mac_lock);
4b988280
SH		 2254 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2255 efx->phy_op->fini(efx);
ef2b90ee 2256 efx->type->fini(efx);
8ceee660
BH		 2257}
2258
2467ca46
BH		 2259/* This function will always ensure that the locks acquired in
2260 * efx_reset_down() are released. A failure return code indicates
2261 * that we were unable to reinitialise the hardware, and the
2262 * driver should be disabled. If ok is false, then the rx and tx
2263 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2264int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 2265{
2266 int rc;
2267
2467ca46 2268 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2269
ef2b90ee 2270 rc = efx->type->init(efx);
8ceee660 2271 if (rc) {
62776d03 2272 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2273 goto fail;
8ceee660
BH		 2274 }
2275
eb9f6744
BH		 2276 if (!ok)
2277 goto fail;
2278
4b988280 2279 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
eb9f6744
BH		 2280 rc = efx->phy_op->init(efx);
2281 if (rc)
2282 goto fail;
2283 if (efx->phy_op->reconfigure(efx))
62776d03
BH		 2284 netif_err(efx, drv, efx->net_dev,
2285 "could not restore PHY settings\n");
4b988280
SH		 2286 }
2287
261e4d96
JC		 2288 rc = efx_enable_interrupts(efx);
2289 if (rc)
2290 goto fail;
64eebcfd 2291 efx_restore_filters(efx);
cd2d5b52 2292 efx_sriov_reset(efx);
eb9f6744 2293
eb9f6744
BH		 2294 mutex_unlock(&efx->mac_lock);
2295
2296 efx_start_all(efx);
2297
2298 return 0;
2299
2300fail:
2301 efx->port_initialized = false;
2467ca46
BH		 2302
2303 mutex_unlock(&efx->mac_lock);
2304
8ceee660
BH		 2305 return rc;
2306}
2307
eb9f6744
BH		 2308/* Reset the NIC using the specified method. Note that the reset may
2309 * fail, in which case the card will be left in an unusable state.
8ceee660 2310 *
eb9f6744 2311 * Caller must hold the rtnl_lock.
8ceee660 2312 */
eb9f6744 2313int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2314{
eb9f6744
BH		 2315 int rc, rc2;
2316 bool disabled;
8ceee660 2317
62776d03
BH		 2318 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2319 RESET_TYPE(method));
8ceee660 2320
c2f3b8e3 2321 efx_device_detach_sync(efx);
d3245b28 2322 efx_reset_down(efx, method);
8ceee660 2323
ef2b90ee 2324 rc = efx->type->reset(efx, method);
8ceee660 2325 if (rc) {
62776d03 2326 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2327 goto out;
8ceee660
BH		 2328 }
2329
a7d529ae
BH		 2330 /* Clear flags for the scopes we covered. We assume the NIC and
2331 * driver are now quiescent so that there is no race here.
2332 */
2333 efx->reset_pending &= -(1 << (method + 1));
8ceee660
BH		 2334
2335 /* Reinitialise bus-mastering, which may have been turned off before
2336 * the reset was scheduled. This is still appropriate, even in the
2337 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2338 * can respond to requests. */
2339 pci_set_master(efx->pci_dev);
2340
eb9f6744 2341out:
8ceee660 2342 /* Leave device stopped if necessary */
626950db
AR		 2343 disabled = rc ||
2344 method == RESET_TYPE_DISABLE ||
2345 method == RESET_TYPE_RECOVER_OR_DISABLE;
eb9f6744
BH		 2346 rc2 = efx_reset_up(efx, method, !disabled);
2347 if (rc2) {
2348 disabled = true;
2349 if (!rc)
2350 rc = rc2;
8ceee660
BH		 2351 }
2352
eb9f6744 2353 if (disabled) {
f49a4589 2354 dev_close(efx->net_dev);
62776d03 2355 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2356 efx->state = STATE_DISABLED;
f4bd954e 2357 } else {
62776d03 2358 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2359 netif_device_attach(efx->net_dev);
f4bd954e 2360 }
8ceee660
BH		 2361 return rc;
2362}
2363
626950db
AR		 2364/* Try recovery mechanisms.
2365 * For now only EEH is supported.
2366 * Returns 0 if the recovery mechanisms are unsuccessful.
2367 * Returns a non-zero value otherwise.
2368 */
b28405b0 2369int efx_try_recovery(struct efx_nic *efx)
626950db
AR		 2370{
2371#ifdef CONFIG_EEH
2372 /* A PCI error can occur and not be seen by EEH because nothing
2373 * happens on the PCI bus. In this case the driver may fail and
2374 * schedule a 'recover or reset', leading to this recovery handler.
2375 * Manually call the eeh failure check function.
2376 */
2377 struct eeh_dev *eehdev =
2378 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
2379
2380 if (eeh_dev_check_failure(eehdev)) {
2381 /* The EEH mechanisms will handle the error and reset the
2382 * device if necessary.
2383 */
2384 return 1;
2385 }
2386#endif
2387 return 0;
2388}
2389
8ceee660
BH		 2390/* The worker thread exists so that code that cannot sleep can
2391 * schedule a reset for later.
2392 */
2393static void efx_reset_work(struct work_struct *data)
2394{
eb9f6744 2395 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
626950db
AR		 2396 unsigned long pending;
2397 enum reset_type method;
2398
2399 pending = ACCESS_ONCE(efx->reset_pending);
2400 method = fls(pending) - 1;
2401
2402 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2403 method == RESET_TYPE_RECOVER_OR_ALL) &&
2404 efx_try_recovery(efx))
2405 return;
8ceee660 2406
a7d529ae 2407 if (!pending)
319ba649
SH		 2408 return;
2409
eb9f6744 2410 rtnl_lock();
7153f623
BH		 2411
2412 /* We checked the state in efx_schedule_reset() but it may
2413 * have changed by now. Now that we have the RTNL lock,
2414 * it cannot change again.
2415 */
2416 if (efx->state == STATE_READY)
626950db 2417 (void)efx_reset(efx, method);
7153f623 2418
eb9f6744 2419 rtnl_unlock();
8ceee660
BH		 2420}
2421
2422void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2423{
2424 enum reset_type method;
2425
626950db
AR		 2426 if (efx->state == STATE_RECOVERY) {
2427 netif_dbg(efx, drv, efx->net_dev,
2428 "recovering: skip scheduling %s reset\n",
2429 RESET_TYPE(type));
2430 return;
2431 }
2432
8ceee660
BH		 2433 switch (type) {
2434 case RESET_TYPE_INVISIBLE:
2435 case RESET_TYPE_ALL:
626950db 2436 case RESET_TYPE_RECOVER_OR_ALL:
8ceee660
BH		 2437 case RESET_TYPE_WORLD:
2438 case RESET_TYPE_DISABLE:
626950db 2439 case RESET_TYPE_RECOVER_OR_DISABLE:
8ceee660 2440 method = type;
0e2a9c7c
BH		 2441 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2442 RESET_TYPE(method));
8ceee660 2443 break;
8ceee660 2444 default:
0e2a9c7c 2445 method = efx->type->map_reset_reason(type);
62776d03
BH		 2446 netif_dbg(efx, drv, efx->net_dev,
2447 "scheduling %s reset for %s\n",
2448 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH		 2449 break;
2450 }
8ceee660 2451
a7d529ae 2452 set_bit(method, &efx->reset_pending);
7153f623
BH		 2453 smp_mb(); /* ensure we change reset_pending before checking state */
2454
2455 /* If we're not READY then just leave the flags set as the cue
2456 * to abort probing or reschedule the reset later.
2457 */
2458 if (ACCESS_ONCE(efx->state) != STATE_READY)
2459 return;
8ceee660 2460
8880f4ec
BH		 2461 /* efx_process_channel() will no longer read events once a
2462 * reset is scheduled. So switch back to poll'd MCDI completions. */
2463 efx_mcdi_mode_poll(efx);
2464
1ab00629 2465 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 2466}
2467
2468/**************************************************************************
2469 *
2470 * List of NICs we support
2471 *
2472 **************************************************************************/
2473
2474/* PCI device ID table */
a3aa1884 2475static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
937383a5
BH		 2476 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2477 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
daeda630 2478 .driver_data = (unsigned long) &falcon_a1_nic_type},
937383a5
BH		 2479 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2480 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
daeda630 2481 .driver_data = (unsigned long) &falcon_b0_nic_type},
547c474f 2482 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2483 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2484 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2485 .driver_data = (unsigned long) &siena_a0_nic_type},
8127d661
BH		 2486 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */
2487 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
8ceee660
BH		 2488 {0} /* end of list */
2489};
2490
2491/**************************************************************************
2492 *
3759433d 2493 * Dummy PHY/MAC operations
8ceee660 2494 *
01aad7b6 2495 * Can be used for some unimplemented operations
8ceee660
BH		 2496 * Needed so all function pointers are valid and do not have to be tested
2497 * before use
2498 *
2499 **************************************************************************/
2500int efx_port_dummy_op_int(struct efx_nic *efx)
2501{
2502 return 0;
2503}
2504void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2505
2506static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH		 2507{
2508 return false;
2509}
8ceee660 2510
6c8c2513 2511static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2512 .init = efx_port_dummy_op_int,
d3245b28 2513 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2514 .poll = efx_port_dummy_op_poll,
8ceee660 2515 .fini = efx_port_dummy_op_void,
8ceee660
BH		 2516};
2517
8ceee660
BH		 2518/**************************************************************************
2519 *
2520 * Data housekeeping
2521 *
2522 **************************************************************************/
2523
2524/* This zeroes out and then fills in the invariants in a struct
2525 * efx_nic (including all sub-structures).
2526 */
adeb15aa 2527static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH		 2528 struct pci_dev *pci_dev, struct net_device *net_dev)
2529{
4642610c 2530 int i;
8ceee660
BH		 2531
2532 /* Initialise common structures */
8ceee660 2533 spin_lock_init(&efx->biu_lock);
76884835
BH		 2534#ifdef CONFIG_SFC_MTD
2535 INIT_LIST_HEAD(&efx->mtd_list);
2536#endif
8ceee660
BH		 2537 INIT_WORK(&efx->reset_work, efx_reset_work);
2538 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2539 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2540 efx->pci_dev = pci_dev;
62776d03 2541 efx->msg_enable = debug;
f16aeea0 2542 efx->state = STATE_UNINIT;
8ceee660 2543 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2544
2545 efx->net_dev = net_dev;
43a3739d
JC		 2546 efx->rx_prefix_size = efx->type->rx_prefix_size;
2547 efx->rx_packet_hash_offset =
2548 efx->type->rx_hash_offset - efx->type->rx_prefix_size;
8ceee660
BH		 2549 spin_lock_init(&efx->stats_lock);
2550 mutex_init(&efx->mac_lock);
2551 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2552 efx->mdio.dev = net_dev;
766ca0fa 2553 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2554 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH		 2555
2556 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH		 2557 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2558 if (!efx->channel[i])
2559 goto fail;
d8291187
BH		 2560 efx->msi_context[i].efx = efx;
2561 efx->msi_context[i].index = i;
8ceee660
BH		 2562 }
2563
8ceee660
BH		 2564 /* Higher numbered interrupt modes are less capable! */
2565 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2566 interrupt_mode);
2567
6977dc63
BH		 2568 /* Would be good to use the net_dev name, but we're too early */
2569 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2570 pci_name(pci_dev));
2571 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2572 if (!efx->workqueue)
4642610c 2573 goto fail;
8d9853d9 2574
8ceee660 2575 return 0;
4642610c
BH		 2576
2577fail:
2578 efx_fini_struct(efx);
2579 return -ENOMEM;
8ceee660
BH		 2580}
2581
2582static void efx_fini_struct(struct efx_nic *efx)
2583{
8313aca3
BH		 2584 int i;
2585
2586 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2587 kfree(efx->channel[i]);
2588
8ceee660
BH		 2589 if (efx->workqueue) {
2590 destroy_workqueue(efx->workqueue);
2591 efx->workqueue = NULL;
2592 }
2593}
2594
2595/**************************************************************************
2596 *
2597 * PCI interface
2598 *
2599 **************************************************************************/
2600
2601/* Main body of final NIC shutdown code
2602 * This is called only at module unload (or hotplug removal).
2603 */
2604static void efx_pci_remove_main(struct efx_nic *efx)
2605{
7153f623
BH		 2606 /* Flush reset_work. It can no longer be scheduled since we
2607 * are not READY.
2608 */
2609 BUG_ON(efx->state == STATE_READY);
2610 cancel_work_sync(&efx->reset_work);
2611
d8291187 2612 efx_disable_interrupts(efx);
152b6a62 2613 efx_nic_fini_interrupt(efx);
8ceee660 2614 efx_fini_port(efx);
ef2b90ee 2615 efx->type->fini(efx);
8ceee660
BH		 2616 efx_fini_napi(efx);
2617 efx_remove_all(efx);
2618}
2619
2620/* Final NIC shutdown
2621 * This is called only at module unload (or hotplug removal).
2622 */
2623static void efx_pci_remove(struct pci_dev *pci_dev)
2624{
2625 struct efx_nic *efx;
2626
2627 efx = pci_get_drvdata(pci_dev);
2628 if (!efx)
2629 return;
2630
2631 /* Mark the NIC as fini, then stop the interface */
2632 rtnl_lock();
8ceee660 2633 dev_close(efx->net_dev);
d8291187 2634 efx_disable_interrupts(efx);
8ceee660
BH		 2635 rtnl_unlock();
2636
cd2d5b52 2637 efx_sriov_fini(efx);
8ceee660
BH		 2638 efx_unregister_netdev(efx);
2639
7dde596e
BH		 2640 efx_mtd_remove(efx);
2641
8ceee660
BH		 2642 efx_pci_remove_main(efx);
2643
8ceee660 2644 efx_fini_io(efx);
62776d03 2645 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 2646
8ceee660 2647 efx_fini_struct(efx);
3de4e301 2648 pci_set_drvdata(pci_dev, NULL);
8ceee660 2649 free_netdev(efx->net_dev);
626950db
AR		 2650
2651 pci_disable_pcie_error_reporting(pci_dev);
8ceee660
BH		 2652};
2653
460eeaa0
BH		 2654/* NIC VPD information
2655 * Called during probe to display the part number of the
2656 * installed NIC. VPD is potentially very large but this should
2657 * always appear within the first 512 bytes.
2658 */
2659#define SFC_VPD_LEN 512
2660static void efx_print_product_vpd(struct efx_nic *efx)
2661{
2662 struct pci_dev *dev = efx->pci_dev;
2663 char vpd_data[SFC_VPD_LEN];
2664 ssize_t vpd_size;
2665 int i, j;
2666
2667 /* Get the vpd data from the device */
2668 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
2669 if (vpd_size <= 0) {
2670 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
2671 return;
2672 }
2673
2674 /* Get the Read only section */
2675 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
2676 if (i < 0) {
2677 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
2678 return;
2679 }
2680
2681 j = pci_vpd_lrdt_size(&vpd_data[i]);
2682 i += PCI_VPD_LRDT_TAG_SIZE;
2683 if (i + j > vpd_size)
2684 j = vpd_size - i;
2685
2686 /* Get the Part number */
2687 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
2688 if (i < 0) {
2689 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
2690 return;
2691 }
2692
2693 j = pci_vpd_info_field_size(&vpd_data[i]);
2694 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2695 if (i + j > vpd_size) {
2696 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
2697 return;
2698 }
2699
2700 netif_info(efx, drv, efx->net_dev,
2701 "Part Number : %.*s\n", j, &vpd_data[i]);
2702}
2703
2704
8ceee660
BH		 2705/* Main body of NIC initialisation
2706 * This is called at module load (or hotplug insertion, theoretically).
2707 */
2708static int efx_pci_probe_main(struct efx_nic *efx)
2709{
2710 int rc;
2711
2712 /* Do start-of-day initialisation */
2713 rc = efx_probe_all(efx);
2714 if (rc)
2715 goto fail1;
2716
e8f14992 2717 efx_init_napi(efx);
8ceee660 2718
ef2b90ee 2719 rc = efx->type->init(efx);
8ceee660 2720 if (rc) {
62776d03
BH		 2721 netif_err(efx, probe, efx->net_dev,
2722 "failed to initialise NIC\n");
278c0621 2723 goto fail3;
8ceee660
BH		 2724 }
2725
2726 rc = efx_init_port(efx);
2727 if (rc) {
62776d03
BH		 2728 netif_err(efx, probe, efx->net_dev,
2729 "failed to initialise port\n");
278c0621 2730 goto fail4;
8ceee660
BH		 2731 }
2732
152b6a62 2733 rc = efx_nic_init_interrupt(efx);
8ceee660 2734 if (rc)
278c0621 2735 goto fail5;
261e4d96
JC		 2736 rc = efx_enable_interrupts(efx);
2737 if (rc)
2738 goto fail6;
8ceee660
BH		 2739
2740 return 0;
2741
261e4d96
JC		 2742 fail6:
2743 efx_nic_fini_interrupt(efx);
278c0621 2744 fail5:
8ceee660 2745 efx_fini_port(efx);
8ceee660 2746 fail4:
ef2b90ee 2747 efx->type->fini(efx);
8ceee660
BH		 2748 fail3:
2749 efx_fini_napi(efx);
8ceee660
BH		 2750 efx_remove_all(efx);
2751 fail1:
2752 return rc;
2753}
2754
2755/* NIC initialisation
2756 *
2757 * This is called at module load (or hotplug insertion,
73ba7b68 2758 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH		 2759 * sets up and registers the network devices with the kernel and hooks
2760 * the interrupt service routine. It does not prepare the device for
2761 * transmission; this is left to the first time one of the network
2762 * interfaces is brought up (i.e. efx_net_open).
2763 */
87d1fc11 2764static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 2765 const struct pci_device_id *entry)
8ceee660 2766{
8ceee660
BH		 2767 struct net_device *net_dev;
2768 struct efx_nic *efx;
fadac6aa 2769 int rc;
8ceee660
BH		 2770
2771 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH		 2772 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2773 EFX_MAX_RX_QUEUES);
8ceee660
BH		 2774 if (!net_dev)
2775 return -ENOMEM;
adeb15aa
BH		 2776 efx = netdev_priv(net_dev);
2777 efx->type = (const struct efx_nic_type *) entry->driver_data;
2778 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
97bc5415 2779 NETIF_F_HIGHDMA | NETIF_F_TSO |
abfe9039 2780 NETIF_F_RXCSUM);
adeb15aa 2781 if (efx->type->offload_features & NETIF_F_V6_CSUM)
738a8f4b 2782 net_dev->features |= NETIF_F_TSO6;
28506563
BH		 2783 /* Mask for features that also apply to VLAN devices */
2784 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
abfe9039
BH		 2785 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2786 NETIF_F_RXCSUM);
2787 /* All offloads can be toggled */
2788 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
8ceee660 2789 pci_set_drvdata(pci_dev, efx);
62776d03 2790 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 2791 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH		 2792 if (rc)
2793 goto fail1;
2794
62776d03 2795 netif_info(efx, probe, efx->net_dev,
ff79c8ac 2796 "Solarflare NIC detected\n");
8ceee660 2797
460eeaa0
BH		 2798 efx_print_product_vpd(efx);
2799
8ceee660
BH		 2800 /* Set up basic I/O (BAR mappings etc) */
2801 rc = efx_init_io(efx);
2802 if (rc)
2803 goto fail2;
2804
fadac6aa 2805 rc = efx_pci_probe_main(efx);
fadac6aa
BH		 2806 if (rc)
2807 goto fail3;
8ceee660 2808
8ceee660
BH		 2809 rc = efx_register_netdev(efx);
2810 if (rc)
fadac6aa 2811 goto fail4;
8ceee660 2812
cd2d5b52
BH		 2813 rc = efx_sriov_init(efx);
2814 if (rc)
2815 netif_err(efx, probe, efx->net_dev,
2816 "SR-IOV can't be enabled rc %d\n", rc);
2817
62776d03 2818 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 2819
7c43161c 2820 /* Try to create MTDs, but allow this to fail */
a5211bb5 2821 rtnl_lock();
7c43161c 2822 rc = efx_mtd_probe(efx);
a5211bb5 2823 rtnl_unlock();
7c43161c
BH		 2824 if (rc)
2825 netif_warn(efx, probe, efx->net_dev,
2826 "failed to create MTDs (%d)\n", rc);
2827
626950db
AR		 2828 rc = pci_enable_pcie_error_reporting(pci_dev);
2829 if (rc && rc != -EINVAL)
2830 netif_warn(efx, probe, efx->net_dev,
2831 "pci_enable_pcie_error_reporting failed (%d)\n", rc);
2832
8ceee660
BH		 2833 return 0;
2834
8ceee660 2835 fail4:
fadac6aa 2836 efx_pci_remove_main(efx);
8ceee660
BH		 2837 fail3:
2838 efx_fini_io(efx);
2839 fail2:
2840 efx_fini_struct(efx);
2841 fail1:
3de4e301 2842 pci_set_drvdata(pci_dev, NULL);
5e2a911c 2843 WARN_ON(rc > 0);
62776d03 2844 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH		 2845 free_netdev(net_dev);
2846 return rc;
2847}
2848
89c758fa
BH		 2849static int efx_pm_freeze(struct device *dev)
2850{
2851 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2852
61da026d
BH		 2853 rtnl_lock();
2854
6032fb56
BH		 2855 if (efx->state != STATE_DISABLED) {
2856 efx->state = STATE_UNINIT;
89c758fa 2857
c2f3b8e3 2858 efx_device_detach_sync(efx);
89c758fa 2859
6032fb56 2860 efx_stop_all(efx);
d8291187 2861 efx_disable_interrupts(efx);
6032fb56 2862 }
89c758fa 2863
61da026d
BH		 2864 rtnl_unlock();
2865
89c758fa
BH		 2866 return 0;
2867}
2868
2869static int efx_pm_thaw(struct device *dev)
2870{
261e4d96 2871 int rc;
89c758fa
BH		 2872 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2873
61da026d
BH		 2874 rtnl_lock();
2875
6032fb56 2876 if (efx->state != STATE_DISABLED) {
261e4d96
JC		 2877 rc = efx_enable_interrupts(efx);
2878 if (rc)
2879 goto fail;
89c758fa 2880
6032fb56
BH		 2881 mutex_lock(&efx->mac_lock);
2882 efx->phy_op->reconfigure(efx);
2883 mutex_unlock(&efx->mac_lock);
89c758fa 2884
6032fb56 2885 efx_start_all(efx);
89c758fa 2886
6032fb56 2887 netif_device_attach(efx->net_dev);
89c758fa 2888
6032fb56 2889 efx->state = STATE_READY;
89c758fa 2890
6032fb56
BH		 2891 efx->type->resume_wol(efx);
2892 }
89c758fa 2893
61da026d
BH		 2894 rtnl_unlock();
2895
319ba649
SH		 2896 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2897 queue_work(reset_workqueue, &efx->reset_work);
2898
89c758fa 2899 return 0;
261e4d96
JC		 2900
2901fail:
2902 rtnl_unlock();
2903
2904 return rc;
89c758fa
BH		 2905}
2906
2907static int efx_pm_poweroff(struct device *dev)
2908{
2909 struct pci_dev *pci_dev = to_pci_dev(dev);
2910 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2911
2912 efx->type->fini(efx);
2913
a7d529ae 2914 efx->reset_pending = 0;
89c758fa
BH		 2915
2916 pci_save_state(pci_dev);
2917 return pci_set_power_state(pci_dev, PCI_D3hot);
2918}
2919
2920/* Used for both resume and restore */
2921static int efx_pm_resume(struct device *dev)
2922{
2923 struct pci_dev *pci_dev = to_pci_dev(dev);
2924 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2925 int rc;
2926
2927 rc = pci_set_power_state(pci_dev, PCI_D0);
2928 if (rc)
2929 return rc;
2930 pci_restore_state(pci_dev);
2931 rc = pci_enable_device(pci_dev);
2932 if (rc)
2933 return rc;
2934 pci_set_master(efx->pci_dev);
2935 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2936 if (rc)
2937 return rc;
2938 rc = efx->type->init(efx);
2939 if (rc)
2940 return rc;
261e4d96
JC		 2941 rc = efx_pm_thaw(dev);
2942 return rc;
89c758fa
BH		 2943}
2944
2945static int efx_pm_suspend(struct device *dev)
2946{
2947 int rc;
2948
2949 efx_pm_freeze(dev);
2950 rc = efx_pm_poweroff(dev);
2951 if (rc)
2952 efx_pm_resume(dev);
2953 return rc;
2954}
2955
18e83e4c 2956static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH		 2957 .suspend = efx_pm_suspend,
2958 .resume = efx_pm_resume,
2959 .freeze = efx_pm_freeze,
2960 .thaw = efx_pm_thaw,
2961 .poweroff = efx_pm_poweroff,
2962 .restore = efx_pm_resume,
2963};
2964
626950db
AR		 2965/* A PCI error affecting this device was detected.
2966 * At this point MMIO and DMA may be disabled.
2967 * Stop the software path and request a slot reset.
2968 */
debd0034 2969static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
2970 enum pci_channel_state state)
626950db
AR		 2971{
2972 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2973 struct efx_nic *efx = pci_get_drvdata(pdev);
2974
2975 if (state == pci_channel_io_perm_failure)
2976 return PCI_ERS_RESULT_DISCONNECT;
2977
2978 rtnl_lock();
2979
2980 if (efx->state != STATE_DISABLED) {
2981 efx->state = STATE_RECOVERY;
2982 efx->reset_pending = 0;
2983
2984 efx_device_detach_sync(efx);
2985
2986 efx_stop_all(efx);
d8291187 2987 efx_disable_interrupts(efx);
626950db
AR		 2988
2989 status = PCI_ERS_RESULT_NEED_RESET;
2990 } else {
2991 /* If the interface is disabled we don't want to do anything
2992 * with it.
2993 */
2994 status = PCI_ERS_RESULT_RECOVERED;
2995 }
2996
2997 rtnl_unlock();
2998
2999 pci_disable_device(pdev);
3000
3001 return status;
3002}
3003
3004/* Fake a successfull reset, which will be performed later in efx_io_resume. */
debd0034 3005static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
626950db
AR		 3006{
3007 struct efx_nic *efx = pci_get_drvdata(pdev);
3008 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3009 int rc;
3010
3011 if (pci_enable_device(pdev)) {
3012 netif_err(efx, hw, efx->net_dev,
3013 "Cannot re-enable PCI device after reset.\n");
3014 status = PCI_ERS_RESULT_DISCONNECT;
3015 }
3016
3017 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
3018 if (rc) {
3019 netif_err(efx, hw, efx->net_dev,
3020 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
3021 /* Non-fatal error. Continue. */
3022 }
3023
3024 return status;
3025}
3026
3027/* Perform the actual reset and resume I/O operations. */
3028static void efx_io_resume(struct pci_dev *pdev)
3029{
3030 struct efx_nic *efx = pci_get_drvdata(pdev);
3031 int rc;
3032
3033 rtnl_lock();
3034
3035 if (efx->state == STATE_DISABLED)
3036 goto out;
3037
3038 rc = efx_reset(efx, RESET_TYPE_ALL);
3039 if (rc) {
3040 netif_err(efx, hw, efx->net_dev,
3041 "efx_reset failed after PCI error (%d)\n", rc);
3042 } else {
3043 efx->state = STATE_READY;
3044 netif_dbg(efx, hw, efx->net_dev,
3045 "Done resetting and resuming IO after PCI error.\n");
3046 }
3047
3048out:
3049 rtnl_unlock();
3050}
3051
3052/* For simplicity and reliability, we always require a slot reset and try to
3053 * reset the hardware when a pci error affecting the device is detected.
3054 * We leave both the link_reset and mmio_enabled callback unimplemented:
3055 * with our request for slot reset the mmio_enabled callback will never be
3056 * called, and the link_reset callback is not used by AER or EEH mechanisms.
3057 */
3058static struct pci_error_handlers efx_err_handlers = {
3059 .error_detected = efx_io_error_detected,
3060 .slot_reset = efx_io_slot_reset,
3061 .resume = efx_io_resume,
3062};
3063
8ceee660 3064static struct pci_driver efx_pci_driver = {
c5d5f5fd 3065 .name = KBUILD_MODNAME,
8ceee660
BH		 3066 .id_table = efx_pci_table,
3067 .probe = efx_pci_probe,
3068 .remove = efx_pci_remove,
89c758fa 3069 .driver.pm = &efx_pm_ops,
626950db 3070 .err_handler = &efx_err_handlers,
8ceee660
BH		 3071};
3072
3073/**************************************************************************
3074 *
3075 * Kernel module interface
3076 *
3077 *************************************************************************/
3078
3079module_param(interrupt_mode, uint, 0444);
3080MODULE_PARM_DESC(interrupt_mode,
3081 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
3082
3083static int __init efx_init_module(void)
3084{
3085 int rc;
3086
3087 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
3088
3089 rc = register_netdevice_notifier(&efx_netdev_notifier);
3090 if (rc)
3091 goto err_notifier;
3092
cd2d5b52
BH		 3093 rc = efx_init_sriov();
3094 if (rc)
3095 goto err_sriov;
3096
1ab00629
SH		 3097 reset_workqueue = create_singlethread_workqueue("sfc_reset");
3098 if (!reset_workqueue) {
3099 rc = -ENOMEM;
3100 goto err_reset;
3101 }
8ceee660
BH		 3102
3103 rc = pci_register_driver(&efx_pci_driver);
3104 if (rc < 0)
3105 goto err_pci;
3106
3107 return 0;
3108
3109 err_pci:
1ab00629
SH		 3110 destroy_workqueue(reset_workqueue);
3111 err_reset:
cd2d5b52
BH		 3112 efx_fini_sriov();
3113 err_sriov:
8ceee660
BH		 3114 unregister_netdevice_notifier(&efx_netdev_notifier);
3115 err_notifier:
3116 return rc;
3117}
3118
3119static void __exit efx_exit_module(void)
3120{
3121 printk(KERN_INFO "Solarflare NET driver unloading\n");
3122
3123 pci_unregister_driver(&efx_pci_driver);
1ab00629 3124 destroy_workqueue(reset_workqueue);
cd2d5b52 3125 efx_fini_sriov();
8ceee660
BH		 3126 unregister_netdevice_notifier(&efx_netdev_notifier);
3127
3128}
3129
3130module_init(efx_init_module);
3131module_exit(efx_exit_module);
3132
906bb26c
BH		 3133MODULE_AUTHOR("Solarflare Communications and "
3134 "Michael Brown <mbrown@fensystems.co.uk>");
8ceee660
BH		 3135MODULE_DESCRIPTION("Solarflare Communications network driver");
3136MODULE_LICENSE("GPL");
3137MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux kernel - Deliverables
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