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net_tstamp: Add SIOCGHWTSTAMP ioctl to match SIOCSHWTSTAMP
[deliverable/linux.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660 1/****************************************************************************
f7a6d2c4 2 * Driver for Solarflare network controllers and boards
8ceee660 3 * Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4 4 * Copyright 2005-2013 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
8ceee660 20#include <linux/ethtool.h>
aa6ef27e 21#include <linux/topology.h>
5a0e3ad6 22#include <linux/gfp.h>
626950db 23#include <linux/aer.h>
b28405b0 24#include <linux/interrupt.h>
8ceee660 25#include "net_driver.h"
8ceee660 26#include "efx.h"
744093c9 27#include "nic.h"
dd40781e 28#include "selftest.h"
8ceee660 29
8880f4ec 30#include "mcdi.h"
fd371e32 31#include "workarounds.h"
8880f4ec 32
c459302d
BH		 33/**************************************************************************
34 *
35 * Type name strings
36 *
37 **************************************************************************
38 */
39
40/* Loopback mode names (see LOOPBACK_MODE()) */
41const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 42const char *const efx_loopback_mode_names[] = {
c459302d 43 [LOOPBACK_NONE] = "NONE",
e58f69f4 44 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 45 [LOOPBACK_GMAC] = "GMAC",
46 [LOOPBACK_XGMII] = "XGMII",
47 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH		 48 [LOOPBACK_XAUI] = "XAUI",
49 [LOOPBACK_GMII] = "GMII",
50 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH		 51 [LOOPBACK_XGBR] = "XGBR",
52 [LOOPBACK_XFI] = "XFI",
53 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
54 [LOOPBACK_GMII_FAR] = "GMII_FAR",
55 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
56 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 57 [LOOPBACK_GPHY] = "GPHY",
58 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH		 59 [LOOPBACK_PCS] = "PCS",
60 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 61 [LOOPBACK_XPORT] = "XPORT",
62 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 63 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH		 64 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
65 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 66 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH		 67 [LOOPBACK_XFI_WS] = "XFI_WS",
68 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 69 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 70};
71
c459302d 72const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 73const char *const efx_reset_type_names[] = {
626950db
AR		 74 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
75 [RESET_TYPE_ALL] = "ALL",
76 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
77 [RESET_TYPE_WORLD] = "WORLD",
78 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
79 [RESET_TYPE_DISABLE] = "DISABLE",
80 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
81 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
82 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
3de82b91 83 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
626950db
AR		 84 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
85 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
c459302d
BH		 86};
87
1ab00629
SH		 88/* Reset workqueue. If any NIC has a hardware failure then a reset will be
89 * queued onto this work queue. This is not a per-nic work queue, because
90 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
91 */
92static struct workqueue_struct *reset_workqueue;
93
8ceee660
BH		 94/**************************************************************************
95 *
96 * Configurable values
97 *
98 *************************************************************************/
99
8ceee660
BH		 100/*
101 * Use separate channels for TX and RX events
102 *
28b581ab
NT		 103 * Set this to 1 to use separate channels for TX and RX. It allows us
104 * to control interrupt affinity separately for TX and RX.
8ceee660 105 *
28b581ab 106 * This is only used in MSI-X interrupt mode
8ceee660 107 */
b9cc977d
BH		 108static bool separate_tx_channels;
109module_param(separate_tx_channels, bool, 0444);
28b581ab
NT		 110MODULE_PARM_DESC(separate_tx_channels,
111 "Use separate channels for TX and RX");
8ceee660
BH		 112
113/* This is the weight assigned to each of the (per-channel) virtual
114 * NAPI devices.
115 */
116static int napi_weight = 64;
117
118/* This is the time (in jiffies) between invocations of the hardware
626950db
AR		 119 * monitor.
120 * On Falcon-based NICs, this will:
e254c274
BH		 121 * - Check the on-board hardware monitor;
122 * - Poll the link state and reconfigure the hardware as necessary.
626950db
AR		 123 * On Siena-based NICs for power systems with EEH support, this will give EEH a
124 * chance to start.
8ceee660 125 */
d215697f 126static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 127
8ceee660
BH		 128/* Initial interrupt moderation settings. They can be modified after
129 * module load with ethtool.
130 *
131 * The default for RX should strike a balance between increasing the
132 * round-trip latency and reducing overhead.
133 */
134static unsigned int rx_irq_mod_usec = 60;
135
136/* Initial interrupt moderation settings. They can be modified after
137 * module load with ethtool.
138 *
139 * This default is chosen to ensure that a 10G link does not go idle
140 * while a TX queue is stopped after it has become full. A queue is
141 * restarted when it drops below half full. The time this takes (assuming
142 * worst case 3 descriptors per packet and 1024 descriptors) is
143 * 512 / 3 * 1.2 = 205 usec.
144 */
145static unsigned int tx_irq_mod_usec = 150;
146
147/* This is the first interrupt mode to try out of:
148 * 0 => MSI-X
149 * 1 => MSI
150 * 2 => legacy
151 */
152static unsigned int interrupt_mode;
153
154/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
155 * i.e. the number of CPUs among which we may distribute simultaneous
156 * interrupt handling.
157 *
158 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 159 * The default (0) means to assign an interrupt to each core.
8ceee660
BH		 160 */
161static unsigned int rss_cpus;
162module_param(rss_cpus, uint, 0444);
163MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
164
b9cc977d
BH		 165static bool phy_flash_cfg;
166module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH		 167MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
168
e7bed9c8 169static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH		 170module_param(irq_adapt_low_thresh, uint, 0644);
171MODULE_PARM_DESC(irq_adapt_low_thresh,
172 "Threshold score for reducing IRQ moderation");
173
e7bed9c8 174static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH		 175module_param(irq_adapt_high_thresh, uint, 0644);
176MODULE_PARM_DESC(irq_adapt_high_thresh,
177 "Threshold score for increasing IRQ moderation");
178
62776d03
BH		 179static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
180 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
181 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
182 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
183module_param(debug, uint, 0);
184MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
185
8ceee660
BH		 186/**************************************************************************
187 *
188 * Utility functions and prototypes
189 *
190 *************************************************************************/
4642610c 191
261e4d96 192static int efx_soft_enable_interrupts(struct efx_nic *efx);
d8291187 193static void efx_soft_disable_interrupts(struct efx_nic *efx);
7f967c01 194static void efx_remove_channel(struct efx_channel *channel);
4642610c 195static void efx_remove_channels(struct efx_nic *efx);
7f967c01 196static const struct efx_channel_type efx_default_channel_type;
8ceee660 197static void efx_remove_port(struct efx_nic *efx);
7f967c01 198static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 199static void efx_fini_napi(struct efx_nic *efx);
e8f14992 200static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH		 201static void efx_fini_struct(struct efx_nic *efx);
202static void efx_start_all(struct efx_nic *efx);
203static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH		 204
205#define EFX_ASSERT_RESET_SERIALISED(efx) \
206 do { \
f16aeea0 207 if ((efx->state == STATE_READY) || \
626950db 208 (efx->state == STATE_RECOVERY) || \
332c1ce9 209 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 210 ASSERT_RTNL(); \
211 } while (0)
212
8b7325b4
BH		 213static int efx_check_disabled(struct efx_nic *efx)
214{
626950db 215 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
8b7325b4
BH		 216 netif_err(efx, drv, efx->net_dev,
217 "device is disabled due to earlier errors\n");
218 return -EIO;
219 }
220 return 0;
221}
222
8ceee660
BH		 223/**************************************************************************
224 *
225 * Event queue processing
226 *
227 *************************************************************************/
228
229/* Process channel's event queue
230 *
231 * This function is responsible for processing the event queue of a
232 * single channel. The caller must guarantee that this function will
233 * never be concurrently called more than once on the same channel,
234 * though different channels may be being processed concurrently.
235 */
fa236e18 236static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 237{
fa236e18 238 int spent;
8ceee660 239
9f2cb71c 240 if (unlikely(!channel->enabled))
42cbe2d7 241 return 0;
8ceee660 242
fa236e18 243 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH		 244 if (spent && efx_channel_has_rx_queue(channel)) {
245 struct efx_rx_queue *rx_queue =
246 efx_channel_get_rx_queue(channel);
247
ff734ef4 248 efx_rx_flush_packet(channel);
d8aec745 249 efx_fast_push_rx_descriptors(rx_queue);
8ceee660
BH		 250 }
251
fa236e18 252 return spent;
8ceee660
BH		 253}
254
8ceee660
BH		 255/* NAPI poll handler
256 *
257 * NAPI guarantees serialisation of polls of the same device, which
258 * provides the guarantee required by efx_process_channel().
259 */
260static int efx_poll(struct napi_struct *napi, int budget)
261{
262 struct efx_channel *channel =
263 container_of(napi, struct efx_channel, napi_str);
62776d03 264 struct efx_nic *efx = channel->efx;
fa236e18 265 int spent;
8ceee660 266
62776d03
BH		 267 netif_vdbg(efx, intr, efx->net_dev,
268 "channel %d NAPI poll executing on CPU %d\n",
269 channel->channel, raw_smp_processor_id());
8ceee660 270
fa236e18 271 spent = efx_process_channel(channel, budget);
8ceee660 272
fa236e18 273 if (spent < budget) {
9d9a6973 274 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH		 275 efx->irq_rx_adaptive &&
276 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH		 277 if (unlikely(channel->irq_mod_score <
278 irq_adapt_low_thresh)) {
0d86ebd8
BH		 279 if (channel->irq_moderation > 1) {
280 channel->irq_moderation -= 1;
ef2b90ee 281 efx->type->push_irq_moderation(channel);
0d86ebd8 282 }
6fb70fd1
BH		 283 } else if (unlikely(channel->irq_mod_score >
284 irq_adapt_high_thresh)) {
0d86ebd8
BH		 285 if (channel->irq_moderation <
286 efx->irq_rx_moderation) {
287 channel->irq_moderation += 1;
ef2b90ee 288 efx->type->push_irq_moderation(channel);
0d86ebd8 289 }
6fb70fd1 290 }
6fb70fd1
BH		 291 channel->irq_count = 0;
292 channel->irq_mod_score = 0;
293 }
294
64d8ad6d
BH		 295 efx_filter_rfs_expire(channel);
296
8ceee660 297 /* There is no race here; although napi_disable() will
288379f0 298 * only wait for napi_complete(), this isn't a problem
514bedbc 299 * since efx_nic_eventq_read_ack() will have no effect if
8ceee660
BH		 300 * interrupts have already been disabled.
301 */
288379f0 302 napi_complete(napi);
514bedbc 303 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 304 }
305
fa236e18 306 return spent;
8ceee660
BH		 307}
308
8ceee660
BH		 309/* Create event queue
310 * Event queue memory allocations are done only once. If the channel
311 * is reset, the memory buffer will be reused; this guards against
312 * errors during channel reset and also simplifies interrupt handling.
313 */
314static int efx_probe_eventq(struct efx_channel *channel)
315{
ecc910f5
SH		 316 struct efx_nic *efx = channel->efx;
317 unsigned long entries;
318
86ee5302 319 netif_dbg(efx, probe, efx->net_dev,
62776d03 320 "chan %d create event queue\n", channel->channel);
8ceee660 321
ecc910f5
SH		 322 /* Build an event queue with room for one event per tx and rx buffer,
323 * plus some extra for link state events and MCDI completions. */
324 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
325 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
326 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
327
152b6a62 328 return efx_nic_probe_eventq(channel);
8ceee660
BH		 329}
330
331/* Prepare channel's event queue */
261e4d96 332static int efx_init_eventq(struct efx_channel *channel)
8ceee660 333{
15acb1ce 334 struct efx_nic *efx = channel->efx;
261e4d96
JC		 335 int rc;
336
337 EFX_WARN_ON_PARANOID(channel->eventq_init);
338
15acb1ce 339 netif_dbg(efx, drv, efx->net_dev,
62776d03 340 "chan %d init event queue\n", channel->channel);
8ceee660 341
261e4d96
JC		 342 rc = efx_nic_init_eventq(channel);
343 if (rc == 0) {
15acb1ce 344 efx->type->push_irq_moderation(channel);
261e4d96
JC		 345 channel->eventq_read_ptr = 0;
346 channel->eventq_init = true;
347 }
348 return rc;
8ceee660
BH		 349}
350
9f2cb71c
BH		 351/* Enable event queue processing and NAPI */
352static void efx_start_eventq(struct efx_channel *channel)
353{
354 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
355 "chan %d start event queue\n", channel->channel);
356
514bedbc 357 /* Make sure the NAPI handler sees the enabled flag set */
9f2cb71c
BH		 358 channel->enabled = true;
359 smp_wmb();
360
361 napi_enable(&channel->napi_str);
362 efx_nic_eventq_read_ack(channel);
363}
364
365/* Disable event queue processing and NAPI */
366static void efx_stop_eventq(struct efx_channel *channel)
367{
368 if (!channel->enabled)
369 return;
370
371 napi_disable(&channel->napi_str);
372 channel->enabled = false;
373}
374
8ceee660
BH		 375static void efx_fini_eventq(struct efx_channel *channel)
376{
be3fc09c
BH		 377 if (!channel->eventq_init)
378 return;
379
62776d03
BH		 380 netif_dbg(channel->efx, drv, channel->efx->net_dev,
381 "chan %d fini event queue\n", channel->channel);
8ceee660 382
152b6a62 383 efx_nic_fini_eventq(channel);
be3fc09c 384 channel->eventq_init = false;
8ceee660
BH		 385}
386
387static void efx_remove_eventq(struct efx_channel *channel)
388{
62776d03
BH		 389 netif_dbg(channel->efx, drv, channel->efx->net_dev,
390 "chan %d remove event queue\n", channel->channel);
8ceee660 391
152b6a62 392 efx_nic_remove_eventq(channel);
8ceee660
BH		 393}
394
395/**************************************************************************
396 *
397 * Channel handling
398 *
399 *************************************************************************/
400
7f967c01 401/* Allocate and initialise a channel structure. */
4642610c
BH		 402static struct efx_channel *
403efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
404{
405 struct efx_channel *channel;
406 struct efx_rx_queue *rx_queue;
407 struct efx_tx_queue *tx_queue;
408 int j;
409
7f967c01
BH		 410 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
411 if (!channel)
412 return NULL;
4642610c 413
7f967c01
BH		 414 channel->efx = efx;
415 channel->channel = i;
416 channel->type = &efx_default_channel_type;
4642610c 417
7f967c01
BH		 418 for (j = 0; j < EFX_TXQ_TYPES; j++) {
419 tx_queue = &channel->tx_queue[j];
420 tx_queue->efx = efx;
421 tx_queue->queue = i * EFX_TXQ_TYPES + j;
422 tx_queue->channel = channel;
423 }
4642610c 424
7f967c01
BH		 425 rx_queue = &channel->rx_queue;
426 rx_queue->efx = efx;
427 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
428 (unsigned long)rx_queue);
4642610c 429
7f967c01
BH		 430 return channel;
431}
432
433/* Allocate and initialise a channel structure, copying parameters
434 * (but not resources) from an old channel structure.
435 */
436static struct efx_channel *
437efx_copy_channel(const struct efx_channel *old_channel)
438{
439 struct efx_channel *channel;
440 struct efx_rx_queue *rx_queue;
441 struct efx_tx_queue *tx_queue;
442 int j;
4642610c 443
7f967c01
BH		 444 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
445 if (!channel)
446 return NULL;
447
448 *channel = *old_channel;
449
450 channel->napi_dev = NULL;
451 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 452
7f967c01
BH		 453 for (j = 0; j < EFX_TXQ_TYPES; j++) {
454 tx_queue = &channel->tx_queue[j];
455 if (tx_queue->channel)
4642610c 456 tx_queue->channel = channel;
7f967c01
BH		 457 tx_queue->buffer = NULL;
458 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH		 459 }
460
4642610c 461 rx_queue = &channel->rx_queue;
7f967c01
BH		 462 rx_queue->buffer = NULL;
463 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH		 464 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
465 (unsigned long)rx_queue);
466
467 return channel;
468}
469
8ceee660
BH		 470static int efx_probe_channel(struct efx_channel *channel)
471{
472 struct efx_tx_queue *tx_queue;
473 struct efx_rx_queue *rx_queue;
474 int rc;
475
62776d03
BH		 476 netif_dbg(channel->efx, probe, channel->efx->net_dev,
477 "creating channel %d\n", channel->channel);
8ceee660 478
7f967c01
BH		 479 rc = channel->type->pre_probe(channel);
480 if (rc)
481 goto fail;
482
8ceee660
BH		 483 rc = efx_probe_eventq(channel);
484 if (rc)
7f967c01 485 goto fail;
8ceee660
BH		 486
487 efx_for_each_channel_tx_queue(tx_queue, channel) {
488 rc = efx_probe_tx_queue(tx_queue);
489 if (rc)
7f967c01 490 goto fail;
8ceee660
BH		 491 }
492
493 efx_for_each_channel_rx_queue(rx_queue, channel) {
494 rc = efx_probe_rx_queue(rx_queue);
495 if (rc)
7f967c01 496 goto fail;
8ceee660
BH		 497 }
498
499 channel->n_rx_frm_trunc = 0;
500
501 return 0;
502
7f967c01
BH		 503fail:
504 efx_remove_channel(channel);
8ceee660
BH		 505 return rc;
506}
507
7f967c01
BH		 508static void
509efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
510{
511 struct efx_nic *efx = channel->efx;
512 const char *type;
513 int number;
514
515 number = channel->channel;
516 if (efx->tx_channel_offset == 0) {
517 type = "";
518 } else if (channel->channel < efx->tx_channel_offset) {
519 type = "-rx";
520 } else {
521 type = "-tx";
522 number -= efx->tx_channel_offset;
523 }
524 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
525}
8ceee660 526
56536e9c
BH		 527static void efx_set_channel_names(struct efx_nic *efx)
528{
529 struct efx_channel *channel;
56536e9c 530
7f967c01
BH		 531 efx_for_each_channel(channel, efx)
532 channel->type->get_name(channel,
d8291187
BH		 533 efx->msi_context[channel->channel].name,
534 sizeof(efx->msi_context[0].name));
56536e9c
BH		 535}
536
4642610c
BH		 537static int efx_probe_channels(struct efx_nic *efx)
538{
539 struct efx_channel *channel;
540 int rc;
541
542 /* Restart special buffer allocation */
543 efx->next_buffer_table = 0;
544
c92aaff1
BH		 545 /* Probe channels in reverse, so that any 'extra' channels
546 * use the start of the buffer table. This allows the traffic
547 * channels to be resized without moving them or wasting the
548 * entries before them.
549 */
550 efx_for_each_channel_rev(channel, efx) {
4642610c
BH		 551 rc = efx_probe_channel(channel);
552 if (rc) {
553 netif_err(efx, probe, efx->net_dev,
554 "failed to create channel %d\n",
555 channel->channel);
556 goto fail;
557 }
558 }
559 efx_set_channel_names(efx);
560
561 return 0;
562
563fail:
564 efx_remove_channels(efx);
565 return rc;
566}
567
8ceee660
BH		 568/* Channels are shutdown and reinitialised whilst the NIC is running
569 * to propagate configuration changes (mtu, checksum offload), or
570 * to clear hardware error conditions
571 */
9f2cb71c 572static void efx_start_datapath(struct efx_nic *efx)
8ceee660 573{
85740cdf 574 bool old_rx_scatter = efx->rx_scatter;
8ceee660
BH		 575 struct efx_tx_queue *tx_queue;
576 struct efx_rx_queue *rx_queue;
577 struct efx_channel *channel;
85740cdf 578 size_t rx_buf_len;
8ceee660 579
f7f13b0b
BH		 580 /* Calculate the rx buffer allocation parameters required to
581 * support the current MTU, including padding for header
582 * alignment and overruns.
583 */
43a3739d 584 efx->rx_dma_len = (efx->rx_prefix_size +
272baeeb
BH		 585 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
586 efx->type->rx_buffer_padding);
85740cdf 587 rx_buf_len = (sizeof(struct efx_rx_page_state) +
c14ff2ea 588 NET_IP_ALIGN + efx->rx_dma_len);
85740cdf 589 if (rx_buf_len <= PAGE_SIZE) {
e8c68c0a 590 efx->rx_scatter = efx->type->always_rx_scatter;
85740cdf 591 efx->rx_buffer_order = 0;
85740cdf 592 } else if (efx->type->can_rx_scatter) {
950c54df 593 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
85740cdf 594 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
950c54df
BH		 595 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
596 EFX_RX_BUF_ALIGNMENT) >
597 PAGE_SIZE);
85740cdf
BH		 598 efx->rx_scatter = true;
599 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
600 efx->rx_buffer_order = 0;
85740cdf
BH		 601 } else {
602 efx->rx_scatter = false;
603 efx->rx_buffer_order = get_order(rx_buf_len);
85740cdf
BH		 604 }
605
1648a23f
DP		 606 efx_rx_config_page_split(efx);
607 if (efx->rx_buffer_order)
608 netif_dbg(efx, drv, efx->net_dev,
609 "RX buf len=%u; page order=%u batch=%u\n",
610 efx->rx_dma_len, efx->rx_buffer_order,
611 efx->rx_pages_per_batch);
612 else
613 netif_dbg(efx, drv, efx->net_dev,
614 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
615 efx->rx_dma_len, efx->rx_page_buf_step,
616 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
2768935a 617
e8c68c0a 618 /* RX filters may also have scatter-enabled flags */
85740cdf 619 if (efx->rx_scatter != old_rx_scatter)
add72477 620 efx->type->filter_update_rx_scatter(efx);
8ceee660 621
14bf718f
BH		 622 /* We must keep at least one descriptor in a TX ring empty.
623 * We could avoid this when the queue size does not exactly
624 * match the hardware ring size, but it's not that important.
625 * Therefore we stop the queue when one more skb might fill
626 * the ring completely. We wake it when half way back to
627 * empty.
628 */
629 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
630 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
631
8ceee660
BH		 632 /* Initialise the channels */
633 efx_for_each_channel(channel, efx) {
3881d8ab 634 efx_for_each_channel_tx_queue(tx_queue, channel) {
bc3c90a2 635 efx_init_tx_queue(tx_queue);
3881d8ab
AR		 636 atomic_inc(&efx->active_queues);
637 }
8ceee660 638
9f2cb71c 639 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 640 efx_init_rx_queue(rx_queue);
3881d8ab 641 atomic_inc(&efx->active_queues);
9f2cb71c
BH		 642 efx_nic_generate_fill_event(rx_queue);
643 }
8ceee660 644
85740cdf 645 WARN_ON(channel->rx_pkt_n_frags);
8ceee660 646 }
8ceee660 647
9f2cb71c
BH		 648 if (netif_device_present(efx->net_dev))
649 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH		 650}
651
9f2cb71c 652static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH		 653{
654 struct efx_channel *channel;
655 struct efx_tx_queue *tx_queue;
656 struct efx_rx_queue *rx_queue;
6bc5d3a9 657 int rc;
8ceee660
BH		 658
659 EFX_ASSERT_RESET_SERIALISED(efx);
660 BUG_ON(efx->port_enabled);
661
d8aec745
BH		 662 /* Stop RX refill */
663 efx_for_each_channel(channel, efx) {
664 efx_for_each_channel_rx_queue(rx_queue, channel)
665 rx_queue->refill_enabled = false;
666 }
667
8ceee660 668 efx_for_each_channel(channel, efx) {
9f2cb71c
BH		 669 /* RX packet processing is pipelined, so wait for the
670 * NAPI handler to complete. At least event queue 0
671 * might be kept active by non-data events, so don't
672 * use napi_synchronize() but actually disable NAPI
673 * temporarily.
674 */
675 if (efx_channel_has_rx_queue(channel)) {
676 efx_stop_eventq(channel);
677 efx_start_eventq(channel);
678 }
e42c3d85 679 }
8ceee660 680
e42c3d85
BH		 681 rc = efx->type->fini_dmaq(efx);
682 if (rc && EFX_WORKAROUND_7803(efx)) {
683 /* Schedule a reset to recover from the flush failure. The
684 * descriptor caches reference memory we're about to free,
685 * but falcon_reconfigure_mac_wrapper() won't reconnect
686 * the MACs because of the pending reset.
687 */
688 netif_err(efx, drv, efx->net_dev,
689 "Resetting to recover from flush failure\n");
690 efx_schedule_reset(efx, RESET_TYPE_ALL);
691 } else if (rc) {
692 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
693 } else {
694 netif_dbg(efx, drv, efx->net_dev,
695 "successfully flushed all queues\n");
696 }
697
698 efx_for_each_channel(channel, efx) {
8ceee660
BH		 699 efx_for_each_channel_rx_queue(rx_queue, channel)
700 efx_fini_rx_queue(rx_queue);
94b274bf 701 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 702 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 703 }
704}
705
706static void efx_remove_channel(struct efx_channel *channel)
707{
708 struct efx_tx_queue *tx_queue;
709 struct efx_rx_queue *rx_queue;
710
62776d03
BH		 711 netif_dbg(channel->efx, drv, channel->efx->net_dev,
712 "destroy chan %d\n", channel->channel);
8ceee660
BH		 713
714 efx_for_each_channel_rx_queue(rx_queue, channel)
715 efx_remove_rx_queue(rx_queue);
94b274bf 716 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH		 717 efx_remove_tx_queue(tx_queue);
718 efx_remove_eventq(channel);
c31e5f9f 719 channel->type->post_remove(channel);
8ceee660
BH		 720}
721
4642610c
BH		 722static void efx_remove_channels(struct efx_nic *efx)
723{
724 struct efx_channel *channel;
725
726 efx_for_each_channel(channel, efx)
727 efx_remove_channel(channel);
728}
729
730int
731efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
732{
733 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
734 u32 old_rxq_entries, old_txq_entries;
7f967c01 735 unsigned i, next_buffer_table = 0;
261e4d96 736 int rc, rc2;
8b7325b4
BH		 737
738 rc = efx_check_disabled(efx);
739 if (rc)
740 return rc;
7f967c01
BH		 741
742 /* Not all channels should be reallocated. We must avoid
743 * reallocating their buffer table entries.
744 */
745 efx_for_each_channel(channel, efx) {
746 struct efx_rx_queue *rx_queue;
747 struct efx_tx_queue *tx_queue;
748
749 if (channel->type->copy)
750 continue;
751 next_buffer_table = max(next_buffer_table,
752 channel->eventq.index +
753 channel->eventq.entries);
754 efx_for_each_channel_rx_queue(rx_queue, channel)
755 next_buffer_table = max(next_buffer_table,
756 rx_queue->rxd.index +
757 rx_queue->rxd.entries);
758 efx_for_each_channel_tx_queue(tx_queue, channel)
759 next_buffer_table = max(next_buffer_table,
760 tx_queue->txd.index +
761 tx_queue->txd.entries);
762 }
4642610c 763
29c69a48 764 efx_device_detach_sync(efx);
4642610c 765 efx_stop_all(efx);
d8291187 766 efx_soft_disable_interrupts(efx);
4642610c 767
7f967c01 768 /* Clone channels (where possible) */
4642610c
BH		 769 memset(other_channel, 0, sizeof(other_channel));
770 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 771 channel = efx->channel[i];
772 if (channel->type->copy)
773 channel = channel->type->copy(channel);
4642610c
BH		 774 if (!channel) {
775 rc = -ENOMEM;
776 goto out;
777 }
778 other_channel[i] = channel;
779 }
780
781 /* Swap entry counts and channel pointers */
782 old_rxq_entries = efx->rxq_entries;
783 old_txq_entries = efx->txq_entries;
784 efx->rxq_entries = rxq_entries;
785 efx->txq_entries = txq_entries;
786 for (i = 0; i < efx->n_channels; i++) {
787 channel = efx->channel[i];
788 efx->channel[i] = other_channel[i];
789 other_channel[i] = channel;
790 }
791
7f967c01
BH		 792 /* Restart buffer table allocation */
793 efx->next_buffer_table = next_buffer_table;
e8f14992 794
e8f14992 795 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 796 channel = efx->channel[i];
797 if (!channel->type->copy)
798 continue;
799 rc = efx_probe_channel(channel);
800 if (rc)
801 goto rollback;
802 efx_init_napi_channel(efx->channel[i]);
e8f14992 803 }
7f967c01 804
4642610c 805out:
7f967c01
BH		 806 /* Destroy unused channel structures */
807 for (i = 0; i < efx->n_channels; i++) {
808 channel = other_channel[i];
809 if (channel && channel->type->copy) {
810 efx_fini_napi_channel(channel);
811 efx_remove_channel(channel);
812 kfree(channel);
813 }
814 }
4642610c 815
261e4d96
JC		 816 rc2 = efx_soft_enable_interrupts(efx);
817 if (rc2) {
818 rc = rc ? rc : rc2;
819 netif_err(efx, drv, efx->net_dev,
820 "unable to restart interrupts on channel reallocation\n");
821 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
822 } else {
823 efx_start_all(efx);
824 netif_device_attach(efx->net_dev);
825 }
4642610c
BH		 826 return rc;
827
828rollback:
829 /* Swap back */
830 efx->rxq_entries = old_rxq_entries;
831 efx->txq_entries = old_txq_entries;
832 for (i = 0; i < efx->n_channels; i++) {
833 channel = efx->channel[i];
834 efx->channel[i] = other_channel[i];
835 other_channel[i] = channel;
836 }
837 goto out;
838}
839
90d683af 840void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 841{
90d683af 842 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH		 843}
844
7f967c01
BH		 845static const struct efx_channel_type efx_default_channel_type = {
846 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 847 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH		 848 .get_name = efx_get_channel_name,
849 .copy = efx_copy_channel,
850 .keep_eventq = false,
851};
852
853int efx_channel_dummy_op_int(struct efx_channel *channel)
854{
855 return 0;
856}
857
c31e5f9f
SH		 858void efx_channel_dummy_op_void(struct efx_channel *channel)
859{
860}
861
8ceee660
BH		 862/**************************************************************************
863 *
864 * Port handling
865 *
866 **************************************************************************/
867
868/* This ensures that the kernel is kept informed (via
869 * netif_carrier_on/off) of the link status, and also maintains the
870 * link status's stop on the port's TX queue.
871 */
fdaa9aed 872void efx_link_status_changed(struct efx_nic *efx)
8ceee660 873{
eb50c0d6
BH		 874 struct efx_link_state *link_state = &efx->link_state;
875
8ceee660
BH		 876 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
877 * that no events are triggered between unregister_netdev() and the
878 * driver unloading. A more general condition is that NETDEV_CHANGE
879 * can only be generated between NETDEV_UP and NETDEV_DOWN */
880 if (!netif_running(efx->net_dev))
881 return;
882
eb50c0d6 883 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 884 efx->n_link_state_changes++;
885
eb50c0d6 886 if (link_state->up)
8ceee660
BH		 887 netif_carrier_on(efx->net_dev);
888 else
889 netif_carrier_off(efx->net_dev);
890 }
891
892 /* Status message for kernel log */
2aa9ef11 893 if (link_state->up)
62776d03 894 netif_info(efx, link, efx->net_dev,
964e6135 895 "link up at %uMbps %s-duplex (MTU %d)\n",
62776d03 896 link_state->speed, link_state->fd ? "full" : "half",
964e6135 897 efx->net_dev->mtu);
2aa9ef11 898 else
62776d03 899 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH		 900}
901
d3245b28
BH		 902void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
903{
904 efx->link_advertising = advertising;
905 if (advertising) {
906 if (advertising & ADVERTISED_Pause)
907 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
908 else
909 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
910 if (advertising & ADVERTISED_Asym_Pause)
911 efx->wanted_fc ^= EFX_FC_TX;
912 }
913}
914
b5626946 915void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH		 916{
917 efx->wanted_fc = wanted_fc;
918 if (efx->link_advertising) {
919 if (wanted_fc & EFX_FC_RX)
920 efx->link_advertising |= (ADVERTISED_Pause |
921 ADVERTISED_Asym_Pause);
922 else
923 efx->link_advertising &= ~(ADVERTISED_Pause |
924 ADVERTISED_Asym_Pause);
925 if (wanted_fc & EFX_FC_TX)
926 efx->link_advertising ^= ADVERTISED_Asym_Pause;
927 }
928}
929
115122af
BH		 930static void efx_fini_port(struct efx_nic *efx);
931
d3245b28
BH		 932/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
933 * the MAC appropriately. All other PHY configuration changes are pushed
934 * through phy_op->set_settings(), and pushed asynchronously to the MAC
935 * through efx_monitor().
936 *
937 * Callers must hold the mac_lock
938 */
939int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 940{
d3245b28
BH		 941 enum efx_phy_mode phy_mode;
942 int rc;
8ceee660 943
d3245b28 944 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 945
d3245b28
BH		 946 /* Disable PHY transmit in mac level loopbacks */
947 phy_mode = efx->phy_mode;
177dfcd8
BH		 948 if (LOOPBACK_INTERNAL(efx))
949 efx->phy_mode |= PHY_MODE_TX_DISABLED;
950 else
951 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 952
d3245b28 953 rc = efx->type->reconfigure_port(efx);
8ceee660 954
d3245b28
BH		 955 if (rc)
956 efx->phy_mode = phy_mode;
177dfcd8 957
d3245b28 958 return rc;
8ceee660
BH		 959}
960
961/* Reinitialise the MAC to pick up new PHY settings, even if the port is
962 * disabled. */
d3245b28 963int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 964{
d3245b28
BH		 965 int rc;
966
8ceee660
BH		 967 EFX_ASSERT_RESET_SERIALISED(efx);
968
969 mutex_lock(&efx->mac_lock);
d3245b28 970 rc = __efx_reconfigure_port(efx);
8ceee660 971 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 972
973 return rc;
8ceee660
BH		 974}
975
8be4f3e6
BH		 976/* Asynchronous work item for changing MAC promiscuity and multicast
977 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
978 * MAC directly. */
766ca0fa
BH		 979static void efx_mac_work(struct work_struct *data)
980{
981 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
982
983 mutex_lock(&efx->mac_lock);
30b81cda 984 if (efx->port_enabled)
710b208d 985 efx->type->reconfigure_mac(efx);
766ca0fa
BH		 986 mutex_unlock(&efx->mac_lock);
987}
988
8ceee660
BH		 989static int efx_probe_port(struct efx_nic *efx)
990{
991 int rc;
992
62776d03 993 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 994
ff3b00a0
SH		 995 if (phy_flash_cfg)
996 efx->phy_mode = PHY_MODE_SPECIAL;
997
ef2b90ee
BH		 998 /* Connect up MAC/PHY operations table */
999 rc = efx->type->probe_port(efx);
8ceee660 1000 if (rc)
e42de262 1001 return rc;
8ceee660 1002
e332bcb3
BH		 1003 /* Initialise MAC address to permanent address */
1004 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN);
8ceee660
BH		 1005
1006 return 0;
8ceee660
BH		 1007}
1008
1009static int efx_init_port(struct efx_nic *efx)
1010{
1011 int rc;
1012
62776d03 1013 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 1014
1dfc5cea
BH		 1015 mutex_lock(&efx->mac_lock);
1016
177dfcd8 1017 rc = efx->phy_op->init(efx);
8ceee660 1018 if (rc)
1dfc5cea 1019 goto fail1;
8ceee660 1020
dc8cfa55 1021 efx->port_initialized = true;
1dfc5cea 1022
d3245b28
BH		 1023 /* Reconfigure the MAC before creating dma queues (required for
1024 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
710b208d 1025 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1026
1027 /* Ensure the PHY advertises the correct flow control settings */
1028 rc = efx->phy_op->reconfigure(efx);
1029 if (rc)
1030 goto fail2;
1031
1dfc5cea 1032 mutex_unlock(&efx->mac_lock);
8ceee660 1033 return 0;
177dfcd8 1034
1dfc5cea 1035fail2:
177dfcd8 1036 efx->phy_op->fini(efx);
1dfc5cea
BH		 1037fail1:
1038 mutex_unlock(&efx->mac_lock);
177dfcd8 1039 return rc;
8ceee660
BH		 1040}
1041
8ceee660
BH		 1042static void efx_start_port(struct efx_nic *efx)
1043{
62776d03 1044 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH		 1045 BUG_ON(efx->port_enabled);
1046
1047 mutex_lock(&efx->mac_lock);
dc8cfa55 1048 efx->port_enabled = true;
8be4f3e6
BH		 1049
1050 /* efx_mac_work() might have been scheduled after efx_stop_port(),
1051 * and then cancelled by efx_flush_all() */
710b208d 1052 efx->type->reconfigure_mac(efx);
8be4f3e6 1053
8ceee660
BH		 1054 mutex_unlock(&efx->mac_lock);
1055}
1056
fdaa9aed 1057/* Prevent efx_mac_work() and efx_monitor() from working */
8ceee660
BH		 1058static void efx_stop_port(struct efx_nic *efx)
1059{
62776d03 1060 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660
BH		 1061
1062 mutex_lock(&efx->mac_lock);
dc8cfa55 1063 efx->port_enabled = false;
8ceee660
BH		 1064 mutex_unlock(&efx->mac_lock);
1065
1066 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH		 1067 netif_addr_lock_bh(efx->net_dev);
1068 netif_addr_unlock_bh(efx->net_dev);
8ceee660
BH		 1069}
1070
1071static void efx_fini_port(struct efx_nic *efx)
1072{
62776d03 1073 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH		 1074
1075 if (!efx->port_initialized)
1076 return;
1077
177dfcd8 1078 efx->phy_op->fini(efx);
dc8cfa55 1079 efx->port_initialized = false;
8ceee660 1080
eb50c0d6 1081 efx->link_state.up = false;
8ceee660
BH		 1082 efx_link_status_changed(efx);
1083}
1084
1085static void efx_remove_port(struct efx_nic *efx)
1086{
62776d03 1087 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1088
ef2b90ee 1089 efx->type->remove_port(efx);
8ceee660
BH		 1090}
1091
1092/**************************************************************************
1093 *
1094 * NIC handling
1095 *
1096 **************************************************************************/
1097
1098/* This configures the PCI device to enable I/O and DMA. */
1099static int efx_init_io(struct efx_nic *efx)
1100{
1101 struct pci_dev *pci_dev = efx->pci_dev;
1102 dma_addr_t dma_mask = efx->type->max_dma_mask;
b105798f 1103 unsigned int mem_map_size = efx->type->mem_map_size(efx);
8ceee660
BH		 1104 int rc;
1105
62776d03 1106 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660
BH		 1107
1108 rc = pci_enable_device(pci_dev);
1109 if (rc) {
62776d03
BH		 1110 netif_err(efx, probe, efx->net_dev,
1111 "failed to enable PCI device\n");
8ceee660
BH		 1112 goto fail1;
1113 }
1114
1115 pci_set_master(pci_dev);
1116
1117 /* Set the PCI DMA mask. Try all possibilities from our
1118 * genuine mask down to 32 bits, because some architectures
1119 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1120 * masks event though they reject 46 bit masks.
1121 */
1122 while (dma_mask > 0x7fffffffUL) {
0e33d870
BH		 1123 if (dma_supported(&pci_dev->dev, dma_mask)) {
1124 rc = dma_set_mask(&pci_dev->dev, dma_mask);
e9e01846
BH		 1125 if (rc == 0)
1126 break;
1127 }
8ceee660
BH		 1128 dma_mask >>= 1;
1129 }
1130 if (rc) {
62776d03
BH		 1131 netif_err(efx, probe, efx->net_dev,
1132 "could not find a suitable DMA mask\n");
8ceee660
BH		 1133 goto fail2;
1134 }
62776d03
BH		 1135 netif_dbg(efx, probe, efx->net_dev,
1136 "using DMA mask %llx\n", (unsigned long long) dma_mask);
0e33d870 1137 rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask);
8ceee660 1138 if (rc) {
0e33d870
BH		 1139 /* dma_set_coherent_mask() is not *allowed* to
1140 * fail with a mask that dma_set_mask() accepted,
8ceee660
BH		 1141 * but just in case...
1142 */
62776d03
BH		 1143 netif_err(efx, probe, efx->net_dev,
1144 "failed to set consistent DMA mask\n");
8ceee660
BH		 1145 goto fail2;
1146 }
1147
dc803df8
BH		 1148 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1149 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
8ceee660 1150 if (rc) {
62776d03
BH		 1151 netif_err(efx, probe, efx->net_dev,
1152 "request for memory BAR failed\n");
8ceee660
BH		 1153 rc = -EIO;
1154 goto fail3;
1155 }
b105798f 1156 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
8ceee660 1157 if (!efx->membase) {
62776d03
BH		 1158 netif_err(efx, probe, efx->net_dev,
1159 "could not map memory BAR at %llx+%x\n",
b105798f 1160 (unsigned long long)efx->membase_phys, mem_map_size);
8ceee660
BH		 1161 rc = -ENOMEM;
1162 goto fail4;
1163 }
62776d03
BH		 1164 netif_dbg(efx, probe, efx->net_dev,
1165 "memory BAR at %llx+%x (virtual %p)\n",
b105798f
BH		 1166 (unsigned long long)efx->membase_phys, mem_map_size,
1167 efx->membase);
8ceee660
BH		 1168
1169 return 0;
1170
1171 fail4:
dc803df8 1172 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
8ceee660 1173 fail3:
2c118e0f 1174 efx->membase_phys = 0;
8ceee660
BH		 1175 fail2:
1176 pci_disable_device(efx->pci_dev);
1177 fail1:
1178 return rc;
1179}
1180
1181static void efx_fini_io(struct efx_nic *efx)
1182{
62776d03 1183 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH		 1184
1185 if (efx->membase) {
1186 iounmap(efx->membase);
1187 efx->membase = NULL;
1188 }
1189
1190 if (efx->membase_phys) {
dc803df8 1191 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
2c118e0f 1192 efx->membase_phys = 0;
8ceee660
BH		 1193 }
1194
1195 pci_disable_device(efx->pci_dev);
1196}
1197
a9a52506 1198static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1199{
cdb08f8f 1200 cpumask_var_t thread_mask;
a16e5b24 1201 unsigned int count;
46123d04 1202 int cpu;
5b874e25 1203
cd2d5b52
BH		 1204 if (rss_cpus) {
1205 count = rss_cpus;
1206 } else {
1207 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1208 netif_warn(efx, probe, efx->net_dev,
1209 "RSS disabled due to allocation failure\n");
1210 return 1;
1211 }
46123d04 1212
cd2d5b52
BH		 1213 count = 0;
1214 for_each_online_cpu(cpu) {
1215 if (!cpumask_test_cpu(cpu, thread_mask)) {
1216 ++count;
1217 cpumask_or(thread_mask, thread_mask,
1218 topology_thread_cpumask(cpu));
1219 }
1220 }
1221
1222 free_cpumask_var(thread_mask);
2f8975fb
RR		 1223 }
1224
cd2d5b52
BH		 1225 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1226 * table entries that are inaccessible to VFs
1227 */
1228 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1229 count > efx_vf_size(efx)) {
1230 netif_warn(efx, probe, efx->net_dev,
1231 "Reducing number of RSS channels from %u to %u for "
1232 "VF support. Increase vf-msix-limit to use more "
1233 "channels on the PF.\n",
1234 count, efx_vf_size(efx));
1235 count = efx_vf_size(efx);
46123d04
BH		 1236 }
1237
1238 return count;
1239}
1240
1241/* Probe the number and type of interrupts we are able to obtain, and
1242 * the resulting numbers of channels and RX queues.
1243 */
64d8ad6d 1244static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1245{
7f967c01
BH		 1246 unsigned int extra_channels = 0;
1247 unsigned int i, j;
a16e5b24 1248 int rc;
8ceee660 1249
7f967c01
BH		 1250 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1251 if (efx->extra_channel_type[i])
1252 ++extra_channels;
1253
8ceee660 1254 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1255 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1256 unsigned int n_channels;
aa6ef27e 1257
a9a52506 1258 n_channels = efx_wanted_parallelism(efx);
a4900ac9
BH		 1259 if (separate_tx_channels)
1260 n_channels *= 2;
7f967c01 1261 n_channels += extra_channels;
b105798f 1262 n_channels = min(n_channels, efx->max_channels);
8ceee660 1263
a4900ac9 1264 for (i = 0; i < n_channels; i++)
8ceee660 1265 xentries[i].entry = i;
a4900ac9 1266 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
8ceee660 1267 if (rc > 0) {
62776d03
BH		 1268 netif_err(efx, drv, efx->net_dev,
1269 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1270 " available (%d < %u).\n", rc, n_channels);
62776d03
BH		 1271 netif_err(efx, drv, efx->net_dev,
1272 "WARNING: Performance may be reduced.\n");
a4900ac9
BH		 1273 EFX_BUG_ON_PARANOID(rc >= n_channels);
1274 n_channels = rc;
8ceee660 1275 rc = pci_enable_msix(efx->pci_dev, xentries,
a4900ac9 1276 n_channels);
8ceee660
BH		 1277 }
1278
1279 if (rc == 0) {
a4900ac9 1280 efx->n_channels = n_channels;
7f967c01
BH		 1281 if (n_channels > extra_channels)
1282 n_channels -= extra_channels;
a4900ac9 1283 if (separate_tx_channels) {
7f967c01
BH		 1284 efx->n_tx_channels = max(n_channels / 2, 1U);
1285 efx->n_rx_channels = max(n_channels -
1286 efx->n_tx_channels,
1287 1U);
a4900ac9 1288 } else {
7f967c01
BH		 1289 efx->n_tx_channels = n_channels;
1290 efx->n_rx_channels = n_channels;
a4900ac9 1291 }
7f967c01 1292 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH		 1293 efx_get_channel(efx, i)->irq =
1294 xentries[i].vector;
8ceee660
BH		 1295 } else {
1296 /* Fall back to single channel MSI */
1297 efx->interrupt_mode = EFX_INT_MODE_MSI;
62776d03
BH		 1298 netif_err(efx, drv, efx->net_dev,
1299 "could not enable MSI-X\n");
8ceee660
BH		 1300 }
1301 }
1302
1303 /* Try single interrupt MSI */
1304 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1305 efx->n_channels = 1;
a4900ac9
BH		 1306 efx->n_rx_channels = 1;
1307 efx->n_tx_channels = 1;
8ceee660
BH		 1308 rc = pci_enable_msi(efx->pci_dev);
1309 if (rc == 0) {
f7d12cdc 1310 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1311 } else {
62776d03
BH		 1312 netif_err(efx, drv, efx->net_dev,
1313 "could not enable MSI\n");
8ceee660
BH		 1314 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1315 }
1316 }
1317
1318 /* Assume legacy interrupts */
1319 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
28b581ab 1320 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
a4900ac9
BH		 1321 efx->n_rx_channels = 1;
1322 efx->n_tx_channels = 1;
8ceee660
BH		 1323 efx->legacy_irq = efx->pci_dev->irq;
1324 }
64d8ad6d 1325
7f967c01
BH		 1326 /* Assign extra channels if possible */
1327 j = efx->n_channels;
1328 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1329 if (!efx->extra_channel_type[i])
1330 continue;
1331 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1332 efx->n_channels <= extra_channels) {
1333 efx->extra_channel_type[i]->handle_no_channel(efx);
1334 } else {
1335 --j;
1336 efx_get_channel(efx, j)->type =
1337 efx->extra_channel_type[i];
1338 }
1339 }
1340
cd2d5b52 1341 /* RSS might be usable on VFs even if it is disabled on the PF */
3132d282 1342 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ?
cd2d5b52
BH		 1343 efx->n_rx_channels : efx_vf_size(efx));
1344
64d8ad6d 1345 return 0;
8ceee660
BH		 1346}
1347
261e4d96 1348static int efx_soft_enable_interrupts(struct efx_nic *efx)
9f2cb71c 1349{
261e4d96
JC		 1350 struct efx_channel *channel, *end_channel;
1351 int rc;
9f2cb71c 1352
8b7325b4
BH		 1353 BUG_ON(efx->state == STATE_DISABLED);
1354
d8291187
BH		 1355 efx->irq_soft_enabled = true;
1356 smp_wmb();
9f2cb71c
BH		 1357
1358 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1359 if (!channel->type->keep_eventq) {
1360 rc = efx_init_eventq(channel);
1361 if (rc)
1362 goto fail;
1363 }
9f2cb71c
BH		 1364 efx_start_eventq(channel);
1365 }
1366
1367 efx_mcdi_mode_event(efx);
261e4d96
JC		 1368
1369 return 0;
1370fail:
1371 end_channel = channel;
1372 efx_for_each_channel(channel, efx) {
1373 if (channel == end_channel)
1374 break;
1375 efx_stop_eventq(channel);
1376 if (!channel->type->keep_eventq)
1377 efx_fini_eventq(channel);
1378 }
1379
1380 return rc;
9f2cb71c
BH		 1381}
1382
d8291187 1383static void efx_soft_disable_interrupts(struct efx_nic *efx)
9f2cb71c
BH		 1384{
1385 struct efx_channel *channel;
1386
8b7325b4
BH		 1387 if (efx->state == STATE_DISABLED)
1388 return;
1389
9f2cb71c
BH		 1390 efx_mcdi_mode_poll(efx);
1391
d8291187
BH		 1392 efx->irq_soft_enabled = false;
1393 smp_wmb();
1394
1395 if (efx->legacy_irq)
9f2cb71c 1396 synchronize_irq(efx->legacy_irq);
9f2cb71c
BH		 1397
1398 efx_for_each_channel(channel, efx) {
1399 if (channel->irq)
1400 synchronize_irq(channel->irq);
1401
1402 efx_stop_eventq(channel);
d8291187 1403 if (!channel->type->keep_eventq)
7f967c01 1404 efx_fini_eventq(channel);
9f2cb71c 1405 }
cade715f
BH		 1406
1407 /* Flush the asynchronous MCDI request queue */
1408 efx_mcdi_flush_async(efx);
9f2cb71c
BH		 1409}
1410
261e4d96 1411static int efx_enable_interrupts(struct efx_nic *efx)
d8291187 1412{
261e4d96
JC		 1413 struct efx_channel *channel, *end_channel;
1414 int rc;
d8291187
BH		 1415
1416 BUG_ON(efx->state == STATE_DISABLED);
1417
1418 if (efx->eeh_disabled_legacy_irq) {
1419 enable_irq(efx->legacy_irq);
1420 efx->eeh_disabled_legacy_irq = false;
1421 }
1422
86094f7f 1423 efx->type->irq_enable_master(efx);
d8291187
BH		 1424
1425 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1426 if (channel->type->keep_eventq) {
1427 rc = efx_init_eventq(channel);
1428 if (rc)
1429 goto fail;
1430 }
1431 }
1432
1433 rc = efx_soft_enable_interrupts(efx);
1434 if (rc)
1435 goto fail;
1436
1437 return 0;
1438
1439fail:
1440 end_channel = channel;
1441 efx_for_each_channel(channel, efx) {
1442 if (channel == end_channel)
1443 break;
d8291187 1444 if (channel->type->keep_eventq)
261e4d96 1445 efx_fini_eventq(channel);
d8291187
BH		 1446 }
1447
261e4d96
JC		 1448 efx->type->irq_disable_non_ev(efx);
1449
1450 return rc;
d8291187
BH		 1451}
1452
1453static void efx_disable_interrupts(struct efx_nic *efx)
1454{
1455 struct efx_channel *channel;
1456
1457 efx_soft_disable_interrupts(efx);
1458
1459 efx_for_each_channel(channel, efx) {
1460 if (channel->type->keep_eventq)
1461 efx_fini_eventq(channel);
1462 }
1463
86094f7f 1464 efx->type->irq_disable_non_ev(efx);
d8291187
BH		 1465}
1466
8ceee660
BH		 1467static void efx_remove_interrupts(struct efx_nic *efx)
1468{
1469 struct efx_channel *channel;
1470
1471 /* Remove MSI/MSI-X interrupts */
64ee3120 1472 efx_for_each_channel(channel, efx)
8ceee660
BH		 1473 channel->irq = 0;
1474 pci_disable_msi(efx->pci_dev);
1475 pci_disable_msix(efx->pci_dev);
1476
1477 /* Remove legacy interrupt */
1478 efx->legacy_irq = 0;
1479}
1480
8831da7b 1481static void efx_set_channels(struct efx_nic *efx)
8ceee660 1482{
602a5322
BH		 1483 struct efx_channel *channel;
1484 struct efx_tx_queue *tx_queue;
1485
97653431 1486 efx->tx_channel_offset =
a4900ac9 1487 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
602a5322 1488
79d68b37
SH		 1489 /* We need to mark which channels really have RX and TX
1490 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH		 1491 * RX-only and TX-only channels.
1492 */
1493 efx_for_each_channel(channel, efx) {
79d68b37
SH		 1494 if (channel->channel < efx->n_rx_channels)
1495 channel->rx_queue.core_index = channel->channel;
1496 else
1497 channel->rx_queue.core_index = -1;
1498
602a5322
BH		 1499 efx_for_each_channel_tx_queue(tx_queue, channel)
1500 tx_queue->queue -= (efx->tx_channel_offset *
1501 EFX_TXQ_TYPES);
1502 }
8ceee660
BH		 1503}
1504
1505static int efx_probe_nic(struct efx_nic *efx)
1506{
765c9f46 1507 size_t i;
8ceee660
BH		 1508 int rc;
1509
62776d03 1510 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH		 1511
1512 /* Carry out hardware-type specific initialisation */
ef2b90ee 1513 rc = efx->type->probe(efx);
8ceee660
BH		 1514 if (rc)
1515 return rc;
1516
a4900ac9 1517 /* Determine the number of channels and queues by trying to hook
8ceee660 1518 * in MSI-X interrupts. */
64d8ad6d
BH		 1519 rc = efx_probe_interrupts(efx);
1520 if (rc)
c15eed22 1521 goto fail1;
8ceee660 1522
c15eed22
BH		 1523 rc = efx->type->dimension_resources(efx);
1524 if (rc)
1525 goto fail2;
28e47c49 1526
5d3a6fca
BH		 1527 if (efx->n_channels > 1)
1528 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
765c9f46 1529 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
278bc429 1530 efx->rx_indir_table[i] =
cd2d5b52 1531 ethtool_rxfh_indir_default(i, efx->rss_spread);
5d3a6fca 1532
8831da7b 1533 efx_set_channels(efx);
c4f4adc7
BH		 1534 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1535 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH		 1536
1537 /* Initialise the interrupt moderation settings */
9e393b30
BH		 1538 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1539 true);
8ceee660
BH		 1540
1541 return 0;
64d8ad6d 1542
c15eed22
BH		 1543fail2:
1544 efx_remove_interrupts(efx);
1545fail1:
64d8ad6d
BH		 1546 efx->type->remove(efx);
1547 return rc;
8ceee660
BH		 1548}
1549
1550static void efx_remove_nic(struct efx_nic *efx)
1551{
62776d03 1552 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH		 1553
1554 efx_remove_interrupts(efx);
ef2b90ee 1555 efx->type->remove(efx);
8ceee660
BH		 1556}
1557
add72477
BH		 1558static int efx_probe_filters(struct efx_nic *efx)
1559{
1560 int rc;
1561
1562 spin_lock_init(&efx->filter_lock);
1563
1564 rc = efx->type->filter_table_probe(efx);
1565 if (rc)
1566 return rc;
1567
1568#ifdef CONFIG_RFS_ACCEL
1569 if (efx->type->offload_features & NETIF_F_NTUPLE) {
1570 efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters,
1571 sizeof(*efx->rps_flow_id),
1572 GFP_KERNEL);
1573 if (!efx->rps_flow_id) {
1574 efx->type->filter_table_remove(efx);
1575 return -ENOMEM;
1576 }
1577 }
1578#endif
1579
1580 return 0;
1581}
1582
1583static void efx_remove_filters(struct efx_nic *efx)
1584{
1585#ifdef CONFIG_RFS_ACCEL
1586 kfree(efx->rps_flow_id);
1587#endif
1588 efx->type->filter_table_remove(efx);
1589}
1590
1591static void efx_restore_filters(struct efx_nic *efx)
1592{
1593 efx->type->filter_table_restore(efx);
1594}
1595
8ceee660
BH		 1596/**************************************************************************
1597 *
1598 * NIC startup/shutdown
1599 *
1600 *************************************************************************/
1601
1602static int efx_probe_all(struct efx_nic *efx)
1603{
8ceee660
BH		 1604 int rc;
1605
8ceee660
BH		 1606 rc = efx_probe_nic(efx);
1607 if (rc) {
62776d03 1608 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH		 1609 goto fail1;
1610 }
1611
8ceee660
BH		 1612 rc = efx_probe_port(efx);
1613 if (rc) {
62776d03 1614 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH		 1615 goto fail2;
1616 }
1617
7e6d06f0
BH		 1618 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1619 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1620 rc = -EINVAL;
1621 goto fail3;
1622 }
ecc910f5 1623 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1624
64eebcfd
BH		 1625 rc = efx_probe_filters(efx);
1626 if (rc) {
1627 netif_err(efx, probe, efx->net_dev,
1628 "failed to create filter tables\n");
7f967c01 1629 goto fail3;
64eebcfd
BH		 1630 }
1631
7f967c01
BH		 1632 rc = efx_probe_channels(efx);
1633 if (rc)
1634 goto fail4;
1635
8ceee660
BH		 1636 return 0;
1637
64eebcfd 1638 fail4:
7f967c01 1639 efx_remove_filters(efx);
8ceee660 1640 fail3:
8ceee660
BH		 1641 efx_remove_port(efx);
1642 fail2:
1643 efx_remove_nic(efx);
1644 fail1:
1645 return rc;
1646}
1647
8b7325b4
BH		 1648/* If the interface is supposed to be running but is not, start
1649 * the hardware and software data path, regular activity for the port
1650 * (MAC statistics, link polling, etc.) and schedule the port to be
1651 * reconfigured. Interrupts must already be enabled. This function
1652 * is safe to call multiple times, so long as the NIC is not disabled.
1653 * Requires the RTNL lock.
9f2cb71c 1654 */
8ceee660
BH		 1655static void efx_start_all(struct efx_nic *efx)
1656{
8ceee660 1657 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1658 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH		 1659
1660 /* Check that it is appropriate to restart the interface. All
1661 * of these flags are safe to read under just the rtnl lock */
8b7325b4 1662 if (efx->port_enabled || !netif_running(efx->net_dev))
8ceee660
BH		 1663 return;
1664
8ceee660 1665 efx_start_port(efx);
9f2cb71c 1666 efx_start_datapath(efx);
8880f4ec 1667
626950db
AR		 1668 /* Start the hardware monitor if there is one */
1669 if (efx->type->monitor != NULL)
8ceee660
BH		 1670 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1671 efx_monitor_interval);
626950db
AR		 1672
1673 /* If link state detection is normally event-driven, we have
1674 * to poll now because we could have missed a change
1675 */
1676 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
78c1f0a0
SH		 1677 mutex_lock(&efx->mac_lock);
1678 if (efx->phy_op->poll(efx))
1679 efx_link_status_changed(efx);
1680 mutex_unlock(&efx->mac_lock);
1681 }
55edc6e6 1682
ef2b90ee 1683 efx->type->start_stats(efx);
8ceee660
BH		 1684}
1685
1686/* Flush all delayed work. Should only be called when no more delayed work
1687 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1688 * since we're holding the rtnl_lock at this point. */
1689static void efx_flush_all(struct efx_nic *efx)
1690{
dd40781e 1691 /* Make sure the hardware monitor and event self-test are stopped */
8ceee660 1692 cancel_delayed_work_sync(&efx->monitor_work);
dd40781e 1693 efx_selftest_async_cancel(efx);
8ceee660 1694 /* Stop scheduled port reconfigurations */
766ca0fa 1695 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1696}
1697
8b7325b4
BH		 1698/* Quiesce the hardware and software data path, and regular activity
1699 * for the port without bringing the link down. Safe to call multiple
1700 * times with the NIC in almost any state, but interrupts should be
1701 * enabled. Requires the RTNL lock.
1702 */
8ceee660
BH		 1703static void efx_stop_all(struct efx_nic *efx)
1704{
8ceee660
BH		 1705 EFX_ASSERT_RESET_SERIALISED(efx);
1706
1707 /* port_enabled can be read safely under the rtnl lock */
1708 if (!efx->port_enabled)
1709 return;
1710
ef2b90ee 1711 efx->type->stop_stats(efx);
8ceee660
BH		 1712 efx_stop_port(efx);
1713
fdaa9aed 1714 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
8ceee660
BH		 1715 efx_flush_all(efx);
1716
29c69a48
BH		 1717 /* Stop the kernel transmit interface. This is only valid if
1718 * the device is stopped or detached; otherwise the watchdog
1719 * may fire immediately.
1720 */
1721 WARN_ON(netif_running(efx->net_dev) &&
1722 netif_device_present(efx->net_dev));
9f2cb71c
BH		 1723 netif_tx_disable(efx->net_dev);
1724
1725 efx_stop_datapath(efx);
8ceee660
BH		 1726}
1727
1728static void efx_remove_all(struct efx_nic *efx)
1729{
4642610c 1730 efx_remove_channels(efx);
7f967c01 1731 efx_remove_filters(efx);
8ceee660
BH		 1732 efx_remove_port(efx);
1733 efx_remove_nic(efx);
1734}
1735
8ceee660
BH		 1736/**************************************************************************
1737 *
1738 * Interrupt moderation
1739 *
1740 **************************************************************************/
1741
cc180b69 1742static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
0d86ebd8 1743{
b548f976
BH		 1744 if (usecs == 0)
1745 return 0;
cc180b69 1746 if (usecs * 1000 < quantum_ns)
0d86ebd8 1747 return 1; /* never round down to 0 */
cc180b69 1748 return usecs * 1000 / quantum_ns;
0d86ebd8
BH		 1749}
1750
8ceee660 1751/* Set interrupt moderation parameters */
9e393b30
BH		 1752int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1753 unsigned int rx_usecs, bool rx_adaptive,
1754 bool rx_may_override_tx)
8ceee660 1755{
f7d12cdc 1756 struct efx_channel *channel;
cc180b69
BH		 1757 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1758 efx->timer_quantum_ns,
1759 1000);
1760 unsigned int tx_ticks;
1761 unsigned int rx_ticks;
8ceee660
BH		 1762
1763 EFX_ASSERT_RESET_SERIALISED(efx);
1764
cc180b69 1765 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
9e393b30
BH		 1766 return -EINVAL;
1767
cc180b69
BH		 1768 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1769 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1770
9e393b30
BH		 1771 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1772 !rx_may_override_tx) {
1773 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1774 "RX and TX IRQ moderation must be equal\n");
1775 return -EINVAL;
1776 }
1777
6fb70fd1 1778 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1779 efx->irq_rx_moderation = rx_ticks;
f7d12cdc 1780 efx_for_each_channel(channel, efx) {
525da907 1781 if (efx_channel_has_rx_queue(channel))
f7d12cdc 1782 channel->irq_moderation = rx_ticks;
525da907 1783 else if (efx_channel_has_tx_queues(channel))
f7d12cdc
BH		 1784 channel->irq_moderation = tx_ticks;
1785 }
9e393b30
BH		 1786
1787 return 0;
8ceee660
BH		 1788}
1789
a0c4faf5
BH		 1790void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
1791 unsigned int *rx_usecs, bool *rx_adaptive)
1792{
cc180b69
BH		 1793 /* We must round up when converting ticks to microseconds
1794 * because we round down when converting the other way.
1795 */
1796
a0c4faf5 1797 *rx_adaptive = efx->irq_rx_adaptive;
cc180b69
BH		 1798 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
1799 efx->timer_quantum_ns,
1800 1000);
a0c4faf5
BH		 1801
1802 /* If channels are shared between RX and TX, so is IRQ
1803 * moderation. Otherwise, IRQ moderation is the same for all
1804 * TX channels and is not adaptive.
1805 */
1806 if (efx->tx_channel_offset == 0)
1807 *tx_usecs = *rx_usecs;
1808 else
cc180b69 1809 *tx_usecs = DIV_ROUND_UP(
a0c4faf5 1810 efx->channel[efx->tx_channel_offset]->irq_moderation *
cc180b69
BH		 1811 efx->timer_quantum_ns,
1812 1000);
a0c4faf5
BH		 1813}
1814
8ceee660
BH		 1815/**************************************************************************
1816 *
1817 * Hardware monitor
1818 *
1819 **************************************************************************/
1820
e254c274 1821/* Run periodically off the general workqueue */
8ceee660
BH		 1822static void efx_monitor(struct work_struct *data)
1823{
1824 struct efx_nic *efx = container_of(data, struct efx_nic,
1825 monitor_work.work);
8ceee660 1826
62776d03
BH		 1827 netif_vdbg(efx, timer, efx->net_dev,
1828 "hardware monitor executing on CPU %d\n",
1829 raw_smp_processor_id());
ef2b90ee 1830 BUG_ON(efx->type->monitor == NULL);
8ceee660 1831
8ceee660
BH		 1832 /* If the mac_lock is already held then it is likely a port
1833 * reconfiguration is already in place, which will likely do
e254c274
BH		 1834 * most of the work of monitor() anyway. */
1835 if (mutex_trylock(&efx->mac_lock)) {
1836 if (efx->port_enabled)
1837 efx->type->monitor(efx);
1838 mutex_unlock(&efx->mac_lock);
1839 }
8ceee660 1840
8ceee660
BH		 1841 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1842 efx_monitor_interval);
1843}
1844
1845/**************************************************************************
1846 *
1847 * ioctls
1848 *
1849 *************************************************************************/
1850
1851/* Net device ioctl
1852 * Context: process, rtnl_lock() held.
1853 */
1854static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1855{
767e468c 1856 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 1857 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 1858
7c236c43
SH		 1859 if (cmd == SIOCSHWTSTAMP)
1860 return efx_ptp_ioctl(efx, ifr, cmd);
1861
68e7f45e
BH		 1862 /* Convert phy_id from older PRTAD/DEVAD format */
1863 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1864 (data->phy_id & 0xfc00) == 0x0400)
1865 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1866
1867 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 1868}
1869
1870/**************************************************************************
1871 *
1872 * NAPI interface
1873 *
1874 **************************************************************************/
1875
7f967c01
BH		 1876static void efx_init_napi_channel(struct efx_channel *channel)
1877{
1878 struct efx_nic *efx = channel->efx;
1879
1880 channel->napi_dev = efx->net_dev;
1881 netif_napi_add(channel->napi_dev, &channel->napi_str,
1882 efx_poll, napi_weight);
1883}
1884
e8f14992 1885static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH		 1886{
1887 struct efx_channel *channel;
8ceee660 1888
7f967c01
BH		 1889 efx_for_each_channel(channel, efx)
1890 efx_init_napi_channel(channel);
e8f14992
BH		 1891}
1892
1893static void efx_fini_napi_channel(struct efx_channel *channel)
1894{
1895 if (channel->napi_dev)
1896 netif_napi_del(&channel->napi_str);
1897 channel->napi_dev = NULL;
8ceee660
BH		 1898}
1899
1900static void efx_fini_napi(struct efx_nic *efx)
1901{
1902 struct efx_channel *channel;
1903
e8f14992
BH		 1904 efx_for_each_channel(channel, efx)
1905 efx_fini_napi_channel(channel);
8ceee660
BH		 1906}
1907
1908/**************************************************************************
1909 *
1910 * Kernel netpoll interface
1911 *
1912 *************************************************************************/
1913
1914#ifdef CONFIG_NET_POLL_CONTROLLER
1915
1916/* Although in the common case interrupts will be disabled, this is not
1917 * guaranteed. However, all our work happens inside the NAPI callback,
1918 * so no locking is required.
1919 */
1920static void efx_netpoll(struct net_device *net_dev)
1921{
767e468c 1922 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1923 struct efx_channel *channel;
1924
64ee3120 1925 efx_for_each_channel(channel, efx)
8ceee660
BH		 1926 efx_schedule_channel(channel);
1927}
1928
1929#endif
1930
1931/**************************************************************************
1932 *
1933 * Kernel net device interface
1934 *
1935 *************************************************************************/
1936
1937/* Context: process, rtnl_lock() held. */
1938static int efx_net_open(struct net_device *net_dev)
1939{
767e468c 1940 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH		 1941 int rc;
1942
62776d03
BH		 1943 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1944 raw_smp_processor_id());
8ceee660 1945
8b7325b4
BH		 1946 rc = efx_check_disabled(efx);
1947 if (rc)
1948 return rc;
f8b87c17
BH		 1949 if (efx->phy_mode & PHY_MODE_SPECIAL)
1950 return -EBUSY;
8880f4ec
BH		 1951 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1952 return -EIO;
f8b87c17 1953
78c1f0a0
SH		 1954 /* Notify the kernel of the link state polled during driver load,
1955 * before the monitor starts running */
1956 efx_link_status_changed(efx);
1957
8ceee660 1958 efx_start_all(efx);
dd40781e 1959 efx_selftest_async_start(efx);
8ceee660
BH		 1960 return 0;
1961}
1962
1963/* Context: process, rtnl_lock() held.
1964 * Note that the kernel will ignore our return code; this method
1965 * should really be a void.
1966 */
1967static int efx_net_stop(struct net_device *net_dev)
1968{
767e468c 1969 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1970
62776d03
BH		 1971 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1972 raw_smp_processor_id());
8ceee660 1973
8b7325b4
BH		 1974 /* Stop the device and flush all the channels */
1975 efx_stop_all(efx);
8ceee660
BH		 1976
1977 return 0;
1978}
1979
5b9e207c 1980/* Context: process, dev_base_lock or RTNL held, non-blocking. */
2aa9ef11
BH		 1981static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
1982 struct rtnl_link_stats64 *stats)
8ceee660 1983{
767e468c 1984 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1985
55edc6e6 1986 spin_lock_bh(&efx->stats_lock);
cd0ecc9a 1987 efx->type->update_stats(efx, NULL, stats);
1cb34522
BH		 1988 spin_unlock_bh(&efx->stats_lock);
1989
8ceee660
BH		 1990 return stats;
1991}
1992
1993/* Context: netif_tx_lock held, BHs disabled. */
1994static void efx_watchdog(struct net_device *net_dev)
1995{
767e468c 1996 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1997
62776d03
BH		 1998 netif_err(efx, tx_err, efx->net_dev,
1999 "TX stuck with port_enabled=%d: resetting channels\n",
2000 efx->port_enabled);
8ceee660 2001
739bb23d 2002 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 2003}
2004
2005
2006/* Context: process, rtnl_lock() held. */
2007static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
2008{
767e468c 2009 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 2010 int rc;
8ceee660 2011
8b7325b4
BH		 2012 rc = efx_check_disabled(efx);
2013 if (rc)
2014 return rc;
8ceee660
BH		 2015 if (new_mtu > EFX_MAX_MTU)
2016 return -EINVAL;
2017
62776d03 2018 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 2019
29c69a48
BH		 2020 efx_device_detach_sync(efx);
2021 efx_stop_all(efx);
2022
d3245b28 2023 mutex_lock(&efx->mac_lock);
8ceee660 2024 net_dev->mtu = new_mtu;
710b208d 2025 efx->type->reconfigure_mac(efx);
d3245b28
BH		 2026 mutex_unlock(&efx->mac_lock);
2027
8ceee660 2028 efx_start_all(efx);
29c69a48 2029 netif_device_attach(efx->net_dev);
6c8eef4a 2030 return 0;
8ceee660
BH		 2031}
2032
2033static int efx_set_mac_address(struct net_device *net_dev, void *data)
2034{
767e468c 2035 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 2036 struct sockaddr *addr = data;
2037 char *new_addr = addr->sa_data;
2038
8ceee660 2039 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH		 2040 netif_err(efx, drv, efx->net_dev,
2041 "invalid ethernet MAC address requested: %pM\n",
2042 new_addr);
504f9b5a 2043 return -EADDRNOTAVAIL;
8ceee660
BH		 2044 }
2045
2046 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
cd2d5b52 2047 efx_sriov_mac_address_changed(efx);
8ceee660
BH		 2048
2049 /* Reconfigure the MAC */
d3245b28 2050 mutex_lock(&efx->mac_lock);
710b208d 2051 efx->type->reconfigure_mac(efx);
d3245b28 2052 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 2053
2054 return 0;
2055}
2056
a816f75a 2057/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 2058static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 2059{
767e468c 2060 struct efx_nic *efx = netdev_priv(net_dev);
a816f75a 2061
8be4f3e6
BH		 2062 if (efx->port_enabled)
2063 queue_work(efx->workqueue, &efx->mac_work);
2064 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 2065}
2066
c8f44aff 2067static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH		 2068{
2069 struct efx_nic *efx = netdev_priv(net_dev);
2070
2071 /* If disabling RX n-tuple filtering, clear existing filters */
2072 if (net_dev->features & ~data & NETIF_F_NTUPLE)
2073 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2074
2075 return 0;
2076}
2077
8127d661 2078static const struct net_device_ops efx_farch_netdev_ops = {
c3ecb9f3
SH		 2079 .ndo_open = efx_net_open,
2080 .ndo_stop = efx_net_stop,
4472702e 2081 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH		 2082 .ndo_tx_timeout = efx_watchdog,
2083 .ndo_start_xmit = efx_hard_start_xmit,
2084 .ndo_validate_addr = eth_validate_addr,
2085 .ndo_do_ioctl = efx_ioctl,
2086 .ndo_change_mtu = efx_change_mtu,
2087 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2088 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2089 .ndo_set_features = efx_set_features,
cd2d5b52
BH		 2090#ifdef CONFIG_SFC_SRIOV
2091 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2092 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2093 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2094 .ndo_get_vf_config = efx_sriov_get_vf_config,
2095#endif
c3ecb9f3
SH		 2096#ifdef CONFIG_NET_POLL_CONTROLLER
2097 .ndo_poll_controller = efx_netpoll,
2098#endif
94b274bf 2099 .ndo_setup_tc = efx_setup_tc,
64d8ad6d
BH		 2100#ifdef CONFIG_RFS_ACCEL
2101 .ndo_rx_flow_steer = efx_filter_rfs,
2102#endif
c3ecb9f3
SH		 2103};
2104
8127d661
BH		 2105static const struct net_device_ops efx_ef10_netdev_ops = {
2106 .ndo_open = efx_net_open,
2107 .ndo_stop = efx_net_stop,
2108 .ndo_get_stats64 = efx_net_stats,
2109 .ndo_tx_timeout = efx_watchdog,
2110 .ndo_start_xmit = efx_hard_start_xmit,
2111 .ndo_validate_addr = eth_validate_addr,
2112 .ndo_do_ioctl = efx_ioctl,
2113 .ndo_change_mtu = efx_change_mtu,
2114 .ndo_set_mac_address = efx_set_mac_address,
2115 .ndo_set_rx_mode = efx_set_rx_mode,
2116 .ndo_set_features = efx_set_features,
2117#ifdef CONFIG_NET_POLL_CONTROLLER
2118 .ndo_poll_controller = efx_netpoll,
2119#endif
2120#ifdef CONFIG_RFS_ACCEL
2121 .ndo_rx_flow_steer = efx_filter_rfs,
2122#endif
2123};
2124
7dde596e
BH		 2125static void efx_update_name(struct efx_nic *efx)
2126{
2127 strcpy(efx->name, efx->net_dev->name);
2128 efx_mtd_rename(efx);
2129 efx_set_channel_names(efx);
2130}
2131
8ceee660
BH		 2132static int efx_netdev_event(struct notifier_block *this,
2133 unsigned long event, void *ptr)
2134{
351638e7 2135 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
8ceee660 2136
8127d661
BH		 2137 if ((net_dev->netdev_ops == &efx_farch_netdev_ops ||
2138 net_dev->netdev_ops == &efx_ef10_netdev_ops) &&
7dde596e
BH		 2139 event == NETDEV_CHANGENAME)
2140 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 2141
2142 return NOTIFY_DONE;
2143}
2144
2145static struct notifier_block efx_netdev_notifier = {
2146 .notifier_call = efx_netdev_event,
2147};
2148
06d5e193
BH		 2149static ssize_t
2150show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2151{
2152 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2153 return sprintf(buf, "%d\n", efx->phy_type);
2154}
776fbcc9 2155static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
06d5e193 2156
8ceee660
BH		 2157static int efx_register_netdev(struct efx_nic *efx)
2158{
2159 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2160 struct efx_channel *channel;
8ceee660
BH		 2161 int rc;
2162
2163 net_dev->watchdog_timeo = 5 * HZ;
2164 net_dev->irq = efx->pci_dev->irq;
8127d661
BH		 2165 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) {
2166 net_dev->netdev_ops = &efx_ef10_netdev_ops;
2167 net_dev->priv_flags |= IFF_UNICAST_FLT;
2168 } else {
2169 net_dev->netdev_ops = &efx_farch_netdev_ops;
2170 }
8ceee660 2171 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
7e6d06f0 2172 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
8ceee660 2173
7dde596e 2174 rtnl_lock();
aed0628d 2175
7153f623
BH		 2176 /* Enable resets to be scheduled and check whether any were
2177 * already requested. If so, the NIC is probably hosed so we
2178 * abort.
2179 */
2180 efx->state = STATE_READY;
2181 smp_mb(); /* ensure we change state before checking reset_pending */
2182 if (efx->reset_pending) {
2183 netif_err(efx, probe, efx->net_dev,
2184 "aborting probe due to scheduled reset\n");
2185 rc = -EIO;
2186 goto fail_locked;
2187 }
2188
aed0628d
BH		 2189 rc = dev_alloc_name(net_dev, net_dev->name);
2190 if (rc < 0)
2191 goto fail_locked;
7dde596e 2192 efx_update_name(efx);
aed0628d 2193
8f8b3d51
BH		 2194 /* Always start with carrier off; PHY events will detect the link */
2195 netif_carrier_off(net_dev);
2196
aed0628d
BH		 2197 rc = register_netdevice(net_dev);
2198 if (rc)
2199 goto fail_locked;
2200
c04bfc6b
BH		 2201 efx_for_each_channel(channel, efx) {
2202 struct efx_tx_queue *tx_queue;
60031fcc
BH		 2203 efx_for_each_channel_tx_queue(tx_queue, channel)
2204 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH		 2205 }
2206
7dde596e 2207 rtnl_unlock();
8ceee660 2208
06d5e193
BH		 2209 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2210 if (rc) {
62776d03
BH		 2211 netif_err(efx, drv, efx->net_dev,
2212 "failed to init net dev attributes\n");
06d5e193
BH		 2213 goto fail_registered;
2214 }
2215
8ceee660 2216 return 0;
06d5e193 2217
7153f623
BH		 2218fail_registered:
2219 rtnl_lock();
2220 unregister_netdevice(net_dev);
aed0628d 2221fail_locked:
7153f623 2222 efx->state = STATE_UNINIT;
aed0628d 2223 rtnl_unlock();
62776d03 2224 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2225 return rc;
8ceee660
BH		 2226}
2227
2228static void efx_unregister_netdev(struct efx_nic *efx)
2229{
8ceee660
BH		 2230 if (!efx->net_dev)
2231 return;
2232
767e468c 2233 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660 2234
73ba7b68
BH		 2235 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2236 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
7153f623
BH		 2237
2238 rtnl_lock();
2239 unregister_netdevice(efx->net_dev);
2240 efx->state = STATE_UNINIT;
2241 rtnl_unlock();
8ceee660
BH		 2242}
2243
2244/**************************************************************************
2245 *
2246 * Device reset and suspend
2247 *
2248 **************************************************************************/
2249
2467ca46
BH		 2250/* Tears down the entire software state and most of the hardware state
2251 * before reset. */
d3245b28 2252void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2253{
8ceee660
BH		 2254 EFX_ASSERT_RESET_SERIALISED(efx);
2255
2467ca46 2256 efx_stop_all(efx);
d8291187 2257 efx_disable_interrupts(efx);
5642ceef
BH		 2258
2259 mutex_lock(&efx->mac_lock);
4b988280
SH		 2260 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2261 efx->phy_op->fini(efx);
ef2b90ee 2262 efx->type->fini(efx);
8ceee660
BH		 2263}
2264
2467ca46
BH		 2265/* This function will always ensure that the locks acquired in
2266 * efx_reset_down() are released. A failure return code indicates
2267 * that we were unable to reinitialise the hardware, and the
2268 * driver should be disabled. If ok is false, then the rx and tx
2269 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2270int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 2271{
2272 int rc;
2273
2467ca46 2274 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2275
ef2b90ee 2276 rc = efx->type->init(efx);
8ceee660 2277 if (rc) {
62776d03 2278 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2279 goto fail;
8ceee660
BH		 2280 }
2281
eb9f6744
BH		 2282 if (!ok)
2283 goto fail;
2284
4b988280 2285 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
eb9f6744
BH		 2286 rc = efx->phy_op->init(efx);
2287 if (rc)
2288 goto fail;
2289 if (efx->phy_op->reconfigure(efx))
62776d03
BH		 2290 netif_err(efx, drv, efx->net_dev,
2291 "could not restore PHY settings\n");
4b988280
SH		 2292 }
2293
261e4d96
JC		 2294 rc = efx_enable_interrupts(efx);
2295 if (rc)
2296 goto fail;
64eebcfd 2297 efx_restore_filters(efx);
cd2d5b52 2298 efx_sriov_reset(efx);
eb9f6744 2299
eb9f6744
BH		 2300 mutex_unlock(&efx->mac_lock);
2301
2302 efx_start_all(efx);
2303
2304 return 0;
2305
2306fail:
2307 efx->port_initialized = false;
2467ca46
BH		 2308
2309 mutex_unlock(&efx->mac_lock);
2310
8ceee660
BH		 2311 return rc;
2312}
2313
eb9f6744
BH		 2314/* Reset the NIC using the specified method. Note that the reset may
2315 * fail, in which case the card will be left in an unusable state.
8ceee660 2316 *
eb9f6744 2317 * Caller must hold the rtnl_lock.
8ceee660 2318 */
eb9f6744 2319int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2320{
eb9f6744
BH		 2321 int rc, rc2;
2322 bool disabled;
8ceee660 2323
62776d03
BH		 2324 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2325 RESET_TYPE(method));
8ceee660 2326
c2f3b8e3 2327 efx_device_detach_sync(efx);
d3245b28 2328 efx_reset_down(efx, method);
8ceee660 2329
ef2b90ee 2330 rc = efx->type->reset(efx, method);
8ceee660 2331 if (rc) {
62776d03 2332 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2333 goto out;
8ceee660
BH		 2334 }
2335
a7d529ae
BH		 2336 /* Clear flags for the scopes we covered. We assume the NIC and
2337 * driver are now quiescent so that there is no race here.
2338 */
2339 efx->reset_pending &= -(1 << (method + 1));
8ceee660
BH		 2340
2341 /* Reinitialise bus-mastering, which may have been turned off before
2342 * the reset was scheduled. This is still appropriate, even in the
2343 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2344 * can respond to requests. */
2345 pci_set_master(efx->pci_dev);
2346
eb9f6744 2347out:
8ceee660 2348 /* Leave device stopped if necessary */
626950db
AR		 2349 disabled = rc ||
2350 method == RESET_TYPE_DISABLE ||
2351 method == RESET_TYPE_RECOVER_OR_DISABLE;
eb9f6744
BH		 2352 rc2 = efx_reset_up(efx, method, !disabled);
2353 if (rc2) {
2354 disabled = true;
2355 if (!rc)
2356 rc = rc2;
8ceee660
BH		 2357 }
2358
eb9f6744 2359 if (disabled) {
f49a4589 2360 dev_close(efx->net_dev);
62776d03 2361 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2362 efx->state = STATE_DISABLED;
f4bd954e 2363 } else {
62776d03 2364 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2365 netif_device_attach(efx->net_dev);
f4bd954e 2366 }
8ceee660
BH		 2367 return rc;
2368}
2369
626950db
AR		 2370/* Try recovery mechanisms.
2371 * For now only EEH is supported.
2372 * Returns 0 if the recovery mechanisms are unsuccessful.
2373 * Returns a non-zero value otherwise.
2374 */
b28405b0 2375int efx_try_recovery(struct efx_nic *efx)
626950db
AR		 2376{
2377#ifdef CONFIG_EEH
2378 /* A PCI error can occur and not be seen by EEH because nothing
2379 * happens on the PCI bus. In this case the driver may fail and
2380 * schedule a 'recover or reset', leading to this recovery handler.
2381 * Manually call the eeh failure check function.
2382 */
2383 struct eeh_dev *eehdev =
2384 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
2385
2386 if (eeh_dev_check_failure(eehdev)) {
2387 /* The EEH mechanisms will handle the error and reset the
2388 * device if necessary.
2389 */
2390 return 1;
2391 }
2392#endif
2393 return 0;
2394}
2395
8ceee660
BH		 2396/* The worker thread exists so that code that cannot sleep can
2397 * schedule a reset for later.
2398 */
2399static void efx_reset_work(struct work_struct *data)
2400{
eb9f6744 2401 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
626950db
AR		 2402 unsigned long pending;
2403 enum reset_type method;
2404
2405 pending = ACCESS_ONCE(efx->reset_pending);
2406 method = fls(pending) - 1;
2407
2408 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2409 method == RESET_TYPE_RECOVER_OR_ALL) &&
2410 efx_try_recovery(efx))
2411 return;
8ceee660 2412
a7d529ae 2413 if (!pending)
319ba649
SH		 2414 return;
2415
eb9f6744 2416 rtnl_lock();
7153f623
BH		 2417
2418 /* We checked the state in efx_schedule_reset() but it may
2419 * have changed by now. Now that we have the RTNL lock,
2420 * it cannot change again.
2421 */
2422 if (efx->state == STATE_READY)
626950db 2423 (void)efx_reset(efx, method);
7153f623 2424
eb9f6744 2425 rtnl_unlock();
8ceee660
BH		 2426}
2427
2428void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2429{
2430 enum reset_type method;
2431
626950db
AR		 2432 if (efx->state == STATE_RECOVERY) {
2433 netif_dbg(efx, drv, efx->net_dev,
2434 "recovering: skip scheduling %s reset\n",
2435 RESET_TYPE(type));
2436 return;
2437 }
2438
8ceee660
BH		 2439 switch (type) {
2440 case RESET_TYPE_INVISIBLE:
2441 case RESET_TYPE_ALL:
626950db 2442 case RESET_TYPE_RECOVER_OR_ALL:
8ceee660
BH		 2443 case RESET_TYPE_WORLD:
2444 case RESET_TYPE_DISABLE:
626950db 2445 case RESET_TYPE_RECOVER_OR_DISABLE:
8ceee660 2446 method = type;
0e2a9c7c
BH		 2447 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2448 RESET_TYPE(method));
8ceee660 2449 break;
8ceee660 2450 default:
0e2a9c7c 2451 method = efx->type->map_reset_reason(type);
62776d03
BH		 2452 netif_dbg(efx, drv, efx->net_dev,
2453 "scheduling %s reset for %s\n",
2454 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH		 2455 break;
2456 }
8ceee660 2457
a7d529ae 2458 set_bit(method, &efx->reset_pending);
7153f623
BH		 2459 smp_mb(); /* ensure we change reset_pending before checking state */
2460
2461 /* If we're not READY then just leave the flags set as the cue
2462 * to abort probing or reschedule the reset later.
2463 */
2464 if (ACCESS_ONCE(efx->state) != STATE_READY)
2465 return;
8ceee660 2466
8880f4ec
BH		 2467 /* efx_process_channel() will no longer read events once a
2468 * reset is scheduled. So switch back to poll'd MCDI completions. */
2469 efx_mcdi_mode_poll(efx);
2470
1ab00629 2471 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 2472}
2473
2474/**************************************************************************
2475 *
2476 * List of NICs we support
2477 *
2478 **************************************************************************/
2479
2480/* PCI device ID table */
a3aa1884 2481static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
937383a5
BH		 2482 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2483 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
daeda630 2484 .driver_data = (unsigned long) &falcon_a1_nic_type},
937383a5
BH		 2485 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2486 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
daeda630 2487 .driver_data = (unsigned long) &falcon_b0_nic_type},
547c474f 2488 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2489 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2490 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2491 .driver_data = (unsigned long) &siena_a0_nic_type},
8127d661
BH		 2492 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */
2493 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
8ceee660
BH		 2494 {0} /* end of list */
2495};
2496
2497/**************************************************************************
2498 *
3759433d 2499 * Dummy PHY/MAC operations
8ceee660 2500 *
01aad7b6 2501 * Can be used for some unimplemented operations
8ceee660
BH		 2502 * Needed so all function pointers are valid and do not have to be tested
2503 * before use
2504 *
2505 **************************************************************************/
2506int efx_port_dummy_op_int(struct efx_nic *efx)
2507{
2508 return 0;
2509}
2510void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2511
2512static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH		 2513{
2514 return false;
2515}
8ceee660 2516
6c8c2513 2517static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2518 .init = efx_port_dummy_op_int,
d3245b28 2519 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2520 .poll = efx_port_dummy_op_poll,
8ceee660 2521 .fini = efx_port_dummy_op_void,
8ceee660
BH		 2522};
2523
8ceee660
BH		 2524/**************************************************************************
2525 *
2526 * Data housekeeping
2527 *
2528 **************************************************************************/
2529
2530/* This zeroes out and then fills in the invariants in a struct
2531 * efx_nic (including all sub-structures).
2532 */
adeb15aa 2533static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH		 2534 struct pci_dev *pci_dev, struct net_device *net_dev)
2535{
4642610c 2536 int i;
8ceee660
BH		 2537
2538 /* Initialise common structures */
8ceee660 2539 spin_lock_init(&efx->biu_lock);
76884835
BH		 2540#ifdef CONFIG_SFC_MTD
2541 INIT_LIST_HEAD(&efx->mtd_list);
2542#endif
8ceee660
BH		 2543 INIT_WORK(&efx->reset_work, efx_reset_work);
2544 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2545 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2546 efx->pci_dev = pci_dev;
62776d03 2547 efx->msg_enable = debug;
f16aeea0 2548 efx->state = STATE_UNINIT;
8ceee660 2549 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2550
2551 efx->net_dev = net_dev;
43a3739d
JC		 2552 efx->rx_prefix_size = efx->type->rx_prefix_size;
2553 efx->rx_packet_hash_offset =
2554 efx->type->rx_hash_offset - efx->type->rx_prefix_size;
8ceee660
BH		 2555 spin_lock_init(&efx->stats_lock);
2556 mutex_init(&efx->mac_lock);
2557 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2558 efx->mdio.dev = net_dev;
766ca0fa 2559 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2560 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH		 2561
2562 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH		 2563 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2564 if (!efx->channel[i])
2565 goto fail;
d8291187
BH		 2566 efx->msi_context[i].efx = efx;
2567 efx->msi_context[i].index = i;
8ceee660
BH		 2568 }
2569
8ceee660
BH		 2570 /* Higher numbered interrupt modes are less capable! */
2571 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2572 interrupt_mode);
2573
6977dc63
BH		 2574 /* Would be good to use the net_dev name, but we're too early */
2575 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2576 pci_name(pci_dev));
2577 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2578 if (!efx->workqueue)
4642610c 2579 goto fail;
8d9853d9 2580
8ceee660 2581 return 0;
4642610c
BH		 2582
2583fail:
2584 efx_fini_struct(efx);
2585 return -ENOMEM;
8ceee660
BH		 2586}
2587
2588static void efx_fini_struct(struct efx_nic *efx)
2589{
8313aca3
BH		 2590 int i;
2591
2592 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2593 kfree(efx->channel[i]);
2594
8ceee660
BH		 2595 if (efx->workqueue) {
2596 destroy_workqueue(efx->workqueue);
2597 efx->workqueue = NULL;
2598 }
2599}
2600
2601/**************************************************************************
2602 *
2603 * PCI interface
2604 *
2605 **************************************************************************/
2606
2607/* Main body of final NIC shutdown code
2608 * This is called only at module unload (or hotplug removal).
2609 */
2610static void efx_pci_remove_main(struct efx_nic *efx)
2611{
7153f623
BH		 2612 /* Flush reset_work. It can no longer be scheduled since we
2613 * are not READY.
2614 */
2615 BUG_ON(efx->state == STATE_READY);
2616 cancel_work_sync(&efx->reset_work);
2617
d8291187 2618 efx_disable_interrupts(efx);
152b6a62 2619 efx_nic_fini_interrupt(efx);
8ceee660 2620 efx_fini_port(efx);
ef2b90ee 2621 efx->type->fini(efx);
8ceee660
BH		 2622 efx_fini_napi(efx);
2623 efx_remove_all(efx);
2624}
2625
2626/* Final NIC shutdown
2627 * This is called only at module unload (or hotplug removal).
2628 */
2629static void efx_pci_remove(struct pci_dev *pci_dev)
2630{
2631 struct efx_nic *efx;
2632
2633 efx = pci_get_drvdata(pci_dev);
2634 if (!efx)
2635 return;
2636
2637 /* Mark the NIC as fini, then stop the interface */
2638 rtnl_lock();
8ceee660 2639 dev_close(efx->net_dev);
d8291187 2640 efx_disable_interrupts(efx);
8ceee660
BH		 2641 rtnl_unlock();
2642
cd2d5b52 2643 efx_sriov_fini(efx);
8ceee660
BH		 2644 efx_unregister_netdev(efx);
2645
7dde596e
BH		 2646 efx_mtd_remove(efx);
2647
8ceee660
BH		 2648 efx_pci_remove_main(efx);
2649
8ceee660 2650 efx_fini_io(efx);
62776d03 2651 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 2652
8ceee660 2653 efx_fini_struct(efx);
3de4e301 2654 pci_set_drvdata(pci_dev, NULL);
8ceee660 2655 free_netdev(efx->net_dev);
626950db
AR		 2656
2657 pci_disable_pcie_error_reporting(pci_dev);
8ceee660
BH		 2658};
2659
460eeaa0
BH		 2660/* NIC VPD information
2661 * Called during probe to display the part number of the
2662 * installed NIC. VPD is potentially very large but this should
2663 * always appear within the first 512 bytes.
2664 */
2665#define SFC_VPD_LEN 512
2666static void efx_print_product_vpd(struct efx_nic *efx)
2667{
2668 struct pci_dev *dev = efx->pci_dev;
2669 char vpd_data[SFC_VPD_LEN];
2670 ssize_t vpd_size;
2671 int i, j;
2672
2673 /* Get the vpd data from the device */
2674 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
2675 if (vpd_size <= 0) {
2676 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
2677 return;
2678 }
2679
2680 /* Get the Read only section */
2681 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
2682 if (i < 0) {
2683 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
2684 return;
2685 }
2686
2687 j = pci_vpd_lrdt_size(&vpd_data[i]);
2688 i += PCI_VPD_LRDT_TAG_SIZE;
2689 if (i + j > vpd_size)
2690 j = vpd_size - i;
2691
2692 /* Get the Part number */
2693 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
2694 if (i < 0) {
2695 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
2696 return;
2697 }
2698
2699 j = pci_vpd_info_field_size(&vpd_data[i]);
2700 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2701 if (i + j > vpd_size) {
2702 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
2703 return;
2704 }
2705
2706 netif_info(efx, drv, efx->net_dev,
2707 "Part Number : %.*s\n", j, &vpd_data[i]);
2708}
2709
2710
8ceee660
BH		 2711/* Main body of NIC initialisation
2712 * This is called at module load (or hotplug insertion, theoretically).
2713 */
2714static int efx_pci_probe_main(struct efx_nic *efx)
2715{
2716 int rc;
2717
2718 /* Do start-of-day initialisation */
2719 rc = efx_probe_all(efx);
2720 if (rc)
2721 goto fail1;
2722
e8f14992 2723 efx_init_napi(efx);
8ceee660 2724
ef2b90ee 2725 rc = efx->type->init(efx);
8ceee660 2726 if (rc) {
62776d03
BH		 2727 netif_err(efx, probe, efx->net_dev,
2728 "failed to initialise NIC\n");
278c0621 2729 goto fail3;
8ceee660
BH		 2730 }
2731
2732 rc = efx_init_port(efx);
2733 if (rc) {
62776d03
BH		 2734 netif_err(efx, probe, efx->net_dev,
2735 "failed to initialise port\n");
278c0621 2736 goto fail4;
8ceee660
BH		 2737 }
2738
152b6a62 2739 rc = efx_nic_init_interrupt(efx);
8ceee660 2740 if (rc)
278c0621 2741 goto fail5;
261e4d96
JC		 2742 rc = efx_enable_interrupts(efx);
2743 if (rc)
2744 goto fail6;
8ceee660
BH		 2745
2746 return 0;
2747
261e4d96
JC		 2748 fail6:
2749 efx_nic_fini_interrupt(efx);
278c0621 2750 fail5:
8ceee660 2751 efx_fini_port(efx);
8ceee660 2752 fail4:
ef2b90ee 2753 efx->type->fini(efx);
8ceee660
BH		 2754 fail3:
2755 efx_fini_napi(efx);
8ceee660
BH		 2756 efx_remove_all(efx);
2757 fail1:
2758 return rc;
2759}
2760
2761/* NIC initialisation
2762 *
2763 * This is called at module load (or hotplug insertion,
73ba7b68 2764 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH		 2765 * sets up and registers the network devices with the kernel and hooks
2766 * the interrupt service routine. It does not prepare the device for
2767 * transmission; this is left to the first time one of the network
2768 * interfaces is brought up (i.e. efx_net_open).
2769 */
87d1fc11 2770static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 2771 const struct pci_device_id *entry)
8ceee660 2772{
8ceee660
BH		 2773 struct net_device *net_dev;
2774 struct efx_nic *efx;
fadac6aa 2775 int rc;
8ceee660
BH		 2776
2777 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH		 2778 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2779 EFX_MAX_RX_QUEUES);
8ceee660
BH		 2780 if (!net_dev)
2781 return -ENOMEM;
adeb15aa
BH		 2782 efx = netdev_priv(net_dev);
2783 efx->type = (const struct efx_nic_type *) entry->driver_data;
2784 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
97bc5415 2785 NETIF_F_HIGHDMA | NETIF_F_TSO |
abfe9039 2786 NETIF_F_RXCSUM);
adeb15aa 2787 if (efx->type->offload_features & NETIF_F_V6_CSUM)
738a8f4b 2788 net_dev->features |= NETIF_F_TSO6;
28506563
BH		 2789 /* Mask for features that also apply to VLAN devices */
2790 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
abfe9039
BH		 2791 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2792 NETIF_F_RXCSUM);
2793 /* All offloads can be toggled */
2794 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
8ceee660 2795 pci_set_drvdata(pci_dev, efx);
62776d03 2796 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 2797 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH		 2798 if (rc)
2799 goto fail1;
2800
62776d03 2801 netif_info(efx, probe, efx->net_dev,
ff79c8ac 2802 "Solarflare NIC detected\n");
8ceee660 2803
460eeaa0
BH		 2804 efx_print_product_vpd(efx);
2805
8ceee660
BH		 2806 /* Set up basic I/O (BAR mappings etc) */
2807 rc = efx_init_io(efx);
2808 if (rc)
2809 goto fail2;
2810
fadac6aa 2811 rc = efx_pci_probe_main(efx);
fadac6aa
BH		 2812 if (rc)
2813 goto fail3;
8ceee660 2814
8ceee660
BH		 2815 rc = efx_register_netdev(efx);
2816 if (rc)
fadac6aa 2817 goto fail4;
8ceee660 2818
cd2d5b52
BH		 2819 rc = efx_sriov_init(efx);
2820 if (rc)
2821 netif_err(efx, probe, efx->net_dev,
2822 "SR-IOV can't be enabled rc %d\n", rc);
2823
62776d03 2824 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 2825
7c43161c 2826 /* Try to create MTDs, but allow this to fail */
a5211bb5 2827 rtnl_lock();
7c43161c 2828 rc = efx_mtd_probe(efx);
a5211bb5 2829 rtnl_unlock();
7c43161c
BH		 2830 if (rc)
2831 netif_warn(efx, probe, efx->net_dev,
2832 "failed to create MTDs (%d)\n", rc);
2833
626950db
AR		 2834 rc = pci_enable_pcie_error_reporting(pci_dev);
2835 if (rc && rc != -EINVAL)
2836 netif_warn(efx, probe, efx->net_dev,
2837 "pci_enable_pcie_error_reporting failed (%d)\n", rc);
2838
8ceee660
BH		 2839 return 0;
2840
8ceee660 2841 fail4:
fadac6aa 2842 efx_pci_remove_main(efx);
8ceee660
BH		 2843 fail3:
2844 efx_fini_io(efx);
2845 fail2:
2846 efx_fini_struct(efx);
2847 fail1:
3de4e301 2848 pci_set_drvdata(pci_dev, NULL);
5e2a911c 2849 WARN_ON(rc > 0);
62776d03 2850 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH		 2851 free_netdev(net_dev);
2852 return rc;
2853}
2854
89c758fa
BH		 2855static int efx_pm_freeze(struct device *dev)
2856{
2857 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2858
61da026d
BH		 2859 rtnl_lock();
2860
6032fb56
BH		 2861 if (efx->state != STATE_DISABLED) {
2862 efx->state = STATE_UNINIT;
89c758fa 2863
c2f3b8e3 2864 efx_device_detach_sync(efx);
89c758fa 2865
6032fb56 2866 efx_stop_all(efx);
d8291187 2867 efx_disable_interrupts(efx);
6032fb56 2868 }
89c758fa 2869
61da026d
BH		 2870 rtnl_unlock();
2871
89c758fa
BH		 2872 return 0;
2873}
2874
2875static int efx_pm_thaw(struct device *dev)
2876{
261e4d96 2877 int rc;
89c758fa
BH		 2878 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2879
61da026d
BH		 2880 rtnl_lock();
2881
6032fb56 2882 if (efx->state != STATE_DISABLED) {
261e4d96
JC		 2883 rc = efx_enable_interrupts(efx);
2884 if (rc)
2885 goto fail;
89c758fa 2886
6032fb56
BH		 2887 mutex_lock(&efx->mac_lock);
2888 efx->phy_op->reconfigure(efx);
2889 mutex_unlock(&efx->mac_lock);
89c758fa 2890
6032fb56 2891 efx_start_all(efx);
89c758fa 2892
6032fb56 2893 netif_device_attach(efx->net_dev);
89c758fa 2894
6032fb56 2895 efx->state = STATE_READY;
89c758fa 2896
6032fb56
BH		 2897 efx->type->resume_wol(efx);
2898 }
89c758fa 2899
61da026d
BH		 2900 rtnl_unlock();
2901
319ba649
SH		 2902 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2903 queue_work(reset_workqueue, &efx->reset_work);
2904
89c758fa 2905 return 0;
261e4d96
JC		 2906
2907fail:
2908 rtnl_unlock();
2909
2910 return rc;
89c758fa
BH		 2911}
2912
2913static int efx_pm_poweroff(struct device *dev)
2914{
2915 struct pci_dev *pci_dev = to_pci_dev(dev);
2916 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2917
2918 efx->type->fini(efx);
2919
a7d529ae 2920 efx->reset_pending = 0;
89c758fa
BH		 2921
2922 pci_save_state(pci_dev);
2923 return pci_set_power_state(pci_dev, PCI_D3hot);
2924}
2925
2926/* Used for both resume and restore */
2927static int efx_pm_resume(struct device *dev)
2928{
2929 struct pci_dev *pci_dev = to_pci_dev(dev);
2930 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2931 int rc;
2932
2933 rc = pci_set_power_state(pci_dev, PCI_D0);
2934 if (rc)
2935 return rc;
2936 pci_restore_state(pci_dev);
2937 rc = pci_enable_device(pci_dev);
2938 if (rc)
2939 return rc;
2940 pci_set_master(efx->pci_dev);
2941 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2942 if (rc)
2943 return rc;
2944 rc = efx->type->init(efx);
2945 if (rc)
2946 return rc;
261e4d96
JC		 2947 rc = efx_pm_thaw(dev);
2948 return rc;
89c758fa
BH		 2949}
2950
2951static int efx_pm_suspend(struct device *dev)
2952{
2953 int rc;
2954
2955 efx_pm_freeze(dev);
2956 rc = efx_pm_poweroff(dev);
2957 if (rc)
2958 efx_pm_resume(dev);
2959 return rc;
2960}
2961
18e83e4c 2962static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH		 2963 .suspend = efx_pm_suspend,
2964 .resume = efx_pm_resume,
2965 .freeze = efx_pm_freeze,
2966 .thaw = efx_pm_thaw,
2967 .poweroff = efx_pm_poweroff,
2968 .restore = efx_pm_resume,
2969};
2970
626950db
AR		 2971/* A PCI error affecting this device was detected.
2972 * At this point MMIO and DMA may be disabled.
2973 * Stop the software path and request a slot reset.
2974 */
debd0034 2975static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
2976 enum pci_channel_state state)
626950db
AR		 2977{
2978 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2979 struct efx_nic *efx = pci_get_drvdata(pdev);
2980
2981 if (state == pci_channel_io_perm_failure)
2982 return PCI_ERS_RESULT_DISCONNECT;
2983
2984 rtnl_lock();
2985
2986 if (efx->state != STATE_DISABLED) {
2987 efx->state = STATE_RECOVERY;
2988 efx->reset_pending = 0;
2989
2990 efx_device_detach_sync(efx);
2991
2992 efx_stop_all(efx);
d8291187 2993 efx_disable_interrupts(efx);
626950db
AR		 2994
2995 status = PCI_ERS_RESULT_NEED_RESET;
2996 } else {
2997 /* If the interface is disabled we don't want to do anything
2998 * with it.
2999 */
3000 status = PCI_ERS_RESULT_RECOVERED;
3001 }
3002
3003 rtnl_unlock();
3004
3005 pci_disable_device(pdev);
3006
3007 return status;
3008}
3009
3010/* Fake a successfull reset, which will be performed later in efx_io_resume. */
debd0034 3011static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
626950db
AR		 3012{
3013 struct efx_nic *efx = pci_get_drvdata(pdev);
3014 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3015 int rc;
3016
3017 if (pci_enable_device(pdev)) {
3018 netif_err(efx, hw, efx->net_dev,
3019 "Cannot re-enable PCI device after reset.\n");
3020 status = PCI_ERS_RESULT_DISCONNECT;
3021 }
3022
3023 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
3024 if (rc) {
3025 netif_err(efx, hw, efx->net_dev,
3026 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
3027 /* Non-fatal error. Continue. */
3028 }
3029
3030 return status;
3031}
3032
3033/* Perform the actual reset and resume I/O operations. */
3034static void efx_io_resume(struct pci_dev *pdev)
3035{
3036 struct efx_nic *efx = pci_get_drvdata(pdev);
3037 int rc;
3038
3039 rtnl_lock();
3040
3041 if (efx->state == STATE_DISABLED)
3042 goto out;
3043
3044 rc = efx_reset(efx, RESET_TYPE_ALL);
3045 if (rc) {
3046 netif_err(efx, hw, efx->net_dev,
3047 "efx_reset failed after PCI error (%d)\n", rc);
3048 } else {
3049 efx->state = STATE_READY;
3050 netif_dbg(efx, hw, efx->net_dev,
3051 "Done resetting and resuming IO after PCI error.\n");
3052 }
3053
3054out:
3055 rtnl_unlock();
3056}
3057
3058/* For simplicity and reliability, we always require a slot reset and try to
3059 * reset the hardware when a pci error affecting the device is detected.
3060 * We leave both the link_reset and mmio_enabled callback unimplemented:
3061 * with our request for slot reset the mmio_enabled callback will never be
3062 * called, and the link_reset callback is not used by AER or EEH mechanisms.
3063 */
3064static struct pci_error_handlers efx_err_handlers = {
3065 .error_detected = efx_io_error_detected,
3066 .slot_reset = efx_io_slot_reset,
3067 .resume = efx_io_resume,
3068};
3069
8ceee660 3070static struct pci_driver efx_pci_driver = {
c5d5f5fd 3071 .name = KBUILD_MODNAME,
8ceee660
BH		 3072 .id_table = efx_pci_table,
3073 .probe = efx_pci_probe,
3074 .remove = efx_pci_remove,
89c758fa 3075 .driver.pm = &efx_pm_ops,
626950db 3076 .err_handler = &efx_err_handlers,
8ceee660
BH		 3077};
3078
3079/**************************************************************************
3080 *
3081 * Kernel module interface
3082 *
3083 *************************************************************************/
3084
3085module_param(interrupt_mode, uint, 0444);
3086MODULE_PARM_DESC(interrupt_mode,
3087 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
3088
3089static int __init efx_init_module(void)
3090{
3091 int rc;
3092
3093 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
3094
3095 rc = register_netdevice_notifier(&efx_netdev_notifier);
3096 if (rc)
3097 goto err_notifier;
3098
cd2d5b52
BH		 3099 rc = efx_init_sriov();
3100 if (rc)
3101 goto err_sriov;
3102
1ab00629
SH		 3103 reset_workqueue = create_singlethread_workqueue("sfc_reset");
3104 if (!reset_workqueue) {
3105 rc = -ENOMEM;
3106 goto err_reset;
3107 }
8ceee660
BH		 3108
3109 rc = pci_register_driver(&efx_pci_driver);
3110 if (rc < 0)
3111 goto err_pci;
3112
3113 return 0;
3114
3115 err_pci:
1ab00629
SH		 3116 destroy_workqueue(reset_workqueue);
3117 err_reset:
cd2d5b52
BH		 3118 efx_fini_sriov();
3119 err_sriov:
8ceee660
BH		 3120 unregister_netdevice_notifier(&efx_netdev_notifier);
3121 err_notifier:
3122 return rc;
3123}
3124
3125static void __exit efx_exit_module(void)
3126{
3127 printk(KERN_INFO "Solarflare NET driver unloading\n");
3128
3129 pci_unregister_driver(&efx_pci_driver);
1ab00629 3130 destroy_workqueue(reset_workqueue);
cd2d5b52 3131 efx_fini_sriov();
8ceee660
BH		 3132 unregister_netdevice_notifier(&efx_netdev_notifier);
3133
3134}
3135
3136module_init(efx_init_module);
3137module_exit(efx_exit_module);
3138
906bb26c
BH		 3139MODULE_AUTHOR("Solarflare Communications and "
3140 "Michael Brown <mbrown@fensystems.co.uk>");
8ceee660
BH		 3141MODULE_DESCRIPTION("Solarflare Communications network driver");
3142MODULE_LICENSE("GPL");
3143MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux kernel - Deliverables
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