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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2006-2010 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #ifndef EFX_EFX_H | |
12 | #define EFX_EFX_H | |
13 | ||
14 | #include "net_driver.h" | |
64eebcfd | 15 | #include "filter.h" |
8ceee660 | 16 | |
dc803df8 BH |
17 | /* Solarstorm controllers use BAR 0 for I/O space and BAR 2(&3) for memory */ |
18 | #define EFX_MEM_BAR 2 | |
19 | ||
8ceee660 | 20 | /* TX */ |
f5e7adc3 BH |
21 | extern int efx_probe_tx_queue(struct efx_tx_queue *tx_queue); |
22 | extern void efx_remove_tx_queue(struct efx_tx_queue *tx_queue); | |
23 | extern void efx_init_tx_queue(struct efx_tx_queue *tx_queue); | |
60031fcc | 24 | extern void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue); |
f5e7adc3 BH |
25 | extern void efx_fini_tx_queue(struct efx_tx_queue *tx_queue); |
26 | extern void efx_release_tx_buffers(struct efx_tx_queue *tx_queue); | |
27 | extern netdev_tx_t | |
28 | efx_hard_start_xmit(struct sk_buff *skb, struct net_device *net_dev); | |
29 | extern netdev_tx_t | |
30 | efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb); | |
59cf09cc | 31 | extern void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index); |
94b274bf | 32 | extern int efx_setup_tc(struct net_device *net_dev, u8 num_tc); |
7e6d06f0 | 33 | extern unsigned int efx_tx_max_skb_descs(struct efx_nic *efx); |
8ceee660 BH |
34 | |
35 | /* RX */ | |
1648a23f | 36 | extern void efx_rx_config_page_split(struct efx_nic *efx); |
f5e7adc3 BH |
37 | extern int efx_probe_rx_queue(struct efx_rx_queue *rx_queue); |
38 | extern void efx_remove_rx_queue(struct efx_rx_queue *rx_queue); | |
39 | extern void efx_init_rx_queue(struct efx_rx_queue *rx_queue); | |
40 | extern void efx_fini_rx_queue(struct efx_rx_queue *rx_queue); | |
f5e7adc3 | 41 | extern void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue); |
90d683af | 42 | extern void efx_rx_slow_fill(unsigned long context); |
85740cdf BH |
43 | extern void __efx_rx_packet(struct efx_channel *channel); |
44 | extern void efx_rx_packet(struct efx_rx_queue *rx_queue, | |
45 | unsigned int index, unsigned int n_frags, | |
db339569 | 46 | unsigned int len, u16 flags); |
ff734ef4 BH |
47 | static inline void efx_rx_flush_packet(struct efx_channel *channel) |
48 | { | |
85740cdf BH |
49 | if (channel->rx_pkt_n_frags) |
50 | __efx_rx_packet(channel); | |
ff734ef4 | 51 | } |
90d683af | 52 | extern void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue); |
ecc910f5 SH |
53 | |
54 | #define EFX_MAX_DMAQ_SIZE 4096UL | |
55 | #define EFX_DEFAULT_DMAQ_SIZE 1024UL | |
56 | #define EFX_MIN_DMAQ_SIZE 512UL | |
57 | ||
58 | #define EFX_MAX_EVQ_SIZE 16384UL | |
59 | #define EFX_MIN_EVQ_SIZE 512UL | |
8ceee660 | 60 | |
7e6d06f0 BH |
61 | /* Maximum number of TCP segments we support for soft-TSO */ |
62 | #define EFX_TSO_MAX_SEGS 100 | |
63 | ||
64 | /* The smallest [rt]xq_entries that the driver supports. RX minimum | |
65 | * is a bit arbitrary. For TX, we must have space for at least 2 | |
66 | * TSO skbs. | |
67 | */ | |
68 | #define EFX_RXQ_MIN_ENT 128U | |
69 | #define EFX_TXQ_MIN_ENT(efx) (2 * efx_tx_max_skb_descs(efx)) | |
4642610c | 70 | |
64eebcfd BH |
71 | /* Filters */ |
72 | extern int efx_probe_filters(struct efx_nic *efx); | |
73 | extern void efx_restore_filters(struct efx_nic *efx); | |
74 | extern void efx_remove_filters(struct efx_nic *efx); | |
85740cdf | 75 | extern void efx_filter_update_rx_scatter(struct efx_nic *efx); |
3532650f | 76 | extern s32 efx_filter_insert_filter(struct efx_nic *efx, |
64eebcfd BH |
77 | struct efx_filter_spec *spec, |
78 | bool replace); | |
1a6281ac BH |
79 | extern int efx_filter_remove_id_safe(struct efx_nic *efx, |
80 | enum efx_filter_priority priority, | |
81 | u32 filter_id); | |
82 | extern int efx_filter_get_filter_safe(struct efx_nic *efx, | |
83 | enum efx_filter_priority priority, | |
84 | u32 filter_id, struct efx_filter_spec *); | |
8891681a BH |
85 | extern void efx_filter_clear_rx(struct efx_nic *efx, |
86 | enum efx_filter_priority priority); | |
1a6281ac BH |
87 | extern u32 efx_filter_count_rx_used(struct efx_nic *efx, |
88 | enum efx_filter_priority priority); | |
89 | extern u32 efx_filter_get_rx_id_limit(struct efx_nic *efx); | |
90 | extern s32 efx_filter_get_rx_ids(struct efx_nic *efx, | |
91 | enum efx_filter_priority priority, | |
92 | u32 *buf, u32 size); | |
64d8ad6d BH |
93 | #ifdef CONFIG_RFS_ACCEL |
94 | extern int efx_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb, | |
95 | u16 rxq_index, u32 flow_id); | |
96 | extern bool __efx_filter_rfs_expire(struct efx_nic *efx, unsigned quota); | |
97 | static inline void efx_filter_rfs_expire(struct efx_channel *channel) | |
98 | { | |
99 | if (channel->rfs_filters_added >= 60 && | |
100 | __efx_filter_rfs_expire(channel->efx, 100)) | |
101 | channel->rfs_filters_added -= 60; | |
102 | } | |
103 | #define efx_filter_rfs_enabled() 1 | |
104 | #else | |
105 | static inline void efx_filter_rfs_expire(struct efx_channel *channel) {} | |
106 | #define efx_filter_rfs_enabled() 0 | |
107 | #endif | |
64eebcfd | 108 | |
8ceee660 | 109 | /* Channels */ |
7f967c01 | 110 | extern int efx_channel_dummy_op_int(struct efx_channel *channel); |
c31e5f9f | 111 | extern void efx_channel_dummy_op_void(struct efx_channel *channel); |
8ceee660 | 112 | extern void efx_process_channel_now(struct efx_channel *channel); |
4642610c BH |
113 | extern int |
114 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries); | |
8ceee660 BH |
115 | |
116 | /* Ports */ | |
d3245b28 BH |
117 | extern int efx_reconfigure_port(struct efx_nic *efx); |
118 | extern int __efx_reconfigure_port(struct efx_nic *efx); | |
8c8661e4 | 119 | |
f5e7adc3 | 120 | /* Ethtool support */ |
f5e7adc3 BH |
121 | extern const struct ethtool_ops efx_ethtool_ops; |
122 | ||
8c8661e4 | 123 | /* Reset handling */ |
eb9f6744 | 124 | extern int efx_reset(struct efx_nic *efx, enum reset_type method); |
d3245b28 BH |
125 | extern void efx_reset_down(struct efx_nic *efx, enum reset_type method); |
126 | extern int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok); | |
b28405b0 | 127 | extern int efx_try_recovery(struct efx_nic *efx); |
8ceee660 BH |
128 | |
129 | /* Global */ | |
130 | extern void efx_schedule_reset(struct efx_nic *efx, enum reset_type type); | |
9e393b30 BH |
131 | extern int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
132 | unsigned int rx_usecs, bool rx_adaptive, | |
133 | bool rx_may_override_tx); | |
a0c4faf5 BH |
134 | extern void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
135 | unsigned int *rx_usecs, bool *rx_adaptive); | |
8ceee660 BH |
136 | |
137 | /* Dummy PHY ops for PHY drivers */ | |
138 | extern int efx_port_dummy_op_int(struct efx_nic *efx); | |
139 | extern void efx_port_dummy_op_void(struct efx_nic *efx); | |
d215697f | 140 | |
8ceee660 | 141 | |
f4150724 BH |
142 | /* MTD */ |
143 | #ifdef CONFIG_SFC_MTD | |
144 | extern int efx_mtd_probe(struct efx_nic *efx); | |
145 | extern void efx_mtd_rename(struct efx_nic *efx); | |
146 | extern void efx_mtd_remove(struct efx_nic *efx); | |
147 | #else | |
148 | static inline int efx_mtd_probe(struct efx_nic *efx) { return 0; } | |
149 | static inline void efx_mtd_rename(struct efx_nic *efx) {} | |
150 | static inline void efx_mtd_remove(struct efx_nic *efx) {} | |
151 | #endif | |
8ceee660 | 152 | |
8ceee660 BH |
153 | static inline void efx_schedule_channel(struct efx_channel *channel) |
154 | { | |
62776d03 BH |
155 | netif_vdbg(channel->efx, intr, channel->efx->net_dev, |
156 | "channel %d scheduling NAPI poll on CPU%d\n", | |
157 | channel->channel, raw_smp_processor_id()); | |
dc8cfa55 | 158 | channel->work_pending = true; |
8ceee660 | 159 | |
288379f0 | 160 | napi_schedule(&channel->napi_str); |
8ceee660 BH |
161 | } |
162 | ||
1646a6f3 BH |
163 | static inline void efx_schedule_channel_irq(struct efx_channel *channel) |
164 | { | |
dd40781e | 165 | channel->event_test_cpu = raw_smp_processor_id(); |
1646a6f3 BH |
166 | efx_schedule_channel(channel); |
167 | } | |
168 | ||
fdaa9aed | 169 | extern void efx_link_status_changed(struct efx_nic *efx); |
d3245b28 | 170 | extern void efx_link_set_advertising(struct efx_nic *efx, u32); |
b5626946 | 171 | extern void efx_link_set_wanted_fc(struct efx_nic *efx, u8); |
fdaa9aed | 172 | |
c2f3b8e3 DP |
173 | static inline void efx_device_detach_sync(struct efx_nic *efx) |
174 | { | |
175 | struct net_device *dev = efx->net_dev; | |
176 | ||
177 | /* Lock/freeze all TX queues so that we can be sure the | |
178 | * TX scheduler is stopped when we're done and before | |
179 | * netif_device_present() becomes false. | |
180 | */ | |
35205b21 | 181 | netif_tx_lock_bh(dev); |
c2f3b8e3 | 182 | netif_device_detach(dev); |
35205b21 | 183 | netif_tx_unlock_bh(dev); |
c2f3b8e3 DP |
184 | } |
185 | ||
8ceee660 | 186 | #endif /* EFX_EFX_H */ |