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86094f7f | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
86094f7f | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2006-2013 Solarflare Communications Inc. |
86094f7f BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/seq_file.h> | |
964e6135 | 17 | #include <linux/crc32.h> |
86094f7f BH |
18 | #include "net_driver.h" |
19 | #include "bitfield.h" | |
20 | #include "efx.h" | |
21 | #include "nic.h" | |
22 | #include "farch_regs.h" | |
23 | #include "io.h" | |
24 | #include "workarounds.h" | |
25 | ||
26 | /* Falcon-architecture (SFC4000 and SFC9000-family) support */ | |
27 | ||
28 | /************************************************************************** | |
29 | * | |
30 | * Configurable values | |
31 | * | |
32 | ************************************************************************** | |
33 | */ | |
34 | ||
35 | /* This is set to 16 for a good reason. In summary, if larger than | |
36 | * 16, the descriptor cache holds more than a default socket | |
37 | * buffer's worth of packets (for UDP we can only have at most one | |
38 | * socket buffer's worth outstanding). This combined with the fact | |
39 | * that we only get 1 TX event per descriptor cache means the NIC | |
40 | * goes idle. | |
41 | */ | |
42 | #define TX_DC_ENTRIES 16 | |
43 | #define TX_DC_ENTRIES_ORDER 1 | |
44 | ||
45 | #define RX_DC_ENTRIES 64 | |
46 | #define RX_DC_ENTRIES_ORDER 3 | |
47 | ||
48 | /* If EFX_MAX_INT_ERRORS internal errors occur within | |
49 | * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and | |
50 | * disable it. | |
51 | */ | |
52 | #define EFX_INT_ERROR_EXPIRE 3600 | |
53 | #define EFX_MAX_INT_ERRORS 5 | |
54 | ||
55 | /* Depth of RX flush request fifo */ | |
56 | #define EFX_RX_FLUSH_COUNT 4 | |
57 | ||
58 | /* Driver generated events */ | |
59 | #define _EFX_CHANNEL_MAGIC_TEST 0x000101 | |
60 | #define _EFX_CHANNEL_MAGIC_FILL 0x000102 | |
61 | #define _EFX_CHANNEL_MAGIC_RX_DRAIN 0x000103 | |
62 | #define _EFX_CHANNEL_MAGIC_TX_DRAIN 0x000104 | |
63 | ||
64 | #define _EFX_CHANNEL_MAGIC(_code, _data) ((_code) << 8 | (_data)) | |
65 | #define _EFX_CHANNEL_MAGIC_CODE(_magic) ((_magic) >> 8) | |
66 | ||
67 | #define EFX_CHANNEL_MAGIC_TEST(_channel) \ | |
68 | _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel) | |
69 | #define EFX_CHANNEL_MAGIC_FILL(_rx_queue) \ | |
70 | _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL, \ | |
71 | efx_rx_queue_index(_rx_queue)) | |
72 | #define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue) \ | |
73 | _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN, \ | |
74 | efx_rx_queue_index(_rx_queue)) | |
75 | #define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue) \ | |
76 | _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN, \ | |
77 | (_tx_queue)->queue) | |
78 | ||
79 | static void efx_farch_magic_event(struct efx_channel *channel, u32 magic); | |
80 | ||
81 | /************************************************************************** | |
82 | * | |
83 | * Hardware access | |
84 | * | |
85 | **************************************************************************/ | |
86 | ||
87 | static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value, | |
88 | unsigned int index) | |
89 | { | |
90 | efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base, | |
91 | value, index); | |
92 | } | |
93 | ||
94 | static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b, | |
95 | const efx_oword_t *mask) | |
96 | { | |
97 | return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || | |
98 | ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); | |
99 | } | |
100 | ||
101 | int efx_farch_test_registers(struct efx_nic *efx, | |
102 | const struct efx_farch_register_test *regs, | |
103 | size_t n_regs) | |
104 | { | |
105 | unsigned address = 0, i, j; | |
106 | efx_oword_t mask, imask, original, reg, buf; | |
107 | ||
108 | for (i = 0; i < n_regs; ++i) { | |
109 | address = regs[i].address; | |
110 | mask = imask = regs[i].mask; | |
111 | EFX_INVERT_OWORD(imask); | |
112 | ||
113 | efx_reado(efx, &original, address); | |
114 | ||
115 | /* bit sweep on and off */ | |
116 | for (j = 0; j < 128; j++) { | |
117 | if (!EFX_EXTRACT_OWORD32(mask, j, j)) | |
118 | continue; | |
119 | ||
120 | /* Test this testable bit can be set in isolation */ | |
121 | EFX_AND_OWORD(reg, original, mask); | |
122 | EFX_SET_OWORD32(reg, j, j, 1); | |
123 | ||
124 | efx_writeo(efx, ®, address); | |
125 | efx_reado(efx, &buf, address); | |
126 | ||
127 | if (efx_masked_compare_oword(®, &buf, &mask)) | |
128 | goto fail; | |
129 | ||
130 | /* Test this testable bit can be cleared in isolation */ | |
131 | EFX_OR_OWORD(reg, original, mask); | |
132 | EFX_SET_OWORD32(reg, j, j, 0); | |
133 | ||
134 | efx_writeo(efx, ®, address); | |
135 | efx_reado(efx, &buf, address); | |
136 | ||
137 | if (efx_masked_compare_oword(®, &buf, &mask)) | |
138 | goto fail; | |
139 | } | |
140 | ||
141 | efx_writeo(efx, &original, address); | |
142 | } | |
143 | ||
144 | return 0; | |
145 | ||
146 | fail: | |
147 | netif_err(efx, hw, efx->net_dev, | |
148 | "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT | |
149 | " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg), | |
150 | EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask)); | |
151 | return -EIO; | |
152 | } | |
153 | ||
154 | /************************************************************************** | |
155 | * | |
156 | * Special buffer handling | |
157 | * Special buffers are used for event queues and the TX and RX | |
158 | * descriptor rings. | |
159 | * | |
160 | *************************************************************************/ | |
161 | ||
162 | /* | |
163 | * Initialise a special buffer | |
164 | * | |
165 | * This will define a buffer (previously allocated via | |
166 | * efx_alloc_special_buffer()) in the buffer table, allowing | |
167 | * it to be used for event queues, descriptor rings etc. | |
168 | */ | |
169 | static void | |
170 | efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) | |
171 | { | |
172 | efx_qword_t buf_desc; | |
173 | unsigned int index; | |
174 | dma_addr_t dma_addr; | |
175 | int i; | |
176 | ||
177 | EFX_BUG_ON_PARANOID(!buffer->buf.addr); | |
178 | ||
179 | /* Write buffer descriptors to NIC */ | |
180 | for (i = 0; i < buffer->entries; i++) { | |
181 | index = buffer->index + i; | |
182 | dma_addr = buffer->buf.dma_addr + (i * EFX_BUF_SIZE); | |
183 | netif_dbg(efx, probe, efx->net_dev, | |
184 | "mapping special buffer %d at %llx\n", | |
185 | index, (unsigned long long)dma_addr); | |
186 | EFX_POPULATE_QWORD_3(buf_desc, | |
187 | FRF_AZ_BUF_ADR_REGION, 0, | |
188 | FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12, | |
189 | FRF_AZ_BUF_OWNER_ID_FBUF, 0); | |
190 | efx_write_buf_tbl(efx, &buf_desc, index); | |
191 | } | |
192 | } | |
193 | ||
194 | /* Unmaps a buffer and clears the buffer table entries */ | |
195 | static void | |
196 | efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) | |
197 | { | |
198 | efx_oword_t buf_tbl_upd; | |
199 | unsigned int start = buffer->index; | |
200 | unsigned int end = (buffer->index + buffer->entries - 1); | |
201 | ||
202 | if (!buffer->entries) | |
203 | return; | |
204 | ||
205 | netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n", | |
206 | buffer->index, buffer->index + buffer->entries - 1); | |
207 | ||
208 | EFX_POPULATE_OWORD_4(buf_tbl_upd, | |
209 | FRF_AZ_BUF_UPD_CMD, 0, | |
210 | FRF_AZ_BUF_CLR_CMD, 1, | |
211 | FRF_AZ_BUF_CLR_END_ID, end, | |
212 | FRF_AZ_BUF_CLR_START_ID, start); | |
213 | efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD); | |
214 | } | |
215 | ||
216 | /* | |
217 | * Allocate a new special buffer | |
218 | * | |
219 | * This allocates memory for a new buffer, clears it and allocates a | |
220 | * new buffer ID range. It does not write into the buffer table. | |
221 | * | |
222 | * This call will allocate 4KB buffers, since 8KB buffers can't be | |
223 | * used for event queues and descriptor rings. | |
224 | */ | |
225 | static int efx_alloc_special_buffer(struct efx_nic *efx, | |
226 | struct efx_special_buffer *buffer, | |
227 | unsigned int len) | |
228 | { | |
2dc313ec SS |
229 | #ifdef CONFIG_SFC_SRIOV |
230 | struct siena_nic_data *nic_data = efx->nic_data; | |
231 | #endif | |
86094f7f BH |
232 | len = ALIGN(len, EFX_BUF_SIZE); |
233 | ||
234 | if (efx_nic_alloc_buffer(efx, &buffer->buf, len, GFP_KERNEL)) | |
235 | return -ENOMEM; | |
236 | buffer->entries = len / EFX_BUF_SIZE; | |
237 | BUG_ON(buffer->buf.dma_addr & (EFX_BUF_SIZE - 1)); | |
238 | ||
239 | /* Select new buffer ID */ | |
240 | buffer->index = efx->next_buffer_table; | |
241 | efx->next_buffer_table += buffer->entries; | |
242 | #ifdef CONFIG_SFC_SRIOV | |
327c685e | 243 | BUG_ON(efx_siena_sriov_enabled(efx) && |
2dc313ec | 244 | nic_data->vf_buftbl_base < efx->next_buffer_table); |
86094f7f BH |
245 | #endif |
246 | ||
247 | netif_dbg(efx, probe, efx->net_dev, | |
248 | "allocating special buffers %d-%d at %llx+%x " | |
249 | "(virt %p phys %llx)\n", buffer->index, | |
250 | buffer->index + buffer->entries - 1, | |
251 | (u64)buffer->buf.dma_addr, len, | |
252 | buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr)); | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
257 | static void | |
258 | efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) | |
259 | { | |
260 | if (!buffer->buf.addr) | |
261 | return; | |
262 | ||
263 | netif_dbg(efx, hw, efx->net_dev, | |
264 | "deallocating special buffers %d-%d at %llx+%x " | |
265 | "(virt %p phys %llx)\n", buffer->index, | |
266 | buffer->index + buffer->entries - 1, | |
267 | (u64)buffer->buf.dma_addr, buffer->buf.len, | |
268 | buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr)); | |
269 | ||
270 | efx_nic_free_buffer(efx, &buffer->buf); | |
271 | buffer->entries = 0; | |
272 | } | |
273 | ||
274 | /************************************************************************** | |
275 | * | |
276 | * TX path | |
277 | * | |
278 | **************************************************************************/ | |
279 | ||
280 | /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ | |
281 | static inline void efx_farch_notify_tx_desc(struct efx_tx_queue *tx_queue) | |
282 | { | |
283 | unsigned write_ptr; | |
284 | efx_dword_t reg; | |
285 | ||
286 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; | |
287 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); | |
288 | efx_writed_page(tx_queue->efx, ®, | |
289 | FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue); | |
290 | } | |
291 | ||
292 | /* Write pointer and first descriptor for TX descriptor ring */ | |
293 | static inline void efx_farch_push_tx_desc(struct efx_tx_queue *tx_queue, | |
294 | const efx_qword_t *txd) | |
295 | { | |
296 | unsigned write_ptr; | |
297 | efx_oword_t reg; | |
298 | ||
299 | BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0); | |
300 | BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0); | |
301 | ||
302 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; | |
303 | EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true, | |
304 | FRF_AZ_TX_DESC_WPTR, write_ptr); | |
305 | reg.qword[0] = *txd; | |
306 | efx_writeo_page(tx_queue->efx, ®, | |
307 | FR_BZ_TX_DESC_UPD_P0, tx_queue->queue); | |
308 | } | |
309 | ||
310 | ||
311 | /* For each entry inserted into the software descriptor ring, create a | |
312 | * descriptor in the hardware TX descriptor ring (in host memory), and | |
313 | * write a doorbell. | |
314 | */ | |
315 | void efx_farch_tx_write(struct efx_tx_queue *tx_queue) | |
316 | { | |
86094f7f BH |
317 | struct efx_tx_buffer *buffer; |
318 | efx_qword_t *txd; | |
319 | unsigned write_ptr; | |
320 | unsigned old_write_count = tx_queue->write_count; | |
321 | ||
322 | BUG_ON(tx_queue->write_count == tx_queue->insert_count); | |
323 | ||
324 | do { | |
325 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; | |
326 | buffer = &tx_queue->buffer[write_ptr]; | |
327 | txd = efx_tx_desc(tx_queue, write_ptr); | |
328 | ++tx_queue->write_count; | |
329 | ||
ba8977bd BH |
330 | EFX_BUG_ON_PARANOID(buffer->flags & EFX_TX_BUF_OPTION); |
331 | ||
86094f7f BH |
332 | /* Create TX descriptor ring entry */ |
333 | BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); | |
334 | EFX_POPULATE_QWORD_4(*txd, | |
335 | FSF_AZ_TX_KER_CONT, | |
336 | buffer->flags & EFX_TX_BUF_CONT, | |
337 | FSF_AZ_TX_KER_BYTE_COUNT, buffer->len, | |
338 | FSF_AZ_TX_KER_BUF_REGION, 0, | |
339 | FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr); | |
340 | } while (tx_queue->write_count != tx_queue->insert_count); | |
341 | ||
342 | wmb(); /* Ensure descriptors are written before they are fetched */ | |
343 | ||
344 | if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { | |
345 | txd = efx_tx_desc(tx_queue, | |
346 | old_write_count & tx_queue->ptr_mask); | |
347 | efx_farch_push_tx_desc(tx_queue, txd); | |
348 | ++tx_queue->pushes; | |
349 | } else { | |
350 | efx_farch_notify_tx_desc(tx_queue); | |
351 | } | |
352 | } | |
353 | ||
354 | /* Allocate hardware resources for a TX queue */ | |
355 | int efx_farch_tx_probe(struct efx_tx_queue *tx_queue) | |
356 | { | |
357 | struct efx_nic *efx = tx_queue->efx; | |
358 | unsigned entries; | |
359 | ||
360 | entries = tx_queue->ptr_mask + 1; | |
361 | return efx_alloc_special_buffer(efx, &tx_queue->txd, | |
362 | entries * sizeof(efx_qword_t)); | |
363 | } | |
364 | ||
365 | void efx_farch_tx_init(struct efx_tx_queue *tx_queue) | |
366 | { | |
367 | struct efx_nic *efx = tx_queue->efx; | |
368 | efx_oword_t reg; | |
369 | ||
370 | /* Pin TX descriptor ring */ | |
371 | efx_init_special_buffer(efx, &tx_queue->txd); | |
372 | ||
373 | /* Push TX descriptor ring to card */ | |
374 | EFX_POPULATE_OWORD_10(reg, | |
375 | FRF_AZ_TX_DESCQ_EN, 1, | |
376 | FRF_AZ_TX_ISCSI_DDIG_EN, 0, | |
377 | FRF_AZ_TX_ISCSI_HDIG_EN, 0, | |
378 | FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, | |
379 | FRF_AZ_TX_DESCQ_EVQ_ID, | |
380 | tx_queue->channel->channel, | |
381 | FRF_AZ_TX_DESCQ_OWNER_ID, 0, | |
382 | FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue, | |
383 | FRF_AZ_TX_DESCQ_SIZE, | |
384 | __ffs(tx_queue->txd.entries), | |
385 | FRF_AZ_TX_DESCQ_TYPE, 0, | |
386 | FRF_BZ_TX_NON_IP_DROP_DIS, 1); | |
387 | ||
388 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { | |
389 | int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; | |
390 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum); | |
391 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS, | |
392 | !csum); | |
393 | } | |
394 | ||
395 | efx_writeo_table(efx, ®, efx->type->txd_ptr_tbl_base, | |
396 | tx_queue->queue); | |
397 | ||
398 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { | |
399 | /* Only 128 bits in this register */ | |
400 | BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128); | |
401 | ||
402 | efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); | |
403 | if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) | |
404 | __clear_bit_le(tx_queue->queue, ®); | |
405 | else | |
406 | __set_bit_le(tx_queue->queue, ®); | |
407 | efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG); | |
408 | } | |
409 | ||
410 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { | |
411 | EFX_POPULATE_OWORD_1(reg, | |
412 | FRF_BZ_TX_PACE, | |
413 | (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ? | |
414 | FFE_BZ_TX_PACE_OFF : | |
415 | FFE_BZ_TX_PACE_RESERVED); | |
416 | efx_writeo_table(efx, ®, FR_BZ_TX_PACE_TBL, | |
417 | tx_queue->queue); | |
418 | } | |
419 | } | |
420 | ||
421 | static void efx_farch_flush_tx_queue(struct efx_tx_queue *tx_queue) | |
422 | { | |
423 | struct efx_nic *efx = tx_queue->efx; | |
424 | efx_oword_t tx_flush_descq; | |
425 | ||
426 | WARN_ON(atomic_read(&tx_queue->flush_outstanding)); | |
427 | atomic_set(&tx_queue->flush_outstanding, 1); | |
428 | ||
429 | EFX_POPULATE_OWORD_2(tx_flush_descq, | |
430 | FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, | |
431 | FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue); | |
432 | efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ); | |
433 | } | |
434 | ||
435 | void efx_farch_tx_fini(struct efx_tx_queue *tx_queue) | |
436 | { | |
437 | struct efx_nic *efx = tx_queue->efx; | |
438 | efx_oword_t tx_desc_ptr; | |
439 | ||
440 | /* Remove TX descriptor ring from card */ | |
441 | EFX_ZERO_OWORD(tx_desc_ptr); | |
442 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, | |
443 | tx_queue->queue); | |
444 | ||
445 | /* Unpin TX descriptor ring */ | |
446 | efx_fini_special_buffer(efx, &tx_queue->txd); | |
447 | } | |
448 | ||
449 | /* Free buffers backing TX queue */ | |
450 | void efx_farch_tx_remove(struct efx_tx_queue *tx_queue) | |
451 | { | |
452 | efx_free_special_buffer(tx_queue->efx, &tx_queue->txd); | |
453 | } | |
454 | ||
455 | /************************************************************************** | |
456 | * | |
457 | * RX path | |
458 | * | |
459 | **************************************************************************/ | |
460 | ||
461 | /* This creates an entry in the RX descriptor queue */ | |
462 | static inline void | |
463 | efx_farch_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index) | |
464 | { | |
465 | struct efx_rx_buffer *rx_buf; | |
466 | efx_qword_t *rxd; | |
467 | ||
468 | rxd = efx_rx_desc(rx_queue, index); | |
469 | rx_buf = efx_rx_buffer(rx_queue, index); | |
470 | EFX_POPULATE_QWORD_3(*rxd, | |
471 | FSF_AZ_RX_KER_BUF_SIZE, | |
472 | rx_buf->len - | |
473 | rx_queue->efx->type->rx_buffer_padding, | |
474 | FSF_AZ_RX_KER_BUF_REGION, 0, | |
475 | FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); | |
476 | } | |
477 | ||
478 | /* This writes to the RX_DESC_WPTR register for the specified receive | |
479 | * descriptor ring. | |
480 | */ | |
481 | void efx_farch_rx_write(struct efx_rx_queue *rx_queue) | |
482 | { | |
483 | struct efx_nic *efx = rx_queue->efx; | |
484 | efx_dword_t reg; | |
485 | unsigned write_ptr; | |
486 | ||
487 | while (rx_queue->notified_count != rx_queue->added_count) { | |
488 | efx_farch_build_rx_desc( | |
489 | rx_queue, | |
490 | rx_queue->notified_count & rx_queue->ptr_mask); | |
491 | ++rx_queue->notified_count; | |
492 | } | |
493 | ||
494 | wmb(); | |
495 | write_ptr = rx_queue->added_count & rx_queue->ptr_mask; | |
496 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); | |
497 | efx_writed_page(efx, ®, FR_AZ_RX_DESC_UPD_DWORD_P0, | |
498 | efx_rx_queue_index(rx_queue)); | |
499 | } | |
500 | ||
501 | int efx_farch_rx_probe(struct efx_rx_queue *rx_queue) | |
502 | { | |
503 | struct efx_nic *efx = rx_queue->efx; | |
504 | unsigned entries; | |
505 | ||
506 | entries = rx_queue->ptr_mask + 1; | |
507 | return efx_alloc_special_buffer(efx, &rx_queue->rxd, | |
508 | entries * sizeof(efx_qword_t)); | |
509 | } | |
510 | ||
511 | void efx_farch_rx_init(struct efx_rx_queue *rx_queue) | |
512 | { | |
513 | efx_oword_t rx_desc_ptr; | |
514 | struct efx_nic *efx = rx_queue->efx; | |
515 | bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0; | |
516 | bool iscsi_digest_en = is_b0; | |
517 | bool jumbo_en; | |
518 | ||
519 | /* For kernel-mode queues in Falcon A1, the JUMBO flag enables | |
520 | * DMA to continue after a PCIe page boundary (and scattering | |
521 | * is not possible). In Falcon B0 and Siena, it enables | |
522 | * scatter. | |
523 | */ | |
524 | jumbo_en = !is_b0 || efx->rx_scatter; | |
525 | ||
526 | netif_dbg(efx, hw, efx->net_dev, | |
527 | "RX queue %d ring in special buffers %d-%d\n", | |
528 | efx_rx_queue_index(rx_queue), rx_queue->rxd.index, | |
529 | rx_queue->rxd.index + rx_queue->rxd.entries - 1); | |
530 | ||
531 | rx_queue->scatter_n = 0; | |
532 | ||
533 | /* Pin RX descriptor ring */ | |
534 | efx_init_special_buffer(efx, &rx_queue->rxd); | |
535 | ||
536 | /* Push RX descriptor ring to card */ | |
537 | EFX_POPULATE_OWORD_10(rx_desc_ptr, | |
538 | FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en, | |
539 | FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en, | |
540 | FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, | |
541 | FRF_AZ_RX_DESCQ_EVQ_ID, | |
542 | efx_rx_queue_channel(rx_queue)->channel, | |
543 | FRF_AZ_RX_DESCQ_OWNER_ID, 0, | |
544 | FRF_AZ_RX_DESCQ_LABEL, | |
545 | efx_rx_queue_index(rx_queue), | |
546 | FRF_AZ_RX_DESCQ_SIZE, | |
547 | __ffs(rx_queue->rxd.entries), | |
548 | FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ , | |
549 | FRF_AZ_RX_DESCQ_JUMBO, jumbo_en, | |
550 | FRF_AZ_RX_DESCQ_EN, 1); | |
551 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, | |
552 | efx_rx_queue_index(rx_queue)); | |
553 | } | |
554 | ||
555 | static void efx_farch_flush_rx_queue(struct efx_rx_queue *rx_queue) | |
556 | { | |
557 | struct efx_nic *efx = rx_queue->efx; | |
558 | efx_oword_t rx_flush_descq; | |
559 | ||
560 | EFX_POPULATE_OWORD_2(rx_flush_descq, | |
561 | FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, | |
562 | FRF_AZ_RX_FLUSH_DESCQ, | |
563 | efx_rx_queue_index(rx_queue)); | |
564 | efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ); | |
565 | } | |
566 | ||
567 | void efx_farch_rx_fini(struct efx_rx_queue *rx_queue) | |
568 | { | |
569 | efx_oword_t rx_desc_ptr; | |
570 | struct efx_nic *efx = rx_queue->efx; | |
571 | ||
572 | /* Remove RX descriptor ring from card */ | |
573 | EFX_ZERO_OWORD(rx_desc_ptr); | |
574 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, | |
575 | efx_rx_queue_index(rx_queue)); | |
576 | ||
577 | /* Unpin RX descriptor ring */ | |
578 | efx_fini_special_buffer(efx, &rx_queue->rxd); | |
579 | } | |
580 | ||
581 | /* Free buffers backing RX queue */ | |
582 | void efx_farch_rx_remove(struct efx_rx_queue *rx_queue) | |
583 | { | |
584 | efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd); | |
585 | } | |
586 | ||
587 | /************************************************************************** | |
588 | * | |
589 | * Flush handling | |
590 | * | |
591 | **************************************************************************/ | |
592 | ||
593 | /* efx_farch_flush_queues() must be woken up when all flushes are completed, | |
594 | * or more RX flushes can be kicked off. | |
595 | */ | |
596 | static bool efx_farch_flush_wake(struct efx_nic *efx) | |
597 | { | |
598 | /* Ensure that all updates are visible to efx_farch_flush_queues() */ | |
599 | smp_mb(); | |
600 | ||
3881d8ab | 601 | return (atomic_read(&efx->active_queues) == 0 || |
86094f7f BH |
602 | (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT |
603 | && atomic_read(&efx->rxq_flush_pending) > 0)); | |
604 | } | |
605 | ||
606 | static bool efx_check_tx_flush_complete(struct efx_nic *efx) | |
607 | { | |
608 | bool i = true; | |
609 | efx_oword_t txd_ptr_tbl; | |
610 | struct efx_channel *channel; | |
611 | struct efx_tx_queue *tx_queue; | |
612 | ||
613 | efx_for_each_channel(channel, efx) { | |
614 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
615 | efx_reado_table(efx, &txd_ptr_tbl, | |
616 | FR_BZ_TX_DESC_PTR_TBL, tx_queue->queue); | |
617 | if (EFX_OWORD_FIELD(txd_ptr_tbl, | |
618 | FRF_AZ_TX_DESCQ_FLUSH) || | |
619 | EFX_OWORD_FIELD(txd_ptr_tbl, | |
620 | FRF_AZ_TX_DESCQ_EN)) { | |
621 | netif_dbg(efx, hw, efx->net_dev, | |
622 | "flush did not complete on TXQ %d\n", | |
623 | tx_queue->queue); | |
624 | i = false; | |
625 | } else if (atomic_cmpxchg(&tx_queue->flush_outstanding, | |
626 | 1, 0)) { | |
627 | /* The flush is complete, but we didn't | |
628 | * receive a flush completion event | |
629 | */ | |
630 | netif_dbg(efx, hw, efx->net_dev, | |
631 | "flush complete on TXQ %d, so drain " | |
632 | "the queue\n", tx_queue->queue); | |
3881d8ab | 633 | /* Don't need to increment active_queues as it |
86094f7f BH |
634 | * has already been incremented for the queues |
635 | * which did not drain | |
636 | */ | |
637 | efx_farch_magic_event(channel, | |
638 | EFX_CHANNEL_MAGIC_TX_DRAIN( | |
639 | tx_queue)); | |
640 | } | |
641 | } | |
642 | } | |
643 | ||
644 | return i; | |
645 | } | |
646 | ||
647 | /* Flush all the transmit queues, and continue flushing receive queues until | |
648 | * they're all flushed. Wait for the DRAIN events to be recieved so that there | |
649 | * are no more RX and TX events left on any channel. */ | |
650 | static int efx_farch_do_flush(struct efx_nic *efx) | |
651 | { | |
652 | unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */ | |
653 | struct efx_channel *channel; | |
654 | struct efx_rx_queue *rx_queue; | |
655 | struct efx_tx_queue *tx_queue; | |
656 | int rc = 0; | |
657 | ||
658 | efx_for_each_channel(channel, efx) { | |
659 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
86094f7f BH |
660 | efx_farch_flush_tx_queue(tx_queue); |
661 | } | |
662 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
86094f7f BH |
663 | rx_queue->flush_pending = true; |
664 | atomic_inc(&efx->rxq_flush_pending); | |
665 | } | |
666 | } | |
667 | ||
3881d8ab | 668 | while (timeout && atomic_read(&efx->active_queues) > 0) { |
86094f7f BH |
669 | /* If SRIOV is enabled, then offload receive queue flushing to |
670 | * the firmware (though we will still have to poll for | |
671 | * completion). If that fails, fall back to the old scheme. | |
672 | */ | |
327c685e | 673 | if (efx_siena_sriov_enabled(efx)) { |
86094f7f BH |
674 | rc = efx_mcdi_flush_rxqs(efx); |
675 | if (!rc) | |
676 | goto wait; | |
677 | } | |
678 | ||
679 | /* The hardware supports four concurrent rx flushes, each of | |
680 | * which may need to be retried if there is an outstanding | |
681 | * descriptor fetch | |
682 | */ | |
683 | efx_for_each_channel(channel, efx) { | |
684 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
685 | if (atomic_read(&efx->rxq_flush_outstanding) >= | |
686 | EFX_RX_FLUSH_COUNT) | |
687 | break; | |
688 | ||
689 | if (rx_queue->flush_pending) { | |
690 | rx_queue->flush_pending = false; | |
691 | atomic_dec(&efx->rxq_flush_pending); | |
692 | atomic_inc(&efx->rxq_flush_outstanding); | |
693 | efx_farch_flush_rx_queue(rx_queue); | |
694 | } | |
695 | } | |
696 | } | |
697 | ||
698 | wait: | |
699 | timeout = wait_event_timeout(efx->flush_wq, | |
700 | efx_farch_flush_wake(efx), | |
701 | timeout); | |
702 | } | |
703 | ||
3881d8ab | 704 | if (atomic_read(&efx->active_queues) && |
86094f7f BH |
705 | !efx_check_tx_flush_complete(efx)) { |
706 | netif_err(efx, hw, efx->net_dev, "failed to flush %d queues " | |
3881d8ab | 707 | "(rx %d+%d)\n", atomic_read(&efx->active_queues), |
86094f7f BH |
708 | atomic_read(&efx->rxq_flush_outstanding), |
709 | atomic_read(&efx->rxq_flush_pending)); | |
710 | rc = -ETIMEDOUT; | |
711 | ||
3881d8ab | 712 | atomic_set(&efx->active_queues, 0); |
86094f7f BH |
713 | atomic_set(&efx->rxq_flush_pending, 0); |
714 | atomic_set(&efx->rxq_flush_outstanding, 0); | |
715 | } | |
716 | ||
717 | return rc; | |
718 | } | |
719 | ||
720 | int efx_farch_fini_dmaq(struct efx_nic *efx) | |
721 | { | |
722 | struct efx_channel *channel; | |
723 | struct efx_tx_queue *tx_queue; | |
724 | struct efx_rx_queue *rx_queue; | |
725 | int rc = 0; | |
726 | ||
727 | /* Do not attempt to write to the NIC during EEH recovery */ | |
728 | if (efx->state != STATE_RECOVERY) { | |
729 | /* Only perform flush if DMA is enabled */ | |
730 | if (efx->pci_dev->is_busmaster) { | |
731 | efx->type->prepare_flush(efx); | |
732 | rc = efx_farch_do_flush(efx); | |
733 | efx->type->finish_flush(efx); | |
734 | } | |
735 | ||
736 | efx_for_each_channel(channel, efx) { | |
737 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
738 | efx_farch_rx_fini(rx_queue); | |
739 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
740 | efx_farch_tx_fini(tx_queue); | |
741 | } | |
742 | } | |
743 | ||
744 | return rc; | |
745 | } | |
746 | ||
e283546c EC |
747 | /* Reset queue and flush accounting after FLR |
748 | * | |
749 | * One possible cause of FLR recovery is that DMA may be failing (eg. if bus | |
750 | * mastering was disabled), in which case we don't receive (RXQ) flush | |
751 | * completion events. This means that efx->rxq_flush_outstanding remained at 4 | |
752 | * after the FLR; also, efx->active_queues was non-zero (as no flush completion | |
753 | * events were received, and we didn't go through efx_check_tx_flush_complete()) | |
754 | * If we don't fix this up, on the next call to efx_realloc_channels() we won't | |
755 | * flush any RX queues because efx->rxq_flush_outstanding is at the limit of 4 | |
756 | * for batched flush requests; and the efx->active_queues gets messed up because | |
757 | * we keep incrementing for the newly initialised queues, but it never went to | |
758 | * zero previously. Then we get a timeout every time we try to restart the | |
759 | * queues, as it doesn't go back to zero when we should be flushing the queues. | |
760 | */ | |
761 | void efx_farch_finish_flr(struct efx_nic *efx) | |
762 | { | |
763 | atomic_set(&efx->rxq_flush_pending, 0); | |
764 | atomic_set(&efx->rxq_flush_outstanding, 0); | |
765 | atomic_set(&efx->active_queues, 0); | |
766 | } | |
767 | ||
768 | ||
86094f7f BH |
769 | /************************************************************************** |
770 | * | |
771 | * Event queue processing | |
772 | * Event queues are processed by per-channel tasklets. | |
773 | * | |
774 | **************************************************************************/ | |
775 | ||
776 | /* Update a channel's event queue's read pointer (RPTR) register | |
777 | * | |
778 | * This writes the EVQ_RPTR_REG register for the specified channel's | |
779 | * event queue. | |
780 | */ | |
781 | void efx_farch_ev_read_ack(struct efx_channel *channel) | |
782 | { | |
783 | efx_dword_t reg; | |
784 | struct efx_nic *efx = channel->efx; | |
785 | ||
786 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, | |
787 | channel->eventq_read_ptr & channel->eventq_mask); | |
788 | ||
789 | /* For Falcon A1, EVQ_RPTR_KER is documented as having a step size | |
790 | * of 4 bytes, but it is really 16 bytes just like later revisions. | |
791 | */ | |
792 | efx_writed(efx, ®, | |
793 | efx->type->evq_rptr_tbl_base + | |
794 | FR_BZ_EVQ_RPTR_STEP * channel->channel); | |
795 | } | |
796 | ||
797 | /* Use HW to insert a SW defined event */ | |
798 | void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq, | |
799 | efx_qword_t *event) | |
800 | { | |
801 | efx_oword_t drv_ev_reg; | |
802 | ||
803 | BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 || | |
804 | FRF_AZ_DRV_EV_DATA_WIDTH != 64); | |
805 | drv_ev_reg.u32[0] = event->u32[0]; | |
806 | drv_ev_reg.u32[1] = event->u32[1]; | |
807 | drv_ev_reg.u32[2] = 0; | |
808 | drv_ev_reg.u32[3] = 0; | |
809 | EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq); | |
810 | efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV); | |
811 | } | |
812 | ||
813 | static void efx_farch_magic_event(struct efx_channel *channel, u32 magic) | |
814 | { | |
815 | efx_qword_t event; | |
816 | ||
817 | EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE, | |
818 | FSE_AZ_EV_CODE_DRV_GEN_EV, | |
819 | FSF_AZ_DRV_GEN_EV_MAGIC, magic); | |
820 | efx_farch_generate_event(channel->efx, channel->channel, &event); | |
821 | } | |
822 | ||
823 | /* Handle a transmit completion event | |
824 | * | |
825 | * The NIC batches TX completion events; the message we receive is of | |
826 | * the form "complete all TX events up to this index". | |
827 | */ | |
828 | static int | |
829 | efx_farch_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) | |
830 | { | |
831 | unsigned int tx_ev_desc_ptr; | |
832 | unsigned int tx_ev_q_label; | |
833 | struct efx_tx_queue *tx_queue; | |
834 | struct efx_nic *efx = channel->efx; | |
835 | int tx_packets = 0; | |
836 | ||
837 | if (unlikely(ACCESS_ONCE(efx->reset_pending))) | |
838 | return 0; | |
839 | ||
840 | if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { | |
841 | /* Transmit completion */ | |
842 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); | |
843 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); | |
844 | tx_queue = efx_channel_get_tx_queue( | |
845 | channel, tx_ev_q_label % EFX_TXQ_TYPES); | |
846 | tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) & | |
847 | tx_queue->ptr_mask); | |
848 | efx_xmit_done(tx_queue, tx_ev_desc_ptr); | |
849 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { | |
850 | /* Rewrite the FIFO write pointer */ | |
851 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); | |
852 | tx_queue = efx_channel_get_tx_queue( | |
853 | channel, tx_ev_q_label % EFX_TXQ_TYPES); | |
854 | ||
855 | netif_tx_lock(efx->net_dev); | |
856 | efx_farch_notify_tx_desc(tx_queue); | |
857 | netif_tx_unlock(efx->net_dev); | |
ab3b8250 | 858 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR)) { |
3de82b91 | 859 | efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR); |
86094f7f BH |
860 | } else { |
861 | netif_err(efx, tx_err, efx->net_dev, | |
862 | "channel %d unexpected TX event " | |
863 | EFX_QWORD_FMT"\n", channel->channel, | |
864 | EFX_QWORD_VAL(*event)); | |
865 | } | |
866 | ||
867 | return tx_packets; | |
868 | } | |
869 | ||
870 | /* Detect errors included in the rx_evt_pkt_ok bit. */ | |
871 | static u16 efx_farch_handle_rx_not_ok(struct efx_rx_queue *rx_queue, | |
872 | const efx_qword_t *event) | |
873 | { | |
874 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); | |
875 | struct efx_nic *efx = rx_queue->efx; | |
876 | bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err; | |
877 | bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err; | |
878 | bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc; | |
879 | bool rx_ev_other_err, rx_ev_pause_frm; | |
880 | bool rx_ev_hdr_type, rx_ev_mcast_pkt; | |
881 | unsigned rx_ev_pkt_type; | |
882 | ||
883 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); | |
884 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); | |
885 | rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC); | |
886 | rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE); | |
887 | rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, | |
888 | FSF_AZ_RX_EV_BUF_OWNER_ID_ERR); | |
889 | rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, | |
890 | FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR); | |
891 | rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, | |
892 | FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR); | |
893 | rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR); | |
894 | rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC); | |
895 | rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ? | |
896 | 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB)); | |
897 | rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR); | |
898 | ||
899 | /* Every error apart from tobe_disc and pause_frm */ | |
900 | rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | | |
901 | rx_ev_buf_owner_id_err | rx_ev_eth_crc_err | | |
902 | rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err); | |
903 | ||
904 | /* Count errors that are not in MAC stats. Ignore expected | |
905 | * checksum errors during self-test. */ | |
906 | if (rx_ev_frm_trunc) | |
907 | ++channel->n_rx_frm_trunc; | |
908 | else if (rx_ev_tobe_disc) | |
909 | ++channel->n_rx_tobe_disc; | |
910 | else if (!efx->loopback_selftest) { | |
911 | if (rx_ev_ip_hdr_chksum_err) | |
912 | ++channel->n_rx_ip_hdr_chksum_err; | |
913 | else if (rx_ev_tcp_udp_chksum_err) | |
914 | ++channel->n_rx_tcp_udp_chksum_err; | |
915 | } | |
916 | ||
917 | /* TOBE_DISC is expected on unicast mismatches; don't print out an | |
918 | * error message. FRM_TRUNC indicates RXDP dropped the packet due | |
919 | * to a FIFO overflow. | |
920 | */ | |
921 | #ifdef DEBUG | |
922 | if (rx_ev_other_err && net_ratelimit()) { | |
923 | netif_dbg(efx, rx_err, efx->net_dev, | |
924 | " RX queue %d unexpected RX event " | |
925 | EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n", | |
926 | efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event), | |
927 | rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "", | |
928 | rx_ev_ip_hdr_chksum_err ? | |
929 | " [IP_HDR_CHKSUM_ERR]" : "", | |
930 | rx_ev_tcp_udp_chksum_err ? | |
931 | " [TCP_UDP_CHKSUM_ERR]" : "", | |
932 | rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "", | |
933 | rx_ev_frm_trunc ? " [FRM_TRUNC]" : "", | |
934 | rx_ev_drib_nib ? " [DRIB_NIB]" : "", | |
935 | rx_ev_tobe_disc ? " [TOBE_DISC]" : "", | |
936 | rx_ev_pause_frm ? " [PAUSE]" : ""); | |
937 | } | |
938 | #endif | |
939 | ||
940 | /* The frame must be discarded if any of these are true. */ | |
941 | return (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib | | |
942 | rx_ev_tobe_disc | rx_ev_pause_frm) ? | |
943 | EFX_RX_PKT_DISCARD : 0; | |
944 | } | |
945 | ||
946 | /* Handle receive events that are not in-order. Return true if this | |
947 | * can be handled as a partial packet discard, false if it's more | |
948 | * serious. | |
949 | */ | |
950 | static bool | |
951 | efx_farch_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index) | |
952 | { | |
953 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); | |
954 | struct efx_nic *efx = rx_queue->efx; | |
955 | unsigned expected, dropped; | |
956 | ||
957 | if (rx_queue->scatter_n && | |
958 | index == ((rx_queue->removed_count + rx_queue->scatter_n - 1) & | |
959 | rx_queue->ptr_mask)) { | |
960 | ++channel->n_rx_nodesc_trunc; | |
961 | return true; | |
962 | } | |
963 | ||
964 | expected = rx_queue->removed_count & rx_queue->ptr_mask; | |
965 | dropped = (index - expected) & rx_queue->ptr_mask; | |
966 | netif_info(efx, rx_err, efx->net_dev, | |
967 | "dropped %d events (index=%d expected=%d)\n", | |
968 | dropped, index, expected); | |
969 | ||
970 | efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ? | |
971 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
972 | return false; | |
973 | } | |
974 | ||
975 | /* Handle a packet received event | |
976 | * | |
977 | * The NIC gives a "discard" flag if it's a unicast packet with the | |
978 | * wrong destination address | |
979 | * Also "is multicast" and "matches multicast filter" flags can be used to | |
980 | * discard non-matching multicast packets. | |
981 | */ | |
982 | static void | |
983 | efx_farch_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event) | |
984 | { | |
985 | unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt; | |
986 | unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt; | |
987 | unsigned expected_ptr; | |
988 | bool rx_ev_pkt_ok, rx_ev_sop, rx_ev_cont; | |
989 | u16 flags; | |
990 | struct efx_rx_queue *rx_queue; | |
991 | struct efx_nic *efx = channel->efx; | |
992 | ||
993 | if (unlikely(ACCESS_ONCE(efx->reset_pending))) | |
994 | return; | |
995 | ||
996 | rx_ev_cont = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT); | |
997 | rx_ev_sop = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP); | |
998 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) != | |
999 | channel->channel); | |
1000 | ||
1001 | rx_queue = efx_channel_get_rx_queue(channel); | |
1002 | ||
1003 | rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR); | |
1004 | expected_ptr = ((rx_queue->removed_count + rx_queue->scatter_n) & | |
1005 | rx_queue->ptr_mask); | |
1006 | ||
1007 | /* Check for partial drops and other errors */ | |
1008 | if (unlikely(rx_ev_desc_ptr != expected_ptr) || | |
1009 | unlikely(rx_ev_sop != (rx_queue->scatter_n == 0))) { | |
1010 | if (rx_ev_desc_ptr != expected_ptr && | |
1011 | !efx_farch_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr)) | |
1012 | return; | |
1013 | ||
1014 | /* Discard all pending fragments */ | |
1015 | if (rx_queue->scatter_n) { | |
1016 | efx_rx_packet( | |
1017 | rx_queue, | |
1018 | rx_queue->removed_count & rx_queue->ptr_mask, | |
1019 | rx_queue->scatter_n, 0, EFX_RX_PKT_DISCARD); | |
1020 | rx_queue->removed_count += rx_queue->scatter_n; | |
1021 | rx_queue->scatter_n = 0; | |
1022 | } | |
1023 | ||
1024 | /* Return if there is no new fragment */ | |
1025 | if (rx_ev_desc_ptr != expected_ptr) | |
1026 | return; | |
1027 | ||
1028 | /* Discard new fragment if not SOP */ | |
1029 | if (!rx_ev_sop) { | |
1030 | efx_rx_packet( | |
1031 | rx_queue, | |
1032 | rx_queue->removed_count & rx_queue->ptr_mask, | |
1033 | 1, 0, EFX_RX_PKT_DISCARD); | |
1034 | ++rx_queue->removed_count; | |
1035 | return; | |
1036 | } | |
1037 | } | |
1038 | ||
1039 | ++rx_queue->scatter_n; | |
1040 | if (rx_ev_cont) | |
1041 | return; | |
1042 | ||
1043 | rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT); | |
1044 | rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK); | |
1045 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); | |
1046 | ||
1047 | if (likely(rx_ev_pkt_ok)) { | |
1048 | /* If packet is marked as OK then we can rely on the | |
1049 | * hardware checksum and classification. | |
1050 | */ | |
1051 | flags = 0; | |
1052 | switch (rx_ev_hdr_type) { | |
1053 | case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP: | |
1054 | flags |= EFX_RX_PKT_TCP; | |
1055 | /* fall through */ | |
1056 | case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP: | |
1057 | flags |= EFX_RX_PKT_CSUMMED; | |
1058 | /* fall through */ | |
1059 | case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER: | |
1060 | case FSE_AZ_RX_EV_HDR_TYPE_OTHER: | |
1061 | break; | |
1062 | } | |
1063 | } else { | |
1064 | flags = efx_farch_handle_rx_not_ok(rx_queue, event); | |
1065 | } | |
1066 | ||
1067 | /* Detect multicast packets that didn't match the filter */ | |
1068 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); | |
1069 | if (rx_ev_mcast_pkt) { | |
1070 | unsigned int rx_ev_mcast_hash_match = | |
1071 | EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH); | |
1072 | ||
1073 | if (unlikely(!rx_ev_mcast_hash_match)) { | |
1074 | ++channel->n_rx_mcast_mismatch; | |
1075 | flags |= EFX_RX_PKT_DISCARD; | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | channel->irq_mod_score += 2; | |
1080 | ||
1081 | /* Handle received packet */ | |
1082 | efx_rx_packet(rx_queue, | |
1083 | rx_queue->removed_count & rx_queue->ptr_mask, | |
1084 | rx_queue->scatter_n, rx_ev_byte_cnt, flags); | |
1085 | rx_queue->removed_count += rx_queue->scatter_n; | |
1086 | rx_queue->scatter_n = 0; | |
1087 | } | |
1088 | ||
1089 | /* If this flush done event corresponds to a &struct efx_tx_queue, then | |
1090 | * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue | |
1091 | * of all transmit completions. | |
1092 | */ | |
1093 | static void | |
1094 | efx_farch_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event) | |
1095 | { | |
1096 | struct efx_tx_queue *tx_queue; | |
1097 | int qid; | |
1098 | ||
1099 | qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); | |
1100 | if (qid < EFX_TXQ_TYPES * efx->n_tx_channels) { | |
1101 | tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES, | |
1102 | qid % EFX_TXQ_TYPES); | |
1103 | if (atomic_cmpxchg(&tx_queue->flush_outstanding, 1, 0)) { | |
1104 | efx_farch_magic_event(tx_queue->channel, | |
1105 | EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue)); | |
1106 | } | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | /* If this flush done event corresponds to a &struct efx_rx_queue: If the flush | |
1111 | * was succesful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add | |
1112 | * the RX queue back to the mask of RX queues in need of flushing. | |
1113 | */ | |
1114 | static void | |
1115 | efx_farch_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event) | |
1116 | { | |
1117 | struct efx_channel *channel; | |
1118 | struct efx_rx_queue *rx_queue; | |
1119 | int qid; | |
1120 | bool failed; | |
1121 | ||
1122 | qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); | |
1123 | failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); | |
1124 | if (qid >= efx->n_channels) | |
1125 | return; | |
1126 | channel = efx_get_channel(efx, qid); | |
1127 | if (!efx_channel_has_rx_queue(channel)) | |
1128 | return; | |
1129 | rx_queue = efx_channel_get_rx_queue(channel); | |
1130 | ||
1131 | if (failed) { | |
1132 | netif_info(efx, hw, efx->net_dev, | |
1133 | "RXQ %d flush retry\n", qid); | |
1134 | rx_queue->flush_pending = true; | |
1135 | atomic_inc(&efx->rxq_flush_pending); | |
1136 | } else { | |
1137 | efx_farch_magic_event(efx_rx_queue_channel(rx_queue), | |
1138 | EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)); | |
1139 | } | |
1140 | atomic_dec(&efx->rxq_flush_outstanding); | |
1141 | if (efx_farch_flush_wake(efx)) | |
1142 | wake_up(&efx->flush_wq); | |
1143 | } | |
1144 | ||
1145 | static void | |
1146 | efx_farch_handle_drain_event(struct efx_channel *channel) | |
1147 | { | |
1148 | struct efx_nic *efx = channel->efx; | |
1149 | ||
3881d8ab AR |
1150 | WARN_ON(atomic_read(&efx->active_queues) == 0); |
1151 | atomic_dec(&efx->active_queues); | |
86094f7f BH |
1152 | if (efx_farch_flush_wake(efx)) |
1153 | wake_up(&efx->flush_wq); | |
1154 | } | |
1155 | ||
1156 | static void efx_farch_handle_generated_event(struct efx_channel *channel, | |
1157 | efx_qword_t *event) | |
1158 | { | |
1159 | struct efx_nic *efx = channel->efx; | |
1160 | struct efx_rx_queue *rx_queue = | |
1161 | efx_channel_has_rx_queue(channel) ? | |
1162 | efx_channel_get_rx_queue(channel) : NULL; | |
1163 | unsigned magic, code; | |
1164 | ||
1165 | magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC); | |
1166 | code = _EFX_CHANNEL_MAGIC_CODE(magic); | |
1167 | ||
1168 | if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) { | |
1169 | channel->event_test_cpu = raw_smp_processor_id(); | |
1170 | } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) { | |
1171 | /* The queue must be empty, so we won't receive any rx | |
1172 | * events, so efx_process_channel() won't refill the | |
1173 | * queue. Refill it here */ | |
cce28794 | 1174 | efx_fast_push_rx_descriptors(rx_queue, true); |
86094f7f BH |
1175 | } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) { |
1176 | efx_farch_handle_drain_event(channel); | |
1177 | } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) { | |
1178 | efx_farch_handle_drain_event(channel); | |
1179 | } else { | |
1180 | netif_dbg(efx, hw, efx->net_dev, "channel %d received " | |
1181 | "generated event "EFX_QWORD_FMT"\n", | |
1182 | channel->channel, EFX_QWORD_VAL(*event)); | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | static void | |
1187 | efx_farch_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) | |
1188 | { | |
1189 | struct efx_nic *efx = channel->efx; | |
1190 | unsigned int ev_sub_code; | |
1191 | unsigned int ev_sub_data; | |
1192 | ||
1193 | ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE); | |
1194 | ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); | |
1195 | ||
1196 | switch (ev_sub_code) { | |
1197 | case FSE_AZ_TX_DESCQ_FLS_DONE_EV: | |
1198 | netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n", | |
1199 | channel->channel, ev_sub_data); | |
1200 | efx_farch_handle_tx_flush_done(efx, event); | |
327c685e | 1201 | efx_siena_sriov_tx_flush_done(efx, event); |
86094f7f BH |
1202 | break; |
1203 | case FSE_AZ_RX_DESCQ_FLS_DONE_EV: | |
1204 | netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n", | |
1205 | channel->channel, ev_sub_data); | |
1206 | efx_farch_handle_rx_flush_done(efx, event); | |
327c685e | 1207 | efx_siena_sriov_rx_flush_done(efx, event); |
86094f7f BH |
1208 | break; |
1209 | case FSE_AZ_EVQ_INIT_DONE_EV: | |
1210 | netif_dbg(efx, hw, efx->net_dev, | |
1211 | "channel %d EVQ %d initialised\n", | |
1212 | channel->channel, ev_sub_data); | |
1213 | break; | |
1214 | case FSE_AZ_SRM_UPD_DONE_EV: | |
1215 | netif_vdbg(efx, hw, efx->net_dev, | |
1216 | "channel %d SRAM update done\n", channel->channel); | |
1217 | break; | |
1218 | case FSE_AZ_WAKE_UP_EV: | |
1219 | netif_vdbg(efx, hw, efx->net_dev, | |
1220 | "channel %d RXQ %d wakeup event\n", | |
1221 | channel->channel, ev_sub_data); | |
1222 | break; | |
1223 | case FSE_AZ_TIMER_EV: | |
1224 | netif_vdbg(efx, hw, efx->net_dev, | |
1225 | "channel %d RX queue %d timer expired\n", | |
1226 | channel->channel, ev_sub_data); | |
1227 | break; | |
1228 | case FSE_AA_RX_RECOVER_EV: | |
1229 | netif_err(efx, rx_err, efx->net_dev, | |
1230 | "channel %d seen DRIVER RX_RESET event. " | |
1231 | "Resetting.\n", channel->channel); | |
1232 | atomic_inc(&efx->rx_reset); | |
1233 | efx_schedule_reset(efx, | |
1234 | EFX_WORKAROUND_6555(efx) ? | |
1235 | RESET_TYPE_RX_RECOVERY : | |
1236 | RESET_TYPE_DISABLE); | |
1237 | break; | |
1238 | case FSE_BZ_RX_DSC_ERROR_EV: | |
1239 | if (ev_sub_data < EFX_VI_BASE) { | |
1240 | netif_err(efx, rx_err, efx->net_dev, | |
1241 | "RX DMA Q %d reports descriptor fetch error." | |
1242 | " RX Q %d is disabled.\n", ev_sub_data, | |
1243 | ev_sub_data); | |
3de82b91 | 1244 | efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR); |
86094f7f | 1245 | } else |
327c685e | 1246 | efx_siena_sriov_desc_fetch_err(efx, ev_sub_data); |
86094f7f BH |
1247 | break; |
1248 | case FSE_BZ_TX_DSC_ERROR_EV: | |
1249 | if (ev_sub_data < EFX_VI_BASE) { | |
1250 | netif_err(efx, tx_err, efx->net_dev, | |
1251 | "TX DMA Q %d reports descriptor fetch error." | |
1252 | " TX Q %d is disabled.\n", ev_sub_data, | |
1253 | ev_sub_data); | |
3de82b91 | 1254 | efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR); |
86094f7f | 1255 | } else |
327c685e | 1256 | efx_siena_sriov_desc_fetch_err(efx, ev_sub_data); |
86094f7f BH |
1257 | break; |
1258 | default: | |
1259 | netif_vdbg(efx, hw, efx->net_dev, | |
1260 | "channel %d unknown driver event code %d " | |
1261 | "data %04x\n", channel->channel, ev_sub_code, | |
1262 | ev_sub_data); | |
1263 | break; | |
1264 | } | |
1265 | } | |
1266 | ||
1267 | int efx_farch_ev_process(struct efx_channel *channel, int budget) | |
1268 | { | |
1269 | struct efx_nic *efx = channel->efx; | |
1270 | unsigned int read_ptr; | |
1271 | efx_qword_t event, *p_event; | |
1272 | int ev_code; | |
1273 | int tx_packets = 0; | |
1274 | int spent = 0; | |
1275 | ||
75363a46 EB |
1276 | if (budget <= 0) |
1277 | return spent; | |
1278 | ||
86094f7f BH |
1279 | read_ptr = channel->eventq_read_ptr; |
1280 | ||
1281 | for (;;) { | |
1282 | p_event = efx_event(channel, read_ptr); | |
1283 | event = *p_event; | |
1284 | ||
1285 | if (!efx_event_present(&event)) | |
1286 | /* End of events */ | |
1287 | break; | |
1288 | ||
1289 | netif_vdbg(channel->efx, intr, channel->efx->net_dev, | |
1290 | "channel %d event is "EFX_QWORD_FMT"\n", | |
1291 | channel->channel, EFX_QWORD_VAL(event)); | |
1292 | ||
1293 | /* Clear this event by marking it all ones */ | |
1294 | EFX_SET_QWORD(*p_event); | |
1295 | ||
1296 | ++read_ptr; | |
1297 | ||
1298 | ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); | |
1299 | ||
1300 | switch (ev_code) { | |
1301 | case FSE_AZ_EV_CODE_RX_EV: | |
1302 | efx_farch_handle_rx_event(channel, &event); | |
1303 | if (++spent == budget) | |
1304 | goto out; | |
1305 | break; | |
1306 | case FSE_AZ_EV_CODE_TX_EV: | |
1307 | tx_packets += efx_farch_handle_tx_event(channel, | |
1308 | &event); | |
1309 | if (tx_packets > efx->txq_entries) { | |
1310 | spent = budget; | |
1311 | goto out; | |
1312 | } | |
1313 | break; | |
1314 | case FSE_AZ_EV_CODE_DRV_GEN_EV: | |
1315 | efx_farch_handle_generated_event(channel, &event); | |
1316 | break; | |
1317 | case FSE_AZ_EV_CODE_DRIVER_EV: | |
1318 | efx_farch_handle_driver_event(channel, &event); | |
1319 | break; | |
1320 | case FSE_CZ_EV_CODE_USER_EV: | |
327c685e | 1321 | efx_siena_sriov_event(channel, &event); |
86094f7f BH |
1322 | break; |
1323 | case FSE_CZ_EV_CODE_MCDI_EV: | |
1324 | efx_mcdi_process_event(channel, &event); | |
1325 | break; | |
1326 | case FSE_AZ_EV_CODE_GLOBAL_EV: | |
1327 | if (efx->type->handle_global_event && | |
1328 | efx->type->handle_global_event(channel, &event)) | |
1329 | break; | |
1330 | /* else fall through */ | |
1331 | default: | |
1332 | netif_err(channel->efx, hw, channel->efx->net_dev, | |
1333 | "channel %d unknown event type %d (data " | |
1334 | EFX_QWORD_FMT ")\n", channel->channel, | |
1335 | ev_code, EFX_QWORD_VAL(event)); | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | out: | |
1340 | channel->eventq_read_ptr = read_ptr; | |
1341 | return spent; | |
1342 | } | |
1343 | ||
1344 | /* Allocate buffer table entries for event queue */ | |
1345 | int efx_farch_ev_probe(struct efx_channel *channel) | |
1346 | { | |
1347 | struct efx_nic *efx = channel->efx; | |
1348 | unsigned entries; | |
1349 | ||
1350 | entries = channel->eventq_mask + 1; | |
1351 | return efx_alloc_special_buffer(efx, &channel->eventq, | |
1352 | entries * sizeof(efx_qword_t)); | |
1353 | } | |
1354 | ||
261e4d96 | 1355 | int efx_farch_ev_init(struct efx_channel *channel) |
86094f7f BH |
1356 | { |
1357 | efx_oword_t reg; | |
1358 | struct efx_nic *efx = channel->efx; | |
1359 | ||
1360 | netif_dbg(efx, hw, efx->net_dev, | |
1361 | "channel %d event queue in special buffers %d-%d\n", | |
1362 | channel->channel, channel->eventq.index, | |
1363 | channel->eventq.index + channel->eventq.entries - 1); | |
1364 | ||
1365 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { | |
1366 | EFX_POPULATE_OWORD_3(reg, | |
1367 | FRF_CZ_TIMER_Q_EN, 1, | |
1368 | FRF_CZ_HOST_NOTIFY_MODE, 0, | |
1369 | FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS); | |
1370 | efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel); | |
1371 | } | |
1372 | ||
1373 | /* Pin event queue buffer */ | |
1374 | efx_init_special_buffer(efx, &channel->eventq); | |
1375 | ||
1376 | /* Fill event queue with all ones (i.e. empty events) */ | |
1377 | memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); | |
1378 | ||
1379 | /* Push event queue to card */ | |
1380 | EFX_POPULATE_OWORD_3(reg, | |
1381 | FRF_AZ_EVQ_EN, 1, | |
1382 | FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries), | |
1383 | FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index); | |
1384 | efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, | |
1385 | channel->channel); | |
1386 | ||
261e4d96 | 1387 | return 0; |
86094f7f BH |
1388 | } |
1389 | ||
1390 | void efx_farch_ev_fini(struct efx_channel *channel) | |
1391 | { | |
1392 | efx_oword_t reg; | |
1393 | struct efx_nic *efx = channel->efx; | |
1394 | ||
1395 | /* Remove event queue from card */ | |
1396 | EFX_ZERO_OWORD(reg); | |
1397 | efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, | |
1398 | channel->channel); | |
1399 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) | |
1400 | efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel); | |
1401 | ||
1402 | /* Unpin event queue */ | |
1403 | efx_fini_special_buffer(efx, &channel->eventq); | |
1404 | } | |
1405 | ||
1406 | /* Free buffers backing event queue */ | |
1407 | void efx_farch_ev_remove(struct efx_channel *channel) | |
1408 | { | |
1409 | efx_free_special_buffer(channel->efx, &channel->eventq); | |
1410 | } | |
1411 | ||
1412 | ||
1413 | void efx_farch_ev_test_generate(struct efx_channel *channel) | |
1414 | { | |
1415 | efx_farch_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel)); | |
1416 | } | |
1417 | ||
1418 | void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue) | |
1419 | { | |
1420 | efx_farch_magic_event(efx_rx_queue_channel(rx_queue), | |
1421 | EFX_CHANNEL_MAGIC_FILL(rx_queue)); | |
1422 | } | |
1423 | ||
1424 | /************************************************************************** | |
1425 | * | |
1426 | * Hardware interrupts | |
1427 | * The hardware interrupt handler does very little work; all the event | |
1428 | * queue processing is carried out by per-channel tasklets. | |
1429 | * | |
1430 | **************************************************************************/ | |
1431 | ||
1432 | /* Enable/disable/generate interrupts */ | |
1433 | static inline void efx_farch_interrupts(struct efx_nic *efx, | |
1434 | bool enabled, bool force) | |
1435 | { | |
1436 | efx_oword_t int_en_reg_ker; | |
1437 | ||
1438 | EFX_POPULATE_OWORD_3(int_en_reg_ker, | |
1439 | FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level, | |
1440 | FRF_AZ_KER_INT_KER, force, | |
1441 | FRF_AZ_DRV_INT_EN_KER, enabled); | |
1442 | efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); | |
1443 | } | |
1444 | ||
1445 | void efx_farch_irq_enable_master(struct efx_nic *efx) | |
1446 | { | |
1447 | EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); | |
1448 | wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ | |
1449 | ||
1450 | efx_farch_interrupts(efx, true, false); | |
1451 | } | |
1452 | ||
1453 | void efx_farch_irq_disable_master(struct efx_nic *efx) | |
1454 | { | |
1455 | /* Disable interrupts */ | |
1456 | efx_farch_interrupts(efx, false, false); | |
1457 | } | |
1458 | ||
1459 | /* Generate a test interrupt | |
1460 | * Interrupt must already have been enabled, otherwise nasty things | |
1461 | * may happen. | |
1462 | */ | |
1463 | void efx_farch_irq_test_generate(struct efx_nic *efx) | |
1464 | { | |
1465 | efx_farch_interrupts(efx, true, true); | |
1466 | } | |
1467 | ||
1468 | /* Process a fatal interrupt | |
1469 | * Disable bus mastering ASAP and schedule a reset | |
1470 | */ | |
1471 | irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx) | |
1472 | { | |
1473 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1474 | efx_oword_t *int_ker = efx->irq_status.addr; | |
1475 | efx_oword_t fatal_intr; | |
1476 | int error, mem_perr; | |
1477 | ||
1478 | efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER); | |
1479 | error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR); | |
1480 | ||
1481 | netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status " | |
1482 | EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), | |
1483 | EFX_OWORD_VAL(fatal_intr), | |
1484 | error ? "disabling bus mastering" : "no recognised error"); | |
1485 | ||
1486 | /* If this is a memory parity error dump which blocks are offending */ | |
1487 | mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) || | |
1488 | EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER)); | |
1489 | if (mem_perr) { | |
1490 | efx_oword_t reg; | |
1491 | efx_reado(efx, ®, FR_AZ_MEM_STAT); | |
1492 | netif_err(efx, hw, efx->net_dev, | |
1493 | "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n", | |
1494 | EFX_OWORD_VAL(reg)); | |
1495 | } | |
1496 | ||
1497 | /* Disable both devices */ | |
1498 | pci_clear_master(efx->pci_dev); | |
1499 | if (efx_nic_is_dual_func(efx)) | |
1500 | pci_clear_master(nic_data->pci_dev2); | |
1501 | efx_farch_irq_disable_master(efx); | |
1502 | ||
1503 | /* Count errors and reset or disable the NIC accordingly */ | |
1504 | if (efx->int_error_count == 0 || | |
1505 | time_after(jiffies, efx->int_error_expire)) { | |
1506 | efx->int_error_count = 0; | |
1507 | efx->int_error_expire = | |
1508 | jiffies + EFX_INT_ERROR_EXPIRE * HZ; | |
1509 | } | |
1510 | if (++efx->int_error_count < EFX_MAX_INT_ERRORS) { | |
1511 | netif_err(efx, hw, efx->net_dev, | |
1512 | "SYSTEM ERROR - reset scheduled\n"); | |
1513 | efx_schedule_reset(efx, RESET_TYPE_INT_ERROR); | |
1514 | } else { | |
1515 | netif_err(efx, hw, efx->net_dev, | |
1516 | "SYSTEM ERROR - max number of errors seen." | |
1517 | "NIC will be disabled\n"); | |
1518 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1519 | } | |
1520 | ||
1521 | return IRQ_HANDLED; | |
1522 | } | |
1523 | ||
1524 | /* Handle a legacy interrupt | |
1525 | * Acknowledges the interrupt and schedule event queue processing. | |
1526 | */ | |
1527 | irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id) | |
1528 | { | |
1529 | struct efx_nic *efx = dev_id; | |
1530 | bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); | |
1531 | efx_oword_t *int_ker = efx->irq_status.addr; | |
1532 | irqreturn_t result = IRQ_NONE; | |
1533 | struct efx_channel *channel; | |
1534 | efx_dword_t reg; | |
1535 | u32 queues; | |
1536 | int syserr; | |
1537 | ||
1538 | /* Read the ISR which also ACKs the interrupts */ | |
1539 | efx_readd(efx, ®, FR_BZ_INT_ISR0); | |
1540 | queues = EFX_EXTRACT_DWORD(reg, 0, 31); | |
1541 | ||
1542 | /* Legacy interrupts are disabled too late by the EEH kernel | |
1543 | * code. Disable them earlier. | |
1544 | * If an EEH error occurred, the read will have returned all ones. | |
1545 | */ | |
1546 | if (EFX_DWORD_IS_ALL_ONES(reg) && efx_try_recovery(efx) && | |
1547 | !efx->eeh_disabled_legacy_irq) { | |
1548 | disable_irq_nosync(efx->legacy_irq); | |
1549 | efx->eeh_disabled_legacy_irq = true; | |
1550 | } | |
1551 | ||
1552 | /* Handle non-event-queue sources */ | |
1553 | if (queues & (1U << efx->irq_level) && soft_enabled) { | |
1554 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); | |
1555 | if (unlikely(syserr)) | |
1556 | return efx_farch_fatal_interrupt(efx); | |
1557 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1558 | } | |
1559 | ||
1560 | if (queues != 0) { | |
ab3b8250 | 1561 | efx->irq_zero_count = 0; |
86094f7f BH |
1562 | |
1563 | /* Schedule processing of any interrupting queues */ | |
1564 | if (likely(soft_enabled)) { | |
1565 | efx_for_each_channel(channel, efx) { | |
1566 | if (queues & 1) | |
1567 | efx_schedule_channel_irq(channel); | |
1568 | queues >>= 1; | |
1569 | } | |
1570 | } | |
1571 | result = IRQ_HANDLED; | |
1572 | ||
ab3b8250 | 1573 | } else { |
86094f7f BH |
1574 | efx_qword_t *event; |
1575 | ||
ab3b8250 BH |
1576 | /* Legacy ISR read can return zero once (SF bug 15783) */ |
1577 | ||
86094f7f BH |
1578 | /* We can't return IRQ_HANDLED more than once on seeing ISR=0 |
1579 | * because this might be a shared interrupt. */ | |
1580 | if (efx->irq_zero_count++ == 0) | |
1581 | result = IRQ_HANDLED; | |
1582 | ||
1583 | /* Ensure we schedule or rearm all event queues */ | |
1584 | if (likely(soft_enabled)) { | |
1585 | efx_for_each_channel(channel, efx) { | |
1586 | event = efx_event(channel, | |
1587 | channel->eventq_read_ptr); | |
1588 | if (efx_event_present(event)) | |
1589 | efx_schedule_channel_irq(channel); | |
1590 | else | |
1591 | efx_farch_ev_read_ack(channel); | |
1592 | } | |
1593 | } | |
1594 | } | |
1595 | ||
1596 | if (result == IRQ_HANDLED) | |
1597 | netif_vdbg(efx, intr, efx->net_dev, | |
1598 | "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", | |
1599 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); | |
1600 | ||
1601 | return result; | |
1602 | } | |
1603 | ||
1604 | /* Handle an MSI interrupt | |
1605 | * | |
1606 | * Handle an MSI hardware interrupt. This routine schedules event | |
1607 | * queue processing. No interrupt acknowledgement cycle is necessary. | |
1608 | * Also, we never need to check that the interrupt is for us, since | |
1609 | * MSI interrupts cannot be shared. | |
1610 | */ | |
1611 | irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id) | |
1612 | { | |
1613 | struct efx_msi_context *context = dev_id; | |
1614 | struct efx_nic *efx = context->efx; | |
1615 | efx_oword_t *int_ker = efx->irq_status.addr; | |
1616 | int syserr; | |
1617 | ||
1618 | netif_vdbg(efx, intr, efx->net_dev, | |
1619 | "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1620 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1621 | ||
1622 | if (!likely(ACCESS_ONCE(efx->irq_soft_enabled))) | |
1623 | return IRQ_HANDLED; | |
1624 | ||
1625 | /* Handle non-event-queue sources */ | |
1626 | if (context->index == efx->irq_level) { | |
1627 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); | |
1628 | if (unlikely(syserr)) | |
1629 | return efx_farch_fatal_interrupt(efx); | |
1630 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1631 | } | |
1632 | ||
1633 | /* Schedule processing of the channel */ | |
1634 | efx_schedule_channel_irq(efx->channel[context->index]); | |
1635 | ||
1636 | return IRQ_HANDLED; | |
1637 | } | |
1638 | ||
86094f7f BH |
1639 | /* Setup RSS indirection table. |
1640 | * This maps from the hash value of the packet to RXQ | |
1641 | */ | |
1642 | void efx_farch_rx_push_indir_table(struct efx_nic *efx) | |
1643 | { | |
1644 | size_t i = 0; | |
1645 | efx_dword_t dword; | |
1646 | ||
d43050c0 | 1647 | BUG_ON(efx_nic_rev(efx) < EFX_REV_FALCON_B0); |
86094f7f BH |
1648 | |
1649 | BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != | |
1650 | FR_BZ_RX_INDIRECTION_TBL_ROWS); | |
1651 | ||
1652 | for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) { | |
1653 | EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, | |
1654 | efx->rx_indir_table[i]); | |
1655 | efx_writed(efx, &dword, | |
1656 | FR_BZ_RX_INDIRECTION_TBL + | |
1657 | FR_BZ_RX_INDIRECTION_TBL_STEP * i); | |
1658 | } | |
1659 | } | |
1660 | ||
1661 | /* Looks at available SRAM resources and works out how many queues we | |
1662 | * can support, and where things like descriptor caches should live. | |
1663 | * | |
1664 | * SRAM is split up as follows: | |
1665 | * 0 buftbl entries for channels | |
1666 | * efx->vf_buftbl_base buftbl entries for SR-IOV | |
1667 | * efx->rx_dc_base RX descriptor caches | |
1668 | * efx->tx_dc_base TX descriptor caches | |
1669 | */ | |
1670 | void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw) | |
1671 | { | |
1672 | unsigned vi_count, buftbl_min; | |
1673 | ||
2dc313ec SS |
1674 | #ifdef CONFIG_SFC_SRIOV |
1675 | struct siena_nic_data *nic_data = efx->nic_data; | |
1676 | #endif | |
1677 | ||
86094f7f BH |
1678 | /* Account for the buffer table entries backing the datapath channels |
1679 | * and the descriptor caches for those channels. | |
1680 | */ | |
1681 | buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE + | |
1682 | efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE + | |
1683 | efx->n_channels * EFX_MAX_EVQ_SIZE) | |
1684 | * sizeof(efx_qword_t) / EFX_BUF_SIZE); | |
1685 | vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); | |
1686 | ||
1687 | #ifdef CONFIG_SFC_SRIOV | |
d98a4ffe | 1688 | if (efx->type->sriov_wanted(efx)) { |
86094f7f BH |
1689 | unsigned vi_dc_entries, buftbl_free, entries_per_vf, vf_limit; |
1690 | ||
2dc313ec | 1691 | nic_data->vf_buftbl_base = buftbl_min; |
86094f7f BH |
1692 | |
1693 | vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES; | |
1694 | vi_count = max(vi_count, EFX_VI_BASE); | |
1695 | buftbl_free = (sram_lim_qw - buftbl_min - | |
1696 | vi_count * vi_dc_entries); | |
1697 | ||
1698 | entries_per_vf = ((vi_dc_entries + EFX_VF_BUFTBL_PER_VI) * | |
1699 | efx_vf_size(efx)); | |
1700 | vf_limit = min(buftbl_free / entries_per_vf, | |
1701 | (1024U - EFX_VI_BASE) >> efx->vi_scale); | |
1702 | ||
1703 | if (efx->vf_count > vf_limit) { | |
1704 | netif_err(efx, probe, efx->net_dev, | |
1705 | "Reducing VF count from from %d to %d\n", | |
1706 | efx->vf_count, vf_limit); | |
1707 | efx->vf_count = vf_limit; | |
1708 | } | |
1709 | vi_count += efx->vf_count * efx_vf_size(efx); | |
1710 | } | |
1711 | #endif | |
1712 | ||
1713 | efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES; | |
1714 | efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES; | |
1715 | } | |
1716 | ||
1717 | u32 efx_farch_fpga_ver(struct efx_nic *efx) | |
1718 | { | |
1719 | efx_oword_t altera_build; | |
1720 | efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD); | |
1721 | return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER); | |
1722 | } | |
1723 | ||
1724 | void efx_farch_init_common(struct efx_nic *efx) | |
1725 | { | |
1726 | efx_oword_t temp; | |
1727 | ||
1728 | /* Set positions of descriptor caches in SRAM. */ | |
1729 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base); | |
1730 | efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); | |
1731 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base); | |
1732 | efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); | |
1733 | ||
1734 | /* Set TX descriptor cache size. */ | |
1735 | BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER)); | |
1736 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER); | |
1737 | efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG); | |
1738 | ||
1739 | /* Set RX descriptor cache size. Set low watermark to size-8, as | |
1740 | * this allows most efficient prefetching. | |
1741 | */ | |
1742 | BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER)); | |
1743 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER); | |
1744 | efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG); | |
1745 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); | |
1746 | efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM); | |
1747 | ||
1748 | /* Program INT_KER address */ | |
1749 | EFX_POPULATE_OWORD_2(temp, | |
1750 | FRF_AZ_NORM_INT_VEC_DIS_KER, | |
1751 | EFX_INT_MODE_USE_MSI(efx), | |
1752 | FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); | |
1753 | efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER); | |
1754 | ||
1755 | if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx)) | |
1756 | /* Use an interrupt level unused by event queues */ | |
1757 | efx->irq_level = 0x1f; | |
1758 | else | |
1759 | /* Use a valid MSI-X vector */ | |
1760 | efx->irq_level = 0; | |
1761 | ||
1762 | /* Enable all the genuinely fatal interrupts. (They are still | |
1763 | * masked by the overall interrupt mask, controlled by | |
1764 | * falcon_interrupts()). | |
1765 | * | |
1766 | * Note: All other fatal interrupts are enabled | |
1767 | */ | |
1768 | EFX_POPULATE_OWORD_3(temp, | |
1769 | FRF_AZ_ILL_ADR_INT_KER_EN, 1, | |
1770 | FRF_AZ_RBUF_OWN_INT_KER_EN, 1, | |
1771 | FRF_AZ_TBUF_OWN_INT_KER_EN, 1); | |
1772 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) | |
1773 | EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1); | |
1774 | EFX_INVERT_OWORD(temp); | |
1775 | efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); | |
1776 | ||
86094f7f BH |
1777 | /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be |
1778 | * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. | |
1779 | */ | |
1780 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); | |
1781 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe); | |
1782 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1); | |
1783 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1); | |
1784 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1); | |
1785 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1); | |
1786 | /* Enable SW_EV to inherit in char driver - assume harmless here */ | |
1787 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1); | |
1788 | /* Prefetch threshold 2 => fetch when descriptor cache half empty */ | |
1789 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2); | |
1790 | /* Disable hardware watchdog which can misfire */ | |
1791 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff); | |
1792 | /* Squash TX of packets of 16 bytes or less */ | |
1793 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) | |
1794 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); | |
1795 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); | |
1796 | ||
1797 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { | |
1798 | EFX_POPULATE_OWORD_4(temp, | |
1799 | /* Default values */ | |
1800 | FRF_BZ_TX_PACE_SB_NOT_AF, 0x15, | |
1801 | FRF_BZ_TX_PACE_SB_AF, 0xb, | |
1802 | FRF_BZ_TX_PACE_FB_BASE, 0, | |
1803 | /* Allow large pace values in the | |
1804 | * fast bin. */ | |
1805 | FRF_BZ_TX_PACE_BIN_TH, | |
1806 | FFE_BZ_TX_PACE_RESERVED); | |
1807 | efx_writeo(efx, &temp, FR_BZ_TX_PACE); | |
1808 | } | |
1809 | } | |
add72477 BH |
1810 | |
1811 | /************************************************************************** | |
1812 | * | |
1813 | * Filter tables | |
1814 | * | |
1815 | ************************************************************************** | |
1816 | */ | |
1817 | ||
1818 | /* "Fudge factors" - difference between programmed value and actual depth. | |
1819 | * Due to pipelined implementation we need to program H/W with a value that | |
1820 | * is larger than the hop limit we want. | |
1821 | */ | |
1822 | #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD 3 | |
1823 | #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL 1 | |
1824 | ||
1825 | /* Hard maximum search limit. Hardware will time-out beyond 200-something. | |
1826 | * We also need to avoid infinite loops in efx_farch_filter_search() when the | |
1827 | * table is full. | |
1828 | */ | |
1829 | #define EFX_FARCH_FILTER_CTL_SRCH_MAX 200 | |
1830 | ||
1831 | /* Don't try very hard to find space for performance hints, as this is | |
1832 | * counter-productive. */ | |
1833 | #define EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX 5 | |
1834 | ||
1835 | enum efx_farch_filter_type { | |
1836 | EFX_FARCH_FILTER_TCP_FULL = 0, | |
1837 | EFX_FARCH_FILTER_TCP_WILD, | |
1838 | EFX_FARCH_FILTER_UDP_FULL, | |
1839 | EFX_FARCH_FILTER_UDP_WILD, | |
1840 | EFX_FARCH_FILTER_MAC_FULL = 4, | |
1841 | EFX_FARCH_FILTER_MAC_WILD, | |
1842 | EFX_FARCH_FILTER_UC_DEF = 8, | |
1843 | EFX_FARCH_FILTER_MC_DEF, | |
1844 | EFX_FARCH_FILTER_TYPE_COUNT, /* number of specific types */ | |
1845 | }; | |
1846 | ||
1847 | enum efx_farch_filter_table_id { | |
1848 | EFX_FARCH_FILTER_TABLE_RX_IP = 0, | |
1849 | EFX_FARCH_FILTER_TABLE_RX_MAC, | |
1850 | EFX_FARCH_FILTER_TABLE_RX_DEF, | |
1851 | EFX_FARCH_FILTER_TABLE_TX_MAC, | |
1852 | EFX_FARCH_FILTER_TABLE_COUNT, | |
1853 | }; | |
1854 | ||
1855 | enum efx_farch_filter_index { | |
1856 | EFX_FARCH_FILTER_INDEX_UC_DEF, | |
1857 | EFX_FARCH_FILTER_INDEX_MC_DEF, | |
1858 | EFX_FARCH_FILTER_SIZE_RX_DEF, | |
1859 | }; | |
1860 | ||
1861 | struct efx_farch_filter_spec { | |
1862 | u8 type:4; | |
1863 | u8 priority:4; | |
1864 | u8 flags; | |
1865 | u16 dmaq_id; | |
1866 | u32 data[3]; | |
1867 | }; | |
1868 | ||
1869 | struct efx_farch_filter_table { | |
1870 | enum efx_farch_filter_table_id id; | |
1871 | u32 offset; /* address of table relative to BAR */ | |
1872 | unsigned size; /* number of entries */ | |
1873 | unsigned step; /* step between entries */ | |
1874 | unsigned used; /* number currently used */ | |
1875 | unsigned long *used_bitmap; | |
1876 | struct efx_farch_filter_spec *spec; | |
1877 | unsigned search_limit[EFX_FARCH_FILTER_TYPE_COUNT]; | |
1878 | }; | |
1879 | ||
1880 | struct efx_farch_filter_state { | |
1881 | struct efx_farch_filter_table table[EFX_FARCH_FILTER_TABLE_COUNT]; | |
1882 | }; | |
1883 | ||
1884 | static void | |
1885 | efx_farch_filter_table_clear_entry(struct efx_nic *efx, | |
1886 | struct efx_farch_filter_table *table, | |
1887 | unsigned int filter_idx); | |
1888 | ||
1889 | /* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit | |
1890 | * key derived from the n-tuple. The initial LFSR state is 0xffff. */ | |
1891 | static u16 efx_farch_filter_hash(u32 key) | |
1892 | { | |
1893 | u16 tmp; | |
1894 | ||
1895 | /* First 16 rounds */ | |
1896 | tmp = 0x1fff ^ key >> 16; | |
1897 | tmp = tmp ^ tmp >> 3 ^ tmp >> 6; | |
1898 | tmp = tmp ^ tmp >> 9; | |
1899 | /* Last 16 rounds */ | |
1900 | tmp = tmp ^ tmp << 13 ^ key; | |
1901 | tmp = tmp ^ tmp >> 3 ^ tmp >> 6; | |
1902 | return tmp ^ tmp >> 9; | |
1903 | } | |
1904 | ||
1905 | /* To allow for hash collisions, filter search continues at these | |
1906 | * increments from the first possible entry selected by the hash. */ | |
1907 | static u16 efx_farch_filter_increment(u32 key) | |
1908 | { | |
1909 | return key * 2 - 1; | |
1910 | } | |
1911 | ||
1912 | static enum efx_farch_filter_table_id | |
1913 | efx_farch_filter_spec_table_id(const struct efx_farch_filter_spec *spec) | |
1914 | { | |
1915 | BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP != | |
1916 | (EFX_FARCH_FILTER_TCP_FULL >> 2)); | |
1917 | BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP != | |
1918 | (EFX_FARCH_FILTER_TCP_WILD >> 2)); | |
1919 | BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP != | |
1920 | (EFX_FARCH_FILTER_UDP_FULL >> 2)); | |
1921 | BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP != | |
1922 | (EFX_FARCH_FILTER_UDP_WILD >> 2)); | |
1923 | BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC != | |
1924 | (EFX_FARCH_FILTER_MAC_FULL >> 2)); | |
1925 | BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC != | |
1926 | (EFX_FARCH_FILTER_MAC_WILD >> 2)); | |
1927 | BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_TX_MAC != | |
1928 | EFX_FARCH_FILTER_TABLE_RX_MAC + 2); | |
1929 | return (spec->type >> 2) + ((spec->flags & EFX_FILTER_FLAG_TX) ? 2 : 0); | |
1930 | } | |
1931 | ||
1932 | static void efx_farch_filter_push_rx_config(struct efx_nic *efx) | |
1933 | { | |
1934 | struct efx_farch_filter_state *state = efx->filter_state; | |
1935 | struct efx_farch_filter_table *table; | |
1936 | efx_oword_t filter_ctl; | |
1937 | ||
1938 | efx_reado(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL); | |
1939 | ||
1940 | table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP]; | |
1941 | EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_FULL_SRCH_LIMIT, | |
1942 | table->search_limit[EFX_FARCH_FILTER_TCP_FULL] + | |
1943 | EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL); | |
1944 | EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_WILD_SRCH_LIMIT, | |
1945 | table->search_limit[EFX_FARCH_FILTER_TCP_WILD] + | |
1946 | EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD); | |
1947 | EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_FULL_SRCH_LIMIT, | |
1948 | table->search_limit[EFX_FARCH_FILTER_UDP_FULL] + | |
1949 | EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL); | |
1950 | EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_WILD_SRCH_LIMIT, | |
1951 | table->search_limit[EFX_FARCH_FILTER_UDP_WILD] + | |
1952 | EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD); | |
1953 | ||
1954 | table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC]; | |
1955 | if (table->size) { | |
1956 | EFX_SET_OWORD_FIELD( | |
1957 | filter_ctl, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT, | |
1958 | table->search_limit[EFX_FARCH_FILTER_MAC_FULL] + | |
1959 | EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL); | |
1960 | EFX_SET_OWORD_FIELD( | |
1961 | filter_ctl, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT, | |
1962 | table->search_limit[EFX_FARCH_FILTER_MAC_WILD] + | |
1963 | EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD); | |
1964 | } | |
1965 | ||
1966 | table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF]; | |
1967 | if (table->size) { | |
1968 | EFX_SET_OWORD_FIELD( | |
1969 | filter_ctl, FRF_CZ_UNICAST_NOMATCH_Q_ID, | |
1970 | table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].dmaq_id); | |
1971 | EFX_SET_OWORD_FIELD( | |
1972 | filter_ctl, FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED, | |
1973 | !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags & | |
1974 | EFX_FILTER_FLAG_RX_RSS)); | |
1975 | EFX_SET_OWORD_FIELD( | |
1976 | filter_ctl, FRF_CZ_MULTICAST_NOMATCH_Q_ID, | |
1977 | table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].dmaq_id); | |
1978 | EFX_SET_OWORD_FIELD( | |
1979 | filter_ctl, FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED, | |
1980 | !!(table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags & | |
1981 | EFX_FILTER_FLAG_RX_RSS)); | |
1982 | ||
1983 | /* There is a single bit to enable RX scatter for all | |
1984 | * unmatched packets. Only set it if scatter is | |
1985 | * enabled in both filter specs. | |
1986 | */ | |
1987 | EFX_SET_OWORD_FIELD( | |
1988 | filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, | |
1989 | !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags & | |
1990 | table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags & | |
1991 | EFX_FILTER_FLAG_RX_SCATTER)); | |
1992 | } else if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { | |
1993 | /* We don't expose 'default' filters because unmatched | |
1994 | * packets always go to the queue number found in the | |
1995 | * RSS table. But we still need to set the RX scatter | |
1996 | * bit here. | |
1997 | */ | |
1998 | EFX_SET_OWORD_FIELD( | |
1999 | filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, | |
2000 | efx->rx_scatter); | |
2001 | } | |
2002 | ||
2003 | efx_writeo(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL); | |
2004 | } | |
2005 | ||
2006 | static void efx_farch_filter_push_tx_limits(struct efx_nic *efx) | |
2007 | { | |
2008 | struct efx_farch_filter_state *state = efx->filter_state; | |
2009 | struct efx_farch_filter_table *table; | |
2010 | efx_oword_t tx_cfg; | |
2011 | ||
2012 | efx_reado(efx, &tx_cfg, FR_AZ_TX_CFG); | |
2013 | ||
2014 | table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC]; | |
2015 | if (table->size) { | |
2016 | EFX_SET_OWORD_FIELD( | |
2017 | tx_cfg, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE, | |
2018 | table->search_limit[EFX_FARCH_FILTER_MAC_FULL] + | |
2019 | EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL); | |
2020 | EFX_SET_OWORD_FIELD( | |
2021 | tx_cfg, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE, | |
2022 | table->search_limit[EFX_FARCH_FILTER_MAC_WILD] + | |
2023 | EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD); | |
2024 | } | |
2025 | ||
2026 | efx_writeo(efx, &tx_cfg, FR_AZ_TX_CFG); | |
2027 | } | |
2028 | ||
2029 | static int | |
2030 | efx_farch_filter_from_gen_spec(struct efx_farch_filter_spec *spec, | |
2031 | const struct efx_filter_spec *gen_spec) | |
2032 | { | |
2033 | bool is_full = false; | |
2034 | ||
2035 | if ((gen_spec->flags & EFX_FILTER_FLAG_RX_RSS) && | |
2036 | gen_spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT) | |
2037 | return -EINVAL; | |
2038 | ||
2039 | spec->priority = gen_spec->priority; | |
2040 | spec->flags = gen_spec->flags; | |
2041 | spec->dmaq_id = gen_spec->dmaq_id; | |
2042 | ||
2043 | switch (gen_spec->match_flags) { | |
2044 | case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO | | |
2045 | EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT | | |
2046 | EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT): | |
2047 | is_full = true; | |
2048 | /* fall through */ | |
2049 | case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO | | |
2050 | EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT): { | |
2051 | __be32 rhost, host1, host2; | |
2052 | __be16 rport, port1, port2; | |
2053 | ||
2054 | EFX_BUG_ON_PARANOID(!(gen_spec->flags & EFX_FILTER_FLAG_RX)); | |
2055 | ||
2056 | if (gen_spec->ether_type != htons(ETH_P_IP)) | |
2057 | return -EPROTONOSUPPORT; | |
2058 | if (gen_spec->loc_port == 0 || | |
2059 | (is_full && gen_spec->rem_port == 0)) | |
2060 | return -EADDRNOTAVAIL; | |
2061 | switch (gen_spec->ip_proto) { | |
2062 | case IPPROTO_TCP: | |
2063 | spec->type = (is_full ? EFX_FARCH_FILTER_TCP_FULL : | |
2064 | EFX_FARCH_FILTER_TCP_WILD); | |
2065 | break; | |
2066 | case IPPROTO_UDP: | |
2067 | spec->type = (is_full ? EFX_FARCH_FILTER_UDP_FULL : | |
2068 | EFX_FARCH_FILTER_UDP_WILD); | |
2069 | break; | |
2070 | default: | |
2071 | return -EPROTONOSUPPORT; | |
2072 | } | |
2073 | ||
2074 | /* Filter is constructed in terms of source and destination, | |
2075 | * with the odd wrinkle that the ports are swapped in a UDP | |
2076 | * wildcard filter. We need to convert from local and remote | |
2077 | * (= zero for wildcard) addresses. | |
2078 | */ | |
2079 | rhost = is_full ? gen_spec->rem_host[0] : 0; | |
2080 | rport = is_full ? gen_spec->rem_port : 0; | |
2081 | host1 = rhost; | |
2082 | host2 = gen_spec->loc_host[0]; | |
2083 | if (!is_full && gen_spec->ip_proto == IPPROTO_UDP) { | |
2084 | port1 = gen_spec->loc_port; | |
2085 | port2 = rport; | |
2086 | } else { | |
2087 | port1 = rport; | |
2088 | port2 = gen_spec->loc_port; | |
2089 | } | |
2090 | spec->data[0] = ntohl(host1) << 16 | ntohs(port1); | |
2091 | spec->data[1] = ntohs(port2) << 16 | ntohl(host1) >> 16; | |
2092 | spec->data[2] = ntohl(host2); | |
2093 | ||
2094 | break; | |
2095 | } | |
2096 | ||
2097 | case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID: | |
2098 | is_full = true; | |
2099 | /* fall through */ | |
2100 | case EFX_FILTER_MATCH_LOC_MAC: | |
2101 | spec->type = (is_full ? EFX_FARCH_FILTER_MAC_FULL : | |
2102 | EFX_FARCH_FILTER_MAC_WILD); | |
2103 | spec->data[0] = is_full ? ntohs(gen_spec->outer_vid) : 0; | |
2104 | spec->data[1] = (gen_spec->loc_mac[2] << 24 | | |
2105 | gen_spec->loc_mac[3] << 16 | | |
2106 | gen_spec->loc_mac[4] << 8 | | |
2107 | gen_spec->loc_mac[5]); | |
2108 | spec->data[2] = (gen_spec->loc_mac[0] << 8 | | |
2109 | gen_spec->loc_mac[1]); | |
2110 | break; | |
2111 | ||
2112 | case EFX_FILTER_MATCH_LOC_MAC_IG: | |
2113 | spec->type = (is_multicast_ether_addr(gen_spec->loc_mac) ? | |
2114 | EFX_FARCH_FILTER_MC_DEF : | |
2115 | EFX_FARCH_FILTER_UC_DEF); | |
2116 | memset(spec->data, 0, sizeof(spec->data)); /* ensure equality */ | |
2117 | break; | |
2118 | ||
2119 | default: | |
2120 | return -EPROTONOSUPPORT; | |
2121 | } | |
2122 | ||
2123 | return 0; | |
2124 | } | |
2125 | ||
2126 | static void | |
2127 | efx_farch_filter_to_gen_spec(struct efx_filter_spec *gen_spec, | |
2128 | const struct efx_farch_filter_spec *spec) | |
2129 | { | |
2130 | bool is_full = false; | |
2131 | ||
2132 | /* *gen_spec should be completely initialised, to be consistent | |
2133 | * with efx_filter_init_{rx,tx}() and in case we want to copy | |
2134 | * it back to userland. | |
2135 | */ | |
2136 | memset(gen_spec, 0, sizeof(*gen_spec)); | |
2137 | ||
2138 | gen_spec->priority = spec->priority; | |
2139 | gen_spec->flags = spec->flags; | |
2140 | gen_spec->dmaq_id = spec->dmaq_id; | |
2141 | ||
2142 | switch (spec->type) { | |
2143 | case EFX_FARCH_FILTER_TCP_FULL: | |
2144 | case EFX_FARCH_FILTER_UDP_FULL: | |
2145 | is_full = true; | |
2146 | /* fall through */ | |
2147 | case EFX_FARCH_FILTER_TCP_WILD: | |
2148 | case EFX_FARCH_FILTER_UDP_WILD: { | |
2149 | __be32 host1, host2; | |
2150 | __be16 port1, port2; | |
2151 | ||
2152 | gen_spec->match_flags = | |
2153 | EFX_FILTER_MATCH_ETHER_TYPE | | |
2154 | EFX_FILTER_MATCH_IP_PROTO | | |
2155 | EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT; | |
2156 | if (is_full) | |
2157 | gen_spec->match_flags |= (EFX_FILTER_MATCH_REM_HOST | | |
2158 | EFX_FILTER_MATCH_REM_PORT); | |
2159 | gen_spec->ether_type = htons(ETH_P_IP); | |
2160 | gen_spec->ip_proto = | |
2161 | (spec->type == EFX_FARCH_FILTER_TCP_FULL || | |
2162 | spec->type == EFX_FARCH_FILTER_TCP_WILD) ? | |
2163 | IPPROTO_TCP : IPPROTO_UDP; | |
2164 | ||
2165 | host1 = htonl(spec->data[0] >> 16 | spec->data[1] << 16); | |
2166 | port1 = htons(spec->data[0]); | |
2167 | host2 = htonl(spec->data[2]); | |
2168 | port2 = htons(spec->data[1] >> 16); | |
2169 | if (spec->flags & EFX_FILTER_FLAG_TX) { | |
2170 | gen_spec->loc_host[0] = host1; | |
2171 | gen_spec->rem_host[0] = host2; | |
2172 | } else { | |
2173 | gen_spec->loc_host[0] = host2; | |
2174 | gen_spec->rem_host[0] = host1; | |
2175 | } | |
2176 | if (!!(gen_spec->flags & EFX_FILTER_FLAG_TX) ^ | |
2177 | (!is_full && gen_spec->ip_proto == IPPROTO_UDP)) { | |
2178 | gen_spec->loc_port = port1; | |
2179 | gen_spec->rem_port = port2; | |
2180 | } else { | |
2181 | gen_spec->loc_port = port2; | |
2182 | gen_spec->rem_port = port1; | |
2183 | } | |
2184 | ||
2185 | break; | |
2186 | } | |
2187 | ||
2188 | case EFX_FARCH_FILTER_MAC_FULL: | |
2189 | is_full = true; | |
2190 | /* fall through */ | |
2191 | case EFX_FARCH_FILTER_MAC_WILD: | |
2192 | gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC; | |
2193 | if (is_full) | |
2194 | gen_spec->match_flags |= EFX_FILTER_MATCH_OUTER_VID; | |
2195 | gen_spec->loc_mac[0] = spec->data[2] >> 8; | |
2196 | gen_spec->loc_mac[1] = spec->data[2]; | |
2197 | gen_spec->loc_mac[2] = spec->data[1] >> 24; | |
2198 | gen_spec->loc_mac[3] = spec->data[1] >> 16; | |
2199 | gen_spec->loc_mac[4] = spec->data[1] >> 8; | |
2200 | gen_spec->loc_mac[5] = spec->data[1]; | |
2201 | gen_spec->outer_vid = htons(spec->data[0]); | |
2202 | break; | |
2203 | ||
2204 | case EFX_FARCH_FILTER_UC_DEF: | |
2205 | case EFX_FARCH_FILTER_MC_DEF: | |
2206 | gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC_IG; | |
2207 | gen_spec->loc_mac[0] = spec->type == EFX_FARCH_FILTER_MC_DEF; | |
2208 | break; | |
2209 | ||
2210 | default: | |
2211 | WARN_ON(1); | |
2212 | break; | |
2213 | } | |
2214 | } | |
2215 | ||
2216 | static void | |
b59e6ef8 BH |
2217 | efx_farch_filter_init_rx_auto(struct efx_nic *efx, |
2218 | struct efx_farch_filter_spec *spec) | |
add72477 | 2219 | { |
add72477 BH |
2220 | /* If there's only one channel then disable RSS for non VF |
2221 | * traffic, thereby allowing VFs to use RSS when the PF can't. | |
2222 | */ | |
7665d1ab BH |
2223 | spec->priority = EFX_FILTER_PRI_AUTO; |
2224 | spec->flags = (EFX_FILTER_FLAG_RX | | |
add72477 BH |
2225 | (efx->n_rx_channels > 1 ? EFX_FILTER_FLAG_RX_RSS : 0) | |
2226 | (efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0)); | |
2227 | spec->dmaq_id = 0; | |
add72477 BH |
2228 | } |
2229 | ||
2230 | /* Build a filter entry and return its n-tuple key. */ | |
2231 | static u32 efx_farch_filter_build(efx_oword_t *filter, | |
2232 | struct efx_farch_filter_spec *spec) | |
2233 | { | |
2234 | u32 data3; | |
2235 | ||
2236 | switch (efx_farch_filter_spec_table_id(spec)) { | |
2237 | case EFX_FARCH_FILTER_TABLE_RX_IP: { | |
2238 | bool is_udp = (spec->type == EFX_FARCH_FILTER_UDP_FULL || | |
2239 | spec->type == EFX_FARCH_FILTER_UDP_WILD); | |
2240 | EFX_POPULATE_OWORD_7( | |
2241 | *filter, | |
2242 | FRF_BZ_RSS_EN, | |
2243 | !!(spec->flags & EFX_FILTER_FLAG_RX_RSS), | |
2244 | FRF_BZ_SCATTER_EN, | |
2245 | !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER), | |
2246 | FRF_BZ_TCP_UDP, is_udp, | |
2247 | FRF_BZ_RXQ_ID, spec->dmaq_id, | |
2248 | EFX_DWORD_2, spec->data[2], | |
2249 | EFX_DWORD_1, spec->data[1], | |
2250 | EFX_DWORD_0, spec->data[0]); | |
2251 | data3 = is_udp; | |
2252 | break; | |
2253 | } | |
2254 | ||
2255 | case EFX_FARCH_FILTER_TABLE_RX_MAC: { | |
2256 | bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD; | |
2257 | EFX_POPULATE_OWORD_7( | |
2258 | *filter, | |
2259 | FRF_CZ_RMFT_RSS_EN, | |
2260 | !!(spec->flags & EFX_FILTER_FLAG_RX_RSS), | |
2261 | FRF_CZ_RMFT_SCATTER_EN, | |
2262 | !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER), | |
2263 | FRF_CZ_RMFT_RXQ_ID, spec->dmaq_id, | |
2264 | FRF_CZ_RMFT_WILDCARD_MATCH, is_wild, | |
2265 | FRF_CZ_RMFT_DEST_MAC_HI, spec->data[2], | |
2266 | FRF_CZ_RMFT_DEST_MAC_LO, spec->data[1], | |
2267 | FRF_CZ_RMFT_VLAN_ID, spec->data[0]); | |
2268 | data3 = is_wild; | |
2269 | break; | |
2270 | } | |
2271 | ||
2272 | case EFX_FARCH_FILTER_TABLE_TX_MAC: { | |
2273 | bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD; | |
2274 | EFX_POPULATE_OWORD_5(*filter, | |
2275 | FRF_CZ_TMFT_TXQ_ID, spec->dmaq_id, | |
2276 | FRF_CZ_TMFT_WILDCARD_MATCH, is_wild, | |
2277 | FRF_CZ_TMFT_SRC_MAC_HI, spec->data[2], | |
2278 | FRF_CZ_TMFT_SRC_MAC_LO, spec->data[1], | |
2279 | FRF_CZ_TMFT_VLAN_ID, spec->data[0]); | |
2280 | data3 = is_wild | spec->dmaq_id << 1; | |
2281 | break; | |
2282 | } | |
2283 | ||
2284 | default: | |
2285 | BUG(); | |
2286 | } | |
2287 | ||
2288 | return spec->data[0] ^ spec->data[1] ^ spec->data[2] ^ data3; | |
2289 | } | |
2290 | ||
2291 | static bool efx_farch_filter_equal(const struct efx_farch_filter_spec *left, | |
2292 | const struct efx_farch_filter_spec *right) | |
2293 | { | |
2294 | if (left->type != right->type || | |
2295 | memcmp(left->data, right->data, sizeof(left->data))) | |
2296 | return false; | |
2297 | ||
2298 | if (left->flags & EFX_FILTER_FLAG_TX && | |
2299 | left->dmaq_id != right->dmaq_id) | |
2300 | return false; | |
2301 | ||
2302 | return true; | |
2303 | } | |
2304 | ||
2305 | /* | |
2306 | * Construct/deconstruct external filter IDs. At least the RX filter | |
2307 | * IDs must be ordered by matching priority, for RX NFC semantics. | |
2308 | * | |
2309 | * Deconstruction needs to be robust against invalid IDs so that | |
2310 | * efx_filter_remove_id_safe() and efx_filter_get_filter_safe() can | |
2311 | * accept user-provided IDs. | |
2312 | */ | |
2313 | ||
2314 | #define EFX_FARCH_FILTER_MATCH_PRI_COUNT 5 | |
2315 | ||
2316 | static const u8 efx_farch_filter_type_match_pri[EFX_FARCH_FILTER_TYPE_COUNT] = { | |
2317 | [EFX_FARCH_FILTER_TCP_FULL] = 0, | |
2318 | [EFX_FARCH_FILTER_UDP_FULL] = 0, | |
2319 | [EFX_FARCH_FILTER_TCP_WILD] = 1, | |
2320 | [EFX_FARCH_FILTER_UDP_WILD] = 1, | |
2321 | [EFX_FARCH_FILTER_MAC_FULL] = 2, | |
2322 | [EFX_FARCH_FILTER_MAC_WILD] = 3, | |
2323 | [EFX_FARCH_FILTER_UC_DEF] = 4, | |
2324 | [EFX_FARCH_FILTER_MC_DEF] = 4, | |
2325 | }; | |
2326 | ||
2327 | static const enum efx_farch_filter_table_id efx_farch_filter_range_table[] = { | |
2328 | EFX_FARCH_FILTER_TABLE_RX_IP, /* RX match pri 0 */ | |
2329 | EFX_FARCH_FILTER_TABLE_RX_IP, | |
2330 | EFX_FARCH_FILTER_TABLE_RX_MAC, | |
2331 | EFX_FARCH_FILTER_TABLE_RX_MAC, | |
2332 | EFX_FARCH_FILTER_TABLE_RX_DEF, /* RX match pri 4 */ | |
2333 | EFX_FARCH_FILTER_TABLE_TX_MAC, /* TX match pri 0 */ | |
2334 | EFX_FARCH_FILTER_TABLE_TX_MAC, /* TX match pri 1 */ | |
2335 | }; | |
2336 | ||
2337 | #define EFX_FARCH_FILTER_INDEX_WIDTH 13 | |
2338 | #define EFX_FARCH_FILTER_INDEX_MASK ((1 << EFX_FARCH_FILTER_INDEX_WIDTH) - 1) | |
2339 | ||
2340 | static inline u32 | |
2341 | efx_farch_filter_make_id(const struct efx_farch_filter_spec *spec, | |
2342 | unsigned int index) | |
2343 | { | |
2344 | unsigned int range; | |
2345 | ||
2346 | range = efx_farch_filter_type_match_pri[spec->type]; | |
2347 | if (!(spec->flags & EFX_FILTER_FLAG_RX)) | |
2348 | range += EFX_FARCH_FILTER_MATCH_PRI_COUNT; | |
2349 | ||
2350 | return range << EFX_FARCH_FILTER_INDEX_WIDTH | index; | |
2351 | } | |
2352 | ||
2353 | static inline enum efx_farch_filter_table_id | |
2354 | efx_farch_filter_id_table_id(u32 id) | |
2355 | { | |
2356 | unsigned int range = id >> EFX_FARCH_FILTER_INDEX_WIDTH; | |
2357 | ||
2358 | if (range < ARRAY_SIZE(efx_farch_filter_range_table)) | |
2359 | return efx_farch_filter_range_table[range]; | |
2360 | else | |
2361 | return EFX_FARCH_FILTER_TABLE_COUNT; /* invalid */ | |
2362 | } | |
2363 | ||
2364 | static inline unsigned int efx_farch_filter_id_index(u32 id) | |
2365 | { | |
2366 | return id & EFX_FARCH_FILTER_INDEX_MASK; | |
2367 | } | |
2368 | ||
2369 | u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx) | |
2370 | { | |
2371 | struct efx_farch_filter_state *state = efx->filter_state; | |
2372 | unsigned int range = EFX_FARCH_FILTER_MATCH_PRI_COUNT - 1; | |
2373 | enum efx_farch_filter_table_id table_id; | |
2374 | ||
2375 | do { | |
2376 | table_id = efx_farch_filter_range_table[range]; | |
2377 | if (state->table[table_id].size != 0) | |
2378 | return range << EFX_FARCH_FILTER_INDEX_WIDTH | | |
2379 | state->table[table_id].size; | |
2380 | } while (range--); | |
2381 | ||
2382 | return 0; | |
2383 | } | |
2384 | ||
2385 | s32 efx_farch_filter_insert(struct efx_nic *efx, | |
2386 | struct efx_filter_spec *gen_spec, | |
2387 | bool replace_equal) | |
2388 | { | |
2389 | struct efx_farch_filter_state *state = efx->filter_state; | |
2390 | struct efx_farch_filter_table *table; | |
2391 | struct efx_farch_filter_spec spec; | |
2392 | efx_oword_t filter; | |
2393 | int rep_index, ins_index; | |
2394 | unsigned int depth = 0; | |
2395 | int rc; | |
2396 | ||
2397 | rc = efx_farch_filter_from_gen_spec(&spec, gen_spec); | |
2398 | if (rc) | |
2399 | return rc; | |
2400 | ||
2401 | table = &state->table[efx_farch_filter_spec_table_id(&spec)]; | |
2402 | if (table->size == 0) | |
2403 | return -EINVAL; | |
2404 | ||
2405 | netif_vdbg(efx, hw, efx->net_dev, | |
2406 | "%s: type %d search_limit=%d", __func__, spec.type, | |
2407 | table->search_limit[spec.type]); | |
2408 | ||
2409 | if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) { | |
2410 | /* One filter spec per type */ | |
2411 | BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_UC_DEF != 0); | |
2412 | BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_MC_DEF != | |
2413 | EFX_FARCH_FILTER_MC_DEF - EFX_FARCH_FILTER_UC_DEF); | |
2414 | rep_index = spec.type - EFX_FARCH_FILTER_UC_DEF; | |
2415 | ins_index = rep_index; | |
2416 | ||
2417 | spin_lock_bh(&efx->filter_lock); | |
2418 | } else { | |
2419 | /* Search concurrently for | |
2420 | * (1) a filter to be replaced (rep_index): any filter | |
2421 | * with the same match values, up to the current | |
2422 | * search depth for this type, and | |
2423 | * (2) the insertion point (ins_index): (1) or any | |
2424 | * free slot before it or up to the maximum search | |
2425 | * depth for this priority | |
2426 | * We fail if we cannot find (2). | |
2427 | * | |
2428 | * We can stop once either | |
2429 | * (a) we find (1), in which case we have definitely | |
2430 | * found (2) as well; or | |
2431 | * (b) we have searched exhaustively for (1), and have | |
2432 | * either found (2) or searched exhaustively for it | |
2433 | */ | |
2434 | u32 key = efx_farch_filter_build(&filter, &spec); | |
2435 | unsigned int hash = efx_farch_filter_hash(key); | |
2436 | unsigned int incr = efx_farch_filter_increment(key); | |
2437 | unsigned int max_rep_depth = table->search_limit[spec.type]; | |
2438 | unsigned int max_ins_depth = | |
2439 | spec.priority <= EFX_FILTER_PRI_HINT ? | |
2440 | EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX : | |
2441 | EFX_FARCH_FILTER_CTL_SRCH_MAX; | |
2442 | unsigned int i = hash & (table->size - 1); | |
2443 | ||
2444 | ins_index = -1; | |
2445 | depth = 1; | |
2446 | ||
2447 | spin_lock_bh(&efx->filter_lock); | |
2448 | ||
2449 | for (;;) { | |
2450 | if (!test_bit(i, table->used_bitmap)) { | |
2451 | if (ins_index < 0) | |
2452 | ins_index = i; | |
2453 | } else if (efx_farch_filter_equal(&spec, | |
2454 | &table->spec[i])) { | |
2455 | /* Case (a) */ | |
2456 | if (ins_index < 0) | |
2457 | ins_index = i; | |
2458 | rep_index = i; | |
2459 | break; | |
2460 | } | |
2461 | ||
2462 | if (depth >= max_rep_depth && | |
2463 | (ins_index >= 0 || depth >= max_ins_depth)) { | |
2464 | /* Case (b) */ | |
2465 | if (ins_index < 0) { | |
2466 | rc = -EBUSY; | |
2467 | goto out; | |
2468 | } | |
2469 | rep_index = -1; | |
2470 | break; | |
2471 | } | |
2472 | ||
2473 | i = (i + incr) & (table->size - 1); | |
2474 | ++depth; | |
2475 | } | |
2476 | } | |
2477 | ||
2478 | /* If we found a filter to be replaced, check whether we | |
2479 | * should do so | |
2480 | */ | |
2481 | if (rep_index >= 0) { | |
2482 | struct efx_farch_filter_spec *saved_spec = | |
2483 | &table->spec[rep_index]; | |
2484 | ||
2485 | if (spec.priority == saved_spec->priority && !replace_equal) { | |
2486 | rc = -EEXIST; | |
2487 | goto out; | |
2488 | } | |
7665d1ab | 2489 | if (spec.priority < saved_spec->priority) { |
add72477 BH |
2490 | rc = -EPERM; |
2491 | goto out; | |
2492 | } | |
7665d1ab BH |
2493 | if (saved_spec->priority == EFX_FILTER_PRI_AUTO || |
2494 | saved_spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) | |
2495 | spec.flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; | |
add72477 BH |
2496 | } |
2497 | ||
2498 | /* Insert the filter */ | |
2499 | if (ins_index != rep_index) { | |
2500 | __set_bit(ins_index, table->used_bitmap); | |
2501 | ++table->used; | |
2502 | } | |
2503 | table->spec[ins_index] = spec; | |
2504 | ||
2505 | if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) { | |
2506 | efx_farch_filter_push_rx_config(efx); | |
2507 | } else { | |
2508 | if (table->search_limit[spec.type] < depth) { | |
2509 | table->search_limit[spec.type] = depth; | |
2510 | if (spec.flags & EFX_FILTER_FLAG_TX) | |
2511 | efx_farch_filter_push_tx_limits(efx); | |
2512 | else | |
2513 | efx_farch_filter_push_rx_config(efx); | |
2514 | } | |
2515 | ||
2516 | efx_writeo(efx, &filter, | |
2517 | table->offset + table->step * ins_index); | |
2518 | ||
2519 | /* If we were able to replace a filter by inserting | |
2520 | * at a lower depth, clear the replaced filter | |
2521 | */ | |
2522 | if (ins_index != rep_index && rep_index >= 0) | |
2523 | efx_farch_filter_table_clear_entry(efx, table, | |
2524 | rep_index); | |
2525 | } | |
2526 | ||
2527 | netif_vdbg(efx, hw, efx->net_dev, | |
2528 | "%s: filter type %d index %d rxq %u set", | |
2529 | __func__, spec.type, ins_index, spec.dmaq_id); | |
2530 | rc = efx_farch_filter_make_id(&spec, ins_index); | |
2531 | ||
2532 | out: | |
2533 | spin_unlock_bh(&efx->filter_lock); | |
2534 | return rc; | |
2535 | } | |
2536 | ||
2537 | static void | |
2538 | efx_farch_filter_table_clear_entry(struct efx_nic *efx, | |
2539 | struct efx_farch_filter_table *table, | |
2540 | unsigned int filter_idx) | |
2541 | { | |
2542 | static efx_oword_t filter; | |
2543 | ||
14990a5d | 2544 | EFX_WARN_ON_PARANOID(!test_bit(filter_idx, table->used_bitmap)); |
8803e150 | 2545 | BUG_ON(table->offset == 0); /* can't clear MAC default filters */ |
14990a5d BH |
2546 | |
2547 | __clear_bit(filter_idx, table->used_bitmap); | |
2548 | --table->used; | |
2549 | memset(&table->spec[filter_idx], 0, sizeof(table->spec[0])); | |
2550 | ||
2551 | efx_writeo(efx, &filter, table->offset + table->step * filter_idx); | |
2552 | ||
2553 | /* If this filter required a greater search depth than | |
2554 | * any other, the search limit for its type can now be | |
2555 | * decreased. However, it is hard to determine that | |
2556 | * unless the table has become completely empty - in | |
2557 | * which case, all its search limits can be set to 0. | |
2558 | */ | |
2559 | if (unlikely(table->used == 0)) { | |
2560 | memset(table->search_limit, 0, sizeof(table->search_limit)); | |
2561 | if (table->id == EFX_FARCH_FILTER_TABLE_TX_MAC) | |
2562 | efx_farch_filter_push_tx_limits(efx); | |
2563 | else | |
2564 | efx_farch_filter_push_rx_config(efx); | |
2565 | } | |
2566 | } | |
2567 | ||
2568 | static int efx_farch_filter_remove(struct efx_nic *efx, | |
2569 | struct efx_farch_filter_table *table, | |
2570 | unsigned int filter_idx, | |
2571 | enum efx_filter_priority priority) | |
2572 | { | |
2573 | struct efx_farch_filter_spec *spec = &table->spec[filter_idx]; | |
2574 | ||
2575 | if (!test_bit(filter_idx, table->used_bitmap) || | |
f7284802 | 2576 | spec->priority != priority) |
14990a5d BH |
2577 | return -ENOENT; |
2578 | ||
7665d1ab | 2579 | if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { |
b59e6ef8 | 2580 | efx_farch_filter_init_rx_auto(efx, spec); |
add72477 | 2581 | efx_farch_filter_push_rx_config(efx); |
14990a5d BH |
2582 | } else { |
2583 | efx_farch_filter_table_clear_entry(efx, table, filter_idx); | |
add72477 | 2584 | } |
14990a5d BH |
2585 | |
2586 | return 0; | |
add72477 BH |
2587 | } |
2588 | ||
2589 | int efx_farch_filter_remove_safe(struct efx_nic *efx, | |
2590 | enum efx_filter_priority priority, | |
2591 | u32 filter_id) | |
2592 | { | |
2593 | struct efx_farch_filter_state *state = efx->filter_state; | |
2594 | enum efx_farch_filter_table_id table_id; | |
2595 | struct efx_farch_filter_table *table; | |
2596 | unsigned int filter_idx; | |
2597 | struct efx_farch_filter_spec *spec; | |
2598 | int rc; | |
2599 | ||
2600 | table_id = efx_farch_filter_id_table_id(filter_id); | |
2601 | if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT) | |
2602 | return -ENOENT; | |
2603 | table = &state->table[table_id]; | |
2604 | ||
2605 | filter_idx = efx_farch_filter_id_index(filter_id); | |
2606 | if (filter_idx >= table->size) | |
2607 | return -ENOENT; | |
2608 | spec = &table->spec[filter_idx]; | |
2609 | ||
2610 | spin_lock_bh(&efx->filter_lock); | |
14990a5d | 2611 | rc = efx_farch_filter_remove(efx, table, filter_idx, priority); |
add72477 BH |
2612 | spin_unlock_bh(&efx->filter_lock); |
2613 | ||
2614 | return rc; | |
2615 | } | |
2616 | ||
2617 | int efx_farch_filter_get_safe(struct efx_nic *efx, | |
2618 | enum efx_filter_priority priority, | |
2619 | u32 filter_id, struct efx_filter_spec *spec_buf) | |
2620 | { | |
2621 | struct efx_farch_filter_state *state = efx->filter_state; | |
2622 | enum efx_farch_filter_table_id table_id; | |
2623 | struct efx_farch_filter_table *table; | |
2624 | struct efx_farch_filter_spec *spec; | |
2625 | unsigned int filter_idx; | |
2626 | int rc; | |
2627 | ||
2628 | table_id = efx_farch_filter_id_table_id(filter_id); | |
2629 | if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT) | |
2630 | return -ENOENT; | |
2631 | table = &state->table[table_id]; | |
2632 | ||
2633 | filter_idx = efx_farch_filter_id_index(filter_id); | |
2634 | if (filter_idx >= table->size) | |
2635 | return -ENOENT; | |
2636 | spec = &table->spec[filter_idx]; | |
2637 | ||
2638 | spin_lock_bh(&efx->filter_lock); | |
2639 | ||
2640 | if (test_bit(filter_idx, table->used_bitmap) && | |
2641 | spec->priority == priority) { | |
2642 | efx_farch_filter_to_gen_spec(spec_buf, spec); | |
2643 | rc = 0; | |
2644 | } else { | |
2645 | rc = -ENOENT; | |
2646 | } | |
2647 | ||
2648 | spin_unlock_bh(&efx->filter_lock); | |
2649 | ||
2650 | return rc; | |
2651 | } | |
2652 | ||
2653 | static void | |
2654 | efx_farch_filter_table_clear(struct efx_nic *efx, | |
2655 | enum efx_farch_filter_table_id table_id, | |
2656 | enum efx_filter_priority priority) | |
2657 | { | |
2658 | struct efx_farch_filter_state *state = efx->filter_state; | |
2659 | struct efx_farch_filter_table *table = &state->table[table_id]; | |
2660 | unsigned int filter_idx; | |
2661 | ||
2662 | spin_lock_bh(&efx->filter_lock); | |
7665d1ab BH |
2663 | for (filter_idx = 0; filter_idx < table->size; ++filter_idx) { |
2664 | if (table->spec[filter_idx].priority != EFX_FILTER_PRI_AUTO) | |
2665 | efx_farch_filter_remove(efx, table, | |
2666 | filter_idx, priority); | |
2667 | } | |
add72477 BH |
2668 | spin_unlock_bh(&efx->filter_lock); |
2669 | } | |
2670 | ||
fbd79120 | 2671 | int efx_farch_filter_clear_rx(struct efx_nic *efx, |
add72477 BH |
2672 | enum efx_filter_priority priority) |
2673 | { | |
2674 | efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_IP, | |
2675 | priority); | |
2676 | efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_MAC, | |
2677 | priority); | |
8803e150 BH |
2678 | efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_DEF, |
2679 | priority); | |
fbd79120 | 2680 | return 0; |
add72477 BH |
2681 | } |
2682 | ||
2683 | u32 efx_farch_filter_count_rx_used(struct efx_nic *efx, | |
2684 | enum efx_filter_priority priority) | |
2685 | { | |
2686 | struct efx_farch_filter_state *state = efx->filter_state; | |
2687 | enum efx_farch_filter_table_id table_id; | |
2688 | struct efx_farch_filter_table *table; | |
2689 | unsigned int filter_idx; | |
2690 | u32 count = 0; | |
2691 | ||
2692 | spin_lock_bh(&efx->filter_lock); | |
2693 | ||
2694 | for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP; | |
2695 | table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF; | |
2696 | table_id++) { | |
2697 | table = &state->table[table_id]; | |
2698 | for (filter_idx = 0; filter_idx < table->size; filter_idx++) { | |
2699 | if (test_bit(filter_idx, table->used_bitmap) && | |
2700 | table->spec[filter_idx].priority == priority) | |
2701 | ++count; | |
2702 | } | |
2703 | } | |
2704 | ||
2705 | spin_unlock_bh(&efx->filter_lock); | |
2706 | ||
2707 | return count; | |
2708 | } | |
2709 | ||
2710 | s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx, | |
2711 | enum efx_filter_priority priority, | |
2712 | u32 *buf, u32 size) | |
2713 | { | |
2714 | struct efx_farch_filter_state *state = efx->filter_state; | |
2715 | enum efx_farch_filter_table_id table_id; | |
2716 | struct efx_farch_filter_table *table; | |
2717 | unsigned int filter_idx; | |
2718 | s32 count = 0; | |
2719 | ||
2720 | spin_lock_bh(&efx->filter_lock); | |
2721 | ||
2722 | for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP; | |
2723 | table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF; | |
2724 | table_id++) { | |
2725 | table = &state->table[table_id]; | |
2726 | for (filter_idx = 0; filter_idx < table->size; filter_idx++) { | |
2727 | if (test_bit(filter_idx, table->used_bitmap) && | |
2728 | table->spec[filter_idx].priority == priority) { | |
2729 | if (count == size) { | |
2730 | count = -EMSGSIZE; | |
2731 | goto out; | |
2732 | } | |
2733 | buf[count++] = efx_farch_filter_make_id( | |
2734 | &table->spec[filter_idx], filter_idx); | |
2735 | } | |
2736 | } | |
2737 | } | |
2738 | out: | |
2739 | spin_unlock_bh(&efx->filter_lock); | |
2740 | ||
2741 | return count; | |
2742 | } | |
2743 | ||
2744 | /* Restore filter stater after reset */ | |
2745 | void efx_farch_filter_table_restore(struct efx_nic *efx) | |
2746 | { | |
2747 | struct efx_farch_filter_state *state = efx->filter_state; | |
2748 | enum efx_farch_filter_table_id table_id; | |
2749 | struct efx_farch_filter_table *table; | |
2750 | efx_oword_t filter; | |
2751 | unsigned int filter_idx; | |
2752 | ||
2753 | spin_lock_bh(&efx->filter_lock); | |
2754 | ||
2755 | for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) { | |
2756 | table = &state->table[table_id]; | |
2757 | ||
2758 | /* Check whether this is a regular register table */ | |
2759 | if (table->step == 0) | |
2760 | continue; | |
2761 | ||
2762 | for (filter_idx = 0; filter_idx < table->size; filter_idx++) { | |
2763 | if (!test_bit(filter_idx, table->used_bitmap)) | |
2764 | continue; | |
2765 | efx_farch_filter_build(&filter, &table->spec[filter_idx]); | |
2766 | efx_writeo(efx, &filter, | |
2767 | table->offset + table->step * filter_idx); | |
2768 | } | |
2769 | } | |
2770 | ||
2771 | efx_farch_filter_push_rx_config(efx); | |
2772 | efx_farch_filter_push_tx_limits(efx); | |
2773 | ||
2774 | spin_unlock_bh(&efx->filter_lock); | |
2775 | } | |
2776 | ||
2777 | void efx_farch_filter_table_remove(struct efx_nic *efx) | |
2778 | { | |
2779 | struct efx_farch_filter_state *state = efx->filter_state; | |
2780 | enum efx_farch_filter_table_id table_id; | |
2781 | ||
2782 | for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) { | |
2783 | kfree(state->table[table_id].used_bitmap); | |
2784 | vfree(state->table[table_id].spec); | |
2785 | } | |
2786 | kfree(state); | |
2787 | } | |
2788 | ||
2789 | int efx_farch_filter_table_probe(struct efx_nic *efx) | |
2790 | { | |
2791 | struct efx_farch_filter_state *state; | |
2792 | struct efx_farch_filter_table *table; | |
2793 | unsigned table_id; | |
2794 | ||
2795 | state = kzalloc(sizeof(struct efx_farch_filter_state), GFP_KERNEL); | |
2796 | if (!state) | |
2797 | return -ENOMEM; | |
2798 | efx->filter_state = state; | |
2799 | ||
2800 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { | |
2801 | table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP]; | |
2802 | table->id = EFX_FARCH_FILTER_TABLE_RX_IP; | |
2803 | table->offset = FR_BZ_RX_FILTER_TBL0; | |
2804 | table->size = FR_BZ_RX_FILTER_TBL0_ROWS; | |
2805 | table->step = FR_BZ_RX_FILTER_TBL0_STEP; | |
2806 | } | |
2807 | ||
2808 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { | |
2809 | table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC]; | |
2810 | table->id = EFX_FARCH_FILTER_TABLE_RX_MAC; | |
2811 | table->offset = FR_CZ_RX_MAC_FILTER_TBL0; | |
2812 | table->size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS; | |
2813 | table->step = FR_CZ_RX_MAC_FILTER_TBL0_STEP; | |
2814 | ||
2815 | table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF]; | |
2816 | table->id = EFX_FARCH_FILTER_TABLE_RX_DEF; | |
2817 | table->size = EFX_FARCH_FILTER_SIZE_RX_DEF; | |
2818 | ||
2819 | table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC]; | |
2820 | table->id = EFX_FARCH_FILTER_TABLE_TX_MAC; | |
2821 | table->offset = FR_CZ_TX_MAC_FILTER_TBL0; | |
2822 | table->size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS; | |
2823 | table->step = FR_CZ_TX_MAC_FILTER_TBL0_STEP; | |
2824 | } | |
2825 | ||
2826 | for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) { | |
2827 | table = &state->table[table_id]; | |
2828 | if (table->size == 0) | |
2829 | continue; | |
2830 | table->used_bitmap = kcalloc(BITS_TO_LONGS(table->size), | |
2831 | sizeof(unsigned long), | |
2832 | GFP_KERNEL); | |
2833 | if (!table->used_bitmap) | |
2834 | goto fail; | |
2835 | table->spec = vzalloc(table->size * sizeof(*table->spec)); | |
2836 | if (!table->spec) | |
2837 | goto fail; | |
2838 | } | |
2839 | ||
8803e150 BH |
2840 | table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF]; |
2841 | if (table->size) { | |
add72477 | 2842 | /* RX default filters must always exist */ |
8803e150 | 2843 | struct efx_farch_filter_spec *spec; |
add72477 | 2844 | unsigned i; |
8803e150 BH |
2845 | |
2846 | for (i = 0; i < EFX_FARCH_FILTER_SIZE_RX_DEF; i++) { | |
2847 | spec = &table->spec[i]; | |
2848 | spec->type = EFX_FARCH_FILTER_UC_DEF + i; | |
b59e6ef8 | 2849 | efx_farch_filter_init_rx_auto(efx, spec); |
8803e150 BH |
2850 | __set_bit(i, table->used_bitmap); |
2851 | } | |
add72477 BH |
2852 | } |
2853 | ||
2854 | efx_farch_filter_push_rx_config(efx); | |
2855 | ||
2856 | return 0; | |
2857 | ||
2858 | fail: | |
2859 | efx_farch_filter_table_remove(efx); | |
2860 | return -ENOMEM; | |
2861 | } | |
2862 | ||
2863 | /* Update scatter enable flags for filters pointing to our own RX queues */ | |
2864 | void efx_farch_filter_update_rx_scatter(struct efx_nic *efx) | |
2865 | { | |
2866 | struct efx_farch_filter_state *state = efx->filter_state; | |
2867 | enum efx_farch_filter_table_id table_id; | |
2868 | struct efx_farch_filter_table *table; | |
2869 | efx_oword_t filter; | |
2870 | unsigned int filter_idx; | |
2871 | ||
2872 | spin_lock_bh(&efx->filter_lock); | |
2873 | ||
2874 | for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP; | |
2875 | table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF; | |
2876 | table_id++) { | |
2877 | table = &state->table[table_id]; | |
2878 | ||
2879 | for (filter_idx = 0; filter_idx < table->size; filter_idx++) { | |
2880 | if (!test_bit(filter_idx, table->used_bitmap) || | |
2881 | table->spec[filter_idx].dmaq_id >= | |
2882 | efx->n_rx_channels) | |
2883 | continue; | |
2884 | ||
2885 | if (efx->rx_scatter) | |
2886 | table->spec[filter_idx].flags |= | |
2887 | EFX_FILTER_FLAG_RX_SCATTER; | |
2888 | else | |
2889 | table->spec[filter_idx].flags &= | |
2890 | ~EFX_FILTER_FLAG_RX_SCATTER; | |
2891 | ||
2892 | if (table_id == EFX_FARCH_FILTER_TABLE_RX_DEF) | |
2893 | /* Pushed by efx_farch_filter_push_rx_config() */ | |
2894 | continue; | |
2895 | ||
2896 | efx_farch_filter_build(&filter, &table->spec[filter_idx]); | |
2897 | efx_writeo(efx, &filter, | |
2898 | table->offset + table->step * filter_idx); | |
2899 | } | |
2900 | } | |
2901 | ||
2902 | efx_farch_filter_push_rx_config(efx); | |
2903 | ||
2904 | spin_unlock_bh(&efx->filter_lock); | |
2905 | } | |
2906 | ||
2907 | #ifdef CONFIG_RFS_ACCEL | |
2908 | ||
2909 | s32 efx_farch_filter_rfs_insert(struct efx_nic *efx, | |
2910 | struct efx_filter_spec *gen_spec) | |
2911 | { | |
2912 | return efx_farch_filter_insert(efx, gen_spec, true); | |
2913 | } | |
2914 | ||
2915 | bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, | |
2916 | unsigned int index) | |
2917 | { | |
2918 | struct efx_farch_filter_state *state = efx->filter_state; | |
2919 | struct efx_farch_filter_table *table = | |
2920 | &state->table[EFX_FARCH_FILTER_TABLE_RX_IP]; | |
2921 | ||
2922 | if (test_bit(index, table->used_bitmap) && | |
2923 | table->spec[index].priority == EFX_FILTER_PRI_HINT && | |
2924 | rps_may_expire_flow(efx->net_dev, table->spec[index].dmaq_id, | |
2925 | flow_id, index)) { | |
2926 | efx_farch_filter_table_clear_entry(efx, table, index); | |
2927 | return true; | |
2928 | } | |
2929 | ||
2930 | return false; | |
2931 | } | |
2932 | ||
2933 | #endif /* CONFIG_RFS_ACCEL */ | |
964e6135 BH |
2934 | |
2935 | void efx_farch_filter_sync_rx_mode(struct efx_nic *efx) | |
2936 | { | |
2937 | struct net_device *net_dev = efx->net_dev; | |
2938 | struct netdev_hw_addr *ha; | |
2939 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
2940 | u32 crc; | |
2941 | int bit; | |
2942 | ||
f650fb45 EC |
2943 | if (!efx_dev_registered(efx)) |
2944 | return; | |
2945 | ||
964e6135 BH |
2946 | netif_addr_lock_bh(net_dev); |
2947 | ||
2948 | efx->unicast_filter = !(net_dev->flags & IFF_PROMISC); | |
2949 | ||
2950 | /* Build multicast hash table */ | |
2951 | if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { | |
2952 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
2953 | } else { | |
2954 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
2955 | netdev_for_each_mc_addr(ha, net_dev) { | |
2956 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
2957 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
2958 | __set_bit_le(bit, mc_hash); | |
2959 | } | |
2960 | ||
2961 | /* Broadcast packets go through the multicast hash filter. | |
2962 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
2963 | * so we always add bit 0xff to the mask. | |
2964 | */ | |
2965 | __set_bit_le(0xff, mc_hash); | |
2966 | } | |
2967 | ||
2968 | netif_addr_unlock_bh(net_dev); | |
2969 | } |