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sfc: Prepare for RX scatter on EF10
[deliverable/linux.git] / drivers / net / ethernet / sfc / farch.c
CommitLineData
86094f7f
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2011 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/interrupt.h>
14#include <linux/pci.h>
15#include <linux/module.h>
16#include <linux/seq_file.h>
964e6135 17#include <linux/crc32.h>
86094f7f
BH		 18#include "net_driver.h"
19#include "bitfield.h"
20#include "efx.h"
21#include "nic.h"
22#include "farch_regs.h"
23#include "io.h"
24#include "workarounds.h"
25
26/* Falcon-architecture (SFC4000 and SFC9000-family) support */
27
28/**************************************************************************
29 *
30 * Configurable values
31 *
32 **************************************************************************
33 */
34
35/* This is set to 16 for a good reason. In summary, if larger than
36 * 16, the descriptor cache holds more than a default socket
37 * buffer's worth of packets (for UDP we can only have at most one
38 * socket buffer's worth outstanding). This combined with the fact
39 * that we only get 1 TX event per descriptor cache means the NIC
40 * goes idle.
41 */
42#define TX_DC_ENTRIES 16
43#define TX_DC_ENTRIES_ORDER 1
44
45#define RX_DC_ENTRIES 64
46#define RX_DC_ENTRIES_ORDER 3
47
48/* If EFX_MAX_INT_ERRORS internal errors occur within
49 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
50 * disable it.
51 */
52#define EFX_INT_ERROR_EXPIRE 3600
53#define EFX_MAX_INT_ERRORS 5
54
55/* Depth of RX flush request fifo */
56#define EFX_RX_FLUSH_COUNT 4
57
58/* Driver generated events */
59#define _EFX_CHANNEL_MAGIC_TEST 0x000101
60#define _EFX_CHANNEL_MAGIC_FILL 0x000102
61#define _EFX_CHANNEL_MAGIC_RX_DRAIN 0x000103
62#define _EFX_CHANNEL_MAGIC_TX_DRAIN 0x000104
63
64#define _EFX_CHANNEL_MAGIC(_code, _data) ((_code) << 8 | (_data))
65#define _EFX_CHANNEL_MAGIC_CODE(_magic) ((_magic) >> 8)
66
67#define EFX_CHANNEL_MAGIC_TEST(_channel) \
68 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel)
69#define EFX_CHANNEL_MAGIC_FILL(_rx_queue) \
70 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL, \
71 efx_rx_queue_index(_rx_queue))
72#define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue) \
73 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN, \
74 efx_rx_queue_index(_rx_queue))
75#define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue) \
76 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN, \
77 (_tx_queue)->queue)
78
79static void efx_farch_magic_event(struct efx_channel *channel, u32 magic);
80
81/**************************************************************************
82 *
83 * Hardware access
84 *
85 **************************************************************************/
86
87static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
88 unsigned int index)
89{
90 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
91 value, index);
92}
93
94static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
95 const efx_oword_t *mask)
96{
97 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
98 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
99}
100
101int efx_farch_test_registers(struct efx_nic *efx,
102 const struct efx_farch_register_test *regs,
103 size_t n_regs)
104{
105 unsigned address = 0, i, j;
106 efx_oword_t mask, imask, original, reg, buf;
107
108 for (i = 0; i < n_regs; ++i) {
109 address = regs[i].address;
110 mask = imask = regs[i].mask;
111 EFX_INVERT_OWORD(imask);
112
113 efx_reado(efx, &original, address);
114
115 /* bit sweep on and off */
116 for (j = 0; j < 128; j++) {
117 if (!EFX_EXTRACT_OWORD32(mask, j, j))
118 continue;
119
120 /* Test this testable bit can be set in isolation */
121 EFX_AND_OWORD(reg, original, mask);
122 EFX_SET_OWORD32(reg, j, j, 1);
123
124 efx_writeo(efx, &reg, address);
125 efx_reado(efx, &buf, address);
126
127 if (efx_masked_compare_oword(&reg, &buf, &mask))
128 goto fail;
129
130 /* Test this testable bit can be cleared in isolation */
131 EFX_OR_OWORD(reg, original, mask);
132 EFX_SET_OWORD32(reg, j, j, 0);
133
134 efx_writeo(efx, &reg, address);
135 efx_reado(efx, &buf, address);
136
137 if (efx_masked_compare_oword(&reg, &buf, &mask))
138 goto fail;
139 }
140
141 efx_writeo(efx, &original, address);
142 }
143
144 return 0;
145
146fail:
147 netif_err(efx, hw, efx->net_dev,
148 "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
149 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
150 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
151 return -EIO;
152}
153
154/**************************************************************************
155 *
156 * Special buffer handling
157 * Special buffers are used for event queues and the TX and RX
158 * descriptor rings.
159 *
160 *************************************************************************/
161
162/*
163 * Initialise a special buffer
164 *
165 * This will define a buffer (previously allocated via
166 * efx_alloc_special_buffer()) in the buffer table, allowing
167 * it to be used for event queues, descriptor rings etc.
168 */
169static void
170efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
171{
172 efx_qword_t buf_desc;
173 unsigned int index;
174 dma_addr_t dma_addr;
175 int i;
176
177 EFX_BUG_ON_PARANOID(!buffer->buf.addr);
178
179 /* Write buffer descriptors to NIC */
180 for (i = 0; i < buffer->entries; i++) {
181 index = buffer->index + i;
182 dma_addr = buffer->buf.dma_addr + (i * EFX_BUF_SIZE);
183 netif_dbg(efx, probe, efx->net_dev,
184 "mapping special buffer %d at %llx\n",
185 index, (unsigned long long)dma_addr);
186 EFX_POPULATE_QWORD_3(buf_desc,
187 FRF_AZ_BUF_ADR_REGION, 0,
188 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
189 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
190 efx_write_buf_tbl(efx, &buf_desc, index);
191 }
192}
193
194/* Unmaps a buffer and clears the buffer table entries */
195static void
196efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
197{
198 efx_oword_t buf_tbl_upd;
199 unsigned int start = buffer->index;
200 unsigned int end = (buffer->index + buffer->entries - 1);
201
202 if (!buffer->entries)
203 return;
204
205 netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
206 buffer->index, buffer->index + buffer->entries - 1);
207
208 EFX_POPULATE_OWORD_4(buf_tbl_upd,
209 FRF_AZ_BUF_UPD_CMD, 0,
210 FRF_AZ_BUF_CLR_CMD, 1,
211 FRF_AZ_BUF_CLR_END_ID, end,
212 FRF_AZ_BUF_CLR_START_ID, start);
213 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
214}
215
216/*
217 * Allocate a new special buffer
218 *
219 * This allocates memory for a new buffer, clears it and allocates a
220 * new buffer ID range. It does not write into the buffer table.
221 *
222 * This call will allocate 4KB buffers, since 8KB buffers can't be
223 * used for event queues and descriptor rings.
224 */
225static int efx_alloc_special_buffer(struct efx_nic *efx,
226 struct efx_special_buffer *buffer,
227 unsigned int len)
228{
229 len = ALIGN(len, EFX_BUF_SIZE);
230
231 if (efx_nic_alloc_buffer(efx, &buffer->buf, len, GFP_KERNEL))
232 return -ENOMEM;
233 buffer->entries = len / EFX_BUF_SIZE;
234 BUG_ON(buffer->buf.dma_addr & (EFX_BUF_SIZE - 1));
235
236 /* Select new buffer ID */
237 buffer->index = efx->next_buffer_table;
238 efx->next_buffer_table += buffer->entries;
239#ifdef CONFIG_SFC_SRIOV
240 BUG_ON(efx_sriov_enabled(efx) &&
241 efx->vf_buftbl_base < efx->next_buffer_table);
242#endif
243
244 netif_dbg(efx, probe, efx->net_dev,
245 "allocating special buffers %d-%d at %llx+%x "
246 "(virt %p phys %llx)\n", buffer->index,
247 buffer->index + buffer->entries - 1,
248 (u64)buffer->buf.dma_addr, len,
249 buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
250
251 return 0;
252}
253
254static void
255efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
256{
257 if (!buffer->buf.addr)
258 return;
259
260 netif_dbg(efx, hw, efx->net_dev,
261 "deallocating special buffers %d-%d at %llx+%x "
262 "(virt %p phys %llx)\n", buffer->index,
263 buffer->index + buffer->entries - 1,
264 (u64)buffer->buf.dma_addr, buffer->buf.len,
265 buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
266
267 efx_nic_free_buffer(efx, &buffer->buf);
268 buffer->entries = 0;
269}
270
271/**************************************************************************
272 *
273 * TX path
274 *
275 **************************************************************************/
276
277/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
278static inline void efx_farch_notify_tx_desc(struct efx_tx_queue *tx_queue)
279{
280 unsigned write_ptr;
281 efx_dword_t reg;
282
283 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
284 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
285 efx_writed_page(tx_queue->efx, &reg,
286 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
287}
288
289/* Write pointer and first descriptor for TX descriptor ring */
290static inline void efx_farch_push_tx_desc(struct efx_tx_queue *tx_queue,
291 const efx_qword_t *txd)
292{
293 unsigned write_ptr;
294 efx_oword_t reg;
295
296 BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
297 BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
298
299 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
300 EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
301 FRF_AZ_TX_DESC_WPTR, write_ptr);
302 reg.qword[0] = *txd;
303 efx_writeo_page(tx_queue->efx, &reg,
304 FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
305}
306
307
308/* For each entry inserted into the software descriptor ring, create a
309 * descriptor in the hardware TX descriptor ring (in host memory), and
310 * write a doorbell.
311 */
312void efx_farch_tx_write(struct efx_tx_queue *tx_queue)
313{
314
315 struct efx_tx_buffer *buffer;
316 efx_qword_t *txd;
317 unsigned write_ptr;
318 unsigned old_write_count = tx_queue->write_count;
319
320 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
321
322 do {
323 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
324 buffer = &tx_queue->buffer[write_ptr];
325 txd = efx_tx_desc(tx_queue, write_ptr);
326 ++tx_queue->write_count;
327
328 /* Create TX descriptor ring entry */
329 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
330 EFX_POPULATE_QWORD_4(*txd,
331 FSF_AZ_TX_KER_CONT,
332 buffer->flags & EFX_TX_BUF_CONT,
333 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
334 FSF_AZ_TX_KER_BUF_REGION, 0,
335 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
336 } while (tx_queue->write_count != tx_queue->insert_count);
337
338 wmb(); /* Ensure descriptors are written before they are fetched */
339
340 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
341 txd = efx_tx_desc(tx_queue,
342 old_write_count & tx_queue->ptr_mask);
343 efx_farch_push_tx_desc(tx_queue, txd);
344 ++tx_queue->pushes;
345 } else {
346 efx_farch_notify_tx_desc(tx_queue);
347 }
348}
349
350/* Allocate hardware resources for a TX queue */
351int efx_farch_tx_probe(struct efx_tx_queue *tx_queue)
352{
353 struct efx_nic *efx = tx_queue->efx;
354 unsigned entries;
355
356 entries = tx_queue->ptr_mask + 1;
357 return efx_alloc_special_buffer(efx, &tx_queue->txd,
358 entries * sizeof(efx_qword_t));
359}
360
361void efx_farch_tx_init(struct efx_tx_queue *tx_queue)
362{
363 struct efx_nic *efx = tx_queue->efx;
364 efx_oword_t reg;
365
366 /* Pin TX descriptor ring */
367 efx_init_special_buffer(efx, &tx_queue->txd);
368
369 /* Push TX descriptor ring to card */
370 EFX_POPULATE_OWORD_10(reg,
371 FRF_AZ_TX_DESCQ_EN, 1,
372 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
373 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
374 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
375 FRF_AZ_TX_DESCQ_EVQ_ID,
376 tx_queue->channel->channel,
377 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
378 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
379 FRF_AZ_TX_DESCQ_SIZE,
380 __ffs(tx_queue->txd.entries),
381 FRF_AZ_TX_DESCQ_TYPE, 0,
382 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
383
384 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
385 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
386 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
387 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS,
388 !csum);
389 }
390
391 efx_writeo_table(efx, &reg, efx->type->txd_ptr_tbl_base,
392 tx_queue->queue);
393
394 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
395 /* Only 128 bits in this register */
396 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
397
398 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
399 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
400 __clear_bit_le(tx_queue->queue, &reg);
401 else
402 __set_bit_le(tx_queue->queue, &reg);
403 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
404 }
405
406 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
407 EFX_POPULATE_OWORD_1(reg,
408 FRF_BZ_TX_PACE,
409 (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
410 FFE_BZ_TX_PACE_OFF :
411 FFE_BZ_TX_PACE_RESERVED);
412 efx_writeo_table(efx, &reg, FR_BZ_TX_PACE_TBL,
413 tx_queue->queue);
414 }
415}
416
417static void efx_farch_flush_tx_queue(struct efx_tx_queue *tx_queue)
418{
419 struct efx_nic *efx = tx_queue->efx;
420 efx_oword_t tx_flush_descq;
421
422 WARN_ON(atomic_read(&tx_queue->flush_outstanding));
423 atomic_set(&tx_queue->flush_outstanding, 1);
424
425 EFX_POPULATE_OWORD_2(tx_flush_descq,
426 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
427 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
428 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
429}
430
431void efx_farch_tx_fini(struct efx_tx_queue *tx_queue)
432{
433 struct efx_nic *efx = tx_queue->efx;
434 efx_oword_t tx_desc_ptr;
435
436 /* Remove TX descriptor ring from card */
437 EFX_ZERO_OWORD(tx_desc_ptr);
438 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
439 tx_queue->queue);
440
441 /* Unpin TX descriptor ring */
442 efx_fini_special_buffer(efx, &tx_queue->txd);
443}
444
445/* Free buffers backing TX queue */
446void efx_farch_tx_remove(struct efx_tx_queue *tx_queue)
447{
448 efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
449}
450
451/**************************************************************************
452 *
453 * RX path
454 *
455 **************************************************************************/
456
457/* This creates an entry in the RX descriptor queue */
458static inline void
459efx_farch_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
460{
461 struct efx_rx_buffer *rx_buf;
462 efx_qword_t *rxd;
463
464 rxd = efx_rx_desc(rx_queue, index);
465 rx_buf = efx_rx_buffer(rx_queue, index);
466 EFX_POPULATE_QWORD_3(*rxd,
467 FSF_AZ_RX_KER_BUF_SIZE,
468 rx_buf->len -
469 rx_queue->efx->type->rx_buffer_padding,
470 FSF_AZ_RX_KER_BUF_REGION, 0,
471 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
472}
473
474/* This writes to the RX_DESC_WPTR register for the specified receive
475 * descriptor ring.
476 */
477void efx_farch_rx_write(struct efx_rx_queue *rx_queue)
478{
479 struct efx_nic *efx = rx_queue->efx;
480 efx_dword_t reg;
481 unsigned write_ptr;
482
483 while (rx_queue->notified_count != rx_queue->added_count) {
484 efx_farch_build_rx_desc(
485 rx_queue,
486 rx_queue->notified_count & rx_queue->ptr_mask);
487 ++rx_queue->notified_count;
488 }
489
490 wmb();
491 write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
492 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
493 efx_writed_page(efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
494 efx_rx_queue_index(rx_queue));
495}
496
497int efx_farch_rx_probe(struct efx_rx_queue *rx_queue)
498{
499 struct efx_nic *efx = rx_queue->efx;
500 unsigned entries;
501
502 entries = rx_queue->ptr_mask + 1;
503 return efx_alloc_special_buffer(efx, &rx_queue->rxd,
504 entries * sizeof(efx_qword_t));
505}
506
507void efx_farch_rx_init(struct efx_rx_queue *rx_queue)
508{
509 efx_oword_t rx_desc_ptr;
510 struct efx_nic *efx = rx_queue->efx;
511 bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
512 bool iscsi_digest_en = is_b0;
513 bool jumbo_en;
514
515 /* For kernel-mode queues in Falcon A1, the JUMBO flag enables
516 * DMA to continue after a PCIe page boundary (and scattering
517 * is not possible). In Falcon B0 and Siena, it enables
518 * scatter.
519 */
520 jumbo_en = !is_b0 || efx->rx_scatter;
521
522 netif_dbg(efx, hw, efx->net_dev,
523 "RX queue %d ring in special buffers %d-%d\n",
524 efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
525 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
526
527 rx_queue->scatter_n = 0;
528
529 /* Pin RX descriptor ring */
530 efx_init_special_buffer(efx, &rx_queue->rxd);
531
532 /* Push RX descriptor ring to card */
533 EFX_POPULATE_OWORD_10(rx_desc_ptr,
534 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
535 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
536 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
537 FRF_AZ_RX_DESCQ_EVQ_ID,
538 efx_rx_queue_channel(rx_queue)->channel,
539 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
540 FRF_AZ_RX_DESCQ_LABEL,
541 efx_rx_queue_index(rx_queue),
542 FRF_AZ_RX_DESCQ_SIZE,
543 __ffs(rx_queue->rxd.entries),
544 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
545 FRF_AZ_RX_DESCQ_JUMBO, jumbo_en,
546 FRF_AZ_RX_DESCQ_EN, 1);
547 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
548 efx_rx_queue_index(rx_queue));
549}
550
551static void efx_farch_flush_rx_queue(struct efx_rx_queue *rx_queue)
552{
553 struct efx_nic *efx = rx_queue->efx;
554 efx_oword_t rx_flush_descq;
555
556 EFX_POPULATE_OWORD_2(rx_flush_descq,
557 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
558 FRF_AZ_RX_FLUSH_DESCQ,
559 efx_rx_queue_index(rx_queue));
560 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
561}
562
563void efx_farch_rx_fini(struct efx_rx_queue *rx_queue)
564{
565 efx_oword_t rx_desc_ptr;
566 struct efx_nic *efx = rx_queue->efx;
567
568 /* Remove RX descriptor ring from card */
569 EFX_ZERO_OWORD(rx_desc_ptr);
570 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
571 efx_rx_queue_index(rx_queue));
572
573 /* Unpin RX descriptor ring */
574 efx_fini_special_buffer(efx, &rx_queue->rxd);
575}
576
577/* Free buffers backing RX queue */
578void efx_farch_rx_remove(struct efx_rx_queue *rx_queue)
579{
580 efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
581}
582
583/**************************************************************************
584 *
585 * Flush handling
586 *
587 **************************************************************************/
588
589/* efx_farch_flush_queues() must be woken up when all flushes are completed,
590 * or more RX flushes can be kicked off.
591 */
592static bool efx_farch_flush_wake(struct efx_nic *efx)
593{
594 /* Ensure that all updates are visible to efx_farch_flush_queues() */
595 smp_mb();
596
597 return (atomic_read(&efx->drain_pending) == 0 ||
598 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT
599 && atomic_read(&efx->rxq_flush_pending) > 0));
600}
601
602static bool efx_check_tx_flush_complete(struct efx_nic *efx)
603{
604 bool i = true;
605 efx_oword_t txd_ptr_tbl;
606 struct efx_channel *channel;
607 struct efx_tx_queue *tx_queue;
608
609 efx_for_each_channel(channel, efx) {
610 efx_for_each_channel_tx_queue(tx_queue, channel) {
611 efx_reado_table(efx, &txd_ptr_tbl,
612 FR_BZ_TX_DESC_PTR_TBL, tx_queue->queue);
613 if (EFX_OWORD_FIELD(txd_ptr_tbl,
614 FRF_AZ_TX_DESCQ_FLUSH) ||
615 EFX_OWORD_FIELD(txd_ptr_tbl,
616 FRF_AZ_TX_DESCQ_EN)) {
617 netif_dbg(efx, hw, efx->net_dev,
618 "flush did not complete on TXQ %d\n",
619 tx_queue->queue);
620 i = false;
621 } else if (atomic_cmpxchg(&tx_queue->flush_outstanding,
622 1, 0)) {
623 /* The flush is complete, but we didn't
624 * receive a flush completion event
625 */
626 netif_dbg(efx, hw, efx->net_dev,
627 "flush complete on TXQ %d, so drain "
628 "the queue\n", tx_queue->queue);
629 /* Don't need to increment drain_pending as it
630 * has already been incremented for the queues
631 * which did not drain
632 */
633 efx_farch_magic_event(channel,
634 EFX_CHANNEL_MAGIC_TX_DRAIN(
635 tx_queue));
636 }
637 }
638 }
639
640 return i;
641}
642
643/* Flush all the transmit queues, and continue flushing receive queues until
644 * they're all flushed. Wait for the DRAIN events to be recieved so that there
645 * are no more RX and TX events left on any channel. */
646static int efx_farch_do_flush(struct efx_nic *efx)
647{
648 unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */
649 struct efx_channel *channel;
650 struct efx_rx_queue *rx_queue;
651 struct efx_tx_queue *tx_queue;
652 int rc = 0;
653
654 efx_for_each_channel(channel, efx) {
655 efx_for_each_channel_tx_queue(tx_queue, channel) {
656 atomic_inc(&efx->drain_pending);
657 efx_farch_flush_tx_queue(tx_queue);
658 }
659 efx_for_each_channel_rx_queue(rx_queue, channel) {
660 atomic_inc(&efx->drain_pending);
661 rx_queue->flush_pending = true;
662 atomic_inc(&efx->rxq_flush_pending);
663 }
664 }
665
666 while (timeout && atomic_read(&efx->drain_pending) > 0) {
667 /* If SRIOV is enabled, then offload receive queue flushing to
668 * the firmware (though we will still have to poll for
669 * completion). If that fails, fall back to the old scheme.
670 */
671 if (efx_sriov_enabled(efx)) {
672 rc = efx_mcdi_flush_rxqs(efx);
673 if (!rc)
674 goto wait;
675 }
676
677 /* The hardware supports four concurrent rx flushes, each of
678 * which may need to be retried if there is an outstanding
679 * descriptor fetch
680 */
681 efx_for_each_channel(channel, efx) {
682 efx_for_each_channel_rx_queue(rx_queue, channel) {
683 if (atomic_read(&efx->rxq_flush_outstanding) >=
684 EFX_RX_FLUSH_COUNT)
685 break;
686
687 if (rx_queue->flush_pending) {
688 rx_queue->flush_pending = false;
689 atomic_dec(&efx->rxq_flush_pending);
690 atomic_inc(&efx->rxq_flush_outstanding);
691 efx_farch_flush_rx_queue(rx_queue);
692 }
693 }
694 }
695
696 wait:
697 timeout = wait_event_timeout(efx->flush_wq,
698 efx_farch_flush_wake(efx),
699 timeout);
700 }
701
702 if (atomic_read(&efx->drain_pending) &&
703 !efx_check_tx_flush_complete(efx)) {
704 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues "
705 "(rx %d+%d)\n", atomic_read(&efx->drain_pending),
706 atomic_read(&efx->rxq_flush_outstanding),
707 atomic_read(&efx->rxq_flush_pending));
708 rc = -ETIMEDOUT;
709
710 atomic_set(&efx->drain_pending, 0);
711 atomic_set(&efx->rxq_flush_pending, 0);
712 atomic_set(&efx->rxq_flush_outstanding, 0);
713 }
714
715 return rc;
716}
717
718int efx_farch_fini_dmaq(struct efx_nic *efx)
719{
720 struct efx_channel *channel;
721 struct efx_tx_queue *tx_queue;
722 struct efx_rx_queue *rx_queue;
723 int rc = 0;
724
725 /* Do not attempt to write to the NIC during EEH recovery */
726 if (efx->state != STATE_RECOVERY) {
727 /* Only perform flush if DMA is enabled */
728 if (efx->pci_dev->is_busmaster) {
729 efx->type->prepare_flush(efx);
730 rc = efx_farch_do_flush(efx);
731 efx->type->finish_flush(efx);
732 }
733
734 efx_for_each_channel(channel, efx) {
735 efx_for_each_channel_rx_queue(rx_queue, channel)
736 efx_farch_rx_fini(rx_queue);
737 efx_for_each_channel_tx_queue(tx_queue, channel)
738 efx_farch_tx_fini(tx_queue);
739 }
740 }
741
742 return rc;
743}
744
745/**************************************************************************
746 *
747 * Event queue processing
748 * Event queues are processed by per-channel tasklets.
749 *
750 **************************************************************************/
751
752/* Update a channel's event queue's read pointer (RPTR) register
753 *
754 * This writes the EVQ_RPTR_REG register for the specified channel's
755 * event queue.
756 */
757void efx_farch_ev_read_ack(struct efx_channel *channel)
758{
759 efx_dword_t reg;
760 struct efx_nic *efx = channel->efx;
761
762 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR,
763 channel->eventq_read_ptr & channel->eventq_mask);
764
765 /* For Falcon A1, EVQ_RPTR_KER is documented as having a step size
766 * of 4 bytes, but it is really 16 bytes just like later revisions.
767 */
768 efx_writed(efx, &reg,
769 efx->type->evq_rptr_tbl_base +
770 FR_BZ_EVQ_RPTR_STEP * channel->channel);
771}
772
773/* Use HW to insert a SW defined event */
774void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
775 efx_qword_t *event)
776{
777 efx_oword_t drv_ev_reg;
778
779 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
780 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
781 drv_ev_reg.u32[0] = event->u32[0];
782 drv_ev_reg.u32[1] = event->u32[1];
783 drv_ev_reg.u32[2] = 0;
784 drv_ev_reg.u32[3] = 0;
785 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq);
786 efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV);
787}
788
789static void efx_farch_magic_event(struct efx_channel *channel, u32 magic)
790{
791 efx_qword_t event;
792
793 EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE,
794 FSE_AZ_EV_CODE_DRV_GEN_EV,
795 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
796 efx_farch_generate_event(channel->efx, channel->channel, &event);
797}
798
799/* Handle a transmit completion event
800 *
801 * The NIC batches TX completion events; the message we receive is of
802 * the form "complete all TX events up to this index".
803 */
804static int
805efx_farch_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
806{
807 unsigned int tx_ev_desc_ptr;
808 unsigned int tx_ev_q_label;
809 struct efx_tx_queue *tx_queue;
810 struct efx_nic *efx = channel->efx;
811 int tx_packets = 0;
812
813 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
814 return 0;
815
816 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
817 /* Transmit completion */
818 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
819 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
820 tx_queue = efx_channel_get_tx_queue(
821 channel, tx_ev_q_label % EFX_TXQ_TYPES);
822 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
823 tx_queue->ptr_mask);
824 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
825 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
826 /* Rewrite the FIFO write pointer */
827 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
828 tx_queue = efx_channel_get_tx_queue(
829 channel, tx_ev_q_label % EFX_TXQ_TYPES);
830
831 netif_tx_lock(efx->net_dev);
832 efx_farch_notify_tx_desc(tx_queue);
833 netif_tx_unlock(efx->net_dev);
ab3b8250 834 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR)) {
3de82b91 835 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
86094f7f
BH		 836 } else {
837 netif_err(efx, tx_err, efx->net_dev,
838 "channel %d unexpected TX event "
839 EFX_QWORD_FMT"\n", channel->channel,
840 EFX_QWORD_VAL(*event));
841 }
842
843 return tx_packets;
844}
845
846/* Detect errors included in the rx_evt_pkt_ok bit. */
847static u16 efx_farch_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
848 const efx_qword_t *event)
849{
850 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
851 struct efx_nic *efx = rx_queue->efx;
852 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
853 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
854 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
855 bool rx_ev_other_err, rx_ev_pause_frm;
856 bool rx_ev_hdr_type, rx_ev_mcast_pkt;
857 unsigned rx_ev_pkt_type;
858
859 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
860 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
861 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
862 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
863 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
864 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
865 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
866 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
867 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
868 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
869 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
870 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
871 rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
872 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
873 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
874
875 /* Every error apart from tobe_disc and pause_frm */
876 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
877 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
878 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
879
880 /* Count errors that are not in MAC stats. Ignore expected
881 * checksum errors during self-test. */
882 if (rx_ev_frm_trunc)
883 ++channel->n_rx_frm_trunc;
884 else if (rx_ev_tobe_disc)
885 ++channel->n_rx_tobe_disc;
886 else if (!efx->loopback_selftest) {
887 if (rx_ev_ip_hdr_chksum_err)
888 ++channel->n_rx_ip_hdr_chksum_err;
889 else if (rx_ev_tcp_udp_chksum_err)
890 ++channel->n_rx_tcp_udp_chksum_err;
891 }
892
893 /* TOBE_DISC is expected on unicast mismatches; don't print out an
894 * error message. FRM_TRUNC indicates RXDP dropped the packet due
895 * to a FIFO overflow.
896 */
897#ifdef DEBUG
898 if (rx_ev_other_err && net_ratelimit()) {
899 netif_dbg(efx, rx_err, efx->net_dev,
900 " RX queue %d unexpected RX event "
901 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
902 efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
903 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
904 rx_ev_ip_hdr_chksum_err ?
905 " [IP_HDR_CHKSUM_ERR]" : "",
906 rx_ev_tcp_udp_chksum_err ?
907 " [TCP_UDP_CHKSUM_ERR]" : "",
908 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
909 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
910 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
911 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
912 rx_ev_pause_frm ? " [PAUSE]" : "");
913 }
914#endif
915
916 /* The frame must be discarded if any of these are true. */
917 return (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
918 rx_ev_tobe_disc | rx_ev_pause_frm) ?
919 EFX_RX_PKT_DISCARD : 0;
920}
921
922/* Handle receive events that are not in-order. Return true if this
923 * can be handled as a partial packet discard, false if it's more
924 * serious.
925 */
926static bool
927efx_farch_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
928{
929 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
930 struct efx_nic *efx = rx_queue->efx;
931 unsigned expected, dropped;
932
933 if (rx_queue->scatter_n &&
934 index == ((rx_queue->removed_count + rx_queue->scatter_n - 1) &
935 rx_queue->ptr_mask)) {
936 ++channel->n_rx_nodesc_trunc;
937 return true;
938 }
939
940 expected = rx_queue->removed_count & rx_queue->ptr_mask;
941 dropped = (index - expected) & rx_queue->ptr_mask;
942 netif_info(efx, rx_err, efx->net_dev,
943 "dropped %d events (index=%d expected=%d)\n",
944 dropped, index, expected);
945
946 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
947 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
948 return false;
949}
950
951/* Handle a packet received event
952 *
953 * The NIC gives a "discard" flag if it's a unicast packet with the
954 * wrong destination address
955 * Also "is multicast" and "matches multicast filter" flags can be used to
956 * discard non-matching multicast packets.
957 */
958static void
959efx_farch_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
960{
961 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
962 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
963 unsigned expected_ptr;
964 bool rx_ev_pkt_ok, rx_ev_sop, rx_ev_cont;
965 u16 flags;
966 struct efx_rx_queue *rx_queue;
967 struct efx_nic *efx = channel->efx;
968
969 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
970 return;
971
972 rx_ev_cont = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT);
973 rx_ev_sop = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP);
974 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
975 channel->channel);
976
977 rx_queue = efx_channel_get_rx_queue(channel);
978
979 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
980 expected_ptr = ((rx_queue->removed_count + rx_queue->scatter_n) &
981 rx_queue->ptr_mask);
982
983 /* Check for partial drops and other errors */
984 if (unlikely(rx_ev_desc_ptr != expected_ptr) ||
985 unlikely(rx_ev_sop != (rx_queue->scatter_n == 0))) {
986 if (rx_ev_desc_ptr != expected_ptr &&
987 !efx_farch_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr))
988 return;
989
990 /* Discard all pending fragments */
991 if (rx_queue->scatter_n) {
992 efx_rx_packet(
993 rx_queue,
994 rx_queue->removed_count & rx_queue->ptr_mask,
995 rx_queue->scatter_n, 0, EFX_RX_PKT_DISCARD);
996 rx_queue->removed_count += rx_queue->scatter_n;
997 rx_queue->scatter_n = 0;
998 }
999
1000 /* Return if there is no new fragment */
1001 if (rx_ev_desc_ptr != expected_ptr)
1002 return;
1003
1004 /* Discard new fragment if not SOP */
1005 if (!rx_ev_sop) {
1006 efx_rx_packet(
1007 rx_queue,
1008 rx_queue->removed_count & rx_queue->ptr_mask,
1009 1, 0, EFX_RX_PKT_DISCARD);
1010 ++rx_queue->removed_count;
1011 return;
1012 }
1013 }
1014
1015 ++rx_queue->scatter_n;
1016 if (rx_ev_cont)
1017 return;
1018
1019 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
1020 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
1021 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
1022
1023 if (likely(rx_ev_pkt_ok)) {
1024 /* If packet is marked as OK then we can rely on the
1025 * hardware checksum and classification.
1026 */
1027 flags = 0;
1028 switch (rx_ev_hdr_type) {
1029 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
1030 flags |= EFX_RX_PKT_TCP;
1031 /* fall through */
1032 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
1033 flags |= EFX_RX_PKT_CSUMMED;
1034 /* fall through */
1035 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
1036 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
1037 break;
1038 }
1039 } else {
1040 flags = efx_farch_handle_rx_not_ok(rx_queue, event);
1041 }
1042
1043 /* Detect multicast packets that didn't match the filter */
1044 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
1045 if (rx_ev_mcast_pkt) {
1046 unsigned int rx_ev_mcast_hash_match =
1047 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
1048
1049 if (unlikely(!rx_ev_mcast_hash_match)) {
1050 ++channel->n_rx_mcast_mismatch;
1051 flags |= EFX_RX_PKT_DISCARD;
1052 }
1053 }
1054
1055 channel->irq_mod_score += 2;
1056
1057 /* Handle received packet */
1058 efx_rx_packet(rx_queue,
1059 rx_queue->removed_count & rx_queue->ptr_mask,
1060 rx_queue->scatter_n, rx_ev_byte_cnt, flags);
1061 rx_queue->removed_count += rx_queue->scatter_n;
1062 rx_queue->scatter_n = 0;
1063}
1064
1065/* If this flush done event corresponds to a &struct efx_tx_queue, then
1066 * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue
1067 * of all transmit completions.
1068 */
1069static void
1070efx_farch_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1071{
1072 struct efx_tx_queue *tx_queue;
1073 int qid;
1074
1075 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1076 if (qid < EFX_TXQ_TYPES * efx->n_tx_channels) {
1077 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES,
1078 qid % EFX_TXQ_TYPES);
1079 if (atomic_cmpxchg(&tx_queue->flush_outstanding, 1, 0)) {
1080 efx_farch_magic_event(tx_queue->channel,
1081 EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue));
1082 }
1083 }
1084}
1085
1086/* If this flush done event corresponds to a &struct efx_rx_queue: If the flush
1087 * was succesful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
1088 * the RX queue back to the mask of RX queues in need of flushing.
1089 */
1090static void
1091efx_farch_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1092{
1093 struct efx_channel *channel;
1094 struct efx_rx_queue *rx_queue;
1095 int qid;
1096 bool failed;
1097
1098 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1099 failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1100 if (qid >= efx->n_channels)
1101 return;
1102 channel = efx_get_channel(efx, qid);
1103 if (!efx_channel_has_rx_queue(channel))
1104 return;
1105 rx_queue = efx_channel_get_rx_queue(channel);
1106
1107 if (failed) {
1108 netif_info(efx, hw, efx->net_dev,
1109 "RXQ %d flush retry\n", qid);
1110 rx_queue->flush_pending = true;
1111 atomic_inc(&efx->rxq_flush_pending);
1112 } else {
1113 efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1114 EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue));
1115 }
1116 atomic_dec(&efx->rxq_flush_outstanding);
1117 if (efx_farch_flush_wake(efx))
1118 wake_up(&efx->flush_wq);
1119}
1120
1121static void
1122efx_farch_handle_drain_event(struct efx_channel *channel)
1123{
1124 struct efx_nic *efx = channel->efx;
1125
1126 WARN_ON(atomic_read(&efx->drain_pending) == 0);
1127 atomic_dec(&efx->drain_pending);
1128 if (efx_farch_flush_wake(efx))
1129 wake_up(&efx->flush_wq);
1130}
1131
1132static void efx_farch_handle_generated_event(struct efx_channel *channel,
1133 efx_qword_t *event)
1134{
1135 struct efx_nic *efx = channel->efx;
1136 struct efx_rx_queue *rx_queue =
1137 efx_channel_has_rx_queue(channel) ?
1138 efx_channel_get_rx_queue(channel) : NULL;
1139 unsigned magic, code;
1140
1141 magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
1142 code = _EFX_CHANNEL_MAGIC_CODE(magic);
1143
1144 if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) {
1145 channel->event_test_cpu = raw_smp_processor_id();
1146 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) {
1147 /* The queue must be empty, so we won't receive any rx
1148 * events, so efx_process_channel() won't refill the
1149 * queue. Refill it here */
1150 efx_fast_push_rx_descriptors(rx_queue);
1151 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) {
1152 efx_farch_handle_drain_event(channel);
1153 } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) {
1154 efx_farch_handle_drain_event(channel);
1155 } else {
1156 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
1157 "generated event "EFX_QWORD_FMT"\n",
1158 channel->channel, EFX_QWORD_VAL(*event));
1159 }
1160}
1161
1162static void
1163efx_farch_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1164{
1165 struct efx_nic *efx = channel->efx;
1166 unsigned int ev_sub_code;
1167 unsigned int ev_sub_data;
1168
1169 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
1170 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1171
1172 switch (ev_sub_code) {
1173 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
1174 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
1175 channel->channel, ev_sub_data);
1176 efx_farch_handle_tx_flush_done(efx, event);
1177 efx_sriov_tx_flush_done(efx, event);
1178 break;
1179 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
1180 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
1181 channel->channel, ev_sub_data);
1182 efx_farch_handle_rx_flush_done(efx, event);
1183 efx_sriov_rx_flush_done(efx, event);
1184 break;
1185 case FSE_AZ_EVQ_INIT_DONE_EV:
1186 netif_dbg(efx, hw, efx->net_dev,
1187 "channel %d EVQ %d initialised\n",
1188 channel->channel, ev_sub_data);
1189 break;
1190 case FSE_AZ_SRM_UPD_DONE_EV:
1191 netif_vdbg(efx, hw, efx->net_dev,
1192 "channel %d SRAM update done\n", channel->channel);
1193 break;
1194 case FSE_AZ_WAKE_UP_EV:
1195 netif_vdbg(efx, hw, efx->net_dev,
1196 "channel %d RXQ %d wakeup event\n",
1197 channel->channel, ev_sub_data);
1198 break;
1199 case FSE_AZ_TIMER_EV:
1200 netif_vdbg(efx, hw, efx->net_dev,
1201 "channel %d RX queue %d timer expired\n",
1202 channel->channel, ev_sub_data);
1203 break;
1204 case FSE_AA_RX_RECOVER_EV:
1205 netif_err(efx, rx_err, efx->net_dev,
1206 "channel %d seen DRIVER RX_RESET event. "
1207 "Resetting.\n", channel->channel);
1208 atomic_inc(&efx->rx_reset);
1209 efx_schedule_reset(efx,
1210 EFX_WORKAROUND_6555(efx) ?
1211 RESET_TYPE_RX_RECOVERY :
1212 RESET_TYPE_DISABLE);
1213 break;
1214 case FSE_BZ_RX_DSC_ERROR_EV:
1215 if (ev_sub_data < EFX_VI_BASE) {
1216 netif_err(efx, rx_err, efx->net_dev,
1217 "RX DMA Q %d reports descriptor fetch error."
1218 " RX Q %d is disabled.\n", ev_sub_data,
1219 ev_sub_data);
3de82b91 1220 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
86094f7f
BH		 1221 } else
1222 efx_sriov_desc_fetch_err(efx, ev_sub_data);
1223 break;
1224 case FSE_BZ_TX_DSC_ERROR_EV:
1225 if (ev_sub_data < EFX_VI_BASE) {
1226 netif_err(efx, tx_err, efx->net_dev,
1227 "TX DMA Q %d reports descriptor fetch error."
1228 " TX Q %d is disabled.\n", ev_sub_data,
1229 ev_sub_data);
3de82b91 1230 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
86094f7f
BH		 1231 } else
1232 efx_sriov_desc_fetch_err(efx, ev_sub_data);
1233 break;
1234 default:
1235 netif_vdbg(efx, hw, efx->net_dev,
1236 "channel %d unknown driver event code %d "
1237 "data %04x\n", channel->channel, ev_sub_code,
1238 ev_sub_data);
1239 break;
1240 }
1241}
1242
1243int efx_farch_ev_process(struct efx_channel *channel, int budget)
1244{
1245 struct efx_nic *efx = channel->efx;
1246 unsigned int read_ptr;
1247 efx_qword_t event, *p_event;
1248 int ev_code;
1249 int tx_packets = 0;
1250 int spent = 0;
1251
1252 read_ptr = channel->eventq_read_ptr;
1253
1254 for (;;) {
1255 p_event = efx_event(channel, read_ptr);
1256 event = *p_event;
1257
1258 if (!efx_event_present(&event))
1259 /* End of events */
1260 break;
1261
1262 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1263 "channel %d event is "EFX_QWORD_FMT"\n",
1264 channel->channel, EFX_QWORD_VAL(event));
1265
1266 /* Clear this event by marking it all ones */
1267 EFX_SET_QWORD(*p_event);
1268
1269 ++read_ptr;
1270
1271 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1272
1273 switch (ev_code) {
1274 case FSE_AZ_EV_CODE_RX_EV:
1275 efx_farch_handle_rx_event(channel, &event);
1276 if (++spent == budget)
1277 goto out;
1278 break;
1279 case FSE_AZ_EV_CODE_TX_EV:
1280 tx_packets += efx_farch_handle_tx_event(channel,
1281 &event);
1282 if (tx_packets > efx->txq_entries) {
1283 spent = budget;
1284 goto out;
1285 }
1286 break;
1287 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1288 efx_farch_handle_generated_event(channel, &event);
1289 break;
1290 case FSE_AZ_EV_CODE_DRIVER_EV:
1291 efx_farch_handle_driver_event(channel, &event);
1292 break;
1293 case FSE_CZ_EV_CODE_USER_EV:
1294 efx_sriov_event(channel, &event);
1295 break;
1296 case FSE_CZ_EV_CODE_MCDI_EV:
1297 efx_mcdi_process_event(channel, &event);
1298 break;
1299 case FSE_AZ_EV_CODE_GLOBAL_EV:
1300 if (efx->type->handle_global_event &&
1301 efx->type->handle_global_event(channel, &event))
1302 break;
1303 /* else fall through */
1304 default:
1305 netif_err(channel->efx, hw, channel->efx->net_dev,
1306 "channel %d unknown event type %d (data "
1307 EFX_QWORD_FMT ")\n", channel->channel,
1308 ev_code, EFX_QWORD_VAL(event));
1309 }
1310 }
1311
1312out:
1313 channel->eventq_read_ptr = read_ptr;
1314 return spent;
1315}
1316
1317/* Allocate buffer table entries for event queue */
1318int efx_farch_ev_probe(struct efx_channel *channel)
1319{
1320 struct efx_nic *efx = channel->efx;
1321 unsigned entries;
1322
1323 entries = channel->eventq_mask + 1;
1324 return efx_alloc_special_buffer(efx, &channel->eventq,
1325 entries * sizeof(efx_qword_t));
1326}
1327
261e4d96 1328int efx_farch_ev_init(struct efx_channel *channel)
86094f7f
BH		 1329{
1330 efx_oword_t reg;
1331 struct efx_nic *efx = channel->efx;
1332
1333 netif_dbg(efx, hw, efx->net_dev,
1334 "channel %d event queue in special buffers %d-%d\n",
1335 channel->channel, channel->eventq.index,
1336 channel->eventq.index + channel->eventq.entries - 1);
1337
1338 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1339 EFX_POPULATE_OWORD_3(reg,
1340 FRF_CZ_TIMER_Q_EN, 1,
1341 FRF_CZ_HOST_NOTIFY_MODE, 0,
1342 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1343 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1344 }
1345
1346 /* Pin event queue buffer */
1347 efx_init_special_buffer(efx, &channel->eventq);
1348
1349 /* Fill event queue with all ones (i.e. empty events) */
1350 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1351
1352 /* Push event queue to card */
1353 EFX_POPULATE_OWORD_3(reg,
1354 FRF_AZ_EVQ_EN, 1,
1355 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1356 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1357 efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1358 channel->channel);
1359
261e4d96 1360 return 0;
86094f7f
BH		 1361}
1362
1363void efx_farch_ev_fini(struct efx_channel *channel)
1364{
1365 efx_oword_t reg;
1366 struct efx_nic *efx = channel->efx;
1367
1368 /* Remove event queue from card */
1369 EFX_ZERO_OWORD(reg);
1370 efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1371 channel->channel);
1372 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1373 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1374
1375 /* Unpin event queue */
1376 efx_fini_special_buffer(efx, &channel->eventq);
1377}
1378
1379/* Free buffers backing event queue */
1380void efx_farch_ev_remove(struct efx_channel *channel)
1381{
1382 efx_free_special_buffer(channel->efx, &channel->eventq);
1383}
1384
1385
1386void efx_farch_ev_test_generate(struct efx_channel *channel)
1387{
1388 efx_farch_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel));
1389}
1390
1391void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue)
1392{
1393 efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1394 EFX_CHANNEL_MAGIC_FILL(rx_queue));
1395}
1396
1397/**************************************************************************
1398 *
1399 * Hardware interrupts
1400 * The hardware interrupt handler does very little work; all the event
1401 * queue processing is carried out by per-channel tasklets.
1402 *
1403 **************************************************************************/
1404
1405/* Enable/disable/generate interrupts */
1406static inline void efx_farch_interrupts(struct efx_nic *efx,
1407 bool enabled, bool force)
1408{
1409 efx_oword_t int_en_reg_ker;
1410
1411 EFX_POPULATE_OWORD_3(int_en_reg_ker,
1412 FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level,
1413 FRF_AZ_KER_INT_KER, force,
1414 FRF_AZ_DRV_INT_EN_KER, enabled);
1415 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1416}
1417
1418void efx_farch_irq_enable_master(struct efx_nic *efx)
1419{
1420 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1421 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1422
1423 efx_farch_interrupts(efx, true, false);
1424}
1425
1426void efx_farch_irq_disable_master(struct efx_nic *efx)
1427{
1428 /* Disable interrupts */
1429 efx_farch_interrupts(efx, false, false);
1430}
1431
1432/* Generate a test interrupt
1433 * Interrupt must already have been enabled, otherwise nasty things
1434 * may happen.
1435 */
1436void efx_farch_irq_test_generate(struct efx_nic *efx)
1437{
1438 efx_farch_interrupts(efx, true, true);
1439}
1440
1441/* Process a fatal interrupt
1442 * Disable bus mastering ASAP and schedule a reset
1443 */
1444irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx)
1445{
1446 struct falcon_nic_data *nic_data = efx->nic_data;
1447 efx_oword_t *int_ker = efx->irq_status.addr;
1448 efx_oword_t fatal_intr;
1449 int error, mem_perr;
1450
1451 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1452 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1453
1454 netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1455 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1456 EFX_OWORD_VAL(fatal_intr),
1457 error ? "disabling bus mastering" : "no recognised error");
1458
1459 /* If this is a memory parity error dump which blocks are offending */
1460 mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1461 EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1462 if (mem_perr) {
1463 efx_oword_t reg;
1464 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1465 netif_err(efx, hw, efx->net_dev,
1466 "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1467 EFX_OWORD_VAL(reg));
1468 }
1469
1470 /* Disable both devices */
1471 pci_clear_master(efx->pci_dev);
1472 if (efx_nic_is_dual_func(efx))
1473 pci_clear_master(nic_data->pci_dev2);
1474 efx_farch_irq_disable_master(efx);
1475
1476 /* Count errors and reset or disable the NIC accordingly */
1477 if (efx->int_error_count == 0 ||
1478 time_after(jiffies, efx->int_error_expire)) {
1479 efx->int_error_count = 0;
1480 efx->int_error_expire =
1481 jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1482 }
1483 if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1484 netif_err(efx, hw, efx->net_dev,
1485 "SYSTEM ERROR - reset scheduled\n");
1486 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1487 } else {
1488 netif_err(efx, hw, efx->net_dev,
1489 "SYSTEM ERROR - max number of errors seen."
1490 "NIC will be disabled\n");
1491 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1492 }
1493
1494 return IRQ_HANDLED;
1495}
1496
1497/* Handle a legacy interrupt
1498 * Acknowledges the interrupt and schedule event queue processing.
1499 */
1500irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id)
1501{
1502 struct efx_nic *efx = dev_id;
1503 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1504 efx_oword_t *int_ker = efx->irq_status.addr;
1505 irqreturn_t result = IRQ_NONE;
1506 struct efx_channel *channel;
1507 efx_dword_t reg;
1508 u32 queues;
1509 int syserr;
1510
1511 /* Read the ISR which also ACKs the interrupts */
1512 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1513 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1514
1515 /* Legacy interrupts are disabled too late by the EEH kernel
1516 * code. Disable them earlier.
1517 * If an EEH error occurred, the read will have returned all ones.
1518 */
1519 if (EFX_DWORD_IS_ALL_ONES(reg) && efx_try_recovery(efx) &&
1520 !efx->eeh_disabled_legacy_irq) {
1521 disable_irq_nosync(efx->legacy_irq);
1522 efx->eeh_disabled_legacy_irq = true;
1523 }
1524
1525 /* Handle non-event-queue sources */
1526 if (queues & (1U << efx->irq_level) && soft_enabled) {
1527 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1528 if (unlikely(syserr))
1529 return efx_farch_fatal_interrupt(efx);
1530 efx->last_irq_cpu = raw_smp_processor_id();
1531 }
1532
1533 if (queues != 0) {
ab3b8250 1534 efx->irq_zero_count = 0;
86094f7f
BH		 1535
1536 /* Schedule processing of any interrupting queues */
1537 if (likely(soft_enabled)) {
1538 efx_for_each_channel(channel, efx) {
1539 if (queues & 1)
1540 efx_schedule_channel_irq(channel);
1541 queues >>= 1;
1542 }
1543 }
1544 result = IRQ_HANDLED;
1545
ab3b8250 1546 } else {
86094f7f
BH		 1547 efx_qword_t *event;
1548
ab3b8250
BH		 1549 /* Legacy ISR read can return zero once (SF bug 15783) */
1550
86094f7f
BH		 1551 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1552 * because this might be a shared interrupt. */
1553 if (efx->irq_zero_count++ == 0)
1554 result = IRQ_HANDLED;
1555
1556 /* Ensure we schedule or rearm all event queues */
1557 if (likely(soft_enabled)) {
1558 efx_for_each_channel(channel, efx) {
1559 event = efx_event(channel,
1560 channel->eventq_read_ptr);
1561 if (efx_event_present(event))
1562 efx_schedule_channel_irq(channel);
1563 else
1564 efx_farch_ev_read_ack(channel);
1565 }
1566 }
1567 }
1568
1569 if (result == IRQ_HANDLED)
1570 netif_vdbg(efx, intr, efx->net_dev,
1571 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1572 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1573
1574 return result;
1575}
1576
1577/* Handle an MSI interrupt
1578 *
1579 * Handle an MSI hardware interrupt. This routine schedules event
1580 * queue processing. No interrupt acknowledgement cycle is necessary.
1581 * Also, we never need to check that the interrupt is for us, since
1582 * MSI interrupts cannot be shared.
1583 */
1584irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id)
1585{
1586 struct efx_msi_context *context = dev_id;
1587 struct efx_nic *efx = context->efx;
1588 efx_oword_t *int_ker = efx->irq_status.addr;
1589 int syserr;
1590
1591 netif_vdbg(efx, intr, efx->net_dev,
1592 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1593 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1594
1595 if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
1596 return IRQ_HANDLED;
1597
1598 /* Handle non-event-queue sources */
1599 if (context->index == efx->irq_level) {
1600 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1601 if (unlikely(syserr))
1602 return efx_farch_fatal_interrupt(efx);
1603 efx->last_irq_cpu = raw_smp_processor_id();
1604 }
1605
1606 /* Schedule processing of the channel */
1607 efx_schedule_channel_irq(efx->channel[context->index]);
1608
1609 return IRQ_HANDLED;
1610}
1611
1612
1613/* Setup RSS indirection table.
1614 * This maps from the hash value of the packet to RXQ
1615 */
1616void efx_farch_rx_push_indir_table(struct efx_nic *efx)
1617{
1618 size_t i = 0;
1619 efx_dword_t dword;
1620
1621 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1622 return;
1623
1624 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1625 FR_BZ_RX_INDIRECTION_TBL_ROWS);
1626
1627 for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1628 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1629 efx->rx_indir_table[i]);
1630 efx_writed(efx, &dword,
1631 FR_BZ_RX_INDIRECTION_TBL +
1632 FR_BZ_RX_INDIRECTION_TBL_STEP * i);
1633 }
1634}
1635
1636/* Looks at available SRAM resources and works out how many queues we
1637 * can support, and where things like descriptor caches should live.
1638 *
1639 * SRAM is split up as follows:
1640 * 0 buftbl entries for channels
1641 * efx->vf_buftbl_base buftbl entries for SR-IOV
1642 * efx->rx_dc_base RX descriptor caches
1643 * efx->tx_dc_base TX descriptor caches
1644 */
1645void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
1646{
1647 unsigned vi_count, buftbl_min;
1648
1649 /* Account for the buffer table entries backing the datapath channels
1650 * and the descriptor caches for those channels.
1651 */
1652 buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
1653 efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
1654 efx->n_channels * EFX_MAX_EVQ_SIZE)
1655 * sizeof(efx_qword_t) / EFX_BUF_SIZE);
1656 vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1657
1658#ifdef CONFIG_SFC_SRIOV
1659 if (efx_sriov_wanted(efx)) {
1660 unsigned vi_dc_entries, buftbl_free, entries_per_vf, vf_limit;
1661
1662 efx->vf_buftbl_base = buftbl_min;
1663
1664 vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES;
1665 vi_count = max(vi_count, EFX_VI_BASE);
1666 buftbl_free = (sram_lim_qw - buftbl_min -
1667 vi_count * vi_dc_entries);
1668
1669 entries_per_vf = ((vi_dc_entries + EFX_VF_BUFTBL_PER_VI) *
1670 efx_vf_size(efx));
1671 vf_limit = min(buftbl_free / entries_per_vf,
1672 (1024U - EFX_VI_BASE) >> efx->vi_scale);
1673
1674 if (efx->vf_count > vf_limit) {
1675 netif_err(efx, probe, efx->net_dev,
1676 "Reducing VF count from from %d to %d\n",
1677 efx->vf_count, vf_limit);
1678 efx->vf_count = vf_limit;
1679 }
1680 vi_count += efx->vf_count * efx_vf_size(efx);
1681 }
1682#endif
1683
1684 efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
1685 efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
1686}
1687
1688u32 efx_farch_fpga_ver(struct efx_nic *efx)
1689{
1690 efx_oword_t altera_build;
1691 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1692 return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1693}
1694
1695void efx_farch_init_common(struct efx_nic *efx)
1696{
1697 efx_oword_t temp;
1698
1699 /* Set positions of descriptor caches in SRAM. */
1700 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
1701 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1702 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
1703 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1704
1705 /* Set TX descriptor cache size. */
1706 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1707 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1708 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1709
1710 /* Set RX descriptor cache size. Set low watermark to size-8, as
1711 * this allows most efficient prefetching.
1712 */
1713 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1714 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1715 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1716 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1717 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1718
1719 /* Program INT_KER address */
1720 EFX_POPULATE_OWORD_2(temp,
1721 FRF_AZ_NORM_INT_VEC_DIS_KER,
1722 EFX_INT_MODE_USE_MSI(efx),
1723 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1724 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1725
1726 if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1727 /* Use an interrupt level unused by event queues */
1728 efx->irq_level = 0x1f;
1729 else
1730 /* Use a valid MSI-X vector */
1731 efx->irq_level = 0;
1732
1733 /* Enable all the genuinely fatal interrupts. (They are still
1734 * masked by the overall interrupt mask, controlled by
1735 * falcon_interrupts()).
1736 *
1737 * Note: All other fatal interrupts are enabled
1738 */
1739 EFX_POPULATE_OWORD_3(temp,
1740 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1741 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1742 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1743 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1744 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1745 EFX_INVERT_OWORD(temp);
1746 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1747
1748 efx_farch_rx_push_indir_table(efx);
1749
1750 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1751 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1752 */
1753 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1754 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1755 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1756 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1757 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
1758 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1759 /* Enable SW_EV to inherit in char driver - assume harmless here */
1760 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1761 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1762 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1763 /* Disable hardware watchdog which can misfire */
1764 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1765 /* Squash TX of packets of 16 bytes or less */
1766 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1767 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1768 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1769
1770 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1771 EFX_POPULATE_OWORD_4(temp,
1772 /* Default values */
1773 FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1774 FRF_BZ_TX_PACE_SB_AF, 0xb,
1775 FRF_BZ_TX_PACE_FB_BASE, 0,
1776 /* Allow large pace values in the
1777 * fast bin. */
1778 FRF_BZ_TX_PACE_BIN_TH,
1779 FFE_BZ_TX_PACE_RESERVED);
1780 efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1781 }
1782}
add72477
BH		 1783
1784/**************************************************************************
1785 *
1786 * Filter tables
1787 *
1788 **************************************************************************
1789 */
1790
1791/* "Fudge factors" - difference between programmed value and actual depth.
1792 * Due to pipelined implementation we need to program H/W with a value that
1793 * is larger than the hop limit we want.
1794 */
1795#define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD 3
1796#define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL 1
1797
1798/* Hard maximum search limit. Hardware will time-out beyond 200-something.
1799 * We also need to avoid infinite loops in efx_farch_filter_search() when the
1800 * table is full.
1801 */
1802#define EFX_FARCH_FILTER_CTL_SRCH_MAX 200
1803
1804/* Don't try very hard to find space for performance hints, as this is
1805 * counter-productive. */
1806#define EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX 5
1807
1808enum efx_farch_filter_type {
1809 EFX_FARCH_FILTER_TCP_FULL = 0,
1810 EFX_FARCH_FILTER_TCP_WILD,
1811 EFX_FARCH_FILTER_UDP_FULL,
1812 EFX_FARCH_FILTER_UDP_WILD,
1813 EFX_FARCH_FILTER_MAC_FULL = 4,
1814 EFX_FARCH_FILTER_MAC_WILD,
1815 EFX_FARCH_FILTER_UC_DEF = 8,
1816 EFX_FARCH_FILTER_MC_DEF,
1817 EFX_FARCH_FILTER_TYPE_COUNT, /* number of specific types */
1818};
1819
1820enum efx_farch_filter_table_id {
1821 EFX_FARCH_FILTER_TABLE_RX_IP = 0,
1822 EFX_FARCH_FILTER_TABLE_RX_MAC,
1823 EFX_FARCH_FILTER_TABLE_RX_DEF,
1824 EFX_FARCH_FILTER_TABLE_TX_MAC,
1825 EFX_FARCH_FILTER_TABLE_COUNT,
1826};
1827
1828enum efx_farch_filter_index {
1829 EFX_FARCH_FILTER_INDEX_UC_DEF,
1830 EFX_FARCH_FILTER_INDEX_MC_DEF,
1831 EFX_FARCH_FILTER_SIZE_RX_DEF,
1832};
1833
1834struct efx_farch_filter_spec {
1835 u8 type:4;
1836 u8 priority:4;
1837 u8 flags;
1838 u16 dmaq_id;
1839 u32 data[3];
1840};
1841
1842struct efx_farch_filter_table {
1843 enum efx_farch_filter_table_id id;
1844 u32 offset; /* address of table relative to BAR */
1845 unsigned size; /* number of entries */
1846 unsigned step; /* step between entries */
1847 unsigned used; /* number currently used */
1848 unsigned long *used_bitmap;
1849 struct efx_farch_filter_spec *spec;
1850 unsigned search_limit[EFX_FARCH_FILTER_TYPE_COUNT];
1851};
1852
1853struct efx_farch_filter_state {
1854 struct efx_farch_filter_table table[EFX_FARCH_FILTER_TABLE_COUNT];
1855};
1856
1857static void
1858efx_farch_filter_table_clear_entry(struct efx_nic *efx,
1859 struct efx_farch_filter_table *table,
1860 unsigned int filter_idx);
1861
1862/* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
1863 * key derived from the n-tuple. The initial LFSR state is 0xffff. */
1864static u16 efx_farch_filter_hash(u32 key)
1865{
1866 u16 tmp;
1867
1868 /* First 16 rounds */
1869 tmp = 0x1fff ^ key >> 16;
1870 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1871 tmp = tmp ^ tmp >> 9;
1872 /* Last 16 rounds */
1873 tmp = tmp ^ tmp << 13 ^ key;
1874 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1875 return tmp ^ tmp >> 9;
1876}
1877
1878/* To allow for hash collisions, filter search continues at these
1879 * increments from the first possible entry selected by the hash. */
1880static u16 efx_farch_filter_increment(u32 key)
1881{
1882 return key * 2 - 1;
1883}
1884
1885static enum efx_farch_filter_table_id
1886efx_farch_filter_spec_table_id(const struct efx_farch_filter_spec *spec)
1887{
1888 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1889 (EFX_FARCH_FILTER_TCP_FULL >> 2));
1890 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1891 (EFX_FARCH_FILTER_TCP_WILD >> 2));
1892 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1893 (EFX_FARCH_FILTER_UDP_FULL >> 2));
1894 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1895 (EFX_FARCH_FILTER_UDP_WILD >> 2));
1896 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1897 (EFX_FARCH_FILTER_MAC_FULL >> 2));
1898 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1899 (EFX_FARCH_FILTER_MAC_WILD >> 2));
1900 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_TX_MAC !=
1901 EFX_FARCH_FILTER_TABLE_RX_MAC + 2);
1902 return (spec->type >> 2) + ((spec->flags & EFX_FILTER_FLAG_TX) ? 2 : 0);
1903}
1904
1905static void efx_farch_filter_push_rx_config(struct efx_nic *efx)
1906{
1907 struct efx_farch_filter_state *state = efx->filter_state;
1908 struct efx_farch_filter_table *table;
1909 efx_oword_t filter_ctl;
1910
1911 efx_reado(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1912
1913 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
1914 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_FULL_SRCH_LIMIT,
1915 table->search_limit[EFX_FARCH_FILTER_TCP_FULL] +
1916 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1917 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_WILD_SRCH_LIMIT,
1918 table->search_limit[EFX_FARCH_FILTER_TCP_WILD] +
1919 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1920 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_FULL_SRCH_LIMIT,
1921 table->search_limit[EFX_FARCH_FILTER_UDP_FULL] +
1922 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1923 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_WILD_SRCH_LIMIT,
1924 table->search_limit[EFX_FARCH_FILTER_UDP_WILD] +
1925 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1926
1927 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
1928 if (table->size) {
1929 EFX_SET_OWORD_FIELD(
1930 filter_ctl, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
1931 table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
1932 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1933 EFX_SET_OWORD_FIELD(
1934 filter_ctl, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
1935 table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
1936 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1937 }
1938
1939 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
1940 if (table->size) {
1941 EFX_SET_OWORD_FIELD(
1942 filter_ctl, FRF_CZ_UNICAST_NOMATCH_Q_ID,
1943 table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].dmaq_id);
1944 EFX_SET_OWORD_FIELD(
1945 filter_ctl, FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED,
1946 !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1947 EFX_FILTER_FLAG_RX_RSS));
1948 EFX_SET_OWORD_FIELD(
1949 filter_ctl, FRF_CZ_MULTICAST_NOMATCH_Q_ID,
1950 table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].dmaq_id);
1951 EFX_SET_OWORD_FIELD(
1952 filter_ctl, FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED,
1953 !!(table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1954 EFX_FILTER_FLAG_RX_RSS));
1955
1956 /* There is a single bit to enable RX scatter for all
1957 * unmatched packets. Only set it if scatter is
1958 * enabled in both filter specs.
1959 */
1960 EFX_SET_OWORD_FIELD(
1961 filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1962 !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1963 table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1964 EFX_FILTER_FLAG_RX_SCATTER));
1965 } else if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1966 /* We don't expose 'default' filters because unmatched
1967 * packets always go to the queue number found in the
1968 * RSS table. But we still need to set the RX scatter
1969 * bit here.
1970 */
1971 EFX_SET_OWORD_FIELD(
1972 filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1973 efx->rx_scatter);
1974 }
1975
1976 efx_writeo(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1977}
1978
1979static void efx_farch_filter_push_tx_limits(struct efx_nic *efx)
1980{
1981 struct efx_farch_filter_state *state = efx->filter_state;
1982 struct efx_farch_filter_table *table;
1983 efx_oword_t tx_cfg;
1984
1985 efx_reado(efx, &tx_cfg, FR_AZ_TX_CFG);
1986
1987 table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
1988 if (table->size) {
1989 EFX_SET_OWORD_FIELD(
1990 tx_cfg, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
1991 table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
1992 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1993 EFX_SET_OWORD_FIELD(
1994 tx_cfg, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
1995 table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
1996 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1997 }
1998
1999 efx_writeo(efx, &tx_cfg, FR_AZ_TX_CFG);
2000}
2001
2002static int
2003efx_farch_filter_from_gen_spec(struct efx_farch_filter_spec *spec,
2004 const struct efx_filter_spec *gen_spec)
2005{
2006 bool is_full = false;
2007
2008 if ((gen_spec->flags & EFX_FILTER_FLAG_RX_RSS) &&
2009 gen_spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT)
2010 return -EINVAL;
2011
2012 spec->priority = gen_spec->priority;
2013 spec->flags = gen_spec->flags;
2014 spec->dmaq_id = gen_spec->dmaq_id;
2015
2016 switch (gen_spec->match_flags) {
2017 case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2018 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
2019 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT):
2020 is_full = true;
2021 /* fall through */
2022 case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2023 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT): {
2024 __be32 rhost, host1, host2;
2025 __be16 rport, port1, port2;
2026
2027 EFX_BUG_ON_PARANOID(!(gen_spec->flags & EFX_FILTER_FLAG_RX));
2028
2029 if (gen_spec->ether_type != htons(ETH_P_IP))
2030 return -EPROTONOSUPPORT;
2031 if (gen_spec->loc_port == 0 ||
2032 (is_full && gen_spec->rem_port == 0))
2033 return -EADDRNOTAVAIL;
2034 switch (gen_spec->ip_proto) {
2035 case IPPROTO_TCP:
2036 spec->type = (is_full ? EFX_FARCH_FILTER_TCP_FULL :
2037 EFX_FARCH_FILTER_TCP_WILD);
2038 break;
2039 case IPPROTO_UDP:
2040 spec->type = (is_full ? EFX_FARCH_FILTER_UDP_FULL :
2041 EFX_FARCH_FILTER_UDP_WILD);
2042 break;
2043 default:
2044 return -EPROTONOSUPPORT;
2045 }
2046
2047 /* Filter is constructed in terms of source and destination,
2048 * with the odd wrinkle that the ports are swapped in a UDP
2049 * wildcard filter. We need to convert from local and remote
2050 * (= zero for wildcard) addresses.
2051 */
2052 rhost = is_full ? gen_spec->rem_host[0] : 0;
2053 rport = is_full ? gen_spec->rem_port : 0;
2054 host1 = rhost;
2055 host2 = gen_spec->loc_host[0];
2056 if (!is_full && gen_spec->ip_proto == IPPROTO_UDP) {
2057 port1 = gen_spec->loc_port;
2058 port2 = rport;
2059 } else {
2060 port1 = rport;
2061 port2 = gen_spec->loc_port;
2062 }
2063 spec->data[0] = ntohl(host1) << 16 | ntohs(port1);
2064 spec->data[1] = ntohs(port2) << 16 | ntohl(host1) >> 16;
2065 spec->data[2] = ntohl(host2);
2066
2067 break;
2068 }
2069
2070 case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
2071 is_full = true;
2072 /* fall through */
2073 case EFX_FILTER_MATCH_LOC_MAC:
2074 spec->type = (is_full ? EFX_FARCH_FILTER_MAC_FULL :
2075 EFX_FARCH_FILTER_MAC_WILD);
2076 spec->data[0] = is_full ? ntohs(gen_spec->outer_vid) : 0;
2077 spec->data[1] = (gen_spec->loc_mac[2] << 24 |
2078 gen_spec->loc_mac[3] << 16 |
2079 gen_spec->loc_mac[4] << 8 |
2080 gen_spec->loc_mac[5]);
2081 spec->data[2] = (gen_spec->loc_mac[0] << 8 |
2082 gen_spec->loc_mac[1]);
2083 break;
2084
2085 case EFX_FILTER_MATCH_LOC_MAC_IG:
2086 spec->type = (is_multicast_ether_addr(gen_spec->loc_mac) ?
2087 EFX_FARCH_FILTER_MC_DEF :
2088 EFX_FARCH_FILTER_UC_DEF);
2089 memset(spec->data, 0, sizeof(spec->data)); /* ensure equality */
2090 break;
2091
2092 default:
2093 return -EPROTONOSUPPORT;
2094 }
2095
2096 return 0;
2097}
2098
2099static void
2100efx_farch_filter_to_gen_spec(struct efx_filter_spec *gen_spec,
2101 const struct efx_farch_filter_spec *spec)
2102{
2103 bool is_full = false;
2104
2105 /* *gen_spec should be completely initialised, to be consistent
2106 * with efx_filter_init_{rx,tx}() and in case we want to copy
2107 * it back to userland.
2108 */
2109 memset(gen_spec, 0, sizeof(*gen_spec));
2110
2111 gen_spec->priority = spec->priority;
2112 gen_spec->flags = spec->flags;
2113 gen_spec->dmaq_id = spec->dmaq_id;
2114
2115 switch (spec->type) {
2116 case EFX_FARCH_FILTER_TCP_FULL:
2117 case EFX_FARCH_FILTER_UDP_FULL:
2118 is_full = true;
2119 /* fall through */
2120 case EFX_FARCH_FILTER_TCP_WILD:
2121 case EFX_FARCH_FILTER_UDP_WILD: {
2122 __be32 host1, host2;
2123 __be16 port1, port2;
2124
2125 gen_spec->match_flags =
2126 EFX_FILTER_MATCH_ETHER_TYPE |
2127 EFX_FILTER_MATCH_IP_PROTO |
2128 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
2129 if (is_full)
2130 gen_spec->match_flags |= (EFX_FILTER_MATCH_REM_HOST |
2131 EFX_FILTER_MATCH_REM_PORT);
2132 gen_spec->ether_type = htons(ETH_P_IP);
2133 gen_spec->ip_proto =
2134 (spec->type == EFX_FARCH_FILTER_TCP_FULL ||
2135 spec->type == EFX_FARCH_FILTER_TCP_WILD) ?
2136 IPPROTO_TCP : IPPROTO_UDP;
2137
2138 host1 = htonl(spec->data[0] >> 16 | spec->data[1] << 16);
2139 port1 = htons(spec->data[0]);
2140 host2 = htonl(spec->data[2]);
2141 port2 = htons(spec->data[1] >> 16);
2142 if (spec->flags & EFX_FILTER_FLAG_TX) {
2143 gen_spec->loc_host[0] = host1;
2144 gen_spec->rem_host[0] = host2;
2145 } else {
2146 gen_spec->loc_host[0] = host2;
2147 gen_spec->rem_host[0] = host1;
2148 }
2149 if (!!(gen_spec->flags & EFX_FILTER_FLAG_TX) ^
2150 (!is_full && gen_spec->ip_proto == IPPROTO_UDP)) {
2151 gen_spec->loc_port = port1;
2152 gen_spec->rem_port = port2;
2153 } else {
2154 gen_spec->loc_port = port2;
2155 gen_spec->rem_port = port1;
2156 }
2157
2158 break;
2159 }
2160
2161 case EFX_FARCH_FILTER_MAC_FULL:
2162 is_full = true;
2163 /* fall through */
2164 case EFX_FARCH_FILTER_MAC_WILD:
2165 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC;
2166 if (is_full)
2167 gen_spec->match_flags |= EFX_FILTER_MATCH_OUTER_VID;
2168 gen_spec->loc_mac[0] = spec->data[2] >> 8;
2169 gen_spec->loc_mac[1] = spec->data[2];
2170 gen_spec->loc_mac[2] = spec->data[1] >> 24;
2171 gen_spec->loc_mac[3] = spec->data[1] >> 16;
2172 gen_spec->loc_mac[4] = spec->data[1] >> 8;
2173 gen_spec->loc_mac[5] = spec->data[1];
2174 gen_spec->outer_vid = htons(spec->data[0]);
2175 break;
2176
2177 case EFX_FARCH_FILTER_UC_DEF:
2178 case EFX_FARCH_FILTER_MC_DEF:
2179 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC_IG;
2180 gen_spec->loc_mac[0] = spec->type == EFX_FARCH_FILTER_MC_DEF;
2181 break;
2182
2183 default:
2184 WARN_ON(1);
2185 break;
2186 }
2187}
2188
2189static void
8803e150
BH		 2190efx_farch_filter_init_rx_for_stack(struct efx_nic *efx,
2191 struct efx_farch_filter_spec *spec)
add72477 2192{
add72477
BH		 2193 /* If there's only one channel then disable RSS for non VF
2194 * traffic, thereby allowing VFs to use RSS when the PF can't.
2195 */
8803e150
BH		 2196 spec->priority = EFX_FILTER_PRI_REQUIRED;
2197 spec->flags = (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_STACK |
add72477
BH		 2198 (efx->n_rx_channels > 1 ? EFX_FILTER_FLAG_RX_RSS : 0) |
2199 (efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0));
2200 spec->dmaq_id = 0;
add72477
BH		 2201}
2202
2203/* Build a filter entry and return its n-tuple key. */
2204static u32 efx_farch_filter_build(efx_oword_t *filter,
2205 struct efx_farch_filter_spec *spec)
2206{
2207 u32 data3;
2208
2209 switch (efx_farch_filter_spec_table_id(spec)) {
2210 case EFX_FARCH_FILTER_TABLE_RX_IP: {
2211 bool is_udp = (spec->type == EFX_FARCH_FILTER_UDP_FULL ||
2212 spec->type == EFX_FARCH_FILTER_UDP_WILD);
2213 EFX_POPULATE_OWORD_7(
2214 *filter,
2215 FRF_BZ_RSS_EN,
2216 !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2217 FRF_BZ_SCATTER_EN,
2218 !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2219 FRF_BZ_TCP_UDP, is_udp,
2220 FRF_BZ_RXQ_ID, spec->dmaq_id,
2221 EFX_DWORD_2, spec->data[2],
2222 EFX_DWORD_1, spec->data[1],
2223 EFX_DWORD_0, spec->data[0]);
2224 data3 = is_udp;
2225 break;
2226 }
2227
2228 case EFX_FARCH_FILTER_TABLE_RX_MAC: {
2229 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2230 EFX_POPULATE_OWORD_7(
2231 *filter,
2232 FRF_CZ_RMFT_RSS_EN,
2233 !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2234 FRF_CZ_RMFT_SCATTER_EN,
2235 !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2236 FRF_CZ_RMFT_RXQ_ID, spec->dmaq_id,
2237 FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
2238 FRF_CZ_RMFT_DEST_MAC_HI, spec->data[2],
2239 FRF_CZ_RMFT_DEST_MAC_LO, spec->data[1],
2240 FRF_CZ_RMFT_VLAN_ID, spec->data[0]);
2241 data3 = is_wild;
2242 break;
2243 }
2244
2245 case EFX_FARCH_FILTER_TABLE_TX_MAC: {
2246 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2247 EFX_POPULATE_OWORD_5(*filter,
2248 FRF_CZ_TMFT_TXQ_ID, spec->dmaq_id,
2249 FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
2250 FRF_CZ_TMFT_SRC_MAC_HI, spec->data[2],
2251 FRF_CZ_TMFT_SRC_MAC_LO, spec->data[1],
2252 FRF_CZ_TMFT_VLAN_ID, spec->data[0]);
2253 data3 = is_wild | spec->dmaq_id << 1;
2254 break;
2255 }
2256
2257 default:
2258 BUG();
2259 }
2260
2261 return spec->data[0] ^ spec->data[1] ^ spec->data[2] ^ data3;
2262}
2263
2264static bool efx_farch_filter_equal(const struct efx_farch_filter_spec *left,
2265 const struct efx_farch_filter_spec *right)
2266{
2267 if (left->type != right->type ||
2268 memcmp(left->data, right->data, sizeof(left->data)))
2269 return false;
2270
2271 if (left->flags & EFX_FILTER_FLAG_TX &&
2272 left->dmaq_id != right->dmaq_id)
2273 return false;
2274
2275 return true;
2276}
2277
2278/*
2279 * Construct/deconstruct external filter IDs. At least the RX filter
2280 * IDs must be ordered by matching priority, for RX NFC semantics.
2281 *
2282 * Deconstruction needs to be robust against invalid IDs so that
2283 * efx_filter_remove_id_safe() and efx_filter_get_filter_safe() can
2284 * accept user-provided IDs.
2285 */
2286
2287#define EFX_FARCH_FILTER_MATCH_PRI_COUNT 5
2288
2289static const u8 efx_farch_filter_type_match_pri[EFX_FARCH_FILTER_TYPE_COUNT] = {
2290 [EFX_FARCH_FILTER_TCP_FULL] = 0,
2291 [EFX_FARCH_FILTER_UDP_FULL] = 0,
2292 [EFX_FARCH_FILTER_TCP_WILD] = 1,
2293 [EFX_FARCH_FILTER_UDP_WILD] = 1,
2294 [EFX_FARCH_FILTER_MAC_FULL] = 2,
2295 [EFX_FARCH_FILTER_MAC_WILD] = 3,
2296 [EFX_FARCH_FILTER_UC_DEF] = 4,
2297 [EFX_FARCH_FILTER_MC_DEF] = 4,
2298};
2299
2300static const enum efx_farch_filter_table_id efx_farch_filter_range_table[] = {
2301 EFX_FARCH_FILTER_TABLE_RX_IP, /* RX match pri 0 */
2302 EFX_FARCH_FILTER_TABLE_RX_IP,
2303 EFX_FARCH_FILTER_TABLE_RX_MAC,
2304 EFX_FARCH_FILTER_TABLE_RX_MAC,
2305 EFX_FARCH_FILTER_TABLE_RX_DEF, /* RX match pri 4 */
2306 EFX_FARCH_FILTER_TABLE_TX_MAC, /* TX match pri 0 */
2307 EFX_FARCH_FILTER_TABLE_TX_MAC, /* TX match pri 1 */
2308};
2309
2310#define EFX_FARCH_FILTER_INDEX_WIDTH 13
2311#define EFX_FARCH_FILTER_INDEX_MASK ((1 << EFX_FARCH_FILTER_INDEX_WIDTH) - 1)
2312
2313static inline u32
2314efx_farch_filter_make_id(const struct efx_farch_filter_spec *spec,
2315 unsigned int index)
2316{
2317 unsigned int range;
2318
2319 range = efx_farch_filter_type_match_pri[spec->type];
2320 if (!(spec->flags & EFX_FILTER_FLAG_RX))
2321 range += EFX_FARCH_FILTER_MATCH_PRI_COUNT;
2322
2323 return range << EFX_FARCH_FILTER_INDEX_WIDTH | index;
2324}
2325
2326static inline enum efx_farch_filter_table_id
2327efx_farch_filter_id_table_id(u32 id)
2328{
2329 unsigned int range = id >> EFX_FARCH_FILTER_INDEX_WIDTH;
2330
2331 if (range < ARRAY_SIZE(efx_farch_filter_range_table))
2332 return efx_farch_filter_range_table[range];
2333 else
2334 return EFX_FARCH_FILTER_TABLE_COUNT; /* invalid */
2335}
2336
2337static inline unsigned int efx_farch_filter_id_index(u32 id)
2338{
2339 return id & EFX_FARCH_FILTER_INDEX_MASK;
2340}
2341
2342u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx)
2343{
2344 struct efx_farch_filter_state *state = efx->filter_state;
2345 unsigned int range = EFX_FARCH_FILTER_MATCH_PRI_COUNT - 1;
2346 enum efx_farch_filter_table_id table_id;
2347
2348 do {
2349 table_id = efx_farch_filter_range_table[range];
2350 if (state->table[table_id].size != 0)
2351 return range << EFX_FARCH_FILTER_INDEX_WIDTH |
2352 state->table[table_id].size;
2353 } while (range--);
2354
2355 return 0;
2356}
2357
2358s32 efx_farch_filter_insert(struct efx_nic *efx,
2359 struct efx_filter_spec *gen_spec,
2360 bool replace_equal)
2361{
2362 struct efx_farch_filter_state *state = efx->filter_state;
2363 struct efx_farch_filter_table *table;
2364 struct efx_farch_filter_spec spec;
2365 efx_oword_t filter;
2366 int rep_index, ins_index;
2367 unsigned int depth = 0;
2368 int rc;
2369
2370 rc = efx_farch_filter_from_gen_spec(&spec, gen_spec);
2371 if (rc)
2372 return rc;
2373
2374 table = &state->table[efx_farch_filter_spec_table_id(&spec)];
2375 if (table->size == 0)
2376 return -EINVAL;
2377
2378 netif_vdbg(efx, hw, efx->net_dev,
2379 "%s: type %d search_limit=%d", __func__, spec.type,
2380 table->search_limit[spec.type]);
2381
2382 if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2383 /* One filter spec per type */
2384 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_UC_DEF != 0);
2385 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_MC_DEF !=
2386 EFX_FARCH_FILTER_MC_DEF - EFX_FARCH_FILTER_UC_DEF);
2387 rep_index = spec.type - EFX_FARCH_FILTER_UC_DEF;
2388 ins_index = rep_index;
2389
2390 spin_lock_bh(&efx->filter_lock);
2391 } else {
2392 /* Search concurrently for
2393 * (1) a filter to be replaced (rep_index): any filter
2394 * with the same match values, up to the current
2395 * search depth for this type, and
2396 * (2) the insertion point (ins_index): (1) or any
2397 * free slot before it or up to the maximum search
2398 * depth for this priority
2399 * We fail if we cannot find (2).
2400 *
2401 * We can stop once either
2402 * (a) we find (1), in which case we have definitely
2403 * found (2) as well; or
2404 * (b) we have searched exhaustively for (1), and have
2405 * either found (2) or searched exhaustively for it
2406 */
2407 u32 key = efx_farch_filter_build(&filter, &spec);
2408 unsigned int hash = efx_farch_filter_hash(key);
2409 unsigned int incr = efx_farch_filter_increment(key);
2410 unsigned int max_rep_depth = table->search_limit[spec.type];
2411 unsigned int max_ins_depth =
2412 spec.priority <= EFX_FILTER_PRI_HINT ?
2413 EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX :
2414 EFX_FARCH_FILTER_CTL_SRCH_MAX;
2415 unsigned int i = hash & (table->size - 1);
2416
2417 ins_index = -1;
2418 depth = 1;
2419
2420 spin_lock_bh(&efx->filter_lock);
2421
2422 for (;;) {
2423 if (!test_bit(i, table->used_bitmap)) {
2424 if (ins_index < 0)
2425 ins_index = i;
2426 } else if (efx_farch_filter_equal(&spec,
2427 &table->spec[i])) {
2428 /* Case (a) */
2429 if (ins_index < 0)
2430 ins_index = i;
2431 rep_index = i;
2432 break;
2433 }
2434
2435 if (depth >= max_rep_depth &&
2436 (ins_index >= 0 || depth >= max_ins_depth)) {
2437 /* Case (b) */
2438 if (ins_index < 0) {
2439 rc = -EBUSY;
2440 goto out;
2441 }
2442 rep_index = -1;
2443 break;
2444 }
2445
2446 i = (i + incr) & (table->size - 1);
2447 ++depth;
2448 }
2449 }
2450
2451 /* If we found a filter to be replaced, check whether we
2452 * should do so
2453 */
2454 if (rep_index >= 0) {
2455 struct efx_farch_filter_spec *saved_spec =
2456 &table->spec[rep_index];
2457
2458 if (spec.priority == saved_spec->priority && !replace_equal) {
2459 rc = -EEXIST;
2460 goto out;
2461 }
8803e150
BH		 2462 if (spec.priority < saved_spec->priority &&
2463 !(saved_spec->priority == EFX_FILTER_PRI_REQUIRED &&
2464 saved_spec->flags & EFX_FILTER_FLAG_RX_STACK)) {
add72477
BH		 2465 rc = -EPERM;
2466 goto out;
2467 }
8803e150
BH		 2468 if (spec.flags & EFX_FILTER_FLAG_RX_STACK) {
2469 /* Just make sure it won't be removed */
2470 saved_spec->flags |= EFX_FILTER_FLAG_RX_STACK;
2471 rc = 0;
2472 goto out;
2473 }
2474 /* Retain the RX_STACK flag */
2475 spec.flags |= saved_spec->flags & EFX_FILTER_FLAG_RX_STACK;
add72477
BH		 2476 }
2477
2478 /* Insert the filter */
2479 if (ins_index != rep_index) {
2480 __set_bit(ins_index, table->used_bitmap);
2481 ++table->used;
2482 }
2483 table->spec[ins_index] = spec;
2484
2485 if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2486 efx_farch_filter_push_rx_config(efx);
2487 } else {
2488 if (table->search_limit[spec.type] < depth) {
2489 table->search_limit[spec.type] = depth;
2490 if (spec.flags & EFX_FILTER_FLAG_TX)
2491 efx_farch_filter_push_tx_limits(efx);
2492 else
2493 efx_farch_filter_push_rx_config(efx);
2494 }
2495
2496 efx_writeo(efx, &filter,
2497 table->offset + table->step * ins_index);
2498
2499 /* If we were able to replace a filter by inserting
2500 * at a lower depth, clear the replaced filter
2501 */
2502 if (ins_index != rep_index && rep_index >= 0)
2503 efx_farch_filter_table_clear_entry(efx, table,
2504 rep_index);
2505 }
2506
2507 netif_vdbg(efx, hw, efx->net_dev,
2508 "%s: filter type %d index %d rxq %u set",
2509 __func__, spec.type, ins_index, spec.dmaq_id);
2510 rc = efx_farch_filter_make_id(&spec, ins_index);
2511
2512out:
2513 spin_unlock_bh(&efx->filter_lock);
2514 return rc;
2515}
2516
2517static void
2518efx_farch_filter_table_clear_entry(struct efx_nic *efx,
2519 struct efx_farch_filter_table *table,
2520 unsigned int filter_idx)
2521{
2522 static efx_oword_t filter;
2523
14990a5d 2524 EFX_WARN_ON_PARANOID(!test_bit(filter_idx, table->used_bitmap));
8803e150 2525 BUG_ON(table->offset == 0); /* can't clear MAC default filters */
14990a5d
BH		 2526
2527 __clear_bit(filter_idx, table->used_bitmap);
2528 --table->used;
2529 memset(&table->spec[filter_idx], 0, sizeof(table->spec[0]));
2530
2531 efx_writeo(efx, &filter, table->offset + table->step * filter_idx);
2532
2533 /* If this filter required a greater search depth than
2534 * any other, the search limit for its type can now be
2535 * decreased. However, it is hard to determine that
2536 * unless the table has become completely empty - in
2537 * which case, all its search limits can be set to 0.
2538 */
2539 if (unlikely(table->used == 0)) {
2540 memset(table->search_limit, 0, sizeof(table->search_limit));
2541 if (table->id == EFX_FARCH_FILTER_TABLE_TX_MAC)
2542 efx_farch_filter_push_tx_limits(efx);
2543 else
2544 efx_farch_filter_push_rx_config(efx);
2545 }
2546}
2547
2548static int efx_farch_filter_remove(struct efx_nic *efx,
2549 struct efx_farch_filter_table *table,
2550 unsigned int filter_idx,
2551 enum efx_filter_priority priority)
2552{
2553 struct efx_farch_filter_spec *spec = &table->spec[filter_idx];
2554
2555 if (!test_bit(filter_idx, table->used_bitmap) ||
2556 spec->priority > priority)
2557 return -ENOENT;
2558
8803e150
BH		 2559 if (spec->flags & EFX_FILTER_FLAG_RX_STACK) {
2560 efx_farch_filter_init_rx_for_stack(efx, spec);
add72477 2561 efx_farch_filter_push_rx_config(efx);
14990a5d
BH		 2562 } else {
2563 efx_farch_filter_table_clear_entry(efx, table, filter_idx);
add72477 2564 }
14990a5d
BH		 2565
2566 return 0;
add72477
BH		 2567}
2568
2569int efx_farch_filter_remove_safe(struct efx_nic *efx,
2570 enum efx_filter_priority priority,
2571 u32 filter_id)
2572{
2573 struct efx_farch_filter_state *state = efx->filter_state;
2574 enum efx_farch_filter_table_id table_id;
2575 struct efx_farch_filter_table *table;
2576 unsigned int filter_idx;
2577 struct efx_farch_filter_spec *spec;
2578 int rc;
2579
2580 table_id = efx_farch_filter_id_table_id(filter_id);
2581 if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2582 return -ENOENT;
2583 table = &state->table[table_id];
2584
2585 filter_idx = efx_farch_filter_id_index(filter_id);
2586 if (filter_idx >= table->size)
2587 return -ENOENT;
2588 spec = &table->spec[filter_idx];
2589
2590 spin_lock_bh(&efx->filter_lock);
14990a5d 2591 rc = efx_farch_filter_remove(efx, table, filter_idx, priority);
add72477
BH		 2592 spin_unlock_bh(&efx->filter_lock);
2593
2594 return rc;
2595}
2596
2597int efx_farch_filter_get_safe(struct efx_nic *efx,
2598 enum efx_filter_priority priority,
2599 u32 filter_id, struct efx_filter_spec *spec_buf)
2600{
2601 struct efx_farch_filter_state *state = efx->filter_state;
2602 enum efx_farch_filter_table_id table_id;
2603 struct efx_farch_filter_table *table;
2604 struct efx_farch_filter_spec *spec;
2605 unsigned int filter_idx;
2606 int rc;
2607
2608 table_id = efx_farch_filter_id_table_id(filter_id);
2609 if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2610 return -ENOENT;
2611 table = &state->table[table_id];
2612
2613 filter_idx = efx_farch_filter_id_index(filter_id);
2614 if (filter_idx >= table->size)
2615 return -ENOENT;
2616 spec = &table->spec[filter_idx];
2617
2618 spin_lock_bh(&efx->filter_lock);
2619
2620 if (test_bit(filter_idx, table->used_bitmap) &&
2621 spec->priority == priority) {
2622 efx_farch_filter_to_gen_spec(spec_buf, spec);
2623 rc = 0;
2624 } else {
2625 rc = -ENOENT;
2626 }
2627
2628 spin_unlock_bh(&efx->filter_lock);
2629
2630 return rc;
2631}
2632
2633static void
2634efx_farch_filter_table_clear(struct efx_nic *efx,
2635 enum efx_farch_filter_table_id table_id,
2636 enum efx_filter_priority priority)
2637{
2638 struct efx_farch_filter_state *state = efx->filter_state;
2639 struct efx_farch_filter_table *table = &state->table[table_id];
2640 unsigned int filter_idx;
2641
2642 spin_lock_bh(&efx->filter_lock);
2643 for (filter_idx = 0; filter_idx < table->size; ++filter_idx)
14990a5d 2644 efx_farch_filter_remove(efx, table, filter_idx, priority);
add72477
BH		 2645 spin_unlock_bh(&efx->filter_lock);
2646}
2647
2648void efx_farch_filter_clear_rx(struct efx_nic *efx,
2649 enum efx_filter_priority priority)
2650{
2651 efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_IP,
2652 priority);
2653 efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_MAC,
2654 priority);
8803e150
BH		 2655 efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_DEF,
2656 priority);
add72477
BH		 2657}
2658
2659u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
2660 enum efx_filter_priority priority)
2661{
2662 struct efx_farch_filter_state *state = efx->filter_state;
2663 enum efx_farch_filter_table_id table_id;
2664 struct efx_farch_filter_table *table;
2665 unsigned int filter_idx;
2666 u32 count = 0;
2667
2668 spin_lock_bh(&efx->filter_lock);
2669
2670 for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2671 table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2672 table_id++) {
2673 table = &state->table[table_id];
2674 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2675 if (test_bit(filter_idx, table->used_bitmap) &&
2676 table->spec[filter_idx].priority == priority)
2677 ++count;
2678 }
2679 }
2680
2681 spin_unlock_bh(&efx->filter_lock);
2682
2683 return count;
2684}
2685
2686s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
2687 enum efx_filter_priority priority,
2688 u32 *buf, u32 size)
2689{
2690 struct efx_farch_filter_state *state = efx->filter_state;
2691 enum efx_farch_filter_table_id table_id;
2692 struct efx_farch_filter_table *table;
2693 unsigned int filter_idx;
2694 s32 count = 0;
2695
2696 spin_lock_bh(&efx->filter_lock);
2697
2698 for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2699 table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2700 table_id++) {
2701 table = &state->table[table_id];
2702 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2703 if (test_bit(filter_idx, table->used_bitmap) &&
2704 table->spec[filter_idx].priority == priority) {
2705 if (count == size) {
2706 count = -EMSGSIZE;
2707 goto out;
2708 }
2709 buf[count++] = efx_farch_filter_make_id(
2710 &table->spec[filter_idx], filter_idx);
2711 }
2712 }
2713 }
2714out:
2715 spin_unlock_bh(&efx->filter_lock);
2716
2717 return count;
2718}
2719
2720/* Restore filter stater after reset */
2721void efx_farch_filter_table_restore(struct efx_nic *efx)
2722{
2723 struct efx_farch_filter_state *state = efx->filter_state;
2724 enum efx_farch_filter_table_id table_id;
2725 struct efx_farch_filter_table *table;
2726 efx_oword_t filter;
2727 unsigned int filter_idx;
2728
2729 spin_lock_bh(&efx->filter_lock);
2730
2731 for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2732 table = &state->table[table_id];
2733
2734 /* Check whether this is a regular register table */
2735 if (table->step == 0)
2736 continue;
2737
2738 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2739 if (!test_bit(filter_idx, table->used_bitmap))
2740 continue;
2741 efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2742 efx_writeo(efx, &filter,
2743 table->offset + table->step * filter_idx);
2744 }
2745 }
2746
2747 efx_farch_filter_push_rx_config(efx);
2748 efx_farch_filter_push_tx_limits(efx);
2749
2750 spin_unlock_bh(&efx->filter_lock);
2751}
2752
2753void efx_farch_filter_table_remove(struct efx_nic *efx)
2754{
2755 struct efx_farch_filter_state *state = efx->filter_state;
2756 enum efx_farch_filter_table_id table_id;
2757
2758 for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2759 kfree(state->table[table_id].used_bitmap);
2760 vfree(state->table[table_id].spec);
2761 }
2762 kfree(state);
2763}
2764
2765int efx_farch_filter_table_probe(struct efx_nic *efx)
2766{
2767 struct efx_farch_filter_state *state;
2768 struct efx_farch_filter_table *table;
2769 unsigned table_id;
2770
2771 state = kzalloc(sizeof(struct efx_farch_filter_state), GFP_KERNEL);
2772 if (!state)
2773 return -ENOMEM;
2774 efx->filter_state = state;
2775
2776 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2777 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2778 table->id = EFX_FARCH_FILTER_TABLE_RX_IP;
2779 table->offset = FR_BZ_RX_FILTER_TBL0;
2780 table->size = FR_BZ_RX_FILTER_TBL0_ROWS;
2781 table->step = FR_BZ_RX_FILTER_TBL0_STEP;
2782 }
2783
2784 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
2785 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
2786 table->id = EFX_FARCH_FILTER_TABLE_RX_MAC;
2787 table->offset = FR_CZ_RX_MAC_FILTER_TBL0;
2788 table->size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
2789 table->step = FR_CZ_RX_MAC_FILTER_TBL0_STEP;
2790
2791 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2792 table->id = EFX_FARCH_FILTER_TABLE_RX_DEF;
2793 table->size = EFX_FARCH_FILTER_SIZE_RX_DEF;
2794
2795 table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2796 table->id = EFX_FARCH_FILTER_TABLE_TX_MAC;
2797 table->offset = FR_CZ_TX_MAC_FILTER_TBL0;
2798 table->size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
2799 table->step = FR_CZ_TX_MAC_FILTER_TBL0_STEP;
2800 }
2801
2802 for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2803 table = &state->table[table_id];
2804 if (table->size == 0)
2805 continue;
2806 table->used_bitmap = kcalloc(BITS_TO_LONGS(table->size),
2807 sizeof(unsigned long),
2808 GFP_KERNEL);
2809 if (!table->used_bitmap)
2810 goto fail;
2811 table->spec = vzalloc(table->size * sizeof(*table->spec));
2812 if (!table->spec)
2813 goto fail;
2814 }
2815
8803e150
BH		 2816 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2817 if (table->size) {
add72477 2818 /* RX default filters must always exist */
8803e150 2819 struct efx_farch_filter_spec *spec;
add72477 2820 unsigned i;
8803e150
BH		 2821
2822 for (i = 0; i < EFX_FARCH_FILTER_SIZE_RX_DEF; i++) {
2823 spec = &table->spec[i];
2824 spec->type = EFX_FARCH_FILTER_UC_DEF + i;
2825 efx_farch_filter_init_rx_for_stack(efx, spec);
2826 __set_bit(i, table->used_bitmap);
2827 }
add72477
BH		 2828 }
2829
2830 efx_farch_filter_push_rx_config(efx);
2831
2832 return 0;
2833
2834fail:
2835 efx_farch_filter_table_remove(efx);
2836 return -ENOMEM;
2837}
2838
2839/* Update scatter enable flags for filters pointing to our own RX queues */
2840void efx_farch_filter_update_rx_scatter(struct efx_nic *efx)
2841{
2842 struct efx_farch_filter_state *state = efx->filter_state;
2843 enum efx_farch_filter_table_id table_id;
2844 struct efx_farch_filter_table *table;
2845 efx_oword_t filter;
2846 unsigned int filter_idx;
2847
2848 spin_lock_bh(&efx->filter_lock);
2849
2850 for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2851 table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2852 table_id++) {
2853 table = &state->table[table_id];
2854
2855 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2856 if (!test_bit(filter_idx, table->used_bitmap) ||
2857 table->spec[filter_idx].dmaq_id >=
2858 efx->n_rx_channels)
2859 continue;
2860
2861 if (efx->rx_scatter)
2862 table->spec[filter_idx].flags |=
2863 EFX_FILTER_FLAG_RX_SCATTER;
2864 else
2865 table->spec[filter_idx].flags &=
2866 ~EFX_FILTER_FLAG_RX_SCATTER;
2867
2868 if (table_id == EFX_FARCH_FILTER_TABLE_RX_DEF)
2869 /* Pushed by efx_farch_filter_push_rx_config() */
2870 continue;
2871
2872 efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2873 efx_writeo(efx, &filter,
2874 table->offset + table->step * filter_idx);
2875 }
2876 }
2877
2878 efx_farch_filter_push_rx_config(efx);
2879
2880 spin_unlock_bh(&efx->filter_lock);
2881}
2882
2883#ifdef CONFIG_RFS_ACCEL
2884
2885s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
2886 struct efx_filter_spec *gen_spec)
2887{
2888 return efx_farch_filter_insert(efx, gen_spec, true);
2889}
2890
2891bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2892 unsigned int index)
2893{
2894 struct efx_farch_filter_state *state = efx->filter_state;
2895 struct efx_farch_filter_table *table =
2896 &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2897
2898 if (test_bit(index, table->used_bitmap) &&
2899 table->spec[index].priority == EFX_FILTER_PRI_HINT &&
2900 rps_may_expire_flow(efx->net_dev, table->spec[index].dmaq_id,
2901 flow_id, index)) {
2902 efx_farch_filter_table_clear_entry(efx, table, index);
2903 return true;
2904 }
2905
2906 return false;
2907}
2908
2909#endif /* CONFIG_RFS_ACCEL */
964e6135
BH		 2910
2911void efx_farch_filter_sync_rx_mode(struct efx_nic *efx)
2912{
2913 struct net_device *net_dev = efx->net_dev;
2914 struct netdev_hw_addr *ha;
2915 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2916 u32 crc;
2917 int bit;
2918
2919 netif_addr_lock_bh(net_dev);
2920
2921 efx->unicast_filter = !(net_dev->flags & IFF_PROMISC);
2922
2923 /* Build multicast hash table */
2924 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2925 memset(mc_hash, 0xff, sizeof(*mc_hash));
2926 } else {
2927 memset(mc_hash, 0x00, sizeof(*mc_hash));
2928 netdev_for_each_mc_addr(ha, net_dev) {
2929 crc = ether_crc_le(ETH_ALEN, ha->addr);
2930 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
2931 __set_bit_le(bit, mc_hash);
2932 }
2933
2934 /* Broadcast packets go through the multicast hash filter.
2935 * ether_crc_le() of the broadcast address is 0xbe2612ff
2936 * so we always add bit 0xff to the mask.
2937 */
2938 __set_bit_le(0xff, mc_hash);
2939 }
2940
2941 netif_addr_unlock_bh(net_dev);
2942}
Linux kernel - Deliverables
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