[deliverable/linux.git] / drivers / net / ethernet / sfc / io.h

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2010 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#ifndef EFX_IO_H
#define EFX_IO_H

#include <linux/io.h>
#include <linux/spinlock.h>

/**************************************************************************
 *
 * NIC register I/O
 *
 **************************************************************************
 *
 * Notes on locking strategy:
 *
 * Many CSRs are very wide and cannot be read or written atomically.
 * Writes from the host are buffered by the Bus Interface Unit (BIU)
 * up to 128 bits.  Whenever the host writes part of such a register,
 * the BIU collects the written value and does not write to the
 * underlying register until all 4 dwords have been written.  A
 * similar buffering scheme applies to host access to the NIC's 64-bit
 * SRAM.
 *
 * Writes to different CSRs and 64-bit SRAM words must be serialised,
 * since interleaved access can result in lost writes.  We use
 * efx_nic::biu_lock for this.
 *
 * We also serialise reads from 128-bit CSRs and SRAM with the same
 * spinlock.  This may not be necessary, but it doesn't really matter
 * as there are no such reads on the fast path.
 *
 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 * 128-bit but are special-cased in the BIU to avoid the need for
 * locking in the host:
 *
 * - They are write-only.
 * - The semantics of writing to these registers are such that
 *   replacing the low 96 bits with zero does not affect functionality.
 * - If the host writes to the last dword address of such a register
 *   (i.e. the high 32 bits) the underlying register will always be
 *   written.  If the collector and the current write together do not
 *   provide values for all 128 bits of the register, the low 96 bits
 *   will be written as zero.
 * - If the host writes to the address of any other part of such a
 *   register while the collector already holds values for some other
 *   register, the write is discarded and the collector maintains its
 *   current state.
 */

#if BITS_PER_LONG == 64
#define EFX_USE_QWORD_IO 1
#endif

#ifdef EFX_USE_QWORD_IO
static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
				  unsigned int reg)
{
	__raw_writeq((__force u64)value, efx->membase + reg);
}
static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
{
	return (__force __le64)__raw_readq(efx->membase + reg);
}
#endif

static inline void _efx_writed(struct efx_nic *efx, __le32 value,
				  unsigned int reg)
{
	__raw_writel((__force u32)value, efx->membase + reg);
}
static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
{
	return (__force __le32)__raw_readl(efx->membase + reg);
}

/* Write a normal 128-bit CSR, locking as appropriate. */
static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
			      unsigned int reg)
{
	unsigned long flags __attribute__ ((unused));

	netif_vdbg(efx, hw, efx->net_dev,
		   "writing register %x with " EFX_OWORD_FMT "\n", reg,
		   EFX_OWORD_VAL(*value));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef EFX_USE_QWORD_IO
	_efx_writeq(efx, value->u64[0], reg + 0);
	_efx_writeq(efx, value->u64[1], reg + 8);
#else
	_efx_writed(efx, value->u32[0], reg + 0);
	_efx_writed(efx, value->u32[1], reg + 4);
	_efx_writed(efx, value->u32[2], reg + 8);
	_efx_writed(efx, value->u32[3], reg + 12);
#endif
	mmiowb();
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
				   efx_qword_t *value, unsigned int index)
{
	unsigned int addr = index * sizeof(*value);
	unsigned long flags __attribute__ ((unused));

	netif_vdbg(efx, hw, efx->net_dev,
		   "writing SRAM address %x with " EFX_QWORD_FMT "\n",
		   addr, EFX_QWORD_VAL(*value));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef EFX_USE_QWORD_IO
	__raw_writeq((__force u64)value->u64[0], membase + addr);
#else
	__raw_writel((__force u32)value->u32[0], membase + addr);
	__raw_writel((__force u32)value->u32[1], membase + addr + 4);
#endif
	mmiowb();
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
static inline void efx_writed(struct efx_nic *efx, efx_dword_t *value,
			      unsigned int reg)
{
	netif_vdbg(efx, hw, efx->net_dev,
		   "writing register %x with "EFX_DWORD_FMT"\n",
		   reg, EFX_DWORD_VAL(*value));

	/* No lock required */
	_efx_writed(efx, value->u32[0], reg);
}

/* Read a 128-bit CSR, locking as appropriate. */
static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
			     unsigned int reg)
{
	unsigned long flags __attribute__ ((unused));

	spin_lock_irqsave(&efx->biu_lock, flags);
	value->u32[0] = _efx_readd(efx, reg + 0);
	value->u32[1] = _efx_readd(efx, reg + 4);
	value->u32[2] = _efx_readd(efx, reg + 8);
	value->u32[3] = _efx_readd(efx, reg + 12);
	spin_unlock_irqrestore(&efx->biu_lock, flags);

	netif_vdbg(efx, hw, efx->net_dev,
		   "read from register %x, got " EFX_OWORD_FMT "\n", reg,
		   EFX_OWORD_VAL(*value));
}

/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
				  efx_qword_t *value, unsigned int index)
{
	unsigned int addr = index * sizeof(*value);
	unsigned long flags __attribute__ ((unused));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef EFX_USE_QWORD_IO
	value->u64[0] = (__force __le64)__raw_readq(membase + addr);
#else
	value->u32[0] = (__force __le32)__raw_readl(membase + addr);
	value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
#endif
	spin_unlock_irqrestore(&efx->biu_lock, flags);

	netif_vdbg(efx, hw, efx->net_dev,
		   "read from SRAM address %x, got "EFX_QWORD_FMT"\n",
		   addr, EFX_QWORD_VAL(*value));
}

/* Read a 32-bit CSR or SRAM */
static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
				unsigned int reg)
{
	value->u32[0] = _efx_readd(efx, reg);
	netif_vdbg(efx, hw, efx->net_dev,
		   "read from register %x, got "EFX_DWORD_FMT"\n",
		   reg, EFX_DWORD_VAL(*value));
}

/* Write a 128-bit CSR forming part of a table */
static inline void efx_writeo_table(struct efx_nic *efx, efx_oword_t *value,
				      unsigned int reg, unsigned int index)
{
	efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Read a 128-bit CSR forming part of a table */
static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
				     unsigned int reg, unsigned int index)
{
	efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Page-mapped register block size */
#define EFX_PAGE_BLOCK_SIZE 0x2000

/* Calculate offset to page-mapped register block */
#define EFX_PAGED_REG(page, reg) \
	((page) * EFX_PAGE_BLOCK_SIZE + (reg))

/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
				    unsigned int reg, unsigned int page)
{
	reg = EFX_PAGED_REG(page, reg);

	netif_vdbg(efx, hw, efx->net_dev,
		   "writing register %x with " EFX_OWORD_FMT "\n", reg,
		   EFX_OWORD_VAL(*value));

#ifdef EFX_USE_QWORD_IO
	_efx_writeq(efx, value->u64[0], reg + 0);
	_efx_writeq(efx, value->u64[1], reg + 8);
#else
	_efx_writed(efx, value->u32[0], reg + 0);
	_efx_writed(efx, value->u32[1], reg + 4);
	_efx_writed(efx, value->u32[2], reg + 8);
	_efx_writed(efx, value->u32[3], reg + 12);
#endif
}
#define efx_writeo_page(efx, value, reg, page)				\
	_efx_writeo_page(efx, value,					\
			 reg +						\
			 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
			 page)

/* Write a page-mapped 32-bit CSR (EVQ_RPTR or the high bits of
 * RX_DESC_UPD or TX_DESC_UPD)
 */
static inline void _efx_writed_page(struct efx_nic *efx, efx_dword_t *value,
				    unsigned int reg, unsigned int page)
{
	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
}
#define efx_writed_page(efx, value, reg, page)				\
	_efx_writed_page(efx, value,					\
			 reg +						\
			 BUILD_BUG_ON_ZERO((reg) != 0x400 && (reg) != 0x83c \
					   && (reg) != 0xa1c),		\
			 page)

/* Write TIMER_COMMAND.  This is a page-mapped 32-bit CSR, but a bug
 * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
 * collector register.
 */
static inline void _efx_writed_page_locked(struct efx_nic *efx,
					   efx_dword_t *value,
					   unsigned int reg,
					   unsigned int page)
{
	unsigned long flags __attribute__ ((unused));

	if (page == 0) {
		spin_lock_irqsave(&efx->biu_lock, flags);
		efx_writed(efx, value, EFX_PAGED_REG(page, reg));
		spin_unlock_irqrestore(&efx->biu_lock, flags);
	} else {
		efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	}
}
#define efx_writed_page_locked(efx, value, reg, page)			\
	_efx_writed_page_locked(efx, value,				\
				reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
				page)

#endif /* EFX_IO_H */
Commit	Line	Data
12d00cad BH	1	/****************************************************************************
	2	* Driver for Solarflare Solarstorm network controllers and boards
	3	* Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6	4	* Copyright 2006-2010 Solarflare Communications Inc.
12d00cad BH	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
	11	#ifndef EFX_IO_H
	12	#define EFX_IO_H
	13
	14	#include <linux/io.h>
	15	#include <linux/spinlock.h>
	16
	17	/**************************************************************************
	18	*
	19	* NIC register I/O
	20	*
	21	**************************************************************************
	22	*
	23	* Notes on locking strategy:
	24	*
778cdaf6 BH	25	* Many CSRs are very wide and cannot be read or written atomically.
	26	* Writes from the host are buffered by the Bus Interface Unit (BIU)
	27	* up to 128 bits. Whenever the host writes part of such a register,
	28	* the BIU collects the written value and does not write to the
	29	* underlying register until all 4 dwords have been written. A
	30	* similar buffering scheme applies to host access to the NIC's 64-bit
	31	* SRAM.
12d00cad	32	*
778cdaf6 BH	33	* Writes to different CSRs and 64-bit SRAM words must be serialised,
	34	* since interleaved access can result in lost writes. We use
	35	* efx_nic::biu_lock for this.
	36	*
	37	* We also serialise reads from 128-bit CSRs and SRAM with the same
	38	* spinlock. This may not be necessary, but it doesn't really matter
	39	* as there are no such reads on the fast path.
12d00cad	40	*
9f2f6cd0 BH	41	* The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
	42	* 128-bit but are special-cased in the BIU to avoid the need for
	43	* locking in the host:
12d00cad	44	*
9f2f6cd0 BH	45	* - They are write-only.
	46	* - The semantics of writing to these registers are such that
	47	* replacing the low 96 bits with zero does not affect functionality.
	48	* - If the host writes to the last dword address of such a register
	49	* (i.e. the high 32 bits) the underlying register will always be
483f97f8 BH	50	* written. If the collector and the current write together do not
	51	* provide values for all 128 bits of the register, the low 96 bits
	52	* will be written as zero.
9f2f6cd0 BH	53	* - If the host writes to the address of any other part of such a
	54	* register while the collector already holds values for some other
	55	* register, the write is discarded and the collector maintains its
	56	* current state.
12d00cad BH	57	*/
	58
	59	#if BITS_PER_LONG == 64
	60	#define EFX_USE_QWORD_IO 1
	61	#endif
	62
	63	#ifdef EFX_USE_QWORD_IO
	64	static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
	65	unsigned int reg)
	66	{
	67	__raw_writeq((__force u64)value, efx->membase + reg);
	68	}
	69	static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
	70	{
	71	return (__force __le64)__raw_readq(efx->membase + reg);
	72	}
	73	#endif
	74
	75	static inline void _efx_writed(struct efx_nic *efx, __le32 value,
	76	unsigned int reg)
	77	{
	78	__raw_writel((__force u32)value, efx->membase + reg);
	79	}
	80	static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
	81	{
	82	return (__force __le32)__raw_readl(efx->membase + reg);
	83	}
	84
9f2f6cd0	85	/* Write a normal 128-bit CSR, locking as appropriate. */
12d00cad BH	86	static inline void efx_writeo(struct efx_nic efx, efx_oword_t value,
	87	unsigned int reg)
	88	{
	89	unsigned long flags __attribute__ ((unused));
	90
62776d03 BH	91	netif_vdbg(efx, hw, efx->net_dev,
	92	"writing register %x with " EFX_OWORD_FMT "\n", reg,
	93	EFX_OWORD_VAL(*value));
12d00cad BH	94
	95	spin_lock_irqsave(&efx->biu_lock, flags);
	96	#ifdef EFX_USE_QWORD_IO
	97	_efx_writeq(efx, value->u64[0], reg + 0);
12d00cad BH	98	_efx_writeq(efx, value->u64[1], reg + 8);
	99	#else
	100	_efx_writed(efx, value->u32[0], reg + 0);
	101	_efx_writed(efx, value->u32[1], reg + 4);
	102	_efx_writed(efx, value->u32[2], reg + 8);
12d00cad BH	103	_efx_writed(efx, value->u32[3], reg + 12);
	104	#endif
	105	mmiowb();
	106	spin_unlock_irqrestore(&efx->biu_lock, flags);
	107	}
	108
9f2f6cd0	109	/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
12d00cad BH	110	static inline void efx_sram_writeq(struct efx_nic efx, void __iomem membase,
	111	efx_qword_t *value, unsigned int index)
	112	{
	113	unsigned int addr = index * sizeof(*value);
	114	unsigned long flags __attribute__ ((unused));
	115
62776d03 BH	116	netif_vdbg(efx, hw, efx->net_dev,
	117	"writing SRAM address %x with " EFX_QWORD_FMT "\n",
	118	addr, EFX_QWORD_VAL(*value));
12d00cad BH	119
	120	spin_lock_irqsave(&efx->biu_lock, flags);
	121	#ifdef EFX_USE_QWORD_IO
	122	__raw_writeq((__force u64)value->u64[0], membase + addr);
	123	#else
	124	__raw_writel((__force u32)value->u32[0], membase + addr);
12d00cad BH	125	__raw_writel((__force u32)value->u32[1], membase + addr + 4);
	126	#endif
	127	mmiowb();
	128	spin_unlock_irqrestore(&efx->biu_lock, flags);
	129	}
	130
9f2f6cd0	131	/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
12d00cad BH	132	static inline void efx_writed(struct efx_nic efx, efx_dword_t value,
	133	unsigned int reg)
	134	{
62776d03	135	netif_vdbg(efx, hw, efx->net_dev,
9f2f6cd0	136	"writing register %x with "EFX_DWORD_FMT"\n",
62776d03	137	reg, EFX_DWORD_VAL(*value));
12d00cad BH	138
	139	/* No lock required */
	140	_efx_writed(efx, value->u32[0], reg);
	141	}
	142
9f2f6cd0	143	/* Read a 128-bit CSR, locking as appropriate. */
12d00cad BH	144	static inline void efx_reado(struct efx_nic efx, efx_oword_t value,
	145	unsigned int reg)
	146	{
	147	unsigned long flags __attribute__ ((unused));
	148
	149	spin_lock_irqsave(&efx->biu_lock, flags);
	150	value->u32[0] = _efx_readd(efx, reg + 0);
12d00cad BH	151	value->u32[1] = _efx_readd(efx, reg + 4);
	152	value->u32[2] = _efx_readd(efx, reg + 8);
	153	value->u32[3] = _efx_readd(efx, reg + 12);
	154	spin_unlock_irqrestore(&efx->biu_lock, flags);
	155
62776d03 BH	156	netif_vdbg(efx, hw, efx->net_dev,
	157	"read from register %x, got " EFX_OWORD_FMT "\n", reg,
	158	EFX_OWORD_VAL(*value));
12d00cad BH	159	}
12d00cad BH	160
9f2f6cd0	161	/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
12d00cad BH	162	static inline void efx_sram_readq(struct efx_nic efx, void __iomem membase,
	163	efx_qword_t *value, unsigned int index)
	164	{
	165	unsigned int addr = index * sizeof(*value);
	166	unsigned long flags __attribute__ ((unused));
	167
	168	spin_lock_irqsave(&efx->biu_lock, flags);
	169	#ifdef EFX_USE_QWORD_IO
	170	value->u64[0] = (__force __le64)__raw_readq(membase + addr);
	171	#else
	172	value->u32[0] = (__force __le32)__raw_readl(membase + addr);
12d00cad BH	173	value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
	174	#endif
	175	spin_unlock_irqrestore(&efx->biu_lock, flags);
	176
62776d03 BH	177	netif_vdbg(efx, hw, efx->net_dev,
	178	"read from SRAM address %x, got "EFX_QWORD_FMT"\n",
	179	addr, EFX_QWORD_VAL(*value));
12d00cad BH	180	}
12d00cad BH	181
9f2f6cd0	182	/* Read a 32-bit CSR or SRAM */
12d00cad BH	183	static inline void efx_readd(struct efx_nic efx, efx_dword_t value,
	184	unsigned int reg)
	185	{
	186	value->u32[0] = _efx_readd(efx, reg);
62776d03 BH	187	netif_vdbg(efx, hw, efx->net_dev,
	188	"read from register %x, got "EFX_DWORD_FMT"\n",
	189	reg, EFX_DWORD_VAL(*value));
12d00cad BH	190	}
12d00cad BH	191
9f2f6cd0	192	/* Write a 128-bit CSR forming part of a table */
12d00cad BH	193	static inline void efx_writeo_table(struct efx_nic efx, efx_oword_t value,
	194	unsigned int reg, unsigned int index)
	195	{
	196	efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
	197	}
	198
9f2f6cd0	199	/* Read a 128-bit CSR forming part of a table */
12d00cad BH	200	static inline void efx_reado_table(struct efx_nic efx, efx_oword_t value,
	201	unsigned int reg, unsigned int index)
	202	{
	203	efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
	204	}
	205
12d00cad BH	206	/* Page-mapped register block size */
	207	#define EFX_PAGE_BLOCK_SIZE 0x2000
	208
	209	/* Calculate offset to page-mapped register block */
	210	#define EFX_PAGED_REG(page, reg) \
	211	((page) * EFX_PAGE_BLOCK_SIZE + (reg))
	212
9f2f6cd0	213	/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
1a29cc40 BH	214	static inline void _efx_writeo_page(struct efx_nic efx, efx_oword_t value,
1a29cc40 BH	215	unsigned int reg, unsigned int page)
12d00cad	216	{
e5061472 BH	217	reg = EFX_PAGED_REG(page, reg);
	218
	219	netif_vdbg(efx, hw, efx->net_dev,
	220	"writing register %x with " EFX_OWORD_FMT "\n", reg,
	221	EFX_OWORD_VAL(*value));
	222
	223	#ifdef EFX_USE_QWORD_IO
	224	_efx_writeq(efx, value->u64[0], reg + 0);
483f97f8	225	_efx_writeq(efx, value->u64[1], reg + 8);
e5061472 BH	226	#else
	227	_efx_writed(efx, value->u32[0], reg + 0);
	228	_efx_writed(efx, value->u32[1], reg + 4);
e5061472 BH	229	_efx_writed(efx, value->u32[2], reg + 8);
e5061472 BH	230	_efx_writed(efx, value->u32[3], reg + 12);
483f97f8	231	#endif
12d00cad	232	}
1a29cc40 BH	233	#define efx_writeo_page(efx, value, reg, page) \
	234	_efx_writeo_page(efx, value, \
	235	reg + \
	236	BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
	237	page)
12d00cad	238
9f2f6cd0 BH	239	/* Write a page-mapped 32-bit CSR (EVQ_RPTR or the high bits of
	240	* RX_DESC_UPD or TX_DESC_UPD)
	241	*/
1a29cc40 BH	242	static inline void _efx_writed_page(struct efx_nic efx, efx_dword_t value,
1a29cc40 BH	243	unsigned int reg, unsigned int page)
12d00cad BH	244	{
	245	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	246	}
1a29cc40 BH	247	#define efx_writed_page(efx, value, reg, page) \
	248	_efx_writed_page(efx, value, \
	249	reg + \
	250	BUILD_BUG_ON_ZERO((reg) != 0x400 && (reg) != 0x83c \
	251	&& (reg) != 0xa1c), \
	252	page)
12d00cad	253
9f2f6cd0 BH	254	/* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
	255	* in the BIU means that writes to TIMER_COMMAND[0] invalidate the
	256	* collector register.
	257	*/
1a29cc40 BH	258	static inline void _efx_writed_page_locked(struct efx_nic *efx,
	259	efx_dword_t *value,
	260	unsigned int reg,
	261	unsigned int page)
12d00cad BH	262	{
	263	unsigned long flags __attribute__ ((unused));
	264
	265	if (page == 0) {
	266	spin_lock_irqsave(&efx->biu_lock, flags);
	267	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	268	spin_unlock_irqrestore(&efx->biu_lock, flags);
	269	} else {
	270	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	271	}
	272	}
1a29cc40 BH	273	#define efx_writed_page_locked(efx, value, reg, page) \
	274	_efx_writed_page_locked(efx, value, \
	275	reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
	276	page)
12d00cad BH	277
12d00cad BH	278	#endif /* EFX_IO_H */