[deliverable/linux.git] / drivers / net / ethernet / sfc / io.h

/****************************************************************************
 * Driver for Solarflare network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2013 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#ifndef EFX_IO_H
#define EFX_IO_H

#include <linux/io.h>
#include <linux/spinlock.h>

/**************************************************************************
 *
 * NIC register I/O
 *
 **************************************************************************
 *
 * Notes on locking strategy for the Falcon architecture:
 *
 * Many CSRs are very wide and cannot be read or written atomically.
 * Writes from the host are buffered by the Bus Interface Unit (BIU)
 * up to 128 bits.  Whenever the host writes part of such a register,
 * the BIU collects the written value and does not write to the
 * underlying register until all 4 dwords have been written.  A
 * similar buffering scheme applies to host access to the NIC's 64-bit
 * SRAM.
 *
 * Writes to different CSRs and 64-bit SRAM words must be serialised,
 * since interleaved access can result in lost writes.  We use
 * efx_nic::biu_lock for this.
 *
 * We also serialise reads from 128-bit CSRs and SRAM with the same
 * spinlock.  This may not be necessary, but it doesn't really matter
 * as there are no such reads on the fast path.
 *
 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 * 128-bit but are special-cased in the BIU to avoid the need for
 * locking in the host:
 *
 * - They are write-only.
 * - The semantics of writing to these registers are such that
 *   replacing the low 96 bits with zero does not affect functionality.
 * - If the host writes to the last dword address of such a register
 *   (i.e. the high 32 bits) the underlying register will always be
 *   written.  If the collector and the current write together do not
 *   provide values for all 128 bits of the register, the low 96 bits
 *   will be written as zero.
 * - If the host writes to the address of any other part of such a
 *   register while the collector already holds values for some other
 *   register, the write is discarded and the collector maintains its
 *   current state.
 *
 * The EF10 architecture exposes very few registers to the host and
 * most of them are only 32 bits wide.  The only exceptions are the MC
 * doorbell register pair, which has its own latching, and
 * TX_DESC_UPD, which works in a similar way to the Falcon
 * architecture.
 */

#if BITS_PER_LONG == 64
#define EFX_USE_QWORD_IO 1
#endif

/* Hardware issue requires that only 64-bit naturally aligned writes
 * are seen by hardware. Its not strictly necessary to restrict to
 * x86_64 arch, but done for safety since unusual write combining behaviour
 * can break PIO.
 */
#ifdef CONFIG_X86_64
/* PIO is a win only if write-combining is possible */
#ifdef ARCH_HAS_IOREMAP_WC
#define EFX_USE_PIO 1
#endif
#endif

#ifdef EFX_USE_QWORD_IO
static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
				  unsigned int reg)
{
	__raw_writeq((__force u64)value, efx->membase + reg);
}
static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
{
	return (__force __le64)__raw_readq(efx->membase + reg);
}
#endif

static inline void _efx_writed(struct efx_nic *efx, __le32 value,
				  unsigned int reg)
{
	__raw_writel((__force u32)value, efx->membase + reg);
}
static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
{
	return (__force __le32)__raw_readl(efx->membase + reg);
}

/* Write a normal 128-bit CSR, locking as appropriate. */
static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value,
			      unsigned int reg)
{
	unsigned long flags __attribute__ ((unused));

	netif_vdbg(efx, hw, efx->net_dev,
		   "writing register %x with " EFX_OWORD_FMT "\n", reg,
		   EFX_OWORD_VAL(*value));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef EFX_USE_QWORD_IO
	_efx_writeq(efx, value->u64[0], reg + 0);
	_efx_writeq(efx, value->u64[1], reg + 8);
#else
	_efx_writed(efx, value->u32[0], reg + 0);
	_efx_writed(efx, value->u32[1], reg + 4);
	_efx_writed(efx, value->u32[2], reg + 8);
	_efx_writed(efx, value->u32[3], reg + 12);
#endif
	mmiowb();
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
				   const efx_qword_t *value, unsigned int index)
{
	unsigned int addr = index * sizeof(*value);
	unsigned long flags __attribute__ ((unused));

	netif_vdbg(efx, hw, efx->net_dev,
		   "writing SRAM address %x with " EFX_QWORD_FMT "\n",
		   addr, EFX_QWORD_VAL(*value));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef EFX_USE_QWORD_IO
	__raw_writeq((__force u64)value->u64[0], membase + addr);
#else
	__raw_writel((__force u32)value->u32[0], membase + addr);
	__raw_writel((__force u32)value->u32[1], membase + addr + 4);
#endif
	mmiowb();
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value,
			      unsigned int reg)
{
	netif_vdbg(efx, hw, efx->net_dev,
		   "writing register %x with "EFX_DWORD_FMT"\n",
		   reg, EFX_DWORD_VAL(*value));

	/* No lock required */
	_efx_writed(efx, value->u32[0], reg);
}

/* Read a 128-bit CSR, locking as appropriate. */
static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
			     unsigned int reg)
{
	unsigned long flags __attribute__ ((unused));

	spin_lock_irqsave(&efx->biu_lock, flags);
	value->u32[0] = _efx_readd(efx, reg + 0);
	value->u32[1] = _efx_readd(efx, reg + 4);
	value->u32[2] = _efx_readd(efx, reg + 8);
	value->u32[3] = _efx_readd(efx, reg + 12);
	spin_unlock_irqrestore(&efx->biu_lock, flags);

	netif_vdbg(efx, hw, efx->net_dev,
		   "read from register %x, got " EFX_OWORD_FMT "\n", reg,
		   EFX_OWORD_VAL(*value));
}

/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
				  efx_qword_t *value, unsigned int index)
{
	unsigned int addr = index * sizeof(*value);
	unsigned long flags __attribute__ ((unused));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef EFX_USE_QWORD_IO
	value->u64[0] = (__force __le64)__raw_readq(membase + addr);
#else
	value->u32[0] = (__force __le32)__raw_readl(membase + addr);
	value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
#endif
	spin_unlock_irqrestore(&efx->biu_lock, flags);

	netif_vdbg(efx, hw, efx->net_dev,
		   "read from SRAM address %x, got "EFX_QWORD_FMT"\n",
		   addr, EFX_QWORD_VAL(*value));
}

/* Read a 32-bit CSR or SRAM */
static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
				unsigned int reg)
{
	value->u32[0] = _efx_readd(efx, reg);
	netif_vdbg(efx, hw, efx->net_dev,
		   "read from register %x, got "EFX_DWORD_FMT"\n",
		   reg, EFX_DWORD_VAL(*value));
}

/* Write a 128-bit CSR forming part of a table */
static inline void
efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value,
		 unsigned int reg, unsigned int index)
{
	efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Read a 128-bit CSR forming part of a table */
static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
				     unsigned int reg, unsigned int index)
{
	efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Page size used as step between per-VI registers */
#define EFX_VI_PAGE_SIZE 0x2000

/* Calculate offset to page-mapped register */
#define EFX_PAGED_REG(page, reg) \
	((page) * EFX_VI_PAGE_SIZE + (reg))

/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
				    unsigned int reg, unsigned int page)
{
	reg = EFX_PAGED_REG(page, reg);

	netif_vdbg(efx, hw, efx->net_dev,
		   "writing register %x with " EFX_OWORD_FMT "\n", reg,
		   EFX_OWORD_VAL(*value));

#ifdef EFX_USE_QWORD_IO
	_efx_writeq(efx, value->u64[0], reg + 0);
	_efx_writeq(efx, value->u64[1], reg + 8);
#else
	_efx_writed(efx, value->u32[0], reg + 0);
	_efx_writed(efx, value->u32[1], reg + 4);
	_efx_writed(efx, value->u32[2], reg + 8);
	_efx_writed(efx, value->u32[3], reg + 12);
#endif
}
#define efx_writeo_page(efx, value, reg, page)				\
	_efx_writeo_page(efx, value,					\
			 reg +						\
			 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
			 page)

/* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
 * high bits of RX_DESC_UPD or TX_DESC_UPD)
 */
static inline void
_efx_writed_page(struct efx_nic *efx, const efx_dword_t *value,
		 unsigned int reg, unsigned int page)
{
	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
}
#define efx_writed_page(efx, value, reg, page)				\
	_efx_writed_page(efx, value,					\
			 reg +						\
			 BUILD_BUG_ON_ZERO((reg) != 0x400 &&		\
					   (reg) != 0x420 &&		\
					   (reg) != 0x830 &&		\
					   (reg) != 0x83c &&		\
					   (reg) != 0xa18 &&		\
					   (reg) != 0xa1c),		\
			 page)

/* Write TIMER_COMMAND.  This is a page-mapped 32-bit CSR, but a bug
 * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
 * collector register.
 */
static inline void _efx_writed_page_locked(struct efx_nic *efx,
					   const efx_dword_t *value,
					   unsigned int reg,
					   unsigned int page)
{
	unsigned long flags __attribute__ ((unused));

	if (page == 0) {
		spin_lock_irqsave(&efx->biu_lock, flags);
		efx_writed(efx, value, EFX_PAGED_REG(page, reg));
		spin_unlock_irqrestore(&efx->biu_lock, flags);
	} else {
		efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	}
}
#define efx_writed_page_locked(efx, value, reg, page)			\
	_efx_writed_page_locked(efx, value,				\
				reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
				page)

#endif /* EFX_IO_H */
Commit	Line	Data
12d00cad	1	/****************************************************************************
f7a6d2c4	2	* Driver for Solarflare network controllers and boards
12d00cad	3	* Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4	4	* Copyright 2006-2013 Solarflare Communications Inc.
12d00cad BH	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
	11	#ifndef EFX_IO_H
	12	#define EFX_IO_H
	13
	14	#include <linux/io.h>
	15	#include <linux/spinlock.h>
	16
	17	/**************************************************************************
	18	*
	19	* NIC register I/O
	20	*
	21	**************************************************************************
	22	*
9c517165	23	* Notes on locking strategy for the Falcon architecture:
12d00cad	24	*
778cdaf6 BH	25	* Many CSRs are very wide and cannot be read or written atomically.
	26	* Writes from the host are buffered by the Bus Interface Unit (BIU)
	27	* up to 128 bits. Whenever the host writes part of such a register,
	28	* the BIU collects the written value and does not write to the
	29	* underlying register until all 4 dwords have been written. A
	30	* similar buffering scheme applies to host access to the NIC's 64-bit
	31	* SRAM.
12d00cad	32	*
778cdaf6 BH	33	* Writes to different CSRs and 64-bit SRAM words must be serialised,
	34	* since interleaved access can result in lost writes. We use
	35	* efx_nic::biu_lock for this.
	36	*
	37	* We also serialise reads from 128-bit CSRs and SRAM with the same
	38	* spinlock. This may not be necessary, but it doesn't really matter
	39	* as there are no such reads on the fast path.
12d00cad	40	*
9f2f6cd0 BH	41	* The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
	42	* 128-bit but are special-cased in the BIU to avoid the need for
	43	* locking in the host:
12d00cad	44	*
9f2f6cd0 BH	45	* - They are write-only.
	46	* - The semantics of writing to these registers are such that
	47	* replacing the low 96 bits with zero does not affect functionality.
	48	* - If the host writes to the last dword address of such a register
	49	* (i.e. the high 32 bits) the underlying register will always be
483f97f8 BH	50	* written. If the collector and the current write together do not
	51	* provide values for all 128 bits of the register, the low 96 bits
	52	* will be written as zero.
9f2f6cd0 BH	53	* - If the host writes to the address of any other part of such a
	54	* register while the collector already holds values for some other
	55	* register, the write is discarded and the collector maintains its
	56	* current state.
9c517165 BH	57	*
	58	* The EF10 architecture exposes very few registers to the host and
	59	* most of them are only 32 bits wide. The only exceptions are the MC
	60	* doorbell register pair, which has its own latching, and
	61	* TX_DESC_UPD, which works in a similar way to the Falcon
	62	* architecture.
12d00cad BH	63	*/
	64
	65	#if BITS_PER_LONG == 64
	66	#define EFX_USE_QWORD_IO 1
	67	#endif
	68
daf37b55 JC	69	/* Hardware issue requires that only 64-bit naturally aligned writes
	70	* are seen by hardware. Its not strictly necessary to restrict to
	71	* x86_64 arch, but done for safety since unusual write combining behaviour
	72	* can break PIO.
	73	*/
	74	#ifdef CONFIG_X86_64
183233be BH	75	/* PIO is a win only if write-combining is possible */
	76	#ifdef ARCH_HAS_IOREMAP_WC
	77	#define EFX_USE_PIO 1
	78	#endif
daf37b55	79	#endif
183233be	80
12d00cad BH	81	#ifdef EFX_USE_QWORD_IO
	82	static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
	83	unsigned int reg)
	84	{
	85	__raw_writeq((__force u64)value, efx->membase + reg);
	86	}
	87	static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
	88	{
	89	return (__force __le64)__raw_readq(efx->membase + reg);
	90	}
	91	#endif
	92
	93	static inline void _efx_writed(struct efx_nic *efx, __le32 value,
	94	unsigned int reg)
	95	{
	96	__raw_writel((__force u32)value, efx->membase + reg);
	97	}
	98	static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
	99	{
	100	return (__force __le32)__raw_readl(efx->membase + reg);
	101	}
	102
9f2f6cd0	103	/* Write a normal 128-bit CSR, locking as appropriate. */
5383825c	104	static inline void efx_writeo(struct efx_nic efx, const efx_oword_t value,
12d00cad BH	105	unsigned int reg)
	106	{
	107	unsigned long flags __attribute__ ((unused));
	108
62776d03 BH	109	netif_vdbg(efx, hw, efx->net_dev,
	110	"writing register %x with " EFX_OWORD_FMT "\n", reg,
	111	EFX_OWORD_VAL(*value));
12d00cad BH	112
	113	spin_lock_irqsave(&efx->biu_lock, flags);
	114	#ifdef EFX_USE_QWORD_IO
	115	_efx_writeq(efx, value->u64[0], reg + 0);
12d00cad BH	116	_efx_writeq(efx, value->u64[1], reg + 8);
	117	#else
	118	_efx_writed(efx, value->u32[0], reg + 0);
	119	_efx_writed(efx, value->u32[1], reg + 4);
	120	_efx_writed(efx, value->u32[2], reg + 8);
12d00cad BH	121	_efx_writed(efx, value->u32[3], reg + 12);
	122	#endif
	123	mmiowb();
	124	spin_unlock_irqrestore(&efx->biu_lock, flags);
	125	}
	126
9f2f6cd0	127	/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
12d00cad	128	static inline void efx_sram_writeq(struct efx_nic efx, void __iomem membase,
5383825c	129	const efx_qword_t *value, unsigned int index)
12d00cad BH	130	{
	131	unsigned int addr = index * sizeof(*value);
	132	unsigned long flags __attribute__ ((unused));
	133
62776d03 BH	134	netif_vdbg(efx, hw, efx->net_dev,
	135	"writing SRAM address %x with " EFX_QWORD_FMT "\n",
	136	addr, EFX_QWORD_VAL(*value));
12d00cad BH	137
	138	spin_lock_irqsave(&efx->biu_lock, flags);
	139	#ifdef EFX_USE_QWORD_IO
	140	__raw_writeq((__force u64)value->u64[0], membase + addr);
	141	#else
	142	__raw_writel((__force u32)value->u32[0], membase + addr);
12d00cad BH	143	__raw_writel((__force u32)value->u32[1], membase + addr + 4);
	144	#endif
	145	mmiowb();
	146	spin_unlock_irqrestore(&efx->biu_lock, flags);
	147	}
	148
9f2f6cd0	149	/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
5383825c	150	static inline void efx_writed(struct efx_nic efx, const efx_dword_t value,
12d00cad BH	151	unsigned int reg)
12d00cad BH	152	{
62776d03	153	netif_vdbg(efx, hw, efx->net_dev,
9f2f6cd0	154	"writing register %x with "EFX_DWORD_FMT"\n",
62776d03	155	reg, EFX_DWORD_VAL(*value));
12d00cad BH	156
	157	/* No lock required */
	158	_efx_writed(efx, value->u32[0], reg);
	159	}
	160
9f2f6cd0	161	/* Read a 128-bit CSR, locking as appropriate. */
12d00cad BH	162	static inline void efx_reado(struct efx_nic efx, efx_oword_t value,
	163	unsigned int reg)
	164	{
	165	unsigned long flags __attribute__ ((unused));
	166
	167	spin_lock_irqsave(&efx->biu_lock, flags);
	168	value->u32[0] = _efx_readd(efx, reg + 0);
12d00cad BH	169	value->u32[1] = _efx_readd(efx, reg + 4);
	170	value->u32[2] = _efx_readd(efx, reg + 8);
	171	value->u32[3] = _efx_readd(efx, reg + 12);
	172	spin_unlock_irqrestore(&efx->biu_lock, flags);
	173
62776d03 BH	174	netif_vdbg(efx, hw, efx->net_dev,
	175	"read from register %x, got " EFX_OWORD_FMT "\n", reg,
	176	EFX_OWORD_VAL(*value));
12d00cad BH	177	}
12d00cad BH	178
9f2f6cd0	179	/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
12d00cad BH	180	static inline void efx_sram_readq(struct efx_nic efx, void __iomem membase,
	181	efx_qword_t *value, unsigned int index)
	182	{
	183	unsigned int addr = index * sizeof(*value);
	184	unsigned long flags __attribute__ ((unused));
	185
	186	spin_lock_irqsave(&efx->biu_lock, flags);
	187	#ifdef EFX_USE_QWORD_IO
	188	value->u64[0] = (__force __le64)__raw_readq(membase + addr);
	189	#else
	190	value->u32[0] = (__force __le32)__raw_readl(membase + addr);
12d00cad BH	191	value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
	192	#endif
	193	spin_unlock_irqrestore(&efx->biu_lock, flags);
	194
62776d03 BH	195	netif_vdbg(efx, hw, efx->net_dev,
	196	"read from SRAM address %x, got "EFX_QWORD_FMT"\n",
	197	addr, EFX_QWORD_VAL(*value));
12d00cad BH	198	}
12d00cad BH	199
9f2f6cd0	200	/* Read a 32-bit CSR or SRAM */
12d00cad BH	201	static inline void efx_readd(struct efx_nic efx, efx_dword_t value,
	202	unsigned int reg)
	203	{
	204	value->u32[0] = _efx_readd(efx, reg);
62776d03 BH	205	netif_vdbg(efx, hw, efx->net_dev,
	206	"read from register %x, got "EFX_DWORD_FMT"\n",
	207	reg, EFX_DWORD_VAL(*value));
12d00cad BH	208	}
12d00cad BH	209
9f2f6cd0	210	/* Write a 128-bit CSR forming part of a table */
5383825c BH	211	static inline void
	212	efx_writeo_table(struct efx_nic efx, const efx_oword_t value,
	213	unsigned int reg, unsigned int index)
12d00cad BH	214	{
	215	efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
	216	}
	217
9f2f6cd0	218	/* Read a 128-bit CSR forming part of a table */
12d00cad BH	219	static inline void efx_reado_table(struct efx_nic efx, efx_oword_t value,
	220	unsigned int reg, unsigned int index)
	221	{
	222	efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
	223	}
	224
64a27752 BH	225	/* Page size used as step between per-VI registers */
64a27752 BH	226	#define EFX_VI_PAGE_SIZE 0x2000
12d00cad	227
64a27752	228	/* Calculate offset to page-mapped register */
12d00cad	229	#define EFX_PAGED_REG(page, reg) \
64a27752	230	((page) * EFX_VI_PAGE_SIZE + (reg))
12d00cad	231
9f2f6cd0	232	/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
1a29cc40 BH	233	static inline void _efx_writeo_page(struct efx_nic efx, efx_oword_t value,
1a29cc40 BH	234	unsigned int reg, unsigned int page)
12d00cad	235	{
e5061472 BH	236	reg = EFX_PAGED_REG(page, reg);
	237
	238	netif_vdbg(efx, hw, efx->net_dev,
	239	"writing register %x with " EFX_OWORD_FMT "\n", reg,
	240	EFX_OWORD_VAL(*value));
	241
	242	#ifdef EFX_USE_QWORD_IO
	243	_efx_writeq(efx, value->u64[0], reg + 0);
483f97f8	244	_efx_writeq(efx, value->u64[1], reg + 8);
e5061472 BH	245	#else
	246	_efx_writed(efx, value->u32[0], reg + 0);
	247	_efx_writed(efx, value->u32[1], reg + 4);
e5061472 BH	248	_efx_writed(efx, value->u32[2], reg + 8);
e5061472 BH	249	_efx_writed(efx, value->u32[3], reg + 12);
483f97f8	250	#endif
12d00cad	251	}
1a29cc40 BH	252	#define efx_writeo_page(efx, value, reg, page) \
	253	_efx_writeo_page(efx, value, \
	254	reg + \
	255	BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
	256	page)
12d00cad	257
9c517165 BH	258	/* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
9c517165 BH	259	* high bits of RX_DESC_UPD or TX_DESC_UPD)
9f2f6cd0	260	*/
5383825c BH	261	static inline void
	262	_efx_writed_page(struct efx_nic efx, const efx_dword_t value,
	263	unsigned int reg, unsigned int page)
12d00cad BH	264	{
	265	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	266	}
1a29cc40 BH	267	#define efx_writed_page(efx, value, reg, page) \
	268	_efx_writed_page(efx, value, \
	269	reg + \
9c517165 BH	270	BUILD_BUG_ON_ZERO((reg) != 0x400 && \
	271	(reg) != 0x420 && \
	272	(reg) != 0x830 && \
	273	(reg) != 0x83c && \
	274	(reg) != 0xa18 && \
	275	(reg) != 0xa1c), \
1a29cc40	276	page)
12d00cad	277
9f2f6cd0 BH	278	/* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
	279	* in the BIU means that writes to TIMER_COMMAND[0] invalidate the
	280	* collector register.
	281	*/
1a29cc40	282	static inline void _efx_writed_page_locked(struct efx_nic *efx,
5383825c	283	const efx_dword_t *value,
1a29cc40 BH	284	unsigned int reg,
1a29cc40 BH	285	unsigned int page)
12d00cad BH	286	{
	287	unsigned long flags __attribute__ ((unused));
	288
	289	if (page == 0) {
	290	spin_lock_irqsave(&efx->biu_lock, flags);
	291	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	292	spin_unlock_irqrestore(&efx->biu_lock, flags);
	293	} else {
	294	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	295	}
	296	}
1a29cc40 BH	297	#define efx_writed_page_locked(efx, value, reg, page) \
	298	_efx_writed_page_locked(efx, value, \
	299	reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
	300	page)
12d00cad BH	301
12d00cad BH	302	#endif /* EFX_IO_H */