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afd4aea0 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
0a6f40c6 | 3 | * Copyright 2008-2011 Solarflare Communications Inc. |
afd4aea0 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
251111d9 | 11 | #include <asm/cmpxchg.h> |
afd4aea0 BH |
12 | #include "net_driver.h" |
13 | #include "nic.h" | |
14 | #include "io.h" | |
8b8a95a1 | 15 | #include "farch_regs.h" |
afd4aea0 BH |
16 | #include "mcdi_pcol.h" |
17 | #include "phy.h" | |
18 | ||
19 | /************************************************************************** | |
20 | * | |
21 | * Management-Controller-to-Driver Interface | |
22 | * | |
23 | ************************************************************************** | |
24 | */ | |
25 | ||
ebf98e79 | 26 | #define MCDI_RPC_TIMEOUT (10 * HZ) |
afd4aea0 | 27 | |
3f713bf4 BH |
28 | /* A reboot/assertion causes the MCDI status word to be set after the |
29 | * command word is set or a REBOOT event is sent. If we notice a reboot | |
d36a08b4 DP |
30 | * via these mechanisms then wait 20ms for the status word to be set. |
31 | */ | |
3f713bf4 | 32 | #define MCDI_STATUS_DELAY_US 100 |
d36a08b4 | 33 | #define MCDI_STATUS_DELAY_COUNT 200 |
3f713bf4 BH |
34 | #define MCDI_STATUS_SLEEP_MS \ |
35 | (MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000) | |
afd4aea0 BH |
36 | |
37 | #define SEQ_MASK \ | |
38 | EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ)) | |
39 | ||
cade715f BH |
40 | struct efx_mcdi_async_param { |
41 | struct list_head list; | |
42 | unsigned int cmd; | |
43 | size_t inlen; | |
44 | size_t outlen; | |
45 | efx_mcdi_async_completer *complete; | |
46 | unsigned long cookie; | |
47 | /* followed by request/response buffer */ | |
48 | }; | |
49 | ||
50 | static void efx_mcdi_timeout_async(unsigned long context); | |
51 | ||
afd4aea0 BH |
52 | static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx) |
53 | { | |
f3ad5003 BH |
54 | EFX_BUG_ON_PARANOID(!efx->mcdi); |
55 | return &efx->mcdi->iface; | |
afd4aea0 BH |
56 | } |
57 | ||
f073dde0 | 58 | int efx_mcdi_init(struct efx_nic *efx) |
afd4aea0 BH |
59 | { |
60 | struct efx_mcdi_iface *mcdi; | |
61 | ||
f3ad5003 BH |
62 | efx->mcdi = kzalloc(sizeof(*efx->mcdi), GFP_KERNEL); |
63 | if (!efx->mcdi) | |
64 | return -ENOMEM; | |
65 | ||
afd4aea0 | 66 | mcdi = efx_mcdi(efx); |
cade715f | 67 | mcdi->efx = efx; |
afd4aea0 BH |
68 | init_waitqueue_head(&mcdi->wq); |
69 | spin_lock_init(&mcdi->iface_lock); | |
251111d9 | 70 | mcdi->state = MCDI_STATE_QUIESCENT; |
afd4aea0 | 71 | mcdi->mode = MCDI_MODE_POLL; |
cade715f BH |
72 | spin_lock_init(&mcdi->async_lock); |
73 | INIT_LIST_HEAD(&mcdi->async_list); | |
74 | setup_timer(&mcdi->async_timer, efx_mcdi_timeout_async, | |
75 | (unsigned long)mcdi); | |
afd4aea0 BH |
76 | |
77 | (void) efx_mcdi_poll_reboot(efx); | |
d36a08b4 | 78 | mcdi->new_epoch = true; |
f073dde0 BH |
79 | |
80 | /* Recover from a failed assertion before probing */ | |
81 | return efx_mcdi_handle_assertion(efx); | |
afd4aea0 BH |
82 | } |
83 | ||
f3ad5003 BH |
84 | void efx_mcdi_fini(struct efx_nic *efx) |
85 | { | |
251111d9 | 86 | BUG_ON(efx->mcdi && efx->mcdi->iface.state != MCDI_STATE_QUIESCENT); |
f3ad5003 BH |
87 | kfree(efx->mcdi); |
88 | } | |
89 | ||
2f4bcdcc BH |
90 | static void efx_mcdi_send_request(struct efx_nic *efx, unsigned cmd, |
91 | const efx_dword_t *inbuf, size_t inlen) | |
afd4aea0 BH |
92 | { |
93 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
df2cd8af BH |
94 | efx_dword_t hdr[2]; |
95 | size_t hdr_len; | |
afd4aea0 BH |
96 | u32 xflags, seqno; |
97 | ||
251111d9 | 98 | BUG_ON(mcdi->state == MCDI_STATE_QUIESCENT); |
afd4aea0 | 99 | |
2f4bcdcc BH |
100 | /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */ |
101 | spin_lock_bh(&mcdi->iface_lock); | |
102 | ++mcdi->seqno; | |
103 | spin_unlock_bh(&mcdi->iface_lock); | |
104 | ||
afd4aea0 BH |
105 | seqno = mcdi->seqno & SEQ_MASK; |
106 | xflags = 0; | |
107 | if (mcdi->mode == MCDI_MODE_EVENTS) | |
108 | xflags |= MCDI_HEADER_XFLAGS_EVREQ; | |
109 | ||
df2cd8af BH |
110 | if (efx->type->mcdi_max_ver == 1) { |
111 | /* MCDI v1 */ | |
d36a08b4 | 112 | EFX_POPULATE_DWORD_7(hdr[0], |
df2cd8af BH |
113 | MCDI_HEADER_RESPONSE, 0, |
114 | MCDI_HEADER_RESYNC, 1, | |
115 | MCDI_HEADER_CODE, cmd, | |
116 | MCDI_HEADER_DATALEN, inlen, | |
117 | MCDI_HEADER_SEQ, seqno, | |
d36a08b4 DP |
118 | MCDI_HEADER_XFLAGS, xflags, |
119 | MCDI_HEADER_NOT_EPOCH, !mcdi->new_epoch); | |
df2cd8af BH |
120 | hdr_len = 4; |
121 | } else { | |
122 | /* MCDI v2 */ | |
123 | BUG_ON(inlen > MCDI_CTL_SDU_LEN_MAX_V2); | |
d36a08b4 | 124 | EFX_POPULATE_DWORD_7(hdr[0], |
df2cd8af BH |
125 | MCDI_HEADER_RESPONSE, 0, |
126 | MCDI_HEADER_RESYNC, 1, | |
127 | MCDI_HEADER_CODE, MC_CMD_V2_EXTN, | |
128 | MCDI_HEADER_DATALEN, 0, | |
129 | MCDI_HEADER_SEQ, seqno, | |
d36a08b4 DP |
130 | MCDI_HEADER_XFLAGS, xflags, |
131 | MCDI_HEADER_NOT_EPOCH, !mcdi->new_epoch); | |
df2cd8af BH |
132 | EFX_POPULATE_DWORD_2(hdr[1], |
133 | MC_CMD_V2_EXTN_IN_EXTENDED_CMD, cmd, | |
134 | MC_CMD_V2_EXTN_IN_ACTUAL_LEN, inlen); | |
135 | hdr_len = 8; | |
136 | } | |
afd4aea0 | 137 | |
df2cd8af | 138 | efx->type->mcdi_request(efx, hdr, hdr_len, inbuf, inlen); |
2f4bcdcc BH |
139 | |
140 | mcdi->new_epoch = false; | |
afd4aea0 BH |
141 | } |
142 | ||
5bc283e5 BH |
143 | static int efx_mcdi_errno(unsigned int mcdi_err) |
144 | { | |
145 | switch (mcdi_err) { | |
146 | case 0: | |
147 | return 0; | |
148 | #define TRANSLATE_ERROR(name) \ | |
149 | case MC_CMD_ERR_ ## name: \ | |
150 | return -name; | |
df2cd8af | 151 | TRANSLATE_ERROR(EPERM); |
5bc283e5 BH |
152 | TRANSLATE_ERROR(ENOENT); |
153 | TRANSLATE_ERROR(EINTR); | |
df2cd8af | 154 | TRANSLATE_ERROR(EAGAIN); |
5bc283e5 BH |
155 | TRANSLATE_ERROR(EACCES); |
156 | TRANSLATE_ERROR(EBUSY); | |
157 | TRANSLATE_ERROR(EINVAL); | |
158 | TRANSLATE_ERROR(EDEADLK); | |
159 | TRANSLATE_ERROR(ENOSYS); | |
160 | TRANSLATE_ERROR(ETIME); | |
df2cd8af BH |
161 | TRANSLATE_ERROR(EALREADY); |
162 | TRANSLATE_ERROR(ENOSPC); | |
5bc283e5 | 163 | #undef TRANSLATE_ERROR |
df2cd8af BH |
164 | case MC_CMD_ERR_ALLOC_FAIL: |
165 | return -ENOBUFS; | |
166 | case MC_CMD_ERR_MAC_EXIST: | |
167 | return -EADDRINUSE; | |
5bc283e5 | 168 | default: |
df2cd8af BH |
169 | return -EPROTO; |
170 | } | |
171 | } | |
172 | ||
173 | static void efx_mcdi_read_response_header(struct efx_nic *efx) | |
174 | { | |
175 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
176 | unsigned int respseq, respcmd, error; | |
177 | efx_dword_t hdr; | |
178 | ||
179 | efx->type->mcdi_read_response(efx, &hdr, 0, 4); | |
180 | respseq = EFX_DWORD_FIELD(hdr, MCDI_HEADER_SEQ); | |
181 | respcmd = EFX_DWORD_FIELD(hdr, MCDI_HEADER_CODE); | |
182 | error = EFX_DWORD_FIELD(hdr, MCDI_HEADER_ERROR); | |
183 | ||
184 | if (respcmd != MC_CMD_V2_EXTN) { | |
185 | mcdi->resp_hdr_len = 4; | |
186 | mcdi->resp_data_len = EFX_DWORD_FIELD(hdr, MCDI_HEADER_DATALEN); | |
187 | } else { | |
188 | efx->type->mcdi_read_response(efx, &hdr, 4, 4); | |
189 | mcdi->resp_hdr_len = 8; | |
190 | mcdi->resp_data_len = | |
191 | EFX_DWORD_FIELD(hdr, MC_CMD_V2_EXTN_IN_ACTUAL_LEN); | |
192 | } | |
193 | ||
194 | if (error && mcdi->resp_data_len == 0) { | |
195 | netif_err(efx, hw, efx->net_dev, "MC rebooted\n"); | |
196 | mcdi->resprc = -EIO; | |
197 | } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) { | |
198 | netif_err(efx, hw, efx->net_dev, | |
199 | "MC response mismatch tx seq 0x%x rx seq 0x%x\n", | |
200 | respseq, mcdi->seqno); | |
201 | mcdi->resprc = -EIO; | |
202 | } else if (error) { | |
203 | efx->type->mcdi_read_response(efx, &hdr, mcdi->resp_hdr_len, 4); | |
204 | mcdi->resprc = | |
205 | efx_mcdi_errno(EFX_DWORD_FIELD(hdr, EFX_DWORD_0)); | |
206 | } else { | |
207 | mcdi->resprc = 0; | |
5bc283e5 BH |
208 | } |
209 | } | |
210 | ||
afd4aea0 BH |
211 | static int efx_mcdi_poll(struct efx_nic *efx) |
212 | { | |
213 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
ebf98e79 | 214 | unsigned long time, finish; |
5bc283e5 | 215 | unsigned int spins; |
5bc283e5 | 216 | int rc; |
afd4aea0 BH |
217 | |
218 | /* Check for a reboot atomically with respect to efx_mcdi_copyout() */ | |
5bc283e5 | 219 | rc = efx_mcdi_poll_reboot(efx); |
df2cd8af | 220 | if (rc) { |
369327fa | 221 | spin_lock_bh(&mcdi->iface_lock); |
df2cd8af BH |
222 | mcdi->resprc = rc; |
223 | mcdi->resp_hdr_len = 0; | |
224 | mcdi->resp_data_len = 0; | |
369327fa | 225 | spin_unlock_bh(&mcdi->iface_lock); |
df2cd8af BH |
226 | return 0; |
227 | } | |
afd4aea0 BH |
228 | |
229 | /* Poll for completion. Poll quickly (once a us) for the 1st jiffy, | |
230 | * because generally mcdi responses are fast. After that, back off | |
231 | * and poll once a jiffy (approximately) | |
232 | */ | |
233 | spins = TICK_USEC; | |
ebf98e79 | 234 | finish = jiffies + MCDI_RPC_TIMEOUT; |
afd4aea0 BH |
235 | |
236 | while (1) { | |
237 | if (spins != 0) { | |
238 | --spins; | |
239 | udelay(1); | |
55029c1d BH |
240 | } else { |
241 | schedule_timeout_uninterruptible(1); | |
242 | } | |
afd4aea0 | 243 | |
ebf98e79 | 244 | time = jiffies; |
afd4aea0 | 245 | |
86c432ca | 246 | rmb(); |
f3ad5003 | 247 | if (efx->type->mcdi_poll_response(efx)) |
afd4aea0 BH |
248 | break; |
249 | ||
ebf98e79 | 250 | if (time_after(time, finish)) |
afd4aea0 BH |
251 | return -ETIMEDOUT; |
252 | } | |
253 | ||
369327fa | 254 | spin_lock_bh(&mcdi->iface_lock); |
df2cd8af | 255 | efx_mcdi_read_response_header(efx); |
369327fa | 256 | spin_unlock_bh(&mcdi->iface_lock); |
afd4aea0 BH |
257 | |
258 | /* Return rc=0 like wait_event_timeout() */ | |
259 | return 0; | |
260 | } | |
261 | ||
876be083 BH |
262 | /* Test and clear MC-rebooted flag for this port/function; reset |
263 | * software state as necessary. | |
264 | */ | |
afd4aea0 BH |
265 | int efx_mcdi_poll_reboot(struct efx_nic *efx) |
266 | { | |
f3ad5003 BH |
267 | if (!efx->mcdi) |
268 | return 0; | |
afd4aea0 | 269 | |
cd0ecc9a | 270 | return efx->type->mcdi_poll_reboot(efx); |
afd4aea0 BH |
271 | } |
272 | ||
cade715f BH |
273 | static bool efx_mcdi_acquire_async(struct efx_mcdi_iface *mcdi) |
274 | { | |
275 | return cmpxchg(&mcdi->state, | |
276 | MCDI_STATE_QUIESCENT, MCDI_STATE_RUNNING_ASYNC) == | |
277 | MCDI_STATE_QUIESCENT; | |
278 | } | |
279 | ||
280 | static void efx_mcdi_acquire_sync(struct efx_mcdi_iface *mcdi) | |
afd4aea0 BH |
281 | { |
282 | /* Wait until the interface becomes QUIESCENT and we win the race | |
cade715f BH |
283 | * to mark it RUNNING_SYNC. |
284 | */ | |
afd4aea0 | 285 | wait_event(mcdi->wq, |
251111d9 | 286 | cmpxchg(&mcdi->state, |
cade715f | 287 | MCDI_STATE_QUIESCENT, MCDI_STATE_RUNNING_SYNC) == |
251111d9 | 288 | MCDI_STATE_QUIESCENT); |
afd4aea0 BH |
289 | } |
290 | ||
291 | static int efx_mcdi_await_completion(struct efx_nic *efx) | |
292 | { | |
293 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
294 | ||
251111d9 BH |
295 | if (wait_event_timeout(mcdi->wq, mcdi->state == MCDI_STATE_COMPLETED, |
296 | MCDI_RPC_TIMEOUT) == 0) | |
afd4aea0 BH |
297 | return -ETIMEDOUT; |
298 | ||
299 | /* Check if efx_mcdi_set_mode() switched us back to polled completions. | |
300 | * In which case, poll for completions directly. If efx_mcdi_ev_cpl() | |
301 | * completed the request first, then we'll just end up completing the | |
302 | * request again, which is safe. | |
303 | * | |
304 | * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which | |
305 | * wait_event_timeout() implicitly provides. | |
306 | */ | |
307 | if (mcdi->mode == MCDI_MODE_POLL) | |
308 | return efx_mcdi_poll(efx); | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
cade715f BH |
313 | /* If the interface is RUNNING_SYNC, switch to COMPLETED and wake the |
314 | * requester. Return whether this was done. Does not take any locks. | |
315 | */ | |
316 | static bool efx_mcdi_complete_sync(struct efx_mcdi_iface *mcdi) | |
afd4aea0 | 317 | { |
cade715f BH |
318 | if (cmpxchg(&mcdi->state, |
319 | MCDI_STATE_RUNNING_SYNC, MCDI_STATE_COMPLETED) == | |
320 | MCDI_STATE_RUNNING_SYNC) { | |
afd4aea0 BH |
321 | wake_up(&mcdi->wq); |
322 | return true; | |
323 | } | |
324 | ||
325 | return false; | |
326 | } | |
327 | ||
328 | static void efx_mcdi_release(struct efx_mcdi_iface *mcdi) | |
329 | { | |
cade715f BH |
330 | if (mcdi->mode == MCDI_MODE_EVENTS) { |
331 | struct efx_mcdi_async_param *async; | |
332 | struct efx_nic *efx = mcdi->efx; | |
333 | ||
334 | /* Process the asynchronous request queue */ | |
335 | spin_lock_bh(&mcdi->async_lock); | |
336 | async = list_first_entry_or_null( | |
337 | &mcdi->async_list, struct efx_mcdi_async_param, list); | |
338 | if (async) { | |
339 | mcdi->state = MCDI_STATE_RUNNING_ASYNC; | |
340 | efx_mcdi_send_request(efx, async->cmd, | |
341 | (const efx_dword_t *)(async + 1), | |
342 | async->inlen); | |
343 | mod_timer(&mcdi->async_timer, | |
344 | jiffies + MCDI_RPC_TIMEOUT); | |
345 | } | |
346 | spin_unlock_bh(&mcdi->async_lock); | |
347 | ||
348 | if (async) | |
349 | return; | |
350 | } | |
351 | ||
251111d9 | 352 | mcdi->state = MCDI_STATE_QUIESCENT; |
afd4aea0 BH |
353 | wake_up(&mcdi->wq); |
354 | } | |
355 | ||
cade715f BH |
356 | /* If the interface is RUNNING_ASYNC, switch to COMPLETED, call the |
357 | * asynchronous completion function, and release the interface. | |
358 | * Return whether this was done. Must be called in bh-disabled | |
359 | * context. Will take iface_lock and async_lock. | |
360 | */ | |
361 | static bool efx_mcdi_complete_async(struct efx_mcdi_iface *mcdi, bool timeout) | |
362 | { | |
363 | struct efx_nic *efx = mcdi->efx; | |
364 | struct efx_mcdi_async_param *async; | |
365 | size_t hdr_len, data_len; | |
366 | efx_dword_t *outbuf; | |
367 | int rc; | |
368 | ||
369 | if (cmpxchg(&mcdi->state, | |
370 | MCDI_STATE_RUNNING_ASYNC, MCDI_STATE_COMPLETED) != | |
371 | MCDI_STATE_RUNNING_ASYNC) | |
372 | return false; | |
373 | ||
374 | spin_lock(&mcdi->iface_lock); | |
375 | if (timeout) { | |
376 | /* Ensure that if the completion event arrives later, | |
377 | * the seqno check in efx_mcdi_ev_cpl() will fail | |
378 | */ | |
379 | ++mcdi->seqno; | |
380 | ++mcdi->credits; | |
381 | rc = -ETIMEDOUT; | |
382 | hdr_len = 0; | |
383 | data_len = 0; | |
384 | } else { | |
385 | rc = mcdi->resprc; | |
386 | hdr_len = mcdi->resp_hdr_len; | |
387 | data_len = mcdi->resp_data_len; | |
388 | } | |
389 | spin_unlock(&mcdi->iface_lock); | |
390 | ||
391 | /* Stop the timer. In case the timer function is running, we | |
392 | * must wait for it to return so that there is no possibility | |
393 | * of it aborting the next request. | |
394 | */ | |
395 | if (!timeout) | |
396 | del_timer_sync(&mcdi->async_timer); | |
397 | ||
398 | spin_lock(&mcdi->async_lock); | |
399 | async = list_first_entry(&mcdi->async_list, | |
400 | struct efx_mcdi_async_param, list); | |
401 | list_del(&async->list); | |
402 | spin_unlock(&mcdi->async_lock); | |
403 | ||
404 | outbuf = (efx_dword_t *)(async + 1); | |
405 | efx->type->mcdi_read_response(efx, outbuf, hdr_len, | |
406 | min(async->outlen, data_len)); | |
407 | async->complete(efx, async->cookie, rc, outbuf, data_len); | |
408 | kfree(async); | |
409 | ||
410 | efx_mcdi_release(mcdi); | |
411 | ||
412 | return true; | |
413 | } | |
414 | ||
afd4aea0 | 415 | static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno, |
5bc283e5 | 416 | unsigned int datalen, unsigned int mcdi_err) |
afd4aea0 BH |
417 | { |
418 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
419 | bool wake = false; | |
420 | ||
421 | spin_lock(&mcdi->iface_lock); | |
422 | ||
423 | if ((seqno ^ mcdi->seqno) & SEQ_MASK) { | |
424 | if (mcdi->credits) | |
425 | /* The request has been cancelled */ | |
426 | --mcdi->credits; | |
427 | else | |
62776d03 BH |
428 | netif_err(efx, hw, efx->net_dev, |
429 | "MC response mismatch tx seq 0x%x rx " | |
430 | "seq 0x%x\n", seqno, mcdi->seqno); | |
afd4aea0 | 431 | } else { |
df2cd8af BH |
432 | if (efx->type->mcdi_max_ver >= 2) { |
433 | /* MCDI v2 responses don't fit in an event */ | |
434 | efx_mcdi_read_response_header(efx); | |
435 | } else { | |
436 | mcdi->resprc = efx_mcdi_errno(mcdi_err); | |
437 | mcdi->resp_hdr_len = 4; | |
438 | mcdi->resp_data_len = datalen; | |
439 | } | |
afd4aea0 BH |
440 | |
441 | wake = true; | |
442 | } | |
443 | ||
444 | spin_unlock(&mcdi->iface_lock); | |
445 | ||
cade715f BH |
446 | if (wake) { |
447 | if (!efx_mcdi_complete_async(mcdi, false)) | |
448 | (void) efx_mcdi_complete_sync(mcdi); | |
449 | ||
450 | /* If the interface isn't RUNNING_ASYNC or | |
451 | * RUNNING_SYNC then we've received a duplicate | |
452 | * completion after we've already transitioned back to | |
453 | * QUIESCENT. [A subsequent invocation would increment | |
454 | * seqno, so would have failed the seqno check]. | |
455 | */ | |
456 | } | |
457 | } | |
458 | ||
459 | static void efx_mcdi_timeout_async(unsigned long context) | |
460 | { | |
461 | struct efx_mcdi_iface *mcdi = (struct efx_mcdi_iface *)context; | |
462 | ||
463 | efx_mcdi_complete_async(mcdi, true); | |
afd4aea0 BH |
464 | } |
465 | ||
2f4bcdcc BH |
466 | static int |
467 | efx_mcdi_check_supported(struct efx_nic *efx, unsigned int cmd, size_t inlen) | |
468 | { | |
469 | if (efx->type->mcdi_max_ver < 0 || | |
470 | (efx->type->mcdi_max_ver < 2 && | |
471 | cmd > MC_CMD_CMD_SPACE_ESCAPE_7)) | |
472 | return -EINVAL; | |
473 | ||
474 | if (inlen > MCDI_CTL_SDU_LEN_MAX_V2 || | |
475 | (efx->type->mcdi_max_ver < 2 && | |
476 | inlen > MCDI_CTL_SDU_LEN_MAX_V1)) | |
477 | return -EMSGSIZE; | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
afd4aea0 | 482 | int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd, |
9528b921 BH |
483 | const efx_dword_t *inbuf, size_t inlen, |
484 | efx_dword_t *outbuf, size_t outlen, | |
afd4aea0 | 485 | size_t *outlen_actual) |
c3cba721 | 486 | { |
df2cd8af BH |
487 | int rc; |
488 | ||
489 | rc = efx_mcdi_rpc_start(efx, cmd, inbuf, inlen); | |
490 | if (rc) | |
491 | return rc; | |
c3cba721 SH |
492 | return efx_mcdi_rpc_finish(efx, cmd, inlen, |
493 | outbuf, outlen, outlen_actual); | |
494 | } | |
495 | ||
df2cd8af BH |
496 | int efx_mcdi_rpc_start(struct efx_nic *efx, unsigned cmd, |
497 | const efx_dword_t *inbuf, size_t inlen) | |
afd4aea0 BH |
498 | { |
499 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
2f4bcdcc | 500 | int rc; |
c3cba721 | 501 | |
2f4bcdcc BH |
502 | rc = efx_mcdi_check_supported(efx, cmd, inlen); |
503 | if (rc) | |
504 | return rc; | |
df2cd8af | 505 | |
cade715f | 506 | efx_mcdi_acquire_sync(mcdi); |
2f4bcdcc | 507 | efx_mcdi_send_request(efx, cmd, inbuf, inlen); |
df2cd8af | 508 | return 0; |
c3cba721 SH |
509 | } |
510 | ||
cade715f BH |
511 | /** |
512 | * efx_mcdi_rpc_async - Schedule an MCDI command to run asynchronously | |
513 | * @efx: NIC through which to issue the command | |
514 | * @cmd: Command type number | |
515 | * @inbuf: Command parameters | |
516 | * @inlen: Length of command parameters, in bytes | |
517 | * @outlen: Length to allocate for response buffer, in bytes | |
518 | * @complete: Function to be called on completion or cancellation. | |
519 | * @cookie: Arbitrary value to be passed to @complete. | |
520 | * | |
521 | * This function does not sleep and therefore may be called in atomic | |
522 | * context. It will fail if event queues are disabled or if MCDI | |
523 | * event completions have been disabled due to an error. | |
524 | * | |
525 | * If it succeeds, the @complete function will be called exactly once | |
526 | * in atomic context, when one of the following occurs: | |
527 | * (a) the completion event is received (in NAPI context) | |
528 | * (b) event queues are disabled (in the process that disables them) | |
529 | * (c) the request times-out (in timer context) | |
530 | */ | |
531 | int | |
532 | efx_mcdi_rpc_async(struct efx_nic *efx, unsigned int cmd, | |
533 | const efx_dword_t *inbuf, size_t inlen, size_t outlen, | |
534 | efx_mcdi_async_completer *complete, unsigned long cookie) | |
535 | { | |
536 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
537 | struct efx_mcdi_async_param *async; | |
538 | int rc; | |
539 | ||
540 | rc = efx_mcdi_check_supported(efx, cmd, inlen); | |
541 | if (rc) | |
542 | return rc; | |
543 | ||
544 | async = kmalloc(sizeof(*async) + ALIGN(max(inlen, outlen), 4), | |
545 | GFP_ATOMIC); | |
546 | if (!async) | |
547 | return -ENOMEM; | |
548 | ||
549 | async->cmd = cmd; | |
550 | async->inlen = inlen; | |
551 | async->outlen = outlen; | |
552 | async->complete = complete; | |
553 | async->cookie = cookie; | |
554 | memcpy(async + 1, inbuf, inlen); | |
555 | ||
556 | spin_lock_bh(&mcdi->async_lock); | |
557 | ||
558 | if (mcdi->mode == MCDI_MODE_EVENTS) { | |
559 | list_add_tail(&async->list, &mcdi->async_list); | |
560 | ||
561 | /* If this is at the front of the queue, try to start it | |
562 | * immediately | |
563 | */ | |
564 | if (mcdi->async_list.next == &async->list && | |
565 | efx_mcdi_acquire_async(mcdi)) { | |
566 | efx_mcdi_send_request(efx, cmd, inbuf, inlen); | |
567 | mod_timer(&mcdi->async_timer, | |
568 | jiffies + MCDI_RPC_TIMEOUT); | |
569 | } | |
570 | } else { | |
571 | kfree(async); | |
572 | rc = -ENETDOWN; | |
573 | } | |
574 | ||
575 | spin_unlock_bh(&mcdi->async_lock); | |
576 | ||
577 | return rc; | |
578 | } | |
579 | ||
c3cba721 | 580 | int efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen, |
9528b921 BH |
581 | efx_dword_t *outbuf, size_t outlen, |
582 | size_t *outlen_actual) | |
c3cba721 SH |
583 | { |
584 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
585 | int rc; | |
586 | ||
afd4aea0 BH |
587 | if (mcdi->mode == MCDI_MODE_POLL) |
588 | rc = efx_mcdi_poll(efx); | |
589 | else | |
590 | rc = efx_mcdi_await_completion(efx); | |
591 | ||
592 | if (rc != 0) { | |
593 | /* Close the race with efx_mcdi_ev_cpl() executing just too late | |
594 | * and completing a request we've just cancelled, by ensuring | |
595 | * that the seqno check therein fails. | |
596 | */ | |
597 | spin_lock_bh(&mcdi->iface_lock); | |
598 | ++mcdi->seqno; | |
599 | ++mcdi->credits; | |
600 | spin_unlock_bh(&mcdi->iface_lock); | |
601 | ||
62776d03 BH |
602 | netif_err(efx, hw, efx->net_dev, |
603 | "MC command 0x%x inlen %d mode %d timed out\n", | |
604 | cmd, (int)inlen, mcdi->mode); | |
afd4aea0 | 605 | } else { |
369327fa | 606 | size_t hdr_len, data_len; |
afd4aea0 BH |
607 | |
608 | /* At the very least we need a memory barrier here to ensure | |
609 | * we pick up changes from efx_mcdi_ev_cpl(). Protect against | |
610 | * a spurious efx_mcdi_ev_cpl() running concurrently by | |
611 | * acquiring the iface_lock. */ | |
612 | spin_lock_bh(&mcdi->iface_lock); | |
5bc283e5 | 613 | rc = mcdi->resprc; |
369327fa BH |
614 | hdr_len = mcdi->resp_hdr_len; |
615 | data_len = mcdi->resp_data_len; | |
afd4aea0 BH |
616 | spin_unlock_bh(&mcdi->iface_lock); |
617 | ||
5bc283e5 BH |
618 | BUG_ON(rc > 0); |
619 | ||
afd4aea0 | 620 | if (rc == 0) { |
369327fa BH |
621 | efx->type->mcdi_read_response(efx, outbuf, hdr_len, |
622 | min(outlen, data_len)); | |
afd4aea0 | 623 | if (outlen_actual != NULL) |
369327fa | 624 | *outlen_actual = data_len; |
afd4aea0 BH |
625 | } else if (cmd == MC_CMD_REBOOT && rc == -EIO) |
626 | ; /* Don't reset if MC_CMD_REBOOT returns EIO */ | |
627 | else if (rc == -EIO || rc == -EINTR) { | |
62776d03 BH |
628 | netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n", |
629 | -rc); | |
afd4aea0 BH |
630 | efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE); |
631 | } else | |
f18ca364 | 632 | netif_dbg(efx, hw, efx->net_dev, |
62776d03 BH |
633 | "MC command 0x%x inlen %d failed rc=%d\n", |
634 | cmd, (int)inlen, -rc); | |
3f713bf4 BH |
635 | |
636 | if (rc == -EIO || rc == -EINTR) { | |
637 | msleep(MCDI_STATUS_SLEEP_MS); | |
638 | efx_mcdi_poll_reboot(efx); | |
d36a08b4 | 639 | mcdi->new_epoch = true; |
3f713bf4 | 640 | } |
afd4aea0 BH |
641 | } |
642 | ||
643 | efx_mcdi_release(mcdi); | |
644 | return rc; | |
645 | } | |
646 | ||
cade715f BH |
647 | /* Switch to polled MCDI completions. This can be called in various |
648 | * error conditions with various locks held, so it must be lockless. | |
649 | * Caller is responsible for flushing asynchronous requests later. | |
650 | */ | |
afd4aea0 BH |
651 | void efx_mcdi_mode_poll(struct efx_nic *efx) |
652 | { | |
653 | struct efx_mcdi_iface *mcdi; | |
654 | ||
f3ad5003 | 655 | if (!efx->mcdi) |
afd4aea0 BH |
656 | return; |
657 | ||
658 | mcdi = efx_mcdi(efx); | |
659 | if (mcdi->mode == MCDI_MODE_POLL) | |
660 | return; | |
661 | ||
662 | /* We can switch from event completion to polled completion, because | |
663 | * mcdi requests are always completed in shared memory. We do this by | |
664 | * switching the mode to POLL'd then completing the request. | |
665 | * efx_mcdi_await_completion() will then call efx_mcdi_poll(). | |
666 | * | |
667 | * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(), | |
cade715f | 668 | * which efx_mcdi_complete_sync() provides for us. |
afd4aea0 BH |
669 | */ |
670 | mcdi->mode = MCDI_MODE_POLL; | |
671 | ||
cade715f BH |
672 | efx_mcdi_complete_sync(mcdi); |
673 | } | |
674 | ||
675 | /* Flush any running or queued asynchronous requests, after event processing | |
676 | * is stopped | |
677 | */ | |
678 | void efx_mcdi_flush_async(struct efx_nic *efx) | |
679 | { | |
680 | struct efx_mcdi_async_param *async, *next; | |
681 | struct efx_mcdi_iface *mcdi; | |
682 | ||
683 | if (!efx->mcdi) | |
684 | return; | |
685 | ||
686 | mcdi = efx_mcdi(efx); | |
687 | ||
688 | /* We must be in polling mode so no more requests can be queued */ | |
689 | BUG_ON(mcdi->mode != MCDI_MODE_POLL); | |
690 | ||
691 | del_timer_sync(&mcdi->async_timer); | |
692 | ||
693 | /* If a request is still running, make sure we give the MC | |
694 | * time to complete it so that the response won't overwrite our | |
695 | * next request. | |
696 | */ | |
697 | if (mcdi->state == MCDI_STATE_RUNNING_ASYNC) { | |
698 | efx_mcdi_poll(efx); | |
699 | mcdi->state = MCDI_STATE_QUIESCENT; | |
700 | } | |
701 | ||
702 | /* Nothing else will access the async list now, so it is safe | |
703 | * to walk it without holding async_lock. If we hold it while | |
704 | * calling a completer then lockdep may warn that we have | |
705 | * acquired locks in the wrong order. | |
706 | */ | |
707 | list_for_each_entry_safe(async, next, &mcdi->async_list, list) { | |
708 | async->complete(efx, async->cookie, -ENETDOWN, NULL, 0); | |
709 | list_del(&async->list); | |
710 | kfree(async); | |
711 | } | |
afd4aea0 BH |
712 | } |
713 | ||
714 | void efx_mcdi_mode_event(struct efx_nic *efx) | |
715 | { | |
716 | struct efx_mcdi_iface *mcdi; | |
717 | ||
f3ad5003 | 718 | if (!efx->mcdi) |
afd4aea0 BH |
719 | return; |
720 | ||
721 | mcdi = efx_mcdi(efx); | |
722 | ||
723 | if (mcdi->mode == MCDI_MODE_EVENTS) | |
724 | return; | |
725 | ||
726 | /* We can't switch from polled to event completion in the middle of a | |
727 | * request, because the completion method is specified in the request. | |
728 | * So acquire the interface to serialise the requestors. We don't need | |
729 | * to acquire the iface_lock to change the mode here, but we do need a | |
730 | * write memory barrier ensure that efx_mcdi_rpc() sees it, which | |
731 | * efx_mcdi_acquire() provides. | |
732 | */ | |
cade715f | 733 | efx_mcdi_acquire_sync(mcdi); |
afd4aea0 BH |
734 | mcdi->mode = MCDI_MODE_EVENTS; |
735 | efx_mcdi_release(mcdi); | |
736 | } | |
737 | ||
738 | static void efx_mcdi_ev_death(struct efx_nic *efx, int rc) | |
739 | { | |
740 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
741 | ||
742 | /* If there is an outstanding MCDI request, it has been terminated | |
743 | * either by a BADASSERT or REBOOT event. If the mcdi interface is | |
744 | * in polled mode, then do nothing because the MC reboot handler will | |
745 | * set the header correctly. However, if the mcdi interface is waiting | |
746 | * for a CMDDONE event it won't receive it [and since all MCDI events | |
747 | * are sent to the same queue, we can't be racing with | |
748 | * efx_mcdi_ev_cpl()] | |
749 | * | |
cade715f BH |
750 | * If there is an outstanding asynchronous request, we can't |
751 | * complete it now (efx_mcdi_complete() would deadlock). The | |
752 | * reset process will take care of this. | |
753 | * | |
754 | * There's a race here with efx_mcdi_send_request(), because | |
755 | * we might receive a REBOOT event *before* the request has | |
756 | * been copied out. In polled mode (during startup) this is | |
757 | * irrelevant, because efx_mcdi_complete_sync() is ignored. In | |
758 | * event mode, this condition is just an edge-case of | |
759 | * receiving a REBOOT event after posting the MCDI | |
760 | * request. Did the mc reboot before or after the copyout? The | |
761 | * best we can do always is just return failure. | |
afd4aea0 BH |
762 | */ |
763 | spin_lock(&mcdi->iface_lock); | |
cade715f | 764 | if (efx_mcdi_complete_sync(mcdi)) { |
afd4aea0 BH |
765 | if (mcdi->mode == MCDI_MODE_EVENTS) { |
766 | mcdi->resprc = rc; | |
df2cd8af BH |
767 | mcdi->resp_hdr_len = 0; |
768 | mcdi->resp_data_len = 0; | |
18e3ee2c | 769 | ++mcdi->credits; |
afd4aea0 | 770 | } |
3f713bf4 BH |
771 | } else { |
772 | int count; | |
773 | ||
afd4aea0 BH |
774 | /* Nobody was waiting for an MCDI request, so trigger a reset */ |
775 | efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE); | |
776 | ||
3f713bf4 BH |
777 | /* Consume the status word since efx_mcdi_rpc_finish() won't */ |
778 | for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) { | |
779 | if (efx_mcdi_poll_reboot(efx)) | |
780 | break; | |
781 | udelay(MCDI_STATUS_DELAY_US); | |
782 | } | |
d36a08b4 | 783 | mcdi->new_epoch = true; |
3f713bf4 BH |
784 | } |
785 | ||
afd4aea0 BH |
786 | spin_unlock(&mcdi->iface_lock); |
787 | } | |
788 | ||
afd4aea0 BH |
789 | /* Called from falcon_process_eventq for MCDI events */ |
790 | void efx_mcdi_process_event(struct efx_channel *channel, | |
791 | efx_qword_t *event) | |
792 | { | |
793 | struct efx_nic *efx = channel->efx; | |
794 | int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE); | |
795 | u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA); | |
796 | ||
797 | switch (code) { | |
798 | case MCDI_EVENT_CODE_BADSSERT: | |
62776d03 BH |
799 | netif_err(efx, hw, efx->net_dev, |
800 | "MC watchdog or assertion failure at 0x%x\n", data); | |
5bc283e5 | 801 | efx_mcdi_ev_death(efx, -EINTR); |
afd4aea0 BH |
802 | break; |
803 | ||
804 | case MCDI_EVENT_CODE_PMNOTICE: | |
62776d03 | 805 | netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n"); |
afd4aea0 BH |
806 | break; |
807 | ||
808 | case MCDI_EVENT_CODE_CMDDONE: | |
809 | efx_mcdi_ev_cpl(efx, | |
810 | MCDI_EVENT_FIELD(*event, CMDDONE_SEQ), | |
811 | MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN), | |
812 | MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO)); | |
813 | break; | |
814 | ||
815 | case MCDI_EVENT_CODE_LINKCHANGE: | |
816 | efx_mcdi_process_link_change(efx, event); | |
817 | break; | |
818 | case MCDI_EVENT_CODE_SENSOREVT: | |
819 | efx_mcdi_sensor_event(efx, event); | |
820 | break; | |
821 | case MCDI_EVENT_CODE_SCHEDERR: | |
62776d03 BH |
822 | netif_info(efx, hw, efx->net_dev, |
823 | "MC Scheduler error address=0x%x\n", data); | |
afd4aea0 BH |
824 | break; |
825 | case MCDI_EVENT_CODE_REBOOT: | |
62776d03 | 826 | netif_info(efx, hw, efx->net_dev, "MC Reboot\n"); |
5bc283e5 | 827 | efx_mcdi_ev_death(efx, -EIO); |
afd4aea0 BH |
828 | break; |
829 | case MCDI_EVENT_CODE_MAC_STATS_DMA: | |
830 | /* MAC stats are gather lazily. We can ignore this. */ | |
831 | break; | |
cd2d5b52 BH |
832 | case MCDI_EVENT_CODE_FLR: |
833 | efx_sriov_flr(efx, MCDI_EVENT_FIELD(*event, FLR_VF)); | |
834 | break; | |
7c236c43 SH |
835 | case MCDI_EVENT_CODE_PTP_RX: |
836 | case MCDI_EVENT_CODE_PTP_FAULT: | |
837 | case MCDI_EVENT_CODE_PTP_PPS: | |
838 | efx_ptp_event(efx, event); | |
839 | break; | |
afd4aea0 | 840 | |
3de82b91 AR |
841 | case MCDI_EVENT_CODE_TX_ERR: |
842 | case MCDI_EVENT_CODE_RX_ERR: | |
843 | netif_err(efx, hw, efx->net_dev, | |
844 | "%s DMA error (event: "EFX_QWORD_FMT")\n", | |
845 | code == MCDI_EVENT_CODE_TX_ERR ? "TX" : "RX", | |
846 | EFX_QWORD_VAL(*event)); | |
847 | efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR); | |
848 | break; | |
afd4aea0 | 849 | default: |
62776d03 BH |
850 | netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n", |
851 | code); | |
afd4aea0 BH |
852 | } |
853 | } | |
854 | ||
855 | /************************************************************************** | |
856 | * | |
857 | * Specific request functions | |
858 | * | |
859 | ************************************************************************** | |
860 | */ | |
861 | ||
e5f0fd27 | 862 | void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len) |
afd4aea0 | 863 | { |
59cfc479 | 864 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_VERSION_OUT_LEN); |
afd4aea0 BH |
865 | size_t outlength; |
866 | const __le16 *ver_words; | |
867 | int rc; | |
868 | ||
869 | BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0); | |
870 | ||
871 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0, | |
872 | outbuf, sizeof(outbuf), &outlength); | |
873 | if (rc) | |
874 | goto fail; | |
875 | ||
05a9320f | 876 | if (outlength < MC_CMD_GET_VERSION_OUT_LEN) { |
00bbb4a5 | 877 | rc = -EIO; |
afd4aea0 BH |
878 | goto fail; |
879 | } | |
880 | ||
881 | ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION); | |
e5f0fd27 BH |
882 | snprintf(buf, len, "%u.%u.%u.%u", |
883 | le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]), | |
884 | le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3])); | |
885 | return; | |
afd4aea0 BH |
886 | |
887 | fail: | |
62776d03 | 888 | netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
e5f0fd27 | 889 | buf[0] = 0; |
afd4aea0 BH |
890 | } |
891 | ||
892 | int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating, | |
893 | bool *was_attached) | |
894 | { | |
59cfc479 BH |
895 | MCDI_DECLARE_BUF(inbuf, MC_CMD_DRV_ATTACH_IN_LEN); |
896 | MCDI_DECLARE_BUF(outbuf, MC_CMD_DRV_ATTACH_OUT_LEN); | |
afd4aea0 BH |
897 | size_t outlen; |
898 | int rc; | |
899 | ||
900 | MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE, | |
901 | driver_operating ? 1 : 0); | |
902 | MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1); | |
f2b0befd | 903 | MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_FIRMWARE_ID, MC_CMD_FW_LOW_LATENCY); |
afd4aea0 BH |
904 | |
905 | rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf), | |
906 | outbuf, sizeof(outbuf), &outlen); | |
907 | if (rc) | |
908 | goto fail; | |
00bbb4a5 BH |
909 | if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) { |
910 | rc = -EIO; | |
afd4aea0 | 911 | goto fail; |
00bbb4a5 | 912 | } |
afd4aea0 BH |
913 | |
914 | if (was_attached != NULL) | |
915 | *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE); | |
916 | return 0; | |
917 | ||
918 | fail: | |
62776d03 | 919 | netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
920 | return rc; |
921 | } | |
922 | ||
923 | int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address, | |
6aa9c7f6 | 924 | u16 *fw_subtype_list, u32 *capabilities) |
afd4aea0 | 925 | { |
59cfc479 | 926 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_BOARD_CFG_OUT_LENMAX); |
c5bb0e98 | 927 | size_t outlen, i; |
afd4aea0 | 928 | int port_num = efx_port_num(efx); |
afd4aea0 BH |
929 | int rc; |
930 | ||
931 | BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0); | |
932 | ||
933 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0, | |
934 | outbuf, sizeof(outbuf), &outlen); | |
935 | if (rc) | |
936 | goto fail; | |
937 | ||
05a9320f | 938 | if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) { |
00bbb4a5 | 939 | rc = -EIO; |
afd4aea0 BH |
940 | goto fail; |
941 | } | |
942 | ||
afd4aea0 | 943 | if (mac_address) |
c5bb0e98 BH |
944 | memcpy(mac_address, |
945 | port_num ? | |
946 | MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1) : | |
947 | MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0), | |
948 | ETH_ALEN); | |
bfeed902 | 949 | if (fw_subtype_list) { |
bfeed902 | 950 | for (i = 0; |
c5bb0e98 BH |
951 | i < MCDI_VAR_ARRAY_LEN(outlen, |
952 | GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST); | |
953 | i++) | |
954 | fw_subtype_list[i] = MCDI_ARRAY_WORD( | |
955 | outbuf, GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST, i); | |
956 | for (; i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM; i++) | |
957 | fw_subtype_list[i] = 0; | |
bfeed902 | 958 | } |
6aa9c7f6 MS |
959 | if (capabilities) { |
960 | if (port_num) | |
961 | *capabilities = MCDI_DWORD(outbuf, | |
962 | GET_BOARD_CFG_OUT_CAPABILITIES_PORT1); | |
963 | else | |
964 | *capabilities = MCDI_DWORD(outbuf, | |
965 | GET_BOARD_CFG_OUT_CAPABILITIES_PORT0); | |
966 | } | |
afd4aea0 BH |
967 | |
968 | return 0; | |
969 | ||
970 | fail: | |
62776d03 BH |
971 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n", |
972 | __func__, rc, (int)outlen); | |
afd4aea0 BH |
973 | |
974 | return rc; | |
975 | } | |
976 | ||
977 | int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq) | |
978 | { | |
59cfc479 | 979 | MCDI_DECLARE_BUF(inbuf, MC_CMD_LOG_CTRL_IN_LEN); |
afd4aea0 BH |
980 | u32 dest = 0; |
981 | int rc; | |
982 | ||
983 | if (uart) | |
984 | dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART; | |
985 | if (evq) | |
986 | dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ; | |
987 | ||
988 | MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest); | |
989 | MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq); | |
990 | ||
991 | BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0); | |
992 | ||
993 | rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf), | |
994 | NULL, 0, NULL); | |
995 | if (rc) | |
996 | goto fail; | |
997 | ||
998 | return 0; | |
999 | ||
1000 | fail: | |
62776d03 | 1001 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1002 | return rc; |
1003 | } | |
1004 | ||
1005 | int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out) | |
1006 | { | |
59cfc479 | 1007 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TYPES_OUT_LEN); |
afd4aea0 BH |
1008 | size_t outlen; |
1009 | int rc; | |
1010 | ||
1011 | BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0); | |
1012 | ||
1013 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0, | |
1014 | outbuf, sizeof(outbuf), &outlen); | |
1015 | if (rc) | |
1016 | goto fail; | |
00bbb4a5 BH |
1017 | if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) { |
1018 | rc = -EIO; | |
afd4aea0 | 1019 | goto fail; |
00bbb4a5 | 1020 | } |
afd4aea0 BH |
1021 | |
1022 | *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES); | |
1023 | return 0; | |
1024 | ||
1025 | fail: | |
62776d03 BH |
1026 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", |
1027 | __func__, rc); | |
afd4aea0 BH |
1028 | return rc; |
1029 | } | |
1030 | ||
1031 | int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type, | |
1032 | size_t *size_out, size_t *erase_size_out, | |
1033 | bool *protected_out) | |
1034 | { | |
59cfc479 BH |
1035 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_INFO_IN_LEN); |
1036 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_INFO_OUT_LEN); | |
afd4aea0 BH |
1037 | size_t outlen; |
1038 | int rc; | |
1039 | ||
1040 | MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type); | |
1041 | ||
1042 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf), | |
1043 | outbuf, sizeof(outbuf), &outlen); | |
1044 | if (rc) | |
1045 | goto fail; | |
00bbb4a5 BH |
1046 | if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) { |
1047 | rc = -EIO; | |
afd4aea0 | 1048 | goto fail; |
00bbb4a5 | 1049 | } |
afd4aea0 BH |
1050 | |
1051 | *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE); | |
1052 | *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE); | |
1053 | *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) & | |
05a9320f | 1054 | (1 << MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN)); |
afd4aea0 BH |
1055 | return 0; |
1056 | ||
1057 | fail: | |
62776d03 | 1058 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1059 | return rc; |
1060 | } | |
1061 | ||
2e803407 BH |
1062 | static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type) |
1063 | { | |
59cfc479 BH |
1064 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_TEST_IN_LEN); |
1065 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TEST_OUT_LEN); | |
2e803407 BH |
1066 | int rc; |
1067 | ||
1068 | MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type); | |
1069 | ||
1070 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf), | |
1071 | outbuf, sizeof(outbuf), NULL); | |
1072 | if (rc) | |
1073 | return rc; | |
1074 | ||
1075 | switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) { | |
1076 | case MC_CMD_NVRAM_TEST_PASS: | |
1077 | case MC_CMD_NVRAM_TEST_NOTSUPP: | |
1078 | return 0; | |
1079 | default: | |
1080 | return -EIO; | |
1081 | } | |
1082 | } | |
1083 | ||
1084 | int efx_mcdi_nvram_test_all(struct efx_nic *efx) | |
1085 | { | |
1086 | u32 nvram_types; | |
1087 | unsigned int type; | |
1088 | int rc; | |
1089 | ||
1090 | rc = efx_mcdi_nvram_types(efx, &nvram_types); | |
1091 | if (rc) | |
b548a988 | 1092 | goto fail1; |
2e803407 BH |
1093 | |
1094 | type = 0; | |
1095 | while (nvram_types != 0) { | |
1096 | if (nvram_types & 1) { | |
1097 | rc = efx_mcdi_nvram_test(efx, type); | |
1098 | if (rc) | |
b548a988 | 1099 | goto fail2; |
2e803407 BH |
1100 | } |
1101 | type++; | |
1102 | nvram_types >>= 1; | |
1103 | } | |
1104 | ||
1105 | return 0; | |
b548a988 BH |
1106 | |
1107 | fail2: | |
62776d03 BH |
1108 | netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n", |
1109 | __func__, type); | |
b548a988 | 1110 | fail1: |
62776d03 | 1111 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
b548a988 | 1112 | return rc; |
2e803407 BH |
1113 | } |
1114 | ||
8b2103ad | 1115 | static int efx_mcdi_read_assertion(struct efx_nic *efx) |
afd4aea0 | 1116 | { |
59cfc479 BH |
1117 | MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_ASSERTS_IN_LEN); |
1118 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_ASSERTS_OUT_LEN); | |
c5bb0e98 | 1119 | unsigned int flags, index; |
afd4aea0 BH |
1120 | const char *reason; |
1121 | size_t outlen; | |
1122 | int retry; | |
1123 | int rc; | |
1124 | ||
8b2103ad SH |
1125 | /* Attempt to read any stored assertion state before we reboot |
1126 | * the mcfw out of the assertion handler. Retry twice, once | |
afd4aea0 BH |
1127 | * because a boot-time assertion might cause this command to fail |
1128 | * with EINTR. And once again because GET_ASSERTS can race with | |
1129 | * MC_CMD_REBOOT running on the other port. */ | |
1130 | retry = 2; | |
1131 | do { | |
8b2103ad | 1132 | MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1); |
afd4aea0 | 1133 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS, |
8b2103ad SH |
1134 | inbuf, MC_CMD_GET_ASSERTS_IN_LEN, |
1135 | outbuf, sizeof(outbuf), &outlen); | |
afd4aea0 BH |
1136 | } while ((rc == -EINTR || rc == -EIO) && retry-- > 0); |
1137 | ||
1138 | if (rc) | |
1139 | return rc; | |
1140 | if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN) | |
00bbb4a5 | 1141 | return -EIO; |
afd4aea0 | 1142 | |
8b2103ad SH |
1143 | /* Print out any recorded assertion state */ |
1144 | flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS); | |
afd4aea0 BH |
1145 | if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS) |
1146 | return 0; | |
1147 | ||
afd4aea0 BH |
1148 | reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL) |
1149 | ? "system-level assertion" | |
1150 | : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL) | |
1151 | ? "thread-level assertion" | |
1152 | : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED) | |
1153 | ? "watchdog reset" | |
1154 | : "unknown assertion"; | |
62776d03 BH |
1155 | netif_err(efx, hw, efx->net_dev, |
1156 | "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason, | |
1157 | MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS), | |
1158 | MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS)); | |
afd4aea0 BH |
1159 | |
1160 | /* Print out the registers */ | |
c5bb0e98 BH |
1161 | for (index = 0; |
1162 | index < MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM; | |
1163 | index++) | |
1164 | netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", | |
1165 | 1 + index, | |
1166 | MCDI_ARRAY_DWORD(outbuf, GET_ASSERTS_OUT_GP_REGS_OFFS, | |
1167 | index)); | |
afd4aea0 BH |
1168 | |
1169 | return 0; | |
1170 | } | |
1171 | ||
8b2103ad SH |
1172 | static void efx_mcdi_exit_assertion(struct efx_nic *efx) |
1173 | { | |
59cfc479 | 1174 | MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN); |
8b2103ad | 1175 | |
0f1e54ae BH |
1176 | /* If the MC is running debug firmware, it might now be |
1177 | * waiting for a debugger to attach, but we just want it to | |
1178 | * reboot. We set a flag that makes the command a no-op if it | |
1179 | * has already done so. We don't know what return code to | |
1180 | * expect (0 or -EIO), so ignore it. | |
1181 | */ | |
8b2103ad SH |
1182 | BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0); |
1183 | MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, | |
1184 | MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION); | |
0f1e54ae BH |
1185 | (void) efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN, |
1186 | NULL, 0, NULL); | |
8b2103ad SH |
1187 | } |
1188 | ||
1189 | int efx_mcdi_handle_assertion(struct efx_nic *efx) | |
1190 | { | |
1191 | int rc; | |
1192 | ||
1193 | rc = efx_mcdi_read_assertion(efx); | |
1194 | if (rc) | |
1195 | return rc; | |
1196 | ||
1197 | efx_mcdi_exit_assertion(efx); | |
1198 | ||
1199 | return 0; | |
1200 | } | |
1201 | ||
afd4aea0 BH |
1202 | void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1203 | { | |
59cfc479 | 1204 | MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_ID_LED_IN_LEN); |
afd4aea0 BH |
1205 | int rc; |
1206 | ||
1207 | BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF); | |
1208 | BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON); | |
1209 | BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT); | |
1210 | ||
1211 | BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0); | |
1212 | ||
1213 | MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode); | |
1214 | ||
1215 | rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf), | |
1216 | NULL, 0, NULL); | |
1217 | if (rc) | |
62776d03 BH |
1218 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", |
1219 | __func__, rc); | |
afd4aea0 BH |
1220 | } |
1221 | ||
6bff861d | 1222 | static int efx_mcdi_reset_port(struct efx_nic *efx) |
afd4aea0 | 1223 | { |
05a9320f | 1224 | int rc = efx_mcdi_rpc(efx, MC_CMD_ENTITY_RESET, NULL, 0, NULL, 0, NULL); |
afd4aea0 | 1225 | if (rc) |
62776d03 BH |
1226 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", |
1227 | __func__, rc); | |
afd4aea0 BH |
1228 | return rc; |
1229 | } | |
1230 | ||
6bff861d | 1231 | static int efx_mcdi_reset_mc(struct efx_nic *efx) |
afd4aea0 | 1232 | { |
59cfc479 | 1233 | MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN); |
afd4aea0 BH |
1234 | int rc; |
1235 | ||
1236 | BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0); | |
1237 | MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0); | |
1238 | rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf), | |
1239 | NULL, 0, NULL); | |
1240 | /* White is black, and up is down */ | |
1241 | if (rc == -EIO) | |
1242 | return 0; | |
1243 | if (rc == 0) | |
1244 | rc = -EIO; | |
62776d03 | 1245 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1246 | return rc; |
1247 | } | |
1248 | ||
6bff861d BH |
1249 | enum reset_type efx_mcdi_map_reset_reason(enum reset_type reason) |
1250 | { | |
1251 | return RESET_TYPE_RECOVER_OR_ALL; | |
1252 | } | |
1253 | ||
1254 | int efx_mcdi_reset(struct efx_nic *efx, enum reset_type method) | |
1255 | { | |
1256 | int rc; | |
1257 | ||
1258 | /* Recover from a failed assertion pre-reset */ | |
1259 | rc = efx_mcdi_handle_assertion(efx); | |
1260 | if (rc) | |
1261 | return rc; | |
1262 | ||
1263 | if (method == RESET_TYPE_WORLD) | |
1264 | return efx_mcdi_reset_mc(efx); | |
1265 | else | |
1266 | return efx_mcdi_reset_port(efx); | |
1267 | } | |
1268 | ||
d215697f | 1269 | static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type, |
1270 | const u8 *mac, int *id_out) | |
afd4aea0 | 1271 | { |
59cfc479 BH |
1272 | MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_SET_IN_LEN); |
1273 | MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_SET_OUT_LEN); | |
afd4aea0 BH |
1274 | size_t outlen; |
1275 | int rc; | |
1276 | ||
1277 | MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type); | |
1278 | MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE, | |
1279 | MC_CMD_FILTER_MODE_SIMPLE); | |
1280 | memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN); | |
1281 | ||
1282 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf), | |
1283 | outbuf, sizeof(outbuf), &outlen); | |
1284 | if (rc) | |
1285 | goto fail; | |
1286 | ||
1287 | if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) { | |
00bbb4a5 | 1288 | rc = -EIO; |
afd4aea0 BH |
1289 | goto fail; |
1290 | } | |
1291 | ||
1292 | *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID); | |
1293 | ||
1294 | return 0; | |
1295 | ||
1296 | fail: | |
1297 | *id_out = -1; | |
62776d03 | 1298 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1299 | return rc; |
1300 | ||
1301 | } | |
1302 | ||
1303 | ||
1304 | int | |
1305 | efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out) | |
1306 | { | |
1307 | return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out); | |
1308 | } | |
1309 | ||
1310 | ||
1311 | int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out) | |
1312 | { | |
59cfc479 | 1313 | MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_GET_OUT_LEN); |
afd4aea0 BH |
1314 | size_t outlen; |
1315 | int rc; | |
1316 | ||
1317 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0, | |
1318 | outbuf, sizeof(outbuf), &outlen); | |
1319 | if (rc) | |
1320 | goto fail; | |
1321 | ||
1322 | if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) { | |
00bbb4a5 | 1323 | rc = -EIO; |
afd4aea0 BH |
1324 | goto fail; |
1325 | } | |
1326 | ||
1327 | *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID); | |
1328 | ||
1329 | return 0; | |
1330 | ||
1331 | fail: | |
1332 | *id_out = -1; | |
62776d03 | 1333 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1334 | return rc; |
1335 | } | |
1336 | ||
1337 | ||
1338 | int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id) | |
1339 | { | |
59cfc479 | 1340 | MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_REMOVE_IN_LEN); |
afd4aea0 BH |
1341 | int rc; |
1342 | ||
1343 | MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id); | |
1344 | ||
1345 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf), | |
1346 | NULL, 0, NULL); | |
1347 | if (rc) | |
1348 | goto fail; | |
1349 | ||
1350 | return 0; | |
1351 | ||
1352 | fail: | |
62776d03 | 1353 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1354 | return rc; |
1355 | } | |
1356 | ||
cd2d5b52 BH |
1357 | int efx_mcdi_flush_rxqs(struct efx_nic *efx) |
1358 | { | |
1359 | struct efx_channel *channel; | |
1360 | struct efx_rx_queue *rx_queue; | |
c5bb0e98 BH |
1361 | MCDI_DECLARE_BUF(inbuf, |
1362 | MC_CMD_FLUSH_RX_QUEUES_IN_LEN(EFX_MAX_CHANNELS)); | |
cd2d5b52 BH |
1363 | int rc, count; |
1364 | ||
45078374 BH |
1365 | BUILD_BUG_ON(EFX_MAX_CHANNELS > |
1366 | MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM); | |
1367 | ||
cd2d5b52 BH |
1368 | count = 0; |
1369 | efx_for_each_channel(channel, efx) { | |
1370 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
1371 | if (rx_queue->flush_pending) { | |
1372 | rx_queue->flush_pending = false; | |
1373 | atomic_dec(&efx->rxq_flush_pending); | |
c5bb0e98 BH |
1374 | MCDI_SET_ARRAY_DWORD( |
1375 | inbuf, FLUSH_RX_QUEUES_IN_QID_OFST, | |
1376 | count, efx_rx_queue_index(rx_queue)); | |
1377 | count++; | |
cd2d5b52 BH |
1378 | } |
1379 | } | |
1380 | } | |
1381 | ||
c5bb0e98 BH |
1382 | rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf, |
1383 | MC_CMD_FLUSH_RX_QUEUES_IN_LEN(count), NULL, 0, NULL); | |
bbec969b | 1384 | WARN_ON(rc < 0); |
cd2d5b52 | 1385 | |
cd2d5b52 BH |
1386 | return rc; |
1387 | } | |
afd4aea0 BH |
1388 | |
1389 | int efx_mcdi_wol_filter_reset(struct efx_nic *efx) | |
1390 | { | |
1391 | int rc; | |
1392 | ||
1393 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL); | |
1394 | if (rc) | |
1395 | goto fail; | |
1396 | ||
1397 | return 0; | |
1398 | ||
1399 | fail: | |
62776d03 | 1400 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1401 | return rc; |
1402 | } | |
1403 | ||
45a3fd55 BH |
1404 | #ifdef CONFIG_SFC_MTD |
1405 | ||
1406 | #define EFX_MCDI_NVRAM_LEN_MAX 128 | |
1407 | ||
1408 | static int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type) | |
1409 | { | |
1410 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_START_IN_LEN); | |
1411 | int rc; | |
1412 | ||
1413 | MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type); | |
1414 | ||
1415 | BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0); | |
1416 | ||
1417 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf), | |
1418 | NULL, 0, NULL); | |
1419 | if (rc) | |
1420 | goto fail; | |
1421 | ||
1422 | return 0; | |
1423 | ||
1424 | fail: | |
1425 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); | |
1426 | return rc; | |
1427 | } | |
1428 | ||
1429 | static int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type, | |
1430 | loff_t offset, u8 *buffer, size_t length) | |
1431 | { | |
1432 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_READ_IN_LEN); | |
1433 | MCDI_DECLARE_BUF(outbuf, | |
1434 | MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)); | |
1435 | size_t outlen; | |
1436 | int rc; | |
1437 | ||
1438 | MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type); | |
1439 | MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset); | |
1440 | MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length); | |
1441 | ||
1442 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf), | |
1443 | outbuf, sizeof(outbuf), &outlen); | |
1444 | if (rc) | |
1445 | goto fail; | |
1446 | ||
1447 | memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length); | |
1448 | return 0; | |
1449 | ||
1450 | fail: | |
1451 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); | |
1452 | return rc; | |
1453 | } | |
1454 | ||
1455 | static int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type, | |
1456 | loff_t offset, const u8 *buffer, size_t length) | |
1457 | { | |
1458 | MCDI_DECLARE_BUF(inbuf, | |
1459 | MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)); | |
1460 | int rc; | |
1461 | ||
1462 | MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type); | |
1463 | MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset); | |
1464 | MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length); | |
1465 | memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length); | |
1466 | ||
1467 | BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0); | |
1468 | ||
1469 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf, | |
1470 | ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4), | |
1471 | NULL, 0, NULL); | |
1472 | if (rc) | |
1473 | goto fail; | |
1474 | ||
1475 | return 0; | |
1476 | ||
1477 | fail: | |
1478 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); | |
1479 | return rc; | |
1480 | } | |
1481 | ||
1482 | static int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type, | |
1483 | loff_t offset, size_t length) | |
1484 | { | |
1485 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_ERASE_IN_LEN); | |
1486 | int rc; | |
1487 | ||
1488 | MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type); | |
1489 | MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset); | |
1490 | MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length); | |
1491 | ||
1492 | BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0); | |
1493 | ||
1494 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf), | |
1495 | NULL, 0, NULL); | |
1496 | if (rc) | |
1497 | goto fail; | |
1498 | ||
1499 | return 0; | |
1500 | ||
1501 | fail: | |
1502 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); | |
1503 | return rc; | |
1504 | } | |
1505 | ||
1506 | static int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type) | |
1507 | { | |
1508 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN); | |
1509 | int rc; | |
1510 | ||
1511 | MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type); | |
1512 | ||
1513 | BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0); | |
1514 | ||
1515 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf), | |
1516 | NULL, 0, NULL); | |
1517 | if (rc) | |
1518 | goto fail; | |
1519 | ||
1520 | return 0; | |
1521 | ||
1522 | fail: | |
1523 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); | |
1524 | return rc; | |
1525 | } | |
1526 | ||
1527 | int efx_mcdi_mtd_read(struct mtd_info *mtd, loff_t start, | |
1528 | size_t len, size_t *retlen, u8 *buffer) | |
1529 | { | |
1530 | struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd); | |
1531 | struct efx_nic *efx = mtd->priv; | |
1532 | loff_t offset = start; | |
1533 | loff_t end = min_t(loff_t, start + len, mtd->size); | |
1534 | size_t chunk; | |
1535 | int rc = 0; | |
1536 | ||
1537 | while (offset < end) { | |
1538 | chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX); | |
1539 | rc = efx_mcdi_nvram_read(efx, part->nvram_type, offset, | |
1540 | buffer, chunk); | |
1541 | if (rc) | |
1542 | goto out; | |
1543 | offset += chunk; | |
1544 | buffer += chunk; | |
1545 | } | |
1546 | out: | |
1547 | *retlen = offset - start; | |
1548 | return rc; | |
1549 | } | |
1550 | ||
1551 | int efx_mcdi_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len) | |
1552 | { | |
1553 | struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd); | |
1554 | struct efx_nic *efx = mtd->priv; | |
1555 | loff_t offset = start & ~((loff_t)(mtd->erasesize - 1)); | |
1556 | loff_t end = min_t(loff_t, start + len, mtd->size); | |
1557 | size_t chunk = part->common.mtd.erasesize; | |
1558 | int rc = 0; | |
1559 | ||
1560 | if (!part->updating) { | |
1561 | rc = efx_mcdi_nvram_update_start(efx, part->nvram_type); | |
1562 | if (rc) | |
1563 | goto out; | |
1564 | part->updating = true; | |
1565 | } | |
1566 | ||
1567 | /* The MCDI interface can in fact do multiple erase blocks at once; | |
1568 | * but erasing may be slow, so we make multiple calls here to avoid | |
1569 | * tripping the MCDI RPC timeout. */ | |
1570 | while (offset < end) { | |
1571 | rc = efx_mcdi_nvram_erase(efx, part->nvram_type, offset, | |
1572 | chunk); | |
1573 | if (rc) | |
1574 | goto out; | |
1575 | offset += chunk; | |
1576 | } | |
1577 | out: | |
1578 | return rc; | |
1579 | } | |
1580 | ||
1581 | int efx_mcdi_mtd_write(struct mtd_info *mtd, loff_t start, | |
1582 | size_t len, size_t *retlen, const u8 *buffer) | |
1583 | { | |
1584 | struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd); | |
1585 | struct efx_nic *efx = mtd->priv; | |
1586 | loff_t offset = start; | |
1587 | loff_t end = min_t(loff_t, start + len, mtd->size); | |
1588 | size_t chunk; | |
1589 | int rc = 0; | |
1590 | ||
1591 | if (!part->updating) { | |
1592 | rc = efx_mcdi_nvram_update_start(efx, part->nvram_type); | |
1593 | if (rc) | |
1594 | goto out; | |
1595 | part->updating = true; | |
1596 | } | |
1597 | ||
1598 | while (offset < end) { | |
1599 | chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX); | |
1600 | rc = efx_mcdi_nvram_write(efx, part->nvram_type, offset, | |
1601 | buffer, chunk); | |
1602 | if (rc) | |
1603 | goto out; | |
1604 | offset += chunk; | |
1605 | buffer += chunk; | |
1606 | } | |
1607 | out: | |
1608 | *retlen = offset - start; | |
1609 | return rc; | |
1610 | } | |
1611 | ||
1612 | int efx_mcdi_mtd_sync(struct mtd_info *mtd) | |
1613 | { | |
1614 | struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd); | |
1615 | struct efx_nic *efx = mtd->priv; | |
1616 | int rc = 0; | |
1617 | ||
1618 | if (part->updating) { | |
1619 | part->updating = false; | |
1620 | rc = efx_mcdi_nvram_update_finish(efx, part->nvram_type); | |
1621 | } | |
1622 | ||
1623 | return rc; | |
1624 | } | |
1625 | ||
1626 | void efx_mcdi_mtd_rename(struct efx_mtd_partition *part) | |
1627 | { | |
1628 | struct efx_mcdi_mtd_partition *mcdi_part = | |
1629 | container_of(part, struct efx_mcdi_mtd_partition, common); | |
1630 | struct efx_nic *efx = part->mtd.priv; | |
1631 | ||
1632 | snprintf(part->name, sizeof(part->name), "%s %s:%02x", | |
1633 | efx->name, part->type_name, mcdi_part->fw_subtype); | |
1634 | } | |
1635 | ||
1636 | #endif /* CONFIG_SFC_MTD */ |