Commit | Line | Data |
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afd4aea0 | 1 | /**************************************************************************** |
f7a6d2c4 BH |
2 | * Driver for Solarflare network controllers and boards |
3 | * Copyright 2008-2013 Solarflare Communications Inc. | |
afd4aea0 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
251111d9 | 11 | #include <asm/cmpxchg.h> |
afd4aea0 BH |
12 | #include "net_driver.h" |
13 | #include "nic.h" | |
14 | #include "io.h" | |
8b8a95a1 | 15 | #include "farch_regs.h" |
afd4aea0 BH |
16 | #include "mcdi_pcol.h" |
17 | #include "phy.h" | |
18 | ||
19 | /************************************************************************** | |
20 | * | |
21 | * Management-Controller-to-Driver Interface | |
22 | * | |
23 | ************************************************************************** | |
24 | */ | |
25 | ||
ebf98e79 | 26 | #define MCDI_RPC_TIMEOUT (10 * HZ) |
afd4aea0 | 27 | |
3f713bf4 BH |
28 | /* A reboot/assertion causes the MCDI status word to be set after the |
29 | * command word is set or a REBOOT event is sent. If we notice a reboot | |
b2d32f03 | 30 | * via these mechanisms then wait 250ms for the status word to be set. |
d36a08b4 | 31 | */ |
3f713bf4 | 32 | #define MCDI_STATUS_DELAY_US 100 |
b2d32f03 | 33 | #define MCDI_STATUS_DELAY_COUNT 2500 |
3f713bf4 BH |
34 | #define MCDI_STATUS_SLEEP_MS \ |
35 | (MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000) | |
afd4aea0 BH |
36 | |
37 | #define SEQ_MASK \ | |
38 | EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ)) | |
39 | ||
cade715f BH |
40 | struct efx_mcdi_async_param { |
41 | struct list_head list; | |
42 | unsigned int cmd; | |
43 | size_t inlen; | |
44 | size_t outlen; | |
1e0b8120 | 45 | bool quiet; |
cade715f BH |
46 | efx_mcdi_async_completer *complete; |
47 | unsigned long cookie; | |
48 | /* followed by request/response buffer */ | |
49 | }; | |
50 | ||
51 | static void efx_mcdi_timeout_async(unsigned long context); | |
4c75b43a BH |
52 | static int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating, |
53 | bool *was_attached_out); | |
5731d7b3 | 54 | static bool efx_mcdi_poll_once(struct efx_nic *efx); |
e283546c | 55 | static void efx_mcdi_abandon(struct efx_nic *efx); |
afd4aea0 | 56 | |
f073dde0 | 57 | int efx_mcdi_init(struct efx_nic *efx) |
afd4aea0 BH |
58 | { |
59 | struct efx_mcdi_iface *mcdi; | |
4c75b43a BH |
60 | bool already_attached; |
61 | int rc; | |
afd4aea0 | 62 | |
f3ad5003 BH |
63 | efx->mcdi = kzalloc(sizeof(*efx->mcdi), GFP_KERNEL); |
64 | if (!efx->mcdi) | |
65 | return -ENOMEM; | |
66 | ||
afd4aea0 | 67 | mcdi = efx_mcdi(efx); |
cade715f | 68 | mcdi->efx = efx; |
afd4aea0 BH |
69 | init_waitqueue_head(&mcdi->wq); |
70 | spin_lock_init(&mcdi->iface_lock); | |
251111d9 | 71 | mcdi->state = MCDI_STATE_QUIESCENT; |
afd4aea0 | 72 | mcdi->mode = MCDI_MODE_POLL; |
cade715f BH |
73 | spin_lock_init(&mcdi->async_lock); |
74 | INIT_LIST_HEAD(&mcdi->async_list); | |
75 | setup_timer(&mcdi->async_timer, efx_mcdi_timeout_async, | |
76 | (unsigned long)mcdi); | |
afd4aea0 BH |
77 | |
78 | (void) efx_mcdi_poll_reboot(efx); | |
d36a08b4 | 79 | mcdi->new_epoch = true; |
f073dde0 BH |
80 | |
81 | /* Recover from a failed assertion before probing */ | |
4c75b43a BH |
82 | rc = efx_mcdi_handle_assertion(efx); |
83 | if (rc) | |
84 | return rc; | |
85 | ||
86 | /* Let the MC (and BMC, if this is a LOM) know that the driver | |
87 | * is loaded. We should do this before we reset the NIC. | |
88 | */ | |
89 | rc = efx_mcdi_drv_attach(efx, true, &already_attached); | |
90 | if (rc) { | |
91 | netif_err(efx, probe, efx->net_dev, | |
92 | "Unable to register driver with MCPU\n"); | |
93 | return rc; | |
94 | } | |
95 | if (already_attached) | |
96 | /* Not a fatal error */ | |
97 | netif_err(efx, probe, efx->net_dev, | |
98 | "Host already registered with MCPU\n"); | |
99 | ||
0bcf4a64 BH |
100 | if (efx->mcdi->fn_flags & |
101 | (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) | |
102 | efx->primary = efx; | |
103 | ||
4c75b43a | 104 | return 0; |
afd4aea0 BH |
105 | } |
106 | ||
f3ad5003 BH |
107 | void efx_mcdi_fini(struct efx_nic *efx) |
108 | { | |
4c75b43a BH |
109 | if (!efx->mcdi) |
110 | return; | |
111 | ||
112 | BUG_ON(efx->mcdi->iface.state != MCDI_STATE_QUIESCENT); | |
113 | ||
114 | /* Relinquish the device (back to the BMC, if this is a LOM) */ | |
115 | efx_mcdi_drv_attach(efx, false, NULL); | |
116 | ||
f3ad5003 BH |
117 | kfree(efx->mcdi); |
118 | } | |
119 | ||
2f4bcdcc BH |
120 | static void efx_mcdi_send_request(struct efx_nic *efx, unsigned cmd, |
121 | const efx_dword_t *inbuf, size_t inlen) | |
afd4aea0 BH |
122 | { |
123 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
df2cd8af BH |
124 | efx_dword_t hdr[2]; |
125 | size_t hdr_len; | |
afd4aea0 BH |
126 | u32 xflags, seqno; |
127 | ||
251111d9 | 128 | BUG_ON(mcdi->state == MCDI_STATE_QUIESCENT); |
afd4aea0 | 129 | |
2f4bcdcc BH |
130 | /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */ |
131 | spin_lock_bh(&mcdi->iface_lock); | |
132 | ++mcdi->seqno; | |
133 | spin_unlock_bh(&mcdi->iface_lock); | |
134 | ||
afd4aea0 BH |
135 | seqno = mcdi->seqno & SEQ_MASK; |
136 | xflags = 0; | |
137 | if (mcdi->mode == MCDI_MODE_EVENTS) | |
138 | xflags |= MCDI_HEADER_XFLAGS_EVREQ; | |
139 | ||
df2cd8af BH |
140 | if (efx->type->mcdi_max_ver == 1) { |
141 | /* MCDI v1 */ | |
d36a08b4 | 142 | EFX_POPULATE_DWORD_7(hdr[0], |
df2cd8af BH |
143 | MCDI_HEADER_RESPONSE, 0, |
144 | MCDI_HEADER_RESYNC, 1, | |
145 | MCDI_HEADER_CODE, cmd, | |
146 | MCDI_HEADER_DATALEN, inlen, | |
147 | MCDI_HEADER_SEQ, seqno, | |
d36a08b4 DP |
148 | MCDI_HEADER_XFLAGS, xflags, |
149 | MCDI_HEADER_NOT_EPOCH, !mcdi->new_epoch); | |
df2cd8af BH |
150 | hdr_len = 4; |
151 | } else { | |
152 | /* MCDI v2 */ | |
153 | BUG_ON(inlen > MCDI_CTL_SDU_LEN_MAX_V2); | |
d36a08b4 | 154 | EFX_POPULATE_DWORD_7(hdr[0], |
df2cd8af BH |
155 | MCDI_HEADER_RESPONSE, 0, |
156 | MCDI_HEADER_RESYNC, 1, | |
157 | MCDI_HEADER_CODE, MC_CMD_V2_EXTN, | |
158 | MCDI_HEADER_DATALEN, 0, | |
159 | MCDI_HEADER_SEQ, seqno, | |
d36a08b4 DP |
160 | MCDI_HEADER_XFLAGS, xflags, |
161 | MCDI_HEADER_NOT_EPOCH, !mcdi->new_epoch); | |
df2cd8af BH |
162 | EFX_POPULATE_DWORD_2(hdr[1], |
163 | MC_CMD_V2_EXTN_IN_EXTENDED_CMD, cmd, | |
164 | MC_CMD_V2_EXTN_IN_ACTUAL_LEN, inlen); | |
165 | hdr_len = 8; | |
166 | } | |
afd4aea0 | 167 | |
df2cd8af | 168 | efx->type->mcdi_request(efx, hdr, hdr_len, inbuf, inlen); |
2f4bcdcc BH |
169 | |
170 | mcdi->new_epoch = false; | |
afd4aea0 BH |
171 | } |
172 | ||
5bc283e5 BH |
173 | static int efx_mcdi_errno(unsigned int mcdi_err) |
174 | { | |
175 | switch (mcdi_err) { | |
176 | case 0: | |
177 | return 0; | |
178 | #define TRANSLATE_ERROR(name) \ | |
179 | case MC_CMD_ERR_ ## name: \ | |
180 | return -name; | |
df2cd8af | 181 | TRANSLATE_ERROR(EPERM); |
5bc283e5 BH |
182 | TRANSLATE_ERROR(ENOENT); |
183 | TRANSLATE_ERROR(EINTR); | |
df2cd8af | 184 | TRANSLATE_ERROR(EAGAIN); |
5bc283e5 BH |
185 | TRANSLATE_ERROR(EACCES); |
186 | TRANSLATE_ERROR(EBUSY); | |
187 | TRANSLATE_ERROR(EINVAL); | |
188 | TRANSLATE_ERROR(EDEADLK); | |
189 | TRANSLATE_ERROR(ENOSYS); | |
190 | TRANSLATE_ERROR(ETIME); | |
df2cd8af BH |
191 | TRANSLATE_ERROR(EALREADY); |
192 | TRANSLATE_ERROR(ENOSPC); | |
5bc283e5 | 193 | #undef TRANSLATE_ERROR |
ea136ae7 BH |
194 | case MC_CMD_ERR_ENOTSUP: |
195 | return -EOPNOTSUPP; | |
df2cd8af BH |
196 | case MC_CMD_ERR_ALLOC_FAIL: |
197 | return -ENOBUFS; | |
198 | case MC_CMD_ERR_MAC_EXIST: | |
199 | return -EADDRINUSE; | |
5bc283e5 | 200 | default: |
df2cd8af BH |
201 | return -EPROTO; |
202 | } | |
203 | } | |
204 | ||
205 | static void efx_mcdi_read_response_header(struct efx_nic *efx) | |
206 | { | |
207 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
208 | unsigned int respseq, respcmd, error; | |
209 | efx_dword_t hdr; | |
210 | ||
211 | efx->type->mcdi_read_response(efx, &hdr, 0, 4); | |
212 | respseq = EFX_DWORD_FIELD(hdr, MCDI_HEADER_SEQ); | |
213 | respcmd = EFX_DWORD_FIELD(hdr, MCDI_HEADER_CODE); | |
214 | error = EFX_DWORD_FIELD(hdr, MCDI_HEADER_ERROR); | |
215 | ||
216 | if (respcmd != MC_CMD_V2_EXTN) { | |
217 | mcdi->resp_hdr_len = 4; | |
218 | mcdi->resp_data_len = EFX_DWORD_FIELD(hdr, MCDI_HEADER_DATALEN); | |
219 | } else { | |
220 | efx->type->mcdi_read_response(efx, &hdr, 4, 4); | |
221 | mcdi->resp_hdr_len = 8; | |
222 | mcdi->resp_data_len = | |
223 | EFX_DWORD_FIELD(hdr, MC_CMD_V2_EXTN_IN_ACTUAL_LEN); | |
224 | } | |
225 | ||
226 | if (error && mcdi->resp_data_len == 0) { | |
227 | netif_err(efx, hw, efx->net_dev, "MC rebooted\n"); | |
228 | mcdi->resprc = -EIO; | |
229 | } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) { | |
230 | netif_err(efx, hw, efx->net_dev, | |
231 | "MC response mismatch tx seq 0x%x rx seq 0x%x\n", | |
232 | respseq, mcdi->seqno); | |
233 | mcdi->resprc = -EIO; | |
234 | } else if (error) { | |
235 | efx->type->mcdi_read_response(efx, &hdr, mcdi->resp_hdr_len, 4); | |
236 | mcdi->resprc = | |
237 | efx_mcdi_errno(EFX_DWORD_FIELD(hdr, EFX_DWORD_0)); | |
238 | } else { | |
239 | mcdi->resprc = 0; | |
5bc283e5 BH |
240 | } |
241 | } | |
242 | ||
5731d7b3 RS |
243 | static bool efx_mcdi_poll_once(struct efx_nic *efx) |
244 | { | |
245 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
246 | ||
247 | rmb(); | |
248 | if (!efx->type->mcdi_poll_response(efx)) | |
249 | return false; | |
250 | ||
251 | spin_lock_bh(&mcdi->iface_lock); | |
252 | efx_mcdi_read_response_header(efx); | |
253 | spin_unlock_bh(&mcdi->iface_lock); | |
254 | ||
255 | return true; | |
256 | } | |
257 | ||
afd4aea0 BH |
258 | static int efx_mcdi_poll(struct efx_nic *efx) |
259 | { | |
260 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
ebf98e79 | 261 | unsigned long time, finish; |
5bc283e5 | 262 | unsigned int spins; |
5bc283e5 | 263 | int rc; |
afd4aea0 BH |
264 | |
265 | /* Check for a reboot atomically with respect to efx_mcdi_copyout() */ | |
5bc283e5 | 266 | rc = efx_mcdi_poll_reboot(efx); |
df2cd8af | 267 | if (rc) { |
369327fa | 268 | spin_lock_bh(&mcdi->iface_lock); |
df2cd8af BH |
269 | mcdi->resprc = rc; |
270 | mcdi->resp_hdr_len = 0; | |
271 | mcdi->resp_data_len = 0; | |
369327fa | 272 | spin_unlock_bh(&mcdi->iface_lock); |
df2cd8af BH |
273 | return 0; |
274 | } | |
afd4aea0 BH |
275 | |
276 | /* Poll for completion. Poll quickly (once a us) for the 1st jiffy, | |
277 | * because generally mcdi responses are fast. After that, back off | |
278 | * and poll once a jiffy (approximately) | |
279 | */ | |
280 | spins = TICK_USEC; | |
ebf98e79 | 281 | finish = jiffies + MCDI_RPC_TIMEOUT; |
afd4aea0 BH |
282 | |
283 | while (1) { | |
284 | if (spins != 0) { | |
285 | --spins; | |
286 | udelay(1); | |
55029c1d BH |
287 | } else { |
288 | schedule_timeout_uninterruptible(1); | |
289 | } | |
afd4aea0 | 290 | |
ebf98e79 | 291 | time = jiffies; |
afd4aea0 | 292 | |
5731d7b3 | 293 | if (efx_mcdi_poll_once(efx)) |
afd4aea0 BH |
294 | break; |
295 | ||
ebf98e79 | 296 | if (time_after(time, finish)) |
afd4aea0 BH |
297 | return -ETIMEDOUT; |
298 | } | |
299 | ||
afd4aea0 BH |
300 | /* Return rc=0 like wait_event_timeout() */ |
301 | return 0; | |
302 | } | |
303 | ||
876be083 BH |
304 | /* Test and clear MC-rebooted flag for this port/function; reset |
305 | * software state as necessary. | |
306 | */ | |
afd4aea0 BH |
307 | int efx_mcdi_poll_reboot(struct efx_nic *efx) |
308 | { | |
f3ad5003 BH |
309 | if (!efx->mcdi) |
310 | return 0; | |
afd4aea0 | 311 | |
cd0ecc9a | 312 | return efx->type->mcdi_poll_reboot(efx); |
afd4aea0 BH |
313 | } |
314 | ||
cade715f BH |
315 | static bool efx_mcdi_acquire_async(struct efx_mcdi_iface *mcdi) |
316 | { | |
317 | return cmpxchg(&mcdi->state, | |
318 | MCDI_STATE_QUIESCENT, MCDI_STATE_RUNNING_ASYNC) == | |
319 | MCDI_STATE_QUIESCENT; | |
320 | } | |
321 | ||
322 | static void efx_mcdi_acquire_sync(struct efx_mcdi_iface *mcdi) | |
afd4aea0 BH |
323 | { |
324 | /* Wait until the interface becomes QUIESCENT and we win the race | |
cade715f BH |
325 | * to mark it RUNNING_SYNC. |
326 | */ | |
afd4aea0 | 327 | wait_event(mcdi->wq, |
251111d9 | 328 | cmpxchg(&mcdi->state, |
cade715f | 329 | MCDI_STATE_QUIESCENT, MCDI_STATE_RUNNING_SYNC) == |
251111d9 | 330 | MCDI_STATE_QUIESCENT); |
afd4aea0 BH |
331 | } |
332 | ||
333 | static int efx_mcdi_await_completion(struct efx_nic *efx) | |
334 | { | |
335 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
336 | ||
251111d9 BH |
337 | if (wait_event_timeout(mcdi->wq, mcdi->state == MCDI_STATE_COMPLETED, |
338 | MCDI_RPC_TIMEOUT) == 0) | |
afd4aea0 BH |
339 | return -ETIMEDOUT; |
340 | ||
341 | /* Check if efx_mcdi_set_mode() switched us back to polled completions. | |
342 | * In which case, poll for completions directly. If efx_mcdi_ev_cpl() | |
343 | * completed the request first, then we'll just end up completing the | |
344 | * request again, which is safe. | |
345 | * | |
346 | * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which | |
347 | * wait_event_timeout() implicitly provides. | |
348 | */ | |
349 | if (mcdi->mode == MCDI_MODE_POLL) | |
350 | return efx_mcdi_poll(efx); | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
cade715f BH |
355 | /* If the interface is RUNNING_SYNC, switch to COMPLETED and wake the |
356 | * requester. Return whether this was done. Does not take any locks. | |
357 | */ | |
358 | static bool efx_mcdi_complete_sync(struct efx_mcdi_iface *mcdi) | |
afd4aea0 | 359 | { |
cade715f BH |
360 | if (cmpxchg(&mcdi->state, |
361 | MCDI_STATE_RUNNING_SYNC, MCDI_STATE_COMPLETED) == | |
362 | MCDI_STATE_RUNNING_SYNC) { | |
afd4aea0 BH |
363 | wake_up(&mcdi->wq); |
364 | return true; | |
365 | } | |
366 | ||
367 | return false; | |
368 | } | |
369 | ||
370 | static void efx_mcdi_release(struct efx_mcdi_iface *mcdi) | |
371 | { | |
cade715f BH |
372 | if (mcdi->mode == MCDI_MODE_EVENTS) { |
373 | struct efx_mcdi_async_param *async; | |
374 | struct efx_nic *efx = mcdi->efx; | |
375 | ||
376 | /* Process the asynchronous request queue */ | |
377 | spin_lock_bh(&mcdi->async_lock); | |
378 | async = list_first_entry_or_null( | |
379 | &mcdi->async_list, struct efx_mcdi_async_param, list); | |
380 | if (async) { | |
381 | mcdi->state = MCDI_STATE_RUNNING_ASYNC; | |
382 | efx_mcdi_send_request(efx, async->cmd, | |
383 | (const efx_dword_t *)(async + 1), | |
384 | async->inlen); | |
385 | mod_timer(&mcdi->async_timer, | |
386 | jiffies + MCDI_RPC_TIMEOUT); | |
387 | } | |
388 | spin_unlock_bh(&mcdi->async_lock); | |
389 | ||
390 | if (async) | |
391 | return; | |
392 | } | |
393 | ||
251111d9 | 394 | mcdi->state = MCDI_STATE_QUIESCENT; |
afd4aea0 BH |
395 | wake_up(&mcdi->wq); |
396 | } | |
397 | ||
cade715f BH |
398 | /* If the interface is RUNNING_ASYNC, switch to COMPLETED, call the |
399 | * asynchronous completion function, and release the interface. | |
400 | * Return whether this was done. Must be called in bh-disabled | |
401 | * context. Will take iface_lock and async_lock. | |
402 | */ | |
403 | static bool efx_mcdi_complete_async(struct efx_mcdi_iface *mcdi, bool timeout) | |
404 | { | |
405 | struct efx_nic *efx = mcdi->efx; | |
406 | struct efx_mcdi_async_param *async; | |
1e0b8120 | 407 | size_t hdr_len, data_len, err_len; |
cade715f | 408 | efx_dword_t *outbuf; |
1e0b8120 | 409 | MCDI_DECLARE_BUF_OUT_OR_ERR(errbuf, 0); |
cade715f BH |
410 | int rc; |
411 | ||
412 | if (cmpxchg(&mcdi->state, | |
413 | MCDI_STATE_RUNNING_ASYNC, MCDI_STATE_COMPLETED) != | |
414 | MCDI_STATE_RUNNING_ASYNC) | |
415 | return false; | |
416 | ||
417 | spin_lock(&mcdi->iface_lock); | |
418 | if (timeout) { | |
419 | /* Ensure that if the completion event arrives later, | |
420 | * the seqno check in efx_mcdi_ev_cpl() will fail | |
421 | */ | |
422 | ++mcdi->seqno; | |
423 | ++mcdi->credits; | |
424 | rc = -ETIMEDOUT; | |
425 | hdr_len = 0; | |
426 | data_len = 0; | |
427 | } else { | |
428 | rc = mcdi->resprc; | |
429 | hdr_len = mcdi->resp_hdr_len; | |
430 | data_len = mcdi->resp_data_len; | |
431 | } | |
432 | spin_unlock(&mcdi->iface_lock); | |
433 | ||
434 | /* Stop the timer. In case the timer function is running, we | |
435 | * must wait for it to return so that there is no possibility | |
436 | * of it aborting the next request. | |
437 | */ | |
438 | if (!timeout) | |
439 | del_timer_sync(&mcdi->async_timer); | |
440 | ||
441 | spin_lock(&mcdi->async_lock); | |
442 | async = list_first_entry(&mcdi->async_list, | |
443 | struct efx_mcdi_async_param, list); | |
444 | list_del(&async->list); | |
445 | spin_unlock(&mcdi->async_lock); | |
446 | ||
447 | outbuf = (efx_dword_t *)(async + 1); | |
448 | efx->type->mcdi_read_response(efx, outbuf, hdr_len, | |
449 | min(async->outlen, data_len)); | |
1e0b8120 EC |
450 | if (!timeout && rc && !async->quiet) { |
451 | err_len = min(sizeof(errbuf), data_len); | |
452 | efx->type->mcdi_read_response(efx, errbuf, hdr_len, | |
453 | sizeof(errbuf)); | |
454 | efx_mcdi_display_error(efx, async->cmd, async->inlen, errbuf, | |
455 | err_len, rc); | |
456 | } | |
cade715f BH |
457 | async->complete(efx, async->cookie, rc, outbuf, data_len); |
458 | kfree(async); | |
459 | ||
460 | efx_mcdi_release(mcdi); | |
461 | ||
462 | return true; | |
463 | } | |
464 | ||
afd4aea0 | 465 | static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno, |
5bc283e5 | 466 | unsigned int datalen, unsigned int mcdi_err) |
afd4aea0 BH |
467 | { |
468 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
469 | bool wake = false; | |
470 | ||
471 | spin_lock(&mcdi->iface_lock); | |
472 | ||
473 | if ((seqno ^ mcdi->seqno) & SEQ_MASK) { | |
474 | if (mcdi->credits) | |
475 | /* The request has been cancelled */ | |
476 | --mcdi->credits; | |
477 | else | |
62776d03 BH |
478 | netif_err(efx, hw, efx->net_dev, |
479 | "MC response mismatch tx seq 0x%x rx " | |
480 | "seq 0x%x\n", seqno, mcdi->seqno); | |
afd4aea0 | 481 | } else { |
df2cd8af BH |
482 | if (efx->type->mcdi_max_ver >= 2) { |
483 | /* MCDI v2 responses don't fit in an event */ | |
484 | efx_mcdi_read_response_header(efx); | |
485 | } else { | |
486 | mcdi->resprc = efx_mcdi_errno(mcdi_err); | |
487 | mcdi->resp_hdr_len = 4; | |
488 | mcdi->resp_data_len = datalen; | |
489 | } | |
afd4aea0 BH |
490 | |
491 | wake = true; | |
492 | } | |
493 | ||
494 | spin_unlock(&mcdi->iface_lock); | |
495 | ||
cade715f BH |
496 | if (wake) { |
497 | if (!efx_mcdi_complete_async(mcdi, false)) | |
498 | (void) efx_mcdi_complete_sync(mcdi); | |
499 | ||
500 | /* If the interface isn't RUNNING_ASYNC or | |
501 | * RUNNING_SYNC then we've received a duplicate | |
502 | * completion after we've already transitioned back to | |
503 | * QUIESCENT. [A subsequent invocation would increment | |
504 | * seqno, so would have failed the seqno check]. | |
505 | */ | |
506 | } | |
507 | } | |
508 | ||
509 | static void efx_mcdi_timeout_async(unsigned long context) | |
510 | { | |
511 | struct efx_mcdi_iface *mcdi = (struct efx_mcdi_iface *)context; | |
512 | ||
513 | efx_mcdi_complete_async(mcdi, true); | |
afd4aea0 BH |
514 | } |
515 | ||
2f4bcdcc BH |
516 | static int |
517 | efx_mcdi_check_supported(struct efx_nic *efx, unsigned int cmd, size_t inlen) | |
518 | { | |
519 | if (efx->type->mcdi_max_ver < 0 || | |
520 | (efx->type->mcdi_max_ver < 2 && | |
521 | cmd > MC_CMD_CMD_SPACE_ESCAPE_7)) | |
522 | return -EINVAL; | |
523 | ||
524 | if (inlen > MCDI_CTL_SDU_LEN_MAX_V2 || | |
525 | (efx->type->mcdi_max_ver < 2 && | |
526 | inlen > MCDI_CTL_SDU_LEN_MAX_V1)) | |
527 | return -EMSGSIZE; | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
1e0b8120 EC |
532 | static int _efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen, |
533 | efx_dword_t *outbuf, size_t outlen, | |
534 | size_t *outlen_actual, bool quiet) | |
535 | { | |
536 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
537 | MCDI_DECLARE_BUF_OUT_OR_ERR(errbuf, 0); | |
538 | int rc; | |
539 | ||
540 | if (mcdi->mode == MCDI_MODE_POLL) | |
541 | rc = efx_mcdi_poll(efx); | |
542 | else | |
543 | rc = efx_mcdi_await_completion(efx); | |
544 | ||
545 | if (rc != 0) { | |
546 | netif_err(efx, hw, efx->net_dev, | |
547 | "MC command 0x%x inlen %d mode %d timed out\n", | |
548 | cmd, (int)inlen, mcdi->mode); | |
549 | ||
550 | if (mcdi->mode == MCDI_MODE_EVENTS && efx_mcdi_poll_once(efx)) { | |
551 | netif_err(efx, hw, efx->net_dev, | |
552 | "MCDI request was completed without an event\n"); | |
553 | rc = 0; | |
554 | } | |
555 | ||
e283546c EC |
556 | efx_mcdi_abandon(efx); |
557 | ||
1e0b8120 EC |
558 | /* Close the race with efx_mcdi_ev_cpl() executing just too late |
559 | * and completing a request we've just cancelled, by ensuring | |
560 | * that the seqno check therein fails. | |
561 | */ | |
562 | spin_lock_bh(&mcdi->iface_lock); | |
563 | ++mcdi->seqno; | |
564 | ++mcdi->credits; | |
565 | spin_unlock_bh(&mcdi->iface_lock); | |
566 | } | |
567 | ||
568 | if (rc != 0) { | |
569 | if (outlen_actual) | |
570 | *outlen_actual = 0; | |
571 | } else { | |
572 | size_t hdr_len, data_len, err_len; | |
573 | ||
574 | /* At the very least we need a memory barrier here to ensure | |
575 | * we pick up changes from efx_mcdi_ev_cpl(). Protect against | |
576 | * a spurious efx_mcdi_ev_cpl() running concurrently by | |
577 | * acquiring the iface_lock. */ | |
578 | spin_lock_bh(&mcdi->iface_lock); | |
579 | rc = mcdi->resprc; | |
580 | hdr_len = mcdi->resp_hdr_len; | |
581 | data_len = mcdi->resp_data_len; | |
582 | err_len = min(sizeof(errbuf), data_len); | |
583 | spin_unlock_bh(&mcdi->iface_lock); | |
584 | ||
585 | BUG_ON(rc > 0); | |
586 | ||
587 | efx->type->mcdi_read_response(efx, outbuf, hdr_len, | |
588 | min(outlen, data_len)); | |
589 | if (outlen_actual) | |
590 | *outlen_actual = data_len; | |
591 | ||
592 | efx->type->mcdi_read_response(efx, errbuf, hdr_len, err_len); | |
593 | ||
594 | if (cmd == MC_CMD_REBOOT && rc == -EIO) { | |
595 | /* Don't reset if MC_CMD_REBOOT returns EIO */ | |
596 | } else if (rc == -EIO || rc == -EINTR) { | |
597 | netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n", | |
598 | -rc); | |
599 | efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE); | |
600 | } else if (rc && !quiet) { | |
601 | efx_mcdi_display_error(efx, cmd, inlen, errbuf, err_len, | |
602 | rc); | |
603 | } | |
604 | ||
605 | if (rc == -EIO || rc == -EINTR) { | |
606 | msleep(MCDI_STATUS_SLEEP_MS); | |
607 | efx_mcdi_poll_reboot(efx); | |
608 | mcdi->new_epoch = true; | |
609 | } | |
610 | } | |
611 | ||
612 | efx_mcdi_release(mcdi); | |
613 | return rc; | |
614 | } | |
615 | ||
616 | static int _efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd, | |
617 | const efx_dword_t *inbuf, size_t inlen, | |
618 | efx_dword_t *outbuf, size_t outlen, | |
619 | size_t *outlen_actual, bool quiet) | |
620 | { | |
621 | int rc; | |
622 | ||
623 | rc = efx_mcdi_rpc_start(efx, cmd, inbuf, inlen); | |
624 | if (rc) { | |
625 | if (outlen_actual) | |
626 | *outlen_actual = 0; | |
627 | return rc; | |
628 | } | |
629 | return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen, | |
630 | outlen_actual, quiet); | |
631 | } | |
632 | ||
afd4aea0 | 633 | int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd, |
9528b921 BH |
634 | const efx_dword_t *inbuf, size_t inlen, |
635 | efx_dword_t *outbuf, size_t outlen, | |
afd4aea0 | 636 | size_t *outlen_actual) |
c3cba721 | 637 | { |
1e0b8120 EC |
638 | return _efx_mcdi_rpc(efx, cmd, inbuf, inlen, outbuf, outlen, |
639 | outlen_actual, false); | |
640 | } | |
df2cd8af | 641 | |
1e0b8120 EC |
642 | /* Normally, on receiving an error code in the MCDI response, |
643 | * efx_mcdi_rpc will log an error message containing (among other | |
644 | * things) the raw error code, by means of efx_mcdi_display_error. | |
645 | * This _quiet version suppresses that; if the caller wishes to log | |
646 | * the error conditionally on the return code, it should call this | |
647 | * function and is then responsible for calling efx_mcdi_display_error | |
648 | * as needed. | |
649 | */ | |
650 | int efx_mcdi_rpc_quiet(struct efx_nic *efx, unsigned cmd, | |
651 | const efx_dword_t *inbuf, size_t inlen, | |
652 | efx_dword_t *outbuf, size_t outlen, | |
653 | size_t *outlen_actual) | |
654 | { | |
655 | return _efx_mcdi_rpc(efx, cmd, inbuf, inlen, outbuf, outlen, | |
656 | outlen_actual, true); | |
c3cba721 SH |
657 | } |
658 | ||
df2cd8af BH |
659 | int efx_mcdi_rpc_start(struct efx_nic *efx, unsigned cmd, |
660 | const efx_dword_t *inbuf, size_t inlen) | |
afd4aea0 BH |
661 | { |
662 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
2f4bcdcc | 663 | int rc; |
c3cba721 | 664 | |
2f4bcdcc BH |
665 | rc = efx_mcdi_check_supported(efx, cmd, inlen); |
666 | if (rc) | |
667 | return rc; | |
df2cd8af | 668 | |
74cd60a4 JC |
669 | if (efx->mc_bist_for_other_fn) |
670 | return -ENETDOWN; | |
671 | ||
e283546c EC |
672 | if (mcdi->mode == MCDI_MODE_FAIL) |
673 | return -ENETDOWN; | |
674 | ||
cade715f | 675 | efx_mcdi_acquire_sync(mcdi); |
2f4bcdcc | 676 | efx_mcdi_send_request(efx, cmd, inbuf, inlen); |
df2cd8af | 677 | return 0; |
c3cba721 SH |
678 | } |
679 | ||
1e0b8120 EC |
680 | static int _efx_mcdi_rpc_async(struct efx_nic *efx, unsigned int cmd, |
681 | const efx_dword_t *inbuf, size_t inlen, | |
682 | size_t outlen, | |
683 | efx_mcdi_async_completer *complete, | |
684 | unsigned long cookie, bool quiet) | |
cade715f BH |
685 | { |
686 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
687 | struct efx_mcdi_async_param *async; | |
688 | int rc; | |
689 | ||
690 | rc = efx_mcdi_check_supported(efx, cmd, inlen); | |
691 | if (rc) | |
692 | return rc; | |
693 | ||
74cd60a4 JC |
694 | if (efx->mc_bist_for_other_fn) |
695 | return -ENETDOWN; | |
696 | ||
cade715f BH |
697 | async = kmalloc(sizeof(*async) + ALIGN(max(inlen, outlen), 4), |
698 | GFP_ATOMIC); | |
699 | if (!async) | |
700 | return -ENOMEM; | |
701 | ||
702 | async->cmd = cmd; | |
703 | async->inlen = inlen; | |
704 | async->outlen = outlen; | |
1e0b8120 | 705 | async->quiet = quiet; |
cade715f BH |
706 | async->complete = complete; |
707 | async->cookie = cookie; | |
708 | memcpy(async + 1, inbuf, inlen); | |
709 | ||
710 | spin_lock_bh(&mcdi->async_lock); | |
711 | ||
712 | if (mcdi->mode == MCDI_MODE_EVENTS) { | |
713 | list_add_tail(&async->list, &mcdi->async_list); | |
714 | ||
715 | /* If this is at the front of the queue, try to start it | |
716 | * immediately | |
717 | */ | |
718 | if (mcdi->async_list.next == &async->list && | |
719 | efx_mcdi_acquire_async(mcdi)) { | |
720 | efx_mcdi_send_request(efx, cmd, inbuf, inlen); | |
721 | mod_timer(&mcdi->async_timer, | |
722 | jiffies + MCDI_RPC_TIMEOUT); | |
723 | } | |
724 | } else { | |
725 | kfree(async); | |
726 | rc = -ENETDOWN; | |
727 | } | |
728 | ||
729 | spin_unlock_bh(&mcdi->async_lock); | |
730 | ||
731 | return rc; | |
732 | } | |
733 | ||
1e0b8120 EC |
734 | /** |
735 | * efx_mcdi_rpc_async - Schedule an MCDI command to run asynchronously | |
736 | * @efx: NIC through which to issue the command | |
737 | * @cmd: Command type number | |
738 | * @inbuf: Command parameters | |
739 | * @inlen: Length of command parameters, in bytes | |
740 | * @outlen: Length to allocate for response buffer, in bytes | |
741 | * @complete: Function to be called on completion or cancellation. | |
742 | * @cookie: Arbitrary value to be passed to @complete. | |
743 | * | |
744 | * This function does not sleep and therefore may be called in atomic | |
745 | * context. It will fail if event queues are disabled or if MCDI | |
746 | * event completions have been disabled due to an error. | |
747 | * | |
748 | * If it succeeds, the @complete function will be called exactly once | |
749 | * in atomic context, when one of the following occurs: | |
750 | * (a) the completion event is received (in NAPI context) | |
751 | * (b) event queues are disabled (in the process that disables them) | |
752 | * (c) the request times-out (in timer context) | |
753 | */ | |
754 | int | |
755 | efx_mcdi_rpc_async(struct efx_nic *efx, unsigned int cmd, | |
756 | const efx_dword_t *inbuf, size_t inlen, size_t outlen, | |
757 | efx_mcdi_async_completer *complete, unsigned long cookie) | |
758 | { | |
759 | return _efx_mcdi_rpc_async(efx, cmd, inbuf, inlen, outlen, complete, | |
760 | cookie, false); | |
761 | } | |
762 | ||
763 | int efx_mcdi_rpc_async_quiet(struct efx_nic *efx, unsigned int cmd, | |
764 | const efx_dword_t *inbuf, size_t inlen, | |
765 | size_t outlen, efx_mcdi_async_completer *complete, | |
766 | unsigned long cookie) | |
767 | { | |
768 | return _efx_mcdi_rpc_async(efx, cmd, inbuf, inlen, outlen, complete, | |
769 | cookie, true); | |
770 | } | |
771 | ||
c3cba721 | 772 | int efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen, |
9528b921 BH |
773 | efx_dword_t *outbuf, size_t outlen, |
774 | size_t *outlen_actual) | |
c3cba721 | 775 | { |
1e0b8120 EC |
776 | return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen, |
777 | outlen_actual, false); | |
778 | } | |
5bc283e5 | 779 | |
1e0b8120 EC |
780 | int efx_mcdi_rpc_finish_quiet(struct efx_nic *efx, unsigned cmd, size_t inlen, |
781 | efx_dword_t *outbuf, size_t outlen, | |
782 | size_t *outlen_actual) | |
783 | { | |
784 | return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen, | |
785 | outlen_actual, true); | |
786 | } | |
3f713bf4 | 787 | |
1e0b8120 EC |
788 | void efx_mcdi_display_error(struct efx_nic *efx, unsigned cmd, |
789 | size_t inlen, efx_dword_t *outbuf, | |
790 | size_t outlen, int rc) | |
791 | { | |
792 | int code = 0, err_arg = 0; | |
afd4aea0 | 793 | |
1e0b8120 EC |
794 | if (outlen >= MC_CMD_ERR_CODE_OFST + 4) |
795 | code = MCDI_DWORD(outbuf, ERR_CODE); | |
796 | if (outlen >= MC_CMD_ERR_ARG_OFST + 4) | |
797 | err_arg = MCDI_DWORD(outbuf, ERR_ARG); | |
798 | netif_err(efx, hw, efx->net_dev, | |
799 | "MC command 0x%x inlen %d failed rc=%d (raw=%d) arg=%d\n", | |
800 | cmd, (int)inlen, rc, code, err_arg); | |
afd4aea0 BH |
801 | } |
802 | ||
cade715f BH |
803 | /* Switch to polled MCDI completions. This can be called in various |
804 | * error conditions with various locks held, so it must be lockless. | |
805 | * Caller is responsible for flushing asynchronous requests later. | |
806 | */ | |
afd4aea0 BH |
807 | void efx_mcdi_mode_poll(struct efx_nic *efx) |
808 | { | |
809 | struct efx_mcdi_iface *mcdi; | |
810 | ||
f3ad5003 | 811 | if (!efx->mcdi) |
afd4aea0 BH |
812 | return; |
813 | ||
814 | mcdi = efx_mcdi(efx); | |
e283546c EC |
815 | /* If already in polling mode, nothing to do. |
816 | * If in fail-fast state, don't switch to polled completion. | |
817 | * FLR recovery will do that later. | |
818 | */ | |
819 | if (mcdi->mode == MCDI_MODE_POLL || mcdi->mode == MCDI_MODE_FAIL) | |
afd4aea0 BH |
820 | return; |
821 | ||
822 | /* We can switch from event completion to polled completion, because | |
823 | * mcdi requests are always completed in shared memory. We do this by | |
824 | * switching the mode to POLL'd then completing the request. | |
825 | * efx_mcdi_await_completion() will then call efx_mcdi_poll(). | |
826 | * | |
827 | * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(), | |
cade715f | 828 | * which efx_mcdi_complete_sync() provides for us. |
afd4aea0 BH |
829 | */ |
830 | mcdi->mode = MCDI_MODE_POLL; | |
831 | ||
cade715f BH |
832 | efx_mcdi_complete_sync(mcdi); |
833 | } | |
834 | ||
835 | /* Flush any running or queued asynchronous requests, after event processing | |
836 | * is stopped | |
837 | */ | |
838 | void efx_mcdi_flush_async(struct efx_nic *efx) | |
839 | { | |
840 | struct efx_mcdi_async_param *async, *next; | |
841 | struct efx_mcdi_iface *mcdi; | |
842 | ||
843 | if (!efx->mcdi) | |
844 | return; | |
845 | ||
846 | mcdi = efx_mcdi(efx); | |
847 | ||
e283546c EC |
848 | /* We must be in poll or fail mode so no more requests can be queued */ |
849 | BUG_ON(mcdi->mode == MCDI_MODE_EVENTS); | |
cade715f BH |
850 | |
851 | del_timer_sync(&mcdi->async_timer); | |
852 | ||
853 | /* If a request is still running, make sure we give the MC | |
854 | * time to complete it so that the response won't overwrite our | |
855 | * next request. | |
856 | */ | |
857 | if (mcdi->state == MCDI_STATE_RUNNING_ASYNC) { | |
858 | efx_mcdi_poll(efx); | |
859 | mcdi->state = MCDI_STATE_QUIESCENT; | |
860 | } | |
861 | ||
862 | /* Nothing else will access the async list now, so it is safe | |
863 | * to walk it without holding async_lock. If we hold it while | |
864 | * calling a completer then lockdep may warn that we have | |
865 | * acquired locks in the wrong order. | |
866 | */ | |
867 | list_for_each_entry_safe(async, next, &mcdi->async_list, list) { | |
868 | async->complete(efx, async->cookie, -ENETDOWN, NULL, 0); | |
869 | list_del(&async->list); | |
870 | kfree(async); | |
871 | } | |
afd4aea0 BH |
872 | } |
873 | ||
874 | void efx_mcdi_mode_event(struct efx_nic *efx) | |
875 | { | |
876 | struct efx_mcdi_iface *mcdi; | |
877 | ||
f3ad5003 | 878 | if (!efx->mcdi) |
afd4aea0 BH |
879 | return; |
880 | ||
881 | mcdi = efx_mcdi(efx); | |
e283546c EC |
882 | /* If already in event completion mode, nothing to do. |
883 | * If in fail-fast state, don't switch to event completion. FLR | |
884 | * recovery will do that later. | |
885 | */ | |
886 | if (mcdi->mode == MCDI_MODE_EVENTS || mcdi->mode == MCDI_MODE_FAIL) | |
afd4aea0 BH |
887 | return; |
888 | ||
889 | /* We can't switch from polled to event completion in the middle of a | |
890 | * request, because the completion method is specified in the request. | |
891 | * So acquire the interface to serialise the requestors. We don't need | |
892 | * to acquire the iface_lock to change the mode here, but we do need a | |
893 | * write memory barrier ensure that efx_mcdi_rpc() sees it, which | |
894 | * efx_mcdi_acquire() provides. | |
895 | */ | |
cade715f | 896 | efx_mcdi_acquire_sync(mcdi); |
afd4aea0 BH |
897 | mcdi->mode = MCDI_MODE_EVENTS; |
898 | efx_mcdi_release(mcdi); | |
899 | } | |
900 | ||
901 | static void efx_mcdi_ev_death(struct efx_nic *efx, int rc) | |
902 | { | |
903 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
904 | ||
905 | /* If there is an outstanding MCDI request, it has been terminated | |
906 | * either by a BADASSERT or REBOOT event. If the mcdi interface is | |
907 | * in polled mode, then do nothing because the MC reboot handler will | |
908 | * set the header correctly. However, if the mcdi interface is waiting | |
909 | * for a CMDDONE event it won't receive it [and since all MCDI events | |
910 | * are sent to the same queue, we can't be racing with | |
911 | * efx_mcdi_ev_cpl()] | |
912 | * | |
cade715f BH |
913 | * If there is an outstanding asynchronous request, we can't |
914 | * complete it now (efx_mcdi_complete() would deadlock). The | |
915 | * reset process will take care of this. | |
916 | * | |
917 | * There's a race here with efx_mcdi_send_request(), because | |
918 | * we might receive a REBOOT event *before* the request has | |
919 | * been copied out. In polled mode (during startup) this is | |
920 | * irrelevant, because efx_mcdi_complete_sync() is ignored. In | |
921 | * event mode, this condition is just an edge-case of | |
922 | * receiving a REBOOT event after posting the MCDI | |
923 | * request. Did the mc reboot before or after the copyout? The | |
924 | * best we can do always is just return failure. | |
afd4aea0 BH |
925 | */ |
926 | spin_lock(&mcdi->iface_lock); | |
cade715f | 927 | if (efx_mcdi_complete_sync(mcdi)) { |
afd4aea0 BH |
928 | if (mcdi->mode == MCDI_MODE_EVENTS) { |
929 | mcdi->resprc = rc; | |
df2cd8af BH |
930 | mcdi->resp_hdr_len = 0; |
931 | mcdi->resp_data_len = 0; | |
18e3ee2c | 932 | ++mcdi->credits; |
afd4aea0 | 933 | } |
3f713bf4 BH |
934 | } else { |
935 | int count; | |
936 | ||
3f713bf4 BH |
937 | /* Consume the status word since efx_mcdi_rpc_finish() won't */ |
938 | for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) { | |
939 | if (efx_mcdi_poll_reboot(efx)) | |
940 | break; | |
941 | udelay(MCDI_STATUS_DELAY_US); | |
942 | } | |
d36a08b4 | 943 | mcdi->new_epoch = true; |
dfdaa95c DP |
944 | |
945 | /* Nobody was waiting for an MCDI request, so trigger a reset */ | |
946 | efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE); | |
3f713bf4 BH |
947 | } |
948 | ||
afd4aea0 BH |
949 | spin_unlock(&mcdi->iface_lock); |
950 | } | |
951 | ||
74cd60a4 JC |
952 | /* The MC is going down in to BIST mode. set the BIST flag to block |
953 | * new MCDI, cancel any outstanding MCDI and and schedule a BIST-type reset | |
954 | * (which doesn't actually execute a reset, it waits for the controlling | |
955 | * function to reset it). | |
956 | */ | |
957 | static void efx_mcdi_ev_bist(struct efx_nic *efx) | |
958 | { | |
959 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
960 | ||
961 | spin_lock(&mcdi->iface_lock); | |
962 | efx->mc_bist_for_other_fn = true; | |
963 | if (efx_mcdi_complete_sync(mcdi)) { | |
964 | if (mcdi->mode == MCDI_MODE_EVENTS) { | |
965 | mcdi->resprc = -EIO; | |
966 | mcdi->resp_hdr_len = 0; | |
967 | mcdi->resp_data_len = 0; | |
968 | ++mcdi->credits; | |
969 | } | |
970 | } | |
971 | mcdi->new_epoch = true; | |
972 | efx_schedule_reset(efx, RESET_TYPE_MC_BIST); | |
973 | spin_unlock(&mcdi->iface_lock); | |
974 | } | |
975 | ||
e283546c EC |
976 | /* MCDI timeouts seen, so make all MCDI calls fail-fast and issue an FLR to try |
977 | * to recover. | |
978 | */ | |
979 | static void efx_mcdi_abandon(struct efx_nic *efx) | |
980 | { | |
981 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
982 | ||
983 | if (xchg(&mcdi->mode, MCDI_MODE_FAIL) == MCDI_MODE_FAIL) | |
984 | return; /* it had already been done */ | |
985 | netif_dbg(efx, hw, efx->net_dev, "MCDI is timing out; trying to recover\n"); | |
986 | efx_schedule_reset(efx, RESET_TYPE_MCDI_TIMEOUT); | |
987 | } | |
988 | ||
afd4aea0 BH |
989 | /* Called from falcon_process_eventq for MCDI events */ |
990 | void efx_mcdi_process_event(struct efx_channel *channel, | |
991 | efx_qword_t *event) | |
992 | { | |
993 | struct efx_nic *efx = channel->efx; | |
994 | int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE); | |
995 | u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA); | |
996 | ||
997 | switch (code) { | |
998 | case MCDI_EVENT_CODE_BADSSERT: | |
62776d03 BH |
999 | netif_err(efx, hw, efx->net_dev, |
1000 | "MC watchdog or assertion failure at 0x%x\n", data); | |
5bc283e5 | 1001 | efx_mcdi_ev_death(efx, -EINTR); |
afd4aea0 BH |
1002 | break; |
1003 | ||
1004 | case MCDI_EVENT_CODE_PMNOTICE: | |
62776d03 | 1005 | netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n"); |
afd4aea0 BH |
1006 | break; |
1007 | ||
1008 | case MCDI_EVENT_CODE_CMDDONE: | |
1009 | efx_mcdi_ev_cpl(efx, | |
1010 | MCDI_EVENT_FIELD(*event, CMDDONE_SEQ), | |
1011 | MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN), | |
1012 | MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO)); | |
1013 | break; | |
1014 | ||
1015 | case MCDI_EVENT_CODE_LINKCHANGE: | |
1016 | efx_mcdi_process_link_change(efx, event); | |
1017 | break; | |
1018 | case MCDI_EVENT_CODE_SENSOREVT: | |
1019 | efx_mcdi_sensor_event(efx, event); | |
1020 | break; | |
1021 | case MCDI_EVENT_CODE_SCHEDERR: | |
2d9955be RS |
1022 | netif_dbg(efx, hw, efx->net_dev, |
1023 | "MC Scheduler alert (0x%x)\n", data); | |
afd4aea0 BH |
1024 | break; |
1025 | case MCDI_EVENT_CODE_REBOOT: | |
8127d661 | 1026 | case MCDI_EVENT_CODE_MC_REBOOT: |
62776d03 | 1027 | netif_info(efx, hw, efx->net_dev, "MC Reboot\n"); |
5bc283e5 | 1028 | efx_mcdi_ev_death(efx, -EIO); |
afd4aea0 | 1029 | break; |
74cd60a4 JC |
1030 | case MCDI_EVENT_CODE_MC_BIST: |
1031 | netif_info(efx, hw, efx->net_dev, "MC entered BIST mode\n"); | |
1032 | efx_mcdi_ev_bist(efx); | |
1033 | break; | |
afd4aea0 BH |
1034 | case MCDI_EVENT_CODE_MAC_STATS_DMA: |
1035 | /* MAC stats are gather lazily. We can ignore this. */ | |
1036 | break; | |
cd2d5b52 BH |
1037 | case MCDI_EVENT_CODE_FLR: |
1038 | efx_sriov_flr(efx, MCDI_EVENT_FIELD(*event, FLR_VF)); | |
1039 | break; | |
7c236c43 SH |
1040 | case MCDI_EVENT_CODE_PTP_RX: |
1041 | case MCDI_EVENT_CODE_PTP_FAULT: | |
1042 | case MCDI_EVENT_CODE_PTP_PPS: | |
1043 | efx_ptp_event(efx, event); | |
1044 | break; | |
bd9a265d JC |
1045 | case MCDI_EVENT_CODE_PTP_TIME: |
1046 | efx_time_sync_event(channel, event); | |
1047 | break; | |
8127d661 BH |
1048 | case MCDI_EVENT_CODE_TX_FLUSH: |
1049 | case MCDI_EVENT_CODE_RX_FLUSH: | |
1050 | /* Two flush events will be sent: one to the same event | |
1051 | * queue as completions, and one to event queue 0. | |
1052 | * In the latter case the {RX,TX}_FLUSH_TO_DRIVER | |
1053 | * flag will be set, and we should ignore the event | |
1054 | * because we want to wait for all completions. | |
1055 | */ | |
1056 | BUILD_BUG_ON(MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN != | |
1057 | MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN); | |
1058 | if (!MCDI_EVENT_FIELD(*event, TX_FLUSH_TO_DRIVER)) | |
1059 | efx_ef10_handle_drain_event(efx); | |
1060 | break; | |
3de82b91 AR |
1061 | case MCDI_EVENT_CODE_TX_ERR: |
1062 | case MCDI_EVENT_CODE_RX_ERR: | |
1063 | netif_err(efx, hw, efx->net_dev, | |
1064 | "%s DMA error (event: "EFX_QWORD_FMT")\n", | |
1065 | code == MCDI_EVENT_CODE_TX_ERR ? "TX" : "RX", | |
1066 | EFX_QWORD_VAL(*event)); | |
1067 | efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR); | |
1068 | break; | |
afd4aea0 | 1069 | default: |
62776d03 BH |
1070 | netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n", |
1071 | code); | |
afd4aea0 BH |
1072 | } |
1073 | } | |
1074 | ||
1075 | /************************************************************************** | |
1076 | * | |
1077 | * Specific request functions | |
1078 | * | |
1079 | ************************************************************************** | |
1080 | */ | |
1081 | ||
e5f0fd27 | 1082 | void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len) |
afd4aea0 | 1083 | { |
8127d661 BH |
1084 | MCDI_DECLARE_BUF(outbuf, |
1085 | max(MC_CMD_GET_VERSION_OUT_LEN, | |
1086 | MC_CMD_GET_CAPABILITIES_OUT_LEN)); | |
afd4aea0 BH |
1087 | size_t outlength; |
1088 | const __le16 *ver_words; | |
8127d661 | 1089 | size_t offset; |
afd4aea0 BH |
1090 | int rc; |
1091 | ||
1092 | BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0); | |
afd4aea0 BH |
1093 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0, |
1094 | outbuf, sizeof(outbuf), &outlength); | |
1095 | if (rc) | |
1096 | goto fail; | |
05a9320f | 1097 | if (outlength < MC_CMD_GET_VERSION_OUT_LEN) { |
00bbb4a5 | 1098 | rc = -EIO; |
afd4aea0 BH |
1099 | goto fail; |
1100 | } | |
1101 | ||
1102 | ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION); | |
8127d661 BH |
1103 | offset = snprintf(buf, len, "%u.%u.%u.%u", |
1104 | le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]), | |
1105 | le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3])); | |
1106 | ||
1107 | /* EF10 may have multiple datapath firmware variants within a | |
1108 | * single version. Report which variants are running. | |
1109 | */ | |
1110 | if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) { | |
1111 | BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); | |
1112 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, | |
1113 | outbuf, sizeof(outbuf), &outlength); | |
1114 | if (rc || outlength < MC_CMD_GET_CAPABILITIES_OUT_LEN) | |
1115 | offset += snprintf( | |
1116 | buf + offset, len - offset, " rx? tx?"); | |
1117 | else | |
1118 | offset += snprintf( | |
1119 | buf + offset, len - offset, " rx%x tx%x", | |
1120 | MCDI_WORD(outbuf, | |
1121 | GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID), | |
1122 | MCDI_WORD(outbuf, | |
1123 | GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID)); | |
1124 | ||
1125 | /* It's theoretically possible for the string to exceed 31 | |
1126 | * characters, though in practice the first three version | |
1127 | * components are short enough that this doesn't happen. | |
1128 | */ | |
1129 | if (WARN_ON(offset >= len)) | |
1130 | buf[0] = 0; | |
1131 | } | |
1132 | ||
e5f0fd27 | 1133 | return; |
afd4aea0 BH |
1134 | |
1135 | fail: | |
62776d03 | 1136 | netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
e5f0fd27 | 1137 | buf[0] = 0; |
afd4aea0 BH |
1138 | } |
1139 | ||
4c75b43a BH |
1140 | static int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating, |
1141 | bool *was_attached) | |
afd4aea0 | 1142 | { |
59cfc479 | 1143 | MCDI_DECLARE_BUF(inbuf, MC_CMD_DRV_ATTACH_IN_LEN); |
ecb1c9cc | 1144 | MCDI_DECLARE_BUF(outbuf, MC_CMD_DRV_ATTACH_EXT_OUT_LEN); |
afd4aea0 BH |
1145 | size_t outlen; |
1146 | int rc; | |
1147 | ||
1148 | MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE, | |
1149 | driver_operating ? 1 : 0); | |
1150 | MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1); | |
f2b0befd | 1151 | MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_FIRMWARE_ID, MC_CMD_FW_LOW_LATENCY); |
afd4aea0 BH |
1152 | |
1153 | rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf), | |
1154 | outbuf, sizeof(outbuf), &outlen); | |
1155 | if (rc) | |
1156 | goto fail; | |
00bbb4a5 BH |
1157 | if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) { |
1158 | rc = -EIO; | |
afd4aea0 | 1159 | goto fail; |
00bbb4a5 | 1160 | } |
afd4aea0 | 1161 | |
8349f7f6 BH |
1162 | if (driver_operating) { |
1163 | if (outlen >= MC_CMD_DRV_ATTACH_EXT_OUT_LEN) { | |
1164 | efx->mcdi->fn_flags = | |
1165 | MCDI_DWORD(outbuf, | |
1166 | DRV_ATTACH_EXT_OUT_FUNC_FLAGS); | |
1167 | } else { | |
1168 | /* Synthesise flags for Siena */ | |
1169 | efx->mcdi->fn_flags = | |
1170 | 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL | | |
1171 | 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED | | |
1172 | (efx_port_num(efx) == 0) << | |
1173 | MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY; | |
1174 | } | |
1175 | } | |
1176 | ||
ecb1c9cc BH |
1177 | /* We currently assume we have control of the external link |
1178 | * and are completely trusted by firmware. Abort probing | |
1179 | * if that's not true for this function. | |
1180 | */ | |
1181 | if (driver_operating && | |
8349f7f6 | 1182 | (efx->mcdi->fn_flags & |
ecb1c9cc BH |
1183 | (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL | |
1184 | 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) != | |
1185 | (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL | | |
1186 | 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) { | |
1187 | netif_err(efx, probe, efx->net_dev, | |
1188 | "This driver version only supports one function per port\n"); | |
1189 | return -ENODEV; | |
1190 | } | |
1191 | ||
afd4aea0 BH |
1192 | if (was_attached != NULL) |
1193 | *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE); | |
1194 | return 0; | |
1195 | ||
1196 | fail: | |
62776d03 | 1197 | netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1198 | return rc; |
1199 | } | |
1200 | ||
1201 | int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address, | |
6aa9c7f6 | 1202 | u16 *fw_subtype_list, u32 *capabilities) |
afd4aea0 | 1203 | { |
59cfc479 | 1204 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_BOARD_CFG_OUT_LENMAX); |
c5bb0e98 | 1205 | size_t outlen, i; |
afd4aea0 | 1206 | int port_num = efx_port_num(efx); |
afd4aea0 BH |
1207 | int rc; |
1208 | ||
1209 | BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0); | |
cd84ff4d EC |
1210 | /* we need __aligned(2) for ether_addr_copy */ |
1211 | BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST & 1); | |
1212 | BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST & 1); | |
afd4aea0 BH |
1213 | |
1214 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0, | |
1215 | outbuf, sizeof(outbuf), &outlen); | |
1216 | if (rc) | |
1217 | goto fail; | |
1218 | ||
05a9320f | 1219 | if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) { |
00bbb4a5 | 1220 | rc = -EIO; |
afd4aea0 BH |
1221 | goto fail; |
1222 | } | |
1223 | ||
afd4aea0 | 1224 | if (mac_address) |
cd84ff4d EC |
1225 | ether_addr_copy(mac_address, |
1226 | port_num ? | |
1227 | MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1) : | |
1228 | MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0)); | |
bfeed902 | 1229 | if (fw_subtype_list) { |
bfeed902 | 1230 | for (i = 0; |
c5bb0e98 BH |
1231 | i < MCDI_VAR_ARRAY_LEN(outlen, |
1232 | GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST); | |
1233 | i++) | |
1234 | fw_subtype_list[i] = MCDI_ARRAY_WORD( | |
1235 | outbuf, GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST, i); | |
1236 | for (; i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM; i++) | |
1237 | fw_subtype_list[i] = 0; | |
bfeed902 | 1238 | } |
6aa9c7f6 MS |
1239 | if (capabilities) { |
1240 | if (port_num) | |
1241 | *capabilities = MCDI_DWORD(outbuf, | |
1242 | GET_BOARD_CFG_OUT_CAPABILITIES_PORT1); | |
1243 | else | |
1244 | *capabilities = MCDI_DWORD(outbuf, | |
1245 | GET_BOARD_CFG_OUT_CAPABILITIES_PORT0); | |
1246 | } | |
afd4aea0 BH |
1247 | |
1248 | return 0; | |
1249 | ||
1250 | fail: | |
62776d03 BH |
1251 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n", |
1252 | __func__, rc, (int)outlen); | |
afd4aea0 BH |
1253 | |
1254 | return rc; | |
1255 | } | |
1256 | ||
1257 | int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq) | |
1258 | { | |
59cfc479 | 1259 | MCDI_DECLARE_BUF(inbuf, MC_CMD_LOG_CTRL_IN_LEN); |
afd4aea0 BH |
1260 | u32 dest = 0; |
1261 | int rc; | |
1262 | ||
1263 | if (uart) | |
1264 | dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART; | |
1265 | if (evq) | |
1266 | dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ; | |
1267 | ||
1268 | MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest); | |
1269 | MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq); | |
1270 | ||
1271 | BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0); | |
1272 | ||
1273 | rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf), | |
1274 | NULL, 0, NULL); | |
afd4aea0 BH |
1275 | return rc; |
1276 | } | |
1277 | ||
1278 | int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out) | |
1279 | { | |
59cfc479 | 1280 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TYPES_OUT_LEN); |
afd4aea0 BH |
1281 | size_t outlen; |
1282 | int rc; | |
1283 | ||
1284 | BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0); | |
1285 | ||
1286 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0, | |
1287 | outbuf, sizeof(outbuf), &outlen); | |
1288 | if (rc) | |
1289 | goto fail; | |
00bbb4a5 BH |
1290 | if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) { |
1291 | rc = -EIO; | |
afd4aea0 | 1292 | goto fail; |
00bbb4a5 | 1293 | } |
afd4aea0 BH |
1294 | |
1295 | *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES); | |
1296 | return 0; | |
1297 | ||
1298 | fail: | |
62776d03 BH |
1299 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", |
1300 | __func__, rc); | |
afd4aea0 BH |
1301 | return rc; |
1302 | } | |
1303 | ||
1304 | int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type, | |
1305 | size_t *size_out, size_t *erase_size_out, | |
1306 | bool *protected_out) | |
1307 | { | |
59cfc479 BH |
1308 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_INFO_IN_LEN); |
1309 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_INFO_OUT_LEN); | |
afd4aea0 BH |
1310 | size_t outlen; |
1311 | int rc; | |
1312 | ||
1313 | MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type); | |
1314 | ||
1315 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf), | |
1316 | outbuf, sizeof(outbuf), &outlen); | |
1317 | if (rc) | |
1318 | goto fail; | |
00bbb4a5 BH |
1319 | if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) { |
1320 | rc = -EIO; | |
afd4aea0 | 1321 | goto fail; |
00bbb4a5 | 1322 | } |
afd4aea0 BH |
1323 | |
1324 | *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE); | |
1325 | *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE); | |
1326 | *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) & | |
05a9320f | 1327 | (1 << MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN)); |
afd4aea0 BH |
1328 | return 0; |
1329 | ||
1330 | fail: | |
62776d03 | 1331 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1332 | return rc; |
1333 | } | |
1334 | ||
2e803407 BH |
1335 | static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type) |
1336 | { | |
59cfc479 BH |
1337 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_TEST_IN_LEN); |
1338 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TEST_OUT_LEN); | |
2e803407 BH |
1339 | int rc; |
1340 | ||
1341 | MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type); | |
1342 | ||
1343 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf), | |
1344 | outbuf, sizeof(outbuf), NULL); | |
1345 | if (rc) | |
1346 | return rc; | |
1347 | ||
1348 | switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) { | |
1349 | case MC_CMD_NVRAM_TEST_PASS: | |
1350 | case MC_CMD_NVRAM_TEST_NOTSUPP: | |
1351 | return 0; | |
1352 | default: | |
1353 | return -EIO; | |
1354 | } | |
1355 | } | |
1356 | ||
1357 | int efx_mcdi_nvram_test_all(struct efx_nic *efx) | |
1358 | { | |
1359 | u32 nvram_types; | |
1360 | unsigned int type; | |
1361 | int rc; | |
1362 | ||
1363 | rc = efx_mcdi_nvram_types(efx, &nvram_types); | |
1364 | if (rc) | |
b548a988 | 1365 | goto fail1; |
2e803407 BH |
1366 | |
1367 | type = 0; | |
1368 | while (nvram_types != 0) { | |
1369 | if (nvram_types & 1) { | |
1370 | rc = efx_mcdi_nvram_test(efx, type); | |
1371 | if (rc) | |
b548a988 | 1372 | goto fail2; |
2e803407 BH |
1373 | } |
1374 | type++; | |
1375 | nvram_types >>= 1; | |
1376 | } | |
1377 | ||
1378 | return 0; | |
b548a988 BH |
1379 | |
1380 | fail2: | |
62776d03 BH |
1381 | netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n", |
1382 | __func__, type); | |
b548a988 | 1383 | fail1: |
62776d03 | 1384 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
b548a988 | 1385 | return rc; |
2e803407 BH |
1386 | } |
1387 | ||
8b2103ad | 1388 | static int efx_mcdi_read_assertion(struct efx_nic *efx) |
afd4aea0 | 1389 | { |
59cfc479 | 1390 | MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_ASSERTS_IN_LEN); |
1e0b8120 | 1391 | MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, MC_CMD_GET_ASSERTS_OUT_LEN); |
c5bb0e98 | 1392 | unsigned int flags, index; |
afd4aea0 BH |
1393 | const char *reason; |
1394 | size_t outlen; | |
1395 | int retry; | |
1396 | int rc; | |
1397 | ||
8b2103ad SH |
1398 | /* Attempt to read any stored assertion state before we reboot |
1399 | * the mcfw out of the assertion handler. Retry twice, once | |
afd4aea0 BH |
1400 | * because a boot-time assertion might cause this command to fail |
1401 | * with EINTR. And once again because GET_ASSERTS can race with | |
1402 | * MC_CMD_REBOOT running on the other port. */ | |
1403 | retry = 2; | |
1404 | do { | |
8b2103ad | 1405 | MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1); |
1e0b8120 EC |
1406 | rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_ASSERTS, |
1407 | inbuf, MC_CMD_GET_ASSERTS_IN_LEN, | |
1408 | outbuf, sizeof(outbuf), &outlen); | |
afd4aea0 BH |
1409 | } while ((rc == -EINTR || rc == -EIO) && retry-- > 0); |
1410 | ||
1e0b8120 EC |
1411 | if (rc) { |
1412 | efx_mcdi_display_error(efx, MC_CMD_GET_ASSERTS, | |
1413 | MC_CMD_GET_ASSERTS_IN_LEN, outbuf, | |
1414 | outlen, rc); | |
afd4aea0 | 1415 | return rc; |
1e0b8120 | 1416 | } |
afd4aea0 | 1417 | if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN) |
00bbb4a5 | 1418 | return -EIO; |
afd4aea0 | 1419 | |
8b2103ad SH |
1420 | /* Print out any recorded assertion state */ |
1421 | flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS); | |
afd4aea0 BH |
1422 | if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS) |
1423 | return 0; | |
1424 | ||
afd4aea0 BH |
1425 | reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL) |
1426 | ? "system-level assertion" | |
1427 | : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL) | |
1428 | ? "thread-level assertion" | |
1429 | : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED) | |
1430 | ? "watchdog reset" | |
1431 | : "unknown assertion"; | |
62776d03 BH |
1432 | netif_err(efx, hw, efx->net_dev, |
1433 | "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason, | |
1434 | MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS), | |
1435 | MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS)); | |
afd4aea0 BH |
1436 | |
1437 | /* Print out the registers */ | |
c5bb0e98 BH |
1438 | for (index = 0; |
1439 | index < MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM; | |
1440 | index++) | |
1441 | netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", | |
1442 | 1 + index, | |
1443 | MCDI_ARRAY_DWORD(outbuf, GET_ASSERTS_OUT_GP_REGS_OFFS, | |
1444 | index)); | |
afd4aea0 BH |
1445 | |
1446 | return 0; | |
1447 | } | |
1448 | ||
8b2103ad SH |
1449 | static void efx_mcdi_exit_assertion(struct efx_nic *efx) |
1450 | { | |
59cfc479 | 1451 | MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN); |
8b2103ad | 1452 | |
0f1e54ae BH |
1453 | /* If the MC is running debug firmware, it might now be |
1454 | * waiting for a debugger to attach, but we just want it to | |
1455 | * reboot. We set a flag that makes the command a no-op if it | |
1456 | * has already done so. We don't know what return code to | |
1457 | * expect (0 or -EIO), so ignore it. | |
1458 | */ | |
8b2103ad SH |
1459 | BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0); |
1460 | MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, | |
1461 | MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION); | |
0f1e54ae BH |
1462 | (void) efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN, |
1463 | NULL, 0, NULL); | |
8b2103ad SH |
1464 | } |
1465 | ||
1466 | int efx_mcdi_handle_assertion(struct efx_nic *efx) | |
1467 | { | |
1468 | int rc; | |
1469 | ||
1470 | rc = efx_mcdi_read_assertion(efx); | |
1471 | if (rc) | |
1472 | return rc; | |
1473 | ||
1474 | efx_mcdi_exit_assertion(efx); | |
1475 | ||
1476 | return 0; | |
1477 | } | |
1478 | ||
afd4aea0 BH |
1479 | void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1480 | { | |
59cfc479 | 1481 | MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_ID_LED_IN_LEN); |
afd4aea0 BH |
1482 | int rc; |
1483 | ||
1484 | BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF); | |
1485 | BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON); | |
1486 | BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT); | |
1487 | ||
1488 | BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0); | |
1489 | ||
1490 | MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode); | |
1491 | ||
1492 | rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf), | |
1493 | NULL, 0, NULL); | |
afd4aea0 BH |
1494 | } |
1495 | ||
3e336261 | 1496 | static int efx_mcdi_reset_func(struct efx_nic *efx) |
afd4aea0 | 1497 | { |
3e336261 JC |
1498 | MCDI_DECLARE_BUF(inbuf, MC_CMD_ENTITY_RESET_IN_LEN); |
1499 | int rc; | |
1500 | ||
1501 | BUILD_BUG_ON(MC_CMD_ENTITY_RESET_OUT_LEN != 0); | |
1502 | MCDI_POPULATE_DWORD_1(inbuf, ENTITY_RESET_IN_FLAG, | |
1503 | ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1); | |
1504 | rc = efx_mcdi_rpc(efx, MC_CMD_ENTITY_RESET, inbuf, sizeof(inbuf), | |
1505 | NULL, 0, NULL); | |
1506 | return rc; | |
afd4aea0 BH |
1507 | } |
1508 | ||
6bff861d | 1509 | static int efx_mcdi_reset_mc(struct efx_nic *efx) |
afd4aea0 | 1510 | { |
59cfc479 | 1511 | MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN); |
afd4aea0 BH |
1512 | int rc; |
1513 | ||
1514 | BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0); | |
1515 | MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0); | |
1516 | rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf), | |
1517 | NULL, 0, NULL); | |
1518 | /* White is black, and up is down */ | |
1519 | if (rc == -EIO) | |
1520 | return 0; | |
1521 | if (rc == 0) | |
1522 | rc = -EIO; | |
afd4aea0 BH |
1523 | return rc; |
1524 | } | |
1525 | ||
6bff861d BH |
1526 | enum reset_type efx_mcdi_map_reset_reason(enum reset_type reason) |
1527 | { | |
1528 | return RESET_TYPE_RECOVER_OR_ALL; | |
1529 | } | |
1530 | ||
1531 | int efx_mcdi_reset(struct efx_nic *efx, enum reset_type method) | |
1532 | { | |
1533 | int rc; | |
1534 | ||
e283546c EC |
1535 | /* If MCDI is down, we can't handle_assertion */ |
1536 | if (method == RESET_TYPE_MCDI_TIMEOUT) { | |
1537 | rc = pci_reset_function(efx->pci_dev); | |
1538 | if (rc) | |
1539 | return rc; | |
1540 | /* Re-enable polled MCDI completion */ | |
1541 | if (efx->mcdi) { | |
1542 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
1543 | mcdi->mode = MCDI_MODE_POLL; | |
1544 | } | |
1545 | return 0; | |
1546 | } | |
1547 | ||
6bff861d BH |
1548 | /* Recover from a failed assertion pre-reset */ |
1549 | rc = efx_mcdi_handle_assertion(efx); | |
1550 | if (rc) | |
1551 | return rc; | |
1552 | ||
1553 | if (method == RESET_TYPE_WORLD) | |
1554 | return efx_mcdi_reset_mc(efx); | |
1555 | else | |
3e336261 | 1556 | return efx_mcdi_reset_func(efx); |
6bff861d BH |
1557 | } |
1558 | ||
d215697f | 1559 | static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type, |
1560 | const u8 *mac, int *id_out) | |
afd4aea0 | 1561 | { |
59cfc479 BH |
1562 | MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_SET_IN_LEN); |
1563 | MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_SET_OUT_LEN); | |
afd4aea0 BH |
1564 | size_t outlen; |
1565 | int rc; | |
1566 | ||
1567 | MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type); | |
1568 | MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE, | |
1569 | MC_CMD_FILTER_MODE_SIMPLE); | |
cd84ff4d | 1570 | ether_addr_copy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac); |
afd4aea0 BH |
1571 | |
1572 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf), | |
1573 | outbuf, sizeof(outbuf), &outlen); | |
1574 | if (rc) | |
1575 | goto fail; | |
1576 | ||
1577 | if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) { | |
00bbb4a5 | 1578 | rc = -EIO; |
afd4aea0 BH |
1579 | goto fail; |
1580 | } | |
1581 | ||
1582 | *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID); | |
1583 | ||
1584 | return 0; | |
1585 | ||
1586 | fail: | |
1587 | *id_out = -1; | |
62776d03 | 1588 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1589 | return rc; |
1590 | ||
1591 | } | |
1592 | ||
1593 | ||
1594 | int | |
1595 | efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out) | |
1596 | { | |
1597 | return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out); | |
1598 | } | |
1599 | ||
1600 | ||
1601 | int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out) | |
1602 | { | |
59cfc479 | 1603 | MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_GET_OUT_LEN); |
afd4aea0 BH |
1604 | size_t outlen; |
1605 | int rc; | |
1606 | ||
1607 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0, | |
1608 | outbuf, sizeof(outbuf), &outlen); | |
1609 | if (rc) | |
1610 | goto fail; | |
1611 | ||
1612 | if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) { | |
00bbb4a5 | 1613 | rc = -EIO; |
afd4aea0 BH |
1614 | goto fail; |
1615 | } | |
1616 | ||
1617 | *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID); | |
1618 | ||
1619 | return 0; | |
1620 | ||
1621 | fail: | |
1622 | *id_out = -1; | |
62776d03 | 1623 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1624 | return rc; |
1625 | } | |
1626 | ||
1627 | ||
1628 | int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id) | |
1629 | { | |
59cfc479 | 1630 | MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_REMOVE_IN_LEN); |
afd4aea0 BH |
1631 | int rc; |
1632 | ||
1633 | MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id); | |
1634 | ||
1635 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf), | |
1636 | NULL, 0, NULL); | |
afd4aea0 BH |
1637 | return rc; |
1638 | } | |
1639 | ||
cd2d5b52 BH |
1640 | int efx_mcdi_flush_rxqs(struct efx_nic *efx) |
1641 | { | |
1642 | struct efx_channel *channel; | |
1643 | struct efx_rx_queue *rx_queue; | |
c5bb0e98 BH |
1644 | MCDI_DECLARE_BUF(inbuf, |
1645 | MC_CMD_FLUSH_RX_QUEUES_IN_LEN(EFX_MAX_CHANNELS)); | |
cd2d5b52 BH |
1646 | int rc, count; |
1647 | ||
45078374 BH |
1648 | BUILD_BUG_ON(EFX_MAX_CHANNELS > |
1649 | MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM); | |
1650 | ||
cd2d5b52 BH |
1651 | count = 0; |
1652 | efx_for_each_channel(channel, efx) { | |
1653 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
1654 | if (rx_queue->flush_pending) { | |
1655 | rx_queue->flush_pending = false; | |
1656 | atomic_dec(&efx->rxq_flush_pending); | |
c5bb0e98 BH |
1657 | MCDI_SET_ARRAY_DWORD( |
1658 | inbuf, FLUSH_RX_QUEUES_IN_QID_OFST, | |
1659 | count, efx_rx_queue_index(rx_queue)); | |
1660 | count++; | |
cd2d5b52 BH |
1661 | } |
1662 | } | |
1663 | } | |
1664 | ||
c5bb0e98 BH |
1665 | rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf, |
1666 | MC_CMD_FLUSH_RX_QUEUES_IN_LEN(count), NULL, 0, NULL); | |
bbec969b | 1667 | WARN_ON(rc < 0); |
cd2d5b52 | 1668 | |
cd2d5b52 BH |
1669 | return rc; |
1670 | } | |
afd4aea0 BH |
1671 | |
1672 | int efx_mcdi_wol_filter_reset(struct efx_nic *efx) | |
1673 | { | |
1674 | int rc; | |
1675 | ||
1676 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL); | |
afd4aea0 BH |
1677 | return rc; |
1678 | } | |
1679 | ||
8127d661 BH |
1680 | int efx_mcdi_set_workaround(struct efx_nic *efx, u32 type, bool enabled) |
1681 | { | |
1682 | MCDI_DECLARE_BUF(inbuf, MC_CMD_WORKAROUND_IN_LEN); | |
1683 | ||
1684 | BUILD_BUG_ON(MC_CMD_WORKAROUND_OUT_LEN != 0); | |
1685 | MCDI_SET_DWORD(inbuf, WORKAROUND_IN_TYPE, type); | |
1686 | MCDI_SET_DWORD(inbuf, WORKAROUND_IN_ENABLED, enabled); | |
1687 | return efx_mcdi_rpc(efx, MC_CMD_WORKAROUND, inbuf, sizeof(inbuf), | |
1688 | NULL, 0, NULL); | |
1689 | } | |
1690 | ||
45a3fd55 BH |
1691 | #ifdef CONFIG_SFC_MTD |
1692 | ||
1693 | #define EFX_MCDI_NVRAM_LEN_MAX 128 | |
1694 | ||
1695 | static int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type) | |
1696 | { | |
1697 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_START_IN_LEN); | |
1698 | int rc; | |
1699 | ||
1700 | MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type); | |
1701 | ||
1702 | BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0); | |
1703 | ||
1704 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf), | |
1705 | NULL, 0, NULL); | |
45a3fd55 BH |
1706 | return rc; |
1707 | } | |
1708 | ||
1709 | static int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type, | |
1710 | loff_t offset, u8 *buffer, size_t length) | |
1711 | { | |
1712 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_READ_IN_LEN); | |
1713 | MCDI_DECLARE_BUF(outbuf, | |
1714 | MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)); | |
1715 | size_t outlen; | |
1716 | int rc; | |
1717 | ||
1718 | MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type); | |
1719 | MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset); | |
1720 | MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length); | |
1721 | ||
1722 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf), | |
1723 | outbuf, sizeof(outbuf), &outlen); | |
1724 | if (rc) | |
1e0b8120 | 1725 | return rc; |
45a3fd55 BH |
1726 | |
1727 | memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length); | |
1728 | return 0; | |
45a3fd55 BH |
1729 | } |
1730 | ||
1731 | static int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type, | |
1732 | loff_t offset, const u8 *buffer, size_t length) | |
1733 | { | |
1734 | MCDI_DECLARE_BUF(inbuf, | |
1735 | MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)); | |
1736 | int rc; | |
1737 | ||
1738 | MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type); | |
1739 | MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset); | |
1740 | MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length); | |
1741 | memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length); | |
1742 | ||
1743 | BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0); | |
1744 | ||
1745 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf, | |
1746 | ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4), | |
1747 | NULL, 0, NULL); | |
45a3fd55 BH |
1748 | return rc; |
1749 | } | |
1750 | ||
1751 | static int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type, | |
1752 | loff_t offset, size_t length) | |
1753 | { | |
1754 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_ERASE_IN_LEN); | |
1755 | int rc; | |
1756 | ||
1757 | MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type); | |
1758 | MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset); | |
1759 | MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length); | |
1760 | ||
1761 | BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0); | |
1762 | ||
1763 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf), | |
1764 | NULL, 0, NULL); | |
45a3fd55 BH |
1765 | return rc; |
1766 | } | |
1767 | ||
1768 | static int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type) | |
1769 | { | |
1770 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN); | |
1771 | int rc; | |
1772 | ||
1773 | MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type); | |
1774 | ||
1775 | BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0); | |
1776 | ||
1777 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf), | |
1778 | NULL, 0, NULL); | |
45a3fd55 BH |
1779 | return rc; |
1780 | } | |
1781 | ||
1782 | int efx_mcdi_mtd_read(struct mtd_info *mtd, loff_t start, | |
1783 | size_t len, size_t *retlen, u8 *buffer) | |
1784 | { | |
1785 | struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd); | |
1786 | struct efx_nic *efx = mtd->priv; | |
1787 | loff_t offset = start; | |
1788 | loff_t end = min_t(loff_t, start + len, mtd->size); | |
1789 | size_t chunk; | |
1790 | int rc = 0; | |
1791 | ||
1792 | while (offset < end) { | |
1793 | chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX); | |
1794 | rc = efx_mcdi_nvram_read(efx, part->nvram_type, offset, | |
1795 | buffer, chunk); | |
1796 | if (rc) | |
1797 | goto out; | |
1798 | offset += chunk; | |
1799 | buffer += chunk; | |
1800 | } | |
1801 | out: | |
1802 | *retlen = offset - start; | |
1803 | return rc; | |
1804 | } | |
1805 | ||
1806 | int efx_mcdi_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len) | |
1807 | { | |
1808 | struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd); | |
1809 | struct efx_nic *efx = mtd->priv; | |
1810 | loff_t offset = start & ~((loff_t)(mtd->erasesize - 1)); | |
1811 | loff_t end = min_t(loff_t, start + len, mtd->size); | |
1812 | size_t chunk = part->common.mtd.erasesize; | |
1813 | int rc = 0; | |
1814 | ||
1815 | if (!part->updating) { | |
1816 | rc = efx_mcdi_nvram_update_start(efx, part->nvram_type); | |
1817 | if (rc) | |
1818 | goto out; | |
1819 | part->updating = true; | |
1820 | } | |
1821 | ||
1822 | /* The MCDI interface can in fact do multiple erase blocks at once; | |
1823 | * but erasing may be slow, so we make multiple calls here to avoid | |
1824 | * tripping the MCDI RPC timeout. */ | |
1825 | while (offset < end) { | |
1826 | rc = efx_mcdi_nvram_erase(efx, part->nvram_type, offset, | |
1827 | chunk); | |
1828 | if (rc) | |
1829 | goto out; | |
1830 | offset += chunk; | |
1831 | } | |
1832 | out: | |
1833 | return rc; | |
1834 | } | |
1835 | ||
1836 | int efx_mcdi_mtd_write(struct mtd_info *mtd, loff_t start, | |
1837 | size_t len, size_t *retlen, const u8 *buffer) | |
1838 | { | |
1839 | struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd); | |
1840 | struct efx_nic *efx = mtd->priv; | |
1841 | loff_t offset = start; | |
1842 | loff_t end = min_t(loff_t, start + len, mtd->size); | |
1843 | size_t chunk; | |
1844 | int rc = 0; | |
1845 | ||
1846 | if (!part->updating) { | |
1847 | rc = efx_mcdi_nvram_update_start(efx, part->nvram_type); | |
1848 | if (rc) | |
1849 | goto out; | |
1850 | part->updating = true; | |
1851 | } | |
1852 | ||
1853 | while (offset < end) { | |
1854 | chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX); | |
1855 | rc = efx_mcdi_nvram_write(efx, part->nvram_type, offset, | |
1856 | buffer, chunk); | |
1857 | if (rc) | |
1858 | goto out; | |
1859 | offset += chunk; | |
1860 | buffer += chunk; | |
1861 | } | |
1862 | out: | |
1863 | *retlen = offset - start; | |
1864 | return rc; | |
1865 | } | |
1866 | ||
1867 | int efx_mcdi_mtd_sync(struct mtd_info *mtd) | |
1868 | { | |
1869 | struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd); | |
1870 | struct efx_nic *efx = mtd->priv; | |
1871 | int rc = 0; | |
1872 | ||
1873 | if (part->updating) { | |
1874 | part->updating = false; | |
1875 | rc = efx_mcdi_nvram_update_finish(efx, part->nvram_type); | |
1876 | } | |
1877 | ||
1878 | return rc; | |
1879 | } | |
1880 | ||
1881 | void efx_mcdi_mtd_rename(struct efx_mtd_partition *part) | |
1882 | { | |
1883 | struct efx_mcdi_mtd_partition *mcdi_part = | |
1884 | container_of(part, struct efx_mcdi_mtd_partition, common); | |
1885 | struct efx_nic *efx = part->mtd.priv; | |
1886 | ||
1887 | snprintf(part->name, sizeof(part->name), "%s %s:%02x", | |
1888 | efx->name, part->type_name, mcdi_part->fw_subtype); | |
1889 | } | |
1890 | ||
1891 | #endif /* CONFIG_SFC_MTD */ |