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afd4aea0 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
0a6f40c6 | 3 | * Copyright 2008-2011 Solarflare Communications Inc. |
afd4aea0 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
11 | #include "net_driver.h" | |
12 | #include "nic.h" | |
13 | #include "io.h" | |
8b8a95a1 | 14 | #include "farch_regs.h" |
afd4aea0 BH |
15 | #include "mcdi_pcol.h" |
16 | #include "phy.h" | |
17 | ||
18 | /************************************************************************** | |
19 | * | |
20 | * Management-Controller-to-Driver Interface | |
21 | * | |
22 | ************************************************************************** | |
23 | */ | |
24 | ||
ebf98e79 | 25 | #define MCDI_RPC_TIMEOUT (10 * HZ) |
afd4aea0 | 26 | |
3f713bf4 BH |
27 | /* A reboot/assertion causes the MCDI status word to be set after the |
28 | * command word is set or a REBOOT event is sent. If we notice a reboot | |
29 | * via these mechanisms then wait 10ms for the status word to be set. */ | |
30 | #define MCDI_STATUS_DELAY_US 100 | |
31 | #define MCDI_STATUS_DELAY_COUNT 100 | |
32 | #define MCDI_STATUS_SLEEP_MS \ | |
33 | (MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000) | |
afd4aea0 BH |
34 | |
35 | #define SEQ_MASK \ | |
36 | EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ)) | |
37 | ||
38 | static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx) | |
39 | { | |
f3ad5003 BH |
40 | EFX_BUG_ON_PARANOID(!efx->mcdi); |
41 | return &efx->mcdi->iface; | |
afd4aea0 BH |
42 | } |
43 | ||
f073dde0 | 44 | int efx_mcdi_init(struct efx_nic *efx) |
afd4aea0 BH |
45 | { |
46 | struct efx_mcdi_iface *mcdi; | |
47 | ||
f3ad5003 BH |
48 | efx->mcdi = kzalloc(sizeof(*efx->mcdi), GFP_KERNEL); |
49 | if (!efx->mcdi) | |
50 | return -ENOMEM; | |
51 | ||
afd4aea0 BH |
52 | mcdi = efx_mcdi(efx); |
53 | init_waitqueue_head(&mcdi->wq); | |
54 | spin_lock_init(&mcdi->iface_lock); | |
55 | atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT); | |
56 | mcdi->mode = MCDI_MODE_POLL; | |
57 | ||
58 | (void) efx_mcdi_poll_reboot(efx); | |
f073dde0 BH |
59 | |
60 | /* Recover from a failed assertion before probing */ | |
61 | return efx_mcdi_handle_assertion(efx); | |
afd4aea0 BH |
62 | } |
63 | ||
f3ad5003 BH |
64 | void efx_mcdi_fini(struct efx_nic *efx) |
65 | { | |
66 | BUG_ON(efx->mcdi && | |
67 | atomic_read(&efx->mcdi->iface.state) != MCDI_STATE_QUIESCENT); | |
68 | kfree(efx->mcdi); | |
69 | } | |
70 | ||
afd4aea0 | 71 | static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd, |
9528b921 | 72 | const efx_dword_t *inbuf, size_t inlen) |
afd4aea0 BH |
73 | { |
74 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
afd4aea0 BH |
75 | efx_dword_t hdr; |
76 | u32 xflags, seqno; | |
77 | ||
78 | BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT); | |
9528b921 | 79 | BUG_ON(inlen > MCDI_CTL_SDU_LEN_MAX_V1); |
afd4aea0 BH |
80 | |
81 | seqno = mcdi->seqno & SEQ_MASK; | |
82 | xflags = 0; | |
83 | if (mcdi->mode == MCDI_MODE_EVENTS) | |
84 | xflags |= MCDI_HEADER_XFLAGS_EVREQ; | |
85 | ||
86 | EFX_POPULATE_DWORD_6(hdr, | |
87 | MCDI_HEADER_RESPONSE, 0, | |
88 | MCDI_HEADER_RESYNC, 1, | |
89 | MCDI_HEADER_CODE, cmd, | |
90 | MCDI_HEADER_DATALEN, inlen, | |
91 | MCDI_HEADER_SEQ, seqno, | |
92 | MCDI_HEADER_XFLAGS, xflags); | |
93 | ||
f3ad5003 | 94 | efx->type->mcdi_request(efx, &hdr, 4, inbuf, inlen); |
afd4aea0 BH |
95 | } |
96 | ||
9528b921 BH |
97 | static void |
98 | efx_mcdi_copyout(struct efx_nic *efx, efx_dword_t *outbuf, size_t outlen) | |
afd4aea0 BH |
99 | { |
100 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
afd4aea0 BH |
101 | |
102 | BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT); | |
9528b921 | 103 | BUG_ON(outlen > MCDI_CTL_SDU_LEN_MAX_V1); |
afd4aea0 | 104 | |
f3ad5003 | 105 | efx->type->mcdi_read_response(efx, outbuf, 4, outlen); |
afd4aea0 BH |
106 | } |
107 | ||
5bc283e5 BH |
108 | static int efx_mcdi_errno(unsigned int mcdi_err) |
109 | { | |
110 | switch (mcdi_err) { | |
111 | case 0: | |
112 | return 0; | |
113 | #define TRANSLATE_ERROR(name) \ | |
114 | case MC_CMD_ERR_ ## name: \ | |
115 | return -name; | |
116 | TRANSLATE_ERROR(ENOENT); | |
117 | TRANSLATE_ERROR(EINTR); | |
118 | TRANSLATE_ERROR(EACCES); | |
119 | TRANSLATE_ERROR(EBUSY); | |
120 | TRANSLATE_ERROR(EINVAL); | |
121 | TRANSLATE_ERROR(EDEADLK); | |
122 | TRANSLATE_ERROR(ENOSYS); | |
123 | TRANSLATE_ERROR(ETIME); | |
124 | #undef TRANSLATE_ERROR | |
125 | default: | |
126 | return -EIO; | |
127 | } | |
128 | } | |
129 | ||
afd4aea0 BH |
130 | static int efx_mcdi_poll(struct efx_nic *efx) |
131 | { | |
132 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
ebf98e79 | 133 | unsigned long time, finish; |
afd4aea0 | 134 | unsigned int respseq, respcmd, error; |
5bc283e5 | 135 | unsigned int spins; |
afd4aea0 | 136 | efx_dword_t reg; |
5bc283e5 | 137 | int rc; |
afd4aea0 BH |
138 | |
139 | /* Check for a reboot atomically with respect to efx_mcdi_copyout() */ | |
5bc283e5 | 140 | rc = efx_mcdi_poll_reboot(efx); |
afd4aea0 BH |
141 | if (rc) |
142 | goto out; | |
143 | ||
144 | /* Poll for completion. Poll quickly (once a us) for the 1st jiffy, | |
145 | * because generally mcdi responses are fast. After that, back off | |
146 | * and poll once a jiffy (approximately) | |
147 | */ | |
148 | spins = TICK_USEC; | |
ebf98e79 | 149 | finish = jiffies + MCDI_RPC_TIMEOUT; |
afd4aea0 BH |
150 | |
151 | while (1) { | |
152 | if (spins != 0) { | |
153 | --spins; | |
154 | udelay(1); | |
55029c1d BH |
155 | } else { |
156 | schedule_timeout_uninterruptible(1); | |
157 | } | |
afd4aea0 | 158 | |
ebf98e79 | 159 | time = jiffies; |
afd4aea0 | 160 | |
86c432ca | 161 | rmb(); |
f3ad5003 | 162 | if (efx->type->mcdi_poll_response(efx)) |
afd4aea0 BH |
163 | break; |
164 | ||
ebf98e79 | 165 | if (time_after(time, finish)) |
afd4aea0 BH |
166 | return -ETIMEDOUT; |
167 | } | |
168 | ||
f3ad5003 | 169 | efx->type->mcdi_read_response(efx, ®, 0, 4); |
afd4aea0 BH |
170 | mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN); |
171 | respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ); | |
172 | respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE); | |
173 | error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR); | |
174 | ||
175 | if (error && mcdi->resplen == 0) { | |
62776d03 | 176 | netif_err(efx, hw, efx->net_dev, "MC rebooted\n"); |
5bc283e5 | 177 | rc = -EIO; |
afd4aea0 | 178 | } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) { |
62776d03 BH |
179 | netif_err(efx, hw, efx->net_dev, |
180 | "MC response mismatch tx seq 0x%x rx seq 0x%x\n", | |
181 | respseq, mcdi->seqno); | |
5bc283e5 | 182 | rc = -EIO; |
afd4aea0 | 183 | } else if (error) { |
f3ad5003 | 184 | efx->type->mcdi_read_response(efx, ®, 4, 4); |
5bc283e5 | 185 | rc = efx_mcdi_errno(EFX_DWORD_FIELD(reg, EFX_DWORD_0)); |
afd4aea0 BH |
186 | } else |
187 | rc = 0; | |
188 | ||
189 | out: | |
190 | mcdi->resprc = rc; | |
191 | if (rc) | |
192 | mcdi->resplen = 0; | |
193 | ||
194 | /* Return rc=0 like wait_event_timeout() */ | |
195 | return 0; | |
196 | } | |
197 | ||
876be083 BH |
198 | /* Test and clear MC-rebooted flag for this port/function; reset |
199 | * software state as necessary. | |
200 | */ | |
afd4aea0 BH |
201 | int efx_mcdi_poll_reboot(struct efx_nic *efx) |
202 | { | |
f3ad5003 | 203 | int rc; |
afd4aea0 | 204 | |
f3ad5003 BH |
205 | if (!efx->mcdi) |
206 | return 0; | |
afd4aea0 | 207 | |
f3ad5003 BH |
208 | rc = efx->type->mcdi_poll_reboot(efx); |
209 | if (!rc) | |
afd4aea0 BH |
210 | return 0; |
211 | ||
876be083 BH |
212 | /* MAC statistics have been cleared on the NIC; clear our copy |
213 | * so that efx_update_diff_stat() can continue to work. | |
214 | */ | |
215 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); | |
216 | ||
f3ad5003 | 217 | return rc; |
afd4aea0 BH |
218 | } |
219 | ||
220 | static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi) | |
221 | { | |
222 | /* Wait until the interface becomes QUIESCENT and we win the race | |
223 | * to mark it RUNNING. */ | |
224 | wait_event(mcdi->wq, | |
225 | atomic_cmpxchg(&mcdi->state, | |
226 | MCDI_STATE_QUIESCENT, | |
227 | MCDI_STATE_RUNNING) | |
228 | == MCDI_STATE_QUIESCENT); | |
229 | } | |
230 | ||
231 | static int efx_mcdi_await_completion(struct efx_nic *efx) | |
232 | { | |
233 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
234 | ||
235 | if (wait_event_timeout( | |
236 | mcdi->wq, | |
237 | atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED, | |
ebf98e79 | 238 | MCDI_RPC_TIMEOUT) == 0) |
afd4aea0 BH |
239 | return -ETIMEDOUT; |
240 | ||
241 | /* Check if efx_mcdi_set_mode() switched us back to polled completions. | |
242 | * In which case, poll for completions directly. If efx_mcdi_ev_cpl() | |
243 | * completed the request first, then we'll just end up completing the | |
244 | * request again, which is safe. | |
245 | * | |
246 | * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which | |
247 | * wait_event_timeout() implicitly provides. | |
248 | */ | |
249 | if (mcdi->mode == MCDI_MODE_POLL) | |
250 | return efx_mcdi_poll(efx); | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
255 | static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi) | |
256 | { | |
257 | /* If the interface is RUNNING, then move to COMPLETED and wake any | |
258 | * waiters. If the interface isn't in RUNNING then we've received a | |
259 | * duplicate completion after we've already transitioned back to | |
260 | * QUIESCENT. [A subsequent invocation would increment seqno, so would | |
261 | * have failed the seqno check]. | |
262 | */ | |
263 | if (atomic_cmpxchg(&mcdi->state, | |
264 | MCDI_STATE_RUNNING, | |
265 | MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) { | |
266 | wake_up(&mcdi->wq); | |
267 | return true; | |
268 | } | |
269 | ||
270 | return false; | |
271 | } | |
272 | ||
273 | static void efx_mcdi_release(struct efx_mcdi_iface *mcdi) | |
274 | { | |
275 | atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT); | |
276 | wake_up(&mcdi->wq); | |
277 | } | |
278 | ||
279 | static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno, | |
5bc283e5 | 280 | unsigned int datalen, unsigned int mcdi_err) |
afd4aea0 BH |
281 | { |
282 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
283 | bool wake = false; | |
284 | ||
285 | spin_lock(&mcdi->iface_lock); | |
286 | ||
287 | if ((seqno ^ mcdi->seqno) & SEQ_MASK) { | |
288 | if (mcdi->credits) | |
289 | /* The request has been cancelled */ | |
290 | --mcdi->credits; | |
291 | else | |
62776d03 BH |
292 | netif_err(efx, hw, efx->net_dev, |
293 | "MC response mismatch tx seq 0x%x rx " | |
294 | "seq 0x%x\n", seqno, mcdi->seqno); | |
afd4aea0 | 295 | } else { |
5bc283e5 | 296 | mcdi->resprc = efx_mcdi_errno(mcdi_err); |
afd4aea0 BH |
297 | mcdi->resplen = datalen; |
298 | ||
299 | wake = true; | |
300 | } | |
301 | ||
302 | spin_unlock(&mcdi->iface_lock); | |
303 | ||
304 | if (wake) | |
305 | efx_mcdi_complete(mcdi); | |
306 | } | |
307 | ||
afd4aea0 | 308 | int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd, |
9528b921 BH |
309 | const efx_dword_t *inbuf, size_t inlen, |
310 | efx_dword_t *outbuf, size_t outlen, | |
afd4aea0 | 311 | size_t *outlen_actual) |
c3cba721 SH |
312 | { |
313 | efx_mcdi_rpc_start(efx, cmd, inbuf, inlen); | |
314 | return efx_mcdi_rpc_finish(efx, cmd, inlen, | |
315 | outbuf, outlen, outlen_actual); | |
316 | } | |
317 | ||
9528b921 BH |
318 | void efx_mcdi_rpc_start(struct efx_nic *efx, unsigned cmd, |
319 | const efx_dword_t *inbuf, size_t inlen) | |
afd4aea0 BH |
320 | { |
321 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
c3cba721 | 322 | |
afd4aea0 BH |
323 | efx_mcdi_acquire(mcdi); |
324 | ||
325 | /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */ | |
326 | spin_lock_bh(&mcdi->iface_lock); | |
327 | ++mcdi->seqno; | |
328 | spin_unlock_bh(&mcdi->iface_lock); | |
329 | ||
330 | efx_mcdi_copyin(efx, cmd, inbuf, inlen); | |
c3cba721 SH |
331 | } |
332 | ||
333 | int efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen, | |
9528b921 BH |
334 | efx_dword_t *outbuf, size_t outlen, |
335 | size_t *outlen_actual) | |
c3cba721 SH |
336 | { |
337 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
338 | int rc; | |
339 | ||
afd4aea0 BH |
340 | if (mcdi->mode == MCDI_MODE_POLL) |
341 | rc = efx_mcdi_poll(efx); | |
342 | else | |
343 | rc = efx_mcdi_await_completion(efx); | |
344 | ||
345 | if (rc != 0) { | |
346 | /* Close the race with efx_mcdi_ev_cpl() executing just too late | |
347 | * and completing a request we've just cancelled, by ensuring | |
348 | * that the seqno check therein fails. | |
349 | */ | |
350 | spin_lock_bh(&mcdi->iface_lock); | |
351 | ++mcdi->seqno; | |
352 | ++mcdi->credits; | |
353 | spin_unlock_bh(&mcdi->iface_lock); | |
354 | ||
62776d03 BH |
355 | netif_err(efx, hw, efx->net_dev, |
356 | "MC command 0x%x inlen %d mode %d timed out\n", | |
357 | cmd, (int)inlen, mcdi->mode); | |
afd4aea0 BH |
358 | } else { |
359 | size_t resplen; | |
360 | ||
361 | /* At the very least we need a memory barrier here to ensure | |
362 | * we pick up changes from efx_mcdi_ev_cpl(). Protect against | |
363 | * a spurious efx_mcdi_ev_cpl() running concurrently by | |
364 | * acquiring the iface_lock. */ | |
365 | spin_lock_bh(&mcdi->iface_lock); | |
5bc283e5 | 366 | rc = mcdi->resprc; |
afd4aea0 BH |
367 | resplen = mcdi->resplen; |
368 | spin_unlock_bh(&mcdi->iface_lock); | |
369 | ||
5bc283e5 BH |
370 | BUG_ON(rc > 0); |
371 | ||
afd4aea0 BH |
372 | if (rc == 0) { |
373 | efx_mcdi_copyout(efx, outbuf, | |
9528b921 | 374 | min(outlen, mcdi->resplen)); |
afd4aea0 BH |
375 | if (outlen_actual != NULL) |
376 | *outlen_actual = resplen; | |
377 | } else if (cmd == MC_CMD_REBOOT && rc == -EIO) | |
378 | ; /* Don't reset if MC_CMD_REBOOT returns EIO */ | |
379 | else if (rc == -EIO || rc == -EINTR) { | |
62776d03 BH |
380 | netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n", |
381 | -rc); | |
afd4aea0 BH |
382 | efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE); |
383 | } else | |
f18ca364 | 384 | netif_dbg(efx, hw, efx->net_dev, |
62776d03 BH |
385 | "MC command 0x%x inlen %d failed rc=%d\n", |
386 | cmd, (int)inlen, -rc); | |
3f713bf4 BH |
387 | |
388 | if (rc == -EIO || rc == -EINTR) { | |
389 | msleep(MCDI_STATUS_SLEEP_MS); | |
390 | efx_mcdi_poll_reboot(efx); | |
391 | } | |
afd4aea0 BH |
392 | } |
393 | ||
394 | efx_mcdi_release(mcdi); | |
395 | return rc; | |
396 | } | |
397 | ||
398 | void efx_mcdi_mode_poll(struct efx_nic *efx) | |
399 | { | |
400 | struct efx_mcdi_iface *mcdi; | |
401 | ||
f3ad5003 | 402 | if (!efx->mcdi) |
afd4aea0 BH |
403 | return; |
404 | ||
405 | mcdi = efx_mcdi(efx); | |
406 | if (mcdi->mode == MCDI_MODE_POLL) | |
407 | return; | |
408 | ||
409 | /* We can switch from event completion to polled completion, because | |
410 | * mcdi requests are always completed in shared memory. We do this by | |
411 | * switching the mode to POLL'd then completing the request. | |
412 | * efx_mcdi_await_completion() will then call efx_mcdi_poll(). | |
413 | * | |
414 | * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(), | |
415 | * which efx_mcdi_complete() provides for us. | |
416 | */ | |
417 | mcdi->mode = MCDI_MODE_POLL; | |
418 | ||
419 | efx_mcdi_complete(mcdi); | |
420 | } | |
421 | ||
422 | void efx_mcdi_mode_event(struct efx_nic *efx) | |
423 | { | |
424 | struct efx_mcdi_iface *mcdi; | |
425 | ||
f3ad5003 | 426 | if (!efx->mcdi) |
afd4aea0 BH |
427 | return; |
428 | ||
429 | mcdi = efx_mcdi(efx); | |
430 | ||
431 | if (mcdi->mode == MCDI_MODE_EVENTS) | |
432 | return; | |
433 | ||
434 | /* We can't switch from polled to event completion in the middle of a | |
435 | * request, because the completion method is specified in the request. | |
436 | * So acquire the interface to serialise the requestors. We don't need | |
437 | * to acquire the iface_lock to change the mode here, but we do need a | |
438 | * write memory barrier ensure that efx_mcdi_rpc() sees it, which | |
439 | * efx_mcdi_acquire() provides. | |
440 | */ | |
441 | efx_mcdi_acquire(mcdi); | |
442 | mcdi->mode = MCDI_MODE_EVENTS; | |
443 | efx_mcdi_release(mcdi); | |
444 | } | |
445 | ||
446 | static void efx_mcdi_ev_death(struct efx_nic *efx, int rc) | |
447 | { | |
448 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | |
449 | ||
450 | /* If there is an outstanding MCDI request, it has been terminated | |
451 | * either by a BADASSERT or REBOOT event. If the mcdi interface is | |
452 | * in polled mode, then do nothing because the MC reboot handler will | |
453 | * set the header correctly. However, if the mcdi interface is waiting | |
454 | * for a CMDDONE event it won't receive it [and since all MCDI events | |
455 | * are sent to the same queue, we can't be racing with | |
456 | * efx_mcdi_ev_cpl()] | |
457 | * | |
458 | * There's a race here with efx_mcdi_rpc(), because we might receive | |
459 | * a REBOOT event *before* the request has been copied out. In polled | |
25985edc | 460 | * mode (during startup) this is irrelevant, because efx_mcdi_complete() |
afd4aea0 BH |
461 | * is ignored. In event mode, this condition is just an edge-case of |
462 | * receiving a REBOOT event after posting the MCDI request. Did the mc | |
463 | * reboot before or after the copyout? The best we can do always is | |
464 | * just return failure. | |
465 | */ | |
466 | spin_lock(&mcdi->iface_lock); | |
467 | if (efx_mcdi_complete(mcdi)) { | |
468 | if (mcdi->mode == MCDI_MODE_EVENTS) { | |
469 | mcdi->resprc = rc; | |
470 | mcdi->resplen = 0; | |
18e3ee2c | 471 | ++mcdi->credits; |
afd4aea0 | 472 | } |
3f713bf4 BH |
473 | } else { |
474 | int count; | |
475 | ||
afd4aea0 BH |
476 | /* Nobody was waiting for an MCDI request, so trigger a reset */ |
477 | efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE); | |
478 | ||
3f713bf4 BH |
479 | /* Consume the status word since efx_mcdi_rpc_finish() won't */ |
480 | for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) { | |
481 | if (efx_mcdi_poll_reboot(efx)) | |
482 | break; | |
483 | udelay(MCDI_STATUS_DELAY_US); | |
484 | } | |
485 | } | |
486 | ||
afd4aea0 BH |
487 | spin_unlock(&mcdi->iface_lock); |
488 | } | |
489 | ||
afd4aea0 BH |
490 | /* Called from falcon_process_eventq for MCDI events */ |
491 | void efx_mcdi_process_event(struct efx_channel *channel, | |
492 | efx_qword_t *event) | |
493 | { | |
494 | struct efx_nic *efx = channel->efx; | |
495 | int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE); | |
496 | u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA); | |
497 | ||
498 | switch (code) { | |
499 | case MCDI_EVENT_CODE_BADSSERT: | |
62776d03 BH |
500 | netif_err(efx, hw, efx->net_dev, |
501 | "MC watchdog or assertion failure at 0x%x\n", data); | |
5bc283e5 | 502 | efx_mcdi_ev_death(efx, -EINTR); |
afd4aea0 BH |
503 | break; |
504 | ||
505 | case MCDI_EVENT_CODE_PMNOTICE: | |
62776d03 | 506 | netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n"); |
afd4aea0 BH |
507 | break; |
508 | ||
509 | case MCDI_EVENT_CODE_CMDDONE: | |
510 | efx_mcdi_ev_cpl(efx, | |
511 | MCDI_EVENT_FIELD(*event, CMDDONE_SEQ), | |
512 | MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN), | |
513 | MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO)); | |
514 | break; | |
515 | ||
516 | case MCDI_EVENT_CODE_LINKCHANGE: | |
517 | efx_mcdi_process_link_change(efx, event); | |
518 | break; | |
519 | case MCDI_EVENT_CODE_SENSOREVT: | |
520 | efx_mcdi_sensor_event(efx, event); | |
521 | break; | |
522 | case MCDI_EVENT_CODE_SCHEDERR: | |
62776d03 BH |
523 | netif_info(efx, hw, efx->net_dev, |
524 | "MC Scheduler error address=0x%x\n", data); | |
afd4aea0 BH |
525 | break; |
526 | case MCDI_EVENT_CODE_REBOOT: | |
62776d03 | 527 | netif_info(efx, hw, efx->net_dev, "MC Reboot\n"); |
5bc283e5 | 528 | efx_mcdi_ev_death(efx, -EIO); |
afd4aea0 BH |
529 | break; |
530 | case MCDI_EVENT_CODE_MAC_STATS_DMA: | |
531 | /* MAC stats are gather lazily. We can ignore this. */ | |
532 | break; | |
cd2d5b52 BH |
533 | case MCDI_EVENT_CODE_FLR: |
534 | efx_sriov_flr(efx, MCDI_EVENT_FIELD(*event, FLR_VF)); | |
535 | break; | |
7c236c43 SH |
536 | case MCDI_EVENT_CODE_PTP_RX: |
537 | case MCDI_EVENT_CODE_PTP_FAULT: | |
538 | case MCDI_EVENT_CODE_PTP_PPS: | |
539 | efx_ptp_event(efx, event); | |
540 | break; | |
afd4aea0 BH |
541 | |
542 | default: | |
62776d03 BH |
543 | netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n", |
544 | code); | |
afd4aea0 BH |
545 | } |
546 | } | |
547 | ||
548 | /************************************************************************** | |
549 | * | |
550 | * Specific request functions | |
551 | * | |
552 | ************************************************************************** | |
553 | */ | |
554 | ||
e5f0fd27 | 555 | void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len) |
afd4aea0 | 556 | { |
59cfc479 | 557 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_VERSION_OUT_LEN); |
afd4aea0 BH |
558 | size_t outlength; |
559 | const __le16 *ver_words; | |
560 | int rc; | |
561 | ||
562 | BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0); | |
563 | ||
564 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0, | |
565 | outbuf, sizeof(outbuf), &outlength); | |
566 | if (rc) | |
567 | goto fail; | |
568 | ||
05a9320f | 569 | if (outlength < MC_CMD_GET_VERSION_OUT_LEN) { |
00bbb4a5 | 570 | rc = -EIO; |
afd4aea0 BH |
571 | goto fail; |
572 | } | |
573 | ||
574 | ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION); | |
e5f0fd27 BH |
575 | snprintf(buf, len, "%u.%u.%u.%u", |
576 | le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]), | |
577 | le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3])); | |
578 | return; | |
afd4aea0 BH |
579 | |
580 | fail: | |
62776d03 | 581 | netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
e5f0fd27 | 582 | buf[0] = 0; |
afd4aea0 BH |
583 | } |
584 | ||
585 | int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating, | |
586 | bool *was_attached) | |
587 | { | |
59cfc479 BH |
588 | MCDI_DECLARE_BUF(inbuf, MC_CMD_DRV_ATTACH_IN_LEN); |
589 | MCDI_DECLARE_BUF(outbuf, MC_CMD_DRV_ATTACH_OUT_LEN); | |
afd4aea0 BH |
590 | size_t outlen; |
591 | int rc; | |
592 | ||
593 | MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE, | |
594 | driver_operating ? 1 : 0); | |
595 | MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1); | |
f2b0befd | 596 | MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_FIRMWARE_ID, MC_CMD_FW_LOW_LATENCY); |
afd4aea0 BH |
597 | |
598 | rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf), | |
599 | outbuf, sizeof(outbuf), &outlen); | |
600 | if (rc) | |
601 | goto fail; | |
00bbb4a5 BH |
602 | if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) { |
603 | rc = -EIO; | |
afd4aea0 | 604 | goto fail; |
00bbb4a5 | 605 | } |
afd4aea0 BH |
606 | |
607 | if (was_attached != NULL) | |
608 | *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE); | |
609 | return 0; | |
610 | ||
611 | fail: | |
62776d03 | 612 | netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
613 | return rc; |
614 | } | |
615 | ||
616 | int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address, | |
6aa9c7f6 | 617 | u16 *fw_subtype_list, u32 *capabilities) |
afd4aea0 | 618 | { |
59cfc479 | 619 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_BOARD_CFG_OUT_LENMAX); |
c5bb0e98 | 620 | size_t outlen, i; |
afd4aea0 | 621 | int port_num = efx_port_num(efx); |
afd4aea0 BH |
622 | int rc; |
623 | ||
624 | BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0); | |
625 | ||
626 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0, | |
627 | outbuf, sizeof(outbuf), &outlen); | |
628 | if (rc) | |
629 | goto fail; | |
630 | ||
05a9320f | 631 | if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) { |
00bbb4a5 | 632 | rc = -EIO; |
afd4aea0 BH |
633 | goto fail; |
634 | } | |
635 | ||
afd4aea0 | 636 | if (mac_address) |
c5bb0e98 BH |
637 | memcpy(mac_address, |
638 | port_num ? | |
639 | MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1) : | |
640 | MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0), | |
641 | ETH_ALEN); | |
bfeed902 | 642 | if (fw_subtype_list) { |
bfeed902 | 643 | for (i = 0; |
c5bb0e98 BH |
644 | i < MCDI_VAR_ARRAY_LEN(outlen, |
645 | GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST); | |
646 | i++) | |
647 | fw_subtype_list[i] = MCDI_ARRAY_WORD( | |
648 | outbuf, GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST, i); | |
649 | for (; i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM; i++) | |
650 | fw_subtype_list[i] = 0; | |
bfeed902 | 651 | } |
6aa9c7f6 MS |
652 | if (capabilities) { |
653 | if (port_num) | |
654 | *capabilities = MCDI_DWORD(outbuf, | |
655 | GET_BOARD_CFG_OUT_CAPABILITIES_PORT1); | |
656 | else | |
657 | *capabilities = MCDI_DWORD(outbuf, | |
658 | GET_BOARD_CFG_OUT_CAPABILITIES_PORT0); | |
659 | } | |
afd4aea0 BH |
660 | |
661 | return 0; | |
662 | ||
663 | fail: | |
62776d03 BH |
664 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n", |
665 | __func__, rc, (int)outlen); | |
afd4aea0 BH |
666 | |
667 | return rc; | |
668 | } | |
669 | ||
670 | int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq) | |
671 | { | |
59cfc479 | 672 | MCDI_DECLARE_BUF(inbuf, MC_CMD_LOG_CTRL_IN_LEN); |
afd4aea0 BH |
673 | u32 dest = 0; |
674 | int rc; | |
675 | ||
676 | if (uart) | |
677 | dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART; | |
678 | if (evq) | |
679 | dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ; | |
680 | ||
681 | MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest); | |
682 | MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq); | |
683 | ||
684 | BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0); | |
685 | ||
686 | rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf), | |
687 | NULL, 0, NULL); | |
688 | if (rc) | |
689 | goto fail; | |
690 | ||
691 | return 0; | |
692 | ||
693 | fail: | |
62776d03 | 694 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
695 | return rc; |
696 | } | |
697 | ||
698 | int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out) | |
699 | { | |
59cfc479 | 700 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TYPES_OUT_LEN); |
afd4aea0 BH |
701 | size_t outlen; |
702 | int rc; | |
703 | ||
704 | BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0); | |
705 | ||
706 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0, | |
707 | outbuf, sizeof(outbuf), &outlen); | |
708 | if (rc) | |
709 | goto fail; | |
00bbb4a5 BH |
710 | if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) { |
711 | rc = -EIO; | |
afd4aea0 | 712 | goto fail; |
00bbb4a5 | 713 | } |
afd4aea0 BH |
714 | |
715 | *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES); | |
716 | return 0; | |
717 | ||
718 | fail: | |
62776d03 BH |
719 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", |
720 | __func__, rc); | |
afd4aea0 BH |
721 | return rc; |
722 | } | |
723 | ||
724 | int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type, | |
725 | size_t *size_out, size_t *erase_size_out, | |
726 | bool *protected_out) | |
727 | { | |
59cfc479 BH |
728 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_INFO_IN_LEN); |
729 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_INFO_OUT_LEN); | |
afd4aea0 BH |
730 | size_t outlen; |
731 | int rc; | |
732 | ||
733 | MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type); | |
734 | ||
735 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf), | |
736 | outbuf, sizeof(outbuf), &outlen); | |
737 | if (rc) | |
738 | goto fail; | |
00bbb4a5 BH |
739 | if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) { |
740 | rc = -EIO; | |
afd4aea0 | 741 | goto fail; |
00bbb4a5 | 742 | } |
afd4aea0 BH |
743 | |
744 | *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE); | |
745 | *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE); | |
746 | *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) & | |
05a9320f | 747 | (1 << MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN)); |
afd4aea0 BH |
748 | return 0; |
749 | ||
750 | fail: | |
62776d03 | 751 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
752 | return rc; |
753 | } | |
754 | ||
755 | int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type) | |
756 | { | |
59cfc479 | 757 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_START_IN_LEN); |
afd4aea0 BH |
758 | int rc; |
759 | ||
760 | MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type); | |
761 | ||
762 | BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0); | |
763 | ||
764 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf), | |
765 | NULL, 0, NULL); | |
766 | if (rc) | |
767 | goto fail; | |
768 | ||
769 | return 0; | |
770 | ||
771 | fail: | |
62776d03 | 772 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
773 | return rc; |
774 | } | |
775 | ||
776 | int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type, | |
777 | loff_t offset, u8 *buffer, size_t length) | |
778 | { | |
59cfc479 BH |
779 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_READ_IN_LEN); |
780 | MCDI_DECLARE_BUF(outbuf, | |
781 | MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)); | |
afd4aea0 BH |
782 | size_t outlen; |
783 | int rc; | |
784 | ||
785 | MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type); | |
786 | MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset); | |
787 | MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length); | |
788 | ||
789 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf), | |
790 | outbuf, sizeof(outbuf), &outlen); | |
791 | if (rc) | |
792 | goto fail; | |
793 | ||
794 | memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length); | |
795 | return 0; | |
796 | ||
797 | fail: | |
62776d03 | 798 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
799 | return rc; |
800 | } | |
801 | ||
802 | int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type, | |
803 | loff_t offset, const u8 *buffer, size_t length) | |
804 | { | |
59cfc479 BH |
805 | MCDI_DECLARE_BUF(inbuf, |
806 | MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)); | |
afd4aea0 BH |
807 | int rc; |
808 | ||
809 | MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type); | |
810 | MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset); | |
811 | MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length); | |
812 | memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length); | |
813 | ||
814 | BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0); | |
815 | ||
5a27e86b BH |
816 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf, |
817 | ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4), | |
afd4aea0 BH |
818 | NULL, 0, NULL); |
819 | if (rc) | |
820 | goto fail; | |
821 | ||
822 | return 0; | |
823 | ||
824 | fail: | |
62776d03 | 825 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
826 | return rc; |
827 | } | |
828 | ||
829 | int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type, | |
830 | loff_t offset, size_t length) | |
831 | { | |
59cfc479 | 832 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_ERASE_IN_LEN); |
afd4aea0 BH |
833 | int rc; |
834 | ||
835 | MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type); | |
836 | MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset); | |
837 | MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length); | |
838 | ||
839 | BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0); | |
840 | ||
841 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf), | |
842 | NULL, 0, NULL); | |
843 | if (rc) | |
844 | goto fail; | |
845 | ||
846 | return 0; | |
847 | ||
848 | fail: | |
62776d03 | 849 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
850 | return rc; |
851 | } | |
852 | ||
853 | int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type) | |
854 | { | |
59cfc479 | 855 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN); |
afd4aea0 BH |
856 | int rc; |
857 | ||
858 | MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type); | |
859 | ||
860 | BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0); | |
861 | ||
862 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf), | |
863 | NULL, 0, NULL); | |
864 | if (rc) | |
865 | goto fail; | |
866 | ||
867 | return 0; | |
868 | ||
869 | fail: | |
62776d03 | 870 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
871 | return rc; |
872 | } | |
873 | ||
2e803407 BH |
874 | static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type) |
875 | { | |
59cfc479 BH |
876 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_TEST_IN_LEN); |
877 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TEST_OUT_LEN); | |
2e803407 BH |
878 | int rc; |
879 | ||
880 | MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type); | |
881 | ||
882 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf), | |
883 | outbuf, sizeof(outbuf), NULL); | |
884 | if (rc) | |
885 | return rc; | |
886 | ||
887 | switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) { | |
888 | case MC_CMD_NVRAM_TEST_PASS: | |
889 | case MC_CMD_NVRAM_TEST_NOTSUPP: | |
890 | return 0; | |
891 | default: | |
892 | return -EIO; | |
893 | } | |
894 | } | |
895 | ||
896 | int efx_mcdi_nvram_test_all(struct efx_nic *efx) | |
897 | { | |
898 | u32 nvram_types; | |
899 | unsigned int type; | |
900 | int rc; | |
901 | ||
902 | rc = efx_mcdi_nvram_types(efx, &nvram_types); | |
903 | if (rc) | |
b548a988 | 904 | goto fail1; |
2e803407 BH |
905 | |
906 | type = 0; | |
907 | while (nvram_types != 0) { | |
908 | if (nvram_types & 1) { | |
909 | rc = efx_mcdi_nvram_test(efx, type); | |
910 | if (rc) | |
b548a988 | 911 | goto fail2; |
2e803407 BH |
912 | } |
913 | type++; | |
914 | nvram_types >>= 1; | |
915 | } | |
916 | ||
917 | return 0; | |
b548a988 BH |
918 | |
919 | fail2: | |
62776d03 BH |
920 | netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n", |
921 | __func__, type); | |
b548a988 | 922 | fail1: |
62776d03 | 923 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
b548a988 | 924 | return rc; |
2e803407 BH |
925 | } |
926 | ||
8b2103ad | 927 | static int efx_mcdi_read_assertion(struct efx_nic *efx) |
afd4aea0 | 928 | { |
59cfc479 BH |
929 | MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_ASSERTS_IN_LEN); |
930 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_ASSERTS_OUT_LEN); | |
c5bb0e98 | 931 | unsigned int flags, index; |
afd4aea0 BH |
932 | const char *reason; |
933 | size_t outlen; | |
934 | int retry; | |
935 | int rc; | |
936 | ||
8b2103ad SH |
937 | /* Attempt to read any stored assertion state before we reboot |
938 | * the mcfw out of the assertion handler. Retry twice, once | |
afd4aea0 BH |
939 | * because a boot-time assertion might cause this command to fail |
940 | * with EINTR. And once again because GET_ASSERTS can race with | |
941 | * MC_CMD_REBOOT running on the other port. */ | |
942 | retry = 2; | |
943 | do { | |
8b2103ad | 944 | MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1); |
afd4aea0 | 945 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS, |
8b2103ad SH |
946 | inbuf, MC_CMD_GET_ASSERTS_IN_LEN, |
947 | outbuf, sizeof(outbuf), &outlen); | |
afd4aea0 BH |
948 | } while ((rc == -EINTR || rc == -EIO) && retry-- > 0); |
949 | ||
950 | if (rc) | |
951 | return rc; | |
952 | if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN) | |
00bbb4a5 | 953 | return -EIO; |
afd4aea0 | 954 | |
8b2103ad SH |
955 | /* Print out any recorded assertion state */ |
956 | flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS); | |
afd4aea0 BH |
957 | if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS) |
958 | return 0; | |
959 | ||
afd4aea0 BH |
960 | reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL) |
961 | ? "system-level assertion" | |
962 | : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL) | |
963 | ? "thread-level assertion" | |
964 | : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED) | |
965 | ? "watchdog reset" | |
966 | : "unknown assertion"; | |
62776d03 BH |
967 | netif_err(efx, hw, efx->net_dev, |
968 | "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason, | |
969 | MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS), | |
970 | MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS)); | |
afd4aea0 BH |
971 | |
972 | /* Print out the registers */ | |
c5bb0e98 BH |
973 | for (index = 0; |
974 | index < MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM; | |
975 | index++) | |
976 | netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", | |
977 | 1 + index, | |
978 | MCDI_ARRAY_DWORD(outbuf, GET_ASSERTS_OUT_GP_REGS_OFFS, | |
979 | index)); | |
afd4aea0 BH |
980 | |
981 | return 0; | |
982 | } | |
983 | ||
8b2103ad SH |
984 | static void efx_mcdi_exit_assertion(struct efx_nic *efx) |
985 | { | |
59cfc479 | 986 | MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN); |
8b2103ad | 987 | |
0f1e54ae BH |
988 | /* If the MC is running debug firmware, it might now be |
989 | * waiting for a debugger to attach, but we just want it to | |
990 | * reboot. We set a flag that makes the command a no-op if it | |
991 | * has already done so. We don't know what return code to | |
992 | * expect (0 or -EIO), so ignore it. | |
993 | */ | |
8b2103ad SH |
994 | BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0); |
995 | MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, | |
996 | MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION); | |
0f1e54ae BH |
997 | (void) efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN, |
998 | NULL, 0, NULL); | |
8b2103ad SH |
999 | } |
1000 | ||
1001 | int efx_mcdi_handle_assertion(struct efx_nic *efx) | |
1002 | { | |
1003 | int rc; | |
1004 | ||
1005 | rc = efx_mcdi_read_assertion(efx); | |
1006 | if (rc) | |
1007 | return rc; | |
1008 | ||
1009 | efx_mcdi_exit_assertion(efx); | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
afd4aea0 BH |
1014 | void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1015 | { | |
59cfc479 | 1016 | MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_ID_LED_IN_LEN); |
afd4aea0 BH |
1017 | int rc; |
1018 | ||
1019 | BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF); | |
1020 | BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON); | |
1021 | BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT); | |
1022 | ||
1023 | BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0); | |
1024 | ||
1025 | MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode); | |
1026 | ||
1027 | rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf), | |
1028 | NULL, 0, NULL); | |
1029 | if (rc) | |
62776d03 BH |
1030 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", |
1031 | __func__, rc); | |
afd4aea0 BH |
1032 | } |
1033 | ||
6bff861d | 1034 | static int efx_mcdi_reset_port(struct efx_nic *efx) |
afd4aea0 | 1035 | { |
05a9320f | 1036 | int rc = efx_mcdi_rpc(efx, MC_CMD_ENTITY_RESET, NULL, 0, NULL, 0, NULL); |
afd4aea0 | 1037 | if (rc) |
62776d03 BH |
1038 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", |
1039 | __func__, rc); | |
afd4aea0 BH |
1040 | return rc; |
1041 | } | |
1042 | ||
6bff861d | 1043 | static int efx_mcdi_reset_mc(struct efx_nic *efx) |
afd4aea0 | 1044 | { |
59cfc479 | 1045 | MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN); |
afd4aea0 BH |
1046 | int rc; |
1047 | ||
1048 | BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0); | |
1049 | MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0); | |
1050 | rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf), | |
1051 | NULL, 0, NULL); | |
1052 | /* White is black, and up is down */ | |
1053 | if (rc == -EIO) | |
1054 | return 0; | |
1055 | if (rc == 0) | |
1056 | rc = -EIO; | |
62776d03 | 1057 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1058 | return rc; |
1059 | } | |
1060 | ||
6bff861d BH |
1061 | enum reset_type efx_mcdi_map_reset_reason(enum reset_type reason) |
1062 | { | |
1063 | return RESET_TYPE_RECOVER_OR_ALL; | |
1064 | } | |
1065 | ||
1066 | int efx_mcdi_reset(struct efx_nic *efx, enum reset_type method) | |
1067 | { | |
1068 | int rc; | |
1069 | ||
1070 | /* Recover from a failed assertion pre-reset */ | |
1071 | rc = efx_mcdi_handle_assertion(efx); | |
1072 | if (rc) | |
1073 | return rc; | |
1074 | ||
1075 | if (method == RESET_TYPE_WORLD) | |
1076 | return efx_mcdi_reset_mc(efx); | |
1077 | else | |
1078 | return efx_mcdi_reset_port(efx); | |
1079 | } | |
1080 | ||
d215697f | 1081 | static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type, |
1082 | const u8 *mac, int *id_out) | |
afd4aea0 | 1083 | { |
59cfc479 BH |
1084 | MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_SET_IN_LEN); |
1085 | MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_SET_OUT_LEN); | |
afd4aea0 BH |
1086 | size_t outlen; |
1087 | int rc; | |
1088 | ||
1089 | MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type); | |
1090 | MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE, | |
1091 | MC_CMD_FILTER_MODE_SIMPLE); | |
1092 | memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN); | |
1093 | ||
1094 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf), | |
1095 | outbuf, sizeof(outbuf), &outlen); | |
1096 | if (rc) | |
1097 | goto fail; | |
1098 | ||
1099 | if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) { | |
00bbb4a5 | 1100 | rc = -EIO; |
afd4aea0 BH |
1101 | goto fail; |
1102 | } | |
1103 | ||
1104 | *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID); | |
1105 | ||
1106 | return 0; | |
1107 | ||
1108 | fail: | |
1109 | *id_out = -1; | |
62776d03 | 1110 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1111 | return rc; |
1112 | ||
1113 | } | |
1114 | ||
1115 | ||
1116 | int | |
1117 | efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out) | |
1118 | { | |
1119 | return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out); | |
1120 | } | |
1121 | ||
1122 | ||
1123 | int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out) | |
1124 | { | |
59cfc479 | 1125 | MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_GET_OUT_LEN); |
afd4aea0 BH |
1126 | size_t outlen; |
1127 | int rc; | |
1128 | ||
1129 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0, | |
1130 | outbuf, sizeof(outbuf), &outlen); | |
1131 | if (rc) | |
1132 | goto fail; | |
1133 | ||
1134 | if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) { | |
00bbb4a5 | 1135 | rc = -EIO; |
afd4aea0 BH |
1136 | goto fail; |
1137 | } | |
1138 | ||
1139 | *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID); | |
1140 | ||
1141 | return 0; | |
1142 | ||
1143 | fail: | |
1144 | *id_out = -1; | |
62776d03 | 1145 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1146 | return rc; |
1147 | } | |
1148 | ||
1149 | ||
1150 | int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id) | |
1151 | { | |
59cfc479 | 1152 | MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_REMOVE_IN_LEN); |
afd4aea0 BH |
1153 | int rc; |
1154 | ||
1155 | MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id); | |
1156 | ||
1157 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf), | |
1158 | NULL, 0, NULL); | |
1159 | if (rc) | |
1160 | goto fail; | |
1161 | ||
1162 | return 0; | |
1163 | ||
1164 | fail: | |
62776d03 | 1165 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1166 | return rc; |
1167 | } | |
1168 | ||
cd2d5b52 BH |
1169 | int efx_mcdi_flush_rxqs(struct efx_nic *efx) |
1170 | { | |
1171 | struct efx_channel *channel; | |
1172 | struct efx_rx_queue *rx_queue; | |
c5bb0e98 BH |
1173 | MCDI_DECLARE_BUF(inbuf, |
1174 | MC_CMD_FLUSH_RX_QUEUES_IN_LEN(EFX_MAX_CHANNELS)); | |
cd2d5b52 BH |
1175 | int rc, count; |
1176 | ||
45078374 BH |
1177 | BUILD_BUG_ON(EFX_MAX_CHANNELS > |
1178 | MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM); | |
1179 | ||
cd2d5b52 BH |
1180 | count = 0; |
1181 | efx_for_each_channel(channel, efx) { | |
1182 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
1183 | if (rx_queue->flush_pending) { | |
1184 | rx_queue->flush_pending = false; | |
1185 | atomic_dec(&efx->rxq_flush_pending); | |
c5bb0e98 BH |
1186 | MCDI_SET_ARRAY_DWORD( |
1187 | inbuf, FLUSH_RX_QUEUES_IN_QID_OFST, | |
1188 | count, efx_rx_queue_index(rx_queue)); | |
1189 | count++; | |
cd2d5b52 BH |
1190 | } |
1191 | } | |
1192 | } | |
1193 | ||
c5bb0e98 BH |
1194 | rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf, |
1195 | MC_CMD_FLUSH_RX_QUEUES_IN_LEN(count), NULL, 0, NULL); | |
bbec969b | 1196 | WARN_ON(rc < 0); |
cd2d5b52 | 1197 | |
cd2d5b52 BH |
1198 | return rc; |
1199 | } | |
afd4aea0 BH |
1200 | |
1201 | int efx_mcdi_wol_filter_reset(struct efx_nic *efx) | |
1202 | { | |
1203 | int rc; | |
1204 | ||
1205 | rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL); | |
1206 | if (rc) | |
1207 | goto fail; | |
1208 | ||
1209 | return 0; | |
1210 | ||
1211 | fail: | |
62776d03 | 1212 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
afd4aea0 BH |
1213 | return rc; |
1214 | } | |
1215 |