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f0d37f42 | 1 | /**************************************************************************** |
f2b0befd BH |
2 | * Driver for Solarflare network controllers and boards |
3 | * Copyright 2009-2013 Solarflare Communications Inc. | |
f0d37f42 SH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | ||
11 | #ifndef MCDI_PCOL_H | |
12 | #define MCDI_PCOL_H | |
13 | ||
14 | /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ | |
15 | /* Power-on reset state */ | |
16 | #define MC_FW_STATE_POR (1) | |
17 | /* If this is set in MC_RESET_STATE_REG then it should be | |
18 | * possible to jump into IMEM without loading code from flash. */ | |
19 | #define MC_FW_WARM_BOOT_OK (2) | |
20 | /* The MC main image has started to boot. */ | |
21 | #define MC_FW_STATE_BOOTING (4) | |
22 | /* The Scheduler has started. */ | |
23 | #define MC_FW_STATE_SCHED (8) | |
f2b0befd BH |
24 | /* If this is set in MC_RESET_STATE_REG then it should be |
25 | * possible to jump into IMEM without loading code from flash. | |
26 | * Unlike a warm boot, assume DMEM has been reloaded, so that | |
27 | * the MC persistent data must be reinitialised. */ | |
28 | #define MC_FW_TEPID_BOOT_OK (16) | |
29 | /* BIST state has been initialized */ | |
30 | #define MC_FW_BIST_INIT_OK (128) | |
f0d37f42 | 31 | |
05a9320f BH |
32 | /* Siena MC shared memmory offsets */ |
33 | /* The 'doorbell' addresses are hard-wired to alert the MC when written */ | |
34 | #define MC_SMEM_P0_DOORBELL_OFST 0x000 | |
35 | #define MC_SMEM_P1_DOORBELL_OFST 0x004 | |
36 | /* The rest of these are firmware-defined */ | |
37 | #define MC_SMEM_P0_PDU_OFST 0x008 | |
38 | #define MC_SMEM_P1_PDU_OFST 0x108 | |
39 | #define MC_SMEM_PDU_LEN 0x100 | |
40 | #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 | |
41 | #define MC_SMEM_P0_STATUS_OFST 0x7f8 | |
42 | #define MC_SMEM_P1_STATUS_OFST 0x7fc | |
43 | ||
f0d37f42 SH |
44 | /* Values to be written to the per-port status dword in shared |
45 | * memory on reboot and assert */ | |
46 | #define MC_STATUS_DWORD_REBOOT (0xb007b007) | |
47 | #define MC_STATUS_DWORD_ASSERT (0xdeaddead) | |
48 | ||
f2b0befd BH |
49 | /* Check whether an mcfw version (in host order) belongs to a bootloader */ |
50 | #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) | |
51 | ||
f0d37f42 SH |
52 | /* The current version of the MCDI protocol. |
53 | * | |
54 | * Note that the ROM burnt into the card only talks V0, so at the very | |
55 | * least every driver must support version 0 and MCDI_PCOL_VERSION | |
56 | */ | |
f2b0befd | 57 | #define MCDI_PCOL_VERSION 2 |
f0d37f42 | 58 | |
05a9320f BH |
59 | /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ |
60 | ||
1aa8b471 | 61 | /* MCDI version 1 |
f0d37f42 | 62 | * |
f2b0befd | 63 | * Each MCDI request starts with an MCDI_HEADER, which is a 32bit |
f0d37f42 SH |
64 | * structure, filled in by the client. |
65 | * | |
66 | * 0 7 8 16 20 22 23 24 31 | |
67 | * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | | |
68 | * | | | | |
69 | * | | \--- Response | |
70 | * | \------- Error | |
71 | * \------------------------------ Resync (always set) | |
72 | * | |
73 | * The client writes it's request into MC shared memory, and rings the | |
74 | * doorbell. Each request is completed by either by the MC writting | |
75 | * back into shared memory, or by writting out an event. | |
76 | * | |
77 | * All MCDI commands support completion by shared memory response. Each | |
78 | * request may also contain additional data (accounted for by HEADER.LEN), | |
79 | * and some response's may also contain additional data (again, accounted | |
80 | * for by HEADER.LEN). | |
81 | * | |
82 | * Some MCDI commands support completion by event, in which any associated | |
83 | * response data is included in the event. | |
84 | * | |
85 | * The protocol requires one response to be delivered for every request, a | |
86 | * request should not be sent unless the response for the previous request | |
87 | * has been received (either by polling shared memory, or by receiving | |
88 | * an event). | |
89 | */ | |
90 | ||
91 | /** Request/Response structure */ | |
92 | #define MCDI_HEADER_OFST 0 | |
93 | #define MCDI_HEADER_CODE_LBN 0 | |
94 | #define MCDI_HEADER_CODE_WIDTH 7 | |
95 | #define MCDI_HEADER_RESYNC_LBN 7 | |
96 | #define MCDI_HEADER_RESYNC_WIDTH 1 | |
97 | #define MCDI_HEADER_DATALEN_LBN 8 | |
98 | #define MCDI_HEADER_DATALEN_WIDTH 8 | |
99 | #define MCDI_HEADER_SEQ_LBN 16 | |
f0d37f42 | 100 | #define MCDI_HEADER_SEQ_WIDTH 4 |
f2b0befd BH |
101 | #define MCDI_HEADER_RSVD_LBN 20 |
102 | #define MCDI_HEADER_RSVD_WIDTH 1 | |
103 | #define MCDI_HEADER_NOT_EPOCH_LBN 21 | |
104 | #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 | |
f0d37f42 SH |
105 | #define MCDI_HEADER_ERROR_LBN 22 |
106 | #define MCDI_HEADER_ERROR_WIDTH 1 | |
107 | #define MCDI_HEADER_RESPONSE_LBN 23 | |
108 | #define MCDI_HEADER_RESPONSE_WIDTH 1 | |
109 | #define MCDI_HEADER_XFLAGS_LBN 24 | |
110 | #define MCDI_HEADER_XFLAGS_WIDTH 8 | |
111 | /* Request response using event */ | |
112 | #define MCDI_HEADER_XFLAGS_EVREQ 0x01 | |
113 | ||
114 | /* Maximum number of payload bytes */ | |
d0c2ee99 | 115 | #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc |
f2b0befd BH |
116 | #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 |
117 | ||
118 | #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 | |
d0c2ee99 | 119 | |
f0d37f42 SH |
120 | |
121 | /* The MC can generate events for two reasons: | |
122 | * - To complete a shared memory request if XFLAGS_EVREQ was set | |
123 | * - As a notification (link state, i2c event), controlled | |
124 | * via MC_CMD_LOG_CTRL | |
125 | * | |
126 | * Both events share a common structure: | |
127 | * | |
128 | * 0 32 33 36 44 52 60 | |
129 | * | Data | Cont | Level | Src | Code | Rsvd | | |
130 | * | | |
131 | * \ There is another event pending in this notification | |
132 | * | |
133 | * If Code==CMDDONE, then the fields are further interpreted as: | |
134 | * | |
25985edc | 135 | * - LEVEL==INFO Command succeeded |
f0d37f42 SH |
136 | * - LEVEL==ERR Command failed |
137 | * | |
138 | * 0 8 16 24 32 | |
139 | * | Seq | Datalen | Errno | Rsvd | | |
140 | * | |
141 | * These fields are taken directly out of the standard MCDI header, i.e., | |
142 | * LEVEL==ERR, Datalen == 0 => Reboot | |
143 | * | |
144 | * Events can be squirted out of the UART (using LOG_CTRL) without a | |
145 | * MCDI header. An event can be distinguished from a MCDI response by | |
146 | * examining the first byte which is 0xc0. This corresponds to the | |
147 | * non-existent MCDI command MC_CMD_DEBUG_LOG. | |
148 | * | |
149 | * 0 7 8 | |
150 | * | command | Resync | = 0xc0 | |
151 | * | |
152 | * Since the event is written in big-endian byte order, this works | |
153 | * providing bits 56-63 of the event are 0xc0. | |
154 | * | |
155 | * 56 60 63 | |
156 | * | Rsvd | Code | = 0xc0 | |
157 | * | |
158 | * Which means for convenience the event code is 0xc for all MC | |
159 | * generated events. | |
160 | */ | |
161 | #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc | |
162 | ||
f0d37f42 | 163 | |
f2b0befd BH |
164 | /* Operation not permitted. */ |
165 | #define MC_CMD_ERR_EPERM 1 | |
f0d37f42 SH |
166 | /* Non-existent command target */ |
167 | #define MC_CMD_ERR_ENOENT 2 | |
168 | /* assert() has killed the MC */ | |
169 | #define MC_CMD_ERR_EINTR 4 | |
f2b0befd BH |
170 | /* I/O failure */ |
171 | #define MC_CMD_ERR_EIO 5 | |
172 | /* Try again */ | |
173 | #define MC_CMD_ERR_EAGAIN 11 | |
174 | /* Out of memory */ | |
175 | #define MC_CMD_ERR_ENOMEM 12 | |
f0d37f42 SH |
176 | /* Caller does not hold required locks */ |
177 | #define MC_CMD_ERR_EACCES 13 | |
178 | /* Resource is currently unavailable (e.g. lock contention) */ | |
179 | #define MC_CMD_ERR_EBUSY 16 | |
f2b0befd BH |
180 | /* No such device */ |
181 | #define MC_CMD_ERR_ENODEV 19 | |
f0d37f42 SH |
182 | /* Invalid argument to target */ |
183 | #define MC_CMD_ERR_EINVAL 22 | |
f2b0befd BH |
184 | /* Out of range */ |
185 | #define MC_CMD_ERR_ERANGE 34 | |
f0d37f42 SH |
186 | /* Non-recursive resource is already acquired */ |
187 | #define MC_CMD_ERR_EDEADLK 35 | |
188 | /* Operation not implemented */ | |
189 | #define MC_CMD_ERR_ENOSYS 38 | |
190 | /* Operation timed out */ | |
191 | #define MC_CMD_ERR_ETIME 62 | |
f2b0befd BH |
192 | /* Link has been severed */ |
193 | #define MC_CMD_ERR_ENOLINK 67 | |
194 | /* Protocol error */ | |
195 | #define MC_CMD_ERR_EPROTO 71 | |
196 | /* Operation not supported */ | |
197 | #define MC_CMD_ERR_ENOTSUP 95 | |
198 | /* Address not available */ | |
199 | #define MC_CMD_ERR_EADDRNOTAVAIL 99 | |
200 | /* Not connected */ | |
201 | #define MC_CMD_ERR_ENOTCONN 107 | |
202 | /* Operation already in progress */ | |
203 | #define MC_CMD_ERR_EALREADY 114 | |
204 | ||
205 | /* Resource allocation failed. */ | |
206 | #define MC_CMD_ERR_ALLOC_FAIL 0x1000 | |
207 | /* V-adaptor not found. */ | |
208 | #define MC_CMD_ERR_NO_VADAPTOR 0x1001 | |
209 | /* EVB port not found. */ | |
210 | #define MC_CMD_ERR_NO_EVB_PORT 0x1002 | |
211 | /* V-switch not found. */ | |
212 | #define MC_CMD_ERR_NO_VSWITCH 0x1003 | |
213 | /* Too many VLAN tags. */ | |
214 | #define MC_CMD_ERR_VLAN_LIMIT 0x1004 | |
215 | /* Bad PCI function number. */ | |
216 | #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 | |
217 | /* Invalid VLAN mode. */ | |
218 | #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 | |
219 | /* Invalid v-switch type. */ | |
220 | #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 | |
221 | /* Invalid v-port type. */ | |
222 | #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 | |
223 | /* MAC address exists. */ | |
224 | #define MC_CMD_ERR_MAC_EXIST 0x1009 | |
225 | /* Slave core not present */ | |
226 | #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a | |
f0d37f42 SH |
227 | |
228 | #define MC_CMD_ERR_CODE_OFST 0 | |
229 | ||
05a9320f BH |
230 | /* We define 8 "escape" commands to allow |
231 | for command number space extension */ | |
232 | ||
233 | #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 | |
234 | #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 | |
235 | #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A | |
236 | #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B | |
237 | #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C | |
238 | #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D | |
239 | #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E | |
240 | #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F | |
241 | ||
242 | /* Vectors in the boot ROM */ | |
243 | /* Point to the copycode entry point. */ | |
f2b0befd BH |
244 | #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) |
245 | #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) | |
05a9320f | 246 | /* Points to the recovery mode entry point. */ |
f2b0befd BH |
247 | #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) |
248 | #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) | |
f0d37f42 | 249 | |
f0d37f42 SH |
250 | /* The command set exported by the boot ROM (MCDI v0) */ |
251 | #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ | |
252 | (1 << MC_CMD_READ32) | \ | |
253 | (1 << MC_CMD_WRITE32) | \ | |
254 | (1 << MC_CMD_COPYCODE) | \ | |
255 | (1 << MC_CMD_GET_VERSION), \ | |
256 | 0, 0, 0 } | |
f0d37f42 | 257 | |
05a9320f BH |
258 | #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ |
259 | (MC_CMD_SENSOR_ENTRY_OFST + (_x)) | |
260 | ||
261 | #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ | |
262 | (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ | |
263 | MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ | |
264 | (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) | |
265 | ||
266 | #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ | |
267 | (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ | |
268 | MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ | |
269 | (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) | |
270 | ||
271 | #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ | |
272 | (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ | |
273 | MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ | |
274 | (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) | |
275 | ||
276 | ||
f2b0befd BH |
277 | /* Version 2 adds an optional argument to error returns: the errno value |
278 | * may be followed by the (0-based) number of the first argument that | |
279 | * could not be processed. | |
280 | */ | |
281 | #define MC_CMD_ERR_ARG_OFST 4 | |
282 | ||
283 | /* No space */ | |
284 | #define MC_CMD_ERR_ENOSPC 28 | |
285 | ||
05a9320f BH |
286 | /* MCDI_EVENT structuredef */ |
287 | #define MCDI_EVENT_LEN 8 | |
288 | #define MCDI_EVENT_CONT_LBN 32 | |
289 | #define MCDI_EVENT_CONT_WIDTH 1 | |
290 | #define MCDI_EVENT_LEVEL_LBN 33 | |
291 | #define MCDI_EVENT_LEVEL_WIDTH 3 | |
f2b0befd BH |
292 | /* enum: Info. */ |
293 | #define MCDI_EVENT_LEVEL_INFO 0x0 | |
294 | /* enum: Warning. */ | |
295 | #define MCDI_EVENT_LEVEL_WARN 0x1 | |
296 | /* enum: Error. */ | |
297 | #define MCDI_EVENT_LEVEL_ERR 0x2 | |
298 | /* enum: Fatal. */ | |
299 | #define MCDI_EVENT_LEVEL_FATAL 0x3 | |
05a9320f BH |
300 | #define MCDI_EVENT_DATA_OFST 0 |
301 | #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 | |
302 | #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 | |
303 | #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 | |
304 | #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 | |
305 | #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 | |
306 | #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 | |
307 | #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 | |
308 | #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 | |
309 | #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 | |
310 | #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 | |
f2b0befd BH |
311 | /* enum: 100Mbs */ |
312 | #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 | |
313 | /* enum: 1Gbs */ | |
314 | #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 | |
315 | /* enum: 10Gbs */ | |
316 | #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 | |
317 | /* enum: 40Gbs */ | |
318 | #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 | |
05a9320f BH |
319 | #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 |
320 | #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 | |
321 | #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 | |
322 | #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 | |
323 | #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 | |
324 | #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 | |
325 | #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 | |
326 | #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 | |
327 | #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 | |
328 | #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 | |
329 | #define MCDI_EVENT_FWALERT_DATA_LBN 8 | |
330 | #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 | |
331 | #define MCDI_EVENT_FWALERT_REASON_LBN 0 | |
332 | #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 | |
f2b0befd BH |
333 | /* enum: SRAM Access. */ |
334 | #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 | |
05a9320f BH |
335 | #define MCDI_EVENT_FLR_VF_LBN 0 |
336 | #define MCDI_EVENT_FLR_VF_WIDTH 8 | |
337 | #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 | |
338 | #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 | |
339 | #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 | |
340 | #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 | |
f2b0befd BH |
341 | /* enum: Descriptor loader reported failure */ |
342 | #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 | |
343 | /* enum: Descriptor ring empty and no EOP seen for packet */ | |
344 | #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 | |
345 | /* enum: Overlength packet */ | |
346 | #define MCDI_EVENT_TX_ERR_2BIG 0x3 | |
347 | /* enum: Malformed option descriptor */ | |
348 | #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 | |
349 | /* enum: Option descriptor part way through a packet */ | |
350 | #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 | |
351 | /* enum: DMA or PIO data access error */ | |
352 | #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 | |
05a9320f BH |
353 | #define MCDI_EVENT_TX_ERR_INFO_LBN 16 |
354 | #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 | |
f2b0befd BH |
355 | #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 |
356 | #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 | |
05a9320f BH |
357 | #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 |
358 | #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 | |
359 | #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 | |
360 | #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 | |
f2b0befd BH |
361 | /* enum: PLL lost lock */ |
362 | #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 | |
363 | /* enum: Filter overflow (PDMA) */ | |
364 | #define MCDI_EVENT_PTP_ERR_FILTER 0x2 | |
365 | /* enum: FIFO overflow (FPGA) */ | |
366 | #define MCDI_EVENT_PTP_ERR_FIFO 0x3 | |
367 | /* enum: Merge queue overflow */ | |
368 | #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 | |
369 | #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 | |
370 | #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 | |
371 | /* enum: AOE failed to load - no valid image? */ | |
372 | #define MCDI_EVENT_AOE_NO_LOAD 0x1 | |
373 | /* enum: AOE FC reported an exception */ | |
374 | #define MCDI_EVENT_AOE_FC_ASSERT 0x2 | |
375 | /* enum: AOE FC watchdogged */ | |
376 | #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 | |
377 | /* enum: AOE FC failed to start */ | |
378 | #define MCDI_EVENT_AOE_FC_NO_START 0x4 | |
379 | /* enum: Generic AOE fault - likely to have been reported via other means too | |
380 | * but intended for use by aoex driver. | |
381 | */ | |
382 | #define MCDI_EVENT_AOE_FAULT 0x5 | |
383 | /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ | |
384 | #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 | |
385 | /* enum: AOE loaded successfully */ | |
386 | #define MCDI_EVENT_AOE_LOAD 0x7 | |
387 | /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ | |
388 | #define MCDI_EVENT_AOE_DMA 0x8 | |
389 | /* enum: AOE byteblaster connected/disconnected (Connection status in | |
390 | * AOE_ERR_DATA) | |
391 | */ | |
392 | #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 | |
393 | #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 | |
394 | #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 | |
395 | #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 | |
396 | #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 | |
397 | #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 | |
398 | #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 | |
399 | #define MCDI_EVENT_RX_ERR_INFO_LBN 16 | |
400 | #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 | |
401 | #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 | |
402 | #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 | |
403 | #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 | |
404 | #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 | |
405 | #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 | |
406 | #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 | |
05a9320f BH |
407 | #define MCDI_EVENT_DATA_LBN 0 |
408 | #define MCDI_EVENT_DATA_WIDTH 32 | |
409 | #define MCDI_EVENT_SRC_LBN 36 | |
410 | #define MCDI_EVENT_SRC_WIDTH 8 | |
411 | #define MCDI_EVENT_EV_CODE_LBN 60 | |
412 | #define MCDI_EVENT_EV_CODE_WIDTH 4 | |
413 | #define MCDI_EVENT_CODE_LBN 44 | |
414 | #define MCDI_EVENT_CODE_WIDTH 8 | |
f2b0befd BH |
415 | /* enum: Bad assert. */ |
416 | #define MCDI_EVENT_CODE_BADSSERT 0x1 | |
417 | /* enum: PM Notice. */ | |
418 | #define MCDI_EVENT_CODE_PMNOTICE 0x2 | |
419 | /* enum: Command done. */ | |
420 | #define MCDI_EVENT_CODE_CMDDONE 0x3 | |
421 | /* enum: Link change. */ | |
422 | #define MCDI_EVENT_CODE_LINKCHANGE 0x4 | |
423 | /* enum: Sensor Event. */ | |
424 | #define MCDI_EVENT_CODE_SENSOREVT 0x5 | |
425 | /* enum: Schedule error. */ | |
426 | #define MCDI_EVENT_CODE_SCHEDERR 0x6 | |
427 | /* enum: Reboot. */ | |
428 | #define MCDI_EVENT_CODE_REBOOT 0x7 | |
429 | /* enum: Mac stats DMA. */ | |
430 | #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 | |
431 | /* enum: Firmware alert. */ | |
432 | #define MCDI_EVENT_CODE_FWALERT 0x9 | |
433 | /* enum: Function level reset. */ | |
434 | #define MCDI_EVENT_CODE_FLR 0xa | |
435 | /* enum: Transmit error */ | |
436 | #define MCDI_EVENT_CODE_TX_ERR 0xb | |
437 | /* enum: Tx flush has completed */ | |
438 | #define MCDI_EVENT_CODE_TX_FLUSH 0xc | |
439 | /* enum: PTP packet received timestamp */ | |
440 | #define MCDI_EVENT_CODE_PTP_RX 0xd | |
441 | /* enum: PTP NIC failure */ | |
442 | #define MCDI_EVENT_CODE_PTP_FAULT 0xe | |
443 | /* enum: PTP PPS event */ | |
444 | #define MCDI_EVENT_CODE_PTP_PPS 0xf | |
445 | /* enum: Rx flush has completed */ | |
446 | #define MCDI_EVENT_CODE_RX_FLUSH 0x10 | |
447 | /* enum: Receive error */ | |
448 | #define MCDI_EVENT_CODE_RX_ERR 0x11 | |
449 | /* enum: AOE fault */ | |
450 | #define MCDI_EVENT_CODE_AOE 0x12 | |
451 | /* enum: Network port calibration failed (VCAL). */ | |
452 | #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 | |
453 | /* enum: HW PPS event */ | |
454 | #define MCDI_EVENT_CODE_HW_PPS 0x14 | |
455 | /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and | |
456 | * a different format) | |
457 | */ | |
458 | #define MCDI_EVENT_CODE_MC_REBOOT 0x15 | |
459 | /* enum: the MC has detected a parity error */ | |
460 | #define MCDI_EVENT_CODE_PAR_ERR 0x16 | |
461 | /* enum: the MC has detected a correctable error */ | |
462 | #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 | |
463 | /* enum: the MC has detected an uncorrectable error */ | |
464 | #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 | |
465 | /* enum: Artificial event generated by host and posted via MC for test | |
466 | * purposes. | |
467 | */ | |
468 | #define MCDI_EVENT_CODE_TESTGEN 0xfa | |
05a9320f BH |
469 | #define MCDI_EVENT_CMDDONE_DATA_OFST 0 |
470 | #define MCDI_EVENT_CMDDONE_DATA_LBN 0 | |
471 | #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 | |
472 | #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 | |
473 | #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 | |
474 | #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 | |
475 | #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 | |
476 | #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 | |
477 | #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 | |
478 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 | |
479 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 | |
480 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 | |
481 | #define MCDI_EVENT_TX_ERR_DATA_OFST 0 | |
482 | #define MCDI_EVENT_TX_ERR_DATA_LBN 0 | |
483 | #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 | |
f2b0befd | 484 | /* Seconds field of timestamp */ |
05a9320f BH |
485 | #define MCDI_EVENT_PTP_SECONDS_OFST 0 |
486 | #define MCDI_EVENT_PTP_SECONDS_LBN 0 | |
487 | #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 | |
f2b0befd | 488 | /* Nanoseconds field of timestamp */ |
05a9320f BH |
489 | #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 |
490 | #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 | |
491 | #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 | |
f2b0befd | 492 | /* Lowest four bytes of sourceUUID from PTP packet */ |
05a9320f BH |
493 | #define MCDI_EVENT_PTP_UUID_OFST 0 |
494 | #define MCDI_EVENT_PTP_UUID_LBN 0 | |
495 | #define MCDI_EVENT_PTP_UUID_WIDTH 32 | |
f2b0befd BH |
496 | #define MCDI_EVENT_RX_ERR_DATA_OFST 0 |
497 | #define MCDI_EVENT_RX_ERR_DATA_LBN 0 | |
498 | #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 | |
499 | #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 | |
500 | #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 | |
501 | #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 | |
502 | #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 | |
503 | #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 | |
504 | #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 | |
505 | #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 | |
506 | #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 | |
507 | #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 | |
508 | ||
509 | /* FCDI_EVENT structuredef */ | |
510 | #define FCDI_EVENT_LEN 8 | |
511 | #define FCDI_EVENT_CONT_LBN 32 | |
512 | #define FCDI_EVENT_CONT_WIDTH 1 | |
513 | #define FCDI_EVENT_LEVEL_LBN 33 | |
514 | #define FCDI_EVENT_LEVEL_WIDTH 3 | |
515 | /* enum: Info. */ | |
516 | #define FCDI_EVENT_LEVEL_INFO 0x0 | |
517 | /* enum: Warning. */ | |
518 | #define FCDI_EVENT_LEVEL_WARN 0x1 | |
519 | /* enum: Error. */ | |
520 | #define FCDI_EVENT_LEVEL_ERR 0x2 | |
521 | /* enum: Fatal. */ | |
522 | #define FCDI_EVENT_LEVEL_FATAL 0x3 | |
523 | #define FCDI_EVENT_DATA_OFST 0 | |
524 | #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 | |
525 | #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 | |
526 | #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ | |
527 | #define FCDI_EVENT_LINK_UP 0x1 /* enum */ | |
528 | #define FCDI_EVENT_DATA_LBN 0 | |
529 | #define FCDI_EVENT_DATA_WIDTH 32 | |
530 | #define FCDI_EVENT_SRC_LBN 36 | |
531 | #define FCDI_EVENT_SRC_WIDTH 8 | |
532 | #define FCDI_EVENT_EV_CODE_LBN 60 | |
533 | #define FCDI_EVENT_EV_CODE_WIDTH 4 | |
534 | #define FCDI_EVENT_CODE_LBN 44 | |
535 | #define FCDI_EVENT_CODE_WIDTH 8 | |
536 | /* enum: The FC was rebooted. */ | |
537 | #define FCDI_EVENT_CODE_REBOOT 0x1 | |
538 | /* enum: Bad assert. */ | |
539 | #define FCDI_EVENT_CODE_ASSERT 0x2 | |
540 | /* enum: DDR3 test result. */ | |
541 | #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 | |
542 | /* enum: Link status. */ | |
543 | #define FCDI_EVENT_CODE_LINK_STATE 0x4 | |
544 | /* enum: A timed read is ready to be serviced. */ | |
545 | #define FCDI_EVENT_CODE_TIMED_READ 0x5 | |
546 | /* enum: One or more PPS IN events */ | |
547 | #define FCDI_EVENT_CODE_PPS_IN 0x6 | |
548 | /* enum: One or more PPS OUT events */ | |
549 | #define FCDI_EVENT_CODE_PPS_OUT 0x7 | |
550 | #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 | |
551 | #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 | |
552 | #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 | |
553 | #define FCDI_EVENT_ASSERT_TYPE_LBN 36 | |
554 | #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 | |
555 | #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 | |
556 | #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 | |
557 | #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 | |
558 | #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 | |
559 | #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 | |
560 | #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 | |
561 | #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 | |
562 | #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 | |
563 | #define FCDI_EVENT_PPS_COUNT_OFST 0 | |
564 | #define FCDI_EVENT_PPS_COUNT_LBN 0 | |
565 | #define FCDI_EVENT_PPS_COUNT_WIDTH 32 | |
566 | ||
567 | /* FCDI_EXTENDED_EVENT structuredef */ | |
568 | #define FCDI_EXTENDED_EVENT_LENMIN 16 | |
569 | #define FCDI_EXTENDED_EVENT_LENMAX 248 | |
570 | #define FCDI_EXTENDED_EVENT_LEN(num) (8+8*(num)) | |
571 | /* Number of timestamps following */ | |
572 | #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 | |
573 | #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 | |
574 | #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 | |
575 | /* Seconds field of a timestamp record */ | |
576 | #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 | |
577 | #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 | |
578 | #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 | |
579 | /* Nanoseconds field of a timestamp record */ | |
580 | #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 | |
581 | #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 | |
582 | #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 | |
583 | /* Timestamp records comprising the event */ | |
584 | #define FCDI_EXTENDED_EVENT_PPS_TIME_OFST 8 | |
585 | #define FCDI_EXTENDED_EVENT_PPS_TIME_LEN 8 | |
586 | #define FCDI_EXTENDED_EVENT_PPS_TIME_LO_OFST 8 | |
587 | #define FCDI_EXTENDED_EVENT_PPS_TIME_HI_OFST 12 | |
588 | #define FCDI_EXTENDED_EVENT_PPS_TIME_MINNUM 1 | |
589 | #define FCDI_EXTENDED_EVENT_PPS_TIME_MAXNUM 30 | |
590 | #define FCDI_EXTENDED_EVENT_PPS_TIME_LBN 64 | |
591 | #define FCDI_EXTENDED_EVENT_PPS_TIME_WIDTH 64 | |
05a9320f BH |
592 | |
593 | ||
594 | /***********************************/ | |
595 | /* MC_CMD_READ32 | |
596 | * Read multiple 32byte words from MC memory. | |
597 | */ | |
598 | #define MC_CMD_READ32 0x1 | |
599 | ||
600 | /* MC_CMD_READ32_IN msgrequest */ | |
601 | #define MC_CMD_READ32_IN_LEN 8 | |
602 | #define MC_CMD_READ32_IN_ADDR_OFST 0 | |
603 | #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 | |
604 | ||
605 | /* MC_CMD_READ32_OUT msgresponse */ | |
606 | #define MC_CMD_READ32_OUT_LENMIN 4 | |
607 | #define MC_CMD_READ32_OUT_LENMAX 252 | |
608 | #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) | |
609 | #define MC_CMD_READ32_OUT_BUFFER_OFST 0 | |
610 | #define MC_CMD_READ32_OUT_BUFFER_LEN 4 | |
611 | #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 | |
612 | #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 | |
613 | ||
614 | ||
615 | /***********************************/ | |
616 | /* MC_CMD_WRITE32 | |
617 | * Write multiple 32byte words to MC memory. | |
618 | */ | |
619 | #define MC_CMD_WRITE32 0x2 | |
620 | ||
621 | /* MC_CMD_WRITE32_IN msgrequest */ | |
622 | #define MC_CMD_WRITE32_IN_LENMIN 8 | |
623 | #define MC_CMD_WRITE32_IN_LENMAX 252 | |
624 | #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) | |
625 | #define MC_CMD_WRITE32_IN_ADDR_OFST 0 | |
626 | #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 | |
627 | #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 | |
628 | #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 | |
629 | #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 | |
630 | ||
631 | /* MC_CMD_WRITE32_OUT msgresponse */ | |
632 | #define MC_CMD_WRITE32_OUT_LEN 0 | |
633 | ||
634 | ||
635 | /***********************************/ | |
636 | /* MC_CMD_COPYCODE | |
637 | * Copy MC code between two locations and jump. | |
638 | */ | |
639 | #define MC_CMD_COPYCODE 0x3 | |
640 | ||
641 | /* MC_CMD_COPYCODE_IN msgrequest */ | |
642 | #define MC_CMD_COPYCODE_IN_LEN 16 | |
f2b0befd | 643 | /* Source address */ |
05a9320f | 644 | #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 |
f2b0befd BH |
645 | /* enum: Entering the main image via a copy of a single word from and to this |
646 | * address indicates that it should not attempt to start the datapath CPUs. | |
647 | * This is useful for certain soft rebooting scenarios. (Huntington only) | |
648 | */ | |
649 | #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 | |
650 | /* enum: Entering the main image via a copy of a single word from and to this | |
651 | * address indicates that it should not attempt to parse any configuration from | |
652 | * flash. (In addition, the datapath CPUs will not be started, as for | |
653 | * MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR above.) This is useful for | |
654 | * certain soft rebooting scenarios. (Huntington only) | |
655 | */ | |
656 | #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc | |
657 | /* Destination address */ | |
05a9320f BH |
658 | #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 |
659 | #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 | |
f2b0befd | 660 | /* Address of where to jump after copy. */ |
05a9320f | 661 | #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 |
f2b0befd BH |
662 | /* enum: Control should return to the caller rather than jumping */ |
663 | #define MC_CMD_COPYCODE_JUMP_NONE 0x1 | |
05a9320f BH |
664 | |
665 | /* MC_CMD_COPYCODE_OUT msgresponse */ | |
666 | #define MC_CMD_COPYCODE_OUT_LEN 0 | |
667 | ||
668 | ||
669 | /***********************************/ | |
670 | /* MC_CMD_SET_FUNC | |
f2b0befd | 671 | * Select function for function-specific commands. |
05a9320f BH |
672 | */ |
673 | #define MC_CMD_SET_FUNC 0x4 | |
674 | ||
675 | /* MC_CMD_SET_FUNC_IN msgrequest */ | |
676 | #define MC_CMD_SET_FUNC_IN_LEN 4 | |
f2b0befd | 677 | /* Set function */ |
05a9320f BH |
678 | #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 |
679 | ||
680 | /* MC_CMD_SET_FUNC_OUT msgresponse */ | |
681 | #define MC_CMD_SET_FUNC_OUT_LEN 0 | |
682 | ||
683 | ||
684 | /***********************************/ | |
685 | /* MC_CMD_GET_BOOT_STATUS | |
f2b0befd | 686 | * Get the instruction address from which the MC booted. |
05a9320f BH |
687 | */ |
688 | #define MC_CMD_GET_BOOT_STATUS 0x5 | |
689 | ||
690 | /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ | |
691 | #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 | |
692 | ||
693 | /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ | |
694 | #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 | |
f2b0befd | 695 | /* ?? */ |
05a9320f | 696 | #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 |
f2b0befd BH |
697 | /* enum: indicates that the MC wasn't flash booted */ |
698 | #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef | |
05a9320f BH |
699 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 |
700 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 | |
701 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 | |
702 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 | |
703 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 | |
704 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 | |
705 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 | |
f0d37f42 | 706 | |
f0d37f42 | 707 | |
05a9320f BH |
708 | /***********************************/ |
709 | /* MC_CMD_GET_ASSERTS | |
f2b0befd BH |
710 | * Get (and optionally clear) the current assertion status. Only |
711 | * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other | |
712 | * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS | |
f0d37f42 | 713 | */ |
05a9320f | 714 | #define MC_CMD_GET_ASSERTS 0x6 |
f0d37f42 | 715 | |
05a9320f BH |
716 | /* MC_CMD_GET_ASSERTS_IN msgrequest */ |
717 | #define MC_CMD_GET_ASSERTS_IN_LEN 4 | |
f2b0befd | 718 | /* Set to clear assertion */ |
05a9320f BH |
719 | #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 |
720 | ||
721 | /* MC_CMD_GET_ASSERTS_OUT msgresponse */ | |
722 | #define MC_CMD_GET_ASSERTS_OUT_LEN 140 | |
f2b0befd | 723 | /* Assertion status flag. */ |
05a9320f | 724 | #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 |
f2b0befd BH |
725 | /* enum: No assertions have failed. */ |
726 | #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 | |
727 | /* enum: A system-level assertion has failed. */ | |
728 | #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 | |
729 | /* enum: A thread-level assertion has failed. */ | |
730 | #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 | |
731 | /* enum: The system was reset by the watchdog. */ | |
732 | #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 | |
733 | /* enum: An illegal address trap stopped the system (huntington and later) */ | |
734 | #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 | |
735 | /* Failing PC value */ | |
05a9320f | 736 | #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 |
f2b0befd | 737 | /* Saved GP regs */ |
05a9320f BH |
738 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 |
739 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 | |
740 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 | |
f2b0befd | 741 | /* Failing thread address */ |
05a9320f BH |
742 | #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 |
743 | #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 | |
f0d37f42 | 744 | |
05a9320f BH |
745 | |
746 | /***********************************/ | |
747 | /* MC_CMD_LOG_CTRL | |
748 | * Configure the output stream for various events and messages. | |
749 | */ | |
750 | #define MC_CMD_LOG_CTRL 0x7 | |
751 | ||
752 | /* MC_CMD_LOG_CTRL_IN msgrequest */ | |
753 | #define MC_CMD_LOG_CTRL_IN_LEN 8 | |
f2b0befd | 754 | /* Log destination */ |
05a9320f | 755 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 |
f2b0befd BH |
756 | /* enum: UART. */ |
757 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 | |
758 | /* enum: Event queue. */ | |
759 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 | |
05a9320f BH |
760 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 |
761 | ||
762 | /* MC_CMD_LOG_CTRL_OUT msgresponse */ | |
763 | #define MC_CMD_LOG_CTRL_OUT_LEN 0 | |
764 | ||
765 | ||
766 | /***********************************/ | |
767 | /* MC_CMD_GET_VERSION | |
768 | * Get version information about the MC firmware. | |
769 | */ | |
770 | #define MC_CMD_GET_VERSION 0x8 | |
771 | ||
772 | /* MC_CMD_GET_VERSION_IN msgrequest */ | |
773 | #define MC_CMD_GET_VERSION_IN_LEN 0 | |
774 | ||
f2b0befd BH |
775 | /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ |
776 | #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 | |
777 | /* placeholder, set to 0 */ | |
778 | #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 | |
779 | ||
780 | /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ | |
05a9320f BH |
781 | #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 |
782 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 | |
f2b0befd BH |
783 | /* enum: Reserved version number to indicate "any" version. */ |
784 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff | |
785 | /* enum: Bootrom version value for Siena. */ | |
786 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 | |
787 | /* enum: Bootrom version value for Huntington. */ | |
788 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 | |
05a9320f BH |
789 | |
790 | /* MC_CMD_GET_VERSION_OUT msgresponse */ | |
791 | #define MC_CMD_GET_VERSION_OUT_LEN 32 | |
792 | /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ | |
793 | /* Enum values, see field(s): */ | |
794 | /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ | |
795 | #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 | |
f2b0befd | 796 | /* 128bit mask of functions supported by the current firmware */ |
05a9320f BH |
797 | #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 |
798 | #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 | |
799 | #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 | |
800 | #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 | |
801 | #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 | |
802 | #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 | |
803 | ||
f2b0befd BH |
804 | /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ |
805 | #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 | |
806 | /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ | |
807 | /* Enum values, see field(s): */ | |
808 | /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ | |
809 | #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 | |
810 | /* 128bit mask of functions supported by the current firmware */ | |
811 | #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 | |
812 | #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 | |
813 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 | |
814 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 | |
815 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 | |
816 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 | |
817 | /* extra info */ | |
818 | #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 | |
819 | #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 | |
05a9320f BH |
820 | |
821 | ||
822 | /***********************************/ | |
823 | /* MC_CMD_PTP | |
824 | * Perform PTP operation | |
825 | */ | |
826 | #define MC_CMD_PTP 0xb | |
827 | ||
828 | /* MC_CMD_PTP_IN msgrequest */ | |
829 | #define MC_CMD_PTP_IN_LEN 1 | |
f2b0befd | 830 | /* PTP operation code */ |
05a9320f BH |
831 | #define MC_CMD_PTP_IN_OP_OFST 0 |
832 | #define MC_CMD_PTP_IN_OP_LEN 1 | |
f2b0befd BH |
833 | /* enum: Enable PTP packet timestamping operation. */ |
834 | #define MC_CMD_PTP_OP_ENABLE 0x1 | |
835 | /* enum: Disable PTP packet timestamping operation. */ | |
836 | #define MC_CMD_PTP_OP_DISABLE 0x2 | |
837 | /* enum: Send a PTP packet. */ | |
838 | #define MC_CMD_PTP_OP_TRANSMIT 0x3 | |
839 | /* enum: Read the current NIC time. */ | |
840 | #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 | |
841 | /* enum: Get the current PTP status. */ | |
842 | #define MC_CMD_PTP_OP_STATUS 0x5 | |
843 | /* enum: Adjust the PTP NIC's time. */ | |
844 | #define MC_CMD_PTP_OP_ADJUST 0x6 | |
845 | /* enum: Synchronize host and NIC time. */ | |
846 | #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 | |
847 | /* enum: Basic manufacturing tests. */ | |
848 | #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 | |
849 | /* enum: Packet based manufacturing tests. */ | |
850 | #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 | |
851 | /* enum: Reset some of the PTP related statistics */ | |
852 | #define MC_CMD_PTP_OP_RESET_STATS 0xa | |
853 | /* enum: Debug operations to MC. */ | |
854 | #define MC_CMD_PTP_OP_DEBUG 0xb | |
855 | /* enum: Read an FPGA register */ | |
856 | #define MC_CMD_PTP_OP_FPGAREAD 0xc | |
857 | /* enum: Write an FPGA register */ | |
858 | #define MC_CMD_PTP_OP_FPGAWRITE 0xd | |
859 | /* enum: Apply an offset to the NIC clock */ | |
860 | #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe | |
861 | /* enum: Change Apply an offset to the NIC clock */ | |
862 | #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf | |
863 | /* enum: Set the MC packet filter VLAN tags for received PTP packets */ | |
864 | #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 | |
865 | /* enum: Set the MC packet filter UUID for received PTP packets */ | |
866 | #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 | |
867 | /* enum: Set the MC packet filter Domain for received PTP packets */ | |
868 | #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 | |
869 | /* enum: Set the clock source */ | |
870 | #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 | |
871 | /* enum: Reset value of Timer Reg. */ | |
872 | #define MC_CMD_PTP_OP_RST_CLK 0x14 | |
873 | /* enum: Enable the forwarding of PPS events to the host */ | |
874 | #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 | |
875 | /* enum: Above this for future use. */ | |
876 | #define MC_CMD_PTP_OP_MAX 0x16 | |
05a9320f BH |
877 | |
878 | /* MC_CMD_PTP_IN_ENABLE msgrequest */ | |
879 | #define MC_CMD_PTP_IN_ENABLE_LEN 16 | |
880 | #define MC_CMD_PTP_IN_CMD_OFST 0 | |
881 | #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 | |
f2b0befd | 882 | /* Event queue for PTP events */ |
05a9320f | 883 | #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 |
f2b0befd | 884 | /* PTP timestamping mode */ |
05a9320f | 885 | #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 |
f2b0befd BH |
886 | /* enum: PTP, version 1 */ |
887 | #define MC_CMD_PTP_MODE_V1 0x0 | |
888 | /* enum: PTP, version 1, with VLAN headers - deprecated */ | |
889 | #define MC_CMD_PTP_MODE_V1_VLAN 0x1 | |
890 | /* enum: PTP, version 2 */ | |
891 | #define MC_CMD_PTP_MODE_V2 0x2 | |
892 | /* enum: PTP, version 2, with VLAN headers - deprecated */ | |
893 | #define MC_CMD_PTP_MODE_V2_VLAN 0x3 | |
894 | /* enum: PTP, version 2, with improved UUID filtering */ | |
895 | #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 | |
896 | /* enum: FCoE (seconds and microseconds) */ | |
897 | #define MC_CMD_PTP_MODE_FCOE 0x5 | |
05a9320f BH |
898 | |
899 | /* MC_CMD_PTP_IN_DISABLE msgrequest */ | |
900 | #define MC_CMD_PTP_IN_DISABLE_LEN 8 | |
901 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
902 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
903 | ||
904 | /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ | |
905 | #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 | |
576eda8b | 906 | #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 |
05a9320f BH |
907 | #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) |
908 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
909 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 910 | /* Transmit packet length */ |
05a9320f | 911 | #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 |
f2b0befd | 912 | /* Transmit packet data */ |
05a9320f BH |
913 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 |
914 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 | |
915 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 | |
576eda8b | 916 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 |
05a9320f BH |
917 | |
918 | /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ | |
919 | #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 | |
920 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
921 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
922 | ||
923 | /* MC_CMD_PTP_IN_STATUS msgrequest */ | |
924 | #define MC_CMD_PTP_IN_STATUS_LEN 8 | |
925 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
926 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
927 | ||
928 | /* MC_CMD_PTP_IN_ADJUST msgrequest */ | |
929 | #define MC_CMD_PTP_IN_ADJUST_LEN 24 | |
930 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
931 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 932 | /* Frequency adjustment 40 bit fixed point ns */ |
05a9320f BH |
933 | #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 |
934 | #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 | |
935 | #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 | |
936 | #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 | |
f2b0befd BH |
937 | /* enum: Number of fractional bits in frequency adjustment */ |
938 | #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 | |
939 | /* Time adjustment in seconds */ | |
05a9320f | 940 | #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 |
f2b0befd | 941 | /* Time adjustment in nanoseconds */ |
05a9320f BH |
942 | #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 |
943 | ||
944 | /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ | |
945 | #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 | |
946 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
947 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 948 | /* Number of time readings to capture */ |
05a9320f | 949 | #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 |
f2b0befd BH |
950 | /* Host address in which to write "synchronization started" indication (64 |
951 | * bits) | |
952 | */ | |
05a9320f BH |
953 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 |
954 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 | |
955 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 | |
956 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 | |
957 | ||
958 | /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ | |
959 | #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 | |
960 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
961 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
962 | ||
963 | /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ | |
964 | #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 | |
965 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
966 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 967 | /* Enable or disable packet testing */ |
05a9320f BH |
968 | #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 |
969 | ||
970 | /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ | |
971 | #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 | |
972 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
f2b0befd | 973 | /* Reset PTP statistics */ |
05a9320f BH |
974 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
975 | ||
976 | /* MC_CMD_PTP_IN_DEBUG msgrequest */ | |
977 | #define MC_CMD_PTP_IN_DEBUG_LEN 12 | |
978 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
979 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 980 | /* Debug operations */ |
05a9320f BH |
981 | #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 |
982 | ||
f2b0befd BH |
983 | /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ |
984 | #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 | |
985 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
986 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
987 | #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 | |
988 | #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 | |
989 | ||
990 | /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ | |
991 | #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 | |
992 | #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 | |
993 | #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) | |
994 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
995 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
996 | #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 | |
997 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 | |
998 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 | |
999 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 | |
1000 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 | |
1001 | ||
1002 | /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ | |
1003 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 | |
1004 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1005 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1006 | /* Time adjustment in seconds */ | |
1007 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 | |
1008 | /* Time adjustment in nanoseconds */ | |
1009 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 | |
1010 | ||
1011 | /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ | |
1012 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 | |
1013 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1014 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1015 | /* Frequency adjustment 40 bit fixed point ns */ | |
1016 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 | |
1017 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 | |
1018 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 | |
1019 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 | |
1020 | /* enum: Number of fractional bits in frequency adjustment */ | |
1021 | /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ | |
1022 | ||
1023 | /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ | |
1024 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 | |
1025 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1026 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1027 | /* Number of VLAN tags, 0 if not VLAN */ | |
1028 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 | |
1029 | /* Set of VLAN tags to filter against */ | |
1030 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 | |
1031 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 | |
1032 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 | |
1033 | ||
1034 | /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ | |
1035 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 | |
1036 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1037 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1038 | /* 1 to enable UUID filtering, 0 to disable */ | |
1039 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 | |
1040 | /* UUID to filter against */ | |
1041 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 | |
1042 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 | |
1043 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 | |
1044 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 | |
1045 | ||
1046 | /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ | |
1047 | #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 | |
1048 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1049 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1050 | /* 1 to enable Domain filtering, 0 to disable */ | |
1051 | #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 | |
1052 | /* Domain number to filter against */ | |
1053 | #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 | |
1054 | ||
1055 | /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ | |
1056 | #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 | |
1057 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1058 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1059 | /* Set the clock source. */ | |
1060 | #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 | |
1061 | /* enum: Internal. */ | |
1062 | #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 | |
1063 | /* enum: External. */ | |
1064 | #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 | |
1065 | ||
1066 | /* MC_CMD_PTP_IN_RST_CLK msgrequest */ | |
1067 | #define MC_CMD_PTP_IN_RST_CLK_LEN 8 | |
1068 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1069 | /* Reset value of Timer Reg. */ | |
1070 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1071 | ||
1072 | /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ | |
1073 | #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 | |
1074 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1075 | /* Enable or disable */ | |
1076 | #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 | |
1077 | /* enum: Enable */ | |
1078 | #define MC_CMD_PTP_ENABLE_PPS 0x0 | |
1079 | /* enum: Disable */ | |
1080 | #define MC_CMD_PTP_DISABLE_PPS 0x1 | |
1081 | /* Queueid to send events back */ | |
1082 | #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 | |
1083 | ||
05a9320f BH |
1084 | /* MC_CMD_PTP_OUT msgresponse */ |
1085 | #define MC_CMD_PTP_OUT_LEN 0 | |
1086 | ||
1087 | /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ | |
1088 | #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 | |
f2b0befd | 1089 | /* Value of seconds timestamp */ |
05a9320f | 1090 | #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 |
f2b0befd | 1091 | /* Value of nanoseconds timestamp */ |
05a9320f BH |
1092 | #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 |
1093 | ||
1094 | /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ | |
1095 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 | |
f2b0befd | 1096 | /* Value of seconds timestamp */ |
05a9320f | 1097 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 |
f2b0befd | 1098 | /* Value of nanoseconds timestamp */ |
05a9320f BH |
1099 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 |
1100 | ||
1101 | /* MC_CMD_PTP_OUT_STATUS msgresponse */ | |
1102 | #define MC_CMD_PTP_OUT_STATUS_LEN 64 | |
f2b0befd | 1103 | /* Frequency of NIC's hardware clock */ |
05a9320f | 1104 | #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 |
f2b0befd | 1105 | /* Number of packets transmitted and timestamped */ |
05a9320f | 1106 | #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 |
f2b0befd | 1107 | /* Number of packets received and timestamped */ |
05a9320f | 1108 | #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 |
f2b0befd | 1109 | /* Number of packets timestamped by the FPGA */ |
05a9320f | 1110 | #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 |
f2b0befd | 1111 | /* Number of packets filter matched */ |
05a9320f | 1112 | #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 |
f2b0befd | 1113 | /* Number of packets not filter matched */ |
05a9320f | 1114 | #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 |
f2b0befd | 1115 | /* Number of PPS overflows (noise on input?) */ |
05a9320f | 1116 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 |
f2b0befd | 1117 | /* Number of PPS bad periods */ |
05a9320f | 1118 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 |
f2b0befd | 1119 | /* Minimum period of PPS pulse */ |
05a9320f | 1120 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 |
f2b0befd | 1121 | /* Maximum period of PPS pulse */ |
05a9320f | 1122 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 |
f2b0befd | 1123 | /* Last period of PPS pulse */ |
05a9320f | 1124 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 |
f2b0befd | 1125 | /* Mean period of PPS pulse */ |
05a9320f | 1126 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 |
f2b0befd | 1127 | /* Minimum offset of PPS pulse (signed) */ |
05a9320f | 1128 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 |
f2b0befd | 1129 | /* Maximum offset of PPS pulse (signed) */ |
05a9320f | 1130 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 |
f2b0befd | 1131 | /* Last offset of PPS pulse (signed) */ |
05a9320f | 1132 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 |
f2b0befd | 1133 | /* Mean offset of PPS pulse (signed) */ |
05a9320f BH |
1134 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 |
1135 | ||
1136 | /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ | |
1137 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 | |
1138 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 | |
1139 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) | |
f2b0befd | 1140 | /* A set of host and NIC times */ |
05a9320f BH |
1141 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 |
1142 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 | |
1143 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 | |
1144 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 | |
f2b0befd | 1145 | /* Host time immediately before NIC's hardware clock read */ |
05a9320f | 1146 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 |
f2b0befd | 1147 | /* Value of seconds timestamp */ |
05a9320f | 1148 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 |
f2b0befd | 1149 | /* Value of nanoseconds timestamp */ |
05a9320f | 1150 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 |
f2b0befd | 1151 | /* Host time immediately after NIC's hardware clock read */ |
05a9320f | 1152 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 |
f2b0befd | 1153 | /* Number of nanoseconds waited after reading NIC's hardware clock */ |
05a9320f BH |
1154 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 |
1155 | ||
1156 | /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ | |
1157 | #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 | |
f2b0befd | 1158 | /* Results of testing */ |
05a9320f | 1159 | #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 |
f2b0befd BH |
1160 | /* enum: Successful test */ |
1161 | #define MC_CMD_PTP_MANF_SUCCESS 0x0 | |
1162 | /* enum: FPGA load failed */ | |
1163 | #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 | |
1164 | /* enum: FPGA version invalid */ | |
1165 | #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 | |
1166 | /* enum: FPGA registers incorrect */ | |
1167 | #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 | |
1168 | /* enum: Oscillator possibly not working? */ | |
1169 | #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 | |
1170 | /* enum: Timestamps not increasing */ | |
1171 | #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 | |
1172 | /* enum: Mismatched packet count */ | |
1173 | #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 | |
1174 | /* enum: Mismatched packet count (Siena filter and FPGA) */ | |
1175 | #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 | |
1176 | /* enum: Not enough packets to perform timestamp check */ | |
1177 | #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 | |
1178 | /* enum: Timestamp trigger GPIO not working */ | |
1179 | #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 | |
1180 | /* Presence of external oscillator */ | |
05a9320f BH |
1181 | #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 |
1182 | ||
1183 | /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ | |
1184 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 | |
f2b0befd | 1185 | /* Results of testing */ |
05a9320f | 1186 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 |
f2b0befd | 1187 | /* Number of packets received by FPGA */ |
05a9320f | 1188 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 |
f2b0befd | 1189 | /* Number of packets received by Siena filters */ |
05a9320f BH |
1190 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 |
1191 | ||
f2b0befd BH |
1192 | /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ |
1193 | #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 | |
1194 | #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 | |
1195 | #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) | |
1196 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 | |
1197 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 | |
1198 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 | |
1199 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 | |
1200 | ||
05a9320f BH |
1201 | |
1202 | /***********************************/ | |
1203 | /* MC_CMD_CSR_READ32 | |
1204 | * Read 32bit words from the indirect memory map. | |
1205 | */ | |
1206 | #define MC_CMD_CSR_READ32 0xc | |
1207 | ||
1208 | /* MC_CMD_CSR_READ32_IN msgrequest */ | |
1209 | #define MC_CMD_CSR_READ32_IN_LEN 12 | |
f2b0befd | 1210 | /* Address */ |
05a9320f BH |
1211 | #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 |
1212 | #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 | |
1213 | #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 | |
1214 | ||
1215 | /* MC_CMD_CSR_READ32_OUT msgresponse */ | |
1216 | #define MC_CMD_CSR_READ32_OUT_LENMIN 4 | |
1217 | #define MC_CMD_CSR_READ32_OUT_LENMAX 252 | |
1218 | #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) | |
f2b0befd | 1219 | /* The last dword is the status, not a value read */ |
05a9320f BH |
1220 | #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 |
1221 | #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 | |
1222 | #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 | |
1223 | #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 | |
1224 | ||
1225 | ||
1226 | /***********************************/ | |
1227 | /* MC_CMD_CSR_WRITE32 | |
1228 | * Write 32bit dwords to the indirect memory map. | |
1229 | */ | |
1230 | #define MC_CMD_CSR_WRITE32 0xd | |
1231 | ||
1232 | /* MC_CMD_CSR_WRITE32_IN msgrequest */ | |
1233 | #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 | |
1234 | #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 | |
1235 | #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) | |
f2b0befd | 1236 | /* Address */ |
05a9320f BH |
1237 | #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 |
1238 | #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 | |
1239 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 | |
1240 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 | |
1241 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 | |
1242 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 | |
1243 | ||
1244 | /* MC_CMD_CSR_WRITE32_OUT msgresponse */ | |
1245 | #define MC_CMD_CSR_WRITE32_OUT_LEN 4 | |
1246 | #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 | |
1247 | ||
1248 | ||
f2b0befd BH |
1249 | /***********************************/ |
1250 | /* MC_CMD_HP | |
1251 | * These commands are used for HP related features. They are grouped under one | |
1252 | * MCDI command to avoid creating too many MCDI commands. | |
1253 | */ | |
1254 | #define MC_CMD_HP 0x54 | |
1255 | ||
1256 | /* MC_CMD_HP_IN msgrequest */ | |
1257 | #define MC_CMD_HP_IN_LEN 16 | |
1258 | /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at | |
1259 | * the specified address with the specified interval.When address is NULL, | |
1260 | * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current | |
1261 | * state / 2: (debug) Show temperature reported by one of the supported | |
1262 | * sensors. | |
1263 | */ | |
1264 | #define MC_CMD_HP_IN_SUBCMD_OFST 0 | |
1265 | /* enum: OCSD (Option Card Sensor Data) sub-command. */ | |
1266 | #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 | |
1267 | /* enum: Last known valid HP sub-command. */ | |
1268 | #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 | |
1269 | /* The address to the array of sensor fields. (Or NULL to use a sub-command.) | |
1270 | */ | |
1271 | #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 | |
1272 | #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 | |
1273 | #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 | |
1274 | #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 | |
1275 | /* The requested update interval, in seconds. (Or the sub-command if ADDR is | |
1276 | * NULL.) | |
1277 | */ | |
1278 | #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 | |
1279 | ||
1280 | /* MC_CMD_HP_OUT msgresponse */ | |
1281 | #define MC_CMD_HP_OUT_LEN 4 | |
1282 | #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 | |
1283 | /* enum: OCSD stopped for this card. */ | |
1284 | #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 | |
1285 | /* enum: OCSD was successfully started with the address provided. */ | |
1286 | #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 | |
1287 | /* enum: OCSD was already started for this card. */ | |
1288 | #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 | |
1289 | ||
1290 | ||
05a9320f BH |
1291 | /***********************************/ |
1292 | /* MC_CMD_STACKINFO | |
1293 | * Get stack information. | |
1294 | */ | |
1295 | #define MC_CMD_STACKINFO 0xf | |
1296 | ||
1297 | /* MC_CMD_STACKINFO_IN msgrequest */ | |
1298 | #define MC_CMD_STACKINFO_IN_LEN 0 | |
1299 | ||
1300 | /* MC_CMD_STACKINFO_OUT msgresponse */ | |
1301 | #define MC_CMD_STACKINFO_OUT_LENMIN 12 | |
1302 | #define MC_CMD_STACKINFO_OUT_LENMAX 252 | |
1303 | #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) | |
f2b0befd | 1304 | /* (thread ptr, stack size, free space) for each thread in system */ |
05a9320f BH |
1305 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 |
1306 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 | |
1307 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 | |
1308 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 | |
1309 | ||
1310 | ||
1311 | /***********************************/ | |
1312 | /* MC_CMD_MDIO_READ | |
1313 | * MDIO register read. | |
f0d37f42 SH |
1314 | */ |
1315 | #define MC_CMD_MDIO_READ 0x10 | |
f0d37f42 | 1316 | |
05a9320f BH |
1317 | /* MC_CMD_MDIO_READ_IN msgrequest */ |
1318 | #define MC_CMD_MDIO_READ_IN_LEN 16 | |
f2b0befd BH |
1319 | /* Bus number; there are two MDIO buses: one for the internal PHY, and one for |
1320 | * external devices. | |
1321 | */ | |
05a9320f | 1322 | #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 |
f2b0befd BH |
1323 | /* enum: Internal. */ |
1324 | #define MC_CMD_MDIO_BUS_INTERNAL 0x0 | |
1325 | /* enum: External. */ | |
1326 | #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 | |
1327 | /* Port address */ | |
05a9320f | 1328 | #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 |
f2b0befd | 1329 | /* Device Address or clause 22. */ |
05a9320f | 1330 | #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 |
f2b0befd BH |
1331 | /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you |
1332 | * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. | |
1333 | */ | |
1334 | #define MC_CMD_MDIO_CLAUSE22 0x20 | |
1335 | /* Address */ | |
05a9320f | 1336 | #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 |
f0d37f42 | 1337 | |
05a9320f BH |
1338 | /* MC_CMD_MDIO_READ_OUT msgresponse */ |
1339 | #define MC_CMD_MDIO_READ_OUT_LEN 8 | |
f2b0befd | 1340 | /* Value */ |
05a9320f | 1341 | #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 |
f2b0befd BH |
1342 | /* Status the MDIO commands return the raw status bits from the MDIO block. A |
1343 | * "good" transaction should have the DONE bit set and all other bits clear. | |
1344 | */ | |
05a9320f | 1345 | #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 |
f2b0befd BH |
1346 | /* enum: Good. */ |
1347 | #define MC_CMD_MDIO_STATUS_GOOD 0x8 | |
f0d37f42 | 1348 | |
05a9320f BH |
1349 | |
1350 | /***********************************/ | |
1351 | /* MC_CMD_MDIO_WRITE | |
1352 | * MDIO register write. | |
f0d37f42 | 1353 | */ |
05a9320f | 1354 | #define MC_CMD_MDIO_WRITE 0x11 |
f0d37f42 | 1355 | |
05a9320f BH |
1356 | /* MC_CMD_MDIO_WRITE_IN msgrequest */ |
1357 | #define MC_CMD_MDIO_WRITE_IN_LEN 20 | |
f2b0befd BH |
1358 | /* Bus number; there are two MDIO buses: one for the internal PHY, and one for |
1359 | * external devices. | |
1360 | */ | |
05a9320f | 1361 | #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 |
f2b0befd | 1362 | /* enum: Internal. */ |
05a9320f | 1363 | /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ |
f2b0befd | 1364 | /* enum: External. */ |
05a9320f | 1365 | /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ |
f2b0befd | 1366 | /* Port address */ |
05a9320f | 1367 | #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 |
f2b0befd | 1368 | /* Device Address or clause 22. */ |
05a9320f | 1369 | #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 |
f2b0befd BH |
1370 | /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you |
1371 | * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. | |
1372 | */ | |
05a9320f | 1373 | /* MC_CMD_MDIO_CLAUSE22 0x20 */ |
f2b0befd | 1374 | /* Address */ |
05a9320f | 1375 | #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 |
f2b0befd | 1376 | /* Value */ |
05a9320f | 1377 | #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 |
f0d37f42 | 1378 | |
05a9320f BH |
1379 | /* MC_CMD_MDIO_WRITE_OUT msgresponse */ |
1380 | #define MC_CMD_MDIO_WRITE_OUT_LEN 4 | |
f2b0befd BH |
1381 | /* Status; the MDIO commands return the raw status bits from the MDIO block. A |
1382 | * "good" transaction should have the DONE bit set and all other bits clear. | |
1383 | */ | |
05a9320f | 1384 | #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 |
f2b0befd | 1385 | /* enum: Good. */ |
05a9320f BH |
1386 | /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ |
1387 | ||
1388 | ||
1389 | /***********************************/ | |
1390 | /* MC_CMD_DBI_WRITE | |
1391 | * Write DBI register(s). | |
f0d37f42 SH |
1392 | */ |
1393 | #define MC_CMD_DBI_WRITE 0x12 | |
05a9320f BH |
1394 | |
1395 | /* MC_CMD_DBI_WRITE_IN msgrequest */ | |
1396 | #define MC_CMD_DBI_WRITE_IN_LENMIN 12 | |
1397 | #define MC_CMD_DBI_WRITE_IN_LENMAX 252 | |
1398 | #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) | |
f2b0befd BH |
1399 | /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset |
1400 | * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. | |
1401 | */ | |
05a9320f BH |
1402 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 |
1403 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 | |
1404 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 | |
1405 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 | |
1406 | ||
1407 | /* MC_CMD_DBI_WRITE_OUT msgresponse */ | |
1408 | #define MC_CMD_DBI_WRITE_OUT_LEN 0 | |
1409 | ||
1410 | /* MC_CMD_DBIWROP_TYPEDEF structuredef */ | |
1411 | #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 | |
1412 | #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 | |
1413 | #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 | |
1414 | #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 | |
f2b0befd BH |
1415 | #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 |
1416 | #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 | |
1417 | #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 | |
1418 | #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 | |
1419 | #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 | |
1420 | #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 | |
1421 | #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 | |
1422 | #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 | |
1423 | #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 | |
05a9320f BH |
1424 | #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 |
1425 | #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 | |
1426 | #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 | |
1427 | ||
1428 | ||
1429 | /***********************************/ | |
1430 | /* MC_CMD_PORT_READ32 | |
f2b0befd BH |
1431 | * Read a 32-bit register from the indirect port register map. The port to |
1432 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1433 | */ |
1434 | #define MC_CMD_PORT_READ32 0x14 | |
f0d37f42 | 1435 | |
05a9320f BH |
1436 | /* MC_CMD_PORT_READ32_IN msgrequest */ |
1437 | #define MC_CMD_PORT_READ32_IN_LEN 4 | |
f2b0befd | 1438 | /* Address */ |
05a9320f BH |
1439 | #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 |
1440 | ||
1441 | /* MC_CMD_PORT_READ32_OUT msgresponse */ | |
1442 | #define MC_CMD_PORT_READ32_OUT_LEN 8 | |
f2b0befd | 1443 | /* Value */ |
05a9320f | 1444 | #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 |
f2b0befd | 1445 | /* Status */ |
05a9320f BH |
1446 | #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 |
1447 | ||
1448 | ||
1449 | /***********************************/ | |
1450 | /* MC_CMD_PORT_WRITE32 | |
f2b0befd BH |
1451 | * Write a 32-bit register to the indirect port register map. The port to |
1452 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1453 | */ |
1454 | #define MC_CMD_PORT_WRITE32 0x15 | |
05a9320f BH |
1455 | |
1456 | /* MC_CMD_PORT_WRITE32_IN msgrequest */ | |
1457 | #define MC_CMD_PORT_WRITE32_IN_LEN 8 | |
f2b0befd | 1458 | /* Address */ |
05a9320f | 1459 | #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 |
f2b0befd | 1460 | /* Value */ |
05a9320f BH |
1461 | #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 |
1462 | ||
1463 | /* MC_CMD_PORT_WRITE32_OUT msgresponse */ | |
1464 | #define MC_CMD_PORT_WRITE32_OUT_LEN 4 | |
f2b0befd | 1465 | /* Status */ |
05a9320f BH |
1466 | #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 |
1467 | ||
1468 | ||
1469 | /***********************************/ | |
1470 | /* MC_CMD_PORT_READ128 | |
f2b0befd BH |
1471 | * Read a 128-bit register from the indirect port register map. The port to |
1472 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1473 | */ |
1474 | #define MC_CMD_PORT_READ128 0x16 | |
05a9320f BH |
1475 | |
1476 | /* MC_CMD_PORT_READ128_IN msgrequest */ | |
1477 | #define MC_CMD_PORT_READ128_IN_LEN 4 | |
f2b0befd | 1478 | /* Address */ |
05a9320f BH |
1479 | #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 |
1480 | ||
1481 | /* MC_CMD_PORT_READ128_OUT msgresponse */ | |
1482 | #define MC_CMD_PORT_READ128_OUT_LEN 20 | |
f2b0befd | 1483 | /* Value */ |
05a9320f BH |
1484 | #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 |
1485 | #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 | |
f2b0befd | 1486 | /* Status */ |
05a9320f BH |
1487 | #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 |
1488 | ||
1489 | ||
1490 | /***********************************/ | |
1491 | /* MC_CMD_PORT_WRITE128 | |
f2b0befd BH |
1492 | * Write a 128-bit register to the indirect port register map. The port to |
1493 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1494 | */ |
1495 | #define MC_CMD_PORT_WRITE128 0x17 | |
05a9320f BH |
1496 | |
1497 | /* MC_CMD_PORT_WRITE128_IN msgrequest */ | |
1498 | #define MC_CMD_PORT_WRITE128_IN_LEN 20 | |
f2b0befd | 1499 | /* Address */ |
05a9320f | 1500 | #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 |
f2b0befd | 1501 | /* Value */ |
05a9320f BH |
1502 | #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 |
1503 | #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 | |
1504 | ||
1505 | /* MC_CMD_PORT_WRITE128_OUT msgresponse */ | |
1506 | #define MC_CMD_PORT_WRITE128_OUT_LEN 4 | |
f2b0befd | 1507 | /* Status */ |
05a9320f BH |
1508 | #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 |
1509 | ||
f2b0befd BH |
1510 | /* MC_CMD_CAPABILITIES structuredef */ |
1511 | #define MC_CMD_CAPABILITIES_LEN 4 | |
1512 | /* Small buf table. */ | |
1513 | #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 | |
1514 | #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 | |
1515 | /* Turbo mode (for Maranello). */ | |
1516 | #define MC_CMD_CAPABILITIES_TURBO_LBN 1 | |
1517 | #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 | |
1518 | /* Turbo mode active (for Maranello). */ | |
1519 | #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 | |
1520 | #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 | |
1521 | /* PTP offload. */ | |
1522 | #define MC_CMD_CAPABILITIES_PTP_LBN 3 | |
1523 | #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 | |
1524 | /* AOE mode. */ | |
1525 | #define MC_CMD_CAPABILITIES_AOE_LBN 4 | |
1526 | #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 | |
1527 | /* AOE mode active. */ | |
1528 | #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 | |
1529 | #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 | |
1530 | /* AOE mode active. */ | |
1531 | #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 | |
1532 | #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 | |
1533 | #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 | |
1534 | #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 | |
1535 | ||
05a9320f BH |
1536 | |
1537 | /***********************************/ | |
1538 | /* MC_CMD_GET_BOARD_CFG | |
1539 | * Returns the MC firmware configuration structure. | |
f0d37f42 SH |
1540 | */ |
1541 | #define MC_CMD_GET_BOARD_CFG 0x18 | |
05a9320f BH |
1542 | |
1543 | /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ | |
1544 | #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 | |
1545 | ||
1546 | /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ | |
1547 | #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 | |
1548 | #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 | |
1549 | #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) | |
1550 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 | |
1551 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 | |
1552 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 | |
f2b0befd | 1553 | /* See MC_CMD_CAPABILITIES */ |
05a9320f | 1554 | #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 |
f2b0befd | 1555 | /* See MC_CMD_CAPABILITIES */ |
05a9320f | 1556 | #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 |
05a9320f BH |
1557 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 |
1558 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 | |
1559 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 | |
1560 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 | |
1561 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 | |
1562 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 | |
1563 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 | |
1564 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 | |
f2b0befd BH |
1565 | /* This field contains a 16-bit value for each of the types of NVRAM area. The |
1566 | * values are defined in the firmware/mc/platform/.c file for a specific board | |
1567 | * type, but otherwise have no meaning to the MC; they are used by the driver | |
1568 | * to manage selection of appropriate firmware updates. | |
1569 | */ | |
05a9320f BH |
1570 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 |
1571 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 | |
1572 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 | |
1573 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 | |
1574 | ||
1575 | ||
1576 | /***********************************/ | |
1577 | /* MC_CMD_DBI_READX | |
f2b0befd | 1578 | * Read DBI register(s) -- extended functionality |
f0d37f42 SH |
1579 | */ |
1580 | #define MC_CMD_DBI_READX 0x19 | |
f0d37f42 | 1581 | |
05a9320f BH |
1582 | /* MC_CMD_DBI_READX_IN msgrequest */ |
1583 | #define MC_CMD_DBI_READX_IN_LENMIN 8 | |
1584 | #define MC_CMD_DBI_READX_IN_LENMAX 248 | |
1585 | #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) | |
f2b0befd | 1586 | /* Each Read op consists of an address (offset 0), VF/CS2) */ |
05a9320f BH |
1587 | #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 |
1588 | #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 | |
1589 | #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 | |
1590 | #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 | |
1591 | #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 | |
1592 | #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 | |
1593 | ||
1594 | /* MC_CMD_DBI_READX_OUT msgresponse */ | |
1595 | #define MC_CMD_DBI_READX_OUT_LENMIN 4 | |
1596 | #define MC_CMD_DBI_READX_OUT_LENMAX 252 | |
1597 | #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) | |
f2b0befd | 1598 | /* Value */ |
05a9320f BH |
1599 | #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 |
1600 | #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 | |
1601 | #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 | |
1602 | #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 | |
1603 | ||
f2b0befd BH |
1604 | /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ |
1605 | #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 | |
1606 | #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 | |
1607 | #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 | |
1608 | #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 | |
1609 | #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 | |
1610 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 | |
1611 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 | |
1612 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 | |
1613 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 | |
1614 | #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 | |
1615 | #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 | |
1616 | #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 | |
1617 | #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 | |
1618 | ||
05a9320f BH |
1619 | |
1620 | /***********************************/ | |
1621 | /* MC_CMD_SET_RAND_SEED | |
1622 | * Set the 16byte seed for the MC pseudo-random generator. | |
f0d37f42 SH |
1623 | */ |
1624 | #define MC_CMD_SET_RAND_SEED 0x1a | |
f0d37f42 | 1625 | |
05a9320f BH |
1626 | /* MC_CMD_SET_RAND_SEED_IN msgrequest */ |
1627 | #define MC_CMD_SET_RAND_SEED_IN_LEN 16 | |
f2b0befd | 1628 | /* Seed value. */ |
05a9320f BH |
1629 | #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 |
1630 | #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 | |
1631 | ||
1632 | /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ | |
1633 | #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 | |
1634 | ||
1635 | ||
1636 | /***********************************/ | |
1637 | /* MC_CMD_LTSSM_HIST | |
f2b0befd | 1638 | * Retrieve the history of the LTSSM, if the build supports it. |
f0d37f42 SH |
1639 | */ |
1640 | #define MC_CMD_LTSSM_HIST 0x1b | |
1641 | ||
05a9320f BH |
1642 | /* MC_CMD_LTSSM_HIST_IN msgrequest */ |
1643 | #define MC_CMD_LTSSM_HIST_IN_LEN 0 | |
1644 | ||
1645 | /* MC_CMD_LTSSM_HIST_OUT msgresponse */ | |
1646 | #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 | |
1647 | #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 | |
1648 | #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) | |
f2b0befd | 1649 | /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ |
05a9320f BH |
1650 | #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 |
1651 | #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 | |
1652 | #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 | |
1653 | #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 | |
1654 | ||
1655 | ||
1656 | /***********************************/ | |
1657 | /* MC_CMD_DRV_ATTACH | |
f2b0befd BH |
1658 | * Inform MCPU that this port is managed on the host (i.e. driver active). For |
1659 | * Huntington, also request the preferred datapath firmware to use if possible | |
1660 | * (it may not be possible for this request to be fulfilled; the driver must | |
1661 | * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which | |
1662 | * features are actually available). The FIRMWARE_ID field is ignored by older | |
1663 | * platforms. | |
f0d37f42 SH |
1664 | */ |
1665 | #define MC_CMD_DRV_ATTACH 0x1c | |
f0d37f42 | 1666 | |
05a9320f | 1667 | /* MC_CMD_DRV_ATTACH_IN msgrequest */ |
f2b0befd BH |
1668 | #define MC_CMD_DRV_ATTACH_IN_LEN 12 |
1669 | /* new state (0=detached, 1=attached) to set if UPDATE=1 */ | |
05a9320f | 1670 | #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 |
f2b0befd | 1671 | /* 1 to set new state, or 0 to just report the existing state */ |
05a9320f | 1672 | #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 |
f2b0befd BH |
1673 | /* preferred datapath firmware (for Huntington; ignored for Siena) */ |
1674 | #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 | |
1675 | /* enum: Prefer to use full featured firmware */ | |
1676 | #define MC_CMD_FW_FULL_FEATURED 0x0 | |
1677 | /* enum: Prefer to use firmware with fewer features but lower latency */ | |
1678 | #define MC_CMD_FW_LOW_LATENCY 0x1 | |
05a9320f BH |
1679 | |
1680 | /* MC_CMD_DRV_ATTACH_OUT msgresponse */ | |
1681 | #define MC_CMD_DRV_ATTACH_OUT_LEN 4 | |
f2b0befd | 1682 | /* previous or existing state (0=detached, 1=attached) */ |
05a9320f BH |
1683 | #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 |
1684 | ||
f2b0befd BH |
1685 | /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ |
1686 | #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 | |
1687 | /* previous or existing state (0=detached, 1=attached) */ | |
1688 | #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 | |
1689 | /* Flags associated with this function */ | |
1690 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 | |
1691 | /* enum: Labels the lowest-numbered function visible to the OS */ | |
1692 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 | |
1693 | /* enum: The function can control the link state of the physical port it is | |
1694 | * bound to. | |
f0d37f42 | 1695 | */ |
f2b0befd BH |
1696 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 |
1697 | /* enum: The function can perform privileged operations */ | |
1698 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 | |
05a9320f BH |
1699 | |
1700 | ||
1701 | /***********************************/ | |
1702 | /* MC_CMD_SHMUART | |
f0d37f42 SH |
1703 | * Route UART output to circular buffer in shared memory instead. |
1704 | */ | |
1705 | #define MC_CMD_SHMUART 0x1f | |
f0d37f42 | 1706 | |
05a9320f BH |
1707 | /* MC_CMD_SHMUART_IN msgrequest */ |
1708 | #define MC_CMD_SHMUART_IN_LEN 4 | |
f2b0befd | 1709 | /* ??? */ |
05a9320f BH |
1710 | #define MC_CMD_SHMUART_IN_FLAG_OFST 0 |
1711 | ||
1712 | /* MC_CMD_SHMUART_OUT msgresponse */ | |
1713 | #define MC_CMD_SHMUART_OUT_LEN 0 | |
1714 | ||
1715 | ||
f2b0befd BH |
1716 | /***********************************/ |
1717 | /* MC_CMD_PORT_RESET | |
1718 | * Generic per-port reset. There is no equivalent for per-board reset. Locks | |
1719 | * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - | |
1720 | * use MC_CMD_ENTITY_RESET instead. | |
1721 | */ | |
1722 | #define MC_CMD_PORT_RESET 0x20 | |
1723 | ||
1724 | /* MC_CMD_PORT_RESET_IN msgrequest */ | |
1725 | #define MC_CMD_PORT_RESET_IN_LEN 0 | |
1726 | ||
1727 | /* MC_CMD_PORT_RESET_OUT msgresponse */ | |
1728 | #define MC_CMD_PORT_RESET_OUT_LEN 0 | |
1729 | ||
1730 | ||
05a9320f BH |
1731 | /***********************************/ |
1732 | /* MC_CMD_ENTITY_RESET | |
f2b0befd BH |
1733 | * Generic per-resource reset. There is no equivalent for per-board reset. |
1734 | * Locks required: None; Return code: 0, ETIME. NOTE: This command is an | |
1735 | * extended version of the deprecated MC_CMD_PORT_RESET with added fields. | |
05a9320f BH |
1736 | */ |
1737 | #define MC_CMD_ENTITY_RESET 0x20 | |
1738 | ||
1739 | /* MC_CMD_ENTITY_RESET_IN msgrequest */ | |
1740 | #define MC_CMD_ENTITY_RESET_IN_LEN 4 | |
f2b0befd BH |
1741 | /* Optional flags field. Omitting this will perform a "legacy" reset action |
1742 | * (TBD). | |
1743 | */ | |
05a9320f BH |
1744 | #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 |
1745 | #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 | |
1746 | #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 | |
1747 | ||
1748 | /* MC_CMD_ENTITY_RESET_OUT msgresponse */ | |
1749 | #define MC_CMD_ENTITY_RESET_OUT_LEN 0 | |
1750 | ||
1751 | ||
1752 | /***********************************/ | |
1753 | /* MC_CMD_PCIE_CREDITS | |
1754 | * Read instantaneous and minimum flow control thresholds. | |
1755 | */ | |
1756 | #define MC_CMD_PCIE_CREDITS 0x21 | |
1757 | ||
1758 | /* MC_CMD_PCIE_CREDITS_IN msgrequest */ | |
1759 | #define MC_CMD_PCIE_CREDITS_IN_LEN 8 | |
f2b0befd | 1760 | /* poll period. 0 is disabled */ |
05a9320f | 1761 | #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 |
f2b0befd | 1762 | /* wipe statistics */ |
05a9320f BH |
1763 | #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 |
1764 | ||
1765 | /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ | |
1766 | #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 | |
1767 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 | |
1768 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 | |
1769 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 | |
1770 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 | |
1771 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 | |
1772 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 | |
1773 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 | |
1774 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 | |
1775 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 | |
1776 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 | |
1777 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 | |
1778 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 | |
1779 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 | |
1780 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 | |
1781 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 | |
1782 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 | |
1783 | ||
1784 | ||
1785 | /***********************************/ | |
1786 | /* MC_CMD_RXD_MONITOR | |
1787 | * Get histogram of RX queue fill level. | |
1788 | */ | |
1789 | #define MC_CMD_RXD_MONITOR 0x22 | |
1790 | ||
1791 | /* MC_CMD_RXD_MONITOR_IN msgrequest */ | |
1792 | #define MC_CMD_RXD_MONITOR_IN_LEN 12 | |
1793 | #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 | |
1794 | #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 | |
1795 | #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 | |
1796 | ||
1797 | /* MC_CMD_RXD_MONITOR_OUT msgresponse */ | |
1798 | #define MC_CMD_RXD_MONITOR_OUT_LEN 80 | |
1799 | #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 | |
1800 | #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 | |
1801 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 | |
1802 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 | |
1803 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 | |
1804 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 | |
1805 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 | |
1806 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 | |
1807 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 | |
1808 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 | |
1809 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 | |
1810 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 | |
1811 | #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 | |
1812 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 | |
1813 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 | |
1814 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 | |
1815 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 | |
1816 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 | |
1817 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 | |
1818 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 | |
1819 | ||
1820 | ||
1821 | /***********************************/ | |
1822 | /* MC_CMD_PUTS | |
f2b0befd | 1823 | * Copy the given ASCII string out onto UART and/or out of the network port. |
05a9320f BH |
1824 | */ |
1825 | #define MC_CMD_PUTS 0x23 | |
1826 | ||
1827 | /* MC_CMD_PUTS_IN msgrequest */ | |
1828 | #define MC_CMD_PUTS_IN_LENMIN 13 | |
576eda8b | 1829 | #define MC_CMD_PUTS_IN_LENMAX 252 |
05a9320f BH |
1830 | #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) |
1831 | #define MC_CMD_PUTS_IN_DEST_OFST 0 | |
1832 | #define MC_CMD_PUTS_IN_UART_LBN 0 | |
1833 | #define MC_CMD_PUTS_IN_UART_WIDTH 1 | |
1834 | #define MC_CMD_PUTS_IN_PORT_LBN 1 | |
1835 | #define MC_CMD_PUTS_IN_PORT_WIDTH 1 | |
1836 | #define MC_CMD_PUTS_IN_DHOST_OFST 4 | |
1837 | #define MC_CMD_PUTS_IN_DHOST_LEN 6 | |
1838 | #define MC_CMD_PUTS_IN_STRING_OFST 12 | |
1839 | #define MC_CMD_PUTS_IN_STRING_LEN 1 | |
1840 | #define MC_CMD_PUTS_IN_STRING_MINNUM 1 | |
576eda8b | 1841 | #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 |
05a9320f BH |
1842 | |
1843 | /* MC_CMD_PUTS_OUT msgresponse */ | |
1844 | #define MC_CMD_PUTS_OUT_LEN 0 | |
1845 | ||
1846 | ||
1847 | /***********************************/ | |
1848 | /* MC_CMD_GET_PHY_CFG | |
f2b0befd BH |
1849 | * Report PHY configuration. This guarantees to succeed even if the PHY is in a |
1850 | * 'zombie' state. Locks required: None | |
f0d37f42 SH |
1851 | */ |
1852 | #define MC_CMD_GET_PHY_CFG 0x24 | |
1853 | ||
05a9320f BH |
1854 | /* MC_CMD_GET_PHY_CFG_IN msgrequest */ |
1855 | #define MC_CMD_GET_PHY_CFG_IN_LEN 0 | |
1856 | ||
1857 | /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ | |
1858 | #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 | |
f2b0befd | 1859 | /* flags */ |
05a9320f BH |
1860 | #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 |
1861 | #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 | |
1862 | #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 | |
1863 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 | |
1864 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 | |
1865 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 | |
1866 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 | |
1867 | #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 | |
1868 | #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 | |
1869 | #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 | |
1870 | #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 | |
1871 | #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 | |
1872 | #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 | |
1873 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 | |
1874 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 | |
f2b0befd | 1875 | /* ?? */ |
05a9320f | 1876 | #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 |
f2b0befd | 1877 | /* Bitmask of supported capabilities */ |
05a9320f BH |
1878 | #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 |
1879 | #define MC_CMD_PHY_CAP_10HDX_LBN 1 | |
1880 | #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 | |
1881 | #define MC_CMD_PHY_CAP_10FDX_LBN 2 | |
1882 | #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 | |
1883 | #define MC_CMD_PHY_CAP_100HDX_LBN 3 | |
1884 | #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 | |
1885 | #define MC_CMD_PHY_CAP_100FDX_LBN 4 | |
1886 | #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 | |
1887 | #define MC_CMD_PHY_CAP_1000HDX_LBN 5 | |
1888 | #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 | |
1889 | #define MC_CMD_PHY_CAP_1000FDX_LBN 6 | |
1890 | #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 | |
1891 | #define MC_CMD_PHY_CAP_10000FDX_LBN 7 | |
1892 | #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 | |
1893 | #define MC_CMD_PHY_CAP_PAUSE_LBN 8 | |
1894 | #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 | |
1895 | #define MC_CMD_PHY_CAP_ASYM_LBN 9 | |
1896 | #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 | |
1897 | #define MC_CMD_PHY_CAP_AN_LBN 10 | |
1898 | #define MC_CMD_PHY_CAP_AN_WIDTH 1 | |
f2b0befd BH |
1899 | #define MC_CMD_PHY_CAP_40000FDX_LBN 11 |
1900 | #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 | |
1901 | #define MC_CMD_PHY_CAP_DDM_LBN 12 | |
1902 | #define MC_CMD_PHY_CAP_DDM_WIDTH 1 | |
1903 | /* ?? */ | |
05a9320f | 1904 | #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 |
f2b0befd | 1905 | /* ?? */ |
05a9320f | 1906 | #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 |
f2b0befd | 1907 | /* ?? */ |
05a9320f | 1908 | #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 |
f2b0befd | 1909 | /* ?? */ |
05a9320f BH |
1910 | #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 |
1911 | #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 | |
f2b0befd | 1912 | /* ?? */ |
05a9320f | 1913 | #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 |
f2b0befd BH |
1914 | /* enum: Xaui. */ |
1915 | #define MC_CMD_MEDIA_XAUI 0x1 | |
1916 | /* enum: CX4. */ | |
1917 | #define MC_CMD_MEDIA_CX4 0x2 | |
1918 | /* enum: KX4. */ | |
1919 | #define MC_CMD_MEDIA_KX4 0x3 | |
1920 | /* enum: XFP Far. */ | |
1921 | #define MC_CMD_MEDIA_XFP 0x4 | |
1922 | /* enum: SFP+. */ | |
1923 | #define MC_CMD_MEDIA_SFP_PLUS 0x5 | |
1924 | /* enum: 10GBaseT. */ | |
1925 | #define MC_CMD_MEDIA_BASE_T 0x6 | |
05a9320f | 1926 | #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 |
f2b0befd BH |
1927 | /* enum: Native clause 22 */ |
1928 | #define MC_CMD_MMD_CLAUSE22 0x0 | |
05a9320f BH |
1929 | #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ |
1930 | #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ | |
1931 | #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ | |
1932 | #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ | |
1933 | #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ | |
1934 | #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ | |
1935 | #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ | |
f2b0befd BH |
1936 | /* enum: Clause22 proxied over clause45 by PHY. */ |
1937 | #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d | |
05a9320f BH |
1938 | #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ |
1939 | #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ | |
1940 | #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 | |
1941 | #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 | |
1942 | ||
1943 | ||
1944 | /***********************************/ | |
1945 | /* MC_CMD_START_BIST | |
f2b0befd BH |
1946 | * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST |
1947 | * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) | |
f0d37f42 SH |
1948 | */ |
1949 | #define MC_CMD_START_BIST 0x25 | |
05a9320f BH |
1950 | |
1951 | /* MC_CMD_START_BIST_IN msgrequest */ | |
1952 | #define MC_CMD_START_BIST_IN_LEN 4 | |
f2b0befd | 1953 | /* Type of test. */ |
05a9320f | 1954 | #define MC_CMD_START_BIST_IN_TYPE_OFST 0 |
f2b0befd BH |
1955 | /* enum: Run the PHY's short cable BIST. */ |
1956 | #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 | |
1957 | /* enum: Run the PHY's long cable BIST. */ | |
1958 | #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 | |
1959 | /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ | |
1960 | #define MC_CMD_BPX_SERDES_BIST 0x3 | |
1961 | /* enum: Run the MC loopback tests. */ | |
1962 | #define MC_CMD_MC_LOOPBACK_BIST 0x4 | |
1963 | /* enum: Run the PHY's standard BIST. */ | |
1964 | #define MC_CMD_PHY_BIST 0x5 | |
1965 | /* enum: Run MC RAM test. */ | |
1966 | #define MC_CMD_MC_MEM_BIST 0x6 | |
1967 | /* enum: Run Port RAM test. */ | |
1968 | #define MC_CMD_PORT_MEM_BIST 0x7 | |
1969 | /* enum: Run register test. */ | |
1970 | #define MC_CMD_REG_BIST 0x8 | |
05a9320f BH |
1971 | |
1972 | /* MC_CMD_START_BIST_OUT msgresponse */ | |
1973 | #define MC_CMD_START_BIST_OUT_LEN 0 | |
1974 | ||
1975 | ||
1976 | /***********************************/ | |
1977 | /* MC_CMD_POLL_BIST | |
f2b0befd BH |
1978 | * Poll for BIST completion. Returns a single status code, and optionally some |
1979 | * PHY specific bist output. The driver should only consume the BIST output | |
1980 | * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't | |
1981 | * successfully parse the BIST output, it should still respect the pass/Fail in | |
1982 | * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, | |
1983 | * EACCES (if PHY_LOCK is not held). | |
f0d37f42 SH |
1984 | */ |
1985 | #define MC_CMD_POLL_BIST 0x26 | |
05a9320f BH |
1986 | |
1987 | /* MC_CMD_POLL_BIST_IN msgrequest */ | |
1988 | #define MC_CMD_POLL_BIST_IN_LEN 0 | |
1989 | ||
1990 | /* MC_CMD_POLL_BIST_OUT msgresponse */ | |
1991 | #define MC_CMD_POLL_BIST_OUT_LEN 8 | |
f2b0befd | 1992 | /* result */ |
05a9320f | 1993 | #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 |
f2b0befd BH |
1994 | /* enum: Running. */ |
1995 | #define MC_CMD_POLL_BIST_RUNNING 0x1 | |
1996 | /* enum: Passed. */ | |
1997 | #define MC_CMD_POLL_BIST_PASSED 0x2 | |
1998 | /* enum: Failed. */ | |
1999 | #define MC_CMD_POLL_BIST_FAILED 0x3 | |
2000 | /* enum: Timed-out. */ | |
2001 | #define MC_CMD_POLL_BIST_TIMEOUT 0x4 | |
05a9320f BH |
2002 | #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 |
2003 | ||
2004 | /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ | |
2005 | #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 | |
f2b0befd | 2006 | /* result */ |
05a9320f BH |
2007 | /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ |
2008 | /* Enum values, see field(s): */ | |
2009 | /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ | |
2010 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 | |
2011 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 | |
2012 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 | |
2013 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 | |
f2b0befd | 2014 | /* Status of each channel A */ |
05a9320f | 2015 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 |
f2b0befd BH |
2016 | /* enum: Ok. */ |
2017 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 | |
2018 | /* enum: Open. */ | |
2019 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 | |
2020 | /* enum: Intra-pair short. */ | |
2021 | #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 | |
2022 | /* enum: Inter-pair short. */ | |
2023 | #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 | |
2024 | /* enum: Busy. */ | |
2025 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 | |
2026 | /* Status of each channel B */ | |
05a9320f BH |
2027 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 |
2028 | /* Enum values, see field(s): */ | |
2029 | /* CABLE_STATUS_A */ | |
f2b0befd | 2030 | /* Status of each channel C */ |
05a9320f BH |
2031 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 |
2032 | /* Enum values, see field(s): */ | |
2033 | /* CABLE_STATUS_A */ | |
f2b0befd | 2034 | /* Status of each channel D */ |
05a9320f BH |
2035 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 |
2036 | /* Enum values, see field(s): */ | |
2037 | /* CABLE_STATUS_A */ | |
2038 | ||
2039 | /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ | |
2040 | #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 | |
f2b0befd | 2041 | /* result */ |
05a9320f BH |
2042 | /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ |
2043 | /* Enum values, see field(s): */ | |
2044 | /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ | |
2045 | #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 | |
f2b0befd BH |
2046 | /* enum: Complete. */ |
2047 | #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 | |
2048 | /* enum: Bus switch off I2C write. */ | |
2049 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 | |
2050 | /* enum: Bus switch off I2C no access IO exp. */ | |
2051 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 | |
2052 | /* enum: Bus switch off I2C no access module. */ | |
2053 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 | |
2054 | /* enum: IO exp I2C configure. */ | |
2055 | #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 | |
2056 | /* enum: Bus switch I2C no cross talk. */ | |
2057 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 | |
2058 | /* enum: Module presence. */ | |
2059 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 | |
2060 | /* enum: Module ID I2C access. */ | |
2061 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 | |
2062 | /* enum: Module ID sane value. */ | |
2063 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 | |
2064 | ||
2065 | /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ | |
2066 | #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 | |
2067 | /* result */ | |
2068 | /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ | |
2069 | /* Enum values, see field(s): */ | |
2070 | /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ | |
2071 | #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 | |
2072 | /* enum: Test has completed. */ | |
2073 | #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 | |
2074 | /* enum: RAM test - walk ones. */ | |
2075 | #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 | |
2076 | /* enum: RAM test - walk zeros. */ | |
2077 | #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 | |
2078 | /* enum: RAM test - walking inversions zeros/ones. */ | |
2079 | #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 | |
2080 | /* enum: RAM test - walking inversions checkerboard. */ | |
2081 | #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 | |
2082 | /* enum: Register test - set / clear individual bits. */ | |
2083 | #define MC_CMD_POLL_BIST_MEM_REG 0x5 | |
2084 | /* enum: ECC error detected. */ | |
2085 | #define MC_CMD_POLL_BIST_MEM_ECC 0x6 | |
2086 | /* Failure address, only valid if result is POLL_BIST_FAILED */ | |
2087 | #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 | |
2088 | /* Bus or address space to which the failure address corresponds */ | |
2089 | #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 | |
2090 | /* enum: MC MIPS bus. */ | |
2091 | #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 | |
2092 | /* enum: CSR IREG bus. */ | |
2093 | #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 | |
2094 | /* enum: RX DPCPU bus. */ | |
2095 | #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 | |
2096 | /* enum: TX0 DPCPU bus. */ | |
2097 | #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 | |
2098 | /* enum: TX1 DPCPU bus. */ | |
2099 | #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 | |
2100 | /* enum: RX DICPU bus. */ | |
2101 | #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 | |
2102 | /* enum: TX DICPU bus. */ | |
2103 | #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 | |
2104 | /* Pattern written to RAM / register */ | |
2105 | #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 | |
2106 | /* Actual value read from RAM / register */ | |
2107 | #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 | |
2108 | /* ECC error mask */ | |
2109 | #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 | |
2110 | /* ECC parity error mask */ | |
2111 | #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 | |
2112 | /* ECC fatal error mask */ | |
2113 | #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 | |
05a9320f BH |
2114 | |
2115 | ||
2116 | /***********************************/ | |
2117 | /* MC_CMD_FLUSH_RX_QUEUES | |
f2b0befd BH |
2118 | * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ |
2119 | * flushes should be initiated via this MCDI operation, rather than via | |
2120 | * directly writing FLUSH_CMD. | |
2121 | * | |
2122 | * The flush is completed (either done/fail) asynchronously (after this command | |
2123 | * returns). The driver must still wait for flush done/failure events as usual. | |
05a9320f BH |
2124 | */ |
2125 | #define MC_CMD_FLUSH_RX_QUEUES 0x27 | |
2126 | ||
2127 | /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ | |
2128 | #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 | |
2129 | #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 | |
2130 | #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) | |
2131 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 | |
2132 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 | |
2133 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 | |
2134 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 | |
2135 | ||
2136 | /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ | |
2137 | #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 | |
2138 | ||
2139 | ||
2140 | /***********************************/ | |
2141 | /* MC_CMD_GET_LOOPBACK_MODES | |
f2b0befd | 2142 | * Returns a bitmask of loopback modes available at each speed. |
f0d37f42 SH |
2143 | */ |
2144 | #define MC_CMD_GET_LOOPBACK_MODES 0x28 | |
05a9320f BH |
2145 | |
2146 | /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ | |
2147 | #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 | |
2148 | ||
2149 | /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ | |
f2b0befd BH |
2150 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 |
2151 | /* Supported loopbacks. */ | |
05a9320f BH |
2152 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 |
2153 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 | |
2154 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 | |
2155 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 | |
f2b0befd BH |
2156 | /* enum: None. */ |
2157 | #define MC_CMD_LOOPBACK_NONE 0x0 | |
2158 | /* enum: Data. */ | |
2159 | #define MC_CMD_LOOPBACK_DATA 0x1 | |
2160 | /* enum: GMAC. */ | |
2161 | #define MC_CMD_LOOPBACK_GMAC 0x2 | |
2162 | /* enum: XGMII. */ | |
2163 | #define MC_CMD_LOOPBACK_XGMII 0x3 | |
2164 | /* enum: XGXS. */ | |
2165 | #define MC_CMD_LOOPBACK_XGXS 0x4 | |
2166 | /* enum: XAUI. */ | |
2167 | #define MC_CMD_LOOPBACK_XAUI 0x5 | |
2168 | /* enum: GMII. */ | |
2169 | #define MC_CMD_LOOPBACK_GMII 0x6 | |
2170 | /* enum: SGMII. */ | |
2171 | #define MC_CMD_LOOPBACK_SGMII 0x7 | |
2172 | /* enum: XGBR. */ | |
2173 | #define MC_CMD_LOOPBACK_XGBR 0x8 | |
2174 | /* enum: XFI. */ | |
2175 | #define MC_CMD_LOOPBACK_XFI 0x9 | |
2176 | /* enum: XAUI Far. */ | |
2177 | #define MC_CMD_LOOPBACK_XAUI_FAR 0xa | |
2178 | /* enum: GMII Far. */ | |
2179 | #define MC_CMD_LOOPBACK_GMII_FAR 0xb | |
2180 | /* enum: SGMII Far. */ | |
2181 | #define MC_CMD_LOOPBACK_SGMII_FAR 0xc | |
2182 | /* enum: XFI Far. */ | |
2183 | #define MC_CMD_LOOPBACK_XFI_FAR 0xd | |
2184 | /* enum: GPhy. */ | |
2185 | #define MC_CMD_LOOPBACK_GPHY 0xe | |
2186 | /* enum: PhyXS. */ | |
2187 | #define MC_CMD_LOOPBACK_PHYXS 0xf | |
2188 | /* enum: PCS. */ | |
2189 | #define MC_CMD_LOOPBACK_PCS 0x10 | |
2190 | /* enum: PMA-PMD. */ | |
2191 | #define MC_CMD_LOOPBACK_PMAPMD 0x11 | |
2192 | /* enum: Cross-Port. */ | |
2193 | #define MC_CMD_LOOPBACK_XPORT 0x12 | |
2194 | /* enum: XGMII-Wireside. */ | |
2195 | #define MC_CMD_LOOPBACK_XGMII_WS 0x13 | |
2196 | /* enum: XAUI Wireside. */ | |
2197 | #define MC_CMD_LOOPBACK_XAUI_WS 0x14 | |
2198 | /* enum: XAUI Wireside Far. */ | |
2199 | #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 | |
2200 | /* enum: XAUI Wireside near. */ | |
2201 | #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 | |
2202 | /* enum: GMII Wireside. */ | |
2203 | #define MC_CMD_LOOPBACK_GMII_WS 0x17 | |
2204 | /* enum: XFI Wireside. */ | |
2205 | #define MC_CMD_LOOPBACK_XFI_WS 0x18 | |
2206 | /* enum: XFI Wireside Far. */ | |
2207 | #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 | |
2208 | /* enum: PhyXS Wireside. */ | |
2209 | #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a | |
2210 | /* enum: PMA lanes MAC-Serdes. */ | |
2211 | #define MC_CMD_LOOPBACK_PMA_INT 0x1b | |
2212 | /* enum: KR Serdes Parallel (Encoder). */ | |
2213 | #define MC_CMD_LOOPBACK_SD_NEAR 0x1c | |
2214 | /* enum: KR Serdes Serial. */ | |
2215 | #define MC_CMD_LOOPBACK_SD_FAR 0x1d | |
2216 | /* enum: PMA lanes MAC-Serdes Wireside. */ | |
2217 | #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e | |
2218 | /* enum: KR Serdes Parallel Wireside (Full PCS). */ | |
2219 | #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f | |
2220 | /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ | |
2221 | #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 | |
2222 | /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ | |
2223 | #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 | |
2224 | /* enum: KR Serdes Serial Wireside. */ | |
2225 | #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 | |
2226 | /* Supported loopbacks. */ | |
05a9320f BH |
2227 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 |
2228 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 | |
2229 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 | |
2230 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 | |
2231 | /* Enum values, see field(s): */ | |
2232 | /* 100M */ | |
f2b0befd | 2233 | /* Supported loopbacks. */ |
05a9320f BH |
2234 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 |
2235 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 | |
2236 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 | |
2237 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 | |
2238 | /* Enum values, see field(s): */ | |
2239 | /* 100M */ | |
f2b0befd | 2240 | /* Supported loopbacks. */ |
05a9320f BH |
2241 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 |
2242 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 | |
2243 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 | |
2244 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 | |
2245 | /* Enum values, see field(s): */ | |
2246 | /* 100M */ | |
f2b0befd BH |
2247 | /* Supported loopbacks. */ |
2248 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 | |
2249 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 | |
2250 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 | |
2251 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 | |
2252 | /* Enum values, see field(s): */ | |
2253 | /* 100M */ | |
05a9320f BH |
2254 | |
2255 | ||
2256 | /***********************************/ | |
2257 | /* MC_CMD_GET_LINK | |
f2b0befd BH |
2258 | * Read the unified MAC/PHY link state. Locks required: None Return code: 0, |
2259 | * ETIME. | |
f0d37f42 SH |
2260 | */ |
2261 | #define MC_CMD_GET_LINK 0x29 | |
05a9320f BH |
2262 | |
2263 | /* MC_CMD_GET_LINK_IN msgrequest */ | |
2264 | #define MC_CMD_GET_LINK_IN_LEN 0 | |
2265 | ||
2266 | /* MC_CMD_GET_LINK_OUT msgresponse */ | |
2267 | #define MC_CMD_GET_LINK_OUT_LEN 28 | |
f2b0befd | 2268 | /* near-side advertised capabilities */ |
05a9320f | 2269 | #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 |
f2b0befd | 2270 | /* link-partner advertised capabilities */ |
05a9320f | 2271 | #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 |
f2b0befd BH |
2272 | /* Autonegotiated speed in mbit/s. The link may still be down even if this |
2273 | * reads non-zero. | |
2274 | */ | |
05a9320f | 2275 | #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 |
f2b0befd | 2276 | /* Current loopback setting. */ |
05a9320f BH |
2277 | #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 |
2278 | /* Enum values, see field(s): */ | |
2279 | /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ | |
2280 | #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 | |
2281 | #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 | |
2282 | #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 | |
2283 | #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 | |
2284 | #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 | |
2285 | #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 | |
2286 | #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 | |
2287 | #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 | |
2288 | #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 | |
f2b0befd | 2289 | /* This returns the negotiated flow control value. */ |
05a9320f | 2290 | #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 |
f2b0befd BH |
2291 | /* enum: Flow control is off. */ |
2292 | #define MC_CMD_FCNTL_OFF 0x0 | |
2293 | /* enum: Respond to flow control. */ | |
2294 | #define MC_CMD_FCNTL_RESPOND 0x1 | |
2295 | /* enum: Respond to and Issue flow control. */ | |
2296 | #define MC_CMD_FCNTL_BIDIR 0x2 | |
05a9320f BH |
2297 | #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 |
2298 | #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 | |
2299 | #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 | |
2300 | #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 | |
2301 | #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 | |
2302 | #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 | |
2303 | #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 | |
2304 | #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 | |
2305 | #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 | |
2306 | ||
2307 | ||
2308 | /***********************************/ | |
2309 | /* MC_CMD_SET_LINK | |
f2b0befd BH |
2310 | * Write the unified MAC/PHY link configuration. Locks required: None. Return |
2311 | * code: 0, EINVAL, ETIME | |
f0d37f42 SH |
2312 | */ |
2313 | #define MC_CMD_SET_LINK 0x2a | |
05a9320f BH |
2314 | |
2315 | /* MC_CMD_SET_LINK_IN msgrequest */ | |
2316 | #define MC_CMD_SET_LINK_IN_LEN 16 | |
f2b0befd | 2317 | /* ??? */ |
05a9320f | 2318 | #define MC_CMD_SET_LINK_IN_CAP_OFST 0 |
f2b0befd | 2319 | /* Flags */ |
05a9320f BH |
2320 | #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 |
2321 | #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 | |
2322 | #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 | |
2323 | #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 | |
2324 | #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 | |
2325 | #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 | |
2326 | #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 | |
f2b0befd | 2327 | /* Loopback mode. */ |
05a9320f BH |
2328 | #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 |
2329 | /* Enum values, see field(s): */ | |
2330 | /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ | |
f2b0befd BH |
2331 | /* A loopback speed of "0" is supported, and means (choose any available |
2332 | * speed). | |
2333 | */ | |
05a9320f BH |
2334 | #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 |
2335 | ||
2336 | /* MC_CMD_SET_LINK_OUT msgresponse */ | |
2337 | #define MC_CMD_SET_LINK_OUT_LEN 0 | |
2338 | ||
2339 | ||
2340 | /***********************************/ | |
2341 | /* MC_CMD_SET_ID_LED | |
f2b0befd | 2342 | * Set identification LED state. Locks required: None. Return code: 0, EINVAL |
f0d37f42 SH |
2343 | */ |
2344 | #define MC_CMD_SET_ID_LED 0x2b | |
05a9320f BH |
2345 | |
2346 | /* MC_CMD_SET_ID_LED_IN msgrequest */ | |
2347 | #define MC_CMD_SET_ID_LED_IN_LEN 4 | |
f2b0befd | 2348 | /* Set LED state. */ |
05a9320f BH |
2349 | #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 |
2350 | #define MC_CMD_LED_OFF 0x0 /* enum */ | |
2351 | #define MC_CMD_LED_ON 0x1 /* enum */ | |
2352 | #define MC_CMD_LED_DEFAULT 0x2 /* enum */ | |
2353 | ||
2354 | /* MC_CMD_SET_ID_LED_OUT msgresponse */ | |
2355 | #define MC_CMD_SET_ID_LED_OUT_LEN 0 | |
2356 | ||
2357 | ||
2358 | /***********************************/ | |
2359 | /* MC_CMD_SET_MAC | |
f2b0befd | 2360 | * Set MAC configuration. Locks required: None. Return code: 0, EINVAL |
f0d37f42 SH |
2361 | */ |
2362 | #define MC_CMD_SET_MAC 0x2c | |
05a9320f BH |
2363 | |
2364 | /* MC_CMD_SET_MAC_IN msgrequest */ | |
2365 | #define MC_CMD_SET_MAC_IN_LEN 24 | |
f2b0befd BH |
2366 | /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of |
2367 | * EtherII, VLAN, bug16011 padding). | |
2368 | */ | |
05a9320f BH |
2369 | #define MC_CMD_SET_MAC_IN_MTU_OFST 0 |
2370 | #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 | |
2371 | #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 | |
2372 | #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 | |
2373 | #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 | |
2374 | #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 | |
2375 | #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 | |
2376 | #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 | |
2377 | #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 | |
2378 | #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 | |
2379 | #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 | |
2380 | #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 | |
f2b0befd | 2381 | /* enum: Flow control is off. */ |
05a9320f | 2382 | /* MC_CMD_FCNTL_OFF 0x0 */ |
f2b0befd | 2383 | /* enum: Respond to flow control. */ |
05a9320f | 2384 | /* MC_CMD_FCNTL_RESPOND 0x1 */ |
f2b0befd | 2385 | /* enum: Respond to and Issue flow control. */ |
05a9320f | 2386 | /* MC_CMD_FCNTL_BIDIR 0x2 */ |
f2b0befd BH |
2387 | /* enum: Auto neg flow control. */ |
2388 | #define MC_CMD_FCNTL_AUTO 0x3 | |
05a9320f BH |
2389 | |
2390 | /* MC_CMD_SET_MAC_OUT msgresponse */ | |
2391 | #define MC_CMD_SET_MAC_OUT_LEN 0 | |
2392 | ||
2393 | ||
2394 | /***********************************/ | |
2395 | /* MC_CMD_PHY_STATS | |
f2b0befd BH |
2396 | * Get generic PHY statistics. This call returns the statistics for a generic |
2397 | * PHY in a sparse array (indexed by the enumerate). Each value is represented | |
2398 | * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the | |
2399 | * statistics may be read from the message response. If DMA_ADDR != 0, then the | |
2400 | * statistics are dmad to that (page-aligned location). Locks required: None. | |
2401 | * Returns: 0, ETIME | |
f0d37f42 SH |
2402 | */ |
2403 | #define MC_CMD_PHY_STATS 0x2d | |
f0d37f42 | 2404 | |
05a9320f BH |
2405 | /* MC_CMD_PHY_STATS_IN msgrequest */ |
2406 | #define MC_CMD_PHY_STATS_IN_LEN 8 | |
f2b0befd | 2407 | /* ??? */ |
05a9320f BH |
2408 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 |
2409 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 | |
2410 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 | |
2411 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 | |
2412 | ||
2413 | /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ | |
2414 | #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 | |
2415 | ||
2416 | /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ | |
2417 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) | |
2418 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 | |
2419 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 | |
2420 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS | |
f2b0befd BH |
2421 | /* enum: OUI. */ |
2422 | #define MC_CMD_OUI 0x0 | |
2423 | /* enum: PMA-PMD Link Up. */ | |
2424 | #define MC_CMD_PMA_PMD_LINK_UP 0x1 | |
2425 | /* enum: PMA-PMD RX Fault. */ | |
2426 | #define MC_CMD_PMA_PMD_RX_FAULT 0x2 | |
2427 | /* enum: PMA-PMD TX Fault. */ | |
2428 | #define MC_CMD_PMA_PMD_TX_FAULT 0x3 | |
2429 | /* enum: PMA-PMD Signal */ | |
2430 | #define MC_CMD_PMA_PMD_SIGNAL 0x4 | |
2431 | /* enum: PMA-PMD SNR A. */ | |
2432 | #define MC_CMD_PMA_PMD_SNR_A 0x5 | |
2433 | /* enum: PMA-PMD SNR B. */ | |
2434 | #define MC_CMD_PMA_PMD_SNR_B 0x6 | |
2435 | /* enum: PMA-PMD SNR C. */ | |
2436 | #define MC_CMD_PMA_PMD_SNR_C 0x7 | |
2437 | /* enum: PMA-PMD SNR D. */ | |
2438 | #define MC_CMD_PMA_PMD_SNR_D 0x8 | |
2439 | /* enum: PCS Link Up. */ | |
2440 | #define MC_CMD_PCS_LINK_UP 0x9 | |
2441 | /* enum: PCS RX Fault. */ | |
2442 | #define MC_CMD_PCS_RX_FAULT 0xa | |
2443 | /* enum: PCS TX Fault. */ | |
2444 | #define MC_CMD_PCS_TX_FAULT 0xb | |
2445 | /* enum: PCS BER. */ | |
2446 | #define MC_CMD_PCS_BER 0xc | |
2447 | /* enum: PCS Block Errors. */ | |
2448 | #define MC_CMD_PCS_BLOCK_ERRORS 0xd | |
2449 | /* enum: PhyXS Link Up. */ | |
2450 | #define MC_CMD_PHYXS_LINK_UP 0xe | |
2451 | /* enum: PhyXS RX Fault. */ | |
2452 | #define MC_CMD_PHYXS_RX_FAULT 0xf | |
2453 | /* enum: PhyXS TX Fault. */ | |
2454 | #define MC_CMD_PHYXS_TX_FAULT 0x10 | |
2455 | /* enum: PhyXS Align. */ | |
2456 | #define MC_CMD_PHYXS_ALIGN 0x11 | |
2457 | /* enum: PhyXS Sync. */ | |
2458 | #define MC_CMD_PHYXS_SYNC 0x12 | |
2459 | /* enum: AN link-up. */ | |
2460 | #define MC_CMD_AN_LINK_UP 0x13 | |
2461 | /* enum: AN Complete. */ | |
2462 | #define MC_CMD_AN_COMPLETE 0x14 | |
2463 | /* enum: AN 10GBaseT Status. */ | |
2464 | #define MC_CMD_AN_10GBT_STATUS 0x15 | |
2465 | /* enum: Clause 22 Link-Up. */ | |
2466 | #define MC_CMD_CL22_LINK_UP 0x16 | |
2467 | /* enum: (Last entry) */ | |
2468 | #define MC_CMD_PHY_NSTATS 0x17 | |
05a9320f BH |
2469 | |
2470 | ||
2471 | /***********************************/ | |
2472 | /* MC_CMD_MAC_STATS | |
f2b0befd BH |
2473 | * Get generic MAC statistics. This call returns unified statistics maintained |
2474 | * by the MC as it switches between the GMAC and XMAC. The MC will write out | |
2475 | * all supported stats. The driver should zero initialise the buffer to | |
2476 | * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is | |
2477 | * performed, and the statistics may be read from the message response. If | |
2478 | * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). | |
2479 | * Locks required: None. Returns: 0, ETIME | |
f0d37f42 | 2480 | */ |
05a9320f | 2481 | #define MC_CMD_MAC_STATS 0x2e |
f0d37f42 | 2482 | |
05a9320f BH |
2483 | /* MC_CMD_MAC_STATS_IN msgrequest */ |
2484 | #define MC_CMD_MAC_STATS_IN_LEN 16 | |
f2b0befd | 2485 | /* ??? */ |
05a9320f BH |
2486 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 |
2487 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 | |
2488 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 | |
2489 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 | |
2490 | #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 | |
2491 | #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 | |
2492 | #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 | |
2493 | #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 | |
2494 | #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 | |
2495 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 | |
2496 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 | |
2497 | #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 | |
2498 | #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 | |
2499 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 | |
2500 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 | |
2501 | #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 | |
2502 | #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 | |
2503 | #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 | |
2504 | #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 | |
2505 | #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 | |
2506 | ||
2507 | /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ | |
2508 | #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 | |
2509 | ||
2510 | /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ | |
2511 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) | |
2512 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 | |
2513 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 | |
2514 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 | |
2515 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 | |
2516 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS | |
2517 | #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ | |
2518 | #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ | |
2519 | #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ | |
2520 | #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ | |
2521 | #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ | |
2522 | #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ | |
2523 | #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ | |
2524 | #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ | |
2525 | #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ | |
2526 | #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ | |
2527 | #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ | |
2528 | #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ | |
2529 | #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ | |
2530 | #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ | |
2531 | #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ | |
2532 | #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ | |
2533 | #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ | |
2534 | #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ | |
2535 | #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ | |
2536 | #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ | |
2537 | #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ | |
2538 | #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ | |
2539 | #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ | |
2540 | #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ | |
2541 | #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ | |
2542 | #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ | |
2543 | #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ | |
2544 | #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ | |
2545 | #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ | |
2546 | #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ | |
2547 | #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ | |
2548 | #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ | |
2549 | #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ | |
2550 | #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ | |
2551 | #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ | |
2552 | #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ | |
2553 | #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ | |
2554 | #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ | |
2555 | #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ | |
2556 | #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ | |
2557 | #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ | |
2558 | #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ | |
2559 | #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ | |
2560 | #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ | |
2561 | #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ | |
2562 | #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ | |
2563 | #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ | |
2564 | #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ | |
2565 | #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ | |
2566 | #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ | |
2567 | #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ | |
2568 | #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ | |
2569 | #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ | |
2570 | #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ | |
2571 | #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ | |
2572 | #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ | |
2573 | #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ | |
2574 | #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ | |
2575 | #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ | |
2576 | #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ | |
2577 | #define MC_CMD_GMAC_DMABUF_START 0x40 /* enum */ | |
2578 | #define MC_CMD_GMAC_DMABUF_END 0x5f /* enum */ | |
2579 | #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ | |
2580 | #define MC_CMD_MAC_NSTATS 0x61 /* enum */ | |
2581 | ||
2582 | ||
2583 | /***********************************/ | |
2584 | /* MC_CMD_SRIOV | |
2585 | * to be documented | |
2586 | */ | |
2587 | #define MC_CMD_SRIOV 0x30 | |
2588 | ||
2589 | /* MC_CMD_SRIOV_IN msgrequest */ | |
2590 | #define MC_CMD_SRIOV_IN_LEN 12 | |
2591 | #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 | |
2592 | #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 | |
2593 | #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 | |
2594 | ||
2595 | /* MC_CMD_SRIOV_OUT msgresponse */ | |
2596 | #define MC_CMD_SRIOV_OUT_LEN 8 | |
2597 | #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 | |
2598 | #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 | |
2599 | ||
2600 | /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ | |
2601 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 | |
f2b0befd | 2602 | /* this is only used for the first record */ |
05a9320f BH |
2603 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 |
2604 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 | |
2605 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 | |
2606 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 | |
2607 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 | |
2608 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 | |
2609 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 | |
2610 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 | |
2611 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 | |
2612 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 | |
2613 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 | |
2614 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 | |
2615 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 | |
2616 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ | |
2617 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 | |
2618 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 | |
2619 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 | |
2620 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 | |
2621 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 | |
2622 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 | |
2623 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 | |
2624 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 | |
2625 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 | |
2626 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 | |
2627 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 | |
2628 | ||
2629 | ||
2630 | /***********************************/ | |
2631 | /* MC_CMD_MEMCPY | |
f2b0befd BH |
2632 | * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data |
2633 | * embedded directly in the command. | |
2634 | * | |
2635 | * A common pattern is for a client to use generation counts to signal a dma | |
2636 | * update of a datastructure. To facilitate this, this MCDI operation can | |
2637 | * contain multiple requests which are executed in strict order. Requests take | |
2638 | * the form of duplicating the entire MCDI request continuously (including the | |
2639 | * requests record, which is ignored in all but the first structure) | |
2640 | * | |
2641 | * The source data can either come from a DMA from the host, or it can be | |
2642 | * embedded within the request directly, thereby eliminating a DMA read. To | |
2643 | * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and | |
2644 | * ADDR_LO=offset, and inserts the data at %offset from the start of the | |
2645 | * payload. It's the callers responsibility to ensure that the embedded data | |
2646 | * doesn't overlap the records. | |
2647 | * | |
2648 | * Returns: 0, EINVAL (invalid RID) | |
05a9320f BH |
2649 | */ |
2650 | #define MC_CMD_MEMCPY 0x31 | |
2651 | ||
2652 | /* MC_CMD_MEMCPY_IN msgrequest */ | |
2653 | #define MC_CMD_MEMCPY_IN_LENMIN 32 | |
2654 | #define MC_CMD_MEMCPY_IN_LENMAX 224 | |
2655 | #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) | |
f2b0befd | 2656 | /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ |
05a9320f BH |
2657 | #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 |
2658 | #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 | |
2659 | #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 | |
2660 | #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 | |
2661 | ||
2662 | /* MC_CMD_MEMCPY_OUT msgresponse */ | |
2663 | #define MC_CMD_MEMCPY_OUT_LEN 0 | |
2664 | ||
2665 | ||
2666 | /***********************************/ | |
2667 | /* MC_CMD_WOL_FILTER_SET | |
2668 | * Set a WoL filter. | |
f0d37f42 SH |
2669 | */ |
2670 | #define MC_CMD_WOL_FILTER_SET 0x32 | |
05a9320f BH |
2671 | |
2672 | /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ | |
2673 | #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 | |
2674 | #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 | |
2675 | #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ | |
2676 | #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ | |
f2b0befd | 2677 | /* A type value of 1 is unused. */ |
05a9320f | 2678 | #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 |
f2b0befd BH |
2679 | /* enum: Magic */ |
2680 | #define MC_CMD_WOL_TYPE_MAGIC 0x0 | |
2681 | /* enum: MS Windows Magic */ | |
2682 | #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 | |
2683 | /* enum: IPv4 Syn */ | |
2684 | #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 | |
2685 | /* enum: IPv6 Syn */ | |
2686 | #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 | |
2687 | /* enum: Bitmap */ | |
2688 | #define MC_CMD_WOL_TYPE_BITMAP 0x5 | |
2689 | /* enum: Link */ | |
2690 | #define MC_CMD_WOL_TYPE_LINK 0x6 | |
2691 | /* enum: (Above this for future use) */ | |
2692 | #define MC_CMD_WOL_TYPE_MAX 0x7 | |
05a9320f BH |
2693 | #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 |
2694 | #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 | |
2695 | #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 | |
2696 | ||
2697 | /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ | |
2698 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 | |
2699 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
2700 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
2701 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 | |
2702 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 | |
2703 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 | |
2704 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 | |
2705 | ||
2706 | /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ | |
2707 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 | |
2708 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
2709 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
2710 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 | |
2711 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 | |
2712 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 | |
2713 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 | |
2714 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 | |
2715 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 | |
2716 | ||
2717 | /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ | |
2718 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 | |
2719 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
2720 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
2721 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 | |
2722 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 | |
2723 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 | |
2724 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 | |
2725 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 | |
2726 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 | |
2727 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 | |
2728 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 | |
2729 | ||
2730 | /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ | |
2731 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 | |
2732 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
2733 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
2734 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 | |
2735 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 | |
2736 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 | |
2737 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 | |
2738 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 | |
2739 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 | |
2740 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 | |
2741 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 | |
2742 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 | |
2743 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 | |
2744 | ||
2745 | /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ | |
2746 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 | |
2747 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
2748 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
2749 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 | |
2750 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 | |
2751 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 | |
2752 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 | |
2753 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 | |
2754 | ||
2755 | /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ | |
2756 | #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 | |
2757 | #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 | |
2758 | ||
2759 | ||
2760 | /***********************************/ | |
2761 | /* MC_CMD_WOL_FILTER_REMOVE | |
f2b0befd | 2762 | * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS |
f0d37f42 SH |
2763 | */ |
2764 | #define MC_CMD_WOL_FILTER_REMOVE 0x33 | |
f0d37f42 | 2765 | |
05a9320f BH |
2766 | /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ |
2767 | #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 | |
2768 | #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 | |
f0d37f42 | 2769 | |
05a9320f BH |
2770 | /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ |
2771 | #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 | |
2772 | ||
2773 | ||
2774 | /***********************************/ | |
2775 | /* MC_CMD_WOL_FILTER_RESET | |
f2b0befd BH |
2776 | * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, |
2777 | * ENOSYS | |
f0d37f42 SH |
2778 | */ |
2779 | #define MC_CMD_WOL_FILTER_RESET 0x34 | |
f0d37f42 | 2780 | |
05a9320f BH |
2781 | /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ |
2782 | #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 | |
2783 | #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 | |
2784 | #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ | |
2785 | #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ | |
2786 | ||
2787 | /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ | |
2788 | #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 | |
2789 | ||
2790 | ||
2791 | /***********************************/ | |
2792 | /* MC_CMD_SET_MCAST_HASH | |
f2b0befd | 2793 | * Set the MCAST hash value without otherwise reconfiguring the MAC |
f0d37f42 SH |
2794 | */ |
2795 | #define MC_CMD_SET_MCAST_HASH 0x35 | |
f0d37f42 | 2796 | |
05a9320f BH |
2797 | /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ |
2798 | #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 | |
2799 | #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 | |
2800 | #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 | |
2801 | #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 | |
2802 | #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 | |
2803 | ||
2804 | /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ | |
2805 | #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 | |
2806 | ||
2807 | ||
2808 | /***********************************/ | |
2809 | /* MC_CMD_NVRAM_TYPES | |
f2b0befd BH |
2810 | * Return bitfield indicating available types of virtual NVRAM partitions. |
2811 | * Locks required: none. Returns: 0 | |
f0d37f42 SH |
2812 | */ |
2813 | #define MC_CMD_NVRAM_TYPES 0x36 | |
05a9320f BH |
2814 | |
2815 | /* MC_CMD_NVRAM_TYPES_IN msgrequest */ | |
2816 | #define MC_CMD_NVRAM_TYPES_IN_LEN 0 | |
2817 | ||
2818 | /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ | |
2819 | #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 | |
f2b0befd | 2820 | /* Bit mask of supported types. */ |
05a9320f | 2821 | #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 |
f2b0befd BH |
2822 | /* enum: Disabled callisto. */ |
2823 | #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 | |
2824 | /* enum: MC firmware. */ | |
2825 | #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 | |
2826 | /* enum: MC backup firmware. */ | |
2827 | #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 | |
2828 | /* enum: Static configuration Port0. */ | |
2829 | #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 | |
2830 | /* enum: Static configuration Port1. */ | |
2831 | #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 | |
2832 | /* enum: Dynamic configuration Port0. */ | |
2833 | #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 | |
2834 | /* enum: Dynamic configuration Port1. */ | |
2835 | #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 | |
2836 | /* enum: Expansion Rom. */ | |
2837 | #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 | |
2838 | /* enum: Expansion Rom Configuration Port0. */ | |
2839 | #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 | |
2840 | /* enum: Expansion Rom Configuration Port1. */ | |
2841 | #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 | |
2842 | /* enum: Phy Configuration Port0. */ | |
2843 | #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa | |
2844 | /* enum: Phy Configuration Port1. */ | |
2845 | #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb | |
2846 | /* enum: Log. */ | |
2847 | #define MC_CMD_NVRAM_TYPE_LOG 0xc | |
2848 | /* enum: FPGA image. */ | |
2849 | #define MC_CMD_NVRAM_TYPE_FPGA 0xd | |
2850 | /* enum: FPGA backup image */ | |
2851 | #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe | |
2852 | /* enum: FC firmware. */ | |
2853 | #define MC_CMD_NVRAM_TYPE_FC_FW 0xf | |
2854 | /* enum: FC backup firmware. */ | |
2855 | #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 | |
2856 | /* enum: CPLD image. */ | |
2857 | #define MC_CMD_NVRAM_TYPE_CPLD 0x11 | |
2858 | /* enum: Licensing information. */ | |
2859 | #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 | |
2860 | /* enum: FC Log. */ | |
2861 | #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 | |
05a9320f BH |
2862 | |
2863 | ||
2864 | /***********************************/ | |
2865 | /* MC_CMD_NVRAM_INFO | |
f2b0befd BH |
2866 | * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, |
2867 | * EINVAL (bad type). | |
f0d37f42 SH |
2868 | */ |
2869 | #define MC_CMD_NVRAM_INFO 0x37 | |
05a9320f BH |
2870 | |
2871 | /* MC_CMD_NVRAM_INFO_IN msgrequest */ | |
2872 | #define MC_CMD_NVRAM_INFO_IN_LEN 4 | |
2873 | #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 | |
2874 | /* Enum values, see field(s): */ | |
2875 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
2876 | ||
2877 | /* MC_CMD_NVRAM_INFO_OUT msgresponse */ | |
2878 | #define MC_CMD_NVRAM_INFO_OUT_LEN 24 | |
2879 | #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 | |
2880 | /* Enum values, see field(s): */ | |
2881 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
2882 | #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 | |
2883 | #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 | |
2884 | #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 | |
2885 | #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 | |
2886 | #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 | |
f2b0befd BH |
2887 | #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 |
2888 | #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 | |
2889 | #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 | |
2890 | #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 | |
05a9320f BH |
2891 | #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 |
2892 | #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 | |
2893 | ||
2894 | ||
2895 | /***********************************/ | |
2896 | /* MC_CMD_NVRAM_UPDATE_START | |
f2b0befd BH |
2897 | * Start a group of update operations on a virtual NVRAM partition. Locks |
2898 | * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if | |
2899 | * PHY_LOCK required and not held). | |
f0d37f42 SH |
2900 | */ |
2901 | #define MC_CMD_NVRAM_UPDATE_START 0x38 | |
f0d37f42 | 2902 | |
05a9320f BH |
2903 | /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ |
2904 | #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 | |
2905 | #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 | |
2906 | /* Enum values, see field(s): */ | |
2907 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
2908 | ||
2909 | /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ | |
2910 | #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 | |
2911 | ||
2912 | ||
2913 | /***********************************/ | |
2914 | /* MC_CMD_NVRAM_READ | |
f2b0befd BH |
2915 | * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if |
2916 | * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if | |
2917 | * PHY_LOCK required and not held) | |
f0d37f42 SH |
2918 | */ |
2919 | #define MC_CMD_NVRAM_READ 0x39 | |
05a9320f BH |
2920 | |
2921 | /* MC_CMD_NVRAM_READ_IN msgrequest */ | |
2922 | #define MC_CMD_NVRAM_READ_IN_LEN 12 | |
2923 | #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 | |
2924 | /* Enum values, see field(s): */ | |
2925 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
2926 | #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 | |
f2b0befd | 2927 | /* amount to read in bytes */ |
05a9320f BH |
2928 | #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 |
2929 | ||
2930 | /* MC_CMD_NVRAM_READ_OUT msgresponse */ | |
2931 | #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 | |
576eda8b | 2932 | #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 |
05a9320f BH |
2933 | #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) |
2934 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 | |
2935 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 | |
2936 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 | |
576eda8b | 2937 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 |
05a9320f BH |
2938 | |
2939 | ||
2940 | /***********************************/ | |
2941 | /* MC_CMD_NVRAM_WRITE | |
f2b0befd BH |
2942 | * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if |
2943 | * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if | |
2944 | * PHY_LOCK required and not held) | |
f0d37f42 SH |
2945 | */ |
2946 | #define MC_CMD_NVRAM_WRITE 0x3a | |
05a9320f BH |
2947 | |
2948 | /* MC_CMD_NVRAM_WRITE_IN msgrequest */ | |
2949 | #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 | |
576eda8b | 2950 | #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 |
05a9320f BH |
2951 | #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) |
2952 | #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 | |
2953 | /* Enum values, see field(s): */ | |
2954 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
2955 | #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 | |
2956 | #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 | |
2957 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 | |
2958 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 | |
2959 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 | |
576eda8b | 2960 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 |
05a9320f BH |
2961 | |
2962 | /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ | |
2963 | #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 | |
2964 | ||
2965 | ||
2966 | /***********************************/ | |
2967 | /* MC_CMD_NVRAM_ERASE | |
f2b0befd BH |
2968 | * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if |
2969 | * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if | |
2970 | * PHY_LOCK required and not held) | |
f0d37f42 SH |
2971 | */ |
2972 | #define MC_CMD_NVRAM_ERASE 0x3b | |
05a9320f BH |
2973 | |
2974 | /* MC_CMD_NVRAM_ERASE_IN msgrequest */ | |
2975 | #define MC_CMD_NVRAM_ERASE_IN_LEN 12 | |
2976 | #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 | |
2977 | /* Enum values, see field(s): */ | |
2978 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
2979 | #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 | |
2980 | #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 | |
2981 | ||
2982 | /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ | |
2983 | #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 | |
2984 | ||
2985 | ||
2986 | /***********************************/ | |
2987 | /* MC_CMD_NVRAM_UPDATE_FINISH | |
f2b0befd BH |
2988 | * Finish a group of update operations on a virtual NVRAM partition. Locks |
2989 | * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad | |
2990 | * type/offset/length), EACCES (if PHY_LOCK required and not held) | |
f0d37f42 SH |
2991 | */ |
2992 | #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c | |
f0d37f42 | 2993 | |
05a9320f BH |
2994 | /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ |
2995 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 | |
2996 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 | |
2997 | /* Enum values, see field(s): */ | |
2998 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
2999 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 | |
3000 | ||
3001 | /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ | |
3002 | #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 | |
3003 | ||
3004 | ||
3005 | /***********************************/ | |
3006 | /* MC_CMD_REBOOT | |
5297a98d | 3007 | * Reboot the MC. |
f2b0befd BH |
3008 | * |
3009 | * The AFTER_ASSERTION flag is intended to be used when the driver notices an | |
3010 | * assertion failure (at which point it is expected to perform a complete tear | |
3011 | * down and reinitialise), to allow both ports to reset the MC once in an | |
3012 | * atomic fashion. | |
3013 | * | |
3014 | * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, | |
3015 | * which means that they will automatically reboot out of the assertion | |
3016 | * handler, so this is in practise an optional operation. It is still | |
3017 | * recommended that drivers execute this to support custom firmwares with | |
3018 | * REBOOT_ON_ASSERT=0. | |
3019 | * | |
3020 | * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, | |
3021 | * DATALEN=0 | |
f0d37f42 SH |
3022 | */ |
3023 | #define MC_CMD_REBOOT 0x3d | |
f0d37f42 | 3024 | |
05a9320f BH |
3025 | /* MC_CMD_REBOOT_IN msgrequest */ |
3026 | #define MC_CMD_REBOOT_IN_LEN 4 | |
3027 | #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 | |
3028 | #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ | |
3029 | ||
3030 | /* MC_CMD_REBOOT_OUT msgresponse */ | |
3031 | #define MC_CMD_REBOOT_OUT_LEN 0 | |
3032 | ||
3033 | ||
3034 | /***********************************/ | |
3035 | /* MC_CMD_SCHEDINFO | |
f2b0befd BH |
3036 | * Request scheduler info. Locks required: NONE. Returns: An array of |
3037 | * (timeslice,maximum overrun), one for each thread, in ascending order of | |
3038 | * thread address. | |
f0d37f42 SH |
3039 | */ |
3040 | #define MC_CMD_SCHEDINFO 0x3e | |
f0d37f42 | 3041 | |
05a9320f BH |
3042 | /* MC_CMD_SCHEDINFO_IN msgrequest */ |
3043 | #define MC_CMD_SCHEDINFO_IN_LEN 0 | |
f0d37f42 | 3044 | |
05a9320f BH |
3045 | /* MC_CMD_SCHEDINFO_OUT msgresponse */ |
3046 | #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 | |
3047 | #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 | |
3048 | #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) | |
3049 | #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 | |
3050 | #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 | |
3051 | #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 | |
3052 | #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 | |
3053 | ||
3054 | ||
3055 | /***********************************/ | |
3056 | /* MC_CMD_REBOOT_MODE | |
f2b0befd BH |
3057 | * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot |
3058 | * mode to the specified value. Returns the old mode. | |
f0d37f42 SH |
3059 | */ |
3060 | #define MC_CMD_REBOOT_MODE 0x3f | |
05a9320f BH |
3061 | |
3062 | /* MC_CMD_REBOOT_MODE_IN msgrequest */ | |
3063 | #define MC_CMD_REBOOT_MODE_IN_LEN 4 | |
3064 | #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 | |
f2b0befd BH |
3065 | /* enum: Normal. */ |
3066 | #define MC_CMD_REBOOT_MODE_NORMAL 0x0 | |
3067 | /* enum: Power-on Reset. */ | |
3068 | #define MC_CMD_REBOOT_MODE_POR 0x2 | |
3069 | /* enum: Snapper. */ | |
3070 | #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 | |
3071 | /* enum: snapper fake POR */ | |
3072 | #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 | |
3073 | #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 | |
3074 | #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 | |
05a9320f BH |
3075 | |
3076 | /* MC_CMD_REBOOT_MODE_OUT msgresponse */ | |
3077 | #define MC_CMD_REBOOT_MODE_OUT_LEN 4 | |
3078 | #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 | |
3079 | ||
3080 | ||
3081 | /***********************************/ | |
3082 | /* MC_CMD_SENSOR_INFO | |
f0d37f42 | 3083 | * Returns information about every available sensor. |
f2b0befd BH |
3084 | * |
3085 | * Each sensor has a single (16bit) value, and a corresponding state. The | |
3086 | * mapping between value and state is nominally determined by the MC, but may | |
3087 | * be implemented using up to 2 ranges per sensor. | |
3088 | * | |
3089 | * This call returns a mask (32bit) of the sensors that are supported by this | |
3090 | * platform, then an array of sensor information structures, in order of sensor | |
3091 | * type (but without gaps for unimplemented sensors). Each structure defines | |
3092 | * the ranges for the corresponding sensor. An unused range is indicated by | |
3093 | * equal limit values. If one range is used, a value outside that range results | |
3094 | * in STATE_FATAL. If two ranges are used, a value outside the second range | |
3095 | * results in STATE_FATAL while a value outside the first and inside the second | |
3096 | * range results in STATE_WARNING. | |
3097 | * | |
3098 | * Sensor masks and sensor information arrays are organised into pages. For | |
3099 | * backward compatibility, older host software can only use sensors in page 0. | |
3100 | * Bit 32 in the sensor mask was previously unused, and is no reserved for use | |
3101 | * as the next page flag. | |
3102 | * | |
3103 | * If the request does not contain a PAGE value then firmware will only return | |
3104 | * page 0 of sensor information, with bit 31 in the sensor mask cleared. | |
3105 | * | |
3106 | * If the request contains a PAGE value then firmware responds with the sensor | |
3107 | * mask and sensor information array for that page of sensors. In this case bit | |
3108 | * 31 in the mask is set if another page exists. | |
3109 | * | |
3110 | * Locks required: None Returns: 0 | |
f0d37f42 SH |
3111 | */ |
3112 | #define MC_CMD_SENSOR_INFO 0x41 | |
f0d37f42 | 3113 | |
05a9320f BH |
3114 | /* MC_CMD_SENSOR_INFO_IN msgrequest */ |
3115 | #define MC_CMD_SENSOR_INFO_IN_LEN 0 | |
3116 | ||
f2b0befd BH |
3117 | /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ |
3118 | #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 | |
3119 | /* Which page of sensors to report. | |
3120 | * | |
3121 | * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). | |
3122 | * | |
3123 | * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. | |
3124 | */ | |
3125 | #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 | |
3126 | ||
05a9320f BH |
3127 | /* MC_CMD_SENSOR_INFO_OUT msgresponse */ |
3128 | #define MC_CMD_SENSOR_INFO_OUT_LENMIN 12 | |
3129 | #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 | |
3130 | #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) | |
3131 | #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 | |
f2b0befd BH |
3132 | /* enum: Controller temperature: degC */ |
3133 | #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 | |
3134 | /* enum: Phy common temperature: degC */ | |
3135 | #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 | |
3136 | /* enum: Controller cooling: bool */ | |
3137 | #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 | |
3138 | /* enum: Phy 0 temperature: degC */ | |
3139 | #define MC_CMD_SENSOR_PHY0_TEMP 0x3 | |
3140 | /* enum: Phy 0 cooling: bool */ | |
3141 | #define MC_CMD_SENSOR_PHY0_COOLING 0x4 | |
3142 | /* enum: Phy 1 temperature: degC */ | |
3143 | #define MC_CMD_SENSOR_PHY1_TEMP 0x5 | |
3144 | /* enum: Phy 1 cooling: bool */ | |
3145 | #define MC_CMD_SENSOR_PHY1_COOLING 0x6 | |
3146 | /* enum: 1.0v power: mV */ | |
3147 | #define MC_CMD_SENSOR_IN_1V0 0x7 | |
3148 | /* enum: 1.2v power: mV */ | |
3149 | #define MC_CMD_SENSOR_IN_1V2 0x8 | |
3150 | /* enum: 1.8v power: mV */ | |
3151 | #define MC_CMD_SENSOR_IN_1V8 0x9 | |
3152 | /* enum: 2.5v power: mV */ | |
3153 | #define MC_CMD_SENSOR_IN_2V5 0xa | |
3154 | /* enum: 3.3v power: mV */ | |
3155 | #define MC_CMD_SENSOR_IN_3V3 0xb | |
3156 | /* enum: 12v power: mV */ | |
3157 | #define MC_CMD_SENSOR_IN_12V0 0xc | |
3158 | /* enum: 1.2v analogue power: mV */ | |
3159 | #define MC_CMD_SENSOR_IN_1V2A 0xd | |
3160 | /* enum: reference voltage: mV */ | |
3161 | #define MC_CMD_SENSOR_IN_VREF 0xe | |
3162 | /* enum: AOE FPGA power: mV */ | |
3163 | #define MC_CMD_SENSOR_OUT_VAOE 0xf | |
3164 | /* enum: AOE FPGA temperature: degC */ | |
3165 | #define MC_CMD_SENSOR_AOE_TEMP 0x10 | |
3166 | /* enum: AOE FPGA PSU temperature: degC */ | |
3167 | #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 | |
3168 | /* enum: AOE PSU temperature: degC */ | |
3169 | #define MC_CMD_SENSOR_PSU_TEMP 0x12 | |
3170 | /* enum: Fan 0 speed: RPM */ | |
3171 | #define MC_CMD_SENSOR_FAN_0 0x13 | |
3172 | /* enum: Fan 1 speed: RPM */ | |
3173 | #define MC_CMD_SENSOR_FAN_1 0x14 | |
3174 | /* enum: Fan 2 speed: RPM */ | |
3175 | #define MC_CMD_SENSOR_FAN_2 0x15 | |
3176 | /* enum: Fan 3 speed: RPM */ | |
3177 | #define MC_CMD_SENSOR_FAN_3 0x16 | |
3178 | /* enum: Fan 4 speed: RPM */ | |
3179 | #define MC_CMD_SENSOR_FAN_4 0x17 | |
3180 | /* enum: AOE FPGA input power: mV */ | |
3181 | #define MC_CMD_SENSOR_IN_VAOE 0x18 | |
3182 | /* enum: AOE FPGA current: mA */ | |
3183 | #define MC_CMD_SENSOR_OUT_IAOE 0x19 | |
3184 | /* enum: AOE FPGA input current: mA */ | |
3185 | #define MC_CMD_SENSOR_IN_IAOE 0x1a | |
3186 | /* enum: NIC power consumption: W */ | |
3187 | #define MC_CMD_SENSOR_NIC_POWER 0x1b | |
3188 | /* enum: 0.9v power voltage: mV */ | |
3189 | #define MC_CMD_SENSOR_IN_0V9 0x1c | |
3190 | /* enum: 0.9v power current: mA */ | |
3191 | #define MC_CMD_SENSOR_IN_I0V9 0x1d | |
3192 | /* enum: 1.2v power current: mA */ | |
3193 | #define MC_CMD_SENSOR_IN_I1V2 0x1e | |
3194 | /* enum: Not a sensor: reserved for the next page flag */ | |
3195 | #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f | |
3196 | /* enum: 0.9v power voltage (at ADC): mV */ | |
3197 | #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 | |
3198 | /* enum: Controller temperature 2: degC */ | |
3199 | #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 | |
3200 | /* enum: Voltage regulator internal temperature: degC */ | |
3201 | #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 | |
3202 | /* enum: 0.9V voltage regulator temperature: degC */ | |
3203 | #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 | |
3204 | /* enum: 1.2V voltage regulator temperature: degC */ | |
3205 | #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 | |
3206 | /* enum: controller internal temperature sensor voltage (internal ADC): mV */ | |
3207 | #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 | |
3208 | /* enum: controller internal temperature (internal ADC): degC */ | |
3209 | #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 | |
3210 | /* enum: controller internal temperature sensor voltage (external ADC): mV */ | |
3211 | #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 | |
3212 | /* enum: controller internal temperature (external ADC): degC */ | |
3213 | #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 | |
3214 | /* enum: ambient temperature: degC */ | |
3215 | #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 | |
3216 | /* enum: air flow: bool */ | |
3217 | #define MC_CMD_SENSOR_AIRFLOW 0x2a | |
3218 | /* enum: voltage between VSS08D and VSS08D at CSR: mV */ | |
3219 | #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b | |
3220 | /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ | |
3221 | #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c | |
3222 | /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ | |
05a9320f BH |
3223 | #define MC_CMD_SENSOR_ENTRY_OFST 4 |
3224 | #define MC_CMD_SENSOR_ENTRY_LEN 8 | |
3225 | #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 | |
3226 | #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 | |
3227 | #define MC_CMD_SENSOR_ENTRY_MINNUM 1 | |
3228 | #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 | |
3229 | ||
f2b0befd BH |
3230 | /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ |
3231 | #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 12 | |
3232 | #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 | |
3233 | #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) | |
3234 | #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 | |
3235 | /* Enum values, see field(s): */ | |
3236 | /* MC_CMD_SENSOR_INFO_OUT */ | |
3237 | #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 | |
3238 | #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 | |
3239 | /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ | |
3240 | /* MC_CMD_SENSOR_ENTRY_OFST 4 */ | |
3241 | /* MC_CMD_SENSOR_ENTRY_LEN 8 */ | |
3242 | /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ | |
3243 | /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ | |
3244 | /* MC_CMD_SENSOR_ENTRY_MINNUM 1 */ | |
3245 | /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ | |
3246 | ||
05a9320f BH |
3247 | /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ |
3248 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 | |
3249 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 | |
3250 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 | |
3251 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 | |
3252 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 | |
3253 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 | |
3254 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 | |
3255 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 | |
3256 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 | |
3257 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 | |
3258 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 | |
3259 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 | |
3260 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 | |
3261 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 | |
3262 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 | |
3263 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 | |
3264 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 | |
3265 | ||
3266 | ||
3267 | /***********************************/ | |
f0d37f42 | 3268 | /* MC_CMD_READ_SENSORS |
f2b0befd BH |
3269 | * Returns the current reading from each sensor. DMAs an array of sensor |
3270 | * readings, in order of sensor type (but without gaps for unimplemented | |
3271 | * sensors), into host memory. Each array element is a | |
3272 | * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. | |
3273 | * | |
3274 | * If the request does not contain the LENGTH field then only sensors 0 to 30 | |
3275 | * are reported, to avoid DMA buffer overflow in older host software. If the | |
3276 | * sensor reading require more space than the LENGTH allows, then return | |
3277 | * EINVAL. | |
3278 | * | |
3279 | * The MC will send a SENSOREVT event every time any sensor changes state. The | |
3280 | * driver is responsible for ensuring that it doesn't miss any events. The | |
3281 | * board will function normally if all sensors are in STATE_OK or | |
3282 | * STATE_WARNING. Otherwise the board should not be expected to function. | |
f0d37f42 SH |
3283 | */ |
3284 | #define MC_CMD_READ_SENSORS 0x42 | |
f0d37f42 | 3285 | |
05a9320f BH |
3286 | /* MC_CMD_READ_SENSORS_IN msgrequest */ |
3287 | #define MC_CMD_READ_SENSORS_IN_LEN 8 | |
f2b0befd | 3288 | /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ |
05a9320f BH |
3289 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 |
3290 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 | |
3291 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 | |
3292 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 | |
3293 | ||
f2b0befd BH |
3294 | /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ |
3295 | #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 | |
3296 | /* DMA address of host buffer for sensor readings */ | |
3297 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 | |
3298 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 | |
3299 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 | |
3300 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 | |
3301 | /* Size in bytes of host buffer. */ | |
3302 | #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 | |
3303 | ||
05a9320f BH |
3304 | /* MC_CMD_READ_SENSORS_OUT msgresponse */ |
3305 | #define MC_CMD_READ_SENSORS_OUT_LEN 0 | |
3306 | ||
f2b0befd BH |
3307 | /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ |
3308 | #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 | |
3309 | ||
05a9320f | 3310 | /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ |
f2b0befd | 3311 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 |
05a9320f BH |
3312 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 |
3313 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 | |
3314 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 | |
3315 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 | |
3316 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 | |
3317 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 | |
f2b0befd BH |
3318 | /* enum: Ok. */ |
3319 | #define MC_CMD_SENSOR_STATE_OK 0x0 | |
3320 | /* enum: Breached warning threshold. */ | |
3321 | #define MC_CMD_SENSOR_STATE_WARNING 0x1 | |
3322 | /* enum: Breached fatal threshold. */ | |
3323 | #define MC_CMD_SENSOR_STATE_FATAL 0x2 | |
3324 | /* enum: Fault with sensor. */ | |
3325 | #define MC_CMD_SENSOR_STATE_BROKEN 0x3 | |
3326 | /* enum: Sensor is working but does not currently have a reading. */ | |
3327 | #define MC_CMD_SENSOR_STATE_NO_READING 0x4 | |
05a9320f BH |
3328 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 |
3329 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 | |
f2b0befd BH |
3330 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 |
3331 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 | |
3332 | /* Enum values, see field(s): */ | |
3333 | /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ | |
3334 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 | |
3335 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 | |
05a9320f BH |
3336 | |
3337 | ||
3338 | /***********************************/ | |
3339 | /* MC_CMD_GET_PHY_STATE | |
f2b0befd BH |
3340 | * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot |
3341 | * (e.g. due to missing or corrupted firmware). Locks required: None. Return | |
3342 | * code: 0 | |
f0d37f42 SH |
3343 | */ |
3344 | #define MC_CMD_GET_PHY_STATE 0x43 | |
3345 | ||
05a9320f BH |
3346 | /* MC_CMD_GET_PHY_STATE_IN msgrequest */ |
3347 | #define MC_CMD_GET_PHY_STATE_IN_LEN 0 | |
f0d37f42 | 3348 | |
05a9320f BH |
3349 | /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ |
3350 | #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 | |
3351 | #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 | |
f2b0befd BH |
3352 | /* enum: Ok. */ |
3353 | #define MC_CMD_PHY_STATE_OK 0x1 | |
3354 | /* enum: Faulty. */ | |
3355 | #define MC_CMD_PHY_STATE_ZOMBIE 0x2 | |
f0d37f42 | 3356 | |
05a9320f BH |
3357 | |
3358 | /***********************************/ | |
3359 | /* MC_CMD_SETUP_8021QBB | |
f2b0befd BH |
3360 | * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to |
3361 | * disable 802.Qbb for a given priority. | |
05a9320f | 3362 | */ |
f0d37f42 | 3363 | #define MC_CMD_SETUP_8021QBB 0x44 |
f0d37f42 | 3364 | |
05a9320f BH |
3365 | /* MC_CMD_SETUP_8021QBB_IN msgrequest */ |
3366 | #define MC_CMD_SETUP_8021QBB_IN_LEN 32 | |
3367 | #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 | |
3368 | #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 | |
f0d37f42 | 3369 | |
05a9320f BH |
3370 | /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ |
3371 | #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 | |
f0d37f42 SH |
3372 | |
3373 | ||
05a9320f BH |
3374 | /***********************************/ |
3375 | /* MC_CMD_WOL_FILTER_GET | |
f2b0befd | 3376 | * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS |
f0d37f42 | 3377 | */ |
05a9320f | 3378 | #define MC_CMD_WOL_FILTER_GET 0x45 |
f0d37f42 | 3379 | |
05a9320f BH |
3380 | /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ |
3381 | #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 | |
f0d37f42 | 3382 | |
05a9320f BH |
3383 | /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ |
3384 | #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 | |
3385 | #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 | |
f0d37f42 | 3386 | |
f0d37f42 | 3387 | |
05a9320f BH |
3388 | /***********************************/ |
3389 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD | |
f2b0befd BH |
3390 | * Add a protocol offload to NIC for lights-out state. Locks required: None. |
3391 | * Returns: 0, ENOSYS | |
05a9320f BH |
3392 | */ |
3393 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 | |
f0d37f42 | 3394 | |
05a9320f BH |
3395 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ |
3396 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 | |
3397 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 | |
3398 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) | |
3399 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 | |
3400 | #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ | |
3401 | #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ | |
3402 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 | |
3403 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 | |
3404 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 | |
3405 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 | |
3406 | ||
3407 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ | |
3408 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 | |
3409 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ | |
3410 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 | |
3411 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 | |
3412 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 | |
3413 | ||
3414 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ | |
3415 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 | |
3416 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ | |
3417 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 | |
3418 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 | |
3419 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 | |
3420 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 | |
3421 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 | |
3422 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 | |
3423 | ||
3424 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ | |
3425 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 | |
3426 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 | |
3427 | ||
3428 | ||
3429 | /***********************************/ | |
3430 | /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD | |
f2b0befd BH |
3431 | * Remove a protocol offload from NIC for lights-out state. Locks required: |
3432 | * None. Returns: 0, ENOSYS | |
f0d37f42 SH |
3433 | */ |
3434 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 | |
f0d37f42 | 3435 | |
05a9320f BH |
3436 | /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ |
3437 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 | |
3438 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 | |
3439 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 | |
f0d37f42 | 3440 | |
05a9320f BH |
3441 | /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ |
3442 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 | |
f0d37f42 SH |
3443 | |
3444 | ||
05a9320f BH |
3445 | /***********************************/ |
3446 | /* MC_CMD_MAC_RESET_RESTORE | |
f2b0befd | 3447 | * Restore MAC after block reset. Locks required: None. Returns: 0. |
f0d37f42 | 3448 | */ |
f0d37f42 | 3449 | #define MC_CMD_MAC_RESET_RESTORE 0x48 |
f0d37f42 | 3450 | |
05a9320f BH |
3451 | /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ |
3452 | #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 | |
3453 | ||
3454 | /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ | |
3455 | #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 | |
5297a98d | 3456 | |
5297a98d | 3457 | |
05a9320f BH |
3458 | /***********************************/ |
3459 | /* MC_CMD_TESTASSERT | |
f2b0befd BH |
3460 | * Deliberately trigger an assert-detonation in the firmware for testing |
3461 | * purposes (i.e. to allow tests that the driver copes gracefully). Locks | |
3462 | * required: None Returns: 0 | |
05a9320f | 3463 | */ |
5297a98d | 3464 | #define MC_CMD_TESTASSERT 0x49 |
5297a98d | 3465 | |
05a9320f BH |
3466 | /* MC_CMD_TESTASSERT_IN msgrequest */ |
3467 | #define MC_CMD_TESTASSERT_IN_LEN 0 | |
3468 | ||
3469 | /* MC_CMD_TESTASSERT_OUT msgresponse */ | |
3470 | #define MC_CMD_TESTASSERT_OUT_LEN 0 | |
3471 | ||
3472 | ||
3473 | /***********************************/ | |
3474 | /* MC_CMD_WORKAROUND | |
f2b0befd BH |
3475 | * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't |
3476 | * understand the given workaround number - which should not be treated as a | |
3477 | * hard error by client code. This op does not imply any semantics about each | |
3478 | * workaround, that's between the driver and the mcfw on a per-workaround | |
3479 | * basis. Locks required: None. Returns: 0, EINVAL . | |
5297a98d BH |
3480 | */ |
3481 | #define MC_CMD_WORKAROUND 0x4a | |
05a9320f BH |
3482 | |
3483 | /* MC_CMD_WORKAROUND_IN msgrequest */ | |
3484 | #define MC_CMD_WORKAROUND_IN_LEN 8 | |
3485 | #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 | |
f2b0befd BH |
3486 | /* enum: Bug 17230 work around. */ |
3487 | #define MC_CMD_WORKAROUND_BUG17230 0x1 | |
3488 | /* enum: Bug 35388 work around (unsafe EVQ writes). */ | |
3489 | #define MC_CMD_WORKAROUND_BUG35388 0x2 | |
3490 | /* enum: Bug35017 workaround (A64 tables must be identity map) */ | |
3491 | #define MC_CMD_WORKAROUND_BUG35017 0x3 | |
05a9320f BH |
3492 | #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 |
3493 | ||
3494 | /* MC_CMD_WORKAROUND_OUT msgresponse */ | |
3495 | #define MC_CMD_WORKAROUND_OUT_LEN 0 | |
3496 | ||
3497 | ||
3498 | /***********************************/ | |
3499 | /* MC_CMD_GET_PHY_MEDIA_INFO | |
f2b0befd BH |
3500 | * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for |
3501 | * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG | |
3502 | * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the | |
3503 | * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 | |
3504 | * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. | |
3505 | * Anything else: currently undefined. Locks required: None. Return code: 0. | |
5297a98d BH |
3506 | */ |
3507 | #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b | |
05a9320f BH |
3508 | |
3509 | /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ | |
3510 | #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 | |
3511 | #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 | |
3512 | ||
3513 | /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ | |
3514 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 | |
576eda8b | 3515 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 |
05a9320f | 3516 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) |
f2b0befd | 3517 | /* in bytes */ |
05a9320f BH |
3518 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 |
3519 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 | |
3520 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 | |
3521 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 | |
576eda8b | 3522 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 |
05a9320f BH |
3523 | |
3524 | ||
3525 | /***********************************/ | |
3526 | /* MC_CMD_NVRAM_TEST | |
f2b0befd BH |
3527 | * Test a particular NVRAM partition for valid contents (where "valid" depends |
3528 | * on the type of partition). | |
5297a98d BH |
3529 | */ |
3530 | #define MC_CMD_NVRAM_TEST 0x4c | |
05a9320f BH |
3531 | |
3532 | /* MC_CMD_NVRAM_TEST_IN msgrequest */ | |
3533 | #define MC_CMD_NVRAM_TEST_IN_LEN 4 | |
3534 | #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 | |
3535 | /* Enum values, see field(s): */ | |
3536 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3537 | ||
3538 | /* MC_CMD_NVRAM_TEST_OUT msgresponse */ | |
3539 | #define MC_CMD_NVRAM_TEST_OUT_LEN 4 | |
3540 | #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 | |
f2b0befd BH |
3541 | /* enum: Passed. */ |
3542 | #define MC_CMD_NVRAM_TEST_PASS 0x0 | |
3543 | /* enum: Failed. */ | |
3544 | #define MC_CMD_NVRAM_TEST_FAIL 0x1 | |
3545 | /* enum: Not supported. */ | |
3546 | #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 | |
05a9320f BH |
3547 | |
3548 | ||
3549 | /***********************************/ | |
3550 | /* MC_CMD_MRSFP_TWEAK | |
f2b0befd BH |
3551 | * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. |
3552 | * I2C I/O expander bits are always read; if equaliser parameters are supplied, | |
3553 | * they are configured first. Locks required: None. Return code: 0, EINVAL. | |
5297a98d BH |
3554 | */ |
3555 | #define MC_CMD_MRSFP_TWEAK 0x4d | |
05a9320f BH |
3556 | |
3557 | /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ | |
3558 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 | |
f2b0befd | 3559 | /* 0-6 low->high de-emph. */ |
05a9320f | 3560 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 |
f2b0befd | 3561 | /* 0-8 low->high ref.V */ |
05a9320f | 3562 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 |
f2b0befd | 3563 | /* 0-8 0-8 low->high boost */ |
05a9320f | 3564 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 |
f2b0befd | 3565 | /* 0-8 low->high ref.V */ |
05a9320f BH |
3566 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 |
3567 | ||
3568 | /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ | |
3569 | #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 | |
3570 | ||
3571 | /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ | |
3572 | #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 | |
f2b0befd | 3573 | /* input bits */ |
05a9320f | 3574 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 |
f2b0befd | 3575 | /* output bits */ |
05a9320f | 3576 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 |
f2b0befd | 3577 | /* direction */ |
05a9320f | 3578 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 |
f2b0befd BH |
3579 | /* enum: Out. */ |
3580 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 | |
3581 | /* enum: In. */ | |
3582 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 | |
05a9320f BH |
3583 | |
3584 | ||
3585 | /***********************************/ | |
3586 | /* MC_CMD_SENSOR_SET_LIMS | |
f2b0befd BH |
3587 | * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: |
3588 | * ENOENT if the sensor specified does not exist, EINVAL if the limits are out | |
3589 | * of range. | |
fbcfe8e1 BH |
3590 | */ |
3591 | #define MC_CMD_SENSOR_SET_LIMS 0x4e | |
05a9320f BH |
3592 | |
3593 | /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ | |
3594 | #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 | |
3595 | #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 | |
3596 | /* Enum values, see field(s): */ | |
3597 | /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ | |
f2b0befd | 3598 | /* interpretation is is sensor-specific. */ |
05a9320f | 3599 | #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 |
f2b0befd | 3600 | /* interpretation is is sensor-specific. */ |
05a9320f | 3601 | #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 |
f2b0befd | 3602 | /* interpretation is is sensor-specific. */ |
05a9320f | 3603 | #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 |
f2b0befd | 3604 | /* interpretation is is sensor-specific. */ |
05a9320f BH |
3605 | #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 |
3606 | ||
3607 | /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ | |
3608 | #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 | |
3609 | ||
3610 | ||
3611 | /***********************************/ | |
3612 | /* MC_CMD_GET_RESOURCE_LIMITS | |
3613 | */ | |
3614 | #define MC_CMD_GET_RESOURCE_LIMITS 0x4f | |
3615 | ||
3616 | /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ | |
3617 | #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 | |
3618 | ||
3619 | /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ | |
3620 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 | |
3621 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 | |
3622 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 | |
3623 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 | |
3624 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 | |
3625 | ||
f2b0befd BH |
3626 | |
3627 | /***********************************/ | |
3628 | /* MC_CMD_NVRAM_PARTITIONS | |
3629 | * Reads the list of available virtual NVRAM partition types. Locks required: | |
3630 | * none. Returns: 0, EINVAL (bad type). | |
3631 | */ | |
3632 | #define MC_CMD_NVRAM_PARTITIONS 0x51 | |
3633 | ||
3634 | /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ | |
3635 | #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 | |
3636 | ||
3637 | /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ | |
3638 | #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 | |
3639 | #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 | |
3640 | #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) | |
3641 | /* total number of partitions */ | |
3642 | #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 | |
3643 | /* type ID code for each of NUM_PARTITIONS partitions */ | |
3644 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 | |
3645 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 | |
3646 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 | |
3647 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 | |
3648 | ||
3649 | ||
3650 | /***********************************/ | |
3651 | /* MC_CMD_NVRAM_METADATA | |
3652 | * Reads soft metadata for a virtual NVRAM partition type. Locks required: | |
3653 | * none. Returns: 0, EINVAL (bad type). | |
3654 | */ | |
3655 | #define MC_CMD_NVRAM_METADATA 0x52 | |
3656 | ||
3657 | /* MC_CMD_NVRAM_METADATA_IN msgrequest */ | |
3658 | #define MC_CMD_NVRAM_METADATA_IN_LEN 4 | |
3659 | /* Partition type ID code */ | |
3660 | #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 | |
3661 | ||
3662 | /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ | |
3663 | #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 | |
3664 | #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 | |
3665 | #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) | |
3666 | /* Partition type ID code */ | |
3667 | #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 | |
3668 | #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 | |
3669 | #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 | |
3670 | #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 | |
3671 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 | |
3672 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 | |
3673 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 | |
3674 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 | |
3675 | /* Subtype ID code for content of this partition */ | |
3676 | #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 | |
3677 | /* 1st component of W.X.Y.Z version number for content of this partition */ | |
3678 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 | |
3679 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 | |
3680 | /* 2nd component of W.X.Y.Z version number for content of this partition */ | |
3681 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 | |
3682 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 | |
3683 | /* 3rd component of W.X.Y.Z version number for content of this partition */ | |
3684 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 | |
3685 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 | |
3686 | /* 4th component of W.X.Y.Z version number for content of this partition */ | |
3687 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 | |
3688 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 | |
3689 | /* Zero-terminated string describing the content of this partition */ | |
3690 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 | |
3691 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 | |
3692 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 | |
3693 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 | |
3694 | ||
3695 | ||
3696 | /***********************************/ | |
3697 | /* MC_CMD_GET_MAC_ADDRESSES | |
3698 | * Returns the base MAC, count and stride for the requestiong function | |
3699 | */ | |
3700 | #define MC_CMD_GET_MAC_ADDRESSES 0x55 | |
3701 | ||
3702 | /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ | |
3703 | #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 | |
3704 | ||
3705 | /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ | |
3706 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 | |
3707 | /* Base MAC address */ | |
3708 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 | |
3709 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 | |
3710 | /* Padding */ | |
3711 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 | |
3712 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 | |
3713 | /* Number of allocated MAC addresses */ | |
3714 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 | |
3715 | /* Spacing of allocated MAC addresses */ | |
3716 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 | |
3717 | ||
05a9320f | 3718 | /* MC_CMD_RESOURCE_SPECIFIER enum */ |
f2b0befd BH |
3719 | /* enum: Any */ |
3720 | #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff | |
3721 | /* enum: None */ | |
3722 | #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe | |
3723 | ||
3724 | /* EVB_PORT_ID structuredef */ | |
3725 | #define EVB_PORT_ID_LEN 4 | |
3726 | #define EVB_PORT_ID_PORT_ID_OFST 0 | |
3727 | /* enum: An invalid port handle. */ | |
3728 | #define EVB_PORT_ID_NULL 0x0 | |
3729 | /* enum: The port assigned to this function.. */ | |
3730 | #define EVB_PORT_ID_ASSIGNED 0x1000000 | |
3731 | /* enum: External network port 0 */ | |
3732 | #define EVB_PORT_ID_MAC0 0x2000000 | |
3733 | /* enum: External network port 1 */ | |
3734 | #define EVB_PORT_ID_MAC1 0x2000001 | |
3735 | /* enum: External network port 2 */ | |
3736 | #define EVB_PORT_ID_MAC2 0x2000002 | |
3737 | /* enum: External network port 3 */ | |
3738 | #define EVB_PORT_ID_MAC3 0x2000003 | |
3739 | #define EVB_PORT_ID_PORT_ID_LBN 0 | |
3740 | #define EVB_PORT_ID_PORT_ID_WIDTH 32 | |
3741 | ||
3742 | /* EVB_VLAN_TAG structuredef */ | |
3743 | #define EVB_VLAN_TAG_LEN 2 | |
3744 | /* The VLAN tag value */ | |
3745 | #define EVB_VLAN_TAG_VLAN_ID_LBN 0 | |
3746 | #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 | |
3747 | #define EVB_VLAN_TAG_MODE_LBN 12 | |
3748 | #define EVB_VLAN_TAG_MODE_WIDTH 4 | |
3749 | /* enum: Insert the VLAN. */ | |
3750 | #define EVB_VLAN_TAG_INSERT 0x0 | |
3751 | /* enum: Replace the VLAN if already present. */ | |
3752 | #define EVB_VLAN_TAG_REPLACE 0x1 | |
3753 | ||
3754 | /* BUFTBL_ENTRY structuredef */ | |
3755 | #define BUFTBL_ENTRY_LEN 12 | |
3756 | /* the owner ID */ | |
3757 | #define BUFTBL_ENTRY_OID_OFST 0 | |
3758 | #define BUFTBL_ENTRY_OID_LEN 2 | |
3759 | #define BUFTBL_ENTRY_OID_LBN 0 | |
3760 | #define BUFTBL_ENTRY_OID_WIDTH 16 | |
3761 | /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ | |
3762 | #define BUFTBL_ENTRY_PGSZ_OFST 2 | |
3763 | #define BUFTBL_ENTRY_PGSZ_LEN 2 | |
3764 | #define BUFTBL_ENTRY_PGSZ_LBN 16 | |
3765 | #define BUFTBL_ENTRY_PGSZ_WIDTH 16 | |
3766 | /* the raw 64-bit address field from the SMC, not adjusted for page size */ | |
3767 | #define BUFTBL_ENTRY_RAWADDR_OFST 4 | |
3768 | #define BUFTBL_ENTRY_RAWADDR_LEN 8 | |
3769 | #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 | |
3770 | #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 | |
3771 | #define BUFTBL_ENTRY_RAWADDR_LBN 32 | |
3772 | #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 | |
3773 | ||
3774 | /* NVRAM_PARTITION_TYPE structuredef */ | |
3775 | #define NVRAM_PARTITION_TYPE_LEN 2 | |
3776 | #define NVRAM_PARTITION_TYPE_ID_OFST 0 | |
3777 | #define NVRAM_PARTITION_TYPE_ID_LEN 2 | |
3778 | /* enum: Primary MC firmware partition */ | |
3779 | #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 | |
3780 | /* enum: Secondary MC firmware partition */ | |
3781 | #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 | |
3782 | /* enum: Expansion ROM partition */ | |
3783 | #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 | |
3784 | /* enum: Static configuration TLV partition */ | |
3785 | #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 | |
3786 | /* enum: Dynamic configuration TLV partition */ | |
3787 | #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 | |
3788 | /* enum: Expansion ROM configuration data for port 0 */ | |
3789 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 | |
3790 | /* enum: Expansion ROM configuration data for port 1 */ | |
3791 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 | |
3792 | /* enum: Expansion ROM configuration data for port 2 */ | |
3793 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 | |
3794 | /* enum: Expansion ROM configuration data for port 3 */ | |
3795 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 | |
3796 | /* enum: Non-volatile log output partition */ | |
3797 | #define NVRAM_PARTITION_TYPE_LOG 0x700 | |
3798 | /* enum: Device state dump output partition */ | |
3799 | #define NVRAM_PARTITION_TYPE_DUMP 0x800 | |
3800 | /* enum: Application license key storage partition */ | |
3801 | #define NVRAM_PARTITION_TYPE_LICENSE 0x900 | |
3802 | /* enum: Start of reserved value range (firmware may use for any purpose) */ | |
3803 | #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 | |
3804 | /* enum: End of reserved value range (firmware may use for any purpose) */ | |
3805 | #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd | |
3806 | /* enum: Recovery partition map (provided if real map is missing or corrupt) */ | |
3807 | #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe | |
3808 | /* enum: Partition map (real map as stored in flash) */ | |
3809 | #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff | |
3810 | #define NVRAM_PARTITION_TYPE_ID_LBN 0 | |
3811 | #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 | |
3812 | ||
3813 | ||
3814 | /***********************************/ | |
3815 | /* MC_CMD_READ_REGS | |
3816 | * Get a dump of the MCPU registers | |
3817 | */ | |
3818 | #define MC_CMD_READ_REGS 0x50 | |
3819 | ||
3820 | /* MC_CMD_READ_REGS_IN msgrequest */ | |
3821 | #define MC_CMD_READ_REGS_IN_LEN 0 | |
3822 | ||
3823 | /* MC_CMD_READ_REGS_OUT msgresponse */ | |
3824 | #define MC_CMD_READ_REGS_OUT_LEN 308 | |
3825 | /* Whether the corresponding register entry contains a valid value */ | |
3826 | #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 | |
3827 | #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 | |
3828 | /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, | |
3829 | * fir, fp) | |
3830 | */ | |
3831 | #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 | |
3832 | #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 | |
3833 | #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 | |
3834 | ||
3835 | ||
3836 | /***********************************/ | |
3837 | /* MC_CMD_INIT_EVQ | |
3838 | * Set up an event queue according to the supplied parameters. The IN arguments | |
3839 | * end with an address for each 4k of host memory required to back the EVQ. | |
3840 | */ | |
3841 | #define MC_CMD_INIT_EVQ 0x80 | |
3842 | ||
3843 | /* MC_CMD_INIT_EVQ_IN msgrequest */ | |
3844 | #define MC_CMD_INIT_EVQ_IN_LENMIN 44 | |
3845 | #define MC_CMD_INIT_EVQ_IN_LENMAX 548 | |
3846 | #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) | |
3847 | /* Size, in entries */ | |
3848 | #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 | |
3849 | /* Desired instance. Must be set to a specific instance, which is a function | |
3850 | * local queue index. | |
3851 | */ | |
3852 | #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 | |
3853 | /* The initial timer value. The load value is ignored if the timer mode is DIS. | |
3854 | */ | |
3855 | #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 | |
3856 | /* The reload value is ignored in one-shot modes */ | |
3857 | #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 | |
3858 | /* tbd */ | |
3859 | #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 | |
3860 | #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 | |
3861 | #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 | |
3862 | #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 | |
3863 | #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 | |
3864 | #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 | |
3865 | #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 | |
3866 | #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 | |
3867 | #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 | |
3868 | #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 | |
3869 | #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 | |
3870 | #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 | |
3871 | #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 | |
3872 | #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 | |
3873 | /* enum: Disabled */ | |
3874 | #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 | |
3875 | /* enum: Immediate */ | |
3876 | #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 | |
3877 | /* enum: Triggered */ | |
3878 | #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 | |
3879 | /* enum: Hold-off */ | |
3880 | #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 | |
3881 | /* Target EVQ for wakeups if in wakeup mode. */ | |
3882 | #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 | |
3883 | /* Target interrupt if in interrupting mode (note union with target EVQ). Use | |
3884 | * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test | |
3885 | * purposes. | |
3886 | */ | |
3887 | #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 | |
3888 | /* Event Counter Mode. */ | |
3889 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 | |
3890 | /* enum: Disabled */ | |
3891 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 | |
3892 | /* enum: Disabled */ | |
3893 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 | |
3894 | /* enum: Disabled */ | |
3895 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 | |
3896 | /* enum: Disabled */ | |
3897 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 | |
3898 | /* Event queue packet count threshold. */ | |
3899 | #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 | |
3900 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
3901 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 | |
3902 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 | |
3903 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 | |
3904 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 | |
3905 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 | |
3906 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 | |
3907 | ||
3908 | /* MC_CMD_INIT_EVQ_OUT msgresponse */ | |
3909 | #define MC_CMD_INIT_EVQ_OUT_LEN 4 | |
3910 | /* Only valid if INTRFLAG was true */ | |
3911 | #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 | |
3912 | ||
3913 | /* QUEUE_CRC_MODE structuredef */ | |
3914 | #define QUEUE_CRC_MODE_LEN 1 | |
3915 | #define QUEUE_CRC_MODE_MODE_LBN 0 | |
3916 | #define QUEUE_CRC_MODE_MODE_WIDTH 4 | |
3917 | /* enum: No CRC. */ | |
3918 | #define QUEUE_CRC_MODE_NONE 0x0 | |
3919 | /* enum: CRC Fiber channel over ethernet. */ | |
3920 | #define QUEUE_CRC_MODE_FCOE 0x1 | |
3921 | /* enum: CRC (digest) iSCSI header only. */ | |
3922 | #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 | |
3923 | /* enum: CRC (digest) iSCSI header and payload. */ | |
3924 | #define QUEUE_CRC_MODE_ISCSI 0x3 | |
3925 | /* enum: CRC Fiber channel over IP over ethernet. */ | |
3926 | #define QUEUE_CRC_MODE_FCOIPOE 0x4 | |
3927 | /* enum: CRC MPA. */ | |
3928 | #define QUEUE_CRC_MODE_MPA 0x5 | |
3929 | #define QUEUE_CRC_MODE_SPARE_LBN 4 | |
3930 | #define QUEUE_CRC_MODE_SPARE_WIDTH 4 | |
3931 | ||
3932 | ||
3933 | /***********************************/ | |
3934 | /* MC_CMD_INIT_RXQ | |
3935 | * set up a receive queue according to the supplied parameters. The IN | |
3936 | * arguments end with an address for each 4k of host memory required to back | |
3937 | * the RXQ. | |
3938 | */ | |
3939 | #define MC_CMD_INIT_RXQ 0x81 | |
3940 | ||
3941 | /* MC_CMD_INIT_RXQ_IN msgrequest */ | |
3942 | #define MC_CMD_INIT_RXQ_IN_LENMIN 36 | |
3943 | #define MC_CMD_INIT_RXQ_IN_LENMAX 252 | |
3944 | #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) | |
3945 | /* Size, in entries */ | |
3946 | #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 | |
3947 | /* The EVQ to send events to. This is an index originally specified to INIT_EVQ | |
3948 | */ | |
3949 | #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 | |
3950 | /* The value to put in the event data. Check hardware spec. for valid range. */ | |
3951 | #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 | |
3952 | /* Desired instance. Must be set to a specific instance, which is a function | |
3953 | * local queue index. | |
3954 | */ | |
3955 | #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 | |
3956 | /* There will be more flags here. */ | |
3957 | #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 | |
3958 | #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 | |
3959 | #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 | |
3960 | #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 | |
3961 | #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 | |
3962 | #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 | |
3963 | #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 | |
3964 | #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 | |
3965 | #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 | |
3966 | #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 | |
3967 | #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 | |
3968 | #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 | |
3969 | #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 | |
3970 | /* Owner ID to use if in buffer mode (zero if physical) */ | |
3971 | #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 | |
3972 | /* The port ID associated with the v-adaptor which should contain this DMAQ. */ | |
3973 | #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 | |
3974 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
3975 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 | |
3976 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 | |
3977 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 | |
3978 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 | |
3979 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 | |
3980 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 | |
3981 | ||
3982 | /* MC_CMD_INIT_RXQ_OUT msgresponse */ | |
3983 | #define MC_CMD_INIT_RXQ_OUT_LEN 0 | |
3984 | ||
3985 | ||
3986 | /***********************************/ | |
3987 | /* MC_CMD_INIT_TXQ | |
3988 | */ | |
3989 | #define MC_CMD_INIT_TXQ 0x82 | |
3990 | ||
3991 | /* MC_CMD_INIT_TXQ_IN msgrequest */ | |
3992 | #define MC_CMD_INIT_TXQ_IN_LENMIN 36 | |
3993 | #define MC_CMD_INIT_TXQ_IN_LENMAX 252 | |
3994 | #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) | |
3995 | /* Size, in entries */ | |
3996 | #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 | |
3997 | /* The EVQ to send events to. This is an index originally specified to | |
3998 | * INIT_EVQ. | |
3999 | */ | |
4000 | #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 | |
4001 | /* The value to put in the event data. Check hardware spec. for valid range. */ | |
4002 | #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 | |
4003 | /* Desired instance. Must be set to a specific instance, which is a function | |
4004 | * local queue index. | |
4005 | */ | |
4006 | #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 | |
4007 | /* There will be more flags here. */ | |
4008 | #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 | |
4009 | #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 | |
4010 | #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 | |
4011 | #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 | |
4012 | #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 | |
4013 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 | |
4014 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 | |
4015 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 | |
4016 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 | |
4017 | #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 | |
4018 | #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 | |
4019 | #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 | |
4020 | #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 | |
4021 | #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 | |
4022 | #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 | |
4023 | /* Owner ID to use if in buffer mode (zero if physical) */ | |
4024 | #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 | |
4025 | /* The port ID associated with the v-adaptor which should contain this DMAQ. */ | |
4026 | #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 | |
4027 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
4028 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 | |
4029 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 | |
4030 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 | |
4031 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 | |
4032 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 | |
4033 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 | |
4034 | ||
4035 | /* MC_CMD_INIT_TXQ_OUT msgresponse */ | |
4036 | #define MC_CMD_INIT_TXQ_OUT_LEN 0 | |
4037 | ||
4038 | ||
4039 | /***********************************/ | |
4040 | /* MC_CMD_FINI_EVQ | |
4041 | * Teardown an EVQ. | |
4042 | * | |
4043 | * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first | |
4044 | * or the operation will fail with EBUSY | |
4045 | */ | |
4046 | #define MC_CMD_FINI_EVQ 0x83 | |
4047 | ||
4048 | /* MC_CMD_FINI_EVQ_IN msgrequest */ | |
4049 | #define MC_CMD_FINI_EVQ_IN_LEN 4 | |
4050 | /* Instance of EVQ to destroy. Should be the same instance as that previously | |
4051 | * passed to INIT_EVQ | |
4052 | */ | |
4053 | #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 | |
4054 | ||
4055 | /* MC_CMD_FINI_EVQ_OUT msgresponse */ | |
4056 | #define MC_CMD_FINI_EVQ_OUT_LEN 0 | |
4057 | ||
4058 | ||
4059 | /***********************************/ | |
4060 | /* MC_CMD_FINI_RXQ | |
4061 | * Teardown a RXQ. | |
4062 | */ | |
4063 | #define MC_CMD_FINI_RXQ 0x84 | |
4064 | ||
4065 | /* MC_CMD_FINI_RXQ_IN msgrequest */ | |
4066 | #define MC_CMD_FINI_RXQ_IN_LEN 4 | |
4067 | /* Instance of RXQ to destroy */ | |
4068 | #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 | |
4069 | ||
4070 | /* MC_CMD_FINI_RXQ_OUT msgresponse */ | |
4071 | #define MC_CMD_FINI_RXQ_OUT_LEN 0 | |
4072 | ||
4073 | ||
4074 | /***********************************/ | |
4075 | /* MC_CMD_FINI_TXQ | |
4076 | * Teardown a TXQ. | |
4077 | */ | |
4078 | #define MC_CMD_FINI_TXQ 0x85 | |
4079 | ||
4080 | /* MC_CMD_FINI_TXQ_IN msgrequest */ | |
4081 | #define MC_CMD_FINI_TXQ_IN_LEN 4 | |
4082 | /* Instance of TXQ to destroy */ | |
4083 | #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 | |
4084 | ||
4085 | /* MC_CMD_FINI_TXQ_OUT msgresponse */ | |
4086 | #define MC_CMD_FINI_TXQ_OUT_LEN 0 | |
4087 | ||
4088 | ||
4089 | /***********************************/ | |
4090 | /* MC_CMD_DRIVER_EVENT | |
4091 | * Generate an event on an EVQ belonging to the function issuing the command. | |
4092 | */ | |
4093 | #define MC_CMD_DRIVER_EVENT 0x86 | |
4094 | ||
4095 | /* MC_CMD_DRIVER_EVENT_IN msgrequest */ | |
4096 | #define MC_CMD_DRIVER_EVENT_IN_LEN 12 | |
4097 | /* Handle of target EVQ */ | |
4098 | #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 | |
4099 | /* Bits 0 - 63 of event */ | |
4100 | #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 | |
4101 | #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 | |
4102 | #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 | |
4103 | #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 | |
4104 | ||
4105 | /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ | |
4106 | #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 | |
4107 | ||
4108 | ||
4109 | /***********************************/ | |
4110 | /* MC_CMD_PROXY_CMD | |
4111 | * Execute an arbitrary MCDI command on behalf of a different function, subject | |
4112 | * to security restrictions. The command to be proxied follows immediately | |
4113 | * afterward in the host buffer (or on the UART). This command supercedes | |
4114 | * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. | |
4115 | */ | |
4116 | #define MC_CMD_PROXY_CMD 0x5b | |
4117 | ||
4118 | /* MC_CMD_PROXY_CMD_IN msgrequest */ | |
4119 | #define MC_CMD_PROXY_CMD_IN_LEN 4 | |
4120 | /* The handle of the target function. */ | |
4121 | #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 | |
4122 | #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 | |
4123 | #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 | |
4124 | #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 | |
4125 | #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 | |
4126 | #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ | |
4127 | ||
4128 | ||
4129 | /***********************************/ | |
4130 | /* MC_CMD_ALLOC_BUFTBL_CHUNK | |
4131 | * Allocate a set of buffer table entries using the specified owner ID. This | |
4132 | * operation allocates the required buffer table entries (and fails if it | |
4133 | * cannot do so). The buffer table entries will initially be zeroed. | |
4134 | */ | |
4135 | #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 | |
4136 | ||
4137 | /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ | |
4138 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 | |
4139 | /* Owner ID to use */ | |
4140 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 | |
4141 | /* Size of buffer table pages to use, in bytes (note that only a few values are | |
4142 | * legal on any specific hardware). | |
4143 | */ | |
4144 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 | |
4145 | ||
4146 | /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ | |
4147 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 | |
4148 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 | |
4149 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 | |
4150 | /* Buffer table IDs for use in DMA descriptors. */ | |
4151 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 | |
4152 | ||
4153 | ||
4154 | /***********************************/ | |
4155 | /* MC_CMD_PROGRAM_BUFTBL_ENTRIES | |
4156 | * Reprogram a set of buffer table entries in the specified chunk. | |
4157 | */ | |
4158 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 | |
4159 | ||
4160 | /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ | |
4161 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 | |
4162 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 252 | |
4163 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) | |
4164 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 | |
4165 | /* ID */ | |
4166 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 | |
4167 | /* Num entries */ | |
4168 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 | |
4169 | /* Buffer table entry address */ | |
4170 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 | |
4171 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 | |
4172 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 | |
4173 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 | |
4174 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 | |
4175 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 30 | |
4176 | ||
4177 | /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ | |
4178 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 | |
4179 | ||
4180 | ||
4181 | /***********************************/ | |
4182 | /* MC_CMD_FREE_BUFTBL_CHUNK | |
4183 | */ | |
4184 | #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 | |
4185 | ||
4186 | /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ | |
4187 | #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 | |
4188 | #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 | |
4189 | ||
4190 | /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ | |
4191 | #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 | |
4192 | ||
4193 | ||
4194 | /***********************************/ | |
4195 | /* MC_CMD_FILTER_OP | |
4196 | * Multiplexed MCDI call for filter operations | |
4197 | */ | |
4198 | #define MC_CMD_FILTER_OP 0x8a | |
4199 | ||
4200 | /* MC_CMD_FILTER_OP_IN msgrequest */ | |
4201 | #define MC_CMD_FILTER_OP_IN_LEN 108 | |
4202 | /* identifies the type of operation requested */ | |
4203 | #define MC_CMD_FILTER_OP_IN_OP_OFST 0 | |
4204 | /* enum: single-recipient filter insert */ | |
4205 | #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 | |
4206 | /* enum: single-recipient filter remove */ | |
4207 | #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 | |
4208 | /* enum: multi-recipient filter subscribe */ | |
4209 | #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 | |
4210 | /* enum: multi-recipient filter unsubscribe */ | |
4211 | #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 | |
4212 | /* enum: replace one recipient with another (warning - the filter handle may | |
4213 | * change) | |
4214 | */ | |
4215 | #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 | |
4216 | /* filter handle (for remove / unsubscribe operations) */ | |
4217 | #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 | |
4218 | #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 | |
4219 | #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 | |
4220 | #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 | |
4221 | /* The port ID associated with the v-adaptor which should contain this filter. | |
4222 | */ | |
4223 | #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 | |
4224 | /* fields to include in match criteria */ | |
4225 | #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 | |
4226 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 | |
4227 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 | |
4228 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 | |
4229 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 | |
4230 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 | |
4231 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 | |
4232 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 | |
4233 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 | |
4234 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 | |
4235 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 | |
4236 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 | |
4237 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 | |
4238 | #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 | |
4239 | #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 | |
4240 | #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 | |
4241 | #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 | |
4242 | #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 | |
4243 | #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 | |
4244 | #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 | |
4245 | #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 | |
4246 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 | |
4247 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 | |
4248 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 | |
4249 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 | |
4250 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 | |
4251 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 | |
4252 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 | |
4253 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 | |
4254 | /* receive destination */ | |
4255 | #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 | |
4256 | /* enum: drop packets */ | |
4257 | #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 | |
4258 | /* enum: receive to host */ | |
4259 | #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 | |
4260 | /* enum: receive to MC */ | |
4261 | #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 | |
4262 | /* enum: loop back to port 0 TX MAC */ | |
4263 | #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 | |
4264 | /* enum: loop back to port 1 TX MAC */ | |
4265 | #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 | |
4266 | /* receive queue handle (for multiple queue modes, this is the base queue) */ | |
4267 | #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 | |
4268 | /* receive mode */ | |
4269 | #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 | |
4270 | /* enum: receive to just the specified queue */ | |
4271 | #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 | |
4272 | /* enum: receive to multiple queues using RSS context */ | |
4273 | #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 | |
4274 | /* enum: receive to multiple queues using .1p mapping */ | |
4275 | #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 | |
4276 | /* enum: install a filter entry that will never match; for test purposes only | |
4277 | */ | |
4278 | #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 | |
4279 | /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for | |
4280 | * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or | |
4281 | * MC_CMD_DOT1P_MAPPING_ALLOC. Note that these handles should be considered | |
4282 | * opaque to the host, although a value of 0xFFFFFFFF is guaranteed never to be | |
4283 | * a valid handle. | |
4284 | */ | |
4285 | #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 | |
4286 | /* transmit domain (reserved; set to 0) */ | |
4287 | #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 | |
4288 | /* transmit destination (either set the MAC and/or PM bits for explicit | |
4289 | * control, or set this field to TX_DEST_DEFAULT for sensible default | |
4290 | * behaviour) | |
4291 | */ | |
4292 | #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 | |
4293 | /* enum: request default behaviour (based on filter type) */ | |
4294 | #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff | |
4295 | #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 | |
4296 | #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 | |
4297 | #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 | |
4298 | #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 | |
4299 | /* source MAC address to match (as bytes in network order) */ | |
4300 | #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 | |
4301 | #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 | |
4302 | /* source port to match (as bytes in network order) */ | |
4303 | #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 | |
4304 | #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 | |
4305 | /* destination MAC address to match (as bytes in network order) */ | |
4306 | #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 | |
4307 | #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 | |
4308 | /* destination port to match (as bytes in network order) */ | |
4309 | #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 | |
4310 | #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 | |
4311 | /* Ethernet type to match (as bytes in network order) */ | |
4312 | #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 | |
4313 | #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 | |
4314 | /* Inner VLAN tag to match (as bytes in network order) */ | |
4315 | #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 | |
4316 | #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 | |
4317 | /* Outer VLAN tag to match (as bytes in network order) */ | |
4318 | #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 | |
4319 | #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 | |
4320 | /* IP protocol to match (in low byte; set high byte to 0) */ | |
4321 | #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 | |
4322 | #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 | |
4323 | /* Firmware defined register 0 to match (reserved; set to 0) */ | |
4324 | #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 | |
4325 | /* Firmware defined register 1 to match (reserved; set to 0) */ | |
4326 | #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 | |
4327 | /* source IP address to match (as bytes in network order; set last 12 bytes to | |
4328 | * 0 for IPv4 address) | |
4329 | */ | |
4330 | #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 | |
4331 | #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 | |
4332 | /* destination IP address to match (as bytes in network order; set last 12 | |
4333 | * bytes to 0 for IPv4 address) | |
4334 | */ | |
4335 | #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 | |
4336 | #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 | |
4337 | ||
4338 | /* MC_CMD_FILTER_OP_OUT msgresponse */ | |
4339 | #define MC_CMD_FILTER_OP_OUT_LEN 12 | |
4340 | /* identifies the type of operation requested */ | |
4341 | #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 | |
4342 | /* Enum values, see field(s): */ | |
4343 | /* MC_CMD_FILTER_OP_IN/OP */ | |
4344 | /* Returned filter handle (for insert / subscribe operations). Note that these | |
4345 | * handles should be considered opaque to the host, although a value of | |
4346 | * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. | |
4347 | */ | |
4348 | #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 | |
4349 | #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 | |
4350 | #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 | |
4351 | #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 | |
4352 | ||
4353 | ||
4354 | /***********************************/ | |
4355 | /* MC_CMD_GET_PARSER_DISP_INFO | |
4356 | * Get information related to the parser-dispatcher subsystem | |
4357 | */ | |
4358 | #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 | |
4359 | ||
4360 | /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ | |
4361 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 | |
4362 | /* identifies the type of operation requested */ | |
4363 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 | |
4364 | /* enum: read the list of supported RX filter matches */ | |
4365 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 | |
4366 | ||
4367 | /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ | |
4368 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 | |
4369 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 | |
4370 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) | |
4371 | /* identifies the type of operation requested */ | |
4372 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 | |
4373 | /* Enum values, see field(s): */ | |
4374 | /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ | |
4375 | /* number of supported match types */ | |
4376 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 | |
4377 | /* array of supported match types (valid MATCH_FIELDS values for | |
4378 | * MC_CMD_FILTER_OP) sorted in decreasing priority order | |
4379 | */ | |
4380 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 | |
4381 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 | |
4382 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 | |
4383 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 | |
4384 | ||
4385 | ||
4386 | /***********************************/ | |
4387 | /* MC_CMD_PARSER_DISP_RW | |
4388 | * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging | |
4389 | */ | |
4390 | #define MC_CMD_PARSER_DISP_RW 0xe5 | |
4391 | ||
4392 | /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ | |
4393 | #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 | |
4394 | /* identifies the target of the operation */ | |
4395 | #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 | |
4396 | /* enum: RX dispatcher CPU */ | |
4397 | #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 | |
4398 | /* enum: TX dispatcher CPU */ | |
4399 | #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 | |
4400 | /* enum: Lookup engine */ | |
4401 | #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 | |
4402 | /* identifies the type of operation requested */ | |
4403 | #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 | |
4404 | /* enum: read a word of DICPU DMEM or a LUE entry */ | |
4405 | #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 | |
4406 | /* enum: write a word of DICPU DMEM or a LUE entry */ | |
4407 | #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 | |
4408 | /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ | |
4409 | #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 | |
4410 | /* data memory address or LUE index */ | |
4411 | #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 | |
4412 | /* value to write (for DMEM writes) */ | |
4413 | #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 | |
4414 | /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ | |
4415 | #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 | |
4416 | /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ | |
4417 | #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 | |
4418 | /* value to write (for LUE writes) */ | |
4419 | #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 | |
4420 | #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 | |
4421 | ||
4422 | /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ | |
4423 | #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 | |
4424 | /* value read (for DMEM reads) */ | |
4425 | #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 | |
4426 | /* value read (for LUE reads) */ | |
4427 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 | |
4428 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 | |
4429 | /* up to 8 32-bit words of additional soft state from the LUE manager (the | |
4430 | * exact content is firmware-dependent and intended only for debug use) | |
4431 | */ | |
4432 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 | |
4433 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 | |
4434 | ||
4435 | ||
4436 | /***********************************/ | |
4437 | /* MC_CMD_GET_PF_COUNT | |
4438 | * Get number of PFs on the device. | |
4439 | */ | |
4440 | #define MC_CMD_GET_PF_COUNT 0xb6 | |
4441 | ||
4442 | /* MC_CMD_GET_PF_COUNT_IN msgrequest */ | |
4443 | #define MC_CMD_GET_PF_COUNT_IN_LEN 0 | |
4444 | ||
4445 | /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ | |
4446 | #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 | |
4447 | /* Identifies the number of PFs on the device. */ | |
4448 | #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 | |
4449 | #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 | |
4450 | ||
4451 | ||
4452 | /***********************************/ | |
4453 | /* MC_CMD_SET_PF_COUNT | |
4454 | * Set number of PFs on the device. | |
4455 | */ | |
4456 | #define MC_CMD_SET_PF_COUNT 0xb7 | |
4457 | ||
4458 | /* MC_CMD_SET_PF_COUNT_IN msgrequest */ | |
4459 | #define MC_CMD_SET_PF_COUNT_IN_LEN 4 | |
4460 | /* New number of PFs on the device. */ | |
4461 | #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 | |
4462 | ||
4463 | /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ | |
4464 | #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 | |
4465 | ||
4466 | ||
4467 | /***********************************/ | |
4468 | /* MC_CMD_GET_PORT_ASSIGNMENT | |
4469 | * Get port assignment for current PCI function. | |
4470 | */ | |
4471 | #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 | |
4472 | ||
4473 | /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ | |
4474 | #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 | |
4475 | ||
4476 | /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ | |
4477 | #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 | |
4478 | /* Identifies the port assignment for this function. */ | |
4479 | #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 | |
4480 | ||
4481 | ||
4482 | /***********************************/ | |
4483 | /* MC_CMD_SET_PORT_ASSIGNMENT | |
4484 | * Set port assignment for current PCI function. | |
4485 | */ | |
4486 | #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 | |
4487 | ||
4488 | /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ | |
4489 | #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 | |
4490 | /* Identifies the port assignment for this function. */ | |
4491 | #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 | |
4492 | ||
4493 | /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ | |
4494 | #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 | |
4495 | ||
4496 | ||
4497 | /***********************************/ | |
4498 | /* MC_CMD_ALLOC_VIS | |
4499 | * Allocate VIs for current PCI function. | |
4500 | */ | |
4501 | #define MC_CMD_ALLOC_VIS 0x8b | |
4502 | ||
4503 | /* MC_CMD_ALLOC_VIS_IN msgrequest */ | |
4504 | #define MC_CMD_ALLOC_VIS_IN_LEN 8 | |
4505 | /* The minimum number of VIs that is acceptable */ | |
4506 | #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 | |
4507 | /* The maximum number of VIs that would be useful */ | |
4508 | #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 | |
4509 | ||
4510 | /* MC_CMD_ALLOC_VIS_OUT msgresponse */ | |
4511 | #define MC_CMD_ALLOC_VIS_OUT_LEN 8 | |
4512 | /* The number of VIs allocated on this function */ | |
4513 | #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 | |
4514 | /* The base absolute VI number allocated to this function. Required to | |
4515 | * correctly interpret wakeup events. | |
4516 | */ | |
4517 | #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 | |
4518 | ||
4519 | ||
4520 | /***********************************/ | |
4521 | /* MC_CMD_FREE_VIS | |
4522 | * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, | |
4523 | * but not freed. | |
4524 | */ | |
4525 | #define MC_CMD_FREE_VIS 0x8c | |
4526 | ||
4527 | /* MC_CMD_FREE_VIS_IN msgrequest */ | |
4528 | #define MC_CMD_FREE_VIS_IN_LEN 0 | |
4529 | ||
4530 | /* MC_CMD_FREE_VIS_OUT msgresponse */ | |
4531 | #define MC_CMD_FREE_VIS_OUT_LEN 0 | |
4532 | ||
4533 | ||
4534 | /***********************************/ | |
4535 | /* MC_CMD_GET_SRIOV_CFG | |
4536 | * Get SRIOV config for this PF. | |
4537 | */ | |
4538 | #define MC_CMD_GET_SRIOV_CFG 0xba | |
4539 | ||
4540 | /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ | |
4541 | #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 | |
4542 | ||
4543 | /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ | |
4544 | #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 | |
4545 | /* Number of VFs currently enabled. */ | |
4546 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 | |
4547 | /* Max number of VFs before sriov stride and offset may need to be changed. */ | |
4548 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 | |
4549 | #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 | |
4550 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 | |
4551 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 | |
4552 | /* RID offset of first VF from PF. */ | |
4553 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 | |
4554 | /* RID offset of each subsequent VF from the previous. */ | |
4555 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 | |
4556 | ||
4557 | ||
4558 | /***********************************/ | |
4559 | /* MC_CMD_SET_SRIOV_CFG | |
4560 | * Set SRIOV config for this PF. | |
4561 | */ | |
4562 | #define MC_CMD_SET_SRIOV_CFG 0xbb | |
4563 | ||
4564 | /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ | |
4565 | #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 | |
4566 | /* Number of VFs currently enabled. */ | |
4567 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 | |
4568 | /* Max number of VFs before sriov stride and offset may need to be changed. */ | |
4569 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 | |
4570 | #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 | |
4571 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 | |
4572 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 | |
4573 | /* RID offset of first VF from PF, or 0 for no change, or | |
4574 | * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. | |
4575 | */ | |
4576 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 | |
4577 | /* RID offset of each subsequent VF from the previous, 0 for no change, or | |
4578 | * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. | |
4579 | */ | |
4580 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 | |
4581 | ||
4582 | /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ | |
4583 | #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 | |
4584 | ||
4585 | ||
4586 | /***********************************/ | |
4587 | /* MC_CMD_GET_VI_ALLOC_INFO | |
4588 | * Get information about number of VI's and base VI number allocated to this | |
4589 | * function. | |
4590 | */ | |
4591 | #define MC_CMD_GET_VI_ALLOC_INFO 0x8d | |
4592 | ||
4593 | /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ | |
4594 | #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 | |
4595 | ||
4596 | /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ | |
4597 | #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 8 | |
4598 | /* The number of VIs allocated on this function */ | |
4599 | #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 | |
4600 | /* The base absolute VI number allocated to this function. Required to | |
4601 | * correctly interpret wakeup events. | |
4602 | */ | |
4603 | #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 | |
4604 | ||
4605 | ||
4606 | /***********************************/ | |
4607 | /* MC_CMD_DUMP_VI_STATE | |
4608 | * For CmdClient use. Dump pertinent information on a specific absolute VI. | |
4609 | */ | |
4610 | #define MC_CMD_DUMP_VI_STATE 0x8e | |
4611 | ||
4612 | /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ | |
4613 | #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 | |
4614 | /* The VI number to query. */ | |
4615 | #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 | |
4616 | ||
4617 | /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ | |
4618 | #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 | |
4619 | /* The PF part of the function owning this VI. */ | |
4620 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 | |
4621 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 | |
4622 | /* The VF part of the function owning this VI. */ | |
4623 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 | |
4624 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 | |
4625 | /* Base of VIs allocated to this function. */ | |
4626 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 | |
4627 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 | |
4628 | /* Count of VIs allocated to the owner function. */ | |
4629 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 | |
4630 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 | |
4631 | /* Base interrupt vector allocated to this function. */ | |
4632 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 | |
4633 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 | |
4634 | /* Number of interrupt vectors allocated to this function. */ | |
4635 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 | |
4636 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 | |
4637 | /* Raw evq ptr table data. */ | |
4638 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 | |
4639 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 | |
4640 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 | |
4641 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 | |
4642 | /* Raw evq timer table data. */ | |
4643 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 | |
4644 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 | |
4645 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 | |
4646 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 | |
4647 | /* Combined metadata field. */ | |
4648 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 | |
4649 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 | |
4650 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 | |
4651 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 | |
4652 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 | |
4653 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 | |
4654 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 | |
4655 | /* TXDPCPU raw table data for queue. */ | |
4656 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 | |
4657 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 | |
4658 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 | |
4659 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 | |
4660 | /* TXDPCPU raw table data for queue. */ | |
4661 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 | |
4662 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 | |
4663 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 | |
4664 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 | |
4665 | /* TXDPCPU raw table data for queue. */ | |
4666 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 | |
4667 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 | |
4668 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 | |
4669 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 | |
4670 | /* Combined metadata field. */ | |
4671 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 | |
4672 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 | |
4673 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 | |
4674 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 | |
4675 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 | |
4676 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 | |
4677 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 | |
4678 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 | |
4679 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 | |
4680 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 | |
4681 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 | |
4682 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 | |
4683 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 | |
4684 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 | |
4685 | /* RXDPCPU raw table data for queue. */ | |
4686 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 | |
4687 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 | |
4688 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 | |
4689 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 | |
4690 | /* RXDPCPU raw table data for queue. */ | |
4691 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 | |
4692 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 | |
4693 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 | |
4694 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 | |
4695 | /* Reserved, currently 0. */ | |
4696 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 | |
4697 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 | |
4698 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 | |
4699 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 | |
4700 | /* Combined metadata field. */ | |
4701 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 | |
4702 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 | |
4703 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 | |
4704 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 | |
4705 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 | |
4706 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 | |
4707 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 | |
4708 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 | |
4709 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 | |
4710 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 | |
4711 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 | |
4712 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 | |
4713 | ||
4714 | ||
4715 | /***********************************/ | |
4716 | /* MC_CMD_ALLOC_PIOBUF | |
4717 | * Allocate a push I/O buffer for later use with a tx queue. | |
4718 | */ | |
4719 | #define MC_CMD_ALLOC_PIOBUF 0x8f | |
4720 | ||
4721 | /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ | |
4722 | #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 | |
4723 | ||
4724 | /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ | |
4725 | #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 | |
4726 | /* Handle for allocated push I/O buffer. */ | |
4727 | #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 | |
4728 | ||
4729 | ||
4730 | /***********************************/ | |
4731 | /* MC_CMD_FREE_PIOBUF | |
4732 | * Free a push I/O buffer. | |
4733 | */ | |
4734 | #define MC_CMD_FREE_PIOBUF 0x90 | |
4735 | ||
4736 | /* MC_CMD_FREE_PIOBUF_IN msgrequest */ | |
4737 | #define MC_CMD_FREE_PIOBUF_IN_LEN 4 | |
4738 | /* Handle for allocated push I/O buffer. */ | |
4739 | #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 | |
4740 | ||
4741 | /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ | |
4742 | #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 | |
4743 | ||
4744 | ||
4745 | /***********************************/ | |
4746 | /* MC_CMD_GET_VI_TLP_PROCESSING | |
4747 | * Get TLP steering and ordering information for a VI. | |
4748 | */ | |
4749 | #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 | |
4750 | ||
4751 | /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ | |
4752 | #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 | |
4753 | /* VI number to get information for. */ | |
4754 | #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 | |
4755 | ||
4756 | /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ | |
4757 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 | |
4758 | /* Transaction processing steering hint 1 for use with the Rx Queue. */ | |
4759 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 | |
4760 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 | |
4761 | /* Transaction processing steering hint 2 for use with the Ev Queue. */ | |
4762 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 | |
4763 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 | |
4764 | /* Use Relaxed ordering model for TLPs on this VI. */ | |
4765 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 | |
4766 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 | |
4767 | /* Use ID based ordering for TLPs on this VI. */ | |
4768 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 | |
4769 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 | |
4770 | /* Set no snoop bit for TLPs on this VI. */ | |
4771 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 | |
4772 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 | |
4773 | /* Enable TPH for TLPs on this VI. */ | |
4774 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 | |
4775 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 | |
4776 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 | |
4777 | ||
4778 | ||
4779 | /***********************************/ | |
4780 | /* MC_CMD_SET_VI_TLP_PROCESSING | |
4781 | * Set TLP steering and ordering information for a VI. | |
4782 | */ | |
4783 | #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 | |
4784 | ||
4785 | /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ | |
4786 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 | |
4787 | /* VI number to set information for. */ | |
4788 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 | |
4789 | /* Transaction processing steering hint 1 for use with the Rx Queue. */ | |
4790 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 | |
4791 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 | |
4792 | /* Transaction processing steering hint 2 for use with the Ev Queue. */ | |
4793 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 | |
4794 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 | |
4795 | /* Use Relaxed ordering model for TLPs on this VI. */ | |
4796 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 | |
4797 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 | |
4798 | /* Use ID based ordering for TLPs on this VI. */ | |
4799 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 | |
4800 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 | |
4801 | /* Set the no snoop bit for TLPs on this VI. */ | |
4802 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 | |
4803 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 | |
4804 | /* Enable TPH for TLPs on this VI. */ | |
4805 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 | |
4806 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 | |
4807 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 | |
4808 | ||
4809 | /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ | |
4810 | #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 | |
4811 | ||
4812 | ||
4813 | /***********************************/ | |
4814 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS | |
4815 | * Get global PCIe steering and transaction processing configuration. | |
4816 | */ | |
4817 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc | |
4818 | ||
4819 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ | |
4820 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 | |
4821 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 | |
4822 | /* enum: MISC. */ | |
4823 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 | |
4824 | /* enum: IDO. */ | |
4825 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 | |
4826 | /* enum: RO. */ | |
4827 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 | |
4828 | /* enum: TPH Type. */ | |
4829 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 | |
4830 | ||
4831 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ | |
4832 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 | |
4833 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 | |
4834 | /* Enum values, see field(s): */ | |
4835 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ | |
4836 | /* Amalgamated TLP info word. */ | |
4837 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 | |
4838 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 | |
4839 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 | |
4840 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 | |
4841 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 | |
4842 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 | |
4843 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 | |
4844 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 | |
4845 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 | |
4846 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 | |
4847 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 | |
4848 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 | |
4849 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 | |
4850 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 | |
4851 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 | |
4852 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 | |
4853 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 | |
4854 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 | |
4855 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 | |
4856 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 | |
4857 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 | |
4858 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 | |
4859 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 | |
4860 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 | |
4861 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 | |
4862 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 | |
4863 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 | |
4864 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 | |
4865 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 | |
4866 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 | |
4867 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 | |
4868 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 | |
4869 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 | |
4870 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 | |
4871 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 | |
4872 | ||
4873 | ||
4874 | /***********************************/ | |
4875 | /* MC_CMD_SET_TLP_PROCESSING_GLOBALS | |
4876 | * Set global PCIe steering and transaction processing configuration. | |
4877 | */ | |
4878 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd | |
4879 | ||
4880 | /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ | |
4881 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 | |
4882 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 | |
4883 | /* Enum values, see field(s): */ | |
4884 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ | |
4885 | /* Amalgamated TLP info word. */ | |
4886 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 | |
4887 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 | |
4888 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 | |
4889 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 | |
4890 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 | |
4891 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 | |
4892 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 | |
4893 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 | |
4894 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 | |
4895 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 | |
4896 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 | |
4897 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 | |
4898 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 | |
4899 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 | |
4900 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 | |
4901 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 | |
4902 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 | |
4903 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 | |
4904 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 | |
4905 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 | |
4906 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 | |
4907 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 | |
4908 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 | |
4909 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 | |
4910 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 | |
4911 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 | |
4912 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 | |
4913 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 | |
4914 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 | |
4915 | ||
4916 | /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ | |
4917 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 | |
4918 | ||
4919 | ||
4920 | /***********************************/ | |
4921 | /* MC_CMD_SATELLITE_DOWNLOAD | |
4922 | * Download a new set of images to the satellite CPUs from the host. | |
4923 | */ | |
4924 | #define MC_CMD_SATELLITE_DOWNLOAD 0x91 | |
4925 | ||
4926 | /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs | |
4927 | * are subtle, and so downloads must proceed in a number of phases. | |
4928 | * | |
4929 | * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. | |
4930 | * | |
4931 | * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download | |
4932 | * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should | |
4933 | * be a checksum (a simple 32-bit sum) of the transferred data. An individual | |
4934 | * download may be aborted using CHUNK_ID_ABORT. | |
4935 | * | |
4936 | * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), | |
4937 | * similar to PHASE_IMEMS. | |
4938 | * | |
4939 | * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. | |
4940 | * | |
4941 | * After any error (a requested abort is not considered to be an error) the | |
4942 | * sequence must be restarted from PHASE_RESET. | |
4943 | */ | |
4944 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 | |
4945 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 | |
4946 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) | |
4947 | /* Download phase. (Note: the IDLE phase is used internally and is never valid | |
4948 | * in a command from the host.) | |
4949 | */ | |
4950 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 | |
4951 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ | |
4952 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ | |
4953 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ | |
4954 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ | |
4955 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ | |
4956 | /* Target for download. (These match the blob numbers defined in | |
4957 | * mc_flash_layout.h.) | |
4958 | */ | |
4959 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 | |
4960 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4961 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 | |
4962 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4963 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 | |
4964 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4965 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 | |
4966 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4967 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 | |
4968 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4969 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 | |
4970 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4971 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 | |
4972 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4973 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 | |
4974 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4975 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 | |
4976 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4977 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 | |
4978 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4979 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 | |
4980 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4981 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa | |
4982 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
4983 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb | |
4984 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
4985 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc | |
4986 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
4987 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd | |
4988 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
4989 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe | |
4990 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
4991 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf | |
4992 | /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ | |
4993 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff | |
4994 | /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ | |
4995 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 | |
4996 | /* enum: Last chunk, containing checksum rather than data */ | |
4997 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff | |
4998 | /* enum: Abort download of this item */ | |
4999 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe | |
5000 | /* Length of this chunk in bytes */ | |
5001 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 | |
5002 | /* Data for this chunk */ | |
5003 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 | |
5004 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 | |
5005 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 | |
5006 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 | |
5007 | ||
5008 | /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ | |
5009 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 | |
5010 | /* Same as MC_CMD_ERR field, but included as 0 in success cases */ | |
5011 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 | |
5012 | /* Extra status information */ | |
5013 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 | |
5014 | /* enum: Code download OK, completed. */ | |
5015 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 | |
5016 | /* enum: Code download aborted as requested. */ | |
5017 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 | |
5018 | /* enum: Code download OK so far, send next chunk. */ | |
5019 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 | |
5020 | /* enum: Download phases out of sequence */ | |
5021 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 | |
5022 | /* enum: Bad target for this phase */ | |
5023 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 | |
5024 | /* enum: Chunk ID out of sequence */ | |
5025 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 | |
5026 | /* enum: Chunk length zero or too large */ | |
5027 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 | |
5028 | /* enum: Checksum was incorrect */ | |
5029 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 | |
5030 | ||
5031 | ||
5032 | /***********************************/ | |
5033 | /* MC_CMD_GET_CAPABILITIES | |
5034 | * Get device capabilities. | |
5035 | * | |
5036 | * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to | |
5037 | * reference inherent device capabilities as opposed to current NVRAM config. | |
5038 | */ | |
5039 | #define MC_CMD_GET_CAPABILITIES 0xbe | |
5040 | ||
5041 | /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ | |
5042 | #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 | |
5043 | ||
5044 | /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ | |
5045 | #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 | |
5046 | /* First word of flags. */ | |
5047 | #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 | |
5048 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 | |
5049 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 | |
5050 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 | |
5051 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 | |
5052 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 | |
5053 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 | |
5054 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 | |
5055 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 | |
5056 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 | |
5057 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 | |
5058 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 | |
5059 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 | |
5060 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 | |
5061 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 | |
5062 | #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 | |
5063 | #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 | |
5064 | /* RxDPCPU firmware id. */ | |
5065 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 | |
5066 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 | |
5067 | /* enum: Standard RXDP firmware */ | |
5068 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 | |
5069 | /* enum: Low latency RXDP firmware */ | |
5070 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 | |
5071 | /* enum: RXDP Test firmware image 1 */ | |
5072 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 | |
5073 | /* enum: RXDP Test firmware image 2 */ | |
5074 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 | |
5075 | /* enum: RXDP Test firmware image 3 */ | |
5076 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 | |
5077 | /* enum: RXDP Test firmware image 4 */ | |
5078 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 | |
5079 | /* enum: RXDP Test firmware image 5 */ | |
5080 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 | |
5081 | /* enum: RXDP Test firmware image 6 */ | |
5082 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 | |
5083 | /* enum: RXDP Test firmware image 7 */ | |
5084 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 | |
5085 | /* enum: RXDP Test firmware image 8 */ | |
5086 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 | |
5087 | /* TxDPCPU firmware id. */ | |
5088 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 | |
5089 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 | |
5090 | /* enum: Standard TXDP firmware */ | |
5091 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 | |
5092 | /* enum: Low latency TXDP firmware */ | |
5093 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 | |
5094 | /* enum: TXDP Test firmware image 1 */ | |
5095 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 | |
5096 | /* enum: TXDP Test firmware image 2 */ | |
5097 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 | |
5098 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 | |
5099 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 | |
5100 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 | |
5101 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 | |
5102 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 | |
5103 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 | |
5104 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */ | |
5105 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */ | |
5106 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 /* enum */ | |
5107 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */ | |
5108 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ | |
5109 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 | |
5110 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 | |
5111 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 | |
5112 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 | |
5113 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 | |
5114 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 | |
5115 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */ | |
5116 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */ | |
5117 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 /* enum */ | |
5118 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */ | |
5119 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ | |
5120 | /* Hardware capabilities of NIC */ | |
5121 | #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 | |
5122 | /* Licensed capabilities */ | |
5123 | #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 | |
5124 | ||
5125 | ||
5126 | /***********************************/ | |
5127 | /* MC_CMD_V2_EXTN | |
5128 | * Encapsulation for a v2 extended command | |
5129 | */ | |
5130 | #define MC_CMD_V2_EXTN 0x7f | |
5131 | ||
5132 | /* MC_CMD_V2_EXTN_IN msgrequest */ | |
5133 | #define MC_CMD_V2_EXTN_IN_LEN 4 | |
5134 | /* the extended command number */ | |
5135 | #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 | |
5136 | #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 | |
5137 | #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 | |
5138 | #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 | |
5139 | /* the actual length of the encapsulated command (which is not in the v1 | |
5140 | * header) | |
5141 | */ | |
5142 | #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 | |
5143 | #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 | |
5144 | #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 | |
5145 | #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 | |
5146 | ||
5147 | ||
5148 | /***********************************/ | |
5149 | /* MC_CMD_TCM_BUCKET_ALLOC | |
5150 | * Allocate a pacer bucket (for qau rp or a snapper test) | |
5151 | */ | |
5152 | #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 | |
5153 | ||
5154 | /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ | |
5155 | #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 | |
5156 | ||
5157 | /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ | |
5158 | #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 | |
5159 | /* the bucket id */ | |
5160 | #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 | |
5161 | ||
5162 | ||
5163 | /***********************************/ | |
5164 | /* MC_CMD_TCM_BUCKET_FREE | |
5165 | * Free a pacer bucket | |
5166 | */ | |
5167 | #define MC_CMD_TCM_BUCKET_FREE 0xb3 | |
5168 | ||
5169 | /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ | |
5170 | #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 | |
5171 | /* the bucket id */ | |
5172 | #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 | |
5173 | ||
5174 | /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ | |
5175 | #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 | |
5176 | ||
5177 | ||
5178 | /***********************************/ | |
5179 | /* MC_CMD_TCM_BUCKET_INIT | |
5180 | * Initialise pacer bucket with a given rate | |
5181 | */ | |
5182 | #define MC_CMD_TCM_BUCKET_INIT 0xb4 | |
5183 | ||
5184 | /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ | |
5185 | #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 | |
5186 | /* the bucket id */ | |
5187 | #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 | |
5188 | /* the rate in mbps */ | |
5189 | #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 | |
5190 | ||
5191 | /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ | |
5192 | #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 | |
5193 | ||
5194 | ||
5195 | /***********************************/ | |
5196 | /* MC_CMD_TCM_TXQ_INIT | |
5197 | * Initialise txq in pacer with given options or set options | |
5198 | */ | |
5199 | #define MC_CMD_TCM_TXQ_INIT 0xb5 | |
5200 | ||
5201 | /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ | |
5202 | #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 | |
5203 | /* the txq id */ | |
5204 | #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 | |
5205 | /* the static priority associated with the txq */ | |
5206 | #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 | |
5207 | /* bitmask of the priority queues this txq is inserted into */ | |
5208 | #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 | |
5209 | /* the reaction point (RP) bucket */ | |
5210 | #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 | |
5211 | /* an already reserved bucket (typically set to bucket associated with outer | |
5212 | * vswitch) | |
5213 | */ | |
5214 | #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 | |
5215 | /* an already reserved bucket (typically set to bucket associated with inner | |
5216 | * vswitch) | |
5217 | */ | |
5218 | #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 | |
5219 | /* the min bucket (typically for ETS/minimum bandwidth) */ | |
5220 | #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 | |
5221 | ||
5222 | /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ | |
5223 | #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 | |
5224 | ||
5225 | ||
5226 | /***********************************/ | |
5227 | /* MC_CMD_LINK_PIOBUF | |
5228 | * Link a push I/O buffer to a TxQ | |
5229 | */ | |
5230 | #define MC_CMD_LINK_PIOBUF 0x92 | |
5231 | ||
5232 | /* MC_CMD_LINK_PIOBUF_IN msgrequest */ | |
5233 | #define MC_CMD_LINK_PIOBUF_IN_LEN 8 | |
5234 | /* Handle for allocated push I/O buffer. */ | |
5235 | #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 | |
5236 | /* Function Local Instance (VI) number. */ | |
5237 | #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 | |
5238 | ||
5239 | /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ | |
5240 | #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 | |
5241 | ||
5242 | ||
5243 | /***********************************/ | |
5244 | /* MC_CMD_UNLINK_PIOBUF | |
5245 | * Unlink a push I/O buffer from a TxQ | |
5246 | */ | |
5247 | #define MC_CMD_UNLINK_PIOBUF 0x93 | |
5248 | ||
5249 | /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ | |
5250 | #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 | |
5251 | /* Function Local Instance (VI) number. */ | |
5252 | #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 | |
5253 | ||
5254 | /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ | |
5255 | #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 | |
5256 | ||
5257 | ||
5258 | /***********************************/ | |
5259 | /* MC_CMD_VSWITCH_ALLOC | |
5260 | * allocate and initialise a v-switch. | |
5261 | */ | |
5262 | #define MC_CMD_VSWITCH_ALLOC 0x94 | |
5263 | ||
5264 | /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ | |
5265 | #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 | |
5266 | /* The port to connect to the v-switch's upstream port. */ | |
5267 | #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5268 | /* The type of v-switch to create. */ | |
5269 | #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 | |
5270 | /* enum: VLAN */ | |
5271 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 | |
5272 | /* enum: VEB */ | |
5273 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 | |
5274 | /* enum: VEPA */ | |
5275 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 | |
5276 | /* Flags controlling v-port creation */ | |
5277 | #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 | |
5278 | #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 | |
5279 | #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 | |
5280 | /* The number of VLAN tags to support. */ | |
5281 | #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 | |
5282 | ||
5283 | /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ | |
5284 | #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 | |
5285 | ||
5286 | ||
5287 | /***********************************/ | |
5288 | /* MC_CMD_VSWITCH_FREE | |
5289 | * de-allocate a v-switch. | |
5290 | */ | |
5291 | #define MC_CMD_VSWITCH_FREE 0x95 | |
5292 | ||
5293 | /* MC_CMD_VSWITCH_FREE_IN msgrequest */ | |
5294 | #define MC_CMD_VSWITCH_FREE_IN_LEN 4 | |
5295 | /* The port to which the v-switch is connected. */ | |
5296 | #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 | |
5297 | ||
5298 | /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ | |
5299 | #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 | |
5300 | ||
5301 | ||
5302 | /***********************************/ | |
5303 | /* MC_CMD_VPORT_ALLOC | |
5304 | * allocate a v-port. | |
5305 | */ | |
5306 | #define MC_CMD_VPORT_ALLOC 0x96 | |
5307 | ||
5308 | /* MC_CMD_VPORT_ALLOC_IN msgrequest */ | |
5309 | #define MC_CMD_VPORT_ALLOC_IN_LEN 20 | |
5310 | /* The port to which the v-switch is connected. */ | |
5311 | #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5312 | /* The type of the new v-port. */ | |
5313 | #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 | |
5314 | /* enum: VLAN (obsolete) */ | |
5315 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 | |
5316 | /* enum: VEB (obsolete) */ | |
5317 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 | |
5318 | /* enum: VEPA (obsolete) */ | |
5319 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 | |
5320 | /* enum: A normal v-port receives packets which match a specified MAC and/or | |
5321 | * VLAN. | |
5322 | */ | |
5323 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 | |
5324 | /* enum: An expansion v-port packets traffic which don't match any other | |
5325 | * v-port. | |
5326 | */ | |
5327 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 | |
5328 | /* enum: An test v-port receives packets which match any filters installed by | |
5329 | * its downstream components. | |
5330 | */ | |
5331 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 | |
5332 | /* Flags controlling v-port creation */ | |
5333 | #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 | |
5334 | #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 | |
5335 | #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 | |
5336 | /* The number of VLAN tags to insert/remove. */ | |
5337 | #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 | |
5338 | /* The actual VLAN tags to insert/remove */ | |
5339 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 | |
5340 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 | |
5341 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 | |
5342 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 | |
5343 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 | |
5344 | ||
5345 | /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ | |
5346 | #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 | |
5347 | /* The handle of the new v-port */ | |
5348 | #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 | |
5349 | ||
5350 | ||
5351 | /***********************************/ | |
5352 | /* MC_CMD_VPORT_FREE | |
5353 | * de-allocate a v-port. | |
5354 | */ | |
5355 | #define MC_CMD_VPORT_FREE 0x97 | |
5356 | ||
5357 | /* MC_CMD_VPORT_FREE_IN msgrequest */ | |
5358 | #define MC_CMD_VPORT_FREE_IN_LEN 4 | |
5359 | /* The handle of the v-port */ | |
5360 | #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 | |
5361 | ||
5362 | /* MC_CMD_VPORT_FREE_OUT msgresponse */ | |
5363 | #define MC_CMD_VPORT_FREE_OUT_LEN 0 | |
5364 | ||
5365 | ||
5366 | /***********************************/ | |
5367 | /* MC_CMD_VADAPTOR_ALLOC | |
5368 | * allocate a v-adaptor. | |
5369 | */ | |
5370 | #define MC_CMD_VADAPTOR_ALLOC 0x98 | |
5371 | ||
5372 | /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ | |
5373 | #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 16 | |
5374 | /* The port to connect to the v-adaptor's port. */ | |
5375 | #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5376 | /* Flags controlling v-adaptor creation */ | |
5377 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 | |
5378 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 | |
5379 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 | |
5380 | /* The number of VLAN tags to strip on receive */ | |
5381 | #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 | |
5382 | ||
5383 | /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ | |
5384 | #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 | |
5385 | ||
5386 | ||
5387 | /***********************************/ | |
5388 | /* MC_CMD_VADAPTOR_FREE | |
5389 | * de-allocate a v-adaptor. | |
5390 | */ | |
5391 | #define MC_CMD_VADAPTOR_FREE 0x99 | |
5392 | ||
5393 | /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ | |
5394 | #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 | |
5395 | /* The port to which the v-adaptor is connected. */ | |
5396 | #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 | |
5397 | ||
5398 | /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ | |
5399 | #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 | |
5400 | ||
5401 | ||
5402 | /***********************************/ | |
5403 | /* MC_CMD_EVB_PORT_ASSIGN | |
5404 | * assign a port to a PCI function. | |
5405 | */ | |
5406 | #define MC_CMD_EVB_PORT_ASSIGN 0x9a | |
5407 | ||
5408 | /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ | |
5409 | #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 | |
5410 | /* The port to assign. */ | |
5411 | #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 | |
5412 | /* The target function to modify. */ | |
5413 | #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 | |
5414 | #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 | |
5415 | #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 | |
5416 | #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 | |
5417 | #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 | |
5418 | ||
5419 | /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ | |
5420 | #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 | |
5421 | ||
5422 | ||
5423 | /***********************************/ | |
5424 | /* MC_CMD_RDWR_A64_REGIONS | |
5425 | * Assign the 64 bit region addresses. | |
5426 | */ | |
5427 | #define MC_CMD_RDWR_A64_REGIONS 0x9b | |
5428 | ||
5429 | /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ | |
5430 | #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 | |
5431 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 | |
5432 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 | |
5433 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 | |
5434 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 | |
5435 | /* Write enable bits 0-3, set to write, clear to read. */ | |
5436 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 | |
5437 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 | |
5438 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 | |
5439 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 | |
5440 | ||
5441 | /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included | |
5442 | * regardless of state of write bits in the request. | |
5443 | */ | |
5444 | #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 | |
5445 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 | |
5446 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 | |
5447 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 | |
5448 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 | |
5449 | ||
5450 | ||
5451 | /***********************************/ | |
5452 | /* MC_CMD_ONLOAD_STACK_ALLOC | |
5453 | * Allocate an Onload stack ID. | |
5454 | */ | |
5455 | #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c | |
5456 | ||
5457 | /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ | |
5458 | #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 | |
5459 | /* The handle of the owning upstream port */ | |
5460 | #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5461 | ||
5462 | /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ | |
5463 | #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 | |
5464 | /* The handle of the new Onload stack */ | |
5465 | #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 | |
5466 | ||
5467 | ||
5468 | /***********************************/ | |
5469 | /* MC_CMD_ONLOAD_STACK_FREE | |
5470 | * Free an Onload stack ID. | |
5471 | */ | |
5472 | #define MC_CMD_ONLOAD_STACK_FREE 0x9d | |
5473 | ||
5474 | /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ | |
5475 | #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 | |
5476 | /* The handle of the Onload stack */ | |
5477 | #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 | |
5478 | ||
5479 | /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ | |
5480 | #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 | |
5481 | ||
5482 | ||
5483 | /***********************************/ | |
5484 | /* MC_CMD_RSS_CONTEXT_ALLOC | |
5485 | * Allocate an RSS context. | |
5486 | */ | |
5487 | #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e | |
5488 | ||
5489 | /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ | |
5490 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 | |
5491 | /* The handle of the owning upstream port */ | |
5492 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5493 | /* The type of context to allocate */ | |
5494 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 | |
5495 | /* enum: Allocate a context for exclusive use. The key and indirection table | |
5496 | * must be explicitly configured. | |
5497 | */ | |
5498 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 | |
5499 | /* enum: Allocate a context for shared use; this will spread across a range of | |
5500 | * queues, but the key and indirection table are pre-configured and may not be | |
5501 | * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. | |
5502 | */ | |
5503 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 | |
5504 | /* Number of queues spanned by this context, in the range 1-64; valid offsets | |
5505 | * in the indirection table will be in the range 0 to NUM_QUEUES-1. | |
5506 | */ | |
5507 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 | |
5508 | ||
5509 | /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ | |
5510 | #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 | |
5511 | /* The handle of the new RSS context */ | |
5512 | #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 | |
5513 | ||
5514 | ||
5515 | /***********************************/ | |
5516 | /* MC_CMD_RSS_CONTEXT_FREE | |
5517 | * Free an RSS context. | |
5518 | */ | |
5519 | #define MC_CMD_RSS_CONTEXT_FREE 0x9f | |
5520 | ||
5521 | /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ | |
5522 | #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 | |
5523 | /* The handle of the RSS context */ | |
5524 | #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 | |
5525 | ||
5526 | /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ | |
5527 | #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 | |
5528 | ||
5529 | ||
5530 | /***********************************/ | |
5531 | /* MC_CMD_RSS_CONTEXT_SET_KEY | |
5532 | * Set the Toeplitz hash key for an RSS context. | |
5533 | */ | |
5534 | #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 | |
5535 | ||
5536 | /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ | |
5537 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 | |
5538 | /* The handle of the RSS context */ | |
5539 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 | |
5540 | /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ | |
5541 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 | |
5542 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 | |
5543 | ||
5544 | /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ | |
5545 | #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 | |
5546 | ||
5547 | ||
5548 | /***********************************/ | |
5549 | /* MC_CMD_RSS_CONTEXT_GET_KEY | |
5550 | * Get the Toeplitz hash key for an RSS context. | |
5551 | */ | |
5552 | #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 | |
5553 | ||
5554 | /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ | |
5555 | #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 | |
5556 | /* The handle of the RSS context */ | |
5557 | #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 | |
5558 | ||
5559 | /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ | |
5560 | #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 | |
5561 | /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ | |
5562 | #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 | |
5563 | #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 | |
5564 | ||
5565 | ||
5566 | /***********************************/ | |
5567 | /* MC_CMD_RSS_CONTEXT_SET_TABLE | |
5568 | * Set the indirection table for an RSS context. | |
5569 | */ | |
5570 | #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 | |
5571 | ||
5572 | /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ | |
5573 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 | |
5574 | /* The handle of the RSS context */ | |
5575 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 | |
5576 | /* The 128-byte indirection table (1 byte per entry) */ | |
5577 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 | |
5578 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 | |
5579 | ||
5580 | /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ | |
5581 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 | |
5582 | ||
5583 | ||
5584 | /***********************************/ | |
5585 | /* MC_CMD_RSS_CONTEXT_GET_TABLE | |
5586 | * Get the indirection table for an RSS context. | |
5587 | */ | |
5588 | #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 | |
5589 | ||
5590 | /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ | |
5591 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 | |
5592 | /* The handle of the RSS context */ | |
5593 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 | |
5594 | ||
5595 | /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ | |
5596 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 | |
5597 | /* The 128-byte indirection table (1 byte per entry) */ | |
5598 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 | |
5599 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 | |
5600 | ||
5601 | ||
5602 | /***********************************/ | |
5603 | /* MC_CMD_RSS_CONTEXT_SET_FLAGS | |
5604 | * Set various control flags for an RSS context. | |
5605 | */ | |
5606 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 | |
5607 | ||
5608 | /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ | |
5609 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 | |
5610 | /* The handle of the RSS context */ | |
5611 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 | |
5612 | /* Hash control flags */ | |
5613 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 | |
5614 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 | |
5615 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 | |
5616 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 | |
5617 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 | |
5618 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 | |
5619 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 | |
5620 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 | |
5621 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 | |
5622 | ||
5623 | /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ | |
5624 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 | |
5625 | ||
5626 | ||
5627 | /***********************************/ | |
5628 | /* MC_CMD_RSS_CONTEXT_GET_FLAGS | |
5629 | * Get various control flags for an RSS context. | |
5630 | */ | |
5631 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 | |
5632 | ||
5633 | /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ | |
5634 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 | |
5635 | /* The handle of the RSS context */ | |
5636 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 | |
5637 | ||
5638 | /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ | |
5639 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 | |
5640 | /* Hash control flags */ | |
5641 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 | |
5642 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 | |
5643 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 | |
5644 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 | |
5645 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 | |
5646 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 | |
5647 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 | |
5648 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 | |
5649 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 | |
5650 | ||
5651 | ||
5652 | /***********************************/ | |
5653 | /* MC_CMD_DOT1P_MAPPING_ALLOC | |
5654 | * Allocate a .1p mapping. | |
5655 | */ | |
5656 | #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 | |
5657 | ||
5658 | /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ | |
5659 | #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 | |
5660 | /* The handle of the owning upstream port */ | |
5661 | #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
5662 | /* Number of queues spanned by this mapping, in the range 1-64; valid fixed | |
5663 | * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and | |
5664 | * referenced RSS contexts must span no more than this number. | |
5665 | */ | |
5666 | #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 | |
5667 | ||
5668 | /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ | |
5669 | #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 | |
5670 | /* The handle of the new .1p mapping */ | |
5671 | #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 | |
5672 | ||
5673 | ||
5674 | /***********************************/ | |
5675 | /* MC_CMD_DOT1P_MAPPING_FREE | |
5676 | * Free a .1p mapping. | |
5677 | */ | |
5678 | #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 | |
5679 | ||
5680 | /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ | |
5681 | #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 | |
5682 | /* The handle of the .1p mapping */ | |
5683 | #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 | |
5684 | ||
5685 | /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ | |
5686 | #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 | |
5687 | ||
5688 | ||
5689 | /***********************************/ | |
5690 | /* MC_CMD_DOT1P_MAPPING_SET_TABLE | |
5691 | * Set the mapping table for a .1p mapping. | |
5692 | */ | |
5693 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 | |
5694 | ||
5695 | /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ | |
5696 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 | |
5697 | /* The handle of the .1p mapping */ | |
5698 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 | |
5699 | /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context | |
5700 | * handle) | |
5701 | */ | |
5702 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 | |
5703 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 | |
5704 | ||
5705 | /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ | |
5706 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 | |
5707 | ||
5708 | ||
5709 | /***********************************/ | |
5710 | /* MC_CMD_DOT1P_MAPPING_GET_TABLE | |
5711 | * Get the mapping table for a .1p mapping. | |
5712 | */ | |
5713 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 | |
5714 | ||
5715 | /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ | |
5716 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 | |
5717 | /* The handle of the .1p mapping */ | |
5718 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 | |
5719 | ||
5720 | /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ | |
5721 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 | |
5722 | /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context | |
5723 | * handle) | |
5724 | */ | |
5725 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 | |
5726 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 | |
5727 | ||
5728 | ||
5729 | /***********************************/ | |
5730 | /* MC_CMD_GET_VECTOR_CFG | |
5731 | * Get Interrupt Vector config for this PF. | |
5732 | */ | |
5733 | #define MC_CMD_GET_VECTOR_CFG 0xbf | |
5734 | ||
5735 | /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ | |
5736 | #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 | |
5737 | ||
5738 | /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ | |
5739 | #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 | |
5740 | /* Base absolute interrupt vector number. */ | |
5741 | #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 | |
5742 | /* Number of interrupt vectors allocate to this PF. */ | |
5743 | #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 | |
5744 | /* Number of interrupt vectors to allocate per VF. */ | |
5745 | #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 | |
5746 | ||
5747 | ||
5748 | /***********************************/ | |
5749 | /* MC_CMD_SET_VECTOR_CFG | |
5750 | * Set Interrupt Vector config for this PF. | |
5751 | */ | |
5752 | #define MC_CMD_SET_VECTOR_CFG 0xc0 | |
5753 | ||
5754 | /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ | |
5755 | #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 | |
5756 | /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to | |
5757 | * let the system find a suitable base. | |
5758 | */ | |
5759 | #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 | |
5760 | /* Number of interrupt vectors allocate to this PF. */ | |
5761 | #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 | |
5762 | /* Number of interrupt vectors to allocate per VF. */ | |
5763 | #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 | |
5764 | ||
5765 | /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ | |
5766 | #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 | |
5767 | ||
5768 | ||
5769 | /***********************************/ | |
5770 | /* MC_CMD_RMON_RX_CLASS_STATS | |
5771 | * Retrieve rmon rx class statistics | |
5772 | */ | |
5773 | #define MC_CMD_RMON_RX_CLASS_STATS 0xc3 | |
5774 | ||
5775 | /* MC_CMD_RMON_RX_CLASS_STATS_IN msgrequest */ | |
5776 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_LEN 4 | |
5777 | /* flags */ | |
5778 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_FLAGS_OFST 0 | |
5779 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_LBN 0 | |
5780 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_WIDTH 8 | |
5781 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_LBN 8 | |
5782 | #define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_WIDTH 1 | |
5783 | ||
5784 | /* MC_CMD_RMON_RX_CLASS_STATS_OUT msgresponse */ | |
5785 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMIN 4 | |
5786 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMAX 252 | |
5787 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LEN(num) (0+4*(num)) | |
5788 | /* Array of stats */ | |
5789 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_OFST 0 | |
5790 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_LEN 4 | |
5791 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MINNUM 1 | |
5792 | #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MAXNUM 63 | |
5793 | ||
5794 | ||
5795 | /***********************************/ | |
5796 | /* MC_CMD_RMON_TX_CLASS_STATS | |
5797 | * Retrieve rmon tx class statistics | |
5798 | */ | |
5799 | #define MC_CMD_RMON_TX_CLASS_STATS 0xc4 | |
5800 | ||
5801 | /* MC_CMD_RMON_TX_CLASS_STATS_IN msgrequest */ | |
5802 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_LEN 4 | |
5803 | /* flags */ | |
5804 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_FLAGS_OFST 0 | |
5805 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_LBN 0 | |
5806 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_WIDTH 8 | |
5807 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_LBN 8 | |
5808 | #define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_WIDTH 1 | |
5809 | ||
5810 | /* MC_CMD_RMON_TX_CLASS_STATS_OUT msgresponse */ | |
5811 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMIN 4 | |
5812 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMAX 252 | |
5813 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LEN(num) (0+4*(num)) | |
5814 | /* Array of stats */ | |
5815 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_OFST 0 | |
5816 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_LEN 4 | |
5817 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MINNUM 1 | |
5818 | #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MAXNUM 63 | |
5819 | ||
5820 | ||
5821 | /***********************************/ | |
5822 | /* MC_CMD_RMON_RX_SUPER_CLASS_STATS | |
5823 | * Retrieve rmon rx super_class statistics | |
5824 | */ | |
5825 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS 0xc5 | |
5826 | ||
5827 | /* MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN msgrequest */ | |
5828 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_LEN 4 | |
5829 | /* flags */ | |
5830 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0 | |
5831 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0 | |
5832 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4 | |
5833 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_LBN 4 | |
5834 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_WIDTH 1 | |
5835 | ||
5836 | /* MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT msgresponse */ | |
5837 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMIN 4 | |
5838 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMAX 252 | |
5839 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num)) | |
5840 | /* Array of stats */ | |
5841 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0 | |
5842 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4 | |
5843 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1 | |
5844 | #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63 | |
5845 | ||
5846 | ||
5847 | /***********************************/ | |
5848 | /* MC_CMD_RMON_TX_SUPER_CLASS_STATS | |
5849 | * Retrieve rmon tx super_class statistics | |
5850 | */ | |
5851 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS 0xc6 | |
5852 | ||
5853 | /* MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN msgrequest */ | |
5854 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_LEN 4 | |
5855 | /* flags */ | |
5856 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0 | |
5857 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0 | |
5858 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4 | |
5859 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_LBN 4 | |
5860 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_WIDTH 1 | |
5861 | ||
5862 | /* MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT msgresponse */ | |
5863 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMIN 4 | |
5864 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMAX 252 | |
5865 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num)) | |
5866 | /* Array of stats */ | |
5867 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0 | |
5868 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4 | |
5869 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1 | |
5870 | #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63 | |
5871 | ||
5872 | ||
5873 | /***********************************/ | |
5874 | /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS | |
5875 | * Add qid to class for statistics collection | |
5876 | */ | |
5877 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS 0xc7 | |
5878 | ||
5879 | /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN msgrequest */ | |
5880 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_LEN 12 | |
5881 | /* class */ | |
5882 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 | |
5883 | /* qid */ | |
5884 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_QID_OFST 4 | |
5885 | /* flags */ | |
5886 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 | |
5887 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 | |
5888 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 | |
5889 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 | |
5890 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 | |
5891 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_LBN 8 | |
5892 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 | |
5893 | ||
5894 | /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT msgresponse */ | |
5895 | #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT_LEN 0 | |
5896 | ||
5897 | ||
5898 | /***********************************/ | |
5899 | /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS | |
5900 | * Add qid to class for statistics collection | |
5901 | */ | |
5902 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS 0xc8 | |
5903 | ||
5904 | /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN msgrequest */ | |
5905 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_LEN 12 | |
5906 | /* class */ | |
5907 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 | |
5908 | /* qid */ | |
5909 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_QID_OFST 4 | |
5910 | /* flags */ | |
5911 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 | |
5912 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 | |
5913 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 | |
5914 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 | |
5915 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 | |
5916 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_LBN 8 | |
5917 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 | |
5918 | ||
5919 | /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT msgresponse */ | |
5920 | #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT_LEN 0 | |
5921 | ||
5922 | ||
5923 | /***********************************/ | |
5924 | /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS | |
5925 | * Add qid to class for statistics collection | |
5926 | */ | |
5927 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS 0xc9 | |
5928 | ||
5929 | /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN msgrequest */ | |
5930 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_LEN 12 | |
5931 | /* class */ | |
5932 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 | |
5933 | /* qid */ | |
5934 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_QID_OFST 4 | |
5935 | /* flags */ | |
5936 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 | |
5937 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 | |
5938 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 | |
5939 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 | |
5940 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 | |
5941 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_LBN 8 | |
5942 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 | |
5943 | ||
5944 | /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT msgresponse */ | |
5945 | #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT_LEN 0 | |
5946 | ||
5947 | ||
5948 | /***********************************/ | |
5949 | /* MC_CMD_RMON_ALLOC_CLASS | |
5950 | * Allocate an rmon class | |
5951 | */ | |
5952 | #define MC_CMD_RMON_ALLOC_CLASS 0xca | |
5953 | ||
5954 | /* MC_CMD_RMON_ALLOC_CLASS_IN msgrequest */ | |
5955 | #define MC_CMD_RMON_ALLOC_CLASS_IN_LEN 0 | |
5956 | ||
5957 | /* MC_CMD_RMON_ALLOC_CLASS_OUT msgresponse */ | |
5958 | #define MC_CMD_RMON_ALLOC_CLASS_OUT_LEN 4 | |
5959 | /* class */ | |
5960 | #define MC_CMD_RMON_ALLOC_CLASS_OUT_CLASS_OFST 0 | |
5961 | ||
5962 | ||
5963 | /***********************************/ | |
5964 | /* MC_CMD_RMON_DEALLOC_CLASS | |
5965 | * Deallocate an rmon class | |
5966 | */ | |
5967 | #define MC_CMD_RMON_DEALLOC_CLASS 0xcb | |
5968 | ||
5969 | /* MC_CMD_RMON_DEALLOC_CLASS_IN msgrequest */ | |
5970 | #define MC_CMD_RMON_DEALLOC_CLASS_IN_LEN 4 | |
5971 | /* class */ | |
5972 | #define MC_CMD_RMON_DEALLOC_CLASS_IN_CLASS_OFST 0 | |
5973 | ||
5974 | /* MC_CMD_RMON_DEALLOC_CLASS_OUT msgresponse */ | |
5975 | #define MC_CMD_RMON_DEALLOC_CLASS_OUT_LEN 0 | |
5976 | ||
5977 | ||
5978 | /***********************************/ | |
5979 | /* MC_CMD_RMON_ALLOC_SUPER_CLASS | |
5980 | * Allocate an rmon super_class | |
5981 | */ | |
5982 | #define MC_CMD_RMON_ALLOC_SUPER_CLASS 0xcc | |
5983 | ||
5984 | /* MC_CMD_RMON_ALLOC_SUPER_CLASS_IN msgrequest */ | |
5985 | #define MC_CMD_RMON_ALLOC_SUPER_CLASS_IN_LEN 0 | |
5986 | ||
5987 | /* MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT msgresponse */ | |
5988 | #define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_LEN 4 | |
5989 | /* super_class */ | |
5990 | #define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_SUPER_CLASS_OFST 0 | |
5991 | ||
5992 | ||
5993 | /***********************************/ | |
5994 | /* MC_CMD_RMON_DEALLOC_SUPER_CLASS | |
5995 | * Deallocate an rmon tx super_class | |
5996 | */ | |
5997 | #define MC_CMD_RMON_DEALLOC_SUPER_CLASS 0xcd | |
5998 | ||
5999 | /* MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN msgrequest */ | |
6000 | #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_LEN 4 | |
6001 | /* super_class */ | |
6002 | #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_SUPER_CLASS_OFST 0 | |
6003 | ||
6004 | /* MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT msgresponse */ | |
6005 | #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT_LEN 0 | |
6006 | ||
6007 | ||
6008 | /***********************************/ | |
6009 | /* MC_CMD_RMON_RX_UP_CONV_STATS | |
6010 | * Retrieve up converter statistics | |
6011 | */ | |
6012 | #define MC_CMD_RMON_RX_UP_CONV_STATS 0xce | |
6013 | ||
6014 | /* MC_CMD_RMON_RX_UP_CONV_STATS_IN msgrequest */ | |
6015 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_LEN 4 | |
6016 | /* flags */ | |
6017 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_FLAGS_OFST 0 | |
6018 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_LBN 0 | |
6019 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_WIDTH 2 | |
6020 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_LBN 2 | |
6021 | #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_WIDTH 1 | |
6022 | ||
6023 | /* MC_CMD_RMON_RX_UP_CONV_STATS_OUT msgresponse */ | |
6024 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMIN 4 | |
6025 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMAX 252 | |
6026 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LEN(num) (0+4*(num)) | |
6027 | /* Array of stats */ | |
6028 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_OFST 0 | |
6029 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_LEN 4 | |
6030 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MINNUM 1 | |
6031 | #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MAXNUM 63 | |
6032 | ||
6033 | ||
6034 | /***********************************/ | |
6035 | /* MC_CMD_RMON_RX_IPI_STATS | |
6036 | * Retrieve rx ipi stats | |
6037 | */ | |
6038 | #define MC_CMD_RMON_RX_IPI_STATS 0xcf | |
6039 | ||
6040 | /* MC_CMD_RMON_RX_IPI_STATS_IN msgrequest */ | |
6041 | #define MC_CMD_RMON_RX_IPI_STATS_IN_LEN 4 | |
6042 | /* flags */ | |
6043 | #define MC_CMD_RMON_RX_IPI_STATS_IN_FLAGS_OFST 0 | |
6044 | #define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_LBN 0 | |
6045 | #define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_WIDTH 5 | |
6046 | #define MC_CMD_RMON_RX_IPI_STATS_IN_RST_LBN 5 | |
6047 | #define MC_CMD_RMON_RX_IPI_STATS_IN_RST_WIDTH 1 | |
6048 | ||
6049 | /* MC_CMD_RMON_RX_IPI_STATS_OUT msgresponse */ | |
6050 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMIN 4 | |
6051 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMAX 252 | |
6052 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_LEN(num) (0+4*(num)) | |
6053 | /* Array of stats */ | |
6054 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_OFST 0 | |
6055 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_LEN 4 | |
6056 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MINNUM 1 | |
6057 | #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MAXNUM 63 | |
6058 | ||
6059 | ||
6060 | /***********************************/ | |
6061 | /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS | |
6062 | * Retrieve rx ipsec cntxt_ptr indexed stats | |
6063 | */ | |
6064 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS 0xd0 | |
6065 | ||
6066 | /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */ | |
6067 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4 | |
6068 | /* flags */ | |
6069 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0 | |
6070 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0 | |
6071 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9 | |
6072 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9 | |
6073 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1 | |
6074 | ||
6075 | /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */ | |
6076 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4 | |
6077 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252 | |
6078 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num)) | |
6079 | /* Array of stats */ | |
6080 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0 | |
6081 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4 | |
6082 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1 | |
6083 | #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63 | |
6084 | ||
6085 | ||
6086 | /***********************************/ | |
6087 | /* MC_CMD_RMON_RX_IPSEC_PORT_STATS | |
6088 | * Retrieve rx ipsec port indexed stats | |
6089 | */ | |
6090 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS 0xd1 | |
6091 | ||
6092 | /* MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN msgrequest */ | |
6093 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_LEN 4 | |
6094 | /* flags */ | |
6095 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0 | |
6096 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_LBN 0 | |
6097 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2 | |
6098 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_LBN 2 | |
6099 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_WIDTH 1 | |
6100 | ||
6101 | /* MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT msgresponse */ | |
6102 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMIN 4 | |
6103 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMAX 252 | |
6104 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num)) | |
6105 | /* Array of stats */ | |
6106 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0 | |
6107 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4 | |
6108 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1 | |
6109 | #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63 | |
6110 | ||
6111 | ||
6112 | /***********************************/ | |
6113 | /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS | |
6114 | * Retrieve tx ipsec overflow | |
6115 | */ | |
6116 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS 0xd2 | |
6117 | ||
6118 | /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN msgrequest */ | |
6119 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_LEN 4 | |
6120 | /* flags */ | |
6121 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0 | |
6122 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0 | |
6123 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2 | |
6124 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_LBN 2 | |
6125 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1 | |
6126 | ||
6127 | /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT msgresponse */ | |
6128 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMIN 4 | |
6129 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMAX 252 | |
6130 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num)) | |
6131 | /* Array of stats */ | |
6132 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0 | |
6133 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4 | |
6134 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1 | |
6135 | #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63 | |
6136 | ||
6137 | ||
6138 | /***********************************/ | |
6139 | /* MC_CMD_VPORT_ADD_MAC_ADDRESS | |
6140 | * Add a MAC address to a v-port | |
6141 | */ | |
6142 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 | |
6143 | ||
6144 | /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ | |
6145 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 | |
6146 | /* The handle of the v-port */ | |
6147 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 | |
6148 | /* MAC address to add */ | |
6149 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 | |
6150 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 | |
6151 | ||
6152 | /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ | |
6153 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 | |
6154 | ||
6155 | ||
6156 | /***********************************/ | |
6157 | /* MC_CMD_VPORT_DEL_MAC_ADDRESS | |
6158 | * Delete a MAC address from a v-port | |
6159 | */ | |
6160 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 | |
6161 | ||
6162 | /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ | |
6163 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 | |
6164 | /* The handle of the v-port */ | |
6165 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 | |
6166 | /* MAC address to add */ | |
6167 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 | |
6168 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 | |
6169 | ||
6170 | /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ | |
6171 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 | |
6172 | ||
6173 | ||
6174 | /***********************************/ | |
6175 | /* MC_CMD_VPORT_GET_MAC_ADDRESSES | |
6176 | * Delete a MAC address from a v-port | |
6177 | */ | |
6178 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa | |
6179 | ||
6180 | /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ | |
6181 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 | |
6182 | /* The handle of the v-port */ | |
6183 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 | |
6184 | ||
6185 | /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ | |
6186 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 | |
6187 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 | |
6188 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) | |
6189 | /* The number of MAC addresses returned */ | |
6190 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 | |
6191 | /* Array of MAC addresses */ | |
6192 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 | |
6193 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 | |
6194 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 | |
6195 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 | |
6196 | ||
6197 | ||
6198 | /***********************************/ | |
6199 | /* MC_CMD_DUMP_BUFTBL_ENTRIES | |
6200 | * Dump buffer table entries, mainly for command client debug use. Dumps | |
6201 | * absolute entries, and does not use chunk handles. All entries must be in | |
6202 | * range, and used for q page mapping, Although the latter restriction may be | |
6203 | * lifted in future. | |
6204 | */ | |
6205 | #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab | |
6206 | ||
6207 | /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ | |
6208 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 | |
6209 | /* Index of the first buffer table entry. */ | |
6210 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 | |
6211 | /* Number of buffer table entries to dump. */ | |
6212 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 | |
6213 | ||
6214 | /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ | |
6215 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 | |
6216 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 | |
6217 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) | |
6218 | /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ | |
6219 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 | |
6220 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 | |
6221 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 | |
6222 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 | |
6223 | ||
6224 | ||
6225 | /***********************************/ | |
6226 | /* MC_CMD_SET_RXDP_CONFIG | |
6227 | * Set global RXDP configuration settings | |
6228 | */ | |
6229 | #define MC_CMD_SET_RXDP_CONFIG 0xc1 | |
6230 | ||
6231 | /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ | |
6232 | #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 | |
6233 | #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 | |
6234 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 | |
6235 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 | |
6236 | ||
6237 | /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ | |
6238 | #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 | |
6239 | ||
6240 | ||
6241 | /***********************************/ | |
6242 | /* MC_CMD_GET_RXDP_CONFIG | |
6243 | * Get global RXDP configuration settings | |
6244 | */ | |
6245 | #define MC_CMD_GET_RXDP_CONFIG 0xc2 | |
6246 | ||
6247 | /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ | |
6248 | #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 | |
6249 | ||
6250 | /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ | |
6251 | #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 | |
6252 | #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 | |
6253 | #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 | |
6254 | #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 | |
6255 | ||
6256 | ||
6257 | /***********************************/ | |
6258 | /* MC_CMD_RMON_RX_CLASS_DROPS_STATS | |
6259 | * Retrieve rx class drop stats | |
6260 | */ | |
6261 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS 0xd3 | |
6262 | ||
6263 | /* MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN msgrequest */ | |
6264 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_LEN 4 | |
6265 | /* flags */ | |
6266 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_FLAGS_OFST 0 | |
6267 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_LBN 0 | |
6268 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_WIDTH 8 | |
6269 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_LBN 8 | |
6270 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_WIDTH 1 | |
6271 | ||
6272 | /* MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT msgresponse */ | |
6273 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMIN 4 | |
6274 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMAX 252 | |
6275 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num)) | |
6276 | /* Array of stats */ | |
6277 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0 | |
6278 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4 | |
6279 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1 | |
6280 | #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63 | |
6281 | ||
6282 | ||
6283 | /***********************************/ | |
6284 | /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS | |
6285 | * Retrieve rx super class drop stats | |
6286 | */ | |
6287 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS 0xd4 | |
6288 | ||
6289 | /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN msgrequest */ | |
6290 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_LEN 4 | |
6291 | /* flags */ | |
6292 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_FLAGS_OFST 0 | |
6293 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_LBN 0 | |
6294 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_WIDTH 4 | |
6295 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_LBN 4 | |
6296 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_WIDTH 1 | |
6297 | ||
6298 | /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT msgresponse */ | |
6299 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMIN 4 | |
6300 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMAX 252 | |
6301 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num)) | |
6302 | /* Array of stats */ | |
6303 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0 | |
6304 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4 | |
6305 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1 | |
6306 | #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63 | |
6307 | ||
6308 | ||
6309 | /***********************************/ | |
6310 | /* MC_CMD_RMON_RX_ERRORS_STATS | |
6311 | * Retrieve rxdp errors | |
6312 | */ | |
6313 | #define MC_CMD_RMON_RX_ERRORS_STATS 0xd5 | |
6314 | ||
6315 | /* MC_CMD_RMON_RX_ERRORS_STATS_IN msgrequest */ | |
6316 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_LEN 4 | |
6317 | /* flags */ | |
6318 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_FLAGS_OFST 0 | |
6319 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_LBN 0 | |
6320 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_WIDTH 11 | |
6321 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_LBN 11 | |
6322 | #define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_WIDTH 1 | |
6323 | ||
6324 | /* MC_CMD_RMON_RX_ERRORS_STATS_OUT msgresponse */ | |
6325 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMIN 4 | |
6326 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMAX 252 | |
6327 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LEN(num) (0+4*(num)) | |
6328 | /* Array of stats */ | |
6329 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_OFST 0 | |
6330 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_LEN 4 | |
6331 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MINNUM 1 | |
6332 | #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63 | |
6333 | ||
6334 | ||
6335 | /***********************************/ | |
6336 | /* MC_CMD_RMON_RX_OVERFLOW_STATS | |
6337 | * Retrieve rxdp overflow | |
6338 | */ | |
6339 | #define MC_CMD_RMON_RX_OVERFLOW_STATS 0xd6 | |
6340 | ||
6341 | /* MC_CMD_RMON_RX_OVERFLOW_STATS_IN msgrequest */ | |
6342 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_LEN 4 | |
6343 | /* flags */ | |
6344 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_FLAGS_OFST 0 | |
6345 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_LBN 0 | |
6346 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_WIDTH 8 | |
6347 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_LBN 8 | |
6348 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_WIDTH 1 | |
6349 | ||
6350 | /* MC_CMD_RMON_RX_OVERFLOW_STATS_OUT msgresponse */ | |
6351 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMIN 4 | |
6352 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMAX 252 | |
6353 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num)) | |
6354 | /* Array of stats */ | |
6355 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_OFST 0 | |
6356 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_LEN 4 | |
6357 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1 | |
6358 | #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63 | |
6359 | ||
6360 | ||
6361 | /***********************************/ | |
6362 | /* MC_CMD_RMON_TX_IPI_STATS | |
6363 | * Retrieve tx ipi stats | |
6364 | */ | |
6365 | #define MC_CMD_RMON_TX_IPI_STATS 0xd7 | |
6366 | ||
6367 | /* MC_CMD_RMON_TX_IPI_STATS_IN msgrequest */ | |
6368 | #define MC_CMD_RMON_TX_IPI_STATS_IN_LEN 4 | |
6369 | /* flags */ | |
6370 | #define MC_CMD_RMON_TX_IPI_STATS_IN_FLAGS_OFST 0 | |
6371 | #define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_LBN 0 | |
6372 | #define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_WIDTH 5 | |
6373 | #define MC_CMD_RMON_TX_IPI_STATS_IN_RST_LBN 5 | |
6374 | #define MC_CMD_RMON_TX_IPI_STATS_IN_RST_WIDTH 1 | |
6375 | ||
6376 | /* MC_CMD_RMON_TX_IPI_STATS_OUT msgresponse */ | |
6377 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMIN 4 | |
6378 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMAX 252 | |
6379 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_LEN(num) (0+4*(num)) | |
6380 | /* Array of stats */ | |
6381 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_OFST 0 | |
6382 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_LEN 4 | |
6383 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MINNUM 1 | |
6384 | #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MAXNUM 63 | |
6385 | ||
6386 | ||
6387 | /***********************************/ | |
6388 | /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS | |
6389 | * Retrieve tx ipsec counters by cntxt_ptr | |
6390 | */ | |
6391 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS 0xd8 | |
6392 | ||
6393 | /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */ | |
6394 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4 | |
6395 | /* flags */ | |
6396 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0 | |
6397 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0 | |
6398 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9 | |
6399 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9 | |
6400 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1 | |
6401 | ||
6402 | /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */ | |
6403 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4 | |
6404 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252 | |
6405 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num)) | |
6406 | /* Array of stats */ | |
6407 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0 | |
6408 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4 | |
6409 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1 | |
6410 | #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63 | |
6411 | ||
6412 | ||
6413 | /***********************************/ | |
6414 | /* MC_CMD_RMON_TX_IPSEC_PORT_STATS | |
6415 | * Retrieve tx ipsec counters by port | |
6416 | */ | |
6417 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS 0xd9 | |
6418 | ||
6419 | /* MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN msgrequest */ | |
6420 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_LEN 4 | |
6421 | /* flags */ | |
6422 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0 | |
6423 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_LBN 0 | |
6424 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2 | |
6425 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_LBN 2 | |
6426 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_WIDTH 1 | |
6427 | ||
6428 | /* MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT msgresponse */ | |
6429 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMIN 4 | |
6430 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMAX 252 | |
6431 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num)) | |
6432 | /* Array of stats */ | |
6433 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0 | |
6434 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4 | |
6435 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1 | |
6436 | #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63 | |
6437 | ||
6438 | ||
6439 | /***********************************/ | |
6440 | /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS | |
6441 | * Retrieve tx ipsec overflow | |
6442 | */ | |
6443 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS 0xda | |
6444 | ||
6445 | /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN msgrequest */ | |
6446 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_LEN 4 | |
6447 | /* flags */ | |
6448 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0 | |
6449 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0 | |
6450 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2 | |
6451 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_LBN 2 | |
6452 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1 | |
6453 | ||
6454 | /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT msgresponse */ | |
6455 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMIN 4 | |
6456 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMAX 252 | |
6457 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num)) | |
6458 | /* Array of stats */ | |
6459 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0 | |
6460 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4 | |
6461 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1 | |
6462 | #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63 | |
6463 | ||
6464 | ||
6465 | /***********************************/ | |
6466 | /* MC_CMD_RMON_TX_NOWHERE_STATS | |
6467 | * Retrieve tx nowhere stats | |
6468 | */ | |
6469 | #define MC_CMD_RMON_TX_NOWHERE_STATS 0xdb | |
6470 | ||
6471 | /* MC_CMD_RMON_TX_NOWHERE_STATS_IN msgrequest */ | |
6472 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_LEN 4 | |
6473 | /* flags */ | |
6474 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_FLAGS_OFST 0 | |
6475 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_LBN 0 | |
6476 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_WIDTH 8 | |
6477 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_LBN 8 | |
6478 | #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_WIDTH 1 | |
6479 | ||
6480 | /* MC_CMD_RMON_TX_NOWHERE_STATS_OUT msgresponse */ | |
6481 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMIN 4 | |
6482 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMAX 252 | |
6483 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LEN(num) (0+4*(num)) | |
6484 | /* Array of stats */ | |
6485 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_OFST 0 | |
6486 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_LEN 4 | |
6487 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MINNUM 1 | |
6488 | #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MAXNUM 63 | |
6489 | ||
6490 | ||
6491 | /***********************************/ | |
6492 | /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS | |
6493 | * Retrieve tx nowhere qbb stats | |
6494 | */ | |
6495 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS 0xdc | |
6496 | ||
6497 | /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN msgrequest */ | |
6498 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_LEN 4 | |
6499 | /* flags */ | |
6500 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_FLAGS_OFST 0 | |
6501 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_LBN 0 | |
6502 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_WIDTH 3 | |
6503 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_LBN 3 | |
6504 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_WIDTH 1 | |
6505 | ||
6506 | /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT msgresponse */ | |
6507 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMIN 4 | |
6508 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMAX 252 | |
6509 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LEN(num) (0+4*(num)) | |
6510 | /* Array of stats */ | |
6511 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_OFST 0 | |
6512 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_LEN 4 | |
6513 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MINNUM 1 | |
6514 | #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MAXNUM 63 | |
6515 | ||
6516 | ||
6517 | /***********************************/ | |
6518 | /* MC_CMD_RMON_TX_ERRORS_STATS | |
6519 | * Retrieve rxdp errors | |
6520 | */ | |
6521 | #define MC_CMD_RMON_TX_ERRORS_STATS 0xdd | |
6522 | ||
6523 | /* MC_CMD_RMON_TX_ERRORS_STATS_IN msgrequest */ | |
6524 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_LEN 4 | |
6525 | /* flags */ | |
6526 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_FLAGS_OFST 0 | |
6527 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_LBN 0 | |
6528 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_WIDTH 11 | |
6529 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_LBN 11 | |
6530 | #define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_WIDTH 1 | |
6531 | ||
6532 | /* MC_CMD_RMON_TX_ERRORS_STATS_OUT msgresponse */ | |
6533 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMIN 4 | |
6534 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMAX 252 | |
6535 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LEN(num) (0+4*(num)) | |
6536 | /* Array of stats */ | |
6537 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_OFST 0 | |
6538 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_LEN 4 | |
6539 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MINNUM 1 | |
6540 | #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63 | |
6541 | ||
6542 | ||
6543 | /***********************************/ | |
6544 | /* MC_CMD_RMON_TX_OVERFLOW_STATS | |
6545 | * Retrieve rxdp overflow | |
6546 | */ | |
6547 | #define MC_CMD_RMON_TX_OVERFLOW_STATS 0xde | |
6548 | ||
6549 | /* MC_CMD_RMON_TX_OVERFLOW_STATS_IN msgrequest */ | |
6550 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_LEN 4 | |
6551 | /* flags */ | |
6552 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_FLAGS_OFST 0 | |
6553 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_LBN 0 | |
6554 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_WIDTH 8 | |
6555 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_LBN 8 | |
6556 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_WIDTH 1 | |
6557 | ||
6558 | /* MC_CMD_RMON_TX_OVERFLOW_STATS_OUT msgresponse */ | |
6559 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMIN 4 | |
6560 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMAX 252 | |
6561 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num)) | |
6562 | /* Array of stats */ | |
6563 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_OFST 0 | |
6564 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_LEN 4 | |
6565 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1 | |
6566 | #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63 | |
6567 | ||
6568 | ||
6569 | /***********************************/ | |
6570 | /* MC_CMD_RMON_COLLECT_CLASS_STATS | |
6571 | * Explicitly collect class stats at the specified evb port | |
6572 | */ | |
6573 | #define MC_CMD_RMON_COLLECT_CLASS_STATS 0xdf | |
6574 | ||
6575 | /* MC_CMD_RMON_COLLECT_CLASS_STATS_IN msgrequest */ | |
6576 | #define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_LEN 4 | |
6577 | /* The port id associated with the vport/pport at which to collect class stats | |
6578 | */ | |
6579 | #define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_PORT_ID_OFST 0 | |
6580 | ||
6581 | /* MC_CMD_RMON_COLLECT_CLASS_STATS_OUT msgresponse */ | |
6582 | #define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_LEN 4 | |
6583 | /* class */ | |
6584 | #define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_CLASS_OFST 0 | |
6585 | ||
6586 | ||
6587 | /***********************************/ | |
6588 | /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS | |
6589 | * Explicitly collect class stats at the specified evb port | |
6590 | */ | |
6591 | #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS 0xe0 | |
6592 | ||
6593 | /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN msgrequest */ | |
6594 | #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_LEN 4 | |
6595 | /* The port id associated with the vport/pport at which to collect class stats | |
6596 | */ | |
6597 | #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_PORT_ID_OFST 0 | |
6598 | ||
6599 | /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT msgresponse */ | |
6600 | #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_LEN 4 | |
6601 | /* super_class */ | |
6602 | #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_SUPER_CLASS_OFST 0 | |
6603 | ||
6604 | ||
6605 | /***********************************/ | |
6606 | /* MC_CMD_GET_CLOCK | |
6607 | * Return the system and PDCPU clock frequencies. | |
6608 | */ | |
6609 | #define MC_CMD_GET_CLOCK 0xac | |
6610 | ||
6611 | /* MC_CMD_GET_CLOCK_IN msgrequest */ | |
6612 | #define MC_CMD_GET_CLOCK_IN_LEN 0 | |
6613 | ||
6614 | /* MC_CMD_GET_CLOCK_OUT msgresponse */ | |
6615 | #define MC_CMD_GET_CLOCK_OUT_LEN 8 | |
6616 | /* System frequency, MHz */ | |
6617 | #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 | |
6618 | /* DPCPU frequency, MHz */ | |
6619 | #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 | |
6620 | ||
6621 | ||
6622 | /***********************************/ | |
6623 | /* MC_CMD_SET_CLOCK | |
6624 | * Control the system and DPCPU clock frequencies. Changes are lost reboot. | |
6625 | */ | |
6626 | #define MC_CMD_SET_CLOCK 0xad | |
6627 | ||
6628 | /* MC_CMD_SET_CLOCK_IN msgrequest */ | |
6629 | #define MC_CMD_SET_CLOCK_IN_LEN 12 | |
6630 | /* Requested system frequency in MHz; 0 leaves unchanged. */ | |
6631 | #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 | |
6632 | /* Requested inter-core frequency in MHz; 0 leaves unchanged. */ | |
6633 | #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 | |
6634 | /* Request DPCPU frequency in MHz; 0 leaves unchanged. */ | |
6635 | #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 | |
6636 | ||
6637 | /* MC_CMD_SET_CLOCK_OUT msgresponse */ | |
6638 | #define MC_CMD_SET_CLOCK_OUT_LEN 12 | |
6639 | /* Resulting system frequency in MHz */ | |
6640 | #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 | |
6641 | /* Resulting inter-core frequency in MHz */ | |
6642 | #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 | |
6643 | /* Resulting DPCPU frequency in MHz */ | |
6644 | #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 | |
6645 | ||
6646 | ||
6647 | /***********************************/ | |
6648 | /* MC_CMD_DPCPU_RPC | |
6649 | * Send an arbitrary DPCPU message. | |
6650 | */ | |
6651 | #define MC_CMD_DPCPU_RPC 0xae | |
6652 | ||
6653 | /* MC_CMD_DPCPU_RPC_IN msgrequest */ | |
6654 | #define MC_CMD_DPCPU_RPC_IN_LEN 36 | |
6655 | #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 | |
6656 | /* enum: RxDPCPU */ | |
6657 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x0 | |
6658 | /* enum: TxDPCPU0 */ | |
6659 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 | |
6660 | /* enum: TxDPCPU1 */ | |
6661 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 | |
6662 | /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be | |
6663 | * initialised to zero | |
6664 | */ | |
6665 | #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 | |
6666 | #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 | |
6667 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 | |
6668 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 | |
6669 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ | |
6670 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ | |
6671 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ | |
6672 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ | |
6673 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ | |
6674 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ | |
6675 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ | |
6676 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ | |
6677 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ | |
6678 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 | |
6679 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 | |
6680 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 | |
6681 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 | |
6682 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 | |
6683 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 | |
6684 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 | |
6685 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 | |
6686 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 | |
6687 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 | |
6688 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ | |
6689 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ | |
6690 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ | |
6691 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ | |
6692 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ | |
6693 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 | |
6694 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 | |
6695 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 | |
6696 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 | |
6697 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 | |
6698 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 | |
6699 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 | |
6700 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 | |
6701 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ | |
6702 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ | |
6703 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ | |
6704 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 | |
6705 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 | |
6706 | #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 | |
6707 | #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 | |
6708 | /* Register data to write. Only valid in write/write-read. */ | |
6709 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 | |
6710 | /* Register address. */ | |
6711 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 | |
6712 | ||
6713 | /* MC_CMD_DPCPU_RPC_OUT msgresponse */ | |
6714 | #define MC_CMD_DPCPU_RPC_OUT_LEN 36 | |
6715 | #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 | |
6716 | /* DATA */ | |
6717 | #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 | |
6718 | #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 | |
6719 | #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 | |
6720 | #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 | |
6721 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 | |
6722 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 | |
6723 | #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 | |
6724 | #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 | |
6725 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 | |
6726 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 | |
6727 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 | |
6728 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 | |
6729 | ||
6730 | ||
6731 | /***********************************/ | |
6732 | /* MC_CMD_TRIGGER_INTERRUPT | |
6733 | * Trigger an interrupt by prodding the BIU. | |
6734 | */ | |
6735 | #define MC_CMD_TRIGGER_INTERRUPT 0xe3 | |
6736 | ||
6737 | /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ | |
6738 | #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 | |
6739 | /* Interrupt level relative to base for function. */ | |
6740 | #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 | |
6741 | ||
6742 | /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ | |
6743 | #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 | |
6744 | ||
6745 | ||
6746 | /***********************************/ | |
6747 | /* MC_CMD_DUMP_DO | |
6748 | * Take a dump of the DUT state | |
6749 | */ | |
6750 | #define MC_CMD_DUMP_DO 0xe8 | |
6751 | ||
6752 | /* MC_CMD_DUMP_DO_IN msgrequest */ | |
6753 | #define MC_CMD_DUMP_DO_IN_LEN 52 | |
6754 | #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 | |
6755 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 | |
6756 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ | |
6757 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ | |
6758 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 | |
6759 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ | |
6760 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ | |
6761 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ | |
6762 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ | |
6763 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 | |
6764 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 | |
6765 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 | |
6766 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 | |
6767 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 | |
6768 | #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ | |
6769 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 | |
6770 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 | |
6771 | #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ | |
6772 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 | |
6773 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 | |
6774 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 | |
6775 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ | |
6776 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ | |
6777 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 | |
6778 | /* Enum values, see field(s): */ | |
6779 | /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ | |
6780 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 | |
6781 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 | |
6782 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 | |
6783 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 | |
6784 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 | |
6785 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 | |
6786 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 | |
6787 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 | |
6788 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 | |
6789 | ||
6790 | /* MC_CMD_DUMP_DO_OUT msgresponse */ | |
6791 | #define MC_CMD_DUMP_DO_OUT_LEN 4 | |
6792 | #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 | |
6793 | ||
6794 | ||
6795 | /***********************************/ | |
6796 | /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED | |
6797 | * Configure unsolicited dumps | |
6798 | */ | |
6799 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 | |
6800 | ||
6801 | /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ | |
6802 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 | |
6803 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 | |
6804 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 | |
6805 | /* Enum values, see field(s): */ | |
6806 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ | |
6807 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 | |
6808 | /* Enum values, see field(s): */ | |
6809 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ | |
6810 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 | |
6811 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 | |
6812 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 | |
6813 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 | |
6814 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 | |
6815 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 | |
6816 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 | |
6817 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 | |
6818 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 | |
6819 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 | |
6820 | /* Enum values, see field(s): */ | |
6821 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ | |
6822 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 | |
6823 | /* Enum values, see field(s): */ | |
6824 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ | |
6825 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 | |
6826 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 | |
6827 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 | |
6828 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 | |
6829 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 | |
6830 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 | |
6831 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 | |
6832 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 | |
6833 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 | |
6834 | ||
6835 | ||
6836 | /***********************************/ | |
6837 | /* MC_CMD_SET_PSU | |
6838 | * Adjusts power supply parameters. This is a warranty-voiding operation. | |
6839 | * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if | |
6840 | * the parameter is out of range. | |
6841 | */ | |
6842 | #define MC_CMD_SET_PSU 0xea | |
6843 | ||
6844 | /* MC_CMD_SET_PSU_IN msgrequest */ | |
6845 | #define MC_CMD_SET_PSU_IN_LEN 12 | |
6846 | #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 | |
6847 | #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ | |
6848 | #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 | |
6849 | #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ | |
6850 | #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ | |
6851 | /* desired value, eg voltage in mV */ | |
6852 | #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 | |
6853 | ||
6854 | /* MC_CMD_SET_PSU_OUT msgresponse */ | |
6855 | #define MC_CMD_SET_PSU_OUT_LEN 0 | |
6856 | ||
6857 | ||
6858 | /***********************************/ | |
6859 | /* MC_CMD_GET_FUNCTION_INFO | |
6860 | * Get function information. PF and VF number. | |
6861 | */ | |
6862 | #define MC_CMD_GET_FUNCTION_INFO 0xec | |
6863 | ||
6864 | /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ | |
6865 | #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 | |
6866 | ||
6867 | /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ | |
6868 | #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 | |
6869 | #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 | |
6870 | #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 | |
6871 | ||
6872 | ||
6873 | /***********************************/ | |
6874 | /* MC_CMD_ENABLE_OFFLINE_BIST | |
6875 | * Enters offline BIST mode. All queues are torn down, chip enters quiescent | |
6876 | * mode, calling function gets exclusive MCDI ownership. The only way out is | |
6877 | * reboot. | |
6878 | */ | |
6879 | #define MC_CMD_ENABLE_OFFLINE_BIST 0xed | |
6880 | ||
6881 | /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ | |
6882 | #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 | |
6883 | ||
6884 | /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ | |
6885 | #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 | |
6886 | ||
6887 | ||
6888 | /***********************************/ | |
6889 | /* MC_CMD_START_KR_EYE_PLOT | |
6890 | * Start KR Serdes Eye diagram plot on a given lane. Lane must have valid | |
6891 | * signal. | |
6892 | */ | |
6893 | #define MC_CMD_START_KR_EYE_PLOT 0xee | |
6894 | ||
6895 | /* MC_CMD_START_KR_EYE_PLOT_IN msgrequest */ | |
6896 | #define MC_CMD_START_KR_EYE_PLOT_IN_LEN 4 | |
6897 | #define MC_CMD_START_KR_EYE_PLOT_IN_LANE_OFST 0 | |
6898 | ||
6899 | /* MC_CMD_START_KR_EYE_PLOT_OUT msgresponse */ | |
6900 | #define MC_CMD_START_KR_EYE_PLOT_OUT_LEN 0 | |
6901 | ||
6902 | ||
6903 | /***********************************/ | |
6904 | /* MC_CMD_POLL_KR_EYE_PLOT | |
6905 | * Poll KR Serdes Eye diagram plot. Returns one row of BER data. The caller | |
6906 | * should call this command repeatedly after starting eye plot, until no more | |
6907 | * data is returned. | |
6908 | */ | |
6909 | #define MC_CMD_POLL_KR_EYE_PLOT 0xef | |
6910 | ||
6911 | /* MC_CMD_POLL_KR_EYE_PLOT_IN msgrequest */ | |
6912 | #define MC_CMD_POLL_KR_EYE_PLOT_IN_LEN 0 | |
6913 | ||
6914 | /* MC_CMD_POLL_KR_EYE_PLOT_OUT msgresponse */ | |
6915 | #define MC_CMD_POLL_KR_EYE_PLOT_OUT_LENMIN 0 | |
6916 | #define MC_CMD_POLL_KR_EYE_PLOT_OUT_LENMAX 252 | |
6917 | #define MC_CMD_POLL_KR_EYE_PLOT_OUT_LEN(num) (0+2*(num)) | |
6918 | #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_OFST 0 | |
6919 | #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_LEN 2 | |
6920 | #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_MINNUM 0 | |
6921 | #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 | |
6922 | ||
6923 | ||
6924 | /***********************************/ | |
6925 | /* MC_CMD_READ_FUSES | |
6926 | * Read data programmed into the device One-Time-Programmable (OTP) Fuses | |
6927 | */ | |
6928 | #define MC_CMD_READ_FUSES 0xf0 | |
6929 | ||
6930 | /* MC_CMD_READ_FUSES_IN msgrequest */ | |
6931 | #define MC_CMD_READ_FUSES_IN_LEN 8 | |
6932 | /* Offset in OTP to read */ | |
6933 | #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 | |
6934 | /* Length of data to read in bytes */ | |
6935 | #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 | |
6936 | ||
6937 | /* MC_CMD_READ_FUSES_OUT msgresponse */ | |
6938 | #define MC_CMD_READ_FUSES_OUT_LENMIN 4 | |
6939 | #define MC_CMD_READ_FUSES_OUT_LENMAX 252 | |
6940 | #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) | |
6941 | /* Length of returned OTP data in bytes */ | |
6942 | #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 | |
6943 | /* Returned data */ | |
6944 | #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 | |
6945 | #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 | |
6946 | #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 | |
6947 | #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 | |
6948 | ||
6949 | ||
6950 | /***********************************/ | |
6951 | /* MC_CMD_KR_TUNE | |
6952 | * Get or set KR Serdes RXEQ and TX Driver settings | |
6953 | */ | |
6954 | #define MC_CMD_KR_TUNE 0xf1 | |
6955 | ||
6956 | /* MC_CMD_KR_TUNE_IN msgrequest */ | |
6957 | #define MC_CMD_KR_TUNE_IN_LENMIN 4 | |
6958 | #define MC_CMD_KR_TUNE_IN_LENMAX 252 | |
6959 | #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) | |
6960 | /* Requested operation */ | |
6961 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 | |
6962 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 | |
6963 | /* enum: Get current RXEQ settings */ | |
6964 | #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 | |
6965 | /* enum: Override RXEQ settings */ | |
6966 | #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 | |
6967 | /* enum: Get current TX Driver settings */ | |
6968 | #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 | |
6969 | /* enum: Override TX Driver settings */ | |
6970 | #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 | |
6971 | /* enum: Force KR Serdes reset / recalibration */ | |
6972 | #define MC_CMD_KR_TUNE_IN_RECAL 0x4 | |
6973 | /* Align the arguments to 32 bits */ | |
6974 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 | |
6975 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 | |
6976 | /* Arguments specific to the operation */ | |
6977 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 | |
6978 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 | |
6979 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 | |
6980 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 | |
6981 | ||
6982 | /* MC_CMD_KR_TUNE_OUT msgresponse */ | |
6983 | #define MC_CMD_KR_TUNE_OUT_LEN 0 | |
6984 | ||
6985 | /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ | |
6986 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 | |
6987 | /* Requested operation */ | |
6988 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 | |
6989 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 | |
6990 | /* Align the arguments to 32 bits */ | |
6991 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 | |
6992 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 | |
6993 | ||
6994 | /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ | |
6995 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 | |
6996 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 | |
6997 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
6998 | /* RXEQ Parameter */ | |
6999 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 | |
7000 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 | |
7001 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 | |
7002 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 | |
7003 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 | |
7004 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
7005 | /* enum: Attenuation (0-15) */ | |
7006 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 | |
7007 | /* enum: CTLE Boost (0-15) */ | |
7008 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 | |
7009 | /* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ | |
7010 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 | |
7011 | /* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7012 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 | |
7013 | /* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7014 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 | |
7015 | /* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7016 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 | |
7017 | /* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7018 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 | |
7019 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 | |
7020 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 | |
7021 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ | |
7022 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ | |
7023 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ | |
7024 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ | |
7025 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ | |
7026 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 | |
7027 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 | |
7028 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 | |
7029 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 | |
7030 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 | |
7031 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 | |
7032 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 | |
7033 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 | |
7034 | ||
7035 | /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ | |
7036 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 | |
7037 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 | |
7038 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) | |
7039 | /* Requested operation */ | |
7040 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 | |
7041 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 | |
7042 | /* Align the arguments to 32 bits */ | |
7043 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 | |
7044 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 | |
7045 | /* RXEQ Parameter */ | |
7046 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 | |
7047 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 | |
7048 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 | |
7049 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 | |
7050 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 | |
7051 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 | |
7052 | /* Enum values, see field(s): */ | |
7053 | /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ | |
7054 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 | |
7055 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 | |
7056 | /* Enum values, see field(s): */ | |
7057 | /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ | |
7058 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 | |
7059 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 | |
7060 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 | |
7061 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 | |
7062 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 | |
7063 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 | |
7064 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 | |
7065 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 | |
7066 | ||
7067 | /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ | |
7068 | #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 | |
7069 | ||
7070 | /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ | |
7071 | #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 | |
7072 | /* Requested operation */ | |
7073 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 | |
7074 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 | |
7075 | /* Align the arguments to 32 bits */ | |
7076 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 | |
7077 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 | |
7078 | ||
7079 | /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ | |
7080 | #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 | |
7081 | ||
7082 | ||
7083 | /***********************************/ | |
7084 | /* MC_CMD_PCIE_TUNE | |
7085 | * Get or set PCIE Serdes RXEQ and TX Driver settings | |
7086 | */ | |
7087 | #define MC_CMD_PCIE_TUNE 0xf2 | |
7088 | ||
7089 | /* MC_CMD_PCIE_TUNE_IN msgrequest */ | |
7090 | #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 | |
7091 | #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 | |
7092 | #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) | |
7093 | /* Requested operation */ | |
7094 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 | |
7095 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 | |
7096 | /* enum: Get current RXEQ settings */ | |
7097 | #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 | |
7098 | /* enum: Override RXEQ settings */ | |
7099 | #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 | |
7100 | /* enum: Get current TX Driver settings */ | |
7101 | #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 | |
7102 | /* enum: Override TX Driver settings */ | |
7103 | #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 | |
7104 | /* Align the arguments to 32 bits */ | |
7105 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 | |
7106 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 | |
7107 | /* Arguments specific to the operation */ | |
7108 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 | |
7109 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 | |
7110 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 | |
7111 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 | |
7112 | ||
7113 | /* MC_CMD_PCIE_TUNE_OUT msgresponse */ | |
7114 | #define MC_CMD_PCIE_TUNE_OUT_LEN 0 | |
7115 | ||
7116 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ | |
7117 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 | |
7118 | /* Requested operation */ | |
7119 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 | |
7120 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 | |
7121 | /* Align the arguments to 32 bits */ | |
7122 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 | |
7123 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 | |
7124 | ||
7125 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ | |
7126 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 | |
7127 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 | |
7128 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
7129 | /* RXEQ Parameter */ | |
7130 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 | |
7131 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 | |
7132 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 | |
7133 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 | |
7134 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 | |
7135 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
7136 | /* enum: Attenuation (0-15) */ | |
7137 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 | |
7138 | /* enum: CTLE Boost (0-15) */ | |
7139 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 | |
7140 | /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ | |
7141 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 | |
7142 | /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7143 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 | |
7144 | /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7145 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 | |
7146 | /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7147 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 | |
7148 | /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ | |
7149 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 | |
7150 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 | |
7151 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4 | |
7152 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ | |
7153 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ | |
7154 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ | |
7155 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ | |
7156 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ | |
7157 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ | |
7158 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ | |
7159 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ | |
7160 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */ | |
7161 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 | |
7162 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12 | |
7163 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 | |
7164 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 | |
7165 | ||
7166 | /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ | |
7167 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 | |
7168 | /* Requested operation */ | |
7169 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 | |
7170 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 | |
7171 | /* Align the arguments to 32 bits */ | |
7172 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 | |
7173 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 | |
7174 | ||
7175 | /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ | |
7176 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 | |
7177 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 | |
7178 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
7179 | /* RXEQ Parameter */ | |
7180 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 | |
7181 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 | |
7182 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 | |
7183 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 | |
7184 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 | |
7185 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
7186 | /* enum: TxMargin (PIPE) */ | |
7187 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 | |
7188 | /* enum: TxSwing (PIPE) */ | |
7189 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 | |
7190 | /* enum: De-emphasis coefficient C(-1) (PIPE) */ | |
7191 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 | |
7192 | /* enum: De-emphasis coefficient C(0) (PIPE) */ | |
7193 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 | |
7194 | /* enum: De-emphasis coefficient C(+1) (PIPE) */ | |
7195 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 | |
7196 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 | |
7197 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 | |
7198 | /* Enum values, see field(s): */ | |
7199 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ | |
7200 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 | |
7201 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 | |
7202 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 | |
7203 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 | |
7204 | ||
7205 | ||
7206 | /***********************************/ | |
7207 | /* MC_CMD_LICENSING | |
7208 | * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition | |
7209 | */ | |
7210 | #define MC_CMD_LICENSING 0xf3 | |
7211 | ||
7212 | /* MC_CMD_LICENSING_IN msgrequest */ | |
7213 | #define MC_CMD_LICENSING_IN_LEN 4 | |
7214 | /* identifies the type of operation requested */ | |
7215 | #define MC_CMD_LICENSING_IN_OP_OFST 0 | |
7216 | /* enum: re-read and apply licenses after a license key partition update; note | |
7217 | * that this operation returns a zero-length response | |
7218 | */ | |
7219 | #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 | |
7220 | /* enum: report counts of installed licenses */ | |
7221 | #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 | |
7222 | ||
7223 | /* MC_CMD_LICENSING_OUT msgresponse */ | |
7224 | #define MC_CMD_LICENSING_OUT_LEN 28 | |
7225 | /* count of application keys which are valid */ | |
7226 | #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 | |
7227 | /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with | |
7228 | * MC_CMD_FC_OP_LICENSE) | |
7229 | */ | |
7230 | #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 | |
7231 | /* count of application keys which are invalid due to being blacklisted */ | |
7232 | #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 | |
7233 | /* count of application keys which are invalid due to being unverifiable */ | |
7234 | #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 | |
7235 | /* count of application keys which are invalid due to being for the wrong node | |
7236 | */ | |
7237 | #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 | |
7238 | /* licensing state (for diagnostics; the exact meaning of the bits in this | |
7239 | * field are private to the firmware) | |
7240 | */ | |
7241 | #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 | |
7242 | /* licensing subsystem self-test report (for manftest) */ | |
7243 | #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 | |
7244 | /* enum: licensing subsystem self-test failed */ | |
7245 | #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 | |
7246 | /* enum: licensing subsystem self-test passed */ | |
7247 | #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 | |
7248 | ||
7249 | ||
7250 | /***********************************/ | |
7251 | /* MC_CMD_MC2MC_PROXY | |
7252 | * Execute an arbitrary MCDI command on the slave MC of a dual-core device. | |
7253 | * This will fail on a single-core system. | |
7254 | */ | |
7255 | #define MC_CMD_MC2MC_PROXY 0xf4 | |
05a9320f | 7256 | |
5297a98d | 7257 | |
f0d37f42 | 7258 | #endif /* MCDI_PCOL_H */ |