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sfc: Do not pass non-TCP packets into GRO code
[deliverable/linux.git] / drivers / net / ethernet / sfc / nic.c
CommitLineData
8e730c15
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6 4 * Copyright 2006-2011 Solarflare Communications Inc.
8e730c15
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
a6b7a407 13#include <linux/interrupt.h>
8e730c15
BH		 14#include <linux/pci.h>
15#include <linux/module.h>
16#include <linux/seq_file.h>
17#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
21#include "regs.h"
22#include "io.h"
23#include "workarounds.h"
24
25/**************************************************************************
26 *
27 * Configurable values
28 *
29 **************************************************************************
30 */
31
32/* This is set to 16 for a good reason. In summary, if larger than
33 * 16, the descriptor cache holds more than a default socket
34 * buffer's worth of packets (for UDP we can only have at most one
35 * socket buffer's worth outstanding). This combined with the fact
36 * that we only get 1 TX event per descriptor cache means the NIC
37 * goes idle.
38 */
39#define TX_DC_ENTRIES 16
40#define TX_DC_ENTRIES_ORDER 1
41
42#define RX_DC_ENTRIES 64
43#define RX_DC_ENTRIES_ORDER 3
44
8e730c15
BH		 45/* If EFX_MAX_INT_ERRORS internal errors occur within
46 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
47 * disable it.
48 */
49#define EFX_INT_ERROR_EXPIRE 3600
50#define EFX_MAX_INT_ERRORS 5
51
8e730c15
BH		 52/* Depth of RX flush request fifo */
53#define EFX_RX_FLUSH_COUNT 4
54
4ef594eb
BH		 55/* Driver generated events */
56#define _EFX_CHANNEL_MAGIC_TEST 0x000101
57#define _EFX_CHANNEL_MAGIC_FILL 0x000102
9f2cb71c
BH		 58#define _EFX_CHANNEL_MAGIC_RX_DRAIN 0x000103
59#define _EFX_CHANNEL_MAGIC_TX_DRAIN 0x000104
d730dc52 60
4ef594eb
BH		 61#define _EFX_CHANNEL_MAGIC(_code, _data) ((_code) << 8 | (_data))
62#define _EFX_CHANNEL_MAGIC_CODE(_magic) ((_magic) >> 8)
63
64#define EFX_CHANNEL_MAGIC_TEST(_channel) \
65 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel)
2ae75dac
BH		 66#define EFX_CHANNEL_MAGIC_FILL(_rx_queue) \
67 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL, \
68 efx_rx_queue_index(_rx_queue))
9f2cb71c
BH		 69#define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue) \
70 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN, \
71 efx_rx_queue_index(_rx_queue))
72#define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue) \
73 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN, \
74 (_tx_queue)->queue)
90d683af 75
525d9e82
DP		 76static void efx_magic_event(struct efx_channel *channel, u32 magic);
77
8e730c15
BH		 78/**************************************************************************
79 *
80 * Solarstorm hardware access
81 *
82 **************************************************************************/
83
84static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
85 unsigned int index)
86{
87 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
88 value, index);
89}
90
91/* Read the current event from the event queue */
92static inline efx_qword_t *efx_event(struct efx_channel *channel,
93 unsigned int index)
94{
d4fabcc8
BH		 95 return ((efx_qword_t *) (channel->eventq.addr)) +
96 (index & channel->eventq_mask);
8e730c15
BH		 97}
98
99/* See if an event is present
100 *
101 * We check both the high and low dword of the event for all ones. We
102 * wrote all ones when we cleared the event, and no valid event can
103 * have all ones in either its high or low dwords. This approach is
104 * robust against reordering.
105 *
106 * Note that using a single 64-bit comparison is incorrect; even
107 * though the CPU read will be atomic, the DMA write may not be.
108 */
109static inline int efx_event_present(efx_qword_t *event)
110{
807540ba
ED		 111 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
112 EFX_DWORD_IS_ALL_ONES(event->dword[1]));
8e730c15
BH		 113}
114
115static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
116 const efx_oword_t *mask)
117{
118 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
119 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
120}
121
122int efx_nic_test_registers(struct efx_nic *efx,
123 const struct efx_nic_register_test *regs,
124 size_t n_regs)
125{
126 unsigned address = 0, i, j;
127 efx_oword_t mask, imask, original, reg, buf;
128
8e730c15
BH		 129 for (i = 0; i < n_regs; ++i) {
130 address = regs[i].address;
131 mask = imask = regs[i].mask;
132 EFX_INVERT_OWORD(imask);
133
134 efx_reado(efx, &original, address);
135
136 /* bit sweep on and off */
137 for (j = 0; j < 128; j++) {
138 if (!EFX_EXTRACT_OWORD32(mask, j, j))
139 continue;
140
141 /* Test this testable bit can be set in isolation */
142 EFX_AND_OWORD(reg, original, mask);
143 EFX_SET_OWORD32(reg, j, j, 1);
144
145 efx_writeo(efx, &reg, address);
146 efx_reado(efx, &buf, address);
147
148 if (efx_masked_compare_oword(&reg, &buf, &mask))
149 goto fail;
150
151 /* Test this testable bit can be cleared in isolation */
152 EFX_OR_OWORD(reg, original, mask);
153 EFX_SET_OWORD32(reg, j, j, 0);
154
155 efx_writeo(efx, &reg, address);
156 efx_reado(efx, &buf, address);
157
158 if (efx_masked_compare_oword(&reg, &buf, &mask))
159 goto fail;
160 }
161
162 efx_writeo(efx, &original, address);
163 }
164
165 return 0;
166
167fail:
62776d03
BH		 168 netif_err(efx, hw, efx->net_dev,
169 "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
170 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
171 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
8e730c15
BH		 172 return -EIO;
173}
174
175/**************************************************************************
176 *
177 * Special buffer handling
178 * Special buffers are used for event queues and the TX and RX
179 * descriptor rings.
180 *
181 *************************************************************************/
182
183/*
184 * Initialise a special buffer
185 *
186 * This will define a buffer (previously allocated via
187 * efx_alloc_special_buffer()) in the buffer table, allowing
188 * it to be used for event queues, descriptor rings etc.
189 */
190static void
191efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
192{
193 efx_qword_t buf_desc;
5bbe2f4f 194 unsigned int index;
8e730c15
BH		 195 dma_addr_t dma_addr;
196 int i;
197
198 EFX_BUG_ON_PARANOID(!buffer->addr);
199
200 /* Write buffer descriptors to NIC */
201 for (i = 0; i < buffer->entries; i++) {
202 index = buffer->index + i;
5b6262d0 203 dma_addr = buffer->dma_addr + (i * EFX_BUF_SIZE);
62776d03
BH		 204 netif_dbg(efx, probe, efx->net_dev,
205 "mapping special buffer %d at %llx\n",
206 index, (unsigned long long)dma_addr);
8e730c15
BH		 207 EFX_POPULATE_QWORD_3(buf_desc,
208 FRF_AZ_BUF_ADR_REGION, 0,
209 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
210 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
211 efx_write_buf_tbl(efx, &buf_desc, index);
212 }
213}
214
215/* Unmaps a buffer and clears the buffer table entries */
216static void
217efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
218{
219 efx_oword_t buf_tbl_upd;
220 unsigned int start = buffer->index;
221 unsigned int end = (buffer->index + buffer->entries - 1);
222
223 if (!buffer->entries)
224 return;
225
62776d03
BH		 226 netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
227 buffer->index, buffer->index + buffer->entries - 1);
8e730c15
BH		 228
229 EFX_POPULATE_OWORD_4(buf_tbl_upd,
230 FRF_AZ_BUF_UPD_CMD, 0,
231 FRF_AZ_BUF_CLR_CMD, 1,
232 FRF_AZ_BUF_CLR_END_ID, end,
233 FRF_AZ_BUF_CLR_START_ID, start);
234 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
235}
236
237/*
238 * Allocate a new special buffer
239 *
240 * This allocates memory for a new buffer, clears it and allocates a
241 * new buffer ID range. It does not write into the buffer table.
242 *
243 * This call will allocate 4KB buffers, since 8KB buffers can't be
244 * used for event queues and descriptor rings.
245 */
246static int efx_alloc_special_buffer(struct efx_nic *efx,
247 struct efx_special_buffer *buffer,
248 unsigned int len)
249{
250 len = ALIGN(len, EFX_BUF_SIZE);
251
58758aa5
BH		 252 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
253 &buffer->dma_addr, GFP_KERNEL);
8e730c15
BH		 254 if (!buffer->addr)
255 return -ENOMEM;
256 buffer->len = len;
257 buffer->entries = len / EFX_BUF_SIZE;
258 BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1));
259
8e730c15
BH		 260 /* Select new buffer ID */
261 buffer->index = efx->next_buffer_table;
262 efx->next_buffer_table += buffer->entries;
cd2d5b52
BH		 263#ifdef CONFIG_SFC_SRIOV
264 BUG_ON(efx_sriov_enabled(efx) &&
265 efx->vf_buftbl_base < efx->next_buffer_table);
266#endif
8e730c15 267
62776d03
BH		 268 netif_dbg(efx, probe, efx->net_dev,
269 "allocating special buffers %d-%d at %llx+%x "
270 "(virt %p phys %llx)\n", buffer->index,
271 buffer->index + buffer->entries - 1,
272 (u64)buffer->dma_addr, len,
273 buffer->addr, (u64)virt_to_phys(buffer->addr));
8e730c15
BH		 274
275 return 0;
276}
277
278static void
279efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
280{
281 if (!buffer->addr)
282 return;
283
62776d03
BH		 284 netif_dbg(efx, hw, efx->net_dev,
285 "deallocating special buffers %d-%d at %llx+%x "
286 "(virt %p phys %llx)\n", buffer->index,
287 buffer->index + buffer->entries - 1,
288 (u64)buffer->dma_addr, buffer->len,
289 buffer->addr, (u64)virt_to_phys(buffer->addr));
8e730c15 290
58758aa5
BH		 291 dma_free_coherent(&efx->pci_dev->dev, buffer->len, buffer->addr,
292 buffer->dma_addr);
8e730c15
BH		 293 buffer->addr = NULL;
294 buffer->entries = 0;
295}
296
297/**************************************************************************
298 *
299 * Generic buffer handling
f7251a9c 300 * These buffers are used for interrupt status, MAC stats, etc.
8e730c15
BH		 301 *
302 **************************************************************************/
303
304int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
305 unsigned int len)
306{
0e33d870 307 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
1f9061d2
JP		 308 &buffer->dma_addr,
309 GFP_ATOMIC | __GFP_ZERO);
8e730c15
BH		 310 if (!buffer->addr)
311 return -ENOMEM;
312 buffer->len = len;
8e730c15
BH		 313 return 0;
314}
315
316void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
317{
318 if (buffer->addr) {
0e33d870
BH		 319 dma_free_coherent(&efx->pci_dev->dev, buffer->len,
320 buffer->addr, buffer->dma_addr);
8e730c15
BH		 321 buffer->addr = NULL;
322 }
323}
324
325/**************************************************************************
326 *
327 * TX path
328 *
329 **************************************************************************/
330
331/* Returns a pointer to the specified transmit descriptor in the TX
332 * descriptor queue belonging to the specified channel.
333 */
334static inline efx_qword_t *
335efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
336{
807540ba 337 return ((efx_qword_t *) (tx_queue->txd.addr)) + index;
8e730c15
BH		 338}
339
340/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
341static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue)
342{
343 unsigned write_ptr;
344 efx_dword_t reg;
345
ecc910f5 346 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
8e730c15
BH		 347 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
348 efx_writed_page(tx_queue->efx, &reg,
349 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
350}
351
cd38557d
BH		 352/* Write pointer and first descriptor for TX descriptor ring */
353static inline void efx_push_tx_desc(struct efx_tx_queue *tx_queue,
354 const efx_qword_t *txd)
355{
356 unsigned write_ptr;
357 efx_oword_t reg;
358
359 BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
360 BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
361
362 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
363 EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
364 FRF_AZ_TX_DESC_WPTR, write_ptr);
365 reg.qword[0] = *txd;
366 efx_writeo_page(tx_queue->efx, &reg,
367 FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
368}
369
370static inline bool
371efx_may_push_tx_desc(struct efx_tx_queue *tx_queue, unsigned int write_count)
372{
373 unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
374
375 if (empty_read_count == 0)
376 return false;
377
378 tx_queue->empty_read_count = 0;
fae8563b
BH		 379 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0
380 && tx_queue->write_count - write_count == 1;
cd38557d 381}
8e730c15
BH		 382
383/* For each entry inserted into the software descriptor ring, create a
384 * descriptor in the hardware TX descriptor ring (in host memory), and
385 * write a doorbell.
386 */
387void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
388{
389
390 struct efx_tx_buffer *buffer;
391 efx_qword_t *txd;
392 unsigned write_ptr;
cd38557d 393 unsigned old_write_count = tx_queue->write_count;
8e730c15
BH		 394
395 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
396
397 do {
ecc910f5 398 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
8e730c15
BH		 399 buffer = &tx_queue->buffer[write_ptr];
400 txd = efx_tx_desc(tx_queue, write_ptr);
401 ++tx_queue->write_count;
402
403 /* Create TX descriptor ring entry */
7668ff9c 404 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
8e730c15 405 EFX_POPULATE_QWORD_4(*txd,
7668ff9c
BH		 406 FSF_AZ_TX_KER_CONT,
407 buffer->flags & EFX_TX_BUF_CONT,
8e730c15
BH		 408 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
409 FSF_AZ_TX_KER_BUF_REGION, 0,
410 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
411 } while (tx_queue->write_count != tx_queue->insert_count);
412
413 wmb(); /* Ensure descriptors are written before they are fetched */
cd38557d
BH		 414
415 if (efx_may_push_tx_desc(tx_queue, old_write_count)) {
416 txd = efx_tx_desc(tx_queue,
417 old_write_count & tx_queue->ptr_mask);
418 efx_push_tx_desc(tx_queue, txd);
419 ++tx_queue->pushes;
420 } else {
421 efx_notify_tx_desc(tx_queue);
422 }
8e730c15
BH		 423}
424
425/* Allocate hardware resources for a TX queue */
426int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
427{
428 struct efx_nic *efx = tx_queue->efx;
ecc910f5
SH		 429 unsigned entries;
430
431 entries = tx_queue->ptr_mask + 1;
8e730c15 432 return efx_alloc_special_buffer(efx, &tx_queue->txd,
ecc910f5 433 entries * sizeof(efx_qword_t));
8e730c15
BH		 434}
435
436void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
437{
8e730c15 438 struct efx_nic *efx = tx_queue->efx;
94b274bf 439 efx_oword_t reg;
8e730c15 440
8e730c15
BH		 441 /* Pin TX descriptor ring */
442 efx_init_special_buffer(efx, &tx_queue->txd);
443
444 /* Push TX descriptor ring to card */
94b274bf 445 EFX_POPULATE_OWORD_10(reg,
8e730c15
BH		 446 FRF_AZ_TX_DESCQ_EN, 1,
447 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
448 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
449 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
450 FRF_AZ_TX_DESCQ_EVQ_ID,
451 tx_queue->channel->channel,
452 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
453 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
454 FRF_AZ_TX_DESCQ_SIZE,
455 __ffs(tx_queue->txd.entries),
456 FRF_AZ_TX_DESCQ_TYPE, 0,
457 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
458
459 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
a4900ac9 460 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
94b274bf
BH		 461 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
462 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS,
8e730c15
BH		 463 !csum);
464 }
465
94b274bf 466 efx_writeo_table(efx, &reg, efx->type->txd_ptr_tbl_base,
8e730c15
BH		 467 tx_queue->queue);
468
469 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
8e730c15 470 /* Only 128 bits in this register */
a4900ac9 471 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
8e730c15
BH		 472
473 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
a4900ac9 474 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
32766ec8 475 __clear_bit_le(tx_queue->queue, &reg);
8e730c15 476 else
32766ec8 477 __set_bit_le(tx_queue->queue, &reg);
8e730c15
BH		 478 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
479 }
94b274bf
BH		 480
481 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
482 EFX_POPULATE_OWORD_1(reg,
483 FRF_BZ_TX_PACE,
484 (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
485 FFE_BZ_TX_PACE_OFF :
486 FFE_BZ_TX_PACE_RESERVED);
487 efx_writeo_table(efx, &reg, FR_BZ_TX_PACE_TBL,
488 tx_queue->queue);
489 }
8e730c15
BH		 490}
491
492static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue)
493{
494 struct efx_nic *efx = tx_queue->efx;
495 efx_oword_t tx_flush_descq;
496
525d9e82
DP		 497 WARN_ON(atomic_read(&tx_queue->flush_outstanding));
498 atomic_set(&tx_queue->flush_outstanding, 1);
499
8e730c15
BH		 500 EFX_POPULATE_OWORD_2(tx_flush_descq,
501 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
502 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
503 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
504}
505
506void efx_nic_fini_tx(struct efx_tx_queue *tx_queue)
507{
508 struct efx_nic *efx = tx_queue->efx;
509 efx_oword_t tx_desc_ptr;
510
8e730c15
BH		 511 /* Remove TX descriptor ring from card */
512 EFX_ZERO_OWORD(tx_desc_ptr);
513 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
514 tx_queue->queue);
515
516 /* Unpin TX descriptor ring */
517 efx_fini_special_buffer(efx, &tx_queue->txd);
518}
519
520/* Free buffers backing TX queue */
521void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
522{
523 efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
524}
525
526/**************************************************************************
527 *
528 * RX path
529 *
530 **************************************************************************/
531
532/* Returns a pointer to the specified descriptor in the RX descriptor queue */
533static inline efx_qword_t *
534efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
535{
807540ba 536 return ((efx_qword_t *) (rx_queue->rxd.addr)) + index;
8e730c15
BH		 537}
538
539/* This creates an entry in the RX descriptor queue */
540static inline void
541efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
542{
543 struct efx_rx_buffer *rx_buf;
544 efx_qword_t *rxd;
545
546 rxd = efx_rx_desc(rx_queue, index);
547 rx_buf = efx_rx_buffer(rx_queue, index);
548 EFX_POPULATE_QWORD_3(*rxd,
549 FSF_AZ_RX_KER_BUF_SIZE,
550 rx_buf->len -
551 rx_queue->efx->type->rx_buffer_padding,
552 FSF_AZ_RX_KER_BUF_REGION, 0,
553 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
554}
555
556/* This writes to the RX_DESC_WPTR register for the specified receive
557 * descriptor ring.
558 */
559void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
560{
ecc910f5 561 struct efx_nic *efx = rx_queue->efx;
8e730c15
BH		 562 efx_dword_t reg;
563 unsigned write_ptr;
564
565 while (rx_queue->notified_count != rx_queue->added_count) {
ecc910f5
SH		 566 efx_build_rx_desc(
567 rx_queue,
568 rx_queue->notified_count & rx_queue->ptr_mask);
8e730c15
BH		 569 ++rx_queue->notified_count;
570 }
571
572 wmb();
ecc910f5 573 write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
8e730c15 574 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
ecc910f5 575 efx_writed_page(efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
ba1e8a35 576 efx_rx_queue_index(rx_queue));
8e730c15
BH		 577}
578
579int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
580{
581 struct efx_nic *efx = rx_queue->efx;
ecc910f5
SH		 582 unsigned entries;
583
584 entries = rx_queue->ptr_mask + 1;
8e730c15 585 return efx_alloc_special_buffer(efx, &rx_queue->rxd,
ecc910f5 586 entries * sizeof(efx_qword_t));
8e730c15
BH		 587}
588
589void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
590{
591 efx_oword_t rx_desc_ptr;
592 struct efx_nic *efx = rx_queue->efx;
593 bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
594 bool iscsi_digest_en = is_b0;
85740cdf
BH		 595 bool jumbo_en;
596
597 /* For kernel-mode queues in Falcon A1, the JUMBO flag enables
598 * DMA to continue after a PCIe page boundary (and scattering
599 * is not possible). In Falcon B0 and Siena, it enables
600 * scatter.
601 */
602 jumbo_en = !is_b0 || efx->rx_scatter;
8e730c15 603
62776d03
BH		 604 netif_dbg(efx, hw, efx->net_dev,
605 "RX queue %d ring in special buffers %d-%d\n",
ba1e8a35 606 efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
62776d03 607 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
8e730c15 608
85740cdf
BH		 609 rx_queue->scatter_n = 0;
610
8e730c15
BH		 611 /* Pin RX descriptor ring */
612 efx_init_special_buffer(efx, &rx_queue->rxd);
613
614 /* Push RX descriptor ring to card */
615 EFX_POPULATE_OWORD_10(rx_desc_ptr,
616 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
617 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
618 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
619 FRF_AZ_RX_DESCQ_EVQ_ID,
ba1e8a35 620 efx_rx_queue_channel(rx_queue)->channel,
8e730c15 621 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
ba1e8a35
BH		 622 FRF_AZ_RX_DESCQ_LABEL,
623 efx_rx_queue_index(rx_queue),
8e730c15
BH		 624 FRF_AZ_RX_DESCQ_SIZE,
625 __ffs(rx_queue->rxd.entries),
626 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
85740cdf 627 FRF_AZ_RX_DESCQ_JUMBO, jumbo_en,
8e730c15
BH		 628 FRF_AZ_RX_DESCQ_EN, 1);
629 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
ba1e8a35 630 efx_rx_queue_index(rx_queue));
8e730c15
BH		 631}
632
633static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue)
634{
635 struct efx_nic *efx = rx_queue->efx;
636 efx_oword_t rx_flush_descq;
637
8e730c15
BH		 638 EFX_POPULATE_OWORD_2(rx_flush_descq,
639 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
ba1e8a35
BH		 640 FRF_AZ_RX_FLUSH_DESCQ,
641 efx_rx_queue_index(rx_queue));
8e730c15
BH		 642 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
643}
644
645void efx_nic_fini_rx(struct efx_rx_queue *rx_queue)
646{
647 efx_oword_t rx_desc_ptr;
648 struct efx_nic *efx = rx_queue->efx;
649
8e730c15
BH		 650 /* Remove RX descriptor ring from card */
651 EFX_ZERO_OWORD(rx_desc_ptr);
652 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
ba1e8a35 653 efx_rx_queue_index(rx_queue));
8e730c15
BH		 654
655 /* Unpin RX descriptor ring */
656 efx_fini_special_buffer(efx, &rx_queue->rxd);
657}
658
659/* Free buffers backing RX queue */
660void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
661{
662 efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
663}
664
9f2cb71c
BH		 665/**************************************************************************
666 *
667 * Flush handling
668 *
669 **************************************************************************/
670
671/* efx_nic_flush_queues() must be woken up when all flushes are completed,
672 * or more RX flushes can be kicked off.
673 */
674static bool efx_flush_wake(struct efx_nic *efx)
675{
676 /* Ensure that all updates are visible to efx_nic_flush_queues() */
677 smp_mb();
678
679 return (atomic_read(&efx->drain_pending) == 0 ||
680 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT
681 && atomic_read(&efx->rxq_flush_pending) > 0));
682}
683
525d9e82
DP		 684static bool efx_check_tx_flush_complete(struct efx_nic *efx)
685{
686 bool i = true;
687 efx_oword_t txd_ptr_tbl;
688 struct efx_channel *channel;
689 struct efx_tx_queue *tx_queue;
690
691 efx_for_each_channel(channel, efx) {
692 efx_for_each_channel_tx_queue(tx_queue, channel) {
693 efx_reado_table(efx, &txd_ptr_tbl,
694 FR_BZ_TX_DESC_PTR_TBL, tx_queue->queue);
695 if (EFX_OWORD_FIELD(txd_ptr_tbl,
696 FRF_AZ_TX_DESCQ_FLUSH) ||
697 EFX_OWORD_FIELD(txd_ptr_tbl,
698 FRF_AZ_TX_DESCQ_EN)) {
699 netif_dbg(efx, hw, efx->net_dev,
700 "flush did not complete on TXQ %d\n",
701 tx_queue->queue);
702 i = false;
703 } else if (atomic_cmpxchg(&tx_queue->flush_outstanding,
704 1, 0)) {
705 /* The flush is complete, but we didn't
706 * receive a flush completion event
707 */
708 netif_dbg(efx, hw, efx->net_dev,
709 "flush complete on TXQ %d, so drain "
710 "the queue\n", tx_queue->queue);
711 /* Don't need to increment drain_pending as it
712 * has already been incremented for the queues
713 * which did not drain
714 */
715 efx_magic_event(channel,
716 EFX_CHANNEL_MAGIC_TX_DRAIN(
717 tx_queue));
718 }
719 }
720 }
721
722 return i;
723}
724
9f2cb71c
BH		 725/* Flush all the transmit queues, and continue flushing receive queues until
726 * they're all flushed. Wait for the DRAIN events to be recieved so that there
727 * are no more RX and TX events left on any channel. */
728int efx_nic_flush_queues(struct efx_nic *efx)
729{
730 unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */
731 struct efx_channel *channel;
732 struct efx_rx_queue *rx_queue;
733 struct efx_tx_queue *tx_queue;
734 int rc = 0;
735
736 efx->type->prepare_flush(efx);
737
738 efx_for_each_channel(channel, efx) {
739 efx_for_each_channel_tx_queue(tx_queue, channel) {
740 atomic_inc(&efx->drain_pending);
741 efx_flush_tx_queue(tx_queue);
742 }
743 efx_for_each_channel_rx_queue(rx_queue, channel) {
744 atomic_inc(&efx->drain_pending);
745 rx_queue->flush_pending = true;
746 atomic_inc(&efx->rxq_flush_pending);
747 }
748 }
749
750 while (timeout && atomic_read(&efx->drain_pending) > 0) {
cd2d5b52
BH		 751 /* If SRIOV is enabled, then offload receive queue flushing to
752 * the firmware (though we will still have to poll for
753 * completion). If that fails, fall back to the old scheme.
754 */
755 if (efx_sriov_enabled(efx)) {
756 rc = efx_mcdi_flush_rxqs(efx);
757 if (!rc)
758 goto wait;
759 }
760
9f2cb71c
BH		 761 /* The hardware supports four concurrent rx flushes, each of
762 * which may need to be retried if there is an outstanding
763 * descriptor fetch
764 */
765 efx_for_each_channel(channel, efx) {
766 efx_for_each_channel_rx_queue(rx_queue, channel) {
767 if (atomic_read(&efx->rxq_flush_outstanding) >=
768 EFX_RX_FLUSH_COUNT)
769 break;
770
771 if (rx_queue->flush_pending) {
772 rx_queue->flush_pending = false;
773 atomic_dec(&efx->rxq_flush_pending);
774 atomic_inc(&efx->rxq_flush_outstanding);
775 efx_flush_rx_queue(rx_queue);
776 }
777 }
778 }
779
cd2d5b52 780 wait:
9f2cb71c
BH		 781 timeout = wait_event_timeout(efx->flush_wq, efx_flush_wake(efx),
782 timeout);
783 }
784
525d9e82
DP		 785 if (atomic_read(&efx->drain_pending) &&
786 !efx_check_tx_flush_complete(efx)) {
9f2cb71c
BH		 787 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues "
788 "(rx %d+%d)\n", atomic_read(&efx->drain_pending),
789 atomic_read(&efx->rxq_flush_outstanding),
790 atomic_read(&efx->rxq_flush_pending));
791 rc = -ETIMEDOUT;
792
793 atomic_set(&efx->drain_pending, 0);
794 atomic_set(&efx->rxq_flush_pending, 0);
795 atomic_set(&efx->rxq_flush_outstanding, 0);
796 }
797
d5e8cc6c 798 efx->type->finish_flush(efx);
a606f432 799
9f2cb71c
BH		 800 return rc;
801}
802
8e730c15
BH		 803/**************************************************************************
804 *
805 * Event queue processing
806 * Event queues are processed by per-channel tasklets.
807 *
808 **************************************************************************/
809
810/* Update a channel's event queue's read pointer (RPTR) register
811 *
812 * This writes the EVQ_RPTR_REG register for the specified channel's
813 * event queue.
8e730c15
BH		 814 */
815void efx_nic_eventq_read_ack(struct efx_channel *channel)
816{
817 efx_dword_t reg;
818 struct efx_nic *efx = channel->efx;
819
d4fabcc8
BH		 820 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR,
821 channel->eventq_read_ptr & channel->eventq_mask);
778cdaf6
BH		 822
823 /* For Falcon A1, EVQ_RPTR_KER is documented as having a step size
824 * of 4 bytes, but it is really 16 bytes just like later revisions.
825 */
826 efx_writed(efx, &reg,
827 efx->type->evq_rptr_tbl_base +
828 FR_BZ_EVQ_RPTR_STEP * channel->channel);
8e730c15
BH		 829}
830
831/* Use HW to insert a SW defined event */
90893000
BH		 832void efx_generate_event(struct efx_nic *efx, unsigned int evq,
833 efx_qword_t *event)
8e730c15
BH		 834{
835 efx_oword_t drv_ev_reg;
836
837 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
838 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
839 drv_ev_reg.u32[0] = event->u32[0];
840 drv_ev_reg.u32[1] = event->u32[1];
841 drv_ev_reg.u32[2] = 0;
842 drv_ev_reg.u32[3] = 0;
90893000
BH		 843 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq);
844 efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV);
8e730c15
BH		 845}
846
4ef594eb
BH		 847static void efx_magic_event(struct efx_channel *channel, u32 magic)
848{
849 efx_qword_t event;
850
851 EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE,
852 FSE_AZ_EV_CODE_DRV_GEN_EV,
853 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
90893000 854 efx_generate_event(channel->efx, channel->channel, &event);
4ef594eb
BH		 855}
856
8e730c15
BH		 857/* Handle a transmit completion event
858 *
859 * The NIC batches TX completion events; the message we receive is of
860 * the form "complete all TX events up to this index".
861 */
fa236e18 862static int
8e730c15
BH		 863efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
864{
865 unsigned int tx_ev_desc_ptr;
866 unsigned int tx_ev_q_label;
867 struct efx_tx_queue *tx_queue;
868 struct efx_nic *efx = channel->efx;
fa236e18 869 int tx_packets = 0;
8e730c15 870
9f2cb71c
BH		 871 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
872 return 0;
873
8e730c15
BH		 874 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
875 /* Transmit completion */
876 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
877 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
f7d12cdc
BH		 878 tx_queue = efx_channel_get_tx_queue(
879 channel, tx_ev_q_label % EFX_TXQ_TYPES);
fa236e18 880 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
ecc910f5 881 tx_queue->ptr_mask);
8e730c15
BH		 882 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
883 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
884 /* Rewrite the FIFO write pointer */
885 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
f7d12cdc
BH		 886 tx_queue = efx_channel_get_tx_queue(
887 channel, tx_ev_q_label % EFX_TXQ_TYPES);
8e730c15 888
73ba7b68 889 netif_tx_lock(efx->net_dev);
8e730c15 890 efx_notify_tx_desc(tx_queue);
73ba7b68 891 netif_tx_unlock(efx->net_dev);
8e730c15
BH		 892 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
893 EFX_WORKAROUND_10727(efx)) {
894 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
895 } else {
62776d03
BH		 896 netif_err(efx, tx_err, efx->net_dev,
897 "channel %d unexpected TX event "
898 EFX_QWORD_FMT"\n", channel->channel,
899 EFX_QWORD_VAL(*event));
8e730c15 900 }
fa236e18
BH		 901
902 return tx_packets;
8e730c15
BH		 903}
904
905/* Detect errors included in the rx_evt_pkt_ok bit. */
db339569
BH		 906static u16 efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
907 const efx_qword_t *event)
8e730c15 908{
ba1e8a35 909 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
8e730c15
BH		 910 struct efx_nic *efx = rx_queue->efx;
911 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
912 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
913 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
914 bool rx_ev_other_err, rx_ev_pause_frm;
915 bool rx_ev_hdr_type, rx_ev_mcast_pkt;
916 unsigned rx_ev_pkt_type;
917
918 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
919 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
920 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
921 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
922 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
923 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
924 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
925 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
926 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
927 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
928 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
929 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
930 rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
931 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
932 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
933
934 /* Every error apart from tobe_disc and pause_frm */
935 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
936 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
937 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
938
939 /* Count errors that are not in MAC stats. Ignore expected
940 * checksum errors during self-test. */
941 if (rx_ev_frm_trunc)
ba1e8a35 942 ++channel->n_rx_frm_trunc;
8e730c15 943 else if (rx_ev_tobe_disc)
ba1e8a35 944 ++channel->n_rx_tobe_disc;
8e730c15
BH		 945 else if (!efx->loopback_selftest) {
946 if (rx_ev_ip_hdr_chksum_err)
ba1e8a35 947 ++channel->n_rx_ip_hdr_chksum_err;
8e730c15 948 else if (rx_ev_tcp_udp_chksum_err)
ba1e8a35 949 ++channel->n_rx_tcp_udp_chksum_err;
8e730c15
BH		 950 }
951
8e730c15
BH		 952 /* TOBE_DISC is expected on unicast mismatches; don't print out an
953 * error message. FRM_TRUNC indicates RXDP dropped the packet due
954 * to a FIFO overflow.
955 */
5f3f9d6c 956#ifdef DEBUG
62776d03
BH		 957 if (rx_ev_other_err && net_ratelimit()) {
958 netif_dbg(efx, rx_err, efx->net_dev,
959 " RX queue %d unexpected RX event "
960 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
ba1e8a35 961 efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
62776d03
BH		 962 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
963 rx_ev_ip_hdr_chksum_err ?
964 " [IP_HDR_CHKSUM_ERR]" : "",
965 rx_ev_tcp_udp_chksum_err ?
966 " [TCP_UDP_CHKSUM_ERR]" : "",
967 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
968 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
969 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
970 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
971 rx_ev_pause_frm ? " [PAUSE]" : "");
8e730c15
BH		 972 }
973#endif
db339569
BH		 974
975 /* The frame must be discarded if any of these are true. */
976 return (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
977 rx_ev_tobe_disc | rx_ev_pause_frm) ?
978 EFX_RX_PKT_DISCARD : 0;
8e730c15
BH		 979}
980
85740cdf
BH		 981/* Handle receive events that are not in-order. Return true if this
982 * can be handled as a partial packet discard, false if it's more
983 * serious.
984 */
985static bool
8e730c15
BH		 986efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
987{
85740cdf 988 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
8e730c15
BH		 989 struct efx_nic *efx = rx_queue->efx;
990 unsigned expected, dropped;
991
85740cdf
BH		 992 if (rx_queue->scatter_n &&
993 index == ((rx_queue->removed_count + rx_queue->scatter_n - 1) &
994 rx_queue->ptr_mask)) {
995 ++channel->n_rx_nodesc_trunc;
996 return true;
997 }
998
ecc910f5
SH		 999 expected = rx_queue->removed_count & rx_queue->ptr_mask;
1000 dropped = (index - expected) & rx_queue->ptr_mask;
62776d03
BH		 1001 netif_info(efx, rx_err, efx->net_dev,
1002 "dropped %d events (index=%d expected=%d)\n",
1003 dropped, index, expected);
8e730c15
BH		 1004
1005 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
1006 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
85740cdf 1007 return false;
8e730c15
BH		 1008}
1009
1010/* Handle a packet received event
1011 *
1012 * The NIC gives a "discard" flag if it's a unicast packet with the
1013 * wrong destination address
1014 * Also "is multicast" and "matches multicast filter" flags can be used to
1015 * discard non-matching multicast packets.
1016 */
1017static void
1018efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
1019{
1020 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
1021 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
1022 unsigned expected_ptr;
85740cdf 1023 bool rx_ev_pkt_ok, rx_ev_sop, rx_ev_cont;
db339569 1024 u16 flags;
8e730c15 1025 struct efx_rx_queue *rx_queue;
9f2cb71c
BH		 1026 struct efx_nic *efx = channel->efx;
1027
1028 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1029 return;
8e730c15 1030
85740cdf
BH		 1031 rx_ev_cont = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT);
1032 rx_ev_sop = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP);
8e730c15
BH		 1033 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
1034 channel->channel);
1035
f7d12cdc 1036 rx_queue = efx_channel_get_rx_queue(channel);
8e730c15
BH		 1037
1038 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
85740cdf
BH		 1039 expected_ptr = ((rx_queue->removed_count + rx_queue->scatter_n) &
1040 rx_queue->ptr_mask);
1041
1042 /* Check for partial drops and other errors */
1043 if (unlikely(rx_ev_desc_ptr != expected_ptr) ||
1044 unlikely(rx_ev_sop != (rx_queue->scatter_n == 0))) {
1045 if (rx_ev_desc_ptr != expected_ptr &&
1046 !efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr))
1047 return;
1048
1049 /* Discard all pending fragments */
1050 if (rx_queue->scatter_n) {
1051 efx_rx_packet(
1052 rx_queue,
1053 rx_queue->removed_count & rx_queue->ptr_mask,
1054 rx_queue->scatter_n, 0, EFX_RX_PKT_DISCARD);
1055 rx_queue->removed_count += rx_queue->scatter_n;
1056 rx_queue->scatter_n = 0;
1057 }
1058
1059 /* Return if there is no new fragment */
1060 if (rx_ev_desc_ptr != expected_ptr)
1061 return;
1062
1063 /* Discard new fragment if not SOP */
1064 if (!rx_ev_sop) {
1065 efx_rx_packet(
1066 rx_queue,
1067 rx_queue->removed_count & rx_queue->ptr_mask,
1068 1, 0, EFX_RX_PKT_DISCARD);
1069 ++rx_queue->removed_count;
1070 return;
1071 }
1072 }
1073
1074 ++rx_queue->scatter_n;
1075 if (rx_ev_cont)
1076 return;
1077
1078 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
1079 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
1080 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
8e730c15
BH		 1081
1082 if (likely(rx_ev_pkt_ok)) {
d07df8ec
BH		 1083 /* If packet is marked as OK then we can rely on the
1084 * hardware checksum and classification.
8e730c15 1085 */
d07df8ec
BH		 1086 flags = 0;
1087 switch (rx_ev_hdr_type) {
1088 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
1089 flags |= EFX_RX_PKT_TCP;
1090 /* fall through */
1091 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
1092 flags |= EFX_RX_PKT_CSUMMED;
1093 /* fall through */
1094 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
1095 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
1096 break;
1097 }
8e730c15 1098 } else {
db339569 1099 flags = efx_handle_rx_not_ok(rx_queue, event);
8e730c15
BH		 1100 }
1101
1102 /* Detect multicast packets that didn't match the filter */
1103 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
1104 if (rx_ev_mcast_pkt) {
1105 unsigned int rx_ev_mcast_hash_match =
1106 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
1107
1108 if (unlikely(!rx_ev_mcast_hash_match)) {
1109 ++channel->n_rx_mcast_mismatch;
db339569 1110 flags |= EFX_RX_PKT_DISCARD;
8e730c15
BH		 1111 }
1112 }
1113
1114 channel->irq_mod_score += 2;
1115
1116 /* Handle received packet */
85740cdf
BH		 1117 efx_rx_packet(rx_queue,
1118 rx_queue->removed_count & rx_queue->ptr_mask,
1119 rx_queue->scatter_n, rx_ev_byte_cnt, flags);
1120 rx_queue->removed_count += rx_queue->scatter_n;
1121 rx_queue->scatter_n = 0;
8e730c15
BH		 1122}
1123
9f2cb71c
BH		 1124/* If this flush done event corresponds to a &struct efx_tx_queue, then
1125 * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue
1126 * of all transmit completions.
1127 */
1128static void
1129efx_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1130{
1131 struct efx_tx_queue *tx_queue;
1132 int qid;
1133
1134 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1135 if (qid < EFX_TXQ_TYPES * efx->n_tx_channels) {
1136 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES,
1137 qid % EFX_TXQ_TYPES);
525d9e82
DP		 1138 if (atomic_cmpxchg(&tx_queue->flush_outstanding, 1, 0)) {
1139 efx_magic_event(tx_queue->channel,
1140 EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue));
1141 }
9f2cb71c
BH		 1142 }
1143}
1144
1145/* If this flush done event corresponds to a &struct efx_rx_queue: If the flush
1146 * was succesful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
1147 * the RX queue back to the mask of RX queues in need of flushing.
1148 */
1149static void
1150efx_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1151{
1152 struct efx_channel *channel;
1153 struct efx_rx_queue *rx_queue;
1154 int qid;
1155 bool failed;
1156
1157 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1158 failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1159 if (qid >= efx->n_channels)
1160 return;
1161 channel = efx_get_channel(efx, qid);
1162 if (!efx_channel_has_rx_queue(channel))
1163 return;
1164 rx_queue = efx_channel_get_rx_queue(channel);
1165
1166 if (failed) {
1167 netif_info(efx, hw, efx->net_dev,
1168 "RXQ %d flush retry\n", qid);
1169 rx_queue->flush_pending = true;
1170 atomic_inc(&efx->rxq_flush_pending);
1171 } else {
1172 efx_magic_event(efx_rx_queue_channel(rx_queue),
1173 EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue));
1174 }
1175 atomic_dec(&efx->rxq_flush_outstanding);
1176 if (efx_flush_wake(efx))
1177 wake_up(&efx->flush_wq);
1178}
1179
1180static void
1181efx_handle_drain_event(struct efx_channel *channel)
1182{
1183 struct efx_nic *efx = channel->efx;
1184
1185 WARN_ON(atomic_read(&efx->drain_pending) == 0);
1186 atomic_dec(&efx->drain_pending);
1187 if (efx_flush_wake(efx))
1188 wake_up(&efx->flush_wq);
1189}
1190
90d683af
SH		 1191static void
1192efx_handle_generated_event(struct efx_channel *channel, efx_qword_t *event)
1193{
1194 struct efx_nic *efx = channel->efx;
2ae75dac
BH		 1195 struct efx_rx_queue *rx_queue =
1196 efx_channel_has_rx_queue(channel) ?
1197 efx_channel_get_rx_queue(channel) : NULL;
9f2cb71c 1198 unsigned magic, code;
90d683af 1199
4ef594eb 1200 magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
9f2cb71c 1201 code = _EFX_CHANNEL_MAGIC_CODE(magic);
4ef594eb 1202
9f2cb71c 1203 if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) {
dd40781e 1204 channel->event_test_cpu = raw_smp_processor_id();
9f2cb71c 1205 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) {
90d683af
SH		 1206 /* The queue must be empty, so we won't receive any rx
1207 * events, so efx_process_channel() won't refill the
1208 * queue. Refill it here */
2ae75dac 1209 efx_fast_push_rx_descriptors(rx_queue);
9f2cb71c
BH		 1210 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) {
1211 rx_queue->enabled = false;
1212 efx_handle_drain_event(channel);
1213 } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) {
1214 efx_handle_drain_event(channel);
1215 } else {
62776d03
BH		 1216 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
1217 "generated event "EFX_QWORD_FMT"\n",
1218 channel->channel, EFX_QWORD_VAL(*event));
9f2cb71c 1219 }
90d683af
SH		 1220}
1221
8e730c15
BH		 1222static void
1223efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1224{
1225 struct efx_nic *efx = channel->efx;
1226 unsigned int ev_sub_code;
1227 unsigned int ev_sub_data;
1228
1229 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
1230 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1231
1232 switch (ev_sub_code) {
1233 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
62776d03
BH		 1234 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
1235 channel->channel, ev_sub_data);
9f2cb71c 1236 efx_handle_tx_flush_done(efx, event);
cd2d5b52 1237 efx_sriov_tx_flush_done(efx, event);
8e730c15
BH		 1238 break;
1239 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
62776d03
BH		 1240 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
1241 channel->channel, ev_sub_data);
9f2cb71c 1242 efx_handle_rx_flush_done(efx, event);
cd2d5b52 1243 efx_sriov_rx_flush_done(efx, event);
8e730c15
BH		 1244 break;
1245 case FSE_AZ_EVQ_INIT_DONE_EV:
62776d03
BH		 1246 netif_dbg(efx, hw, efx->net_dev,
1247 "channel %d EVQ %d initialised\n",
1248 channel->channel, ev_sub_data);
8e730c15
BH		 1249 break;
1250 case FSE_AZ_SRM_UPD_DONE_EV:
62776d03
BH		 1251 netif_vdbg(efx, hw, efx->net_dev,
1252 "channel %d SRAM update done\n", channel->channel);
8e730c15
BH		 1253 break;
1254 case FSE_AZ_WAKE_UP_EV:
62776d03
BH		 1255 netif_vdbg(efx, hw, efx->net_dev,
1256 "channel %d RXQ %d wakeup event\n",
1257 channel->channel, ev_sub_data);
8e730c15
BH		 1258 break;
1259 case FSE_AZ_TIMER_EV:
62776d03
BH		 1260 netif_vdbg(efx, hw, efx->net_dev,
1261 "channel %d RX queue %d timer expired\n",
1262 channel->channel, ev_sub_data);
8e730c15
BH		 1263 break;
1264 case FSE_AA_RX_RECOVER_EV:
62776d03
BH		 1265 netif_err(efx, rx_err, efx->net_dev,
1266 "channel %d seen DRIVER RX_RESET event. "
8e730c15
BH		 1267 "Resetting.\n", channel->channel);
1268 atomic_inc(&efx->rx_reset);
1269 efx_schedule_reset(efx,
1270 EFX_WORKAROUND_6555(efx) ?
1271 RESET_TYPE_RX_RECOVERY :
1272 RESET_TYPE_DISABLE);
1273 break;
1274 case FSE_BZ_RX_DSC_ERROR_EV:
cd2d5b52
BH		 1275 if (ev_sub_data < EFX_VI_BASE) {
1276 netif_err(efx, rx_err, efx->net_dev,
1277 "RX DMA Q %d reports descriptor fetch error."
1278 " RX Q %d is disabled.\n", ev_sub_data,
1279 ev_sub_data);
1280 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1281 } else
1282 efx_sriov_desc_fetch_err(efx, ev_sub_data);
8e730c15
BH		 1283 break;
1284 case FSE_BZ_TX_DSC_ERROR_EV:
cd2d5b52
BH		 1285 if (ev_sub_data < EFX_VI_BASE) {
1286 netif_err(efx, tx_err, efx->net_dev,
1287 "TX DMA Q %d reports descriptor fetch error."
1288 " TX Q %d is disabled.\n", ev_sub_data,
1289 ev_sub_data);
1290 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1291 } else
1292 efx_sriov_desc_fetch_err(efx, ev_sub_data);
8e730c15
BH		 1293 break;
1294 default:
62776d03
BH		 1295 netif_vdbg(efx, hw, efx->net_dev,
1296 "channel %d unknown driver event code %d "
1297 "data %04x\n", channel->channel, ev_sub_code,
1298 ev_sub_data);
8e730c15
BH		 1299 break;
1300 }
1301}
1302
fa236e18 1303int efx_nic_process_eventq(struct efx_channel *channel, int budget)
8e730c15 1304{
ecc910f5 1305 struct efx_nic *efx = channel->efx;
8e730c15
BH		 1306 unsigned int read_ptr;
1307 efx_qword_t event, *p_event;
1308 int ev_code;
fa236e18
BH		 1309 int tx_packets = 0;
1310 int spent = 0;
8e730c15
BH		 1311
1312 read_ptr = channel->eventq_read_ptr;
1313
fa236e18 1314 for (;;) {
8e730c15
BH		 1315 p_event = efx_event(channel, read_ptr);
1316 event = *p_event;
1317
1318 if (!efx_event_present(&event))
1319 /* End of events */
1320 break;
1321
62776d03
BH		 1322 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1323 "channel %d event is "EFX_QWORD_FMT"\n",
1324 channel->channel, EFX_QWORD_VAL(event));
8e730c15
BH		 1325
1326 /* Clear this event by marking it all ones */
1327 EFX_SET_QWORD(*p_event);
1328
d4fabcc8 1329 ++read_ptr;
fa236e18 1330
8e730c15
BH		 1331 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1332
1333 switch (ev_code) {
1334 case FSE_AZ_EV_CODE_RX_EV:
1335 efx_handle_rx_event(channel, &event);
fa236e18
BH		 1336 if (++spent == budget)
1337 goto out;
8e730c15
BH		 1338 break;
1339 case FSE_AZ_EV_CODE_TX_EV:
fa236e18 1340 tx_packets += efx_handle_tx_event(channel, &event);
ecc910f5 1341 if (tx_packets > efx->txq_entries) {
fa236e18
BH		 1342 spent = budget;
1343 goto out;
1344 }
8e730c15
BH		 1345 break;
1346 case FSE_AZ_EV_CODE_DRV_GEN_EV:
90d683af 1347 efx_handle_generated_event(channel, &event);
8e730c15 1348 break;
8e730c15
BH		 1349 case FSE_AZ_EV_CODE_DRIVER_EV:
1350 efx_handle_driver_event(channel, &event);
1351 break;
cd2d5b52
BH		 1352 case FSE_CZ_EV_CODE_USER_EV:
1353 efx_sriov_event(channel, &event);
1354 break;
8880f4ec
BH		 1355 case FSE_CZ_EV_CODE_MCDI_EV:
1356 efx_mcdi_process_event(channel, &event);
1357 break;
40641ed9
BH		 1358 case FSE_AZ_EV_CODE_GLOBAL_EV:
1359 if (efx->type->handle_global_event &&
1360 efx->type->handle_global_event(channel, &event))
1361 break;
1362 /* else fall through */
8e730c15 1363 default:
62776d03
BH		 1364 netif_err(channel->efx, hw, channel->efx->net_dev,
1365 "channel %d unknown event type %d (data "
1366 EFX_QWORD_FMT ")\n", channel->channel,
1367 ev_code, EFX_QWORD_VAL(event));
8e730c15 1368 }
fa236e18 1369 }
8e730c15 1370
fa236e18 1371out:
8e730c15 1372 channel->eventq_read_ptr = read_ptr;
fa236e18 1373 return spent;
8e730c15
BH		 1374}
1375
d4fabcc8
BH		 1376/* Check whether an event is present in the eventq at the current
1377 * read pointer. Only useful for self-test.
1378 */
1379bool efx_nic_event_present(struct efx_channel *channel)
1380{
1381 return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
1382}
8e730c15
BH		 1383
1384/* Allocate buffer table entries for event queue */
1385int efx_nic_probe_eventq(struct efx_channel *channel)
1386{
1387 struct efx_nic *efx = channel->efx;
ecc910f5
SH		 1388 unsigned entries;
1389
1390 entries = channel->eventq_mask + 1;
8e730c15 1391 return efx_alloc_special_buffer(efx, &channel->eventq,
ecc910f5 1392 entries * sizeof(efx_qword_t));
8e730c15
BH		 1393}
1394
1395void efx_nic_init_eventq(struct efx_channel *channel)
1396{
8880f4ec 1397 efx_oword_t reg;
8e730c15
BH		 1398 struct efx_nic *efx = channel->efx;
1399
62776d03
BH		 1400 netif_dbg(efx, hw, efx->net_dev,
1401 "channel %d event queue in special buffers %d-%d\n",
1402 channel->channel, channel->eventq.index,
1403 channel->eventq.index + channel->eventq.entries - 1);
8e730c15 1404
8880f4ec
BH		 1405 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1406 EFX_POPULATE_OWORD_3(reg,
1407 FRF_CZ_TIMER_Q_EN, 1,
1408 FRF_CZ_HOST_NOTIFY_MODE, 0,
1409 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1410 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1411 }
1412
8e730c15
BH		 1413 /* Pin event queue buffer */
1414 efx_init_special_buffer(efx, &channel->eventq);
1415
1416 /* Fill event queue with all ones (i.e. empty events) */
1417 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1418
1419 /* Push event queue to card */
8880f4ec 1420 EFX_POPULATE_OWORD_3(reg,
8e730c15
BH		 1421 FRF_AZ_EVQ_EN, 1,
1422 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1423 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
8880f4ec 1424 efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
8e730c15
BH		 1425 channel->channel);
1426
1427 efx->type->push_irq_moderation(channel);
1428}
1429
1430void efx_nic_fini_eventq(struct efx_channel *channel)
1431{
8880f4ec 1432 efx_oword_t reg;
8e730c15
BH		 1433 struct efx_nic *efx = channel->efx;
1434
1435 /* Remove event queue from card */
8880f4ec
BH		 1436 EFX_ZERO_OWORD(reg);
1437 efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
8e730c15 1438 channel->channel);
8880f4ec
BH		 1439 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1440 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
8e730c15
BH		 1441
1442 /* Unpin event queue */
1443 efx_fini_special_buffer(efx, &channel->eventq);
1444}
1445
1446/* Free buffers backing event queue */
1447void efx_nic_remove_eventq(struct efx_channel *channel)
1448{
1449 efx_free_special_buffer(channel->efx, &channel->eventq);
1450}
1451
1452
eee6f6a9 1453void efx_nic_event_test_start(struct efx_channel *channel)
8e730c15 1454{
dd40781e 1455 channel->event_test_cpu = -1;
eee6f6a9 1456 smp_wmb();
4ef594eb 1457 efx_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel));
90d683af
SH		 1458}
1459
2ae75dac 1460void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
90d683af 1461{
2ae75dac
BH		 1462 efx_magic_event(efx_rx_queue_channel(rx_queue),
1463 EFX_CHANNEL_MAGIC_FILL(rx_queue));
8e730c15
BH		 1464}
1465
8e730c15
BH		 1466/**************************************************************************
1467 *
1468 * Hardware interrupts
1469 * The hardware interrupt handler does very little work; all the event
1470 * queue processing is carried out by per-channel tasklets.
1471 *
1472 **************************************************************************/
1473
1474/* Enable/disable/generate interrupts */
1475static inline void efx_nic_interrupts(struct efx_nic *efx,
1476 bool enabled, bool force)
1477{
1478 efx_oword_t int_en_reg_ker;
8880f4ec
BH		 1479
1480 EFX_POPULATE_OWORD_3(int_en_reg_ker,
1646a6f3 1481 FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level,
8e730c15
BH		 1482 FRF_AZ_KER_INT_KER, force,
1483 FRF_AZ_DRV_INT_EN_KER, enabled);
1484 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1485}
1486
1487void efx_nic_enable_interrupts(struct efx_nic *efx)
1488{
8e730c15
BH		 1489 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1490 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1491
8e730c15 1492 efx_nic_interrupts(efx, true, false);
8e730c15
BH		 1493}
1494
1495void efx_nic_disable_interrupts(struct efx_nic *efx)
1496{
1497 /* Disable interrupts */
1498 efx_nic_interrupts(efx, false, false);
1499}
1500
1501/* Generate a test interrupt
1502 * Interrupt must already have been enabled, otherwise nasty things
1503 * may happen.
1504 */
eee6f6a9 1505void efx_nic_irq_test_start(struct efx_nic *efx)
8e730c15 1506{
eee6f6a9
BH		 1507 efx->last_irq_cpu = -1;
1508 smp_wmb();
8e730c15
BH		 1509 efx_nic_interrupts(efx, true, true);
1510}
1511
1512/* Process a fatal interrupt
1513 * Disable bus mastering ASAP and schedule a reset
1514 */
1515irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx)
1516{
1517 struct falcon_nic_data *nic_data = efx->nic_data;
1518 efx_oword_t *int_ker = efx->irq_status.addr;
1519 efx_oword_t fatal_intr;
1520 int error, mem_perr;
1521
1522 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1523 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1524
62776d03
BH		 1525 netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1526 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1527 EFX_OWORD_VAL(fatal_intr),
1528 error ? "disabling bus mastering" : "no recognised error");
8e730c15
BH		 1529
1530 /* If this is a memory parity error dump which blocks are offending */
97e1eaa0
SH		 1531 mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1532 EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
8e730c15
BH		 1533 if (mem_perr) {
1534 efx_oword_t reg;
1535 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
62776d03
BH		 1536 netif_err(efx, hw, efx->net_dev,
1537 "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1538 EFX_OWORD_VAL(reg));
8e730c15
BH		 1539 }
1540
1541 /* Disable both devices */
1542 pci_clear_master(efx->pci_dev);
1543 if (efx_nic_is_dual_func(efx))
1544 pci_clear_master(nic_data->pci_dev2);
1545 efx_nic_disable_interrupts(efx);
1546
1547 /* Count errors and reset or disable the NIC accordingly */
1548 if (efx->int_error_count == 0 ||
1549 time_after(jiffies, efx->int_error_expire)) {
1550 efx->int_error_count = 0;
1551 efx->int_error_expire =
1552 jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1553 }
1554 if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
62776d03
BH		 1555 netif_err(efx, hw, efx->net_dev,
1556 "SYSTEM ERROR - reset scheduled\n");
8e730c15
BH		 1557 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1558 } else {
62776d03
BH		 1559 netif_err(efx, hw, efx->net_dev,
1560 "SYSTEM ERROR - max number of errors seen."
1561 "NIC will be disabled\n");
8e730c15
BH		 1562 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1563 }
63695459 1564
8e730c15
BH		 1565 return IRQ_HANDLED;
1566}
1567
1568/* Handle a legacy interrupt
1569 * Acknowledges the interrupt and schedule event queue processing.
1570 */
1571static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id)
1572{
1573 struct efx_nic *efx = dev_id;
1574 efx_oword_t *int_ker = efx->irq_status.addr;
1575 irqreturn_t result = IRQ_NONE;
1576 struct efx_channel *channel;
1577 efx_dword_t reg;
1578 u32 queues;
1579 int syserr;
1580
94dec6a2
BH		 1581 /* Could this be ours? If interrupts are disabled then the
1582 * channel state may not be valid.
1583 */
1584 if (!efx->legacy_irq_enabled)
1585 return result;
1586
8e730c15
BH		 1587 /* Read the ISR which also ACKs the interrupts */
1588 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1589 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1590
b28405b0
AR		 1591 /* Legacy interrupts are disabled too late by the EEH kernel
1592 * code. Disable them earlier.
1593 * If an EEH error occurred, the read will have returned all ones.
1594 */
1595 if (EFX_DWORD_IS_ALL_ONES(reg) && efx_try_recovery(efx) &&
1596 !efx->eeh_disabled_legacy_irq) {
1597 disable_irq_nosync(efx->legacy_irq);
1598 efx->eeh_disabled_legacy_irq = true;
1599 }
1600
1646a6f3
BH		 1601 /* Handle non-event-queue sources */
1602 if (queues & (1U << efx->irq_level)) {
63695459
SH		 1603 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1604 if (unlikely(syserr))
1605 return efx_nic_fatal_interrupt(efx);
1646a6f3 1606 efx->last_irq_cpu = raw_smp_processor_id();
63695459 1607 }
8e730c15 1608
8880f4ec
BH		 1609 if (queues != 0) {
1610 if (EFX_WORKAROUND_15783(efx))
1611 efx->irq_zero_count = 0;
1612
1613 /* Schedule processing of any interrupting queues */
1614 efx_for_each_channel(channel, efx) {
1615 if (queues & 1)
1646a6f3 1616 efx_schedule_channel_irq(channel);
8880f4ec 1617 queues >>= 1;
8e730c15 1618 }
8880f4ec
BH		 1619 result = IRQ_HANDLED;
1620
41b7e4c3 1621 } else if (EFX_WORKAROUND_15783(efx)) {
8880f4ec
BH		 1622 efx_qword_t *event;
1623
41b7e4c3
SH		 1624 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1625 * because this might be a shared interrupt. */
1626 if (efx->irq_zero_count++ == 0)
1627 result = IRQ_HANDLED;
1628
1629 /* Ensure we schedule or rearm all event queues */
8880f4ec
BH		 1630 efx_for_each_channel(channel, efx) {
1631 event = efx_event(channel, channel->eventq_read_ptr);
1632 if (efx_event_present(event))
1646a6f3 1633 efx_schedule_channel_irq(channel);
41b7e4c3
SH		 1634 else
1635 efx_nic_eventq_read_ack(channel);
8880f4ec 1636 }
8e730c15
BH		 1637 }
1638
1646a6f3 1639 if (result == IRQ_HANDLED)
62776d03
BH		 1640 netif_vdbg(efx, intr, efx->net_dev,
1641 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1642 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
8e730c15
BH		 1643
1644 return result;
1645}
1646
1647/* Handle an MSI interrupt
1648 *
1649 * Handle an MSI hardware interrupt. This routine schedules event
1650 * queue processing. No interrupt acknowledgement cycle is necessary.
1651 * Also, we never need to check that the interrupt is for us, since
1652 * MSI interrupts cannot be shared.
1653 */
1654static irqreturn_t efx_msi_interrupt(int irq, void *dev_id)
1655{
4642610c 1656 struct efx_channel *channel = *(struct efx_channel **)dev_id;
8e730c15
BH		 1657 struct efx_nic *efx = channel->efx;
1658 efx_oword_t *int_ker = efx->irq_status.addr;
1659 int syserr;
1660
62776d03
BH		 1661 netif_vdbg(efx, intr, efx->net_dev,
1662 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1663 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
8e730c15 1664
1646a6f3
BH		 1665 /* Handle non-event-queue sources */
1666 if (channel->channel == efx->irq_level) {
63695459
SH		 1667 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1668 if (unlikely(syserr))
1669 return efx_nic_fatal_interrupt(efx);
1646a6f3 1670 efx->last_irq_cpu = raw_smp_processor_id();
63695459 1671 }
8e730c15
BH		 1672
1673 /* Schedule processing of the channel */
1646a6f3 1674 efx_schedule_channel_irq(channel);
8e730c15
BH		 1675
1676 return IRQ_HANDLED;
1677}
1678
1679
1680/* Setup RSS indirection table.
1681 * This maps from the hash value of the packet to RXQ
1682 */
765c9f46 1683void efx_nic_push_rx_indir_table(struct efx_nic *efx)
8e730c15 1684{
765c9f46 1685 size_t i = 0;
8e730c15
BH		 1686 efx_dword_t dword;
1687
1688 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1689 return;
1690
765c9f46
BH		 1691 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1692 FR_BZ_RX_INDIRECTION_TBL_ROWS);
1693
1694 for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
8e730c15 1695 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
765c9f46 1696 efx->rx_indir_table[i]);
778cdaf6
BH		 1697 efx_writed(efx, &dword,
1698 FR_BZ_RX_INDIRECTION_TBL +
1699 FR_BZ_RX_INDIRECTION_TBL_STEP * i);
8e730c15
BH		 1700 }
1701}
1702
1703/* Hook interrupt handler(s)
1704 * Try MSI and then legacy interrupts.
1705 */
1706int efx_nic_init_interrupt(struct efx_nic *efx)
1707{
1708 struct efx_channel *channel;
1709 int rc;
1710
1711 if (!EFX_INT_MODE_USE_MSI(efx)) {
1712 irq_handler_t handler;
1713 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1714 handler = efx_legacy_interrupt;
1715 else
1716 handler = falcon_legacy_interrupt_a1;
1717
1718 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1719 efx->name, efx);
1720 if (rc) {
62776d03
BH		 1721 netif_err(efx, drv, efx->net_dev,
1722 "failed to hook legacy IRQ %d\n",
1723 efx->pci_dev->irq);
8e730c15
BH		 1724 goto fail1;
1725 }
1726 return 0;
1727 }
1728
1729 /* Hook MSI or MSI-X interrupt */
1730 efx_for_each_channel(channel, efx) {
1731 rc = request_irq(channel->irq, efx_msi_interrupt,
1732 IRQF_PROBE_SHARED, /* Not shared */
4642610c
BH		 1733 efx->channel_name[channel->channel],
1734 &efx->channel[channel->channel]);
8e730c15 1735 if (rc) {
62776d03
BH		 1736 netif_err(efx, drv, efx->net_dev,
1737 "failed to hook IRQ %d\n", channel->irq);
8e730c15
BH		 1738 goto fail2;
1739 }
1740 }
1741
1742 return 0;
1743
1744 fail2:
1745 efx_for_each_channel(channel, efx)
4642610c 1746 free_irq(channel->irq, &efx->channel[channel->channel]);
8e730c15
BH		 1747 fail1:
1748 return rc;
1749}
1750
1751void efx_nic_fini_interrupt(struct efx_nic *efx)
1752{
1753 struct efx_channel *channel;
1754 efx_oword_t reg;
1755
1756 /* Disable MSI/MSI-X interrupts */
1757 efx_for_each_channel(channel, efx) {
1758 if (channel->irq)
4642610c 1759 free_irq(channel->irq, &efx->channel[channel->channel]);
8e730c15
BH		 1760 }
1761
1762 /* ACK legacy interrupt */
1763 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1764 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1765 else
1766 falcon_irq_ack_a1(efx);
1767
1768 /* Disable legacy interrupt */
1769 if (efx->legacy_irq)
1770 free_irq(efx->legacy_irq, efx);
1771}
1772
cd2d5b52
BH		 1773/* Looks at available SRAM resources and works out how many queues we
1774 * can support, and where things like descriptor caches should live.
1775 *
1776 * SRAM is split up as follows:
1777 * 0 buftbl entries for channels
1778 * efx->vf_buftbl_base buftbl entries for SR-IOV
1779 * efx->rx_dc_base RX descriptor caches
1780 * efx->tx_dc_base TX descriptor caches
1781 */
28e47c49
BH		 1782void efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
1783{
1784 unsigned vi_count, buftbl_min;
1785
1786 /* Account for the buffer table entries backing the datapath channels
1787 * and the descriptor caches for those channels.
1788 */
1789 buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
1790 efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
1791 efx->n_channels * EFX_MAX_EVQ_SIZE)
1792 * sizeof(efx_qword_t) / EFX_BUF_SIZE);
1793 vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1794
cd2d5b52
BH		 1795#ifdef CONFIG_SFC_SRIOV
1796 if (efx_sriov_wanted(efx)) {
1797 unsigned vi_dc_entries, buftbl_free, entries_per_vf, vf_limit;
1798
1799 efx->vf_buftbl_base = buftbl_min;
1800
1801 vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES;
1802 vi_count = max(vi_count, EFX_VI_BASE);
1803 buftbl_free = (sram_lim_qw - buftbl_min -
1804 vi_count * vi_dc_entries);
1805
1806 entries_per_vf = ((vi_dc_entries + EFX_VF_BUFTBL_PER_VI) *
1807 efx_vf_size(efx));
1808 vf_limit = min(buftbl_free / entries_per_vf,
1809 (1024U - EFX_VI_BASE) >> efx->vi_scale);
1810
1811 if (efx->vf_count > vf_limit) {
1812 netif_err(efx, probe, efx->net_dev,
1813 "Reducing VF count from from %d to %d\n",
1814 efx->vf_count, vf_limit);
1815 efx->vf_count = vf_limit;
1816 }
1817 vi_count += efx->vf_count * efx_vf_size(efx);
1818 }
1819#endif
1820
28e47c49
BH		 1821 efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
1822 efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
1823}
1824
8e730c15
BH		 1825u32 efx_nic_fpga_ver(struct efx_nic *efx)
1826{
1827 efx_oword_t altera_build;
1828 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1829 return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1830}
1831
1832void efx_nic_init_common(struct efx_nic *efx)
1833{
1834 efx_oword_t temp;
1835
1836 /* Set positions of descriptor caches in SRAM. */
28e47c49 1837 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
8e730c15 1838 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
28e47c49 1839 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
8e730c15
BH		 1840 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1841
1842 /* Set TX descriptor cache size. */
1843 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1844 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1845 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1846
1847 /* Set RX descriptor cache size. Set low watermark to size-8, as
1848 * this allows most efficient prefetching.
1849 */
1850 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1851 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1852 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1853 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1854 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1855
1856 /* Program INT_KER address */
1857 EFX_POPULATE_OWORD_2(temp,
1858 FRF_AZ_NORM_INT_VEC_DIS_KER,
1859 EFX_INT_MODE_USE_MSI(efx),
1860 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1861 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1862
63695459
SH		 1863 if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1864 /* Use an interrupt level unused by event queues */
1646a6f3 1865 efx->irq_level = 0x1f;
63695459
SH		 1866 else
1867 /* Use a valid MSI-X vector */
1646a6f3 1868 efx->irq_level = 0;
63695459 1869
8e730c15
BH		 1870 /* Enable all the genuinely fatal interrupts. (They are still
1871 * masked by the overall interrupt mask, controlled by
1872 * falcon_interrupts()).
1873 *
1874 * Note: All other fatal interrupts are enabled
1875 */
1876 EFX_POPULATE_OWORD_3(temp,
1877 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1878 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1879 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
b17424b0
SH		 1880 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1881 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
8e730c15
BH		 1882 EFX_INVERT_OWORD(temp);
1883 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1884
765c9f46 1885 efx_nic_push_rx_indir_table(efx);
8e730c15
BH		 1886
1887 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1888 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1889 */
1890 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1891 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1892 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1893 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
cd38557d 1894 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
8e730c15
BH		 1895 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1896 /* Enable SW_EV to inherit in char driver - assume harmless here */
1897 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1898 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1899 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
286d47ba
BH		 1900 /* Disable hardware watchdog which can misfire */
1901 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
8e730c15
BH		 1902 /* Squash TX of packets of 16 bytes or less */
1903 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1904 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1905 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
94b274bf
BH		 1906
1907 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1908 EFX_POPULATE_OWORD_4(temp,
1909 /* Default values */
1910 FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1911 FRF_BZ_TX_PACE_SB_AF, 0xb,
1912 FRF_BZ_TX_PACE_FB_BASE, 0,
1913 /* Allow large pace values in the
1914 * fast bin. */
1915 FRF_BZ_TX_PACE_BIN_TH,
1916 FFE_BZ_TX_PACE_RESERVED);
1917 efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1918 }
8e730c15 1919}
5b98c1bf
BH		 1920
1921/* Register dump */
1922
1923#define REGISTER_REVISION_A 1
1924#define REGISTER_REVISION_B 2
1925#define REGISTER_REVISION_C 3
1926#define REGISTER_REVISION_Z 3 /* latest revision */
1927
1928struct efx_nic_reg {
1929 u32 offset:24;
1930 u32 min_revision:2, max_revision:2;
1931};
1932
1933#define REGISTER(name, min_rev, max_rev) { \
1934 FR_ ## min_rev ## max_rev ## _ ## name, \
1935 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \
1936}
1937#define REGISTER_AA(name) REGISTER(name, A, A)
1938#define REGISTER_AB(name) REGISTER(name, A, B)
1939#define REGISTER_AZ(name) REGISTER(name, A, Z)
1940#define REGISTER_BB(name) REGISTER(name, B, B)
1941#define REGISTER_BZ(name) REGISTER(name, B, Z)
1942#define REGISTER_CZ(name) REGISTER(name, C, Z)
1943
1944static const struct efx_nic_reg efx_nic_regs[] = {
1945 REGISTER_AZ(ADR_REGION),
1946 REGISTER_AZ(INT_EN_KER),
1947 REGISTER_BZ(INT_EN_CHAR),
1948 REGISTER_AZ(INT_ADR_KER),
1949 REGISTER_BZ(INT_ADR_CHAR),
1950 /* INT_ACK_KER is WO */
1951 /* INT_ISR0 is RC */
1952 REGISTER_AZ(HW_INIT),
1953 REGISTER_CZ(USR_EV_CFG),
1954 REGISTER_AB(EE_SPI_HCMD),
1955 REGISTER_AB(EE_SPI_HADR),
1956 REGISTER_AB(EE_SPI_HDATA),
1957 REGISTER_AB(EE_BASE_PAGE),
1958 REGISTER_AB(EE_VPD_CFG0),
1959 /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
1960 /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
1961 /* PCIE_CORE_INDIRECT is indirect */
1962 REGISTER_AB(NIC_STAT),
1963 REGISTER_AB(GPIO_CTL),
1964 REGISTER_AB(GLB_CTL),
1965 /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
1966 REGISTER_BZ(DP_CTRL),
1967 REGISTER_AZ(MEM_STAT),
1968 REGISTER_AZ(CS_DEBUG),
1969 REGISTER_AZ(ALTERA_BUILD),
1970 REGISTER_AZ(CSR_SPARE),
1971 REGISTER_AB(PCIE_SD_CTL0123),
1972 REGISTER_AB(PCIE_SD_CTL45),
1973 REGISTER_AB(PCIE_PCS_CTL_STAT),
1974 /* DEBUG_DATA_OUT is not used */
1975 /* DRV_EV is WO */
1976 REGISTER_AZ(EVQ_CTL),
1977 REGISTER_AZ(EVQ_CNT1),
1978 REGISTER_AZ(EVQ_CNT2),
1979 REGISTER_AZ(BUF_TBL_CFG),
1980 REGISTER_AZ(SRM_RX_DC_CFG),
1981 REGISTER_AZ(SRM_TX_DC_CFG),
1982 REGISTER_AZ(SRM_CFG),
1983 /* BUF_TBL_UPD is WO */
1984 REGISTER_AZ(SRM_UPD_EVQ),
1985 REGISTER_AZ(SRAM_PARITY),
1986 REGISTER_AZ(RX_CFG),
1987 REGISTER_BZ(RX_FILTER_CTL),
1988 /* RX_FLUSH_DESCQ is WO */
1989 REGISTER_AZ(RX_DC_CFG),
1990 REGISTER_AZ(RX_DC_PF_WM),
1991 REGISTER_BZ(RX_RSS_TKEY),
1992 /* RX_NODESC_DROP is RC */
1993 REGISTER_AA(RX_SELF_RST),
1994 /* RX_DEBUG, RX_PUSH_DROP are not used */
1995 REGISTER_CZ(RX_RSS_IPV6_REG1),
1996 REGISTER_CZ(RX_RSS_IPV6_REG2),
1997 REGISTER_CZ(RX_RSS_IPV6_REG3),
1998 /* TX_FLUSH_DESCQ is WO */
1999 REGISTER_AZ(TX_DC_CFG),
2000 REGISTER_AA(TX_CHKSM_CFG),
2001 REGISTER_AZ(TX_CFG),
2002 /* TX_PUSH_DROP is not used */
2003 REGISTER_AZ(TX_RESERVED),
2004 REGISTER_BZ(TX_PACE),
2005 /* TX_PACE_DROP_QID is RC */
2006 REGISTER_BB(TX_VLAN),
2007 REGISTER_BZ(TX_IPFIL_PORTEN),
2008 REGISTER_AB(MD_TXD),
2009 REGISTER_AB(MD_RXD),
2010 REGISTER_AB(MD_CS),
2011 REGISTER_AB(MD_PHY_ADR),
2012 REGISTER_AB(MD_ID),
2013 /* MD_STAT is RC */
2014 REGISTER_AB(MAC_STAT_DMA),
2015 REGISTER_AB(MAC_CTRL),
2016 REGISTER_BB(GEN_MODE),
2017 REGISTER_AB(MAC_MC_HASH_REG0),
2018 REGISTER_AB(MAC_MC_HASH_REG1),
2019 REGISTER_AB(GM_CFG1),
2020 REGISTER_AB(GM_CFG2),
2021 /* GM_IPG and GM_HD are not used */
2022 REGISTER_AB(GM_MAX_FLEN),
2023 /* GM_TEST is not used */
2024 REGISTER_AB(GM_ADR1),
2025 REGISTER_AB(GM_ADR2),
2026 REGISTER_AB(GMF_CFG0),
2027 REGISTER_AB(GMF_CFG1),
2028 REGISTER_AB(GMF_CFG2),
2029 REGISTER_AB(GMF_CFG3),
2030 REGISTER_AB(GMF_CFG4),
2031 REGISTER_AB(GMF_CFG5),
2032 REGISTER_BB(TX_SRC_MAC_CTL),
2033 REGISTER_AB(XM_ADR_LO),
2034 REGISTER_AB(XM_ADR_HI),
2035 REGISTER_AB(XM_GLB_CFG),
2036 REGISTER_AB(XM_TX_CFG),
2037 REGISTER_AB(XM_RX_CFG),
2038 REGISTER_AB(XM_MGT_INT_MASK),
2039 REGISTER_AB(XM_FC),
2040 REGISTER_AB(XM_PAUSE_TIME),
2041 REGISTER_AB(XM_TX_PARAM),
2042 REGISTER_AB(XM_RX_PARAM),
2043 /* XM_MGT_INT_MSK (note no 'A') is RC */
2044 REGISTER_AB(XX_PWR_RST),
2045 REGISTER_AB(XX_SD_CTL),
2046 REGISTER_AB(XX_TXDRV_CTL),
2047 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
2048 /* XX_CORE_STAT is partly RC */
2049};
2050
2051struct efx_nic_reg_table {
2052 u32 offset:24;
2053 u32 min_revision:2, max_revision:2;
2054 u32 step:6, rows:21;
2055};
2056
2057#define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \
2058 offset, \
2059 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \
2060 step, rows \
2061}
9c636baf 2062#define REGISTER_TABLE(name, min_rev, max_rev) \
5b98c1bf
BH		 2063 REGISTER_TABLE_DIMENSIONS( \
2064 name, FR_ ## min_rev ## max_rev ## _ ## name, \
2065 min_rev, max_rev, \
2066 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
2067 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
2068#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A)
2069#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z)
2070#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B)
2071#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z)
2072#define REGISTER_TABLE_BB_CZ(name) \
2073 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \
2074 FR_BZ_ ## name ## _STEP, \
2075 FR_BB_ ## name ## _ROWS), \
2076 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \
2077 FR_BZ_ ## name ## _STEP, \
2078 FR_CZ_ ## name ## _ROWS)
2079#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z)
2080
2081static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
2082 /* DRIVER is not used */
2083 /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
2084 REGISTER_TABLE_BB(TX_IPFIL_TBL),
2085 REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
2086 REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
2087 REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
2088 REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
2089 REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
2090 REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
2091 REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
75abc51c 2092 /* We can't reasonably read all of the buffer table (up to 8MB!).
5b98c1bf
BH		 2093 * However this driver will only use a few entries. Reading
2094 * 1K entries allows for some expansion of queue count and
2095 * size before we need to change the version. */
2096 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
2097 A, A, 8, 1024),
2098 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
2099 B, Z, 8, 1024),
5b98c1bf
BH		 2100 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
2101 REGISTER_TABLE_BB_CZ(TIMER_TBL),
2102 REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
2103 REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
2104 /* TX_FILTER_TBL0 is huge and not used by this driver */
2105 REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
2106 REGISTER_TABLE_CZ(MC_TREG_SMEM),
2107 /* MSIX_PBA_TABLE is not mapped */
2108 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
75abc51c 2109 REGISTER_TABLE_BZ(RX_FILTER_TBL0),
5b98c1bf
BH		 2110};
2111
2112size_t efx_nic_get_regs_len(struct efx_nic *efx)
2113{
2114 const struct efx_nic_reg *reg;
2115 const struct efx_nic_reg_table *table;
2116 size_t len = 0;
2117
2118 for (reg = efx_nic_regs;
2119 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
2120 reg++)
2121 if (efx->type->revision >= reg->min_revision &&
2122 efx->type->revision <= reg->max_revision)
2123 len += sizeof(efx_oword_t);
2124
2125 for (table = efx_nic_reg_tables;
2126 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
2127 table++)
2128 if (efx->type->revision >= table->min_revision &&
2129 efx->type->revision <= table->max_revision)
2130 len += table->rows * min_t(size_t, table->step, 16);
2131
2132 return len;
2133}
2134
2135void efx_nic_get_regs(struct efx_nic *efx, void *buf)
2136{
2137 const struct efx_nic_reg *reg;
2138 const struct efx_nic_reg_table *table;
2139
2140 for (reg = efx_nic_regs;
2141 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
2142 reg++) {
2143 if (efx->type->revision >= reg->min_revision &&
2144 efx->type->revision <= reg->max_revision) {
2145 efx_reado(efx, (efx_oword_t *)buf, reg->offset);
2146 buf += sizeof(efx_oword_t);
2147 }
2148 }
2149
2150 for (table = efx_nic_reg_tables;
2151 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
2152 table++) {
2153 size_t size, i;
2154
2155 if (!(efx->type->revision >= table->min_revision &&
2156 efx->type->revision <= table->max_revision))
2157 continue;
2158
2159 size = min_t(size_t, table->step, 16);
2160
2161 for (i = 0; i < table->rows; i++) {
2162 switch (table->step) {
778cdaf6
BH		 2163 case 4: /* 32-bit SRAM */
2164 efx_readd(efx, buf, table->offset + 4 * i);
5b98c1bf
BH		 2165 break;
2166 case 8: /* 64-bit SRAM */
2167 efx_sram_readq(efx,
2168 efx->membase + table->offset,
2169 buf, i);
2170 break;
778cdaf6 2171 case 16: /* 128-bit-readable register */
5b98c1bf
BH		 2172 efx_reado_table(efx, buf, table->offset, i);
2173 break;
2174 case 32: /* 128-bit register, interleaved */
2175 efx_reado_table(efx, buf, table->offset, 2 * i);
2176 break;
2177 default:
2178 WARN_ON(1);
2179 return;
2180 }
2181 buf += size;
2182 }
2183 }
2184}
Linux kernel - Deliverables
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